1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2001,
3 ;; 2002, 2003, 2004, 2005, 2006, 2007
4 ;; Free Software Foundation, Inc.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;;- Information about MCF5200 port.
24 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
25 ;;- 68k ISA. Differences include reduced support for byte and word
26 ;;- operands and the removal of BCD, bitfield, rotate, and integer
27 ;;- divide instructions. The TARGET_COLDFIRE flag turns the use of the
28 ;;- removed opcodes and addressing modes off.
32 ;;- instruction definitions
34 ;;- @@The original PO technology requires these to be ordered by speed,
35 ;;- @@ so that assigner will pick the fastest.
37 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
39 ;;- When naming insn's (operand 0 of define_insn) be careful about using
40 ;;- names from other targets machine descriptions.
42 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
43 ;;- updates for most instructions.
45 ;;- Operand classes for the register allocator:
46 ;;- 'a' one of the address registers can be used.
47 ;;- 'd' one of the data registers can be used.
48 ;;- 'f' one of the m68881/fpu registers can be used
49 ;;- 'r' either a data or an address register can be used.
51 ;;- Immediate Floating point operator constraints
52 ;;- 'G' a floating point constant that is *NOT* one of the standard
53 ;; 68881 constant values (to force calling output_move_const_double
54 ;; to get it from rom if it is a 68881 constant).
56 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
59 ;;- Immediate integer operand constraints:
61 ;;- 'J' -32768 .. 32767
62 ;;- 'K' all integers EXCEPT -128 .. 127
64 ;;- 'M' all integers EXCEPT -256 .. 255
70 ;;- "%." size separator ("." or "") move%.l d0,d1
71 ;;- "%-" push operand "sp@-" move%.l d0,%-
72 ;;- "%+" pop operand "sp@+" move%.l d0,%+
73 ;;- "%@" top of stack "sp@" move%.l d0,%@
74 ;;- "%!" fpcr register
75 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
76 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
78 ;;- Information about 68040 port.
80 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
81 ;;- be emulated in software by the OS. It is faster to avoid these
82 ;;- instructions and issue a library call rather than trapping into
83 ;;- the kernel. The affected instructions are fintrz and fscale. The
84 ;;- TUNE_68040 flag turns the use of the opcodes off.
86 ;;- The '040 also implements a set of new floating-point instructions
87 ;;- which specify the rounding precision in the opcode. This finally
88 ;;- permit the 68k series to be truly IEEE compliant, and solves all
89 ;;- issues of excess precision accumulating in the extended registers.
90 ;;- By default, GCC does not use these instructions, since such code will
91 ;;- not run on an '030. To use these instructions, use the -m68040-only
94 ;;- These new instructions aren't directly in the md. They are brought
95 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
98 ;;- Information about 68060 port.
100 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
101 ;;- be emulated in software by the OS. It is faster to avoid these
102 ;;- instructions and issue a library call rather than trapping into
103 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
104 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
105 ;;- fscale. The TUNE_68060 flag turns the use of the opcodes off.
107 ;;- Some of these insn's are composites of several m68000 op codes.
108 ;;- The assembler (or final @@??) insures that the appropriate one is
122 ;; UNSPEC_VOLATILE usage:
125 [(UNSPECV_BLOCKAGE 0)
128 ;; Registers by name.
139 (include "predicates.md")
140 (include "constraints.md")
142 ;; ::::::::::::::::::::
146 ;; ::::::::::::::::::::
149 (define_attr "cpu" "cfv1, cfv2, cfv3, cfv4, unknown"
150 (const (symbol_ref "m68k_sched_cpu")))
153 (define_attr "mac" "no, cf_mac, cf_emac"
154 (const (symbol_ref "m68k_sched_mac")))
156 ;; Instruction type for use in scheduling description.
157 ;; _l and _w suffixes indicate size of the operands of instruction.
158 ;; alu - usual arithmetic or logic instruction.
159 ;; aluq - arithmetic or logic instruction which has a quick immediate (the one
160 ;; that is encoded in the instruction word) for its Y operand.
161 ;; alux - Arithmetic instruction that uses carry bit (e.g., addx and subx).
162 ;; bcc - conditional branch.
163 ;; bitr - bit operation that only updates flags.
164 ;; bitrw - bit operation that updates flags and output operand.
165 ;; bra, bsr, clr, cmp, div, ext - corresponding instruction.
166 ;; falu, fbcc, fcmp, fdiv, fmove, fmul, fneg, fsqrt, ftst - corresponding
168 ;; ib - fake instruction to subscribe slots in ColdFire V1,V2,V3 instruction
170 ;; ignore - fake instruction.
171 ;; jmp, jsr, lea, link, mov3q, move, moveq, mul - corresponding instruction.
172 ;; mvsz - mvs or mvz instruction.
173 ;; neg, nop, pea, rts, scc - corresponding instruction.
174 ;; shift - arithmetic or logical shift instruction.
175 ;; trap, tst, unlk - corresponding instruction.
177 "alu_l,aluq_l,alux_l,bcc,bitr,bitrw,bra,bsr,clr,clr_l,cmp,cmp_l,
179 falu,fbcc,fcmp,fdiv,fmove,fmul,fneg,fsqrt,ftst,
181 jmp,jsr,lea,link,mov3q_l,move,move_l,moveq_l,mul_w,mul_l,mvsz,neg_l,nop,
185 (const_string "unknown"))
187 ;; Index of the X or Y operand in recog_data.operand[].
188 ;; Should be used only within opx_type and opy_type.
189 (define_attr "opx" "" (const_int 0))
190 (define_attr "opy" "" (const_int 1))
192 ;; Type of the Y operand.
193 ;; See m68k.c: enum attr_op_type.
194 (define_attr "opy_type"
195 "none,Rn,FPn,mem1,mem234,mem5,mem6,mem7,imm_q,imm_w,imm_l"
196 (cond [(eq_attr "type" "ext,fbcc,ftst,neg_l,bcc,bra,bsr,clr,clr_l,ib,ignore,
197 jmp,jsr,nop,rts,scc,trap,tst,tst_l,
198 unlk,unknown") (const_string "none")
199 (eq_attr "type" "lea,pea")
200 (symbol_ref "m68k_sched_attr_opy_type (insn, 1)")]
201 (symbol_ref "m68k_sched_attr_opy_type (insn, 0)")))
203 ;; Type of the X operand.
204 ;; See m68k.c: enum attr_op_type.
205 (define_attr "opx_type"
206 "none,Rn,FPn,mem1,mem234,mem5,mem6,mem7,imm_q,imm_w,imm_l"
207 (cond [(eq_attr "type" "ib,ignore,nop,rts,trap,unlk,
208 unknown") (const_string "none")
209 (eq_attr "type" "pea") (const_string "mem1")
210 (eq_attr "type" "jmp,jsr")
211 (symbol_ref "m68k_sched_attr_opx_type (insn, 1)")]
212 (symbol_ref "m68k_sched_attr_opx_type (insn, 0)")))
214 ;; Access to the X operand: none, read, write, read/write, unknown.
215 ;; Access to the Y operand is either none (if opy_type is none)
216 ;; or read otherwise.
217 (define_attr "opx_access" "none, r, w, rw"
218 (cond [(eq_attr "type" "ib,ignore,nop,rts,trap,unlk,
219 unknown") (const_string "none")
220 (eq_attr "type" "bcc,bra,bsr,bitr,cmp,cmp_l,fbcc,fcmp,ftst,
221 jmp,jsr,tst,tst_l") (const_string "r")
222 (eq_attr "type" "clr,clr_l,fneg,fmove,lea,
223 mov3q_l,move,move_l,moveq_l,mvsz,
224 pea,scc") (const_string "w")
225 (eq_attr "type" "alu_l,aluq_l,alux_l,bitrw,div_w,div_l,ext,
226 falu,fdiv,fmul,fsqrt,link,mul_w,mul_l,
227 neg_l,shift") (const_string "rw")]
228 ;; Should never be used.
229 (symbol_ref "(gcc_unreachable (), OPX_ACCESS_NONE)")))
231 ;; Memory accesses of the insn.
232 ;; 00 - no memory references
233 ;; 10 - memory is read
234 ;; i0 - indexed memory is read
235 ;; 01 - memory is written
236 ;; 0i - indexed memory is written
237 ;; 11 - memory is read, memory is written
238 ;; i1 - indexed memory is read, memory is written
239 ;; 1i - memory is read, indexed memory is written
240 (define_attr "op_mem" "00, 10, i0, 01, 0i, 11, i1, 1i"
241 (symbol_ref "m68k_sched_attr_op_mem (insn)"))
243 ;; Instruction size in words.
244 (define_attr "size" "1,2,3"
245 (symbol_ref "m68k_sched_attr_size (insn)"))
248 ;; Mode macros for floating point operations.
249 ;; Valid floating point modes
250 (define_mode_iterator FP [SF DF (XF "TARGET_68881")])
251 ;; Mnemonic infix to round result
252 (define_mode_attr round [(SF "%$") (DF "%&") (XF "")])
253 ;; Mnemonic infix to round result for mul or div instruction
254 (define_mode_attr round_mul [(SF "sgl") (DF "%&") (XF "")])
255 ;; Suffix specifying source operand format
256 (define_mode_attr prec [(SF "s") (DF "d") (XF "x")])
257 ;; Allowable D registers
258 (define_mode_attr dreg [(SF "d") (DF "") (XF "")])
259 ;; Allowable 68881 constant constraints
260 (define_mode_attr const [(SF "F") (DF "G") (XF "")])
263 (define_insn_and_split "*movdf_internal"
264 [(set (match_operand:DF 0 "push_operand" "=m, m")
265 (match_operand:DF 1 "general_operand" "f, ro<>E"))]
270 "&& reload_completed && (extract_constrain_insn_cached (insn), which_alternative == 1)"
273 m68k_emit_move_double (operands);
276 [(set_attr "type" "fmove,*")])
278 (define_insn_and_split "pushdi"
279 [(set (match_operand:DI 0 "push_operand" "=m")
280 (match_operand:DI 1 "general_operand" "ro<>Fi"))]
283 "&& reload_completed"
286 m68k_emit_move_double (operands);
290 ;; We don't want to allow a constant operand for test insns because
291 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
292 ;; be folded while optimizing anyway.
294 (define_expand "tstdi"
295 [(parallel [(set (cc0)
296 (match_operand:DI 0 "nonimmediate_operand" ""))
297 (clobber (match_scratch:SI 1 ""))
298 (clobber (match_scratch:DI 2 ""))])]
300 "m68k_last_compare_had_fp_operands = 0;")
304 (match_operand:DI 0 "nonimmediate_operand" "am,d"))
305 (clobber (match_scratch:SI 1 "=X,d"))
306 (clobber (match_scratch:DI 2 "=d,X"))]
309 if (which_alternative == 0)
313 xoperands[0] = operands[2];
314 xoperands[1] = operands[0];
315 output_move_double (xoperands);
316 cc_status.flags |= CC_REVERSED; /*|*/
317 return "neg%.l %R2\;negx%.l %2";
319 if (find_reg_note (insn, REG_DEAD, operands[0]))
321 cc_status.flags |= CC_REVERSED; /*|*/
322 return "neg%.l %R0\;negx%.l %0";
326 'sub' clears %1, and also clears the X cc bit
327 'tst' sets the Z cc bit according to the low part of the DImode operand
328 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part.
330 return "sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0";
333 (define_expand "tstsi"
335 (match_operand:SI 0 "nonimmediate_operand" ""))]
337 "m68k_last_compare_had_fp_operands = 0;")
339 ;; If you think that the 68020 does not support tstl a0,
340 ;; reread page B-167 of the 68020 manual more carefully.
341 (define_insn "*tstsi_internal_68020_cf"
343 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
344 "TARGET_68020 || TARGET_COLDFIRE"
346 [(set_attr "type" "tst_l")])
348 ;; On an address reg, cmpw may replace cmpl.
349 (define_insn "*tstsi_internal"
351 (match_operand:SI 0 "nonimmediate_operand" "dm,r"))]
352 "!(TARGET_68020 || TARGET_COLDFIRE)"
356 [(set_attr "type" "tst_l,cmp")])
358 ;; This can't use an address register, because comparisons
359 ;; with address registers as second operand always test the whole word.
360 (define_expand "tsthi"
362 (match_operand:HI 0 "nonimmediate_operand" ""))]
364 "m68k_last_compare_had_fp_operands = 0;")
366 (define_insn "*tsthi_internal"
368 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
371 [(set_attr "type" "tst")])
373 (define_expand "tstqi"
375 (match_operand:QI 0 "nonimmediate_operand" ""))]
377 "m68k_last_compare_had_fp_operands = 0;")
379 (define_insn "*tstqi_internal"
381 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
384 [(set_attr "type" "tst")])
386 (define_expand "tst<mode>"
388 (match_operand:FP 0 "general_operand" ""))]
391 m68k_last_compare_had_fp_operands = 1;
394 (define_insn "tst<mode>_68881"
396 (match_operand:FP 0 "general_operand" "f<FP:dreg>m"))]
399 cc_status.flags = CC_IN_68881;
400 if (FP_REG_P (operands[0]))
402 return "ftst%.<FP:prec> %0";
404 [(set_attr "type" "ftst")])
406 (define_insn "tst<mode>_cf"
408 (match_operand:FP 0 "general_operand" "f<FP:dreg><Q>U"))]
409 "TARGET_COLDFIRE_FPU"
411 cc_status.flags = CC_IN_68881;
412 if (FP_REG_P (operands[0]))
414 return "ftst%.<FP:prec> %0";
416 [(set_attr "type" "ftst")])
419 ;; compare instructions.
421 (define_expand "cmpdi"
424 (compare (match_operand:DI 0 "nonimmediate_operand" "")
425 (match_operand:DI 1 "general_operand" "")))
426 (clobber (match_dup 2))])]
428 "m68k_last_compare_had_fp_operands = 0; operands[2] = gen_reg_rtx (DImode);")
432 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
433 (match_operand:DI 2 "general_operand" "d,0")))
434 (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
437 if (rtx_equal_p (operands[0], operands[1]))
438 return "sub%.l %R2,%R0\;subx%.l %2,%0";
441 cc_status.flags |= CC_REVERSED; /*|*/
442 return "sub%.l %R1,%R0\;subx%.l %1,%0";
446 (define_expand "cmpsi"
448 (compare (match_operand:SI 0 "nonimmediate_operand" "")
449 (match_operand:SI 1 "general_operand" "")))]
452 m68k_last_compare_had_fp_operands = 0;
455 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
458 (compare (match_operand:SI 0 "nonimmediate_operand" "rKT,rKs,mSr,mSa,>")
459 (match_operand:SI 1 "general_src_operand" "mSr,mSa,KTr,Ksr,>")))]
462 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
463 return "cmpm%.l %1,%0";
464 if (REG_P (operands[1])
465 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
467 cc_status.flags |= CC_REVERSED; /*|*/
468 return "cmp%.l %d0,%d1";
470 if (ADDRESS_REG_P (operands[0])
471 && GET_CODE (operands[1]) == CONST_INT
472 && INTVAL (operands[1]) < 0x8000
473 && INTVAL (operands[1]) >= -0x8000)
474 return "cmp%.w %1,%0";
475 return "cmp%.l %d1,%d0";
478 (define_insn "*cmpsi_cf"
480 (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
481 (match_operand:SI 1 "general_operand" "r,mrKs")))]
484 if (REG_P (operands[1])
485 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
487 cc_status.flags |= CC_REVERSED; /*|*/
488 return "cmp%.l %d0,%d1";
490 return "cmp%.l %d1,%d0";
492 [(set_attr "type" "cmp_l")])
494 (define_expand "cmphi"
496 (compare (match_operand:HI 0 "nonimmediate_src_operand" "")
497 (match_operand:HI 1 "general_src_operand" "")))]
499 "m68k_last_compare_had_fp_operands = 0;")
503 (compare (match_operand:HI 0 "nonimmediate_src_operand" "rnmS,d,n,mS,>")
504 (match_operand:HI 1 "general_src_operand" "d,rnmS,mS,n,>")))]
507 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
508 return "cmpm%.w %1,%0";
509 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
510 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
512 cc_status.flags |= CC_REVERSED; /*|*/
513 return "cmp%.w %d0,%d1";
515 return "cmp%.w %d1,%d0";
518 (define_expand "cmpqi"
520 (compare (match_operand:QI 0 "nonimmediate_src_operand" "")
521 (match_operand:QI 1 "general_src_operand" "")))]
523 "m68k_last_compare_had_fp_operands = 0;")
527 (compare (match_operand:QI 0 "nonimmediate_src_operand" "dn,dmS,>")
528 (match_operand:QI 1 "general_src_operand" "dmS,nd,>")))]
531 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
532 return "cmpm%.b %1,%0";
533 if (REG_P (operands[1])
534 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
536 cc_status.flags |= CC_REVERSED; /*|*/
537 return "cmp%.b %d0,%d1";
539 return "cmp%.b %d1,%d0";
542 (define_expand "cmp<mode>"
544 (compare (match_operand:FP 0 "register_operand" "")
545 (match_operand:FP 1 "fp_src_operand" "")))]
547 "m68k_last_compare_had_fp_operands = 1;")
549 (define_insn "*cmp<mode>_68881"
551 (compare (match_operand:FP 0 "fp_src_operand" "f,f,<FP:dreg>mF")
552 (match_operand:FP 1 "fp_src_operand" "f,<FP:dreg>mF,f")))]
554 && (register_operand (operands[0], <MODE>mode)
555 || register_operand (operands[1], <MODE>mode))"
558 fcmp%.<FP:prec> %f1,%0
559 fcmp%.<FP:prec> %0,%f1"
560 [(set_attr "type" "fcmp")])
562 (define_insn "*cmp<mode>_cf"
564 (compare (match_operand:FP 0 "fp_src_operand" "f,f,<FP:dreg><Q>U")
565 (match_operand:FP 1 "fp_src_operand" "f,<FP:dreg><Q>U,f")))]
567 && (register_operand (operands[0], <MODE>mode)
568 || register_operand (operands[1], <MODE>mode))"
571 fcmp%.<FP:prec> %f1,%0
572 fcmp%.<FP:prec> %0,%f1"
573 [(set_attr "type" "fcmp")])
575 ;; Recognizers for btst instructions.
577 ;; ColdFire/5200 only allows "<Q>" type addresses when the bit position is
578 ;; specified as a constant, so we must disable all patterns that may extract
579 ;; from a MEM at a constant bit position if we can't use this as a constraint.
582 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_src_operand" "oS")
584 (minus:SI (const_int 7)
585 (match_operand:SI 1 "general_operand" "di"))))]
588 return output_btst (operands, operands[1], operands[0], insn, 7);
591 ;; This is the same as the above pattern except for the constraints. The 'i'
595 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
597 (minus:SI (const_int 7)
598 (match_operand:SI 1 "general_operand" "d"))))]
601 return output_btst (operands, operands[1], operands[0], insn, 7);
605 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
607 (minus:SI (const_int 31)
608 (match_operand:SI 1 "general_operand" "di"))))]
611 return output_btst (operands, operands[1], operands[0], insn, 31);
614 ;; The following two patterns are like the previous two
615 ;; except that they use the fact that bit-number operands
616 ;; are automatically masked to 3 or 5 bits.
619 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
621 (minus:SI (const_int 7)
623 (match_operand:SI 1 "register_operand" "d")
627 return output_btst (operands, operands[1], operands[0], insn, 7);
631 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
633 (minus:SI (const_int 31)
635 (match_operand:SI 1 "register_operand" "d")
639 return output_btst (operands, operands[1], operands[0], insn, 31);
642 ;; Nonoffsettable mem refs are ok in this one pattern
643 ;; since we don't try to adjust them.
645 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
647 (match_operand:SI 1 "const_int_operand" "n")))]
648 "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_COLDFIRE"
650 operands[1] = GEN_INT (7 - INTVAL (operands[1]));
651 return output_btst (operands, operands[1], operands[0], insn, 7);
655 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
657 (match_operand:SI 1 "const_int_operand" "n")))]
660 if (GET_CODE (operands[0]) == MEM)
662 operands[0] = adjust_address (operands[0], QImode,
663 INTVAL (operands[1]) / 8);
664 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
665 return output_btst (operands, operands[1], operands[0], insn, 7);
667 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
668 return output_btst (operands, operands[1], operands[0], insn, 31);
671 ;; This is the same as the above pattern except for the constraints.
672 ;; The 'o' has been replaced with 'Q'.
675 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ")
677 (match_operand:SI 1 "const_int_operand" "n")))]
680 if (GET_CODE (operands[0]) == MEM)
682 operands[0] = adjust_address (operands[0], QImode,
683 INTVAL (operands[1]) / 8);
684 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
685 return output_btst (operands, operands[1], operands[0], insn, 7);
687 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
688 return output_btst (operands, operands[1], operands[0], insn, 31);
694 ;; A special case in which it is not desirable
695 ;; to reload the constant into a data register.
696 (define_insn "pushexthisi_const"
697 [(set (match_operand:SI 0 "push_operand" "=m,m,m")
698 (match_operand:SI 1 "const_int_operand" "C0,R,J"))]
699 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
704 [(set_attr "type" "clr_l,mov3q_l,pea")])
707 ;(define_insn "swapsi"
708 ; [(set (match_operand:SI 0 "nonimmediate_operand" "+r")
709 ; (match_operand:SI 1 "general_operand" "+r"))
710 ; (set (match_dup 1) (match_dup 0))]
714 ;; Special case of fullword move when source is zero for 68000_10.
715 ;; moveq is faster on the 68000.
716 (define_insn "*movsi_const0_68000_10"
717 [(set (match_operand:SI 0 "movsi_const0_operand" "=d,a,g")
724 [(set_attr "type" "moveq_l,alu_l,clr_l")
725 (set_attr "opy" "*,0,*")])
727 ;; Special case of fullword move when source is zero for 68040_60.
728 ;; On the '040, 'subl an,an' takes 2 clocks while lea takes only 1
729 (define_insn "*movsi_const0_68040_60"
730 [(set (match_operand:SI 0 "movsi_const0_operand" "=a,g")
734 if (which_alternative == 0)
735 return MOTOROLA ? "lea 0.w,%0" : "lea 0:w,%0";
736 else if (which_alternative == 1)
744 [(set_attr "type" "lea,clr_l")])
746 ;; Special case of fullword move when source is zero.
747 (define_insn "*movsi_const0"
748 [(set (match_operand:SI 0 "movsi_const0_operand" "=a,g")
750 "!(TUNE_68000_10 || TUNE_68040_60)"
754 [(set_attr "type" "alu_l,clr_l")
755 (set_attr "opy" "0,*")])
757 ;; General case of fullword move.
759 ;; This is the main "hook" for PIC code. When generating
760 ;; PIC, movsi is responsible for determining when the source address
761 ;; needs PIC relocation and appropriately calling legitimize_pic_address
762 ;; to perform the actual relocation.
764 ;; In both the PIC and non-PIC cases the patterns generated will
765 ;; matched by the next define_insn.
766 (define_expand "movsi"
767 [(set (match_operand:SI 0 "" "")
768 (match_operand:SI 1 "" ""))]
771 rtx tmp, base, offset;
773 if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
775 /* The source is an address which requires PIC relocation.
776 Call legitimize_pic_address with the source, mode, and a relocation
777 register (a new pseudo, or the final destination if reload_in_progress
778 is set). Then fall through normally */
779 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
780 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
782 else if (flag_pic && TARGET_PCREL && ! reload_in_progress)
784 /* Don't allow writes to memory except via a register;
785 the m68k doesn't consider PC-relative addresses to be writable. */
786 if (symbolic_operand (operands[0], SImode))
787 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
788 else if (GET_CODE (operands[0]) == MEM
789 && symbolic_operand (XEXP (operands[0], 0), SImode))
790 operands[0] = gen_rtx_MEM (SImode,
791 force_reg (SImode, XEXP (operands[0], 0)));
793 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P)
795 split_const (operands[1], &base, &offset);
796 if (GET_CODE (base) == SYMBOL_REF
797 && !offset_within_block_p (base, INTVAL (offset)))
799 tmp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (SImode);
800 emit_move_insn (tmp, base);
801 emit_insn (gen_addsi3 (operands[0], tmp, offset));
807 ;; General case of fullword move.
808 (define_insn "*movsi_m68k"
809 ;; Notes: make sure no alternative allows g vs g.
810 ;; We don't allow f-regs since fixed point cannot go in them.
811 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d,a<")
812 (match_operand:SI 1 "general_src_operand" "damSnT,n,i"))]
813 "!TARGET_COLDFIRE && reload_completed"
815 return output_move_simode (operands);
818 ;; Before reload is completed the register constraints
819 ;; force integer constants in range for a moveq to be reloaded
820 ;; if they are headed for memory.
821 (define_insn "*movsi_m68k2"
822 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d,a<")
823 (match_operand:SI 1 "general_src_operand" "damSKT,n,i"))]
827 return output_move_simode (operands);
830 ;; ColdFire move instructions can have at most one operand of mode >= 6.
831 (define_insn "*movsi_cf"
832 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d, d, d, d, d, a,Ap, a, r<Q>,g, U")
833 (match_operand:SI 1 "general_operand" " R,CQ,CW,CZ,CS,Ci,J,J Cs,Cs, g, Rr<Q>,U"))]
836 switch (which_alternative)
839 return "mov3q%.l %1,%0";
842 return "moveq %1,%0";
846 unsigned u = INTVAL (operands[1]);
848 operands[1] = GEN_INT ((u << 16) | (u >> 16)); /*|*/
849 return "moveq %1,%0\n\tswap %0";
853 return "mvz%.w %1,%0";
856 return "mvs%.w %1,%0";
859 return "move%.l %1,%0";
862 return "move%.w %1,%0";
873 return "move%.l %1,%0";
880 [(set_attr "type" "mov3q_l,moveq_l,*,mvsz,mvsz,move_l,move,pea,lea,move_l,move_l,move_l")])
882 ;; Special case of fullword move, where we need to get a non-GOT PIC
883 ;; reference into an address register.
885 [(set (match_operand:SI 0 "nonimmediate_operand" "=a<")
886 (match_operand:SI 1 "pcrel_address" ""))]
889 if (push_operand (operands[0], SImode))
894 (define_expand "movhi"
895 [(set (match_operand:HI 0 "nonimmediate_operand" "")
896 (match_operand:HI 1 "general_operand" ""))]
901 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
902 (match_operand:HI 1 "general_src_operand" "gS"))]
904 "* return output_move_himode (operands);")
907 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<Q>,g,U")
908 (match_operand:HI 1 "general_operand" "g,r<Q>,U"))]
910 "* return output_move_himode (operands);")
912 (define_expand "movstricthi"
913 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
914 (match_operand:HI 1 "general_src_operand" ""))]
919 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
920 (match_operand:HI 1 "general_src_operand" "rmSn"))]
922 "* return output_move_stricthi (operands);")
925 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+d,m"))
926 (match_operand:HI 1 "general_src_operand" "rmn,r"))]
928 "* return output_move_stricthi (operands);")
930 (define_expand "movqi"
931 [(set (match_operand:QI 0 "nonimmediate_operand" "")
932 (match_operand:QI 1 "general_src_operand" ""))]
937 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,*a,m")
938 (match_operand:QI 1 "general_src_operand" "dmSi*a,di*a,dmSi"))]
940 "* return output_move_qimode (operands);")
943 [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>,dm,U,d*a")
944 (match_operand:QI 1 "general_src_operand" "dmi,d<Q>,U,di*a"))]
946 "* return output_move_qimode (operands);")
948 (define_expand "movstrictqi"
949 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
950 (match_operand:QI 1 "general_src_operand" ""))]
955 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
956 (match_operand:QI 1 "general_src_operand" "dmSn"))]
958 "* return output_move_strictqi (operands);")
960 (define_insn "*movstrictqi_cf"
961 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+d, Ac, d,m"))
962 (match_operand:QI 1 "general_src_operand" "C0,C0, dmn,d"))]
969 [(set_attr "type" "clr,clr,move,move")])
971 (define_expand "pushqi1"
972 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -2)))
973 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int 1)))
974 (match_operand:QI 0 "general_operand" ""))]
978 (define_expand "reload_insf"
979 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
980 (match_operand:SF 1 "general_operand" "mf"))
981 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
982 "TARGET_COLDFIRE_FPU"
984 if (emit_move_sequence (operands, SFmode, operands[2]))
987 /* We don't want the clobber emitted, so handle this ourselves. */
988 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
992 (define_expand "reload_outsf"
993 [(set (match_operand:SF 0 "general_operand" "")
994 (match_operand:SF 1 "register_operand" "f"))
995 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
996 "TARGET_COLDFIRE_FPU"
998 if (emit_move_sequence (operands, SFmode, operands[2]))
1001 /* We don't want the clobber emitted, so handle this ourselves. */
1002 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
1006 (define_expand "movsf"
1007 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1008 (match_operand:SF 1 "general_operand" ""))]
1013 [(set (match_operand:SF 0 "nonimmediate_operand" "=rmf")
1014 (match_operand:SF 1 "general_operand" "rmfF"))]
1017 if (FP_REG_P (operands[0]))
1019 if (FP_REG_P (operands[1]))
1020 return "f%$move%.x %1,%0";
1021 else if (ADDRESS_REG_P (operands[1]))
1022 return "move%.l %1,%-\;f%$move%.s %+,%0";
1023 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1024 return output_move_const_single (operands);
1025 return "f%$move%.s %f1,%0";
1027 if (FP_REG_P (operands[1]))
1029 if (ADDRESS_REG_P (operands[0]))
1030 return "fmove%.s %1,%-\;move%.l %+,%0";
1031 return "fmove%.s %f1,%0";
1033 if (operands[1] == CONST0_RTX (SFmode)
1034 /* clr insns on 68000 read before writing. */
1035 && ((TARGET_68010 || TARGET_COLDFIRE)
1036 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1038 if (ADDRESS_REG_P (operands[0]))
1040 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
1042 return MOTOROLA ? "lea 0.w,%0" : "lea 0:w,%0";
1044 return "sub%.l %0,%0";
1046 /* moveq is faster on the 68000. */
1047 if (DATA_REG_P (operands[0]) && TUNE_68000_10)
1048 return "moveq #0,%0";
1051 return "move%.l %1,%0";
1054 (define_insn "movsf_cf_soft"
1055 [(set (match_operand:SF 0 "nonimmediate_operand" "=r<Q>,g,U")
1056 (match_operand:SF 1 "general_operand" "g,r<Q>,U"))]
1057 "TARGET_COLDFIRE && !TARGET_COLDFIRE_FPU"
1059 [(set_attr "type" "move_l")])
1061 ;; SFmode MEMs are restricted to modes 2-4 if TARGET_COLDFIRE_FPU.
1062 ;; The move instructions can handle all combinations.
1063 (define_insn "movsf_cf_hard"
1064 [(set (match_operand:SF 0 "nonimmediate_operand" "=r<Q>U, f, f,mr,f,r<Q>,f
1066 (match_operand:SF 1 "general_operand" " f, r<Q>U,f,rm,F,F, m
1068 "TARGET_COLDFIRE_FPU"
1070 if (which_alternative == 4 || which_alternative == 5) {
1074 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
1075 REAL_VALUE_TO_TARGET_SINGLE (r, l);
1076 xoperands[0] = operands[0];
1077 xoperands[1] = GEN_INT (l);
1078 if (which_alternative == 5) {
1080 if (ADDRESS_REG_P (xoperands[0]))
1081 output_asm_insn ("sub%.l %0,%0", xoperands);
1083 output_asm_insn ("clr%.l %0", xoperands);
1085 if (GET_CODE (operands[0]) == MEM
1086 && symbolic_operand (XEXP (operands[0], 0), SImode))
1087 output_asm_insn ("move%.l %1,%-;move%.l %+,%0", xoperands);
1089 output_asm_insn ("move%.l %1,%0", xoperands);
1093 output_asm_insn ("move%.l %1,%-;fsmove%.s %+,%0", xoperands);
1095 output_asm_insn ("clr%.l %-;fsmove%.s %+,%0", xoperands);
1098 if (FP_REG_P (operands[0]))
1100 if (ADDRESS_REG_P (operands[1]))
1101 return "move%.l %1,%-;fsmove%.s %+,%0";
1102 if (FP_REG_P (operands[1]))
1103 return "fsmove%.d %1,%0";
1104 return "fsmove%.s %f1,%0";
1106 if (FP_REG_P (operands[1]))
1108 if (ADDRESS_REG_P (operands[0]))
1109 return "fmove%.s %1,%-;move%.l %+,%0";
1110 return "fmove%.s %f1,%0";
1112 if (operands[1] == CONST0_RTX (SFmode))
1114 if (ADDRESS_REG_P (operands[0]))
1115 return "sub%.l %0,%0";
1118 return "move%.l %1,%0";
1121 (define_expand "reload_indf"
1122 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
1123 (match_operand:DF 1 "general_operand" "mf"))
1124 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
1125 "TARGET_COLDFIRE_FPU"
1127 if (emit_move_sequence (operands, DFmode, operands[2]))
1130 /* We don't want the clobber emitted, so handle this ourselves. */
1131 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
1135 (define_expand "reload_outdf"
1136 [(set (match_operand:DF 0 "general_operand" "")
1137 (match_operand:DF 1 "register_operand" "f"))
1138 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
1139 "TARGET_COLDFIRE_FPU"
1141 if (emit_move_sequence (operands, DFmode, operands[2]))
1144 /* We don't want the clobber emitted, so handle this ourselves. */
1145 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
1149 (define_expand "movdf"
1150 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1151 (match_operand:DF 1 "general_operand" ""))]
1154 if (TARGET_COLDFIRE_FPU)
1155 if (emit_move_sequence (operands, DFmode, 0))
1160 [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,rf,rf,&rof<>")
1161 (match_operand:DF 1 "general_operand" "*rf,m,0,*rofE<>"))]
1162 ; [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,&rf,&rof<>")
1163 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
1166 if (FP_REG_P (operands[0]))
1168 if (FP_REG_P (operands[1]))
1169 return "f%&move%.x %1,%0";
1170 if (REG_P (operands[1]))
1173 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1174 output_asm_insn ("move%.l %1,%-", xoperands);
1175 output_asm_insn ("move%.l %1,%-", operands);
1176 return "f%&move%.d %+,%0";
1178 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1179 return output_move_const_double (operands);
1180 return "f%&move%.d %f1,%0";
1182 else if (FP_REG_P (operands[1]))
1184 if (REG_P (operands[0]))
1186 output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands);
1187 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1188 return "move%.l %+,%0";
1191 return "fmove%.d %f1,%0";
1193 return output_move_double (operands);
1196 (define_insn_and_split "movdf_cf_soft"
1197 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,g")
1198 (match_operand:DF 1 "general_operand" "g,r"))]
1199 "TARGET_COLDFIRE && !TARGET_COLDFIRE_FPU"
1201 "&& reload_completed"
1204 m68k_emit_move_double (operands);
1208 (define_insn "movdf_cf_hard"
1209 [(set (match_operand:DF 0 "nonimmediate_operand" "=f, <Q>U,r,f,r,r,m,f")
1210 (match_operand:DF 1 "general_operand" " f<Q>U,f, f,r,r,m,r,E"))]
1211 "TARGET_COLDFIRE_FPU"
1217 switch (which_alternative)
1220 return "fdmove%.d %1,%0";
1222 return "fmove%.d %1,%0";
1224 return "fmove%.d %1,%-;move%.l %+,%0;move%.l %+,%R0";
1226 return "move%.l %R1,%-;move%.l %1,%-;fdmove%.d %+,%0";
1227 case 4: case 5: case 6:
1228 return output_move_double (operands);
1230 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
1231 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
1232 xoperands[0] = operands[0];
1233 xoperands[1] = GEN_INT (l[0]);
1234 xoperands[2] = GEN_INT (l[1]);
1235 if (operands[1] == CONST0_RTX (DFmode))
1236 output_asm_insn ("clr%.l %-;clr%.l %-;fdmove%.d %+,%0",
1240 output_asm_insn ("clr%.l %-;move%.l %1,%-;fdmove%.d %+,%0",
1243 output_asm_insn ("move%.l %2,%-;move%.l %1,%-;fdmove%.d %+,%0",
1249 ;; ??? The XFmode patterns are schizophrenic about whether constants are
1250 ;; allowed. Most but not all have predicates and constraint that disallow
1251 ;; constants. Most but not all have output templates that handle constants.
1252 ;; See also LEGITIMATE_CONSTANT_P.
1254 (define_expand "movxf"
1255 [(set (match_operand:XF 0 "nonimmediate_operand" "")
1256 (match_operand:XF 1 "general_operand" ""))]
1259 /* We can't rewrite operands during reload. */
1260 if (! reload_in_progress)
1262 if (CONSTANT_P (operands[1]))
1264 operands[1] = force_const_mem (XFmode, operands[1]);
1265 if (! memory_address_p (XFmode, XEXP (operands[1], 0)))
1266 operands[1] = adjust_address (operands[1], XFmode, 0);
1268 if (flag_pic && TARGET_PCREL)
1270 /* Don't allow writes to memory except via a register; the
1271 m68k doesn't consider PC-relative addresses to be writable. */
1272 if (GET_CODE (operands[0]) == MEM
1273 && symbolic_operand (XEXP (operands[0], 0), SImode))
1274 operands[0] = gen_rtx_MEM (XFmode,
1275 force_reg (SImode, XEXP (operands[0], 0)));
1281 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f,!r,m,!r")
1282 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r,!r,!r,m"))]
1285 if (FP_REG_P (operands[0]))
1287 if (FP_REG_P (operands[1]))
1288 return "fmove%.x %1,%0";
1289 if (REG_P (operands[1]))
1292 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1293 output_asm_insn ("move%.l %1,%-", xoperands);
1294 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1295 output_asm_insn ("move%.l %1,%-", xoperands);
1296 output_asm_insn ("move%.l %1,%-", operands);
1297 return "fmove%.x %+,%0";
1299 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1300 return "fmove%.x %1,%0";
1301 return "fmove%.x %f1,%0";
1303 if (FP_REG_P (operands[1]))
1305 if (REG_P (operands[0]))
1307 output_asm_insn ("fmove%.x %f1,%-\;move%.l %+,%0", operands);
1308 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1309 output_asm_insn ("move%.l %+,%0", operands);
1310 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1311 return "move%.l %+,%0";
1313 /* Must be memory destination. */
1314 return "fmove%.x %f1,%0";
1316 return output_move_double (operands);
1320 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1321 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1322 "! TARGET_68881 && ! TARGET_COLDFIRE"
1324 if (FP_REG_P (operands[0]))
1326 if (FP_REG_P (operands[1]))
1327 return "fmove%.x %1,%0";
1328 if (REG_P (operands[1]))
1331 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1332 output_asm_insn ("move%.l %1,%-", xoperands);
1333 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1334 output_asm_insn ("move%.l %1,%-", xoperands);
1335 output_asm_insn ("move%.l %1,%-", operands);
1336 return "fmove%.x %+,%0";
1338 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1339 return "fmove%.x %1,%0";
1340 return "fmove%.x %f1,%0";
1342 if (FP_REG_P (operands[1]))
1344 if (REG_P (operands[0]))
1346 output_asm_insn ("fmove%.x %f1,%-\;move%.l %+,%0", operands);
1347 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1348 output_asm_insn ("move%.l %+,%0", operands);
1349 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1350 return "move%.l %+,%0";
1353 return "fmove%.x %f1,%0";
1355 return output_move_double (operands);
1359 [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
1360 (match_operand:XF 1 "nonimmediate_operand" "g,r"))]
1361 "! TARGET_68881 && TARGET_COLDFIRE"
1362 "* return output_move_double (operands);")
1364 (define_expand "movdi"
1365 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1366 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1367 (match_operand:DI 1 "general_operand" ""))]
1371 ;; movdi can apply to fp regs in some cases
1373 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1374 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r,&ro<>")
1375 (match_operand:DI 1 "general_operand" "rF,m,roi<>F"))]
1376 ; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&r,&ro<>,!&rm,!&f")
1377 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF"))]
1378 ; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1379 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1382 if (FP_REG_P (operands[0]))
1384 if (FP_REG_P (operands[1]))
1385 return "fmove%.x %1,%0";
1386 if (REG_P (operands[1]))
1389 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1390 output_asm_insn ("move%.l %1,%-", xoperands);
1391 output_asm_insn ("move%.l %1,%-", operands);
1392 return "fmove%.d %+,%0";
1394 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1395 return output_move_const_double (operands);
1396 return "fmove%.d %f1,%0";
1398 else if (FP_REG_P (operands[1]))
1400 if (REG_P (operands[0]))
1402 output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands);
1403 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1404 return "move%.l %+,%0";
1407 return "fmove%.d %f1,%0";
1409 return output_move_double (operands);
1413 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,g")
1414 (match_operand:DI 1 "general_operand" "g,r"))]
1416 "* return output_move_double (operands);")
1418 ;; Thus goes after the move instructions
1419 ;; because the move instructions are better (require no spilling)
1420 ;; when they can apply. It goes before the add/sub insns
1421 ;; so we will prefer it to them.
1423 (define_insn "pushasi"
1424 [(set (match_operand:SI 0 "push_operand" "=m")
1425 (match_operand:SI 1 "address_operand" "p"))]
1428 [(set_attr "type" "pea")])
1430 ;; truncation instructions
1431 (define_insn "truncsiqi2"
1432 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d")
1434 (match_operand:SI 1 "general_src_operand" "doJS,i")))]
1437 if (GET_CODE (operands[0]) == REG)
1439 /* Must clear condition codes, since the move.l bases them on
1440 the entire 32 bits, not just the desired 8 bits. */
1442 return "move%.l %1,%0";
1444 if (GET_CODE (operands[1]) == MEM)
1445 operands[1] = adjust_address (operands[1], QImode, 3);
1446 return "move%.b %1,%0";
1449 (define_insn "trunchiqi2"
1450 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d")
1452 (match_operand:HI 1 "general_src_operand" "doJS,i")))]
1455 if (GET_CODE (operands[0]) == REG
1456 && (GET_CODE (operands[1]) == MEM
1457 || GET_CODE (operands[1]) == CONST_INT))
1459 /* Must clear condition codes, since the move.w bases them on
1460 the entire 16 bits, not just the desired 8 bits. */
1462 return "move%.w %1,%0";
1464 if (GET_CODE (operands[0]) == REG)
1466 /* Must clear condition codes, since the move.l bases them on
1467 the entire 32 bits, not just the desired 8 bits. */
1469 return "move%.l %1,%0";
1471 if (GET_CODE (operands[1]) == MEM)
1472 operands[1] = adjust_address (operands[1], QImode, 1);
1473 return "move%.b %1,%0";
1476 (define_insn "truncsihi2"
1477 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm,d")
1479 (match_operand:SI 1 "general_src_operand" "roJS,i")))]
1482 if (GET_CODE (operands[0]) == REG)
1484 /* Must clear condition codes, since the move.l bases them on
1485 the entire 32 bits, not just the desired 8 bits. */
1487 return "move%.l %1,%0";
1489 if (GET_CODE (operands[1]) == MEM)
1490 operands[1] = adjust_address (operands[1], QImode, 2);
1491 return "move%.w %1,%0";
1494 ;; zero extension instructions
1496 ;; two special patterns to match various post_inc/pre_dec patterns
1497 (define_insn_and_split "*zero_extend_inc"
1498 [(set (match_operand 0 "post_inc_operand" "")
1499 (zero_extend (match_operand 1 "register_operand" "")))]
1500 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT &&
1501 GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT &&
1502 GET_MODE_SIZE (GET_MODE (operands[0])) == GET_MODE_SIZE (GET_MODE (operands[1])) * 2"
1510 operands[0] = adjust_address (operands[0], GET_MODE (operands[1]), 0);
1513 (define_insn_and_split "*zero_extend_dec"
1514 [(set (match_operand 0 "pre_dec_operand" "")
1515 (zero_extend (match_operand 1 "register_operand" "")))]
1516 "(GET_MODE (operands[0]) != HImode || XEXP (XEXP (operands[0], 0), 0) != stack_pointer_rtx) &&
1517 GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT &&
1518 GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT &&
1519 GET_MODE_SIZE (GET_MODE (operands[0])) == GET_MODE_SIZE (GET_MODE (operands[1])) * 2"
1527 operands[0] = adjust_address (operands[0], GET_MODE (operands[1]), 0);
1530 (define_insn_and_split "zero_extendqidi2"
1531 [(set (match_operand:DI 0 "register_operand" "")
1532 (zero_extend:DI (match_operand:QI 1 "nonimmediate_src_operand" "")))]
1537 (zero_extend:SI (match_dup 1)))
1541 operands[2] = gen_lowpart (SImode, operands[0]);
1542 operands[3] = gen_highpart (SImode, operands[0]);
1545 (define_insn_and_split "zero_extendhidi2"
1546 [(set (match_operand:DI 0 "register_operand" "")
1547 (zero_extend:DI (match_operand:HI 1 "nonimmediate_src_operand" "")))]
1552 (zero_extend:SI (match_dup 1)))
1556 operands[2] = gen_lowpart (SImode, operands[0]);
1557 operands[3] = gen_highpart (SImode, operands[0]);
1560 (define_expand "zero_extendsidi2"
1561 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1562 (zero_extend:DI (match_operand:SI 1 "nonimmediate_src_operand" "")))]
1565 if (GET_CODE (operands[0]) == MEM
1566 && GET_CODE (operands[1]) == MEM)
1567 operands[1] = force_reg (SImode, operands[1]);
1570 (define_insn_and_split "*zero_extendsidi2"
1571 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1572 (zero_extend:DI (match_operand:SI 1 "nonimmediate_src_operand" "")))]
1573 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1581 operands[2] = gen_lowpart (SImode, operands[0]);
1582 operands[3] = gen_highpart (SImode, operands[0]);
1585 (define_insn "*zero_extendhisi2_cf"
1586 [(set (match_operand:SI 0 "register_operand" "=d")
1587 (zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))]
1590 [(set_attr "type" "mvsz")])
1592 (define_insn "zero_extendhisi2"
1593 [(set (match_operand:SI 0 "register_operand" "=d")
1594 (zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))]
1598 (define_expand "zero_extendqihi2"
1599 [(set (match_operand:HI 0 "register_operand" "")
1600 (zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "")))]
1604 (define_insn "*zero_extendqihi2"
1605 [(set (match_operand:HI 0 "register_operand" "=d")
1606 (zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "dmS")))]
1610 (define_insn "*zero_extendqisi2_cfv4"
1611 [(set (match_operand:SI 0 "register_operand" "=d")
1612 (zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "dmS")))]
1615 [(set_attr "type" "mvsz")])
1617 (define_insn "zero_extendqisi2"
1618 [(set (match_operand:SI 0 "register_operand" "=d")
1619 (zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "dmS")))]
1623 ;; these two pattern split everything else which isn't matched by
1624 ;; something else above
1626 [(set (match_operand 0 "register_operand" "")
1627 (zero_extend (match_operand 1 "nonimmediate_src_operand" "")))]
1630 && reg_mentioned_p (operands[0], operands[1])"
1631 [(set (strict_low_part (match_dup 2))
1634 (match_op_dup 4 [(match_dup 0) (match_dup 3)]))]
1636 operands[2] = gen_lowpart (GET_MODE (operands[1]), operands[0]);
1637 operands[3] = GEN_INT (GET_MODE_MASK (GET_MODE (operands[1])));
1638 operands[4] = gen_rtx_AND (GET_MODE (operands[0]), operands[0], operands[3]);
1642 [(set (match_operand 0 "register_operand" "")
1643 (zero_extend (match_operand 1 "nonimmediate_src_operand" "")))]
1644 "!ISA_HAS_MVS_MVZ && reload_completed"
1647 (set (strict_low_part (match_dup 2))
1650 operands[2] = gen_lowpart (GET_MODE (operands[1]), operands[0]);
1653 ;; sign extension instructions
1655 (define_insn "extendqidi2"
1656 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1657 (sign_extend:DI (match_operand:QI 1 "general_src_operand" "rmS")))]
1661 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1662 if (ISA_HAS_MVS_MVZ)
1663 return "mvs%.b %1,%2\;smi %0\;extb%.l %0";
1664 if (TARGET_68020 || TARGET_COLDFIRE)
1666 if (ADDRESS_REG_P (operands[1]))
1667 return "move%.w %1,%2\;extb%.l %2\;smi %0\;extb%.l %0";
1669 return "move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0";
1673 if (ADDRESS_REG_P (operands[1]))
1674 return "move%.w %1,%2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\;smi %0";
1676 return "move%.b %1,%2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\;smi %0";
1680 (define_insn "extendhidi2"
1681 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1683 (match_operand:HI 1 "general_src_operand" "rmS")))]
1687 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1688 if (ISA_HAS_MVS_MVZ)
1689 return "mvs%.w %1,%2\;smi %0\;extb%.l %0";
1690 if (TARGET_68020 || TARGET_COLDFIRE)
1691 return "move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0";
1693 return "move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0";
1696 (define_insn "extendsidi2"
1697 [(set (match_operand:DI 0 "register_operand" "=d")
1698 (sign_extend:DI (match_operand:SI 1 "nonimmediate_src_operand" "rm")))]
1702 if (TARGET_68020 || TARGET_COLDFIRE)
1703 return "move%.l %1,%R0\;smi %0\;extb%.l %0";
1705 return "move%.l %1,%R0\;smi %0\;ext%.w %0\;ext%.l %0";
1708 (define_insn "*extendsidi2_mem"
1709 [(set (match_operand:DI 0 "memory_operand" "=o,<")
1710 (sign_extend:DI (match_operand:SI 1 "nonimmediate_src_operand" "rm,rm")))
1711 (clobber (match_scratch:SI 2 "=d,d"))]
1715 operands[3] = adjust_address (operands[0], SImode,
1716 which_alternative == 0 ? 4 : 0);
1717 operands[0] = adjust_address (operands[0], SImode, 0);
1718 if (TARGET_68020 || TARGET_COLDFIRE)
1719 return "move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0";
1721 return "move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0";
1724 ;; Special case when one can avoid register clobbering, copy and test
1725 ;; Maybe there is a way to make that the general case, by forcing the
1726 ;; result of the SI tree to be in the lower register of the DI target
1728 (define_insn "extendplussidi"
1729 [(set (match_operand:DI 0 "register_operand" "=d")
1730 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1731 (match_operand:SI 2 "general_operand" "rmn"))))]
1735 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1736 if (GET_CODE (operands[1]) == CONST_INT
1737 && (unsigned) INTVAL (operands[1]) > 8)
1739 rtx tmp = operands[1];
1741 operands[1] = operands[2];
1744 if (GET_CODE (operands[1]) == REG
1745 && REGNO (operands[1]) == REGNO (operands[3]))
1746 output_asm_insn ("add%.l %2,%3", operands);
1748 output_asm_insn ("move%.l %2,%3\;add%.l %1,%3", operands);
1749 if (TARGET_68020 || TARGET_COLDFIRE)
1750 return "smi %0\;extb%.l %0";
1752 return "smi %0\;ext%.w %0\;ext%.l %0";
1755 (define_expand "extendhisi2"
1756 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1758 (match_operand:HI 1 "nonimmediate_src_operand" "")))]
1762 (define_insn "*cfv4_extendhisi2"
1763 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
1765 (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))]
1768 [(set_attr "type" "mvsz")])
1770 (define_insn "*68k_extendhisi2"
1771 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,a")
1773 (match_operand:HI 1 "nonimmediate_src_operand" "0,rmS")))]
1778 [(set_attr "type" "ext,move")])
1780 (define_insn "extendqihi2"
1781 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
1782 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1785 [(set_attr "type" "ext")])
1787 (define_expand "extendqisi2"
1788 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1789 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1790 "TARGET_68020 || TARGET_COLDFIRE"
1793 (define_insn "*cfv4_extendqisi2"
1794 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
1795 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rms")))]
1798 [(set_attr "type" "mvsz")])
1800 (define_insn "*68k_extendqisi2"
1801 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
1802 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1803 "TARGET_68020 || (TARGET_COLDFIRE && !ISA_HAS_MVS_MVZ)"
1805 [(set_attr "type" "ext")])
1807 ;; Conversions between float and double.
1809 (define_expand "extendsfdf2"
1810 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1812 (match_operand:SF 1 "general_operand" "")))]
1817 [(set (match_operand:DF 0 "nonimmediate_operand" "=*fdm,f")
1819 (match_operand:SF 1 "general_operand" "f,dmF")))]
1822 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1824 if (REGNO (operands[0]) == REGNO (operands[1]))
1826 /* Extending float to double in an fp-reg is a no-op.
1827 NOTICE_UPDATE_CC has already assumed that the
1828 cc will be set. So cancel what it did. */
1829 cc_status = cc_prev_status;
1832 return "f%&move%.x %1,%0";
1834 if (FP_REG_P (operands[0]))
1835 return "f%&move%.s %f1,%0";
1836 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1838 output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands);
1839 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1840 return "move%.l %+,%0";
1842 return "fmove%.d %f1,%0";
1845 (define_insn "extendsfdf2_cf"
1846 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f")
1848 (match_operand:SF 1 "general_operand" "f,<Q>U")))]
1849 "TARGET_COLDFIRE_FPU"
1851 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1853 if (REGNO (operands[0]) == REGNO (operands[1]))
1855 /* Extending float to double in an fp-reg is a no-op.
1856 NOTICE_UPDATE_CC has already assumed that the
1857 cc will be set. So cancel what it did. */
1858 cc_status = cc_prev_status;
1861 return "fdmove%.d %1,%0";
1863 return "fdmove%.s %f1,%0";
1866 ;; This cannot output into an f-reg because there is no way to be
1867 ;; sure of truncating in that case.
1868 (define_expand "truncdfsf2"
1869 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1871 (match_operand:DF 1 "general_operand" "")))]
1875 ;; On the '040 we can truncate in a register accurately and easily.
1877 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1879 (match_operand:DF 1 "general_operand" "fmG")))]
1880 "TARGET_68881 && TARGET_68040"
1882 if (FP_REG_P (operands[1]))
1883 return "f%$move%.x %1,%0";
1884 return "f%$move%.d %f1,%0";
1887 (define_insn "truncdfsf2_cf"
1888 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,d<Q>U")
1890 (match_operand:DF 1 "general_operand" "<Q>U,f")))]
1891 "TARGET_COLDFIRE_FPU"
1895 [(set_attr "type" "fmove")])
1897 (define_insn "*truncdfsf2_68881"
1898 [(set (match_operand:SF 0 "nonimmediate_operand" "=dm")
1900 (match_operand:DF 1 "general_operand" "f")))]
1903 [(set_attr "type" "fmove")])
1905 ;; Conversion between fixed point and floating point.
1906 ;; Note that among the fix-to-float insns
1907 ;; the ones that start with SImode come first.
1908 ;; That is so that an operand that is a CONST_INT
1909 ;; (and therefore lacks a specific machine mode).
1910 ;; will be recognized as SImode (which is always valid)
1911 ;; rather than as QImode or HImode.
1913 (define_expand "floatsi<mode>2"
1914 [(set (match_operand:FP 0 "nonimmediate_operand" "")
1915 (float:FP (match_operand:SI 1 "general_operand" "")))]
1919 (define_insn "floatsi<mode>2_68881"
1920 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
1921 (float:FP (match_operand:SI 1 "general_operand" "dmi")))]
1923 "f<FP:round>move%.l %1,%0"
1924 [(set_attr "type" "fmove")])
1926 (define_insn "floatsi<mode>2_cf"
1927 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
1928 (float:FP (match_operand:SI 1 "general_operand" "d<Q>U")))]
1929 "TARGET_COLDFIRE_FPU"
1930 "f<FP:prec>move%.l %1,%0"
1931 [(set_attr "type" "fmove")])
1934 (define_expand "floathi<mode>2"
1935 [(set (match_operand:FP 0 "nonimmediate_operand" "")
1936 (float:FP (match_operand:HI 1 "general_operand" "")))]
1940 (define_insn "floathi<mode>2_68881"
1941 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
1942 (float:FP (match_operand:HI 1 "general_operand" "dmn")))]
1945 [(set_attr "type" "fmove")])
1947 (define_insn "floathi<mode>2_cf"
1948 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
1949 (float:FP (match_operand:HI 1 "general_operand" "d<Q>U")))]
1950 "TARGET_COLDFIRE_FPU"
1952 [(set_attr "type" "fmove")])
1955 (define_expand "floatqi<mode>2"
1956 [(set (match_operand:FP 0 "nonimmediate_operand" "")
1957 (float:FP (match_operand:QI 1 "general_operand" "")))]
1961 (define_insn "floatqi<mode>2_68881"
1962 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
1963 (float:FP (match_operand:QI 1 "general_operand" "dmn")))]
1966 [(set_attr "type" "fmove")])
1968 (define_insn "floatqi<mode>2_cf"
1969 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
1970 (float:FP (match_operand:QI 1 "general_operand" "d<Q>U")))]
1971 "TARGET_COLDFIRE_FPU"
1973 [(set_attr "type" "fmove")])
1976 ;; New routines to convert floating-point values to integers
1977 ;; to be used on the '040. These should be faster than trapping
1978 ;; into the kernel to emulate fintrz. They should also be faster
1979 ;; than calling the subroutines fixsfsi or fixdfsi.
1981 (define_insn "fix_truncdfsi2"
1982 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
1983 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1984 (clobber (match_scratch:SI 2 "=d"))
1985 (clobber (match_scratch:SI 3 "=d"))]
1986 "TARGET_68881 && TUNE_68040"
1989 return "fmovem%.l %!,%2\;moveq #16,%3\;or%.l %2,%3\;and%.w #-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!";
1992 (define_insn "fix_truncdfhi2"
1993 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
1994 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1995 (clobber (match_scratch:SI 2 "=d"))
1996 (clobber (match_scratch:SI 3 "=d"))]
1997 "TARGET_68881 && TUNE_68040"
2000 return "fmovem%.l %!,%2\;moveq #16,%3\;or%.l %2,%3\;and%.w #-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!";
2003 (define_insn "fix_truncdfqi2"
2004 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
2005 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
2006 (clobber (match_scratch:SI 2 "=d"))
2007 (clobber (match_scratch:SI 3 "=d"))]
2008 "TARGET_68881 && TUNE_68040"
2011 return "fmovem%.l %!,%2\;moveq #16,%3\;or%.l %2,%3\;and%.w #-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!";
2014 ;; Convert a float to a float whose value is an integer.
2015 ;; This is the first stage of converting it to an integer type.
2017 (define_expand "ftrunc<mode>2"
2018 [(set (match_operand:FP 0 "nonimmediate_operand" "")
2019 (fix:FP (match_operand:FP 1 "general_operand" "")))]
2020 "TARGET_HARD_FLOAT && !TUNE_68040"
2023 (define_insn "ftrunc<mode>2_68881"
2024 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2025 (fix:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m")))]
2026 "TARGET_68881 && !TUNE_68040"
2028 if (FP_REG_P (operands[1]))
2029 return "fintrz%.x %f1,%0";
2030 return "fintrz%.<FP:prec> %f1,%0";
2032 [(set_attr "type" "falu")])
2034 (define_insn "ftrunc<mode>2_cf"
2035 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2036 (fix:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U")))]
2037 "TARGET_COLDFIRE_FPU"
2039 if (FP_REG_P (operands[1]))
2040 return "fintrz%.d %f1,%0";
2041 return "fintrz%.<FP:prec> %f1,%0";
2043 [(set_attr "type" "falu")])
2045 ;; Convert a float whose value is an integer
2046 ;; to an actual integer. Second stage of converting float to integer type.
2047 (define_expand "fix<mode>qi2"
2048 [(set (match_operand:QI 0 "nonimmediate_operand" "")
2049 (fix:QI (match_operand:FP 1 "general_operand" "")))]
2053 (define_insn "fix<mode>qi2_68881"
2054 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
2055 (fix:QI (match_operand:FP 1 "general_operand" "f")))]
2058 [(set_attr "type" "fmove")])
2060 (define_insn "fix<mode>qi2_cf"
2061 [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>U")
2062 (fix:QI (match_operand:FP 1 "general_operand" "f")))]
2063 "TARGET_COLDFIRE_FPU"
2065 [(set_attr "type" "fmove")])
2067 (define_expand "fix<mode>hi2"
2068 [(set (match_operand:HI 0 "nonimmediate_operand" "")
2069 (fix:HI (match_operand:FP 1 "general_operand" "")))]
2073 (define_insn "fix<mode>hi2_68881"
2074 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
2075 (fix:HI (match_operand:FP 1 "general_operand" "f")))]
2078 [(set_attr "type" "fmove")])
2080 (define_insn "fix<mode>hi2_cf"
2081 [(set (match_operand:HI 0 "nonimmediate_operand" "=d<Q>U")
2082 (fix:HI (match_operand:FP 1 "general_operand" "f")))]
2083 "TARGET_COLDFIRE_FPU"
2085 [(set_attr "type" "fmove")])
2087 (define_expand "fix<mode>si2"
2088 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2089 (fix:SI (match_operand:FP 1 "general_operand" "")))]
2093 (define_insn "fix<mode>si2_68881"
2094 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
2095 (fix:SI (match_operand:FP 1 "general_operand" "f")))]
2098 [(set_attr "type" "fmove")])
2100 (define_insn "fix<mode>si2_cf"
2101 [(set (match_operand:SI 0 "nonimmediate_operand" "=d<Q>U")
2102 (fix:SI (match_operand:FP 1 "general_operand" "f")))]
2103 "TARGET_COLDFIRE_FPU"
2105 [(set_attr "type" "fmove")])
2110 (define_insn "adddi_lshrdi_63"
2111 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
2112 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
2115 (clobber (match_scratch:SI 2 "=d"))]
2118 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2119 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
2121 "move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0";
2122 if (GET_CODE (operands[1]) == REG)
2123 operands[4] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2124 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
2125 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2126 operands[4] = operands[1];
2128 operands[4] = adjust_address (operands[1], SImode, 4);
2129 if (GET_CODE (operands[1]) == MEM
2130 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2131 output_asm_insn ("move%.l %4,%3", operands);
2132 output_asm_insn ("move%.l %1,%0\;smi %2", operands);
2133 if (TARGET_68020 || TARGET_COLDFIRE)
2134 output_asm_insn ("extb%.l %2", operands);
2136 output_asm_insn ("ext%.w %2\;ext%.l %2", operands);
2137 if (GET_CODE (operands[1]) != MEM
2138 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
2139 output_asm_insn ("move%.l %4,%3", operands);
2140 return "sub%.l %2,%3\;subx%.l %2,%0";
2143 (define_insn "adddi_sexthishl32"
2144 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,a,*d,*d")
2145 (plus:DI (ashift:DI (sign_extend:DI
2146 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
2148 (match_operand:DI 2 "general_operand" "0,0,0,0")))
2149 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2153 if (ADDRESS_REG_P (operands[0]))
2154 return "add%.w %1,%0";
2155 else if (ADDRESS_REG_P (operands[3]))
2156 return "move%.w %1,%3\;add%.l %3,%0";
2158 return "move%.w %1,%3\;ext%.l %3\;add%.l %3,%0";
2161 (define_insn "*adddi_dilshr32"
2162 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,o")
2163 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,d")
2165 (match_operand:DI 2 "general_operand" "0,0")))]
2169 if (GET_CODE (operands[0]) == REG)
2170 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2172 operands[2] = adjust_address (operands[0], SImode, 4);
2173 return "add%.l %1,%2\;negx%.l %0\;neg%.l %0";
2176 (define_insn "*adddi_dilshr32_cf"
2177 [(set (match_operand:DI 0 "register_operand" "=d")
2178 (plus:DI (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "ro")
2180 (match_operand:DI 2 "register_operand" "0")))]
2184 return "add%.l %1,%R0\;negx%.l %0\;neg%.l %0";
2187 (define_insn "adddi_dishl32"
2188 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
2189 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2190 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2191 ;; (const_int 32))))]
2192 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro,d")
2194 (match_operand:DI 2 "general_operand" "0,0")))]
2198 if (GET_CODE (operands[1]) == REG)
2199 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2201 operands[1] = adjust_address (operands[1], SImode, 4);
2202 return "add%.l %1,%0";
2204 [(set_attr "type" "alu_l")])
2206 (define_insn "adddi3"
2207 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,d,d,d")
2208 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0")
2209 (match_operand:DI 2 "general_operand" "d,no>,d,a")))
2210 (clobber (match_scratch:SI 3 "=&d,&d,X,&d"))]
2213 if (DATA_REG_P (operands[0]))
2215 if (DATA_REG_P (operands[2]))
2216 return "add%.l %R2,%R0\;addx%.l %2,%0";
2217 else if (GET_CODE (operands[2]) == MEM
2218 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2219 return "move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0";
2225 if (GET_CODE (operands[2]) == REG)
2227 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2230 else if (CONSTANT_P (operands[2]))
2231 split_double (operands[2], &high, &low);
2234 low = adjust_address (operands[2], SImode, 4);
2238 operands[1] = low, operands[2] = high;
2239 xoperands[0] = operands[3];
2240 if (GET_CODE (operands[1]) == CONST_INT
2241 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2242 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2244 xoperands[1] = operands[2];
2246 output_asm_insn (output_move_simode (xoperands), xoperands);
2247 if (GET_CODE (operands[1]) == CONST_INT)
2249 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2250 return "addq%.l %1,%R0\;addx%.l %3,%0";
2251 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2253 operands[1] = GEN_INT (-INTVAL (operands[1]));
2254 return "subq%.l %1,%R0\;subx%.l %3,%0";
2257 return "add%.l %1,%R0\;addx%.l %3,%0";
2262 gcc_assert (GET_CODE (operands[0]) == MEM);
2264 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2266 operands[1] = gen_rtx_MEM (SImode,
2267 plus_constant (XEXP(operands[0], 0), -8));
2268 return "move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1";
2270 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2272 operands[1] = XEXP(operands[0], 0);
2273 return "add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1";
2277 operands[1] = adjust_address (operands[0], SImode, 4);
2278 return "add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0";
2283 (define_insn "addsi_lshrsi_31"
2284 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
2285 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
2290 operands[2] = operands[0];
2291 operands[3] = gen_label_rtx();
2292 if (GET_CODE (operands[0]) == MEM)
2294 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2295 operands[0] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2296 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2297 operands[2] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2299 output_asm_insn ("move%.l %1,%0", operands);
2300 output_asm_insn ("jpl %l3", operands);
2301 output_asm_insn ("addq%.l #1,%2", operands);
2302 (*targetm.asm_out.internal_label) (asm_out_file, "L",
2303 CODE_LABEL_NUMBER (operands[3]));
2307 (define_expand "addsi3"
2308 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2309 (plus:SI (match_operand:SI 1 "general_operand" "")
2310 (match_operand:SI 2 "general_src_operand" "")))]
2314 ;; Note that the middle two alternatives are near-duplicates
2315 ;; in order to handle insns generated by reload.
2316 ;; This is needed since they are not themselves reloaded,
2317 ;; so commutativity won't apply to them.
2318 (define_insn "*addsi3_internal"
2319 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,d,a")
2320 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0,0")
2321 (match_operand:SI 2 "general_src_operand" "dIKLT,rJK,a,mSrIKLT,mSrIKLs")))]
2325 "* return output_addsi3 (operands);")
2327 (define_insn_and_split "*addsi3_5200"
2328 [(set (match_operand:SI 0 "nonimmediate_operand" "=mr,mr,m,r, ?a,?a,?a,?a")
2329 (plus:SI (match_operand:SI 1 "general_operand" "%0, 0, 0,0, a, a, r, a")
2330 (match_operand:SI 2 "general_src_operand" " I, L, d,mrKi,Cj,r, a, J")))]
2333 switch (which_alternative)
2336 return "addq%.l %2,%0";
2339 operands[2] = GEN_INT (- INTVAL (operands[2]));
2340 return "subq%.l %2,%0";
2344 return "add%.l %2,%0";
2347 /* move%.l %2,%0\n\tadd%.l %1,%0 */
2351 return MOTOROLA ? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
2354 return MOTOROLA ? "lea (%2,%1.l),%0" : "lea %2@(0,%1:l),%0";
2357 return MOTOROLA ? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
2364 "&& reload_completed && (extract_constrain_insn_cached (insn), which_alternative == 4) && !operands_match_p (operands[0], operands[1])"
2368 (plus:SI (match_dup 0)
2371 [(set_attr "type" "aluq_l,aluq_l,alu_l,alu_l,*,lea,lea,lea")
2372 (set_attr "opy" "2,2,2,2,*,*,*,*")
2373 (set_attr "opy_type" "*,*,*,*,*,mem6,mem6,mem5")])
2376 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
2377 (plus:SI (match_operand:SI 1 "general_operand" "0")
2379 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2383 (define_insn "addhi3"
2384 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
2385 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2386 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2389 if (GET_CODE (operands[2]) == CONST_INT)
2391 /* If the constant would be a negative number when interpreted as
2392 HImode, make it negative. This is usually, but not always, done
2393 elsewhere in the compiler. First check for constants out of range,
2394 which could confuse us. */
2396 if (INTVAL (operands[2]) >= 32768)
2397 operands[2] = GEN_INT (INTVAL (operands[2]) - 65536);
2399 if (INTVAL (operands[2]) > 0
2400 && INTVAL (operands[2]) <= 8)
2401 return "addq%.w %2,%0";
2402 if (INTVAL (operands[2]) < 0
2403 && INTVAL (operands[2]) >= -8)
2405 operands[2] = GEN_INT (- INTVAL (operands[2]));
2406 return "subq%.w %2,%0";
2408 /* On the CPU32 it is faster to use two addqw instructions to
2409 add a small integer (8 < N <= 16) to a register.
2410 Likewise for subqw. */
2411 if (TUNE_CPU32 && REG_P (operands[0]))
2413 if (INTVAL (operands[2]) > 8
2414 && INTVAL (operands[2]) <= 16)
2416 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
2417 return "addq%.w #8,%0\;addq%.w %2,%0";
2419 if (INTVAL (operands[2]) < -8
2420 && INTVAL (operands[2]) >= -16)
2422 operands[2] = GEN_INT (- INTVAL (operands[2]) - 8);
2423 return "subq%.w #8,%0\;subq%.w %2,%0";
2426 if (ADDRESS_REG_P (operands[0]) && !TUNE_68040)
2427 return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
2429 return "add%.w %2,%0";
2432 ;; These insns must use MATCH_DUP instead of the more expected
2433 ;; use of a matching constraint because the "output" here is also
2434 ;; an input, so you can't use the matching constraint. That also means
2435 ;; that you can't use the "%", so you need patterns with the matched
2436 ;; operand in both positions.
2439 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2440 (plus:HI (match_dup 0)
2441 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2444 if (GET_CODE (operands[1]) == CONST_INT)
2446 /* If the constant would be a negative number when interpreted as
2447 HImode, make it negative. This is usually, but not always, done
2448 elsewhere in the compiler. First check for constants out of range,
2449 which could confuse us. */
2451 if (INTVAL (operands[1]) >= 32768)
2452 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2454 if (INTVAL (operands[1]) > 0
2455 && INTVAL (operands[1]) <= 8)
2456 return "addq%.w %1,%0";
2457 if (INTVAL (operands[1]) < 0
2458 && INTVAL (operands[1]) >= -8)
2460 operands[1] = GEN_INT (- INTVAL (operands[1]));
2461 return "subq%.w %1,%0";
2463 /* On the CPU32 it is faster to use two addqw instructions to
2464 add a small integer (8 < N <= 16) to a register.
2465 Likewise for subqw. */
2466 if (TUNE_CPU32 && REG_P (operands[0]))
2468 if (INTVAL (operands[1]) > 8
2469 && INTVAL (operands[1]) <= 16)
2471 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2472 return "addq%.w #8,%0\;addq%.w %1,%0";
2474 if (INTVAL (operands[1]) < -8
2475 && INTVAL (operands[1]) >= -16)
2477 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
2478 return "subq%.w #8,%0\;subq%.w %1,%0";
2481 if (ADDRESS_REG_P (operands[0]) && !TUNE_68040)
2482 return MOTOROLA ? "lea (%c1,%0),%0" : "lea %0@(%c1),%0";
2484 return "add%.w %1,%0";
2488 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2489 (plus:HI (match_operand:HI 1 "general_src_operand" "dn,rmSn")
2493 if (GET_CODE (operands[1]) == CONST_INT)
2495 /* If the constant would be a negative number when interpreted as
2496 HImode, make it negative. This is usually, but not always, done
2497 elsewhere in the compiler. First check for constants out of range,
2498 which could confuse us. */
2500 if (INTVAL (operands[1]) >= 32768)
2501 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2503 if (INTVAL (operands[1]) > 0
2504 && INTVAL (operands[1]) <= 8)
2505 return "addq%.w %1,%0";
2506 if (INTVAL (operands[1]) < 0
2507 && INTVAL (operands[1]) >= -8)
2509 operands[1] = GEN_INT (- INTVAL (operands[1]));
2510 return "subq%.w %1,%0";
2512 /* On the CPU32 it is faster to use two addqw instructions to
2513 add a small integer (8 < N <= 16) to a register.
2514 Likewise for subqw. */
2515 if (TUNE_CPU32 && REG_P (operands[0]))
2517 if (INTVAL (operands[1]) > 8
2518 && INTVAL (operands[1]) <= 16)
2520 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2521 return "addq%.w #8,%0\;addq%.w %1,%0";
2523 if (INTVAL (operands[1]) < -8
2524 && INTVAL (operands[1]) >= -16)
2526 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
2527 return "subq%.w #8,%0\;subq%.w %1,%0";
2530 if (ADDRESS_REG_P (operands[0]) && !TUNE_68040)
2531 return MOTOROLA ? "lea (%c1,%0),%0" : "lea %0@(%c1),%0";
2533 return "add%.w %1,%0";
2536 (define_insn "addqi3"
2537 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
2538 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2539 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2542 if (GET_CODE (operands[2]) == CONST_INT)
2544 if (INTVAL (operands[2]) >= 128)
2545 operands[2] = GEN_INT (INTVAL (operands[2]) - 256);
2547 if (INTVAL (operands[2]) > 0
2548 && INTVAL (operands[2]) <= 8)
2549 return "addq%.b %2,%0";
2550 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2552 operands[2] = GEN_INT (- INTVAL (operands[2]));
2553 return "subq%.b %2,%0";
2556 return "add%.b %2,%0";
2560 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2561 (plus:QI (match_dup 0)
2562 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2565 if (GET_CODE (operands[1]) == CONST_INT)
2567 if (INTVAL (operands[1]) >= 128)
2568 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2570 if (INTVAL (operands[1]) > 0
2571 && INTVAL (operands[1]) <= 8)
2572 return "addq%.b %1,%0";
2573 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2575 operands[1] = GEN_INT (- INTVAL (operands[1]));
2576 return "subq%.b %1,%0";
2579 return "add%.b %1,%0";
2583 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2584 (plus:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
2588 if (GET_CODE (operands[1]) == CONST_INT)
2590 if (INTVAL (operands[1]) >= 128)
2591 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2593 if (INTVAL (operands[1]) > 0
2594 && INTVAL (operands[1]) <= 8)
2595 return "addq%.b %1,%0";
2596 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2598 operands[1] = GEN_INT (- INTVAL (operands[1]));
2599 return "subq%.b %1,%0";
2602 return "add%.b %1,%0";
2605 (define_expand "add<mode>3"
2606 [(set (match_operand:FP 0 "nonimmediate_operand" "")
2607 (plus:FP (match_operand:FP 1 "general_operand" "")
2608 (match_operand:FP 2 "general_operand" "")))]
2612 (define_insn "add<mode>3_floatsi_68881"
2613 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2614 (plus:FP (float:FP (match_operand:SI 2 "general_operand" "dmi"))
2615 (match_operand:FP 1 "general_operand" "0")))]
2617 "f<FP:round>add%.l %2,%0"
2618 [(set_attr "type" "falu")
2619 (set_attr "opy" "2")])
2621 (define_insn "add<mode>3_floathi_68881"
2622 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2623 (plus:FP (float:FP (match_operand:HI 2 "general_operand" "dmn"))
2624 (match_operand:FP 1 "general_operand" "0")))]
2626 "f<FP:round>add%.w %2,%0"
2627 [(set_attr "type" "falu")
2628 (set_attr "opy" "2")])
2630 (define_insn "add<mode>3_floatqi_68881"
2631 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2632 (plus:FP (float:FP (match_operand:QI 2 "general_operand" "dmn"))
2633 (match_operand:FP 1 "general_operand" "0")))]
2635 "f<FP:round>add%.b %2,%0"
2636 [(set_attr "type" "falu")
2637 (set_attr "opy" "2")])
2639 (define_insn "add<mode>3_68881"
2640 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2641 (plus:FP (match_operand:FP 1 "general_operand" "%0")
2642 (match_operand:FP 2 "general_operand" "f<FP:dreg>m<FP:const>")))]
2645 if (FP_REG_P (operands[2]))
2646 return "f<FP:round>add%.x %2,%0";
2647 return "f<FP:round>add%.<FP:prec> %f2,%0";
2649 [(set_attr "type" "falu")
2650 (set_attr "opy" "2")])
2652 (define_insn "add<mode>3_cf"
2653 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2654 (plus:FP (match_operand:FP 1 "general_operand" "%0")
2655 (match_operand:FP 2 "general_operand" "f<FP:dreg><Q>U")))]
2656 "TARGET_COLDFIRE_FPU"
2658 if (FP_REG_P (operands[2]))
2659 return "f<FP:prec>add%.d %2,%0";
2660 return "f<FP:prec>add%.<FP:prec> %2,%0";
2662 [(set_attr "type" "falu")
2663 (set_attr "opy" "2")])
2665 ;; subtract instructions
2667 (define_insn "subdi_sexthishl32"
2668 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,a,*d,*d")
2669 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2670 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2672 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2676 if (ADDRESS_REG_P (operands[0]))
2677 return "sub%.w %2,%0";
2678 else if (ADDRESS_REG_P (operands[3]))
2679 return "move%.w %2,%3\;sub%.l %3,%0";
2681 return "move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0";
2684 (define_insn "subdi_dishl32"
2685 [(set (match_operand:DI 0 "nonimmediate_operand" "+ro")
2686 (minus:DI (match_dup 0)
2687 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2692 if (GET_CODE (operands[1]) == REG)
2693 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2695 operands[1] = adjust_address (operands[1], SImode, 4);
2696 return "sub%.l %1,%0";
2698 [(set_attr "type" "alu_l")])
2700 (define_insn "subdi3"
2701 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,d,d,d")
2702 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2703 (match_operand:DI 2 "general_operand" "d,no>,d,a")))
2704 (clobber (match_scratch:SI 3 "=&d,&d,X,&d"))]
2707 if (DATA_REG_P (operands[0]))
2709 if (DATA_REG_P (operands[2]))
2710 return "sub%.l %R2,%R0\;subx%.l %2,%0";
2711 else if (GET_CODE (operands[2]) == MEM
2712 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2714 return "move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0";
2721 if (GET_CODE (operands[2]) == REG)
2723 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2726 else if (CONSTANT_P (operands[2]))
2727 split_double (operands[2], &high, &low);
2730 low = adjust_address (operands[2], SImode, 4);
2734 operands[1] = low, operands[2] = high;
2735 xoperands[0] = operands[3];
2736 if (GET_CODE (operands[1]) == CONST_INT
2737 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2738 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2740 xoperands[1] = operands[2];
2742 output_asm_insn (output_move_simode (xoperands), xoperands);
2743 if (GET_CODE (operands[1]) == CONST_INT)
2745 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2746 return "subq%.l %1,%R0\;subx%.l %3,%0";
2747 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2749 operands[1] = GEN_INT (-INTVAL (operands[1]));
2750 return "addq%.l %1,%R0\;addx%.l %3,%0";
2753 return "sub%.l %1,%R0\;subx%.l %3,%0";
2758 gcc_assert (GET_CODE (operands[0]) == MEM);
2760 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2763 = gen_rtx_MEM (SImode, plus_constant (XEXP (operands[0], 0), -8));
2764 return "move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1";
2766 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2768 operands[1] = XEXP(operands[0], 0);
2769 return "sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1";
2773 operands[1] = adjust_address (operands[0], SImode, 4);
2774 return "sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0";
2779 (define_insn "subsi3"
2780 [(set (match_operand:SI 0 "nonimmediate_operand" "=mda,m,d,a")
2781 (minus:SI (match_operand:SI 1 "general_operand" "0,0,0,0")
2782 (match_operand:SI 2 "general_src_operand" "I,dT,mSrT,mSrs")))]
2789 [(set_attr "type" "aluq_l,alu_l,alu_l,alu_l")
2790 (set_attr "opy" "2")])
2793 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
2794 (minus:SI (match_operand:SI 1 "general_operand" "0")
2796 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2800 (define_insn "subhi3"
2801 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
2802 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2803 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2808 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2809 (minus:HI (match_dup 0)
2810 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2814 (define_insn "subqi3"
2815 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
2816 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2817 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2822 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2823 (minus:QI (match_dup 0)
2824 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2828 (define_expand "sub<mode>3"
2829 [(set (match_operand:FP 0 "nonimmediate_operand" "")
2830 (minus:FP (match_operand:FP 1 "general_operand" "")
2831 (match_operand:FP 2 "general_operand" "")))]
2835 (define_insn "sub<mode>3_floatsi_68881"
2836 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2837 (minus:FP (match_operand:FP 1 "general_operand" "0")
2838 (float:FP (match_operand:SI 2 "general_operand" "dmi"))))]
2840 "f<FP:round>sub%.l %2,%0"
2841 [(set_attr "type" "falu")
2842 (set_attr "opy" "2")])
2844 (define_insn "sub<mode>3_floathi_68881"
2845 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2846 (minus:FP (match_operand:FP 1 "general_operand" "0")
2847 (float:FP (match_operand:HI 2 "general_operand" "dmn"))))]
2849 "f<FP:round>sub%.w %2,%0"
2850 [(set_attr "type" "falu")
2851 (set_attr "opy" "2")])
2853 (define_insn "sub<mode>3_floatqi_68881"
2854 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2855 (minus:FP (match_operand:FP 1 "general_operand" "0")
2856 (float:FP (match_operand:QI 2 "general_operand" "dmn"))))]
2858 "f<FP:round>sub%.b %2,%0"
2859 [(set_attr "type" "falu")
2860 (set_attr "opy" "2")])
2862 (define_insn "sub<mode>3_68881"
2863 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2864 (minus:FP (match_operand:FP 1 "general_operand" "0")
2865 (match_operand:FP 2 "general_operand" "f<FP:dreg>m<FP:const>")))]
2868 if (FP_REG_P (operands[2]))
2869 return "f<FP:round>sub%.x %2,%0";
2870 return "f<FP:round>sub%.<FP:prec> %f2,%0";
2872 [(set_attr "type" "falu")
2873 (set_attr "opy" "2")])
2875 (define_insn "sub<mode>3_cf"
2876 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2877 (minus:FP (match_operand:FP 1 "general_operand" "0")
2878 (match_operand:FP 2 "general_operand" "f<FP:dreg><Q>U")))]
2879 "TARGET_COLDFIRE_FPU"
2881 if (FP_REG_P (operands[2]))
2882 return "f<FP:prec>sub%.d %2,%0";
2883 return "f<FP:prec>sub%.<FP:prec> %2,%0";
2885 [(set_attr "type" "falu")
2886 (set_attr "opy" "2")])
2888 ;; multiply instructions
2890 (define_insn "mulhi3"
2891 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
2892 (mult:HI (match_operand:HI 1 "general_operand" "%0")
2893 (match_operand:HI 2 "general_src_operand" "dmSn")))]
2896 return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0";
2898 [(set_attr "type" "mul_w")
2899 (set_attr "opy" "2")])
2901 (define_insn "mulhisi3"
2902 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2903 (mult:SI (sign_extend:SI
2904 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2906 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
2909 return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0";
2911 [(set_attr "type" "mul_w")
2912 (set_attr "opy" "2")])
2914 (define_insn "*mulhisisi3_s"
2915 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2916 (mult:SI (sign_extend:SI
2917 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2918 (match_operand:SI 2 "const_int_operand" "n")))]
2919 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
2921 return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0";
2923 [(set_attr "type" "mul_w")
2924 (set_attr "opy" "2")])
2926 (define_expand "mulsi3"
2927 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2928 (mult:SI (match_operand:SI 1 "general_operand" "")
2929 (match_operand:SI 2 "general_operand" "")))]
2930 "TARGET_68020 || TARGET_COLDFIRE"
2933 (define_insn "*mulsi3_68020"
2934 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2935 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2936 (match_operand:SI 2 "general_src_operand" "dmSTK")))]
2940 [(set_attr "type" "mul_l")
2941 (set_attr "opy" "2")])
2943 (define_insn "*mulsi3_cf"
2944 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2945 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2946 (match_operand:SI 2 "general_operand" "d<Q>")))]
2949 [(set_attr "type" "mul_l")
2950 (set_attr "opy" "2")])
2952 (define_insn "umulhisi3"
2953 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2954 (mult:SI (zero_extend:SI
2955 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2957 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
2960 return MOTOROLA ? "mulu%.w %2,%0" : "mulu %2,%0";
2962 [(set_attr "type" "mul_w")
2963 (set_attr "opy" "2")])
2965 (define_insn "*mulhisisi3_z"
2966 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2967 (mult:SI (zero_extend:SI
2968 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2969 (match_operand:SI 2 "const_int_operand" "n")))]
2970 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
2972 return MOTOROLA ? "mulu%.w %2,%0" : "mulu %2,%0";
2974 [(set_attr "type" "mul_w")
2975 (set_attr "opy" "2")])
2977 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
2978 ;; proper matching constraint. This is because the matching is between
2979 ;; the high-numbered word of the DImode operand[0] and operand[1].
2980 (define_expand "umulsidi3"
2982 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
2983 (mult:SI (match_operand:SI 1 "register_operand" "")
2984 (match_operand:SI 2 "register_operand" "")))
2985 (set (subreg:SI (match_dup 0) 0)
2986 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2987 (zero_extend:DI (match_dup 2)))
2988 (const_int 32))))])]
2989 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
2993 [(set (match_operand:SI 0 "register_operand" "=d")
2994 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2995 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2996 (set (match_operand:SI 3 "register_operand" "=d")
2997 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2998 (zero_extend:DI (match_dup 2)))
3000 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3003 ; Match immediate case. For 2.4 only match things < 2^31.
3004 ; It's tricky with larger values in these patterns since we need to match
3005 ; values between the two parallel multiplies, between a CONST_DOUBLE and
3008 [(set (match_operand:SI 0 "register_operand" "=d")
3009 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3010 (match_operand:SI 2 "const_int_operand" "n")))
3011 (set (match_operand:SI 3 "register_operand" "=d")
3012 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3015 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE
3016 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
3019 (define_expand "mulsidi3"
3021 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
3022 (mult:SI (match_operand:SI 1 "register_operand" "")
3023 (match_operand:SI 2 "register_operand" "")))
3024 (set (subreg:SI (match_dup 0) 0)
3025 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3026 (sign_extend:DI (match_dup 2)))
3027 (const_int 32))))])]
3028 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3032 [(set (match_operand:SI 0 "register_operand" "=d")
3033 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3034 (match_operand:SI 2 "nonimmediate_operand" "dm")))
3035 (set (match_operand:SI 3 "register_operand" "=d")
3036 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3037 (sign_extend:DI (match_dup 2)))
3039 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3043 [(set (match_operand:SI 0 "register_operand" "=d")
3044 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3045 (match_operand:SI 2 "const_int_operand" "n")))
3046 (set (match_operand:SI 3 "register_operand" "=d")
3047 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3050 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3053 (define_expand "umulsi3_highpart"
3055 [(set (match_operand:SI 0 "register_operand" "")
3058 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
3059 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
3061 (clobber (match_dup 3))])]
3062 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3064 operands[3] = gen_reg_rtx (SImode);
3066 if (GET_CODE (operands[2]) == CONST_INT)
3068 operands[2] = immed_double_const (INTVAL (operands[2]) & 0xffffffff,
3071 /* We have to adjust the operand order for the matching constraints. */
3072 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
3073 operands[1], operands[2]));
3079 [(set (match_operand:SI 0 "register_operand" "=d")
3082 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3083 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3085 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3086 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3089 (define_insn "const_umulsi3_highpart"
3090 [(set (match_operand:SI 0 "register_operand" "=d")
3093 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
3094 (match_operand:DI 3 "const_uint32_operand" "n"))
3096 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3097 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3100 (define_expand "smulsi3_highpart"
3102 [(set (match_operand:SI 0 "register_operand" "")
3105 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
3106 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
3108 (clobber (match_dup 3))])]
3109 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3111 operands[3] = gen_reg_rtx (SImode);
3112 if (GET_CODE (operands[2]) == CONST_INT)
3114 /* We have to adjust the operand order for the matching constraints. */
3115 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
3116 operands[1], operands[2]));
3122 [(set (match_operand:SI 0 "register_operand" "=d")
3125 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3126 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3128 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3129 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3132 (define_insn "const_smulsi3_highpart"
3133 [(set (match_operand:SI 0 "register_operand" "=d")
3136 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
3137 (match_operand:DI 3 "const_sint32_operand" "n"))
3139 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3140 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3143 (define_expand "mul<mode>3"
3144 [(set (match_operand:FP 0 "nonimmediate_operand" "")
3145 (mult:FP (match_operand:FP 1 "general_operand" "")
3146 (match_operand:FP 2 "general_operand" "")))]
3150 (define_insn "mul<mode>3_floatsi_68881"
3151 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3152 (mult:FP (float:FP (match_operand:SI 2 "general_operand" "dmi"))
3153 (match_operand:FP 1 "general_operand" "0")))]
3157 ? "f<FP:round>mul%.l %2,%0"
3158 : "f<FP:round_mul>mul%.l %2,%0";
3160 [(set_attr "type" "fmul")
3161 (set_attr "opy" "2")])
3163 (define_insn "mul<mode>3_floathi_68881"
3164 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3165 (mult:FP (float:FP (match_operand:HI 2 "general_operand" "dmn"))
3166 (match_operand:FP 1 "general_operand" "0")))]
3170 ? "f<FP:round>mul%.w %2,%0"
3171 : "f<FP:round_mul>mul%.w %2,%0";
3173 [(set_attr "type" "fmul")
3174 (set_attr "opy" "2")])
3176 (define_insn "mul<mode>3_floatqi_68881"
3177 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3178 (mult:FP (float:FP (match_operand:QI 2 "general_operand" "dmn"))
3179 (match_operand:FP 1 "general_operand" "0")))]
3183 ? "f<FP:round>mul%.b %2,%0"
3184 : "f<FP:round_mul>mul%.b %2,%0";
3186 [(set_attr "type" "fmul")
3187 (set_attr "opy" "2")])
3189 (define_insn "muldf_68881"
3190 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3191 (mult:DF (match_operand:DF 1 "general_operand" "%0")
3192 (match_operand:DF 2 "general_operand" "fmG")))]
3195 if (GET_CODE (operands[2]) == CONST_DOUBLE
3196 && floating_exact_log2 (operands[2]) && !TUNE_68040_60)
3198 int i = floating_exact_log2 (operands[2]);
3199 operands[2] = GEN_INT (i);
3200 return "fscale%.l %2,%0";
3202 if (REG_P (operands[2]))
3203 return "f%&mul%.x %2,%0";
3204 return "f%&mul%.d %f2,%0";
3207 (define_insn "mulsf_68881"
3208 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3209 (mult:SF (match_operand:SF 1 "general_operand" "%0")
3210 (match_operand:SF 2 "general_operand" "fdmF")))]
3213 if (FP_REG_P (operands[2]))
3214 return (TARGET_68040
3216 : "fsglmul%.x %2,%0");
3217 return (TARGET_68040
3219 : "fsglmul%.s %f2,%0");
3222 (define_insn "mulxf3_68881"
3223 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
3224 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
3225 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
3228 return "fmul%.x %f2,%0";
3231 (define_insn "fmul<mode>3_cf"
3232 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3233 (mult:FP (match_operand:FP 1 "general_operand" "%0")
3234 (match_operand:FP 2 "general_operand" "f<Q>U<FP:dreg>")))]
3235 "TARGET_COLDFIRE_FPU"
3237 if (FP_REG_P (operands[2]))
3238 return "f<FP:prec>mul%.d %2,%0";
3239 return "f<FP:prec>mul%.<FP:prec> %2,%0";
3241 [(set_attr "type" "fmul")
3242 (set_attr "opy" "2")])
3244 ;; divide instructions
3246 (define_expand "div<mode>3"
3247 [(set (match_operand:FP 0 "nonimmediate_operand" "")
3248 (div:FP (match_operand:FP 1 "general_operand" "")
3249 (match_operand:FP 2 "general_operand" "")))]
3253 (define_insn "div<mode>3_floatsi_68881"
3254 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3255 (div:FP (match_operand:FP 1 "general_operand" "0")
3256 (float:FP (match_operand:SI 2 "general_operand" "dmi"))))]
3260 ? "f<FP:round>div%.l %2,%0"
3261 : "f<FP:round_mul>div%.l %2,%0";
3264 (define_insn "div<mode>3_floathi_68881"
3265 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3266 (div:FP (match_operand:FP 1 "general_operand" "0")
3267 (float:FP (match_operand:HI 2 "general_operand" "dmn"))))]
3271 ? "f<FP:round>div%.w %2,%0"
3272 : "f<FP:round_mul>div%.w %2,%0";
3275 (define_insn "div<mode>3_floatqi_68881"
3276 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3277 (div:FP (match_operand:FP 1 "general_operand" "0")
3278 (float:FP (match_operand:QI 2 "general_operand" "dmn"))))]
3282 ? "f<FP:round>div%.b %2,%0"
3283 : "f<FP:round_mul>div%.b %2,%0";
3286 (define_insn "div<mode>3_68881"
3287 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3288 (div:FP (match_operand:FP 1 "general_operand" "0")
3289 (match_operand:FP 2 "general_operand" "f<FP:dreg>m<FP:const>")))]
3292 if (FP_REG_P (operands[2]))
3293 return (TARGET_68040
3294 ? "f<FP:round>div%.x %2,%0"
3295 : "f<FP:round_mul>div%.x %2,%0");
3296 return (TARGET_68040
3297 ? "f<FP:round>div%.<FP:prec> %f2,%0"
3298 : "f<FP:round_mul>div%.<FP:prec> %f2,%0");
3301 (define_insn "div<mode>3_cf"
3302 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3303 (div:FP (match_operand:FP 1 "general_operand" "0")
3304 (match_operand:FP 2 "general_operand" "f<Q>U<FP:dreg>")))]
3305 "TARGET_COLDFIRE_FPU"
3307 if (FP_REG_P (operands[2]))
3308 return "f<FP:prec>div%.d %2,%0";
3309 return "f<FP:prec>div%.<FP:prec> %2,%0";
3311 [(set_attr "type" "fdiv")
3312 (set_attr "opy" "2")])
3314 ;; Remainder instructions.
3316 (define_expand "divmodsi4"
3318 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3319 (div:SI (match_operand:SI 1 "general_operand" "")
3320 (match_operand:SI 2 "general_src_operand" "")))
3321 (set (match_operand:SI 3 "nonimmediate_operand" "")
3322 (mod:SI (match_dup 1) (match_dup 2)))])]
3323 "TARGET_68020 || TARGET_CF_HWDIV"
3327 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3328 (div:SI (match_operand:SI 1 "general_operand" "0")
3329 (match_operand:SI 2 "general_src_operand" "d<Q>U")))
3330 (set (match_operand:SI 3 "nonimmediate_operand" "=&d")
3331 (mod:SI (match_dup 1) (match_dup 2)))]
3334 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3335 return "divs%.l %2,%0";
3336 else if (find_reg_note (insn, REG_UNUSED, operands[0]))
3337 return "rems%.l %2,%3:%0";
3339 return "rems%.l %2,%3:%0\;divs%.l %2,%0";
3341 [(set_attr "type" "div_l")
3342 (set_attr "opy" "2")])
3345 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3346 (div:SI (match_operand:SI 1 "general_operand" "0")
3347 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3348 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3349 (mod:SI (match_dup 1) (match_dup 2)))]
3352 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3353 return "divs%.l %2,%0";
3355 return "divsl%.l %2,%3:%0";
3358 (define_expand "udivmodsi4"
3360 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3361 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3362 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3363 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3364 (umod:SI (match_dup 1) (match_dup 2)))])]
3365 "TARGET_68020 || TARGET_CF_HWDIV"
3369 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3370 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3371 (match_operand:SI 2 "general_src_operand" "d<Q>U")))
3372 (set (match_operand:SI 3 "nonimmediate_operand" "=&d")
3373 (umod:SI (match_dup 1) (match_dup 2)))]
3376 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3377 return "divu%.l %2,%0";
3378 else if (find_reg_note (insn, REG_UNUSED, operands[0]))
3379 return "remu%.l %2,%3:%0";
3381 return "remu%.l %2,%3:%0\;divu%.l %2,%0";
3383 [(set_attr "type" "div_l")
3384 (set_attr "opy" "2")])
3387 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3388 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3389 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3390 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3391 (umod:SI (match_dup 1) (match_dup 2)))]
3392 "TARGET_68020 && !TARGET_COLDFIRE"
3394 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3395 return "divu%.l %2,%0";
3397 return "divul%.l %2,%3:%0";
3400 (define_insn "divmodhi4"
3401 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
3402 (div:HI (match_operand:HI 1 "general_operand" "0")
3403 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3404 (set (match_operand:HI 3 "nonimmediate_operand" "=d")
3405 (mod:HI (match_dup 1) (match_dup 2)))]
3406 "!TARGET_COLDFIRE || TARGET_CF_HWDIV"
3408 output_asm_insn (MOTOROLA ?
3409 "ext%.l %0\;divs%.w %2,%0" :
3410 "extl %0\;divs %2,%0",
3412 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3415 return "move%.l %0,%3\;swap %3";
3421 (define_insn "udivmodhi4"
3422 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
3423 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3424 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3425 (set (match_operand:HI 3 "nonimmediate_operand" "=d")
3426 (umod:HI (match_dup 1) (match_dup 2)))]
3427 "!TARGET_COLDFIRE || TARGET_CF_HWDIV"
3429 if (ISA_HAS_MVS_MVZ)
3430 output_asm_insn (MOTOROLA ?
3431 "mvz%.w %0,%0\;divu%.w %2,%0" :
3432 "mvz%.w %0,%0\;divu %2,%0",
3435 output_asm_insn (MOTOROLA ?
3436 "and%.l #0xFFFF,%0\;divu%.w %2,%0" :
3437 "and%.l #0xFFFF,%0\;divu %2,%0",
3440 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3443 return "move%.l %0,%3\;swap %3";
3449 ;; logical-and instructions
3451 ;; "anddi3" is mainly here to help combine().
3452 (define_insn "anddi3"
3453 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3454 (and:DI (match_operand:DI 1 "general_operand" "%0,0")
3455 (match_operand:DI 2 "general_operand" "dn,don")))]
3459 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3460 if (CONSTANT_P (operands[2]))
3464 split_double (operands[2], &hi, &lo);
3466 switch (INTVAL (hi))
3469 output_asm_insn ("clr%.l %0", operands);
3477 xoperands[0] = operands[0];
3479 output_asm_insn (output_andsi3 (xoperands), xoperands);
3482 if (GET_CODE (operands[0]) == REG)
3483 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3485 operands[0] = adjust_address (operands[0], SImode, 4);
3486 switch (INTVAL (lo))
3489 output_asm_insn ("clr%.l %0", operands);
3497 xoperands[0] = operands[0];
3499 output_asm_insn (output_andsi3 (xoperands), xoperands);
3504 if (GET_CODE (operands[0]) != REG)
3506 operands[1] = adjust_address (operands[0], SImode, 4);
3507 return "and%.l %2,%0\;and%.l %R2,%1";
3509 if (GET_CODE (operands[2]) != REG)
3511 operands[1] = adjust_address (operands[2], SImode, 4);
3512 return "and%.l %2,%0\;and%.l %1,%R0";
3514 return "and%.l %2,%0\;and%.l %R2,%R0";
3517 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3518 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3519 ;; can't allocate pseudos into it.
3521 (define_expand "andsi3"
3522 [(set (match_operand:SI 0 "not_sp_operand" "")
3523 (and:SI (match_operand:SI 1 "general_operand" "")
3524 (match_operand:SI 2 "general_src_operand" "")))]
3528 ;; produced by split operations after reload finished
3529 (define_insn "*andsi3_split"
3530 [(set (match_operand:SI 0 "register_operand" "=d")
3531 (and:SI (match_operand:SI 1 "register_operand" "0")
3532 (match_operand:SI 2 "const_int_operand" "i")))]
3533 "reload_completed && !TARGET_COLDFIRE"
3535 return output_andsi3 (operands);
3538 (define_insn "andsi3_internal"
3539 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3540 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3541 (match_operand:SI 2 "general_src_operand" "dKT,dmSM")))]
3544 return output_andsi3 (operands);
3547 (define_insn "andsi3_5200"
3548 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3549 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3550 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3554 && DATA_REG_P (operands[0])
3555 && GET_CODE (operands[2]) == CONST_INT)
3557 if (INTVAL (operands[2]) == 0x000000ff)
3558 return "mvz%.b %0,%0";
3559 else if (INTVAL (operands[2]) == 0x0000ffff)
3560 return "mvz%.w %0,%0";
3562 return output_andsi3 (operands);
3565 (define_insn "andhi3"
3566 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
3567 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3568 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3573 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3574 (and:HI (match_dup 0)
3575 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3580 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3581 (and:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3586 (define_insn "andqi3"
3587 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
3588 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3589 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3594 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3595 (and:QI (match_dup 0)
3596 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3601 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3602 (and:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3607 ;; inclusive-or instructions
3609 (define_insn "iordi_zext"
3610 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3611 (ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn"))
3612 (match_operand:DI 2 "general_operand" "0,0")))]
3618 if (GET_CODE (operands[0]) == REG)
3619 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3621 operands[0] = adjust_address (operands[0], SImode, 4);
3622 if (GET_MODE (operands[1]) == SImode)
3623 return "or%.l %1,%0";
3624 byte_mode = (GET_MODE (operands[1]) == QImode);
3625 if (GET_CODE (operands[0]) == MEM)
3626 operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
3629 return "or%.b %1,%0";
3631 return "or%.w %1,%0";
3634 ;; "iordi3" is mainly here to help combine().
3635 (define_insn "iordi3"
3636 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3637 (ior:DI (match_operand:DI 1 "general_operand" "%0,0")
3638 (match_operand:DI 2 "general_operand" "dn,don")))]
3642 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3643 if (CONSTANT_P (operands[2]))
3647 split_double (operands[2], &hi, &lo);
3649 switch (INTVAL (hi))
3654 /* FIXME : a scratch register would be welcome here if operand[0]
3655 is not a register */
3656 output_asm_insn ("move%.l #-1,%0", operands);
3662 xoperands[0] = operands[0];
3664 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3667 if (GET_CODE (operands[0]) == REG)
3668 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3670 operands[0] = adjust_address (operands[0], SImode, 4);
3671 switch (INTVAL (lo))
3676 /* FIXME : a scratch register would be welcome here if operand[0]
3677 is not a register */
3678 output_asm_insn ("move%.l #-1,%0", operands);
3684 xoperands[0] = operands[0];
3686 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3691 if (GET_CODE (operands[0]) != REG)
3693 operands[1] = adjust_address (operands[0], SImode, 4);
3694 return "or%.l %2,%0\;or%.l %R2,%1";
3696 if (GET_CODE (operands[2]) != REG)
3698 operands[1] = adjust_address (operands[2], SImode, 4);
3699 return "or%.l %2,%0\;or%.l %1,%R0";
3701 return "or%.l %2,%0\;or%.l %R2,%R0";
3704 (define_expand "iorsi3"
3705 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3706 (ior:SI (match_operand:SI 1 "general_operand" "")
3707 (match_operand:SI 2 "general_src_operand" "")))]
3711 (define_insn "iorsi3_internal"
3712 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
3713 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3714 (match_operand:SI 2 "general_src_operand" "dKT,dmSMT")))]
3717 return output_iorsi3 (operands);
3720 (define_insn "iorsi3_5200"
3721 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
3722 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3723 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3726 return output_iorsi3 (operands);
3729 (define_insn "iorhi3"
3730 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
3731 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3732 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3737 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3738 (ior:HI (match_dup 0)
3739 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3744 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3745 (ior:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3750 (define_insn "iorqi3"
3751 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
3752 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3753 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3758 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3759 (ior:QI (match_dup 0)
3760 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3765 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3766 (ior:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3771 ;; On all 68k models, this makes faster code in a special case.
3772 ;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
3774 (define_insn "iorsi_zexthi_ashl16"
3775 [(set (match_operand:SI 0 "nonimmediate_operand" "=&d")
3776 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "rmn"))
3777 (ashift:SI (match_operand:SI 2 "general_operand" "or")
3782 if (GET_CODE (operands[2]) != REG)
3783 operands[2] = adjust_address (operands[2], HImode, 2);
3784 if (GET_CODE (operands[2]) != REG
3785 || REGNO (operands[2]) != REGNO (operands[0]))
3786 output_asm_insn ("move%.w %2,%0", operands);
3787 return "swap %0\;mov%.w %1,%0";
3790 (define_insn "iorsi_zext"
3791 [(set (match_operand:SI 0 "nonimmediate_operand" "=o,d")
3792 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3793 (match_operand:SI 2 "general_operand" "0,0")))]
3799 byte_mode = (GET_MODE (operands[1]) == QImode);
3800 if (GET_CODE (operands[0]) == MEM)
3801 operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
3804 return "or%.b %1,%0";
3806 return "or%.w %1,%0";
3811 ;; "xordi3" is mainly here to help combine().
3812 (define_insn "xordi3"
3813 [(set (match_operand:DI 0 "nonimmediate_operand" "=od")
3814 (xor:DI (match_operand:DI 1 "general_operand" "%0")
3815 (match_operand:DI 2 "general_operand" "dn")))]
3819 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3821 if (CONSTANT_P (operands[2]))
3825 split_double (operands[2], &hi, &lo);
3827 switch (INTVAL (hi))
3832 output_asm_insn ("not%.l %0", operands);
3835 /* FIXME : a scratch register would be welcome here if
3836 -128 <= INTVAL (hi) < -1 */
3840 xoperands[0] = operands[0];
3842 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3845 if (GET_CODE (operands[0]) == REG)
3846 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3848 operands[0] = adjust_address (operands[0], SImode, 4);
3849 switch (INTVAL (lo))
3854 output_asm_insn ("not%.l %0", operands);
3857 /* FIXME : a scratch register would be welcome here if
3858 -128 <= INTVAL (lo) < -1 */
3860 /* FIXME : this should be merged with xorsi3 */
3864 xoperands[0] = operands[0];
3866 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3871 if (GET_CODE (operands[0]) != REG)
3873 operands[1] = adjust_address (operands[0], SImode, 4);
3874 return "eor%.l %2,%0\;eor%.l %R2,%1";
3876 if (GET_CODE (operands[2]) != REG)
3878 operands[1] = adjust_address (operands[2], SImode, 4);
3879 return "eor%.l %2,%0\;eor%.l %1,%R0";
3881 return "eor%.l %2,%0\;eor%.l %R2,%R0";
3884 (define_expand "xorsi3"
3885 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3886 (xor:SI (match_operand:SI 1 "general_operand" "")
3887 (match_operand:SI 2 "general_operand" "")))]
3891 (define_insn "xorsi3_internal"
3892 [(set (match_operand:SI 0 "nonimmediate_operand" "=do,m")
3893 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3894 (match_operand:SI 2 "general_operand" "di,dKT")))]
3898 return output_xorsi3 (operands);
3901 (define_insn "xorsi3_5200"
3902 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm,d")
3903 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3904 (match_operand:SI 2 "general_operand" "d,Ks")))]
3907 return output_xorsi3 (operands);
3910 (define_insn "xorhi3"
3911 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
3912 (xor:HI (match_operand:HI 1 "general_operand" "%0")
3913 (match_operand:HI 2 "general_operand" "dn")))]
3918 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
3919 (xor:HI (match_dup 0)
3920 (match_operand:HI 1 "general_operand" "dn")))]
3925 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
3926 (xor:HI (match_operand:HI 1 "general_operand" "dn")
3931 (define_insn "xorqi3"
3932 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
3933 (xor:QI (match_operand:QI 1 "general_operand" "%0")
3934 (match_operand:QI 2 "general_operand" "dn")))]
3939 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
3940 (xor:QI (match_dup 0)
3941 (match_operand:QI 1 "general_operand" "dn")))]
3946 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
3947 (xor:QI (match_operand:QI 1 "general_operand" "dn")
3952 ;; negation instructions
3954 (define_expand "negdi2"
3955 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3956 (neg:DI (match_operand:DI 1 "general_operand" "")))]
3959 if (TARGET_COLDFIRE)
3960 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
3962 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
3966 (define_insn "negdi2_internal"
3967 [(set (match_operand:DI 0 "nonimmediate_operand" "=<,do,!*a")
3968 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
3971 if (which_alternative == 0)
3972 return "neg%.l %0\;negx%.l %0";
3973 if (GET_CODE (operands[0]) == REG)
3974 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3976 operands[1] = adjust_address (operands[0], SImode, 4);
3977 if (ADDRESS_REG_P (operands[0]))
3978 return "exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0";
3980 return "neg%.l %1\;negx%.l %0";
3983 (define_insn "negdi2_5200"
3984 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3985 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
3988 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3989 return "neg%.l %1\;negx%.l %0";
3992 (define_expand "negsi2"
3993 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3994 (neg:SI (match_operand:SI 1 "general_operand" "")))]
3997 if (TARGET_COLDFIRE)
3998 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
4000 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
4004 (define_insn "negsi2_internal"
4005 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
4006 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4009 [(set_attr "type" "neg_l")])
4011 (define_insn "negsi2_5200"
4012 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
4013 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4016 [(set_attr "type" "neg_l")])
4018 (define_insn "neghi2"
4019 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
4020 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
4025 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
4026 (neg:HI (match_dup 0)))]
4030 (define_insn "negqi2"
4031 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
4032 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
4037 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
4038 (neg:QI (match_dup 0)))]
4042 ;; If using software floating point, just flip the sign bit.
4044 (define_expand "negsf2"
4045 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4046 (neg:SF (match_operand:SF 1 "general_operand" "")))]
4049 if (!TARGET_HARD_FLOAT)
4054 target = operand_subword_force (operands[0], 0, SFmode);
4055 result = expand_binop (SImode, xor_optab,
4056 operand_subword_force (operands[1], 0, SFmode),
4057 GEN_INT (-2147483647 - 1), target, 0, OPTAB_WIDEN);
4058 gcc_assert (result);
4060 if (result != target)
4061 emit_move_insn (result, target);
4063 /* Make a place for REG_EQUAL. */
4064 emit_move_insn (operands[0], operands[0]);
4069 (define_expand "negdf2"
4070 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4071 (neg:DF (match_operand:DF 1 "general_operand" "")))]
4074 if (!TARGET_HARD_FLOAT)
4081 target = operand_subword (operands[0], 0, 1, DFmode);
4082 result = expand_binop (SImode, xor_optab,
4083 operand_subword_force (operands[1], 0, DFmode),
4084 GEN_INT (-2147483647 - 1), target, 0, OPTAB_WIDEN);
4085 gcc_assert (result);
4087 if (result != target)
4088 emit_move_insn (result, target);
4090 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4091 operand_subword_force (operands[1], 1, DFmode));
4093 insns = get_insns ();
4101 (define_expand "negxf2"
4102 [(set (match_operand:XF 0 "nonimmediate_operand" "")
4103 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
4113 target = operand_subword (operands[0], 0, 1, XFmode);
4114 result = expand_binop (SImode, xor_optab,
4115 operand_subword_force (operands[1], 0, XFmode),
4116 GEN_INT (-2147483647 - 1), target, 0, OPTAB_WIDEN);
4117 gcc_assert (result);
4119 if (result != target)
4120 emit_move_insn (result, target);
4122 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
4123 operand_subword_force (operands[1], 1, XFmode));
4124 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
4125 operand_subword_force (operands[1], 2, XFmode));
4127 insns = get_insns ();
4135 (define_insn "neg<mode>2_68881"
4136 [(set (match_operand:FP 0 "nonimmediate_operand" "=f,d")
4137 (neg:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m<FP:const>,0")))]
4140 if (DATA_REG_P (operands[0]))
4142 operands[1] = GEN_INT (31);
4143 return "bchg %1,%0";
4145 if (FP_REG_P (operands[1]))
4146 return "f<FP:round>neg%.x %1,%0";
4147 return "f<FP:round>neg%.<FP:prec> %f1,%0";
4150 (define_insn "neg<mode>2_cf"
4151 [(set (match_operand:FP 0 "nonimmediate_operand" "=f,d")
4152 (neg:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U,0")))]
4153 "TARGET_COLDFIRE_FPU"
4155 if (DATA_REG_P (operands[0]))
4157 operands[1] = GEN_INT (31);
4158 return "bchg %1,%0";
4160 if (FP_REG_P (operands[1]))
4161 return "f<FP:prec>neg%.d %1,%0";
4162 return "f<FP:prec>neg%.<FP:prec> %1,%0";
4165 ;; Sqrt instruction for the 68881
4167 (define_expand "sqrt<mode>2"
4168 [(set (match_operand:FP 0 "nonimmediate_operand" "")
4169 (sqrt:FP (match_operand:FP 1 "general_operand" "")))]
4173 (define_insn "sqrt<mode>2_68881"
4174 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
4175 (sqrt:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m")))]
4178 if (FP_REG_P (operands[1]))
4179 return "f<FP:round>sqrt%.x %1,%0";
4180 return "f<FP:round>sqrt%.<FP:prec> %1,%0";
4182 [(set_attr "type" "fsqrt")])
4184 (define_insn "sqrt<mode>2_cf"
4185 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
4186 (sqrt:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U")))]
4187 "TARGET_COLDFIRE_FPU"
4189 if (FP_REG_P (operands[1]))
4190 return "f<FP:prec>sqrt%.d %1,%0";
4191 return "f<FP:prec>sqrt%.<FP:prec> %1,%0";
4193 [(set_attr "type" "fsqrt")])
4194 ;; Absolute value instructions
4195 ;; If using software floating point, just zero the sign bit.
4197 (define_expand "abssf2"
4198 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4199 (abs:SF (match_operand:SF 1 "general_operand" "")))]
4202 if (!TARGET_HARD_FLOAT)
4207 target = operand_subword_force (operands[0], 0, SFmode);
4208 result = expand_binop (SImode, and_optab,
4209 operand_subword_force (operands[1], 0, SFmode),
4210 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
4211 gcc_assert (result);
4213 if (result != target)
4214 emit_move_insn (result, target);
4216 /* Make a place for REG_EQUAL. */
4217 emit_move_insn (operands[0], operands[0]);
4222 (define_expand "absdf2"
4223 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4224 (abs:DF (match_operand:DF 1 "general_operand" "")))]
4227 if (!TARGET_HARD_FLOAT)
4234 target = operand_subword (operands[0], 0, 1, DFmode);
4235 result = expand_binop (SImode, and_optab,
4236 operand_subword_force (operands[1], 0, DFmode),
4237 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
4238 gcc_assert (result);
4240 if (result != target)
4241 emit_move_insn (result, target);
4243 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4244 operand_subword_force (operands[1], 1, DFmode));
4246 insns = get_insns ();
4254 (define_expand "absxf2"
4255 [(set (match_operand:XF 0 "nonimmediate_operand" "")
4256 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
4266 target = operand_subword (operands[0], 0, 1, XFmode);
4267 result = expand_binop (SImode, and_optab,
4268 operand_subword_force (operands[1], 0, XFmode),
4269 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
4270 gcc_assert (result);
4272 if (result != target)
4273 emit_move_insn (result, target);
4275 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
4276 operand_subword_force (operands[1], 1, XFmode));
4277 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
4278 operand_subword_force (operands[1], 2, XFmode));
4280 insns = get_insns ();
4288 (define_insn "abs<mode>2_68881"
4289 [(set (match_operand:FP 0 "nonimmediate_operand" "=f,d")
4290 (abs:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m<FP:const>,0")))]
4293 if (DATA_REG_P (operands[0]))
4295 operands[1] = GEN_INT (31);
4296 return "bclr %1,%0";
4298 if (FP_REG_P (operands[1]))
4299 return "f<FP:round>abs%.x %1,%0";
4300 return "f<FP:round>abs%.<FP:prec> %f1,%0";
4303 (define_insn "abs<mode>2_cf"
4304 [(set (match_operand:FP 0 "nonimmediate_operand" "=f,d")
4305 (abs:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U,0")))]
4306 "TARGET_COLDFIRE_FPU"
4308 if (DATA_REG_P (operands[0]))
4310 operands[1] = GEN_INT (31);
4311 return "bclr %1,%0";
4313 if (FP_REG_P (operands[1]))
4314 return "f<FP:prec>abs%.d %1,%0";
4315 return "f<FP:prec>abs%.<FP:prec> %1,%0";
4317 [(set_attr "type" "bitrw,fneg")])
4319 ;; bit indexing instructions
4321 ;; ColdFire ff1 instruction implements clz.
4322 (define_insn "clzsi2"
4323 [(set (match_operand:SI 0 "register_operand" "=d")
4324 (clz:SI (match_operand:SI 1 "register_operand" "0")))]
4327 [(set_attr "type" "ext")])
4329 ;; one complement instructions
4331 ;; "one_cmpldi2" is mainly here to help combine().
4332 (define_insn "one_cmpldi2"
4333 [(set (match_operand:DI 0 "nonimmediate_operand" "=dm")
4334 (not:DI (match_operand:DI 1 "general_operand" "0")))]
4338 if (GET_CODE (operands[0]) == REG)
4339 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4340 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
4341 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4342 operands[1] = operands[0];
4344 operands[1] = adjust_address (operands[0], SImode, 4);
4345 return "not%.l %1\;not%.l %0";
4348 (define_expand "one_cmplsi2"
4349 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4350 (not:SI (match_operand:SI 1 "general_operand" "")))]
4353 if (TARGET_COLDFIRE)
4354 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
4356 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
4360 (define_insn "one_cmplsi2_internal"
4361 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
4362 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4366 (define_insn "one_cmplsi2_5200"
4367 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
4368 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4371 [(set_attr "type" "neg_l")])
4373 (define_insn "one_cmplhi2"
4374 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
4375 (not:HI (match_operand:HI 1 "general_operand" "0")))]
4380 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
4381 (not:HI (match_dup 0)))]
4385 (define_insn "one_cmplqi2"
4386 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
4387 (not:QI (match_operand:QI 1 "general_operand" "0")))]
4392 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
4393 (not:QI (match_dup 0)))]
4397 ;; arithmetic shift instructions
4398 ;; We don't need the shift memory by 1 bit instruction
4400 (define_insn "ashldi_extsi"
4401 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
4403 (match_operator:DI 2 "extend_operator"
4404 [(match_operand:SI 1 "general_operand" "rm")])
4409 if (GET_CODE (operands[0]) == REG)
4410 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4412 operands[2] = adjust_address (operands[0], SImode, 4);
4413 if (ADDRESS_REG_P (operands[0]))
4414 return "move%.l %1,%0\;sub%.l %2,%2";
4416 return "move%.l %1,%0\;clr%.l %2";
4419 (define_insn "ashldi_sexthi"
4420 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,a*d")
4421 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
4423 (clobber (match_scratch:SI 2 "=a,X"))]
4427 if (GET_CODE (operands[0]) == MEM)
4429 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4430 return "clr%.l %0\;move%.w %1,%2\;move%.l %2,%0";
4431 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4432 return "move%.w %1,%2\;move%.l %2,%0\;clr%.l %0";
4435 operands[3] = adjust_address (operands[0], SImode, 4);
4436 return "move%.w %1,%2\;move%.l %2,%0\;clr%.l %3";
4439 else if (DATA_REG_P (operands[0]))
4440 return "move%.w %1,%0\;ext%.l %0\;clr%.l %R0";
4442 return "move%.w %1,%0\;sub%.l %R0,%R0";
4445 (define_insn "*ashldi3_const1"
4446 [(set (match_operand:DI 0 "register_operand" "=d")
4447 (ashift:DI (match_operand:DI 1 "register_operand" "0")
4450 "add%.l %R0,%R0\;addx%.l %0,%0")
4453 [(set (match_operand:DI 0 "register_operand" "")
4454 (ashift:DI (match_operand:DI 1 "register_operand" "")
4456 "reload_completed && !TARGET_COLDFIRE"
4458 (ashift:DI (match_dup 1) (const_int 1)))
4460 (ashift:DI (match_dup 0) (const_int 1)))]
4464 [(set (match_operand:DI 0 "register_operand" "")
4465 (ashift:DI (match_operand:DI 1 "register_operand" "")
4467 "reload_completed && !TARGET_COLDFIRE"
4469 (ashift:DI (match_dup 1) (const_int 2)))
4471 (ashift:DI (match_dup 0) (const_int 1)))]
4475 [(set (match_operand:DI 0 "register_operand" "")
4476 (ashift:DI (match_operand:DI 1 "register_operand" "")
4478 "reload_completed && !TARGET_COLDFIRE"
4480 (rotate:SI (match_dup 2) (const_int 8)))
4482 (rotate:SI (match_dup 3) (const_int 8)))
4483 (set (strict_low_part (subreg:QI (match_dup 0) 3))
4484 (subreg:QI (match_dup 0) 7))
4485 (set (strict_low_part (subreg:QI (match_dup 0) 7))
4488 operands[2] = gen_highpart (SImode, operands[0]);
4489 operands[3] = gen_lowpart (SImode, operands[0]);
4493 [(set (match_operand:DI 0 "register_operand" "")
4494 (ashift:DI (match_operand:DI 1 "register_operand" "")
4496 "reload_completed && !TARGET_COLDFIRE"
4498 (rotate:SI (match_dup 2) (const_int 16)))
4500 (rotate:SI (match_dup 3) (const_int 16)))
4501 (set (strict_low_part (subreg:HI (match_dup 0) 2))
4502 (subreg:HI (match_dup 0) 6))
4503 (set (strict_low_part (subreg:HI (match_dup 0) 6))
4506 operands[2] = gen_highpart (SImode, operands[0]);
4507 operands[3] = gen_lowpart (SImode, operands[0]);
4511 [(set (match_operand:DI 0 "pre_dec_operand" "")
4512 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "")
4515 [(set (match_dup 0) (const_int 0))
4516 (set (match_dup 0) (match_dup 1))]
4518 operands[0] = adjust_address(operands[0], SImode, 0);
4519 operands[1] = gen_lowpart(SImode, operands[1]);
4523 [(set (match_operand:DI 0 "post_inc_operand" "")
4524 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "")
4527 [(set (match_dup 0) (match_dup 1))
4528 (set (match_dup 0) (const_int 0))]
4530 operands[0] = adjust_address(operands[0], SImode, 0);
4531 operands[1] = gen_lowpart(SImode, operands[1]);
4534 (define_insn_and_split "*ashldi3_const32"
4535 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro<>")
4536 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "ro")
4540 "&& reload_completed"
4541 [(set (match_dup 4) (match_dup 3))
4542 (set (match_dup 2) (const_int 0))]
4543 "split_di(operands, 2, operands + 2, operands + 4);")
4546 [(set (match_operand:DI 0 "register_operand" "")
4547 (ashift:DI (match_operand:DI 1 "register_operand" "")
4548 (match_operand 2 "const_int_operand" "")))]
4549 "reload_completed && !TARGET_COLDFIRE
4550 && INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 40"
4551 [(set (match_dup 4) (ashift:SI (match_dup 4) (match_dup 2)))
4552 (set (match_dup 3) (match_dup 4))
4553 (set (match_dup 4) (const_int 0))]
4555 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4556 operands[3] = gen_highpart (SImode, operands[0]);
4557 operands[4] = gen_lowpart (SImode, operands[0]);
4561 [(set (match_operand:DI 0 "register_operand" "")
4562 (ashift:DI (match_operand:DI 1 "register_operand" "")
4564 "reload_completed && !TARGET_COLDFIRE"
4565 [(set (match_dup 2) (match_dup 3))
4567 (rotate:SI (match_dup 2) (const_int 16)))
4568 (set (match_dup 3) (const_int 0))
4569 (set (strict_low_part (subreg:HI (match_dup 0) 2))
4572 operands[2] = gen_highpart (SImode, operands[0]);
4573 operands[3] = gen_lowpart (SImode, operands[0]);
4577 [(set (match_operand:DI 0 "register_operand" "")
4578 (ashift:DI (match_operand:DI 1 "register_operand" "")
4579 (match_operand 2 "const_int_operand" "")))]
4580 "reload_completed && !TARGET_COLDFIRE
4581 && INTVAL (operands[2]) > 40 && INTVAL (operands[2]) <= 63"
4582 [(set (match_dup 3) (match_dup 2))
4583 (set (match_dup 4) (ashift:SI (match_dup 4) (match_dup 3)))
4584 (set (match_dup 3) (match_dup 4))
4585 (set (match_dup 4) (const_int 0))]
4587 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4588 operands[3] = gen_highpart (SImode, operands[0]);
4589 operands[4] = gen_lowpart (SImode, operands[0]);
4592 (define_insn "*ashldi3"
4593 [(set (match_operand:DI 0 "register_operand" "=d")
4594 (ashift:DI (match_operand:DI 1 "register_operand" "0")
4595 (match_operand 2 "const_int_operand" "n")))]
4597 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4598 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4599 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))"
4602 (define_expand "ashldi3"
4603 [(set (match_operand:DI 0 "register_operand" "")
4604 (ashift:DI (match_operand:DI 1 "register_operand" "")
4605 (match_operand 2 "const_int_operand" "")))]
4608 /* ??? This is a named pattern like this is not allowed to FAIL based
4610 if (GET_CODE (operands[2]) != CONST_INT
4611 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4612 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4613 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4617 ;; On most 68k models, this makes faster code in a special case.
4619 (define_insn "ashlsi_16"
4620 [(set (match_operand:SI 0 "register_operand" "=d")
4621 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4626 return "swap %0\;clr%.w %0";
4629 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
4630 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
4632 ;; On the 68000, this makes faster code in a special case.
4634 (define_insn "ashlsi_17_24"
4635 [(set (match_operand:SI 0 "register_operand" "=d")
4636 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4637 (match_operand:SI 2 "const_int_operand" "n")))]
4639 && INTVAL (operands[2]) > 16
4640 && INTVAL (operands[2]) <= 24"
4644 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4645 return "lsl%.w %2,%0\;swap %0\;clr%.w %0";
4648 (define_insn "ashlsi3"
4649 [(set (match_operand:SI 0 "register_operand" "=d")
4650 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4651 (match_operand:SI 2 "general_operand" "dI")))]
4654 if (operands[2] == const1_rtx)
4656 cc_status.flags = CC_NO_OVERFLOW;
4657 return "add%.l %0,%0";
4659 return "lsl%.l %2,%0";
4662 (define_insn "ashlhi3"
4663 [(set (match_operand:HI 0 "register_operand" "=d")
4664 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4665 (match_operand:HI 2 "general_operand" "dI")))]
4670 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4671 (ashift:HI (match_dup 0)
4672 (match_operand:HI 1 "general_operand" "dI")))]
4676 (define_insn "ashlqi3"
4677 [(set (match_operand:QI 0 "register_operand" "=d")
4678 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4679 (match_operand:QI 2 "general_operand" "dI")))]
4684 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4685 (ashift:QI (match_dup 0)
4686 (match_operand:QI 1 "general_operand" "dI")))]
4690 ;; On most 68k models, this makes faster code in a special case.
4692 (define_insn "ashrsi_16"
4693 [(set (match_operand:SI 0 "register_operand" "=d")
4694 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4697 "swap %0\;ext%.l %0")
4699 ;; On the 68000, this makes faster code in a special case.
4702 [(set (match_operand:SI 0 "register_operand" "=d")
4703 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4704 (match_operand:SI 2 "const_int_operand" "n")))]
4706 && INTVAL (operands[2]) > 16
4707 && INTVAL (operands[2]) <= 24"
4709 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4710 return "swap %0\;asr%.w %2,%0\;ext%.l %0";
4713 (define_insn "subreghi1ashrdi_const32"
4714 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
4715 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4716 (const_int 32)) 6))]
4719 if (GET_CODE (operands[1]) != REG)
4720 operands[1] = adjust_address (operands[1], HImode, 2);
4721 return "move%.w %1,%0";
4723 [(set_attr "type" "move")])
4725 (define_insn "subregsi1ashrdi_const32"
4726 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4727 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4728 (const_int 32)) 4))]
4731 return "move%.l %1,%0";
4733 [(set_attr "type" "move_l")])
4735 (define_insn "*ashrdi3_const1"
4736 [(set (match_operand:DI 0 "register_operand" "=d")
4737 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
4741 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4742 return "asr%.l #1,%0\;roxr%.l #1,%1";
4746 [(set (match_operand:DI 0 "register_operand" "")
4747 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
4749 "reload_completed && !TARGET_COLDFIRE"
4751 (ashiftrt:DI (match_dup 1) (const_int 1)))
4753 (ashiftrt:DI (match_dup 0) (const_int 1)))]
4757 [(set (match_operand:DI 0 "register_operand" "")
4758 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
4760 "reload_completed && !TARGET_COLDFIRE"
4762 (ashiftrt:DI (match_dup 1) (const_int 2)))
4764 (ashiftrt:DI (match_dup 0) (const_int 1)))]
4768 [(set (match_operand:DI 0 "register_operand" "")
4769 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
4771 "reload_completed && !TARGET_COLDFIRE"
4772 [(set (strict_low_part (subreg:QI (match_dup 0) 7))
4773 (subreg:QI (match_dup 0) 3))
4775 (ashiftrt:SI (match_dup 2) (const_int 8)))
4777 (rotatert:SI (match_dup 3) (const_int 8)))]
4779 operands[2] = gen_highpart (SImode, operands[0]);
4780 operands[3] = gen_lowpart (SImode, operands[0]);
4784 [(set (match_operand:DI 0 "register_operand" "")
4785 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
4787 "reload_completed && !TARGET_COLDFIRE"
4788 [(set (strict_low_part (subreg:HI (match_dup 0) 6))
4789 (subreg:HI (match_dup 0) 2))
4791 (rotate:SI (match_dup 2) (const_int 16)))
4793 (rotate:SI (match_dup 3) (const_int 16)))
4795 (sign_extend:SI (subreg:HI (match_dup 2) 2)))]
4797 operands[2] = gen_highpart (SImode, operands[0]);
4798 operands[3] = gen_lowpart (SImode, operands[0]);
4801 (define_insn "*ashrdi_const32"
4802 [(set (match_operand:DI 0 "register_operand" "=d")
4803 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_src_operand" "ro")
4809 return "move%.l %1,%R0\;smi %0\;extb%.l %0";
4811 return "move%.l %1,%R0\;smi %0\;ext%.w %0\;ext%.l %0";
4814 (define_insn "*ashrdi_const32_mem"
4815 [(set (match_operand:DI 0 "memory_operand" "=o,<")
4816 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_src_operand" "ro,ro")
4818 (clobber (match_scratch:SI 2 "=d,d"))]
4822 operands[3] = adjust_address (operands[0], SImode,
4823 which_alternative == 0 ? 4 : 0);
4824 operands[0] = adjust_address (operands[0], SImode, 0);
4825 if (TARGET_68020 || TARGET_COLDFIRE)
4826 return "move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0";
4828 return "move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0";
4832 [(set (match_operand:DI 0 "register_operand" "")
4833 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
4835 "reload_completed && !TARGET_COLDFIRE"
4837 (ashiftrt:SI (match_dup 3) (const_int 31)))
4840 "split_di(operands, 1, operands + 2, operands + 3);")
4842 ;; The predicate below must be general_operand, because ashrdi3 allows that
4843 (define_insn "ashrdi_const"
4844 [(set (match_operand:DI 0 "register_operand" "=d")
4845 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
4846 (match_operand 2 "const_int_operand" "n")))]
4848 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4849 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4850 || INTVAL (operands[2]) == 31
4851 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))"
4853 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4855 if (INTVAL (operands[2]) == 48)
4856 return "swap %0\;ext%.l %0\;move%.l %0,%1\;smi %0\;ext%.w %0";
4857 if (INTVAL (operands[2]) == 31)
4858 return "add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0";
4859 if (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)
4861 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4862 output_asm_insn (INTVAL (operands[2]) <= 8 ? "asr%.l %2,%0" :
4863 "moveq %2,%1\;asr%.l %1,%0", operands);
4864 output_asm_insn ("mov%.l %0,%1\;smi %0", operands);
4865 return INTVAL (operands[2]) >= 15 ? "ext%.w %d0" :
4866 TARGET_68020 ? "extb%.l %0" : "ext%.w %0\;ext%.l %0";
4871 (define_expand "ashrdi3"
4872 [(set (match_operand:DI 0 "register_operand" "")
4873 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
4874 (match_operand 2 "const_int_operand" "")))]
4877 /* ??? This is a named pattern like this is not allowed to FAIL based
4879 if (GET_CODE (operands[2]) != CONST_INT
4880 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4881 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4882 && (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63)))
4886 ;; On all 68k models, this makes faster code in a special case.
4888 (define_insn "ashrsi_31"
4889 [(set (match_operand:SI 0 "register_operand" "=d")
4890 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4894 return "add%.l %0,%0\;subx%.l %0,%0";
4897 (define_insn "ashrsi3"
4898 [(set (match_operand:SI 0 "register_operand" "=d")
4899 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4900 (match_operand:SI 2 "general_operand" "dI")))]
4903 [(set_attr "type" "shift")
4904 (set_attr "opy" "2")])
4906 (define_insn "ashrhi3"
4907 [(set (match_operand:HI 0 "register_operand" "=d")
4908 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4909 (match_operand:HI 2 "general_operand" "dI")))]
4914 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4915 (ashiftrt:HI (match_dup 0)
4916 (match_operand:HI 1 "general_operand" "dI")))]
4920 (define_insn "ashrqi3"
4921 [(set (match_operand:QI 0 "register_operand" "=d")
4922 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4923 (match_operand:QI 2 "general_operand" "dI")))]
4928 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4929 (ashiftrt:QI (match_dup 0)
4930 (match_operand:QI 1 "general_operand" "dI")))]
4934 ;; logical shift instructions
4936 ;; commented out because of reload problems in 950612-1.c
4939 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4940 ;; (const_int 32)) 4))
4941 ;; (set (match_operand:SI 1 "nonimmediate_operand" "=dm")
4942 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
4943 ;; (const_int 32)) 4))]
4946 ;; return "move%.l %0,%1";
4951 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4952 ;; (const_int 32)) 0))
4953 ;; (set (match_operand:DI 1 "nonimmediate_operand" "=do")
4954 ;; (lshiftrt:DI (match_dup 0)
4955 ;; (const_int 32)))]
4958 ;; if (GET_CODE (operands[1]) == REG)
4959 ;; operands[2] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4961 ;; operands[2] = adjust_address (operands[1], SImode, 4);
4962 ;; return "move%.l %0,%2\;clr%.l %1";
4965 (define_insn "subreg1lshrdi_const32"
4966 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4967 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4968 (const_int 32)) 4))]
4971 [(set_attr "type" "move_l")])
4973 (define_insn "*lshrdi3_const1"
4974 [(set (match_operand:DI 0 "register_operand" "=d")
4975 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
4978 "lsr%.l #1,%0\;roxr%.l #1,%R0")
4981 [(set (match_operand:DI 0 "register_operand" "")
4982 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
4984 "reload_completed && !TARGET_COLDFIRE"
4986 (lshiftrt:DI (match_dup 1) (const_int 1)))
4988 (lshiftrt:DI (match_dup 0) (const_int 1)))]
4992 [(set (match_operand:DI 0 "register_operand" "")
4993 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
4995 "reload_completed && !TARGET_COLDFIRE"
4997 (lshiftrt:DI (match_dup 1) (const_int 2)))
4999 (lshiftrt:DI (match_dup 0) (const_int 1)))]
5003 [(set (match_operand:DI 0 "register_operand" "")
5004 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5006 "reload_completed && !TARGET_COLDFIRE"
5007 [(set (strict_low_part (subreg:QI (match_dup 0) 7))
5008 (subreg:QI (match_dup 0) 3))
5010 (lshiftrt:SI (match_dup 2) (const_int 8)))
5012 (rotatert:SI (match_dup 3) (const_int 8)))]
5014 operands[2] = gen_highpart (SImode, operands[0]);
5015 operands[3] = gen_lowpart (SImode, operands[0]);
5019 [(set (match_operand:DI 0 "register_operand" "")
5020 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5022 "reload_completed && !TARGET_COLDFIRE"
5023 [(set (strict_low_part (subreg:HI (match_dup 0) 6))
5024 (subreg:HI (match_dup 0) 2))
5025 (set (strict_low_part (subreg:HI (match_dup 0) 2))
5028 (rotate:SI (match_dup 3) (const_int 16)))
5030 (rotate:SI (match_dup 2) (const_int 16)))]
5032 operands[2] = gen_highpart (SImode, operands[0]);
5033 operands[3] = gen_lowpart (SImode, operands[0]);
5037 [(set (match_operand:DI 0 "pre_dec_operand" "")
5038 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "")
5041 [(set (match_dup 0) (match_dup 1))
5042 (set (match_dup 0) (const_int 0))]
5044 operands[0] = adjust_address(operands[0], SImode, 0);
5045 operands[1] = gen_highpart(SImode, operands[1]);
5049 [(set (match_operand:DI 0 "post_inc_operand" "")
5050 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "")
5053 [(set (match_dup 0) (const_int 0))
5054 (set (match_dup 0) (match_dup 1))]
5056 operands[0] = adjust_address(operands[0], SImode, 0);
5057 operands[1] = gen_highpart(SImode, operands[1]);
5061 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5062 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "")
5065 [(set (match_dup 2) (match_dup 5))
5066 (set (match_dup 4) (const_int 0))]
5067 "split_di(operands, 2, operands + 2, operands + 4);")
5069 (define_insn "*lshrdi_const32"
5070 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro<>")
5071 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
5077 [(set (match_operand:DI 0 "register_operand" "")
5078 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5079 (match_operand 2 "const_int_operand" "")))]
5080 "reload_completed && !TARGET_COLDFIRE
5081 && INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 40"
5082 [(set (match_dup 3) (lshiftrt:SI (match_dup 3) (match_dup 2)))
5083 (set (match_dup 4) (match_dup 3))
5084 (set (match_dup 3) (const_int 0))]
5086 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
5087 operands[3] = gen_highpart (SImode, operands[0]);
5088 operands[4] = gen_lowpart (SImode, operands[0]);
5092 [(set (match_operand:DI 0 "register_operand" "")
5093 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5096 [(set (match_dup 3) (match_dup 2))
5097 (set (strict_low_part (subreg:HI (match_dup 0) 6))
5099 (set (match_dup 2) (const_int 0))
5101 (rotate:SI (match_dup 3) (const_int 16)))]
5103 operands[2] = gen_highpart (SImode, operands[0]);
5104 operands[3] = gen_lowpart (SImode, operands[0]);
5108 [(set (match_operand:DI 0 "register_operand" "")
5109 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5110 (match_operand 2 "const_int_operand" "")))]
5111 "reload_completed && !TARGET_COLDFIRE
5112 && INTVAL (operands[2]) > 40 && INTVAL (operands[2]) <= 62"
5113 [(set (match_dup 4) (match_dup 2))
5114 (set (match_dup 3) (lshiftrt:SI (match_dup 3) (match_dup 4)))
5115 (set (match_dup 4) (match_dup 3))
5116 (set (match_dup 3) (const_int 0))]
5118 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
5119 operands[3] = gen_highpart (SImode, operands[0]);
5120 operands[4] = gen_lowpart (SImode, operands[0]);
5123 (define_insn "*lshrdi_const63"
5124 [(set (match_operand:DI 0 "register_operand" "=d")
5125 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
5128 "add%.l %0,%0\;clr%.l %0\;clr%.l %R1\;addx%.l %R1,%R1")
5130 (define_insn "*lshrdi3_const"
5131 [(set (match_operand:DI 0 "register_operand" "=d")
5132 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
5133 (match_operand 2 "const_int_operand" "n")))]
5135 && ((INTVAL (operands[2]) >= 2 && INTVAL (operands[2]) <= 3)
5136 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
5137 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
5140 (define_expand "lshrdi3"
5141 [(set (match_operand:DI 0 "register_operand" "")
5142 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5143 (match_operand 2 "const_int_operand" "")))]
5146 /* ??? This is a named pattern like this is not allowed to FAIL based
5148 if (GET_CODE (operands[2]) != CONST_INT
5149 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
5150 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
5151 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
5155 ;; On all 68k models, this makes faster code in a special case.
5157 (define_insn "lshrsi_31"
5158 [(set (match_operand:SI 0 "register_operand" "=d")
5159 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5163 return "add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0";
5166 ;; On most 68k models, this makes faster code in a special case.
5168 (define_insn "lshrsi_16"
5169 [(set (match_operand:SI 0 "register_operand" "=d")
5170 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5175 return "clr%.w %0\;swap %0";
5178 ;; On the 68000, this makes faster code in a special case.
5180 (define_insn "lshrsi_17_24"
5181 [(set (match_operand:SI 0 "register_operand" "=d")
5182 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5183 (match_operand:SI 2 "const_int_operand" "n")))]
5185 && INTVAL (operands[2]) > 16
5186 && INTVAL (operands[2]) <= 24"
5188 /* I think lsr%.w sets the CC properly. */
5189 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
5190 return "clr%.w %0\;swap %0\;lsr%.w %2,%0";
5193 (define_insn "lshrsi3"
5194 [(set (match_operand:SI 0 "register_operand" "=d")
5195 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5196 (match_operand:SI 2 "general_operand" "dI")))]
5199 [(set_attr "type" "shift")
5200 (set_attr "opy" "2")])
5202 (define_insn "lshrhi3"
5203 [(set (match_operand:HI 0 "register_operand" "=d")
5204 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
5205 (match_operand:HI 2 "general_operand" "dI")))]
5210 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5211 (lshiftrt:HI (match_dup 0)
5212 (match_operand:HI 1 "general_operand" "dI")))]
5216 (define_insn "lshrqi3"
5217 [(set (match_operand:QI 0 "register_operand" "=d")
5218 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
5219 (match_operand:QI 2 "general_operand" "dI")))]
5224 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5225 (lshiftrt:QI (match_dup 0)
5226 (match_operand:QI 1 "general_operand" "dI")))]
5230 ;; rotate instructions
5232 (define_insn "rotlsi3"
5233 [(set (match_operand:SI 0 "register_operand" "=d")
5234 (rotate:SI (match_operand:SI 1 "register_operand" "0")
5235 (match_operand:SI 2 "general_operand" "dINO")))]
5238 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
5240 else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
5242 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
5243 return "ror%.l %2,%0";
5246 return "rol%.l %2,%0";
5249 (define_insn "rotlhi3"
5250 [(set (match_operand:HI 0 "register_operand" "=d")
5251 (rotate:HI (match_operand:HI 1 "register_operand" "0")
5252 (match_operand:HI 2 "general_operand" "dIP")))]
5255 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
5257 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
5258 return "ror%.w %2,%0";
5261 return "rol%.w %2,%0";
5265 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5266 (rotate:HI (match_dup 0)
5267 (match_operand:HI 1 "general_operand" "dIP")))]
5270 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
5272 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
5273 return "ror%.w %2,%0";
5276 return "rol%.w %2,%0";
5279 (define_insn "rotlqi3"
5280 [(set (match_operand:QI 0 "register_operand" "=d")
5281 (rotate:QI (match_operand:QI 1 "register_operand" "0")
5282 (match_operand:QI 2 "general_operand" "dI")))]
5285 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
5287 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
5288 return "ror%.b %2,%0";
5291 return "rol%.b %2,%0";
5295 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5296 (rotate:QI (match_dup 0)
5297 (match_operand:QI 1 "general_operand" "dI")))]
5300 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
5302 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
5303 return "ror%.b %2,%0";
5306 return "rol%.b %2,%0";
5309 (define_insn "rotrsi3"
5310 [(set (match_operand:SI 0 "register_operand" "=d")
5311 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
5312 (match_operand:SI 2 "general_operand" "dI")))]
5316 (define_insn "rotrhi3"
5317 [(set (match_operand:HI 0 "register_operand" "=d")
5318 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
5319 (match_operand:HI 2 "general_operand" "dI")))]
5324 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5325 (rotatert:HI (match_dup 0)
5326 (match_operand:HI 1 "general_operand" "dI")))]
5330 (define_insn "rotrqi3"
5331 [(set (match_operand:QI 0 "register_operand" "=d")
5332 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
5333 (match_operand:QI 2 "general_operand" "dI")))]
5338 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5339 (rotatert:QI (match_dup 0)
5340 (match_operand:QI 1 "general_operand" "dI")))]
5345 ;; Bit set/clear in memory byte.
5347 ;; set bit, bit number is int
5348 (define_insn "bsetmemqi"
5349 [(set (match_operand:QI 0 "memory_operand" "+m")
5350 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5351 (match_operand:SI 1 "general_operand" "d")) 3)
5356 return "bset %1,%0";
5358 [(set_attr "type" "bitrw")])
5360 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
5361 (define_insn "*bsetmemqi_ext"
5362 [(set (match_operand:QI 0 "memory_operand" "+m")
5363 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5364 (match_operator:SI 2 "extend_operator"
5365 [(match_operand 1 "general_operand" "d")])) 3)
5370 return "bset %1,%0";
5372 [(set_attr "type" "bitrw")])
5374 ;; clear bit, bit number is int
5375 (define_insn "bclrmemqi"
5376 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5378 (minus:SI (const_int 7)
5379 (match_operand:SI 1 "general_operand" "d")))
5384 return "bclr %1,%0";
5386 [(set_attr "type" "bitrw")])
5388 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
5389 (define_insn "*bclrmemqi_ext"
5390 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5392 (minus:SI (const_int 7)
5393 (match_operator:SI 2 "extend_operator"
5394 [(match_operand 1 "general_operand" "d")])))
5399 return "bclr %1,%0";
5401 [(set_attr "type" "bitrw")])
5403 ;; Special cases of bit-field insns which we should
5404 ;; recognize in preference to the general case.
5405 ;; These handle aligned 8-bit and 16-bit fields,
5406 ;; which can usually be done with move instructions.
5409 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5410 ; alignment of structure members is specified.
5412 ; The move is allowed to be odd byte aligned, because that's still faster
5413 ; than an odd byte aligned bit-field instruction.
5416 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5418 (match_operand:SI 1 "const_int_operand" "n"))
5419 (match_operand:SI 2 "general_src_operand" "rmSi"))]
5420 "TARGET_68020 && TARGET_BITFIELD
5421 && (INTVAL (operands[1]) % 8) == 0
5422 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
5425 = adjust_address (operands[0], SImode, INTVAL (operands[1]) / 8);
5427 return "move%.l %2,%0";
5431 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
5432 (match_operand:SI 1 "const_int_operand" "n")
5433 (match_operand:SI 2 "const_int_operand" "n"))
5434 (match_operand:SI 3 "register_operand" "d"))]
5435 "TARGET_68020 && TARGET_BITFIELD
5436 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
5437 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
5438 && (GET_CODE (operands[0]) == REG
5439 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
5441 if (REG_P (operands[0]))
5443 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
5444 return "bfins %3,%0{%b2:%b1}";
5447 operands[0] = adjust_address (operands[0],
5448 INTVAL (operands[1]) == 8 ? QImode : HImode,
5449 INTVAL (operands[2]) / 8);
5451 if (GET_CODE (operands[3]) == MEM)
5452 operands[3] = adjust_address (operands[3],
5453 INTVAL (operands[1]) == 8 ? QImode : HImode,
5454 (32 - INTVAL (operands[1])) / 8);
5456 if (INTVAL (operands[1]) == 8)
5457 return "move%.b %3,%0";
5458 return "move%.w %3,%0";
5463 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5464 ; alignment of structure members is specified.
5466 ; The move is allowed to be odd byte aligned, because that's still faster
5467 ; than an odd byte aligned bit-field instruction.
5470 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5471 (zero_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
5473 (match_operand:SI 2 "const_int_operand" "n")))]
5474 "TARGET_68020 && TARGET_BITFIELD
5475 && (INTVAL (operands[2]) % 8) == 0
5476 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5479 = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8);
5481 return "move%.l %1,%0";
5485 [(set (match_operand:SI 0 "nonimmediate_operand" "=&d")
5486 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
5487 (match_operand:SI 2 "const_int_operand" "n")
5488 (match_operand:SI 3 "const_int_operand" "n")))]
5489 "TARGET_68020 && TARGET_BITFIELD
5490 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5491 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5492 && (GET_CODE (operands[1]) == REG
5493 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5495 cc_status.flags |= CC_NOT_NEGATIVE;
5496 if (REG_P (operands[1]))
5498 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5499 return "bfextu %1{%b3:%b2},%0";
5503 = adjust_address (operands[1], SImode, INTVAL (operands[3]) / 8);
5505 output_asm_insn ("clr%.l %0", operands);
5506 if (GET_CODE (operands[0]) == MEM)
5507 operands[0] = adjust_address (operands[0],
5508 INTVAL (operands[2]) == 8 ? QImode : HImode,
5509 (32 - INTVAL (operands[1])) / 8);
5511 if (INTVAL (operands[2]) == 8)
5512 return "move%.b %1,%0";
5513 return "move%.w %1,%0";
5517 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5518 ; alignment of structure members is specified.
5520 ; The move is allowed to be odd byte aligned, because that's still faster
5521 ; than an odd byte aligned bit-field instruction.
5524 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5525 (sign_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
5527 (match_operand:SI 2 "const_int_operand" "n")))]
5528 "TARGET_68020 && TARGET_BITFIELD
5529 && (INTVAL (operands[2]) % 8) == 0
5530 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5533 = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8);
5535 return "move%.l %1,%0";
5539 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5540 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
5541 (match_operand:SI 2 "const_int_operand" "n")
5542 (match_operand:SI 3 "const_int_operand" "n")))]
5543 "TARGET_68020 && TARGET_BITFIELD
5544 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5545 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5546 && (GET_CODE (operands[1]) == REG
5547 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5549 if (REG_P (operands[1]))
5551 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5552 return "bfexts %1{%b3:%b2},%0";
5556 = adjust_address (operands[1],
5557 INTVAL (operands[2]) == 8 ? QImode : HImode,
5558 INTVAL (operands[3]) / 8);
5560 if (INTVAL (operands[2]) == 8)
5561 return "move%.b %1,%0\;extb%.l %0";
5562 return "move%.w %1,%0\;ext%.l %0";
5565 ;; Bit-field instructions, general cases.
5566 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
5567 ;; so that its address is reloaded.
5569 (define_expand "extv"
5570 [(set (match_operand:SI 0 "register_operand" "")
5571 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
5572 (match_operand:SI 2 "const_int_operand" "")
5573 (match_operand:SI 3 "const_int_operand" "")))]
5574 "TARGET_68020 && TARGET_BITFIELD"
5578 [(set (match_operand:SI 0 "register_operand" "=d")
5579 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5580 (match_operand:SI 2 "nonmemory_operand" "dn")
5581 (match_operand:SI 3 "nonmemory_operand" "dn")))]
5582 "TARGET_68020 && TARGET_BITFIELD"
5583 "bfexts %1{%b3:%b2},%0")
5585 (define_expand "extzv"
5586 [(set (match_operand:SI 0 "register_operand" "")
5587 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
5588 (match_operand:SI 2 "const_int_operand" "")
5589 (match_operand:SI 3 "const_int_operand" "")))]
5590 "TARGET_68020 && TARGET_BITFIELD"
5594 [(set (match_operand:SI 0 "register_operand" "=d")
5595 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o")
5596 (match_operand:SI 2 "nonmemory_operand" "dn")
5597 (match_operand:SI 3 "nonmemory_operand" "dn")))]
5598 "TARGET_68020 && TARGET_BITFIELD"
5600 if (GET_CODE (operands[2]) == CONST_INT)
5602 if (INTVAL (operands[2]) != 32)
5603 cc_status.flags |= CC_NOT_NEGATIVE;
5609 return "bfextu %1{%b3:%b2},%0";
5613 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5614 (match_operand:SI 1 "nonmemory_operand" "dn")
5615 (match_operand:SI 2 "nonmemory_operand" "dn"))
5616 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
5617 (match_operand 3 "const_int_operand" "n")))]
5618 "TARGET_68020 && TARGET_BITFIELD
5619 && (INTVAL (operands[3]) == -1
5620 || (GET_CODE (operands[1]) == CONST_INT
5621 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
5624 return "bfchg %0{%b2:%b1}";
5628 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5629 (match_operand:SI 1 "nonmemory_operand" "dn")
5630 (match_operand:SI 2 "nonmemory_operand" "dn"))
5632 "TARGET_68020 && TARGET_BITFIELD"
5635 return "bfclr %0{%b2:%b1}";
5639 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5640 (match_operand:SI 1 "general_operand" "dn")
5641 (match_operand:SI 2 "general_operand" "dn"))
5643 "TARGET_68020 && TARGET_BITFIELD"
5646 return "bfset %0{%b2:%b1}";
5649 (define_expand "insv"
5650 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "")
5651 (match_operand:SI 1 "const_int_operand" "")
5652 (match_operand:SI 2 "const_int_operand" ""))
5653 (match_operand:SI 3 "register_operand" ""))]
5654 "TARGET_68020 && TARGET_BITFIELD"
5658 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5659 (match_operand:SI 1 "nonmemory_operand" "dn")
5660 (match_operand:SI 2 "nonmemory_operand" "dn"))
5661 (match_operand:SI 3 "register_operand" "d"))]
5662 "TARGET_68020 && TARGET_BITFIELD"
5663 "bfins %3,%0{%b2:%b1}")
5665 ;; Now recognize bit-field insns that operate on registers
5666 ;; (or at least were intended to do so).
5669 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5670 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5671 (match_operand:SI 2 "const_int_operand" "n")
5672 (match_operand:SI 3 "const_int_operand" "n")))]
5673 "TARGET_68020 && TARGET_BITFIELD"
5674 "bfexts %1{%b3:%b2},%0")
5677 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5678 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5679 (match_operand:SI 2 "const_int_operand" "n")
5680 (match_operand:SI 3 "const_int_operand" "n")))]
5681 "TARGET_68020 && TARGET_BITFIELD"
5683 if (GET_CODE (operands[2]) == CONST_INT)
5685 if (INTVAL (operands[2]) != 32)
5686 cc_status.flags |= CC_NOT_NEGATIVE;
5692 return "bfextu %1{%b3:%b2},%0";
5696 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5697 (match_operand:SI 1 "const_int_operand" "n")
5698 (match_operand:SI 2 "const_int_operand" "n"))
5700 "TARGET_68020 && TARGET_BITFIELD"
5703 return "bfclr %0{%b2:%b1}";
5707 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5708 (match_operand:SI 1 "const_int_operand" "n")
5709 (match_operand:SI 2 "const_int_operand" "n"))
5711 "TARGET_68020 && TARGET_BITFIELD"
5714 return "bfset %0{%b2:%b1}";
5718 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5719 (match_operand:SI 1 "const_int_operand" "n")
5720 (match_operand:SI 2 "const_int_operand" "n"))
5721 (match_operand:SI 3 "register_operand" "d"))]
5722 "TARGET_68020 && TARGET_BITFIELD"
5725 /* These special cases are now recognized by a specific pattern. */
5726 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5727 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5728 return "move%.w %3,%0";
5729 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5730 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
5731 return "move%.b %3,%0";
5733 return "bfins %3,%0{%b2:%b1}";
5736 ;; Special patterns for optimizing bit-field instructions.
5740 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5741 (match_operand:SI 1 "const_int_operand" "n")
5742 (match_operand:SI 2 "general_operand" "dn")))]
5743 "TARGET_68020 && TARGET_BITFIELD"
5745 if (operands[1] == const1_rtx
5746 && GET_CODE (operands[2]) == CONST_INT)
5748 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5749 return output_btst (operands,
5750 GEN_INT (width - INTVAL (operands[2])),
5751 operands[0], insn, 1000);
5752 /* Pass 1000 as SIGNPOS argument so that btst will
5753 not think we are testing the sign bit for an `and'
5754 and assume that nonzero implies a negative result. */
5756 if (INTVAL (operands[1]) != 32)
5757 cc_status.flags = CC_NOT_NEGATIVE;
5758 return "bftst %0{%b2:%b1}";
5762 ;;; now handle the register cases
5765 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5766 (match_operand:SI 1 "const_int_operand" "n")
5767 (match_operand:SI 2 "general_operand" "dn")))]
5768 "TARGET_68020 && TARGET_BITFIELD"
5770 if (operands[1] == const1_rtx
5771 && GET_CODE (operands[2]) == CONST_INT)
5773 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5774 return output_btst (operands, GEN_INT (width - INTVAL (operands[2])),
5775 operands[0], insn, 1000);
5776 /* Pass 1000 as SIGNPOS argument so that btst will
5777 not think we are testing the sign bit for an `and'
5778 and assume that nonzero implies a negative result. */
5780 if (INTVAL (operands[1]) != 32)
5781 cc_status.flags = CC_NOT_NEGATIVE;
5782 return "bftst %0{%b2:%b1}";
5785 (define_insn "scc0_di"
5786 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
5787 (match_operator 1 "valid_dbcc_comparison_p"
5788 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5791 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5794 (define_insn "scc0_di_5200"
5795 [(set (match_operand:QI 0 "nonimmediate_operand" "=d")
5796 (match_operator 1 "valid_dbcc_comparison_p"
5797 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5800 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5803 (define_insn "scc_di"
5804 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,dm")
5805 (match_operator 1 "valid_dbcc_comparison_p"
5806 [(match_operand:DI 2 "general_operand" "ro,r")
5807 (match_operand:DI 3 "general_operand" "r,ro")]))]
5810 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5813 (define_insn "scc_di_5200"
5814 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d")
5815 (match_operator 1 "valid_dbcc_comparison_p"
5816 [(match_operand:DI 2 "general_operand" "ro,r")
5817 (match_operand:DI 3 "general_operand" "r,ro")]))]
5820 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5823 ;; Note that operand 0 of an SCC insn is supported in the hardware as
5824 ;; memory, but we cannot allow it to be in memory in case the address
5825 ;; needs to be reloaded.
5827 (define_expand "seq"
5828 [(set (match_operand:QI 0 "register_operand" "")
5829 (eq:QI (cc0) (const_int 0)))]
5832 if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
5833 && m68k_last_compare_had_fp_operands)
5835 m68k_last_compare_had_fp_operands = 0;
5841 [(set (match_operand:QI 0 "register_operand" "=d")
5842 (eq:QI (cc0) (const_int 0)))]
5845 cc_status = cc_prev_status;
5846 OUTPUT_JUMP ("seq %0", "fseq %0", "seq %0");
5849 (define_expand "sne"
5850 [(set (match_operand:QI 0 "register_operand" "")
5851 (ne:QI (cc0) (const_int 0)))]
5854 if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
5855 && m68k_last_compare_had_fp_operands)
5857 m68k_last_compare_had_fp_operands = 0;
5863 [(set (match_operand:QI 0 "register_operand" "=d")
5864 (ne:QI (cc0) (const_int 0)))]
5867 cc_status = cc_prev_status;
5868 OUTPUT_JUMP ("sne %0", "fsne %0", "sne %0");
5871 (define_expand "sgt"
5872 [(set (match_operand:QI 0 "register_operand" "")
5873 (gt:QI (cc0) (const_int 0)))]
5876 if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
5877 && m68k_last_compare_had_fp_operands)
5879 m68k_last_compare_had_fp_operands = 0;
5885 [(set (match_operand:QI 0 "register_operand" "=d")
5886 (gt:QI (cc0) (const_int 0)))]
5889 cc_status = cc_prev_status;
5890 OUTPUT_JUMP ("sgt %0", "fsgt %0", 0);
5893 (define_expand "sgtu"
5894 [(set (match_operand:QI 0 "register_operand" "")
5895 (gtu:QI (cc0) (const_int 0)))]
5900 [(set (match_operand:QI 0 "register_operand" "=d")
5901 (gtu:QI (cc0) (const_int 0)))]
5904 cc_status = cc_prev_status;
5908 (define_expand "slt"
5909 [(set (match_operand:QI 0 "register_operand" "")
5910 (lt:QI (cc0) (const_int 0)))]
5913 if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
5914 && m68k_last_compare_had_fp_operands)
5916 m68k_last_compare_had_fp_operands = 0;
5922 [(set (match_operand:QI 0 "register_operand" "=d")
5923 (lt:QI (cc0) (const_int 0)))]
5926 cc_status = cc_prev_status;
5927 OUTPUT_JUMP ("slt %0", "fslt %0", "smi %0");
5930 (define_expand "sltu"
5931 [(set (match_operand:QI 0 "register_operand" "")
5932 (ltu:QI (cc0) (const_int 0)))]
5937 [(set (match_operand:QI 0 "register_operand" "=d")
5938 (ltu:QI (cc0) (const_int 0)))]
5941 cc_status = cc_prev_status;
5945 (define_expand "sge"
5946 [(set (match_operand:QI 0 "register_operand" "")
5947 (ge:QI (cc0) (const_int 0)))]
5950 if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
5951 && m68k_last_compare_had_fp_operands)
5953 m68k_last_compare_had_fp_operands = 0;
5959 [(set (match_operand:QI 0 "register_operand" "=d")
5960 (ge:QI (cc0) (const_int 0)))]
5963 cc_status = cc_prev_status;
5964 OUTPUT_JUMP ("sge %0", "fsge %0", "spl %0");
5967 (define_expand "sgeu"
5968 [(set (match_operand:QI 0 "register_operand" "")
5969 (geu:QI (cc0) (const_int 0)))]
5974 [(set (match_operand:QI 0 "register_operand" "=d")
5975 (geu:QI (cc0) (const_int 0)))]
5978 cc_status = cc_prev_status;
5981 [(set_attr "type" "scc")])
5983 (define_expand "sle"
5984 [(set (match_operand:QI 0 "register_operand" "")
5985 (le:QI (cc0) (const_int 0)))]
5988 if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
5989 && m68k_last_compare_had_fp_operands)
5991 m68k_last_compare_had_fp_operands = 0;
5997 [(set (match_operand:QI 0 "register_operand" "=d")
5998 (le:QI (cc0) (const_int 0)))]
6001 cc_status = cc_prev_status;
6002 OUTPUT_JUMP ("sle %0", "fsle %0", 0);
6005 (define_expand "sleu"
6006 [(set (match_operand:QI 0 "register_operand" "")
6007 (leu:QI (cc0) (const_int 0)))]
6012 [(set (match_operand:QI 0 "register_operand" "=d")
6013 (leu:QI (cc0) (const_int 0)))]
6016 cc_status = cc_prev_status;
6019 [(set_attr "type" "scc")])
6021 (define_expand "sordered"
6022 [(set (match_operand:QI 0 "register_operand" "")
6023 (ordered:QI (cc0) (const_int 0)))]
6024 "TARGET_68881 && !TUNE_68060"
6026 gcc_assert (m68k_last_compare_had_fp_operands);
6027 m68k_last_compare_had_fp_operands = 0;
6030 (define_insn "*sordered_1"
6031 [(set (match_operand:QI 0 "register_operand" "=d")
6032 (ordered:QI (cc0) (const_int 0)))]
6033 "TARGET_68881 && !TUNE_68060"
6035 cc_status = cc_prev_status;
6039 (define_expand "sunordered"
6040 [(set (match_operand:QI 0 "register_operand" "")
6041 (unordered:QI (cc0) (const_int 0)))]
6042 "TARGET_68881 && !TUNE_68060"
6044 gcc_assert (m68k_last_compare_had_fp_operands);
6045 m68k_last_compare_had_fp_operands = 0;
6048 (define_insn "*sunordered_1"
6049 [(set (match_operand:QI 0 "register_operand" "=d")
6050 (unordered:QI (cc0) (const_int 0)))]
6051 "TARGET_68881 && !TUNE_68060"
6053 cc_status = cc_prev_status;
6057 (define_expand "suneq"
6058 [(set (match_operand:QI 0 "register_operand" "")
6059 (uneq:QI (cc0) (const_int 0)))]
6060 "TARGET_68881 && !TUNE_68060"
6062 gcc_assert (m68k_last_compare_had_fp_operands);
6063 m68k_last_compare_had_fp_operands = 0;
6066 (define_insn "*suneq_1"
6067 [(set (match_operand:QI 0 "register_operand" "=d")
6068 (uneq:QI (cc0) (const_int 0)))]
6069 "TARGET_68881 && !TUNE_68060"
6071 cc_status = cc_prev_status;
6075 (define_expand "sunge"
6076 [(set (match_operand:QI 0 "register_operand" "")
6077 (unge:QI (cc0) (const_int 0)))]
6078 "TARGET_68881 && !TUNE_68060"
6080 gcc_assert (m68k_last_compare_had_fp_operands);
6081 m68k_last_compare_had_fp_operands = 0;
6084 (define_insn "*sunge_1"
6085 [(set (match_operand:QI 0 "register_operand" "=d")
6086 (unge:QI (cc0) (const_int 0)))]
6087 "TARGET_68881 && !TUNE_68060"
6089 cc_status = cc_prev_status;
6093 (define_expand "sungt"
6094 [(set (match_operand:QI 0 "register_operand" "")
6095 (ungt:QI (cc0) (const_int 0)))]
6096 "TARGET_68881 && !TUNE_68060"
6098 gcc_assert (m68k_last_compare_had_fp_operands);
6099 m68k_last_compare_had_fp_operands = 0;
6102 (define_insn "*sungt_1"
6103 [(set (match_operand:QI 0 "register_operand" "=d")
6104 (ungt:QI (cc0) (const_int 0)))]
6105 "TARGET_68881 && !TUNE_68060"
6107 cc_status = cc_prev_status;
6111 (define_expand "sunle"
6112 [(set (match_operand:QI 0 "register_operand" "")
6113 (unle:QI (cc0) (const_int 0)))]
6114 "TARGET_68881 && !TUNE_68060"
6116 gcc_assert (m68k_last_compare_had_fp_operands);
6117 m68k_last_compare_had_fp_operands = 0;
6120 (define_insn "*sunle_1"
6121 [(set (match_operand:QI 0 "register_operand" "=d")
6122 (unle:QI (cc0) (const_int 0)))]
6123 "TARGET_68881 && !TUNE_68060"
6125 cc_status = cc_prev_status;
6129 (define_expand "sunlt"
6130 [(set (match_operand:QI 0 "register_operand" "")
6131 (unlt:QI (cc0) (const_int 0)))]
6132 "TARGET_68881 && !TUNE_68060"
6134 gcc_assert (m68k_last_compare_had_fp_operands);
6135 m68k_last_compare_had_fp_operands = 0;
6138 (define_insn "*sunlt_1"
6139 [(set (match_operand:QI 0 "register_operand" "=d")
6140 (unlt:QI (cc0) (const_int 0)))]
6141 "TARGET_68881 && !TUNE_68060"
6143 cc_status = cc_prev_status;
6147 (define_expand "sltgt"
6148 [(set (match_operand:QI 0 "register_operand" "")
6149 (ltgt:QI (cc0) (const_int 0)))]
6150 "TARGET_68881 && !TUNE_68060"
6152 gcc_assert (m68k_last_compare_had_fp_operands);
6153 m68k_last_compare_had_fp_operands = 0;
6156 (define_insn "*sltgt_1"
6157 [(set (match_operand:QI 0 "register_operand" "=d")
6158 (ltgt:QI (cc0) (const_int 0)))]
6159 "TARGET_68881 && !TUNE_68060"
6161 cc_status = cc_prev_status;
6165 (define_insn "*fsogt_1"
6166 [(set (match_operand:QI 0 "register_operand" "=d")
6167 (not:QI (unle:QI (cc0) (const_int 0))))]
6168 "TARGET_68881 && !TUNE_68060"
6170 cc_status = cc_prev_status;
6174 (define_insn "*fsoge_1"
6175 [(set (match_operand:QI 0 "register_operand" "=d")
6176 (not:QI (unlt:QI (cc0) (const_int 0))))]
6177 "TARGET_68881 && !TUNE_68060"
6179 cc_status = cc_prev_status;
6183 (define_insn "*fsolt_1"
6184 [(set (match_operand:QI 0 "register_operand" "=d")
6185 (not:QI (unge:QI (cc0) (const_int 0))))]
6186 "TARGET_68881 && !TUNE_68060"
6188 cc_status = cc_prev_status;
6192 (define_insn "*fsole_1"
6193 [(set (match_operand:QI 0 "register_operand" "=d")
6194 (not:QI (ungt:QI (cc0) (const_int 0))))]
6195 "TARGET_68881 && !TUNE_68060"
6197 cc_status = cc_prev_status;
6201 ;; Basic conditional jump instructions.
6203 (define_insn "beq0_di"
6205 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
6207 (label_ref (match_operand 1 "" ","))
6209 (clobber (match_scratch:SI 2 "=d,d"))]
6213 if (which_alternative == 1)
6214 return "move%.l %0,%2\;or%.l %0,%2\;jeq %l1";
6215 if ((cc_prev_status.value1
6216 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6217 || (cc_prev_status.value2
6218 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6220 cc_status = cc_prev_status;
6223 if (GET_CODE (operands[0]) == REG)
6224 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
6226 operands[3] = adjust_address (operands[0], SImode, 4);
6227 if (! ADDRESS_REG_P (operands[0]))
6229 if (reg_overlap_mentioned_p (operands[2], operands[0]))
6231 if (reg_overlap_mentioned_p (operands[2], operands[3]))
6232 return "or%.l %0,%2\;jeq %l1";
6234 return "or%.l %3,%2\;jeq %l1";
6236 return "move%.l %0,%2\;or%.l %3,%2\;jeq %l1";
6238 operands[4] = gen_label_rtx();
6239 if (TARGET_68020 || TARGET_COLDFIRE)
6240 output_asm_insn ("tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1", operands);
6242 output_asm_insn ("cmp%.w #0,%0\;jne %l4\;cmp%.w #0,%3\;jeq %l1", operands);
6243 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6244 CODE_LABEL_NUMBER (operands[4]));
6248 (define_insn "bne0_di"
6250 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
6252 (label_ref (match_operand 1 "" ","))
6254 (clobber (match_scratch:SI 2 "=d,X"))]
6257 if ((cc_prev_status.value1
6258 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6259 || (cc_prev_status.value2
6260 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6262 cc_status = cc_prev_status;
6266 if (GET_CODE (operands[0]) == REG)
6267 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
6269 operands[3] = adjust_address (operands[0], SImode, 4);
6270 if (!ADDRESS_REG_P (operands[0]))
6272 if (reg_overlap_mentioned_p (operands[2], operands[0]))
6274 if (reg_overlap_mentioned_p (operands[2], operands[3]))
6275 return "or%.l %0,%2\;jne %l1";
6277 return "or%.l %3,%2\;jne %l1";
6279 return "move%.l %0,%2\;or%.l %3,%2\;jne %l1";
6281 if (TARGET_68020 || TARGET_COLDFIRE)
6282 return "tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1";
6284 return "cmp%.w #0,%0\;jne %l1\;cmp%.w #0,%3\;jne %l1";
6287 (define_insn "bge0_di"
6289 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
6291 (label_ref (match_operand 1 "" ""))
6295 if ((cc_prev_status.value1
6296 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6297 || (cc_prev_status.value2
6298 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6300 cc_status = cc_prev_status;
6301 return cc_status.flags & CC_REVERSED ? "jle %l1" : "jpl %l1";
6304 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
6305 output_asm_insn("tst%.l %0", operands);
6308 /* On an address reg, cmpw may replace cmpl. */
6309 output_asm_insn("cmp%.w #0,%0", operands);
6314 (define_insn "blt0_di"
6316 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
6318 (label_ref (match_operand 1 "" ""))
6322 if ((cc_prev_status.value1
6323 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6324 || (cc_prev_status.value2
6325 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6327 cc_status = cc_prev_status;
6328 return cc_status.flags & CC_REVERSED ? "jgt %l1" : "jmi %l1";
6331 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
6332 output_asm_insn("tst%.l %0", operands);
6335 /* On an address reg, cmpw may replace cmpl. */
6336 output_asm_insn("cmp%.w #0,%0", operands);
6343 (if_then_else (eq (cc0)
6345 (label_ref (match_operand 0 "" ""))
6349 OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0");
6351 [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))])
6355 (if_then_else (ne (cc0)
6357 (label_ref (match_operand 0 "" ""))
6361 OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0");
6363 [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))])
6367 (if_then_else (gt (cc0)
6369 (label_ref (match_operand 0 "" ""))
6373 OUTPUT_JUMP ("jgt %l0", "fjgt %l0", 0);
6375 [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))])
6379 (if_then_else (gtu (cc0)
6381 (label_ref (match_operand 0 "" ""))
6385 [(set_attr "type" "bcc")])
6389 (if_then_else (lt (cc0)
6391 (label_ref (match_operand 0 "" ""))
6395 OUTPUT_JUMP ("jlt %l0", "fjlt %l0", "jmi %l0");
6397 [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))])
6401 (if_then_else (ltu (cc0)
6403 (label_ref (match_operand 0 "" ""))
6407 [(set_attr "type" "bcc")])
6411 (if_then_else (ge (cc0)
6413 (label_ref (match_operand 0 "" ""))
6417 OUTPUT_JUMP ("jge %l0", "fjge %l0", "jpl %l0");
6422 (if_then_else (geu (cc0)
6424 (label_ref (match_operand 0 "" ""))
6428 [(set_attr "type" "bcc")])
6432 (if_then_else (le (cc0)
6434 (label_ref (match_operand 0 "" ""))
6438 OUTPUT_JUMP ("jle %l0", "fjle %l0", 0);
6440 [(set_attr "type" "bcc")])
6444 (if_then_else (leu (cc0)
6446 (label_ref (match_operand 0 "" ""))
6450 [(set_attr "type" "bcc")])
6452 (define_insn "bordered"
6454 (if_then_else (ordered (cc0) (const_int 0))
6455 (label_ref (match_operand 0 "" ""))
6459 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6462 [(set_attr "type" "fbcc")])
6464 (define_insn "bunordered"
6466 (if_then_else (unordered (cc0) (const_int 0))
6467 (label_ref (match_operand 0 "" ""))
6471 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6474 [(set_attr "type" "fbcc")])
6476 (define_insn "buneq"
6478 (if_then_else (uneq (cc0) (const_int 0))
6479 (label_ref (match_operand 0 "" ""))
6483 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6486 [(set_attr "type" "fbcc")])
6488 (define_insn "bunge"
6490 (if_then_else (unge (cc0) (const_int 0))
6491 (label_ref (match_operand 0 "" ""))
6495 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6498 [(set_attr "type" "fbcc")])
6500 (define_insn "bungt"
6502 (if_then_else (ungt (cc0) (const_int 0))
6503 (label_ref (match_operand 0 "" ""))
6507 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6510 [(set_attr "type" "fbcc")])
6512 (define_insn "bunle"
6514 (if_then_else (unle (cc0) (const_int 0))
6515 (label_ref (match_operand 0 "" ""))
6519 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6522 [(set_attr "type" "fbcc")])
6524 (define_insn "bunlt"
6526 (if_then_else (unlt (cc0) (const_int 0))
6527 (label_ref (match_operand 0 "" ""))
6531 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6534 [(set_attr "type" "fbcc")])
6536 (define_insn "bltgt"
6538 (if_then_else (ltgt (cc0) (const_int 0))
6539 (label_ref (match_operand 0 "" ""))
6543 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6546 [(set_attr "type" "fbcc")])
6548 ;; Negated conditional jump instructions.
6550 (define_insn "*beq_rev"
6552 (if_then_else (eq (cc0)
6555 (label_ref (match_operand 0 "" ""))))]
6558 OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0");
6560 [(set_attr "type" "bcc")])
6562 (define_insn "*bne_rev"
6564 (if_then_else (ne (cc0)
6567 (label_ref (match_operand 0 "" ""))))]
6570 OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0");
6572 [(set_attr "type" "bcc")])
6574 (define_insn "*bgt_rev"
6576 (if_then_else (gt (cc0)
6579 (label_ref (match_operand 0 "" ""))))]
6582 OUTPUT_JUMP ("jle %l0", "fjngt %l0", 0);
6584 [(set_attr "type" "bcc")])
6586 (define_insn "*bgtu_rev"
6588 (if_then_else (gtu (cc0)
6591 (label_ref (match_operand 0 "" ""))))]
6594 [(set_attr "type" "bcc")])
6596 (define_insn "*blt_rev"
6598 (if_then_else (lt (cc0)
6601 (label_ref (match_operand 0 "" ""))))]
6604 OUTPUT_JUMP ("jge %l0", "fjnlt %l0", "jpl %l0");
6606 [(set_attr "type" "bcc")])
6608 (define_insn "*bltu_rev"
6610 (if_then_else (ltu (cc0)
6613 (label_ref (match_operand 0 "" ""))))]
6616 [(set_attr "type" "bcc")])
6618 (define_insn "*bge_rev"
6620 (if_then_else (ge (cc0)
6623 (label_ref (match_operand 0 "" ""))))]
6626 OUTPUT_JUMP ("jlt %l0", "fjnge %l0", "jmi %l0");
6628 [(set_attr "type" "bcc")])
6630 (define_insn "*bgeu_rev"
6632 (if_then_else (geu (cc0)
6635 (label_ref (match_operand 0 "" ""))))]
6638 [(set_attr "type" "bcc")])
6640 (define_insn "*ble_rev"
6642 (if_then_else (le (cc0)
6645 (label_ref (match_operand 0 "" ""))))]
6648 OUTPUT_JUMP ("jgt %l0", "fjnle %l0", 0);
6650 [(set_attr "type" "bcc")])
6652 (define_insn "*bleu_rev"
6654 (if_then_else (leu (cc0)
6657 (label_ref (match_operand 0 "" ""))))]
6660 [(set_attr "type" "bcc")])
6662 (define_insn "*bordered_rev"
6664 (if_then_else (ordered (cc0) (const_int 0))
6666 (label_ref (match_operand 0 "" ""))))]
6669 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6672 [(set_attr "type" "fbcc")])
6674 (define_insn "*bunordered_rev"
6676 (if_then_else (unordered (cc0) (const_int 0))
6678 (label_ref (match_operand 0 "" ""))))]
6681 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6684 [(set_attr "type" "fbcc")])
6686 (define_insn "*buneq_rev"
6688 (if_then_else (uneq (cc0) (const_int 0))
6690 (label_ref (match_operand 0 "" ""))))]
6693 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6696 [(set_attr "type" "fbcc")])
6698 (define_insn "*bunge_rev"
6700 (if_then_else (unge (cc0) (const_int 0))
6702 (label_ref (match_operand 0 "" ""))))]
6705 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6708 [(set_attr "type" "fbcc")])
6710 (define_insn "*bungt_rev"
6712 (if_then_else (ungt (cc0) (const_int 0))
6714 (label_ref (match_operand 0 "" ""))))]
6717 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6720 [(set_attr "type" "fbcc")])
6722 (define_insn "*bunle_rev"
6724 (if_then_else (unle (cc0) (const_int 0))
6726 (label_ref (match_operand 0 "" ""))))]
6729 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6732 [(set_attr "type" "fbcc")])
6734 (define_insn "*bunlt_rev"
6736 (if_then_else (unlt (cc0) (const_int 0))
6738 (label_ref (match_operand 0 "" ""))))]
6741 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6744 [(set_attr "type" "fbcc")])
6746 (define_insn "*bltgt_rev"
6748 (if_then_else (ltgt (cc0) (const_int 0))
6750 (label_ref (match_operand 0 "" ""))))]
6753 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6756 [(set_attr "type" "fbcc")])
6758 ;; Unconditional and other jump instructions
6761 (label_ref (match_operand 0 "" "")))]
6764 [(set_attr "type" "bra")])
6766 (define_expand "tablejump"
6767 [(parallel [(set (pc) (match_operand 0 "" ""))
6768 (use (label_ref (match_operand 1 "" "")))])]
6771 #ifdef CASE_VECTOR_PC_RELATIVE
6772 operands[0] = gen_rtx_PLUS (SImode, pc_rtx,
6773 gen_rtx_SIGN_EXTEND (SImode, operands[0]));
6777 ;; Jump to variable address from dispatch table of absolute addresses.
6778 (define_insn "*tablejump_internal"
6779 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
6780 (use (label_ref (match_operand 1 "" "")))]
6783 return MOTOROLA ? "jmp (%0)" : "jmp %0@";
6785 [(set_attr "type" "jmp")])
6787 ;; Jump to variable address from dispatch table of relative addresses.
6791 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
6792 (use (label_ref (match_operand 1 "" "")))]
6795 #ifdef ASM_RETURN_CASE_JUMP
6796 ASM_RETURN_CASE_JUMP;
6798 if (TARGET_COLDFIRE)
6800 if (ADDRESS_REG_P (operands[0]))
6801 return MOTOROLA ? "jmp (2,pc,%0.l)" : "jmp pc@(2,%0:l)";
6803 return "ext%.l %0\;jmp (2,pc,%0.l)";
6805 return "extl %0\;jmp pc@(2,%0:l)";
6808 return MOTOROLA ? "jmp (2,pc,%0.w)" : "jmp pc@(2,%0:w)";
6812 ;; Decrement-and-branch insns.
6813 (define_insn "*dbne_hi"
6816 (ne (match_operand:HI 0 "nonimmediate_operand" "+d*g")
6818 (label_ref (match_operand 1 "" ""))
6821 (plus:HI (match_dup 0)
6826 if (DATA_REG_P (operands[0]))
6827 return "dbra %0,%l1";
6828 if (GET_CODE (operands[0]) == MEM)
6829 return "subq%.w #1,%0\;jcc %l1";
6830 return "subq%.w #1,%0\;cmp%.w #-1,%0\;jne %l1";
6833 (define_insn "*dbne_si"
6836 (ne (match_operand:SI 0 "nonimmediate_operand" "+d*g")
6838 (label_ref (match_operand 1 "" ""))
6841 (plus:SI (match_dup 0)
6846 if (DATA_REG_P (operands[0]))
6847 return "dbra %0,%l1\;clr%.w %0\;subq%.l #1,%0\;jcc %l1";
6848 if (GET_CODE (operands[0]) == MEM)
6849 return "subq%.l #1,%0\;jcc %l1";
6850 return "subq%.l #1,%0\;cmp%.l #-1,%0\;jne %l1";
6853 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
6855 (define_insn "*dbge_hi"
6858 (ge (plus:HI (match_operand:HI 0 "nonimmediate_operand" "+d*am")
6861 (label_ref (match_operand 1 "" ""))
6864 (plus:HI (match_dup 0)
6866 "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)"
6869 if (DATA_REG_P (operands[0]))
6870 return "dbra %0,%l1";
6871 if (GET_CODE (operands[0]) == MEM)
6872 return "subq%.w #1,%0\;jcc %l1";
6873 return "subq%.w #1,%0\;cmp%.w #-1,%0\;jne %l1";
6876 (define_expand "decrement_and_branch_until_zero"
6877 [(parallel [(set (pc)
6879 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "")
6882 (label_ref (match_operand 1 "" ""))
6885 (plus:SI (match_dup 0)
6890 (define_insn "*dbge_si"
6893 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+d*am")
6896 (label_ref (match_operand 1 "" ""))
6899 (plus:SI (match_dup 0)
6901 "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)"
6904 if (DATA_REG_P (operands[0]))
6905 return "dbra %0,%l1\;clr%.w %0\;subq%.l #1,%0\;jcc %l1";
6906 if (GET_CODE (operands[0]) == MEM)
6907 return "subq%.l #1,%0\;jcc %l1";
6908 return "subq%.l #1,%0\;cmp%.l #-1,%0\;jne %l1";
6911 (define_expand "sibcall"
6912 [(call (match_operand:QI 0 "memory_operand" "")
6913 (match_operand:SI 1 "general_operand" ""))]
6916 operands[0] = m68k_legitimize_sibcall_address (operands[0]);
6919 (define_insn "*sibcall"
6920 [(call (mem:QI (match_operand:SI 0 "sibcall_operand" ""))
6921 (match_operand:SI 1 "general_operand" ""))]
6922 "SIBLING_CALL_P (insn)"
6924 return output_sibcall (operands[0]);
6927 (define_expand "sibcall_value"
6928 [(set (match_operand 0 "" "")
6929 (call (match_operand:QI 1 "memory_operand" "")
6930 (match_operand:SI 2 "general_operand" "")))]
6933 operands[1] = m68k_legitimize_sibcall_address (operands[1]);
6936 (define_insn "*sibcall_value"
6937 [(set (match_operand 0 "" "=rf,rf")
6938 (call (mem:QI (match_operand:SI 1 "sibcall_operand" ""))
6939 (match_operand:SI 2 "general_operand" "")))]
6940 "SIBLING_CALL_P (insn)"
6942 operands[0] = operands[1];
6943 return output_sibcall (operands[0]);
6946 ;; Call subroutine with no return value.
6947 (define_expand "call"
6948 [(call (match_operand:QI 0 "memory_operand" "")
6949 (match_operand:SI 1 "general_operand" ""))]
6950 ;; Operand 1 not really used on the m68000.
6953 operands[0] = m68k_legitimize_call_address (operands[0]);
6956 (define_insn "*call"
6957 [(call (mem:QI (match_operand:SI 0 "call_operand" "a,W"))
6958 (match_operand:SI 1 "general_operand" "g,g"))]
6959 ;; Operand 1 not really used on the m68000.
6960 "!SIBLING_CALL_P (insn)"
6962 return output_call (operands[0]);
6964 [(set_attr "type" "jsr")])
6966 ;; Call subroutine, returning value in operand 0
6967 ;; (which must be a hard register).
6968 (define_expand "call_value"
6969 [(set (match_operand 0 "" "")
6970 (call (match_operand:QI 1 "memory_operand" "")
6971 (match_operand:SI 2 "general_operand" "")))]
6972 ;; Operand 2 not really used on the m68000.
6975 operands[1] = m68k_legitimize_call_address (operands[1]);
6978 (define_insn "*non_symbolic_call_value"
6979 [(set (match_operand 0 "" "=rf,rf")
6980 (call (mem:QI (match_operand:SI 1 "non_symbolic_call_operand" "a,W"))
6981 (match_operand:SI 2 "general_operand" "g,g")))]
6982 ;; Operand 2 not really used on the m68000.
6983 "!SIBLING_CALL_P (insn)"
6985 [(set_attr "type" "jsr")
6986 (set_attr "opx" "1")])
6988 (define_insn "*symbolic_call_value_jsr"
6989 [(set (match_operand 0 "" "=rf,rf")
6990 (call (mem:QI (match_operand:SI 1 "symbolic_operand" "a,W"))
6991 (match_operand:SI 2 "general_operand" "g,g")))]
6992 ;; Operand 2 not really used on the m68000.
6993 "!SIBLING_CALL_P (insn) && m68k_symbolic_call_var == M68K_SYMBOLIC_CALL_JSR"
6995 operands[0] = operands[1];
6996 return m68k_symbolic_call;
6998 [(set_attr "type" "jsr")
6999 (set_attr "opx" "1")])
7001 (define_insn "*symbolic_call_value_bsr"
7002 [(set (match_operand 0 "" "=rf,rf")
7003 (call (mem:QI (match_operand:SI 1 "symbolic_operand" "a,W"))
7004 (match_operand:SI 2 "general_operand" "g,g")))]
7005 ;; Operand 2 not really used on the m68000.
7006 "!SIBLING_CALL_P (insn)
7007 && (m68k_symbolic_call_var == M68K_SYMBOLIC_CALL_BSR_C
7008 || m68k_symbolic_call_var == M68K_SYMBOLIC_CALL_BSR_P)"
7010 operands[0] = operands[1];
7011 return m68k_symbolic_call;
7013 [(set_attr "type" "bsr")
7014 (set_attr "opx" "1")])
7016 ;; Call subroutine returning any type.
7018 (define_expand "untyped_call"
7019 [(parallel [(call (match_operand 0 "" "")
7021 (match_operand 1 "" "")
7022 (match_operand 2 "" "")])]
7023 "NEEDS_UNTYPED_CALL"
7027 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
7029 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7031 rtx set = XVECEXP (operands[2], 0, i);
7032 emit_move_insn (SET_DEST (set), SET_SRC (set));
7035 /* The optimizer does not know that the call sets the function value
7036 registers we stored in the result block. We avoid problems by
7037 claiming that all hard registers are used and clobbered at this
7039 emit_insn (gen_blockage ());
7044 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
7045 ;; all of memory. This blocks insns from being moved across this point.
7047 (define_insn "blockage"
7048 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
7056 [(set_attr "type" "nop")])
7058 (define_expand "prologue"
7062 m68k_expand_prologue ();
7066 (define_expand "epilogue"
7070 m68k_expand_epilogue (false);
7074 (define_expand "sibcall_epilogue"
7078 m68k_expand_epilogue (true);
7082 ;; Used for frameless functions which save no regs and allocate no locals.
7083 (define_expand "return"
7085 "m68k_use_return_insn ()"
7088 (define_insn "*return"
7092 switch (m68k_get_function_kind (current_function_decl))
7094 case m68k_fk_interrupt_handler:
7097 case m68k_fk_interrupt_thread:
7101 if (crtl->args.pops_args)
7103 operands[0] = GEN_INT (crtl->args.pops_args);
7110 [(set_attr "type" "rts")])
7112 (define_insn "*m68k_store_multiple"
7113 [(match_parallel 0 "" [(match_operand 1 "")])]
7114 "m68k_movem_pattern_p (operands[0], NULL, 0, true)"
7116 return m68k_output_movem (operands, operands[0], 0, true);
7119 (define_insn "*m68k_store_multiple_automod"
7120 [(match_parallel 0 ""
7121 [(set (match_operand:SI 1 "register_operand" "=a")
7122 (plus:SI (match_operand:SI 2 "register_operand" "1")
7123 (match_operand:SI 3 "const_int_operand")))])]
7124 "m68k_movem_pattern_p (operands[0], operands[1], INTVAL (operands[3]), true)"
7126 return m68k_output_movem (operands, operands[0], INTVAL (operands[3]), true);
7129 (define_insn "*m68k_load_multiple"
7130 [(match_parallel 0 "" [(match_operand 1 "")])]
7131 "m68k_movem_pattern_p (operands[0], NULL, 0, false)"
7133 return m68k_output_movem (operands, operands[0], 0, false);
7136 (define_insn "*m68k_load_multiple_automod"
7137 [(match_parallel 0 ""
7138 [(set (match_operand:SI 1 "register_operand" "=a")
7139 (plus:SI (match_operand:SI 2 "register_operand" "1")
7140 (match_operand:SI 3 "const_int_operand")))])]
7141 "m68k_movem_pattern_p (operands[0], operands[1],
7142 INTVAL (operands[3]), false)"
7144 return m68k_output_movem (operands, operands[0],
7145 INTVAL (operands[3]), false);
7148 (define_expand "link"
7150 [(set (match_operand:SI 0 "register_operand")
7151 (plus:SI (reg:SI SP_REG) (const_int -4)))
7154 (set (reg:SI SP_REG)
7155 (plus:SI (reg:SI SP_REG)
7156 (match_operand:SI 1 "const_int_operand")))])]
7157 "TARGET_68020 || INTVAL (operands[1]) >= -0x8004"
7159 operands[2] = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, -4));
7162 (define_insn "*link"
7163 [(set (match_operand:SI 0 "register_operand" "+r")
7164 (plus:SI (reg:SI SP_REG) (const_int -4)))
7165 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
7167 (set (reg:SI SP_REG)
7168 (plus:SI (reg:SI SP_REG)
7169 (match_operand:SI 1 "const_int_operand")))]
7170 "TARGET_68020 || INTVAL (operands[1]) >= -0x8004"
7172 operands[1] = GEN_INT (INTVAL (operands[1]) + 4);
7174 return "link %0,%1";
7175 else if (INTVAL (operands[1]) >= -0x8000)
7176 return "link.w %0,%1";
7178 return "link.l %0,%1";
7180 [(set_attr "type" "link")])
7182 (define_expand "unlink"
7184 [(set (match_operand:SI 0 "register_operand")
7186 (set (reg:SI SP_REG)
7187 (plus:SI (match_dup 0)
7191 operands[1] = gen_frame_mem (SImode, copy_rtx (operands[0]));
7194 (define_insn "*unlink"
7195 [(set (match_operand:SI 0 "register_operand" "+r")
7196 (mem:SI (match_dup 0)))
7197 (set (reg:SI SP_REG)
7198 (plus:SI (match_dup 0)
7202 [(set_attr "type" "unlk")])
7204 (define_insn "load_got"
7205 [(set (match_operand:SI 0 "register_operand" "=a")
7206 (unspec:SI [(const_int 0)] UNSPEC_GOT))]
7209 if (TARGET_ID_SHARED_LIBRARY)
7211 operands[1] = gen_rtx_REG (Pmode, PIC_REG);
7212 return MOTOROLA ? "move.l %?(%1),%0" : "movel %1@(%?), %0";
7216 if (TARGET_COLDFIRE)
7217 /* Load the full 32-bit PC-relative offset of
7218 _GLOBAL_OFFSET_TABLE_ into the PIC register, then use it to
7219 calculate the absolute value. The offset and "lea"
7220 operation word together occupy 6 bytes. */
7221 return ("move.l #_GLOBAL_OFFSET_TABLE_@GOTPC, %0\n\t"
7222 "lea (-6, %%pc, %0), %0");
7224 return "lea (%%pc, _GLOBAL_OFFSET_TABLE_@GOTPC), %0";
7227 return ("movel #_GLOBAL_OFFSET_TABLE_, %0\n\t"
7228 "lea %%pc@(0,%0:l),%0");
7231 (define_insn "indirect_jump"
7232 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
7235 [(set_attr "type" "jmp")])
7237 ;; This should not be used unless the add/sub insns can't be.
7240 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
7241 (match_operand:QI 1 "address_operand" "p"))]
7245 ;; This is the first machine-dependent peephole optimization.
7246 ;; It is useful when a floating value is returned from a function call
7247 ;; and then is moved into an FP register.
7248 ;; But it is mainly intended to test the support for these optimizations.
7251 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
7252 (set (match_operand:DF 0 "register_operand" "")
7253 (match_operand:DF 1 "register_operand" ""))]
7254 "FP_REG_P (operands[0]) && !FP_REG_P (operands[1])"
7255 [(set (mem:SI (reg:SI SP_REG)) (match_dup 1))
7256 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 2))
7257 (set (match_dup 0) (mem:DF (post_inc:SI (reg:SI SP_REG))))]
7258 "split_di(operands + 1, 1, operands + 1, operands + 2);")
7260 ;; Optimize a stack-adjust followed by a push of an argument.
7261 ;; This is said to happen frequently with -msoft-float
7262 ;; when there are consecutive library calls.
7265 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
7266 (set (match_operand:SF 0 "push_operand" "")
7267 (match_operand:SF 1 "general_operand" ""))]
7268 "!reg_mentioned_p (stack_pointer_rtx, operands[0])"
7269 [(set (match_dup 0) (match_dup 1))]
7270 "operands[0] = replace_equiv_address (operands[0], stack_pointer_rtx);")
7273 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
7274 (match_operand:SI 0 "const_int_operand" "")))
7275 (set (match_operand:SF 1 "push_operand" "")
7276 (match_operand:SF 2 "general_operand" ""))]
7277 "INTVAL (operands[0]) > 4
7278 && !reg_mentioned_p (stack_pointer_rtx, operands[2])"
7279 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 0)))
7280 (set (match_dup 1) (match_dup 2))]
7282 operands[0] = GEN_INT (INTVAL (operands[0]) - 4);
7283 operands[1] = replace_equiv_address (operands[1], stack_pointer_rtx);
7286 ;; Speed up stack adjust followed by a fullword fixedpoint push.
7287 ;; Constant operands need special care, as replacing a "pea X.w" with
7288 ;; "move.l #X,(%sp)" is often not a win.
7290 ;; Already done by the previous csa pass, left as reference.
7292 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
7293 (set (match_operand:SI 0 "push_operand" "")
7294 (match_operand:SI 1 "general_operand" ""))]
7295 "!reg_mentioned_p (stack_pointer_rtx, operands[1])"
7296 [(set (match_dup 0) (match_dup 1))]
7297 "operands[0] = replace_equiv_address (operands[0], stack_pointer_rtx);")
7299 ;; Try to use moveq, after stack push has been changed into a simple move.
7301 [(match_scratch:SI 2 "d")
7302 (set (match_operand:SI 0 "memory_operand" "")
7303 (match_operand:SI 1 "const_int_operand" ""))]
7304 "GET_CODE (XEXP (operands[0], 0)) != PRE_DEC
7305 && INTVAL (operands[1]) != 0
7306 && IN_RANGE (INTVAL (operands[1]), -0x80, 0x7f)
7307 && !valid_mov3q_const (INTVAL (operands[1]))"
7308 [(set (match_dup 2) (match_dup 1))
7309 (set (match_dup 0) (match_dup 2))])
7311 ;; This sequence adds an instruction, but is two bytes shorter.
7313 [(match_scratch:SI 2 "d")
7314 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 12)))
7315 (set (match_operand:SI 0 "push_operand" "")
7316 (match_operand:SI 1 "const_int_operand" ""))]
7317 "INTVAL (operands[1]) != 0
7318 && IN_RANGE (INTVAL (operands[1]), -0x80, 0x7f)
7319 && !valid_mov3q_const (INTVAL (operands[1]))"
7320 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
7321 (set (match_dup 2) (match_dup 1))
7322 (set (match_dup 0) (match_dup 2))]
7323 "operands[0] = replace_equiv_address (operands[0], stack_pointer_rtx);")
7325 ;; Changing pea X.w into a move.l is no real win here.
7327 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
7328 (match_operand:SI 0 "const_int_operand" "")))
7329 (set (match_operand:SI 1 "push_operand" "")
7330 (match_operand:SI 2 "general_operand" ""))]
7331 "INTVAL (operands[0]) > 4
7332 && !reg_mentioned_p (stack_pointer_rtx, operands[2])
7333 && !(CONST_INT_P (operands[2]) && INTVAL (operands[2]) != 0
7334 && IN_RANGE (INTVAL (operands[2]), -0x8000, 0x7fff)
7335 && !valid_mov3q_const (INTVAL (operands[2])))"
7336 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 0)))
7337 (set (match_dup 1) (match_dup 2))]
7339 operands[0] = GEN_INT (INTVAL (operands[0]) - 4);
7340 operands[1] = replace_equiv_address (operands[1], stack_pointer_rtx);
7343 ;; Speed up pushing a single byte/two bytes but leaving four bytes of space
7344 ;; (which differs slightly between m680x0 and ColdFire).
7347 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
7348 (set (match_operand:QI 0 "memory_operand" "")
7349 (match_operand:QI 1 "register_operand" ""))]
7350 "!reg_mentioned_p (stack_pointer_rtx, operands[1])
7351 && GET_CODE (XEXP (operands[0], 0)) == PLUS
7352 && rtx_equal_p (XEXP (XEXP (operands[0], 0), 0), stack_pointer_rtx)
7353 && CONST_INT_P (XEXP (XEXP (operands[0], 0), 1))
7354 && INTVAL (XEXP (XEXP (operands[0], 0), 1)) == 3"
7355 [(set (match_dup 0) (match_dup 1))]
7357 rtx addr = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx);
7358 operands[0] = adjust_automodify_address (operands[0], SImode, addr, -3);
7359 operands[1] = simplify_gen_subreg (SImode, operands[1], QImode, 0);
7363 [(set (match_operand:QI 0 "push_operand" "")
7364 (match_operand:QI 1 "register_operand" ""))
7365 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -3)))]
7366 "!reg_mentioned_p (stack_pointer_rtx, operands[1])"
7367 [(set (match_dup 0) (match_dup 1))]
7369 operands[0] = adjust_automodify_address (operands[0], SImode,
7370 XEXP (operands[0], 0), -3);
7371 operands[1] = simplify_gen_subreg (SImode, operands[1], QImode, 0);
7375 [(set (match_operand:HI 0 "push_operand" "")
7376 (match_operand:HI 1 "register_operand" ""))
7377 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -2)))]
7378 "!reg_mentioned_p (stack_pointer_rtx, operands[1])"
7379 [(set (match_dup 0) (match_dup 1))]
7381 operands[0] = adjust_automodify_address (operands[0], SImode,
7382 XEXP (operands[0], 0), -2);
7383 operands[1] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
7386 ;; Optimize a series of strict_low_part assignments
7389 [(set (match_operand:SI 0 "register_operand" "")
7391 (set (strict_low_part (match_operand:HI 1 "register_operand" ""))
7392 (match_operand:HI 2 "general_operand" ""))]
7393 "REGNO (operands[0]) == REGNO (operands[1])
7394 && strict_low_part_peephole_ok (HImode, insn, operands[0])"
7395 [(set (strict_low_part (match_dup 1)) (match_dup 2))]
7399 [(set (match_operand:SI 0 "register_operand" "")
7401 (set (strict_low_part (match_operand:QI 1 "register_operand" ""))
7402 (match_operand:QI 2 "general_operand" ""))]
7403 "REGNO (operands[0]) == REGNO (operands[1])
7404 && strict_low_part_peephole_ok (QImode, insn, operands[0])"
7405 [(set (strict_low_part (match_dup 1)) (match_dup 2))]
7413 ;; jCC label ; abnormal loop termination
7414 ;; dbra dN, loop ; normal loop termination
7422 ;; Which moves the jCC condition outside the inner loop for free.
7426 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7427 [(cc0) (const_int 0)])
7428 (label_ref (match_operand 2 "" ""))
7433 (ne (match_operand:HI 0 "register_operand" "")
7435 (label_ref (match_operand 1 "" ""))
7438 (plus:HI (match_dup 0)
7440 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7443 output_dbcc_and_branch (operands);
7448 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7449 [(cc0) (const_int 0)])
7450 (label_ref (match_operand 2 "" ""))
7455 (ne (match_operand:SI 0 "register_operand" "")
7457 (label_ref (match_operand 1 "" ""))
7460 (plus:SI (match_dup 0)
7462 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7465 output_dbcc_and_branch (operands);
7470 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7471 [(cc0) (const_int 0)])
7472 (label_ref (match_operand 2 "" ""))
7477 (ge (plus:HI (match_operand:HI 0 "register_operand" "")
7480 (label_ref (match_operand 1 "" ""))
7483 (plus:HI (match_dup 0)
7485 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7488 output_dbcc_and_branch (operands);
7493 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7494 [(cc0) (const_int 0)])
7495 (label_ref (match_operand 2 "" ""))
7500 (ge (plus:SI (match_operand:SI 0 "register_operand" "")
7503 (label_ref (match_operand 1 "" ""))
7506 (plus:SI (match_dup 0)
7508 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7511 output_dbcc_and_branch (operands);
7516 (define_insn "extendsfxf2"
7517 [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f")
7518 (float_extend:XF (match_operand:SF 1 "general_operand" "f,rmF")))]
7521 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7523 if (REGNO (operands[0]) == REGNO (operands[1]))
7525 /* Extending float to double in an fp-reg is a no-op.
7526 NOTICE_UPDATE_CC has already assumed that the
7527 cc will be set. So cancel what it did. */
7528 cc_status = cc_prev_status;
7531 return "f%$move%.x %1,%0";
7533 if (FP_REG_P (operands[0]))
7535 if (FP_REG_P (operands[1]))
7536 return "f%$move%.x %1,%0";
7537 else if (ADDRESS_REG_P (operands[1]))
7538 return "move%.l %1,%-\;f%$move%.s %+,%0";
7539 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
7540 return output_move_const_single (operands);
7541 return "f%$move%.s %f1,%0";
7543 return "fmove%.x %f1,%0";
7547 (define_insn "extenddfxf2"
7548 [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f")
7550 (match_operand:DF 1 "general_operand" "f,rmE")))]
7553 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7555 if (REGNO (operands[0]) == REGNO (operands[1]))
7557 /* Extending float to double in an fp-reg is a no-op.
7558 NOTICE_UPDATE_CC has already assumed that the
7559 cc will be set. So cancel what it did. */
7560 cc_status = cc_prev_status;
7563 return "fmove%.x %1,%0";
7565 if (FP_REG_P (operands[0]))
7567 if (REG_P (operands[1]))
7570 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7571 output_asm_insn ("move%.l %1,%-", xoperands);
7572 output_asm_insn ("move%.l %1,%-", operands);
7573 return "f%&move%.d %+,%0";
7575 if (GET_CODE (operands[1]) == CONST_DOUBLE)
7576 return output_move_const_double (operands);
7577 return "f%&move%.d %f1,%0";
7579 return "fmove%.x %f1,%0";
7582 (define_insn "truncxfdf2"
7583 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,!r")
7585 (match_operand:XF 1 "general_operand" "f,f")))]
7588 if (REG_P (operands[0]))
7590 output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands);
7591 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
7592 return "move%.l %+,%0";
7594 return "fmove%.d %f1,%0";
7597 (define_insn "truncxfsf2"
7598 [(set (match_operand:SF 0 "nonimmediate_operand" "=dm")
7600 (match_operand:XF 1 "general_operand" "f")))]
7604 (define_insn "sin<mode>2"
7605 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
7607 [(match_operand:FP 1 "general_operand" "f<FP:dreg>m")] UNSPEC_SIN))]
7608 "TARGET_68881 && flag_unsafe_math_optimizations"
7610 if (FP_REG_P (operands[1]))
7611 return "fsin%.x %1,%0";
7613 return "fsin%.<FP:prec> %1,%0";
7616 (define_insn "cos<mode>2"
7617 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
7619 [(match_operand:FP 1 "general_operand" "f<FP:dreg>m")] UNSPEC_COS))]
7620 "TARGET_68881 && flag_unsafe_math_optimizations"
7622 if (FP_REG_P (operands[1]))
7623 return "fcos%.x %1,%0";
7625 return "fcos%.<FP:prec> %1,%0";
7628 ;; Unconditional traps are assumed to have (const_int 1) for the condition.
7630 [(trap_if (const_int 1) (const_int 7))]
7633 [(set_attr "type" "trap")])
7635 (define_expand "conditional_trap"
7636 [(trap_if (match_operator 0 "valid_dbcc_comparison_p"
7637 [(cc0) (const_int 0)])
7638 (match_operand:SI 1 "const_int_operand" "I"))]
7641 if (m68k_last_compare_had_fp_operands)
7643 m68k_last_compare_had_fp_operands = 0;
7648 (define_insn "*conditional_trap"
7649 [(trap_if (match_operator 0 "valid_dbcc_comparison_p"
7650 [(cc0) (const_int 0)])
7651 (match_operand:SI 1 "const_int_operand" "I"))]
7652 "TARGET_68020 && ! flags_in_68881 ()"
7654 switch (GET_CODE (operands[0]))
7656 case EQ: return "trapeq";
7657 case NE: return "trapne";
7658 case GT: return "trapgt";
7659 case GTU: return "traphi";
7660 case LT: return "traplt";
7661 case LTU: return "trapcs";
7662 case GE: return "trapge";
7663 case GEU: return "trapcc";
7664 case LE: return "traple";
7665 case LEU: return "trapls";
7666 default: gcc_unreachable ();
7670 ;; These are to prevent the scheduler from moving stores to the frame
7671 ;; before the stack adjustment.
7672 (define_insn "stack_tie"
7673 [(set (mem:BLK (scratch))
7674 (unspec:BLK [(match_operand:SI 0 "register_operand" "r")
7675 (match_operand:SI 1 "register_operand" "r")]
7679 [(set_attr "type" "ignore")])
7681 ;; Instruction that subscribes one word in ColdFire instruction buffer.
7682 ;; This instruction is used within scheduler only and should not appear
7683 ;; in the instruction stream.
7685 [(unspec [(const_int 0)] UNSPEC_IB)]
7688 [(set_attr "type" "ib")])