1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 1988, 1993, 1994, 1995 Free Software Foundation, Inc.
4 ;; This file is part of GNU CC.
6 ;; GNU CC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GNU CC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GNU CC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21 ;;- instruction definitions
23 ;;- @@The original PO technology requires these to be ordered by speed,
24 ;;- @@ so that assigner will pick the fastest.
26 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
28 ;;- When naming insn's (operand 0 of define_insn) be careful about using
29 ;;- names from other targets machine descriptions.
31 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
32 ;;- updates for most instructions.
34 ;;- Operand classes for the register allocator:
35 ;;- 'a' one of the address registers can be used.
36 ;;- 'd' one of the data registers can be used.
37 ;;- 'f' one of the m68881 registers can be used
38 ;;- 'r' either a data or an address register can be used.
39 ;;- 'x' if one of the Sun FPA registers
40 ;;- 'y' if one of the Low Sun FPA registers (fpa0-fpa15).
42 ;;- Immediate Floating point operator constraints
43 ;;- 'G' a floating point constant that is *NOT* one of the standard
44 ;; 68881 constant values (to force calling output_move_const_double
45 ;; to get it from rom if it is a 68881 constant).
46 ;;- 'H' one of the standard FPA constant values
48 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
51 ;;- Immediate integer operand constraints:
53 ;;- 'J' -32768 .. 32767
54 ;;- 'K' all integers EXCEPT -128 .. 127
58 ;;- "%." size separator ("." or "") move%.l d0,d1
59 ;;- "%#" immediate separator ("#" or "") move%.l %#0,d0
60 ;;- "%-" push operand "sp@-" move%.l d0,%-
61 ;;- "%+" pop operand "sp@+" move%.l d0,%+
62 ;;- "%@" top of stack "sp@" move%.l d0,%@
63 ;;- "%!" fpcr register
64 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
65 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
68 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
69 ;; operand 1 is the argument for `sin'.
70 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
71 ;; operand 1 is the argument for `cos'.
73 ;;- Information about 68040 port.
75 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
76 ;;- be emulated in software by the OS. It is faster to avoid these
77 ;;- instructions and issue a library call rather than trapping into
78 ;;- the kernel. The affected instructions are fintrz and fscale. The
79 ;;- TARGET_68040 flag turns the use of the opcodes off.
81 ;;- The '040 also implements a set of new floating-point instructions
82 ;;- which specify the rounding precision in the opcode. This finally
83 ;;- permit the 68k series to be truly IEEE compliant, and solves all
84 ;;- issues of excess precision accumulating in the extended registers.
85 ;;- By default, GCC does not use these instructions, since such code will
86 ;;- not run on an '030. To use these instructions, use the -m68040-only
87 ;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY,
88 ;;- you can make these instructions the default.
90 ;;- These new instructions aren't directly in the md. They are brought
91 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
95 ;;- FPA port explanation:
97 ;;- Usage of the Sun FPA and the 68881 together
99 ;;- The current port of gcc to the sun fpa disallows use of the m68881
100 ;;- instructions completely if code is targeted for the fpa. This is
101 ;;- for the following reasons:
103 ;;- 1) Expressing the preference hierarchy (ie. use the fpa if you
104 ;;- can, the 68881 otherwise, and data registers only if you are
105 ;;- forced to it) is a bitch with the current constraint scheme,
106 ;;- especially since it would have to work for any combination of
109 ;;- 2) There are no instructions to move between the two types of
110 ;;- registers; the stack must be used as an intermediary.
112 ;;- It could indeed be done; I think the best way would be to have
113 ;;- separate patterns for TARGET_FPA (which implies a 68881),
114 ;;- TARGET_68881, and no floating point co-processor. Use
115 ;;- define_expands for all of the named instruction patterns, and
116 ;;- include code in the FPA instruction to deal with the 68881 with
117 ;;- preferences specifically set to favor the fpa. Some of this has
118 ;;- already been done:
120 ;;- 1) Separation of most of the patterns out into a TARGET_FPA
121 ;;- case and a TARGET_68881 case (the exceptions are the patterns
122 ;;- which would need one define_expand and three define_insn's under
123 ;;- it (with a lot of duplicate code between them) to replace the
124 ;;- current single define_insn. These are mov{[ds]f,[ds]i} and the
125 ;;- first two patterns in the md.
127 ;;- Some would still have to be done:
129 ;;- 1) Add code to the fpa patterns which correspond to 68881
130 ;;- patterns to deal with the 68881 case (including preferences!).
131 ;;- What you might actually do here is combine the fpa and 68881 code
132 ;;- back together into one pattern for those instructions where it's
133 ;;- absolutely necessary and save yourself some duplicate code. I'm
134 ;;- not completely sure as to whether you could get away with doing
135 ;;- this only for the mov* insns, or if you'd have to do it for all
137 ;;- 2) Add code to the mov{[ds]f,[ds]i} instructions to handle
138 ;;- moving between fpa regs and 68881 regs.
140 ;;- Since the fpa is more powerful than the 68881 and also has more
141 ;;- registers, and since I think the resultant md would be medium ugly
142 ;;- (lot's of duplicate code, ugly constraint strings), I elected not
143 ;;- to do this change.
145 ;;- Another reason why someone *might* want to do the change is to
146 ;;- control which register classes are accessed in a slightly cleaner
147 ;;- way than I have. See the blurb on CONDITIONAL_REGISTER_USAGE in
148 ;;- the internals manual.
150 ;;- Yet another reason why someone might want to do this change is to
151 ;;- allow use of some of the 68881 insns which have no equivalent on
152 ;;- the fpa. The sqrt instruction comes fairly quickly to mind.
154 ;;- If this is ever done, don't forget to change sun3.h so that
155 ;;- it *will* define __HAVE_68881__ when the FPA is in use.
157 ;;- Condition code hack
159 ;;- When a floating point compare is done in the fpa, the resulting
160 ;;- condition codes are left in the fpastatus register. The values in
161 ;;- this register must be moved into the 68000 cc register before any
162 ;;- jump is executed. Once this has been done, regular jump
163 ;;- instructions are fine (ie. floating point jumps are not necessary.
164 ;;- They are only done if the cc is in the 68881).
166 ;;- The instructions that move the fpastatus register to the 68000
167 ;;- register clobber a data register (the move cannot be done direct).
168 ;;- These instructions might be bundled either with the compare
169 ;;- instruction, or the branch instruction. If we were using both the
170 ;;- fpa and the 68881 together, we would wish to only mark the
171 ;;- register clobbered if we were doing the compare in the fpa, but I
172 ;;- think that that decision (whether to clobber the register or not)
173 ;;- must be done before register allocation (makes sense) and hence we
174 ;;- can't know if the floating point compare will be done in the fpa
175 ;;- or the fp. So whenever we are asked for code that uses the fpa,
176 ;;- we will mark a data register as clobbered. This is reasonable, as
177 ;;- almost all floating point compare operations done with fpa code
178 ;;- enabled will be done in the fpa. It's even more reasonable since
179 ;;- we decided to make the 68881 and the fpa mutually exclusive.
181 ;;- We place to code to move the fpastatus register inside of a
182 ;;- define_expand so that we can do it conditionally based on whether
183 ;;- we are targeting an fpa or not.
185 ;;- This still leaves us with the question of where we wish to put the
186 ;;- code to move the fpastatus reg. If we put it in the compare
187 ;;- instruction, we can restrict the clobbering of the register to
188 ;;- floating point compares, but we can't take advantage of floating
189 ;;- point subtracts & etc. that alter the fpastatus register. If we
190 ;;- put it in the branch instruction, all branches compiled with fpa
191 ;;- code enabled will clobber a data register, but we will be able to
192 ;;- take advantage of fpa subtracts. This balance favors putting the
193 ;;- code in with the compare instruction.
195 ;;- Note that if some enterprising hacker should decide to switch
196 ;;- this, he'll need to modify the code in NOTICE_UPDATE_CC.
198 ;;- Usage of the top 16 fpa registers
200 ;;- The only locations which we may transfer fpa registers 16-31 from
201 ;;- or to are the fpa registers 0-15. (68000 registers and memory
202 ;;- locations are impossible). This causes problems in gcc, which
203 ;;- assumes that mov?? instructions require no additional registers
204 ;;- (see section 11.7) and since floating point moves *must* be
205 ;;- supported into general registers (see section 12.3 under
206 ;;- HARD_REGNO_OK_FOR_MODE_P) from anywhere.
208 ;;- My solution was to reserve fpa0 for moves into or out of these top
209 ;;- 16 registers and to disparage the choice to reload into or out of
210 ;;- these registers as much as I could. That alternative is always
211 ;;- last in the list, so it will not be used unless all else fails. I
212 ;;- will note that according to my current information, sun's compiler
213 ;;- doesn't use these top 16 registers at all.
215 ;;- There is another possible way to do it. I *believe* that if you
216 ;;- make absolutely sure that the code will not be executed in the
217 ;;- reload pass, you can support the mov?? names with define_expands
218 ;;- which require new registers. This may be possible by the
219 ;;- appropriate juggling of constraints. I may come back to this later.
221 ;;- Usage of constant RAM
223 ;;- This has been handled correctly (I believe) but the way I've done
224 ;;- it could use a little explanation. The constant RAM can only be
225 ;;- accessed when the instruction is in "command register" mode.
226 ;;- "command register" mode means that no accessing of memory or the
227 ;;- 68000 registers is being done. This can be expressed easily in
228 ;;- constraints, so generally the mode of the instruction is
229 ;;- determined by a branch off of which_alternative. In outputting
230 ;;- instructions, a 'w' means to output an access to the constant ram
231 ;;- (if the arg is CONST_DOUBLE and is one of the available
232 ;;- constants), and 'x' means to output a register pair (if the arg is
233 ;;- a 68000 register) and a 'y' is the combination of the above two
234 ;;- processes. You use a 'y' in two operand DF instructions where you
235 ;;- *know* the other operand is an fpa register, you use an 'x' in DF
236 ;;- instructions where the arg might be a 68000 register and the
237 ;;- instruction is *not* in "command register" mode, and you use a 'w'
238 ;;- in two situations: 1) The instruction *is* in command register
239 ;;- mode (and hence won't be accessing 68000 registers), or 2) The
240 ;;- instruction is a two operand SF instruction where you know the
241 ;;- other operand is an fpa register.
243 ;;- Optimization issues
245 ;;- I actually think that I've included all of the fpa instructions
246 ;;- that should be included. Note that if someone is interested in
247 ;;- doing serious floating point work on the sun fpa, I would advise
248 ;;- the use of the "asm" instruction in gcc to allow you to use the
249 ;;- sin, cos, and exponential functions on the fpa board.
251 ;;- END FPA Explanation Section.
254 ;;- Some of these insn's are composites of several m68000 op codes.
255 ;;- The assembler (or final @@??) insures that the appropriate one is
259 [(set (match_operand:DF 0 "push_operand" "=m")
260 (match_operand:DF 1 "general_operand" "ro<>fyE"))]
264 if (FP_REG_P (operands[1]))
265 return \"fmove%.d %f1,%0\";
266 if (FPA_REG_P (operands[1]))
267 return \"fpmove%.d %1, %x0\";
268 return output_move_double (operands);
272 [(set (match_operand:DI 0 "push_operand" "=m")
273 (match_operand:DI 1 "general_operand" "ro<>Fy"))]
277 return output_move_double (operands);
280 ;; We don't want to allow a constant operand for test insns because
281 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
282 ;; be folded while optimizing anyway.
285 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
290 /* ISI's assembler fails to handle tstl a0. */
291 if (! ADDRESS_REG_P (operands[0]))
293 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
295 return \"tst%.l %0\";
296 /* If you think that the 68020 does not support tstl a0,
297 reread page B-167 of the 68020 manual more carefully. */
298 /* On an address reg, cmpw may replace cmpl. */
300 return \"cmp%.w %0,%#0\";
302 return \"cmp%.w %#0,%0\";
306 ;; This can't use an address register, because comparisons
307 ;; with address registers as second operand always test the whole word.
310 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
316 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
320 (define_expand "tstsf"
322 (match_operand:SF 0 "general_operand" ""))]
323 "TARGET_68881 || TARGET_FPA"
328 emit_insn (gen_tstsf_fpa (operands[0]));
333 (define_insn "tstsf_fpa"
335 (match_operand:SF 0 "general_operand" "xmdF"))
336 (clobber (match_scratch:SI 1 "=d"))]
338 "fptst%.s %x0\;fpmove fpastatus,%1\;movw %1,cc")
342 (match_operand:SF 0 "general_operand" "fdm"))]
346 cc_status.flags = CC_IN_68881;
347 if (FP_REG_P (operands[0]))
348 return \"ftst%.x %0\";
349 return \"ftst%.s %0\";
352 (define_expand "tstdf"
354 (match_operand:DF 0 "general_operand" ""))]
355 "TARGET_68881 || TARGET_FPA"
360 emit_insn (gen_tstsf_fpa (operands[0]));
365 (define_insn "tstdf_fpa"
367 (match_operand:DF 0 "general_operand" "xrmF"))
368 (clobber (match_scratch:SI 1 "=d"))]
370 "fptst%.d %x0\;fpmove fpastatus,%1\;movw %1,cc")
374 (match_operand:DF 0 "general_operand" "fm"))]
378 cc_status.flags = CC_IN_68881;
379 if (FP_REG_P (operands[0]))
380 return \"ftst%.x %0\";
381 return \"ftst%.d %0\";
384 ;; compare instructions.
386 ;; This is the second "hook" for PIC code (in addition to movsi). See
387 ;; comment of movsi for a description of PIC handling.
388 (define_expand "cmpsi"
390 (compare (match_operand:SI 0 "nonimmediate_operand" "")
391 (match_operand:SI 1 "general_operand" "")))]
395 if (flag_pic && symbolic_operand (operands[1], SImode))
397 /* The source is an address which requires PIC relocation.
398 Call legitimize_pic_address with the source, mode, and a relocation
399 register (a new pseudo, or the final destination if reload_in_progress
400 is set). Then fall through normally */
401 extern rtx legitimize_pic_address();
402 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
403 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
407 ;; A composite of the cmp, cmpa, & cmpi m68000 op codes.
410 (compare (match_operand:SI 0 "nonimmediate_operand" "rKs,mr,>")
411 (match_operand:SI 1 "general_operand" "mr,Ksr,>")))]
415 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
417 return \"cmpm%.l %0,%1\";
419 return \"cmpm%.l %1,%0\";
421 if (REG_P (operands[1])
422 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
423 { cc_status.flags |= CC_REVERSED;
425 return \"cmp%.l %d1,%d0\";
427 return \"cmp%.l %d0,%d1\";
431 return \"cmp%.l %d0,%d1\";
433 return \"cmp%.l %d1,%d0\";
439 (compare (match_operand:HI 0 "nonimmediate_operand" "rnm,d,n,m,>")
440 (match_operand:HI 1 "general_operand" "d,rnm,m,n,>")))]
444 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
446 return \"cmpm%.w %0,%1\";
448 return \"cmpm%.w %1,%0\";
450 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
451 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
452 { cc_status.flags |= CC_REVERSED;
454 return \"cmp%.w %d1,%d0\";
456 return \"cmp%.w %d0,%d1\";
460 return \"cmp%.w %d0,%d1\";
462 return \"cmp%.w %d1,%d0\";
468 (compare (match_operand:QI 0 "nonimmediate_operand" "dn,md,>")
469 (match_operand:QI 1 "general_operand" "dm,nd,>")))]
473 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
475 return \"cmpm%.b %0,%1\";
477 return \"cmpm%.b %1,%0\";
479 if (REG_P (operands[1])
480 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
481 { cc_status.flags |= CC_REVERSED;
483 return \"cmp%.b %d1,%d0\";
485 return \"cmp%.b %d0,%d1\";
489 return \"cmp%.b %d0,%d1\";
491 return \"cmp%.b %d1,%d0\";
495 (define_expand "cmpdf"
497 (compare (match_operand:DF 0 "general_operand" "")
498 (match_operand:DF 1 "general_operand" "")))]
499 "TARGET_68881 || TARGET_FPA"
504 emit_insn (gen_cmpdf_fpa (operands[0], operands[1]));
509 (define_insn "cmpdf_fpa"
511 (compare (match_operand:DF 0 "general_operand" "x,y")
512 (match_operand:DF 1 "general_operand" "xH,rmF")))
513 (clobber (match_scratch:SI 2 "=d,d"))]
515 "fpcmp%.d %y1,%0\;fpmove fpastatus,%2\;movw %2,cc")
519 (compare (match_operand:DF 0 "general_operand" "f,mG")
520 (match_operand:DF 1 "general_operand" "fmG,f")))]
524 cc_status.flags = CC_IN_68881;
526 if (REG_P (operands[0]))
528 if (REG_P (operands[1]))
529 return \"fcmp%.x %0,%1\";
531 return \"fcmp%.d %0,%f1\";
533 cc_status.flags |= CC_REVERSED;
534 return \"fcmp%.d %1,%f0\";
536 if (REG_P (operands[0]))
538 if (REG_P (operands[1]))
539 return \"fcmp%.x %1,%0\";
541 return \"fcmp%.d %f1,%0\";
543 cc_status.flags |= CC_REVERSED;
544 return \"fcmp%.d %f0,%1\";
548 (define_expand "cmpsf"
550 (compare (match_operand:SF 0 "general_operand" "")
551 (match_operand:SF 1 "general_operand" "")))]
552 "TARGET_68881 || TARGET_FPA"
557 emit_insn (gen_cmpsf_fpa (operands[0], operands[1]));
562 (define_insn "cmpsf_fpa"
564 (compare (match_operand:SF 0 "general_operand" "x,y")
565 (match_operand:SF 1 "general_operand" "xH,rmF")))
566 (clobber (match_scratch:SI 2 "=d,d"))]
568 "fpcmp%.s %w1,%x0\;fpmove fpastatus,%2\;movw %2,cc")
572 (compare (match_operand:SF 0 "general_operand" "f,mdG")
573 (match_operand:SF 1 "general_operand" "fmdG,f")))]
577 cc_status.flags = CC_IN_68881;
579 if (FP_REG_P (operands[0]))
581 if (FP_REG_P (operands[1]))
582 return \"fcmp%.x %0,%1\";
584 return \"fcmp%.s %0,%f1\";
586 cc_status.flags |= CC_REVERSED;
587 return \"fcmp%.s %1,%f0\";
589 if (FP_REG_P (operands[0]))
591 if (FP_REG_P (operands[1]))
592 return \"fcmp%.x %1,%0\";
594 return \"fcmp%.s %f1,%0\";
596 cc_status.flags |= CC_REVERSED;
597 return \"fcmp%.s %f0,%1\";
601 ;; Recognizers for btst instructions.
604 [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "do")
606 (minus:SI (const_int 7)
607 (match_operand:SI 1 "general_operand" "di"))))]
609 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
612 [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "d")
614 (minus:SI (const_int 31)
615 (match_operand:SI 1 "general_operand" "di"))))]
617 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
619 ;; The following two patterns are like the previous two
620 ;; except that they use the fact that bit-number operands
621 ;; are automatically masked to 3 or 5 bits.
624 [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "do")
626 (minus:SI (const_int 7)
628 (match_operand:SI 1 "register_operand" "d")
631 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
634 [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "d")
636 (minus:SI (const_int 31)
638 (match_operand:SI 1 "register_operand" "d")
641 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
643 ;; Nonoffsettable mem refs are ok in this one pattern
644 ;; since we don't try to adjust them.
646 [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "md")
648 (match_operand:SI 1 "const_int_operand" "n")))]
649 "(unsigned) INTVAL (operands[1]) < 8"
652 operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1]));
653 return output_btst (operands, operands[1], operands[0], insn, 7);
657 [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "do")
659 (match_operand:SI 1 "const_int_operand" "n")))]
663 if (GET_CODE (operands[0]) == MEM)
665 operands[0] = adj_offsettable_operand (operands[0],
666 INTVAL (operands[1]) / 8);
667 operands[1] = gen_rtx (CONST_INT, VOIDmode,
668 7 - INTVAL (operands[1]) % 8);
669 return output_btst (operands, operands[1], operands[0], insn, 7);
671 operands[1] = gen_rtx (CONST_INT, VOIDmode,
672 31 - INTVAL (operands[1]));
673 return output_btst (operands, operands[1], operands[0], insn, 31);
679 ;; A special case in which it is not desirable
680 ;; to reload the constant into a data register.
682 [(set (match_operand:SI 0 "push_operand" "=m")
683 (match_operand:SI 1 "const_int_operand" "J"))]
684 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
687 if (operands[1] == const0_rtx)
688 return \"clr%.l %0\";
693 ;(define_insn "swapsi"
694 ; [(set (match_operand:SI 0 "general_operand" "+r")
695 ; (match_operand:SI 1 "general_operand" "+r"))
696 ; (set (match_dup 1) (match_dup 0))]
700 ;; Special case of fullword move when source is zero.
701 ;; The reason this is special is to avoid loading a zero
702 ;; into a data reg with moveq in order to store it elsewhere.
705 [(set (match_operand:SI 0 "general_operand" "=g")
707 ;; clr insns on 68000 read before writing.
708 ;; This isn't so on the 68010, but we have no alternative for it.
710 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
713 if (ADDRESS_REG_P (operands[0]))
714 return \"sub%.l %0,%0\";
715 /* moveq is faster on the 68000. */
716 if (DATA_REG_P (operands[0]) && !TARGET_68020)
717 #if defined(MOTOROLA) && !defined(CRDS)
718 return \"moveq%.l %#0,%0\";
720 return \"moveq %#0,%0\";
722 return \"clr%.l %0\";
725 ;; General case of fullword move.
727 ;; This is the main "hook" for PIC code. When generating
728 ;; PIC, movsi is responsible for determining when the source address
729 ;; needs PIC relocation and appropriately calling legitimize_pic_address
730 ;; to perform the actual relocation.
732 ;; In both the PIC and non-PIC cases the patterns generated will
733 ;; matched by the next define_insn.
734 (define_expand "movsi"
735 [(set (match_operand:SI 0 "general_operand" "")
736 (match_operand:SI 1 "general_operand" ""))]
740 if (flag_pic && symbolic_operand (operands[1], SImode))
742 /* The source is an address which requires PIC relocation.
743 Call legitimize_pic_address with the source, mode, and a relocation
744 register (a new pseudo, or the final destination if reload_in_progress
745 is set). Then fall through normally */
746 extern rtx legitimize_pic_address();
747 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
748 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
752 ;; General case of fullword move. The register constraints
753 ;; force integer constants in range for a moveq to be reloaded
754 ;; if they are headed for memory.
756 ;; Notes: make sure no alternative allows g vs g.
757 ;; We don't allow f-regs since fixed point cannot go in them.
758 ;; We do allow y and x regs since fixed point is allowed in them.
759 [(set (match_operand:SI 0 "general_operand" "=g,da,y,!*x*r*m")
760 (match_operand:SI 1 "general_operand" "daymKs,i,g,*x*r*m"))]
764 if (which_alternative == 3)
765 return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\";
766 if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0]))
767 return \"fpmove%.l %x1,%x0\";
768 if (GET_CODE (operands[1]) == CONST_INT)
770 if (operands[1] == const0_rtx
771 && (DATA_REG_P (operands[0])
772 || GET_CODE (operands[0]) == MEM)
773 /* clr insns on 68000 read before writing.
774 This isn't so on the 68010, but we have no alternative for it. */
776 || !(GET_CODE (operands[0]) == MEM
777 && MEM_VOLATILE_P (operands[0]))))
778 return \"clr%.l %0\";
779 else if (DATA_REG_P (operands[0]))
780 return output_move_const_into_data_reg (operands);
781 else if (ADDRESS_REG_P (operands[0])
782 && INTVAL (operands[1]) < 0x8000
783 && INTVAL (operands[1]) >= -0x8000)
784 return \"move%.w %1,%0\";
785 else if (push_operand (operands[0], SImode)
786 && INTVAL (operands[1]) < 0x8000
787 && INTVAL (operands[1]) >= -0x8000)
790 else if ((GET_CODE (operands[1]) == SYMBOL_REF
791 || GET_CODE (operands[1]) == CONST)
792 && push_operand (operands[0], SImode))
794 else if ((GET_CODE (operands[1]) == SYMBOL_REF
795 || GET_CODE (operands[1]) == CONST)
796 && ADDRESS_REG_P (operands[0]))
797 return \"lea %a1,%0\";
798 return \"move%.l %1,%0\";
802 [(set (match_operand:HI 0 "general_operand" "=g")
803 (match_operand:HI 1 "general_operand" "g"))]
807 if (GET_CODE (operands[1]) == CONST_INT)
809 if (operands[1] == const0_rtx
810 && (DATA_REG_P (operands[0])
811 || GET_CODE (operands[0]) == MEM)
812 /* clr insns on 68000 read before writing.
813 This isn't so on the 68010, but we have no alternative for it. */
815 || !(GET_CODE (operands[0]) == MEM
816 && MEM_VOLATILE_P (operands[0]))))
817 return \"clr%.w %0\";
818 else if (DATA_REG_P (operands[0])
819 && INTVAL (operands[1]) < 128
820 && INTVAL (operands[1]) >= -128)
822 #if defined(MOTOROLA) && !defined(CRDS)
823 return \"moveq%.l %1,%0\";
825 return \"moveq %1,%0\";
828 else if (INTVAL (operands[1]) < 0x8000
829 && INTVAL (operands[1]) >= -0x8000)
830 return \"move%.w %1,%0\";
832 else if (CONSTANT_P (operands[1]))
833 return \"move%.l %1,%0\";
835 /* Recognize the insn before a tablejump, one that refers
836 to a table of offsets. Such an insn will need to refer
837 to a label on the insn. So output one. Use the label-number
838 of the table of offsets to generate this label. This code,
839 and similar code below, assumes that there will be at most one
840 reference to each table. */
841 if (GET_CODE (operands[1]) == MEM
842 && GET_CODE (XEXP (operands[1], 0)) == PLUS
843 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF
844 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS)
846 rtx labelref = XEXP (XEXP (operands[1], 0), 1);
847 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
849 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
850 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
852 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
853 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
855 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
856 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
857 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
858 #ifdef SGS_SWITCH_TABLES
859 /* Set flag saying we need to define the symbol
860 LD%n (with value L%n-LI%n) at the end of the switch table. */
861 switch_table_difference_label_flag = 1;
862 #endif /* SGS_SWITCH_TABLES */
863 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
865 #endif /* SGS_NO_LI */
866 return \"move%.w %1,%0\";
869 (define_insn "movstricthi"
870 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
871 (match_operand:HI 1 "general_operand" "rmn"))]
875 if (GET_CODE (operands[1]) == CONST_INT)
877 if (operands[1] == const0_rtx
878 && (DATA_REG_P (operands[0])
879 || GET_CODE (operands[0]) == MEM)
880 /* clr insns on 68000 read before writing.
881 This isn't so on the 68010, but we have no alternative for it. */
883 || !(GET_CODE (operands[0]) == MEM
884 && MEM_VOLATILE_P (operands[0]))))
885 return \"clr%.w %0\";
887 return \"move%.w %1,%0\";
891 [(set (match_operand:QI 0 "general_operand" "=d,*a,m,m,?*a")
892 (match_operand:QI 1 "general_operand" "dmi*a,d*a,dmi,?*a,m"))]
898 /* This is probably useless, since it loses for pushing a struct
899 of several bytes a byte at a time. */
900 if (GET_CODE (operands[0]) == MEM
901 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
902 && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx
903 && ! ADDRESS_REG_P (operands[1]))
905 xoperands[1] = operands[1];
907 = gen_rtx (MEM, QImode,
908 gen_rtx (PLUS, VOIDmode, stack_pointer_rtx, const1_rtx));
909 /* Just pushing a byte puts it in the high byte of the halfword. */
910 /* We must put it in the low-order, high-numbered byte. */
911 output_asm_insn (\"move%.b %1,%-\;move%.b %@,%2\", xoperands);
915 /* Moving a byte into an address register is not possible. */
916 /* Use d0 as an intermediate, but don't clobber its contents. */
917 if (ADDRESS_REG_P (operands[0]) && GET_CODE (operands[1]) == MEM)
919 /* ??? For 2.5, don't allow this choice and use secondary reloads
922 See if the address register is used in the address. If it
923 is, we have to generate a more complex sequence than those below. */
924 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
925 operands[1], NULL_RTX))
927 /* See if the stack pointer is used in the address. If it isn't,
928 we can push d0 or d1 (the insn can't use both of them) on
929 the stack, perform our move into d0/d1, copy the byte from d0/1,
931 if (! reg_mentioned_p (stack_pointer_rtx, operands[1]))
933 if (! refers_to_regno_p (0, 1, operands[1], NULL_RTX))
934 return \"move%.l %/d0,%-\;move%.b %1,%/d0\;move%.l %/d0,%0\;move%.l %+,%/d0\";
936 return \"move%.l %/d1,%-\;move%.b %1,%/d1\;move%.l %/d1,%0\;move%.l %+,%/d1\";
940 /* Otherwise, we know that d0 cannot be used in the address
941 (since sp and one address register is). Assume that sp is
942 being used as a base register and replace the address
943 register that is our operand[0] with d0. */
944 rtx reg_map[FIRST_PSEUDO_REGISTER];
947 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
950 reg_map[REGNO (operands[0])] = gen_rtx (REG, Pmode, 0);
951 operands[1] = copy_rtx (operands[1]);
952 replace_regs (operands[1], reg_map, FIRST_PSEUDO_REGISTER, 0);
953 return \"exg %/d0,%0\;move%.b %1,%/d0\;exg %/d0,%0\";
957 /* If the address of operand 1 uses d0, choose d1 as intermediate. */
958 if (refers_to_regno_p (0, 1, operands[1], NULL_RTX))
959 return \"exg %/d1,%0\;move%.b %1,%/d1\;exg %/d1,%0\";
960 /* Otherwise d0 is usable.
961 (An effective address on the 68k can't use two d-regs.) */
963 return \"exg %/d0,%0\;move%.b %1,%/d0\;exg %/d0,%0\";
966 /* Likewise for moving from an address reg. */
967 if (ADDRESS_REG_P (operands[1]) && GET_CODE (operands[0]) == MEM)
969 /* ??? For 2.5, don't allow this choice and use secondary reloads
972 See if the address register is used in the address. If it
973 is, we have to generate a more complex sequence than those below. */
974 if (refers_to_regno_p (REGNO (operands[1]), REGNO (operands[1]) + 1,
975 operands[0], NULL_RTX))
977 /* See if the stack pointer is used in the address. If it isn't,
978 we can push d0 or d1 (the insn can't use both of them) on
979 the stack, copy the byte to d0/1, perform our move from d0/d1,
981 if (! reg_mentioned_p (stack_pointer_rtx, operands[0]))
983 if (! refers_to_regno_p (0, 1, operands[0], NULL_RTX))
984 return \"move%.l %/d0,%-\;move%.l %1,%/d0\;move%.b %/d0,%0\;move%.l %+,%/d0\";
986 return \"move%.l %/d1,%-\;move%.l %1,%/d1\;move%.b %/d1,%0\;move%.l %+,%/d1\";
990 /* Otherwise, we know that d0 cannot be used in the address
991 (since sp and one address register is). Assume that sp is
992 being used as a base register and replace the address
993 register that is our operand[1] with d0. */
994 rtx reg_map[FIRST_PSEUDO_REGISTER];
997 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1000 reg_map[REGNO (operands[1])] = gen_rtx (REG, Pmode, 0);
1001 operands[0] = copy_rtx (operands[0]);
1002 replace_regs (operands[0], reg_map, FIRST_PSEUDO_REGISTER, 0);
1003 return \"exg %/d0,%1\;move%.b %/d0,%0\;exg %/d0,%1\";
1007 if (refers_to_regno_p (0, 1, operands[0], NULL_RTX))
1008 return \"exg %/d1,%1\;move%.b %/d1,%0\;exg %/d1,%1\";
1010 return \"exg %/d0,%1\;move%.b %/d0,%0\;exg %/d0,%1\";
1013 /* clr and st insns on 68000 read before writing.
1014 This isn't so on the 68010, but we have no alternative for it. */
1016 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))
1018 if (operands[1] == const0_rtx)
1019 return \"clr%.b %0\";
1020 if (GET_CODE (operands[1]) == CONST_INT
1021 && INTVAL (operands[1]) == -1)
1027 if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
1028 return \"move%.l %1,%0\";
1029 if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
1030 return \"move%.w %1,%0\";
1031 return \"move%.b %1,%0\";
1034 (define_insn "movstrictqi"
1035 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
1036 (match_operand:QI 1 "general_operand" "dmn"))]
1040 if (operands[1] == const0_rtx
1041 /* clr insns on 68000 read before writing.
1042 This isn't so on the 68010, but we have no alternative for it. */
1044 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1045 return \"clr%.b %0\";
1046 return \"move%.b %1,%0\";
1049 (define_insn "movsf"
1050 [(set (match_operand:SF 0 "general_operand" "=rmf,x,y,rm,!x,!rm")
1051 (match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))]
1052 ; [(set (match_operand:SF 0 "general_operand" "=rmf")
1053 ; (match_operand:SF 1 "general_operand" "rmfF"))]
1057 if (which_alternative >= 4)
1058 return \"fpmove%.s %1,fpa0\;fpmove%.s fpa0,%0\";
1059 if (FPA_REG_P (operands[0]))
1061 if (FPA_REG_P (operands[1]))
1062 return \"fpmove%.s %x1,%x0\";
1063 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1064 return output_move_const_single (operands);
1065 else if (FP_REG_P (operands[1]))
1066 return \"fmove%.s %1,sp@-\;fpmove%.d sp@+, %0\";
1067 return \"fpmove%.s %x1,%x0\";
1069 if (FPA_REG_P (operands[1]))
1071 if (FP_REG_P (operands[0]))
1072 return \"fpmove%.s %x1,sp@-\;fmove%.s sp@+,%0\";
1074 return \"fpmove%.s %x1,%x0\";
1076 if (FP_REG_P (operands[0]))
1078 if (FP_REG_P (operands[1]))
1079 return \"f%$move%.x %1,%0\";
1080 else if (ADDRESS_REG_P (operands[1]))
1081 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
1082 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1083 return output_move_const_single (operands);
1084 return \"f%$move%.s %f1,%0\";
1086 if (FP_REG_P (operands[1]))
1088 if (ADDRESS_REG_P (operands[0]))
1089 return \"fmove%.s %1,%-\;move%.l %+,%0\";
1090 return \"fmove%.s %f1,%0\";
1092 return \"move%.l %1,%0\";
1095 (define_insn "movdf"
1096 [(set (match_operand:DF 0 "general_operand" "=rm,rf,rf,&rof<>,y,rm,x,!x,!rm")
1097 (match_operand:DF 1 "general_operand" "rf,m,0,rofE<>,rmE,y,xH,rm,x"))]
1098 ; [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>")
1099 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
1103 if (which_alternative == 7)
1104 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1105 if (FPA_REG_P (operands[0]))
1107 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1108 return output_move_const_double (operands);
1109 if (FP_REG_P (operands[1]))
1110 return \"fmove%.d %1,sp@-\;fpmove%.d sp@+,%x0\";
1111 return \"fpmove%.d %x1,%x0\";
1113 else if (FPA_REG_P (operands[1]))
1115 if (FP_REG_P(operands[0]))
1116 return \"fpmove%.d %x1,sp@-\;fmoved sp@+,%0\";
1118 return \"fpmove%.d %x1,%x0\";
1120 if (FP_REG_P (operands[0]))
1122 if (FP_REG_P (operands[1]))
1123 return \"f%&move%.x %1,%0\";
1124 if (REG_P (operands[1]))
1127 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1128 output_asm_insn (\"move%.l %1,%-\", xoperands);
1129 output_asm_insn (\"move%.l %1,%-\", operands);
1130 return \"f%&move%.d %+,%0\";
1132 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1133 return output_move_const_double (operands);
1134 return \"f%&move%.d %f1,%0\";
1136 else if (FP_REG_P (operands[1]))
1138 if (REG_P (operands[0]))
1140 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1141 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1142 return \"move%.l %+,%0\";
1145 return \"fmove%.d %f1,%0\";
1147 return output_move_double (operands);
1151 (define_expand "movxf"
1152 [(set (match_operand:XF 0 "nonimmediate_operand" "")
1153 (match_operand:XF 1 "general_operand" ""))]
1157 if (CONSTANT_P (operands[1]))
1159 operands[1] = force_const_mem (XFmode, operands[1]);
1160 if (! memory_address_p (XFmode, XEXP (operands[1], 0))
1161 && ! reload_in_progress)
1162 operands[1] = change_address (operands[1], XFmode,
1163 XEXP (operands[1], 0));
1168 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f")
1169 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r"))]
1173 if (FP_REG_P (operands[0]))
1175 if (FP_REG_P (operands[1]))
1176 return \"fmove%.x %1,%0\";
1177 if (REG_P (operands[1]))
1180 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
1181 output_asm_insn (\"move%.l %1,%-\", xoperands);
1182 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1183 output_asm_insn (\"move%.l %1,%-\", xoperands);
1184 output_asm_insn (\"move%.l %1,%-\", operands);
1185 return \"fmove%.x %+,%0\";
1187 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1188 return \"fmove%.x %1,%0\";
1189 return \"fmove%.x %f1,%0\";
1191 if (REG_P (operands[0]))
1193 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1194 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1195 output_asm_insn (\"move%.l %+,%0\", operands);
1196 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1197 return \"move%.l %+,%0\";
1199 return \"fmove%.x %f1,%0\";
1204 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1205 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1209 if (FP_REG_P (operands[0]))
1211 if (FP_REG_P (operands[1]))
1212 return \"fmove%.x %1,%0\";
1213 if (REG_P (operands[1]))
1216 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
1217 output_asm_insn (\"move%.l %1,%-\", xoperands);
1218 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1219 output_asm_insn (\"move%.l %1,%-\", xoperands);
1220 output_asm_insn (\"move%.l %1,%-\", operands);
1221 return \"fmove%.x %+,%0\";
1223 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1224 return \"fmove%.x %1,%0\";
1225 return \"fmove%.x %f1,%0\";
1227 if (FP_REG_P (operands[1]))
1229 if (REG_P (operands[0]))
1231 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1232 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1233 output_asm_insn (\"move%.l %+,%0\", operands);
1234 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1235 return \"move%.l %+,%0\";
1238 return \"fmove%.x %f1,%0\";
1240 return output_move_double (operands);
1244 ;; movdi can apply to fp regs in some cases
1245 (define_insn "movdi"
1246 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1247 [(set (match_operand:DI 0 "general_operand" "=rm,r,&ro<>,y,rm,!*x,!rm")
1248 (match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))]
1249 ; [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm")
1250 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))]
1251 ; [(set (match_operand:DI 0 "general_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1252 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1256 if (which_alternative == 8)
1257 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1258 if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
1259 return \"fpmove%.d %x1,%x0\";
1260 if (FP_REG_P (operands[0]))
1262 if (FP_REG_P (operands[1]))
1263 return \"fmove%.x %1,%0\";
1264 if (REG_P (operands[1]))
1267 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1268 output_asm_insn (\"move%.l %1,%-\", xoperands);
1269 output_asm_insn (\"move%.l %1,%-\", operands);
1270 return \"fmove%.d %+,%0\";
1272 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1273 return output_move_const_double (operands);
1274 return \"fmove%.d %f1,%0\";
1276 else if (FP_REG_P (operands[1]))
1278 if (REG_P (operands[0]))
1280 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1281 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1282 return \"move%.l %+,%0\";
1285 return \"fmove%.d %f1,%0\";
1287 return output_move_double (operands);
1291 ;; Thus goes after the move instructions
1292 ;; because the move instructions are better (require no spilling)
1293 ;; when they can apply. It goes before the add/sub insns
1294 ;; so we will prefer it to them.
1296 (define_insn "pushasi"
1297 [(set (match_operand:SI 0 "push_operand" "=m")
1298 (match_operand:SI 1 "address_operand" "p"))]
1302 ;; truncation instructions
1303 (define_insn "truncsiqi2"
1304 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1306 (match_operand:SI 1 "general_operand" "doJ,i")))]
1310 if (GET_CODE (operands[0]) == REG)
1312 /* Must clear condition codes, since the move.l bases them on
1313 the entire 32 bits, not just the desired 8 bits. */
1315 return \"move%.l %1,%0\";
1317 if (GET_CODE (operands[1]) == MEM)
1318 operands[1] = adj_offsettable_operand (operands[1], 3);
1319 return \"move%.b %1,%0\";
1322 (define_insn "trunchiqi2"
1323 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1325 (match_operand:HI 1 "general_operand" "doJ,i")))]
1329 if (GET_CODE (operands[0]) == REG
1330 && (GET_CODE (operands[1]) == MEM
1331 || GET_CODE (operands[1]) == CONST_INT))
1333 /* Must clear condition codes, since the move.w bases them on
1334 the entire 16 bits, not just the desired 8 bits. */
1336 return \"move%.w %1,%0\";
1338 if (GET_CODE (operands[0]) == REG)
1340 /* Must clear condition codes, since the move.l bases them on
1341 the entire 32 bits, not just the desired 8 bits. */
1343 return \"move%.l %1,%0\";
1345 if (GET_CODE (operands[1]) == MEM)
1346 operands[1] = adj_offsettable_operand (operands[1], 1);
1347 return \"move%.b %1,%0\";
1350 (define_insn "truncsihi2"
1351 [(set (match_operand:HI 0 "general_operand" "=dm,d")
1353 (match_operand:SI 1 "general_operand" "roJ,i")))]
1357 if (GET_CODE (operands[0]) == REG)
1359 /* Must clear condition codes, since the move.l bases them on
1360 the entire 32 bits, not just the desired 8 bits. */
1362 return \"move%.l %1,%0\";
1364 if (GET_CODE (operands[1]) == MEM)
1365 operands[1] = adj_offsettable_operand (operands[1], 2);
1366 return \"move%.w %1,%0\";
1369 ;; zero extension instructions
1371 ;; this one is the canonical form for (lshiftrt:DI x 32)
1372 (define_insn "zero_extendsidi2"
1373 [(set (match_operand:DI 0 "general_operand" "ro,<,>")
1374 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm,rm,rm")))]
1379 if (which_alternative == 2)
1380 return \"clr%.l %0\;move%.l %1,%0\";
1381 if (which_alternative == 1)
1382 return \"move%.l %1,%0\;clr%.l %0\";
1383 if (GET_CODE (operands[0]) == REG)
1384 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1386 operands[2] = adj_offsettable_operand (operands[0], 4);
1387 if (ADDRESS_REG_P (operands[0]))
1388 return \"move%.l %1,%2\;sub%.l %0,%0\";
1390 return \"move%.l %1,%2\;clr%.l %0\";
1393 (define_expand "zero_extendhisi2"
1394 [(set (match_operand:SI 0 "register_operand" "")
1396 (set (strict_low_part (match_dup 2))
1397 (match_operand:HI 1 "general_operand" ""))]
1401 operands[1] = make_safe_from (operands[1], operands[0]);
1402 if (GET_CODE (operands[0]) == SUBREG)
1403 operands[2] = gen_rtx (SUBREG, HImode, SUBREG_REG (operands[0]),
1404 SUBREG_WORD (operands[0]));
1406 operands[2] = gen_rtx (SUBREG, HImode, operands[0], 0);
1409 (define_expand "zero_extendqihi2"
1410 [(set (match_operand:HI 0 "register_operand" "")
1412 (set (strict_low_part (match_dup 2))
1413 (match_operand:QI 1 "general_operand" ""))]
1417 operands[1] = make_safe_from (operands[1], operands[0]);
1418 if (GET_CODE (operands[0]) == SUBREG)
1419 operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]),
1420 SUBREG_WORD (operands[0]));
1422 operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0);
1425 (define_expand "zero_extendqisi2"
1426 [(set (match_operand:SI 0 "register_operand" "")
1428 (set (strict_low_part (match_dup 2))
1429 (match_operand:QI 1 "general_operand" ""))]
1433 operands[1] = make_safe_from (operands[1], operands[0]);
1434 if (GET_CODE (operands[0]) == SUBREG)
1435 operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]),
1436 SUBREG_WORD (operands[0]));
1438 operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0);
1441 ;; Patterns to recognize zero-extend insns produced by the combiner.
1442 ;; We don't allow both operands in memory, because of aliasing problems.
1443 ;; Explicitly disallow two memory operands via the condition since reloading
1444 ;; of this case will result in worse code than the uncombined patterns.
1447 [(set (match_operand:SI 0 "general_operand" "=do<>,d<")
1448 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1449 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1452 if (DATA_REG_P (operands[0]))
1454 if (GET_CODE (operands[1]) == REG
1455 && REGNO (operands[0]) == REGNO (operands[1]))
1456 return \"and%.l %#0xFFFF,%0\";
1457 if (reg_mentioned_p (operands[0], operands[1]))
1458 return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\";
1459 return \"clr%.l %0\;move%.w %1,%0\";
1461 else if (GET_CODE (operands[0]) == MEM
1462 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1463 return \"move%.w %1,%0\;clr%.w %0\";
1464 else if (GET_CODE (operands[0]) == MEM
1465 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1466 return \"clr%.w %0\;move%.w %1,%0\";
1469 output_asm_insn (\"clr%.w %0\", operands);
1470 operands[0] = adj_offsettable_operand (operands[0], 2);
1471 return \"move%.w %1,%0\";
1476 [(set (match_operand:HI 0 "general_operand" "=do<>,d")
1477 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1478 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1481 if (DATA_REG_P (operands[0]))
1483 if (GET_CODE (operands[1]) == REG
1484 && REGNO (operands[0]) == REGNO (operands[1]))
1485 return \"and%.w %#0xFF,%0\";
1486 if (reg_mentioned_p (operands[0], operands[1]))
1487 return \"move%.b %1,%0\;and%.w %#0xFF,%0\";
1488 return \"clr%.w %0\;move%.b %1,%0\";
1490 else if (GET_CODE (operands[0]) == MEM
1491 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1493 if (REGNO (XEXP (XEXP (operands[0], 0), 0))
1494 == STACK_POINTER_REGNUM)
1496 output_asm_insn (\"clr%.w %-\", operands);
1497 operands[0] = gen_rtx (MEM, GET_MODE (operands[0]),
1498 plus_constant (stack_pointer_rtx, 1));
1499 return \"move%.b %1,%0\";
1502 return \"move%.b %1,%0\;clr%.b %0\";
1504 else if (GET_CODE (operands[0]) == MEM
1505 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1506 return \"clr%.b %0\;move%.b %1,%0\";
1509 output_asm_insn (\"clr%.b %0\", operands);
1510 operands[0] = adj_offsettable_operand (operands[0], 1);
1511 return \"move%.b %1,%0\";
1516 [(set (match_operand:SI 0 "general_operand" "=do<>,d")
1517 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1518 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1521 if (DATA_REG_P (operands[0]))
1523 if (GET_CODE (operands[1]) == REG
1524 && REGNO (operands[0]) == REGNO (operands[1]))
1525 return \"and%.l %#0xFF,%0\";
1526 if (reg_mentioned_p (operands[0], operands[1]))
1527 return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
1528 return \"clr%.l %0\;move%.b %1,%0\";
1530 else if (GET_CODE (operands[0]) == MEM
1531 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1533 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1536 return \"clr%.l -(%0)\;move%.b %1,3(%0)\";
1538 return \"clr%.l -(%0)\;move%.b %1,(3,%0)\";
1541 return \"clrl %0@-\;moveb %1,%0@(3)\";
1544 else if (GET_CODE (operands[0]) == MEM
1545 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1547 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1550 return \"clr%.l (%0)+\;move%.b %1,-1(%0)\";
1552 return \"clr%.l (%0)+\;move%.b %1,(-1,%0)\";
1555 return \"clrl %0@+\;moveb %1,%0@(-1)\";
1560 output_asm_insn (\"clr%.l %0\", operands);
1561 operands[0] = adj_offsettable_operand (operands[0], 3);
1562 return \"move%.b %1,%0\";
1566 ;; sign extension instructions
1568 (define_insn "extendqidi2"
1569 [(set (match_operand:DI 0 "register_operand" "=d")
1571 (match_operand:QI 1 "general_operand" "rm")))]
1576 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1578 return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
1580 return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
1583 (define_insn "extendhidi2"
1584 [(set (match_operand:DI 0 "register_operand" "=d")
1586 (match_operand:HI 1 "general_operand" "rm")))]
1591 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1593 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
1595 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
1598 (define_insn "extendsidi2"
1599 [(set (match_operand:DI 0 "register_operand" "=d")
1601 (match_operand:SI 1 "general_operand" "rm")))]
1606 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1608 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
1610 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
1613 ;; Special case when one can avoid register clobbering, copy and test
1614 ;; Maybe there is a way to make that the general case, by forcing the
1615 ;; result of the SI tree to be in the lower register of the DI target
1617 (define_insn "extendplussidi"
1618 [(set (match_operand:DI 0 "register_operand" "=d")
1619 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1620 (match_operand:SI 2 "general_operand" "rmn"))))]
1625 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1626 if (GET_CODE (operands[1]) == CONST_INT
1627 && (unsigned) INTVAL (operands[1]) > 8)
1629 rtx tmp = operands[1];
1631 operands[1] = operands[2];
1635 return \"move%.l %2,%3\;add%.l %1,%3\;smi %0\;extb%.l %0\";
1637 return \"move%.l %2,%3\;add%.l %1,%3\;smi %0\;ext%.w %0\;ext%.l %0\";
1640 (define_insn "extendhisi2"
1641 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1643 (match_operand:HI 1 "nonimmediate_operand" "0,rm")))]
1647 if (ADDRESS_REG_P (operands[0]))
1648 return \"move%.w %1,%0\";
1649 return \"ext%.l %0\";
1652 (define_insn "extendqihi2"
1653 [(set (match_operand:HI 0 "general_operand" "=d")
1654 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1658 (define_insn "extendqisi2"
1659 [(set (match_operand:SI 0 "general_operand" "=d")
1660 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1664 ;; Conversions between float and double.
1666 (define_expand "extendsfdf2"
1667 [(set (match_operand:DF 0 "general_operand" "")
1669 (match_operand:SF 1 "general_operand" "")))]
1670 "TARGET_68881 || TARGET_FPA"
1674 [(set (match_operand:DF 0 "general_operand" "=x,y")
1676 (match_operand:SF 1 "general_operand" "xH,rmF")))]
1681 [(set (match_operand:DF 0 "general_operand" "=*fdm,f")
1683 (match_operand:SF 1 "general_operand" "f,dmF")))]
1687 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1689 if (REGNO (operands[0]) == REGNO (operands[1]))
1691 /* Extending float to double in an fp-reg is a no-op.
1692 NOTICE_UPDATE_CC has already assumed that the
1693 cc will be set. So cancel what it did. */
1694 cc_status = cc_prev_status;
1697 return \"f%&move%.x %1,%0\";
1699 if (FP_REG_P (operands[0]))
1700 return \"f%&move%.s %f1,%0\";
1701 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1703 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1704 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1705 return \"move%.l %+,%0\";
1707 return \"fmove%.d %f1,%0\";
1710 ;; This cannot output into an f-reg because there is no way to be
1711 ;; sure of truncating in that case.
1712 ;; But on the Sun FPA, we can be sure.
1713 (define_expand "truncdfsf2"
1714 [(set (match_operand:SF 0 "general_operand" "")
1716 (match_operand:DF 1 "general_operand" "")))]
1717 "TARGET_68881 || TARGET_FPA"
1721 [(set (match_operand:SF 0 "general_operand" "=x,y")
1723 (match_operand:DF 1 "general_operand" "xH,rmF")))]
1727 ;; On the '040 we can truncate in a register accurately and easily.
1729 [(set (match_operand:SF 0 "general_operand" "=f")
1731 (match_operand:DF 1 "general_operand" "fmG")))]
1735 if (FP_REG_P (operands[1]))
1736 return \"f%$move%.x %1,%0\";
1737 return \"f%$move%.d %f1,%0\";
1741 [(set (match_operand:SF 0 "general_operand" "=dm")
1743 (match_operand:DF 1 "general_operand" "f")))]
1747 ;; Conversion between fixed point and floating point.
1748 ;; Note that among the fix-to-float insns
1749 ;; the ones that start with SImode come first.
1750 ;; That is so that an operand that is a CONST_INT
1751 ;; (and therefore lacks a specific machine mode).
1752 ;; will be recognized as SImode (which is always valid)
1753 ;; rather than as QImode or HImode.
1755 (define_expand "floatsisf2"
1756 [(set (match_operand:SF 0 "general_operand" "")
1757 (float:SF (match_operand:SI 1 "general_operand" "")))]
1758 "TARGET_68881 || TARGET_FPA"
1762 [(set (match_operand:SF 0 "general_operand" "=y,x")
1763 (float:SF (match_operand:SI 1 "general_operand" "rmi,x")))]
1768 [(set (match_operand:SF 0 "general_operand" "=f")
1769 (float:SF (match_operand:SI 1 "general_operand" "dmi")))]
1773 (define_expand "floatsidf2"
1774 [(set (match_operand:DF 0 "general_operand" "")
1775 (float:DF (match_operand:SI 1 "general_operand" "")))]
1776 "TARGET_68881 || TARGET_FPA"
1780 [(set (match_operand:DF 0 "general_operand" "=y,x")
1781 (float:DF (match_operand:SI 1 "general_operand" "rmi,x")))]
1786 [(set (match_operand:DF 0 "general_operand" "=f")
1787 (float:DF (match_operand:SI 1 "general_operand" "dmi")))]
1791 (define_insn "floathisf2"
1792 [(set (match_operand:SF 0 "general_operand" "=f")
1793 (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
1797 (define_insn "floathidf2"
1798 [(set (match_operand:DF 0 "general_operand" "=f")
1799 (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
1803 (define_insn "floatqisf2"
1804 [(set (match_operand:SF 0 "general_operand" "=f")
1805 (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
1809 (define_insn "floatqidf2"
1810 [(set (match_operand:DF 0 "general_operand" "=f")
1811 (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
1815 ;; New routines to convert floating-point values to integers
1816 ;; to be used on the '040. These should be faster than trapping
1817 ;; into the kernel to emulate fintrz. They should also be faster
1818 ;; than calling the subroutines fixsfsi or fixdfsi.
1820 (define_insn "fix_truncdfsi2"
1821 [(set (match_operand:SI 0 "general_operand" "=dm")
1822 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1823 (clobber (match_scratch:SI 2 "=d"))
1824 (clobber (match_scratch:SI 3 "=d"))]
1825 "TARGET_68881 && TARGET_68040"
1829 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\";
1832 (define_insn "fix_truncdfhi2"
1833 [(set (match_operand:HI 0 "general_operand" "=dm")
1834 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1835 (clobber (match_scratch:SI 2 "=d"))
1836 (clobber (match_scratch:SI 3 "=d"))]
1837 "TARGET_68881 && TARGET_68040"
1841 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\";
1844 (define_insn "fix_truncdfqi2"
1845 [(set (match_operand:QI 0 "general_operand" "=dm")
1846 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1847 (clobber (match_scratch:SI 2 "=d"))
1848 (clobber (match_scratch:SI 3 "=d"))]
1849 "TARGET_68881 && TARGET_68040"
1853 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\";
1856 ;; Convert a float to a float whose value is an integer.
1857 ;; This is the first stage of converting it to an integer type.
1859 (define_insn "ftruncdf2"
1860 [(set (match_operand:DF 0 "general_operand" "=f")
1861 (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
1862 "TARGET_68881 && !TARGET_68040"
1865 if (FP_REG_P (operands[1]))
1866 return \"fintrz%.x %f1,%0\";
1867 return \"fintrz%.d %f1,%0\";
1870 (define_insn "ftruncsf2"
1871 [(set (match_operand:SF 0 "general_operand" "=f")
1872 (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
1873 "TARGET_68881 && !TARGET_68040"
1876 if (FP_REG_P (operands[1]))
1877 return \"fintrz%.x %f1,%0\";
1878 return \"fintrz%.s %f1,%0\";
1881 ;; Convert a float whose value is an integer
1882 ;; to an actual integer. Second stage of converting float to integer type.
1883 (define_insn "fixsfqi2"
1884 [(set (match_operand:QI 0 "general_operand" "=dm")
1885 (fix:QI (match_operand:SF 1 "general_operand" "f")))]
1889 (define_insn "fixsfhi2"
1890 [(set (match_operand:HI 0 "general_operand" "=dm")
1891 (fix:HI (match_operand:SF 1 "general_operand" "f")))]
1895 (define_insn "fixsfsi2"
1896 [(set (match_operand:SI 0 "general_operand" "=dm")
1897 (fix:SI (match_operand:SF 1 "general_operand" "f")))]
1901 (define_insn "fixdfqi2"
1902 [(set (match_operand:QI 0 "general_operand" "=dm")
1903 (fix:QI (match_operand:DF 1 "general_operand" "f")))]
1907 (define_insn "fixdfhi2"
1908 [(set (match_operand:HI 0 "general_operand" "=dm")
1909 (fix:HI (match_operand:DF 1 "general_operand" "f")))]
1913 (define_insn "fixdfsi2"
1914 [(set (match_operand:SI 0 "general_operand" "=dm")
1915 (fix:SI (match_operand:DF 1 "general_operand" "f")))]
1919 ;; Convert a float to an integer.
1920 ;; On the Sun FPA, this is done in one step.
1923 [(set (match_operand:SI 0 "general_operand" "=x,y")
1924 (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "xH,rmF"))))]
1929 [(set (match_operand:SI 0 "general_operand" "=x,y")
1930 (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "xH,rmF"))))]
1936 (define_insn "adddia_sexthishl32"
1937 [(set (match_operand:DI 0 "register_operand" "+a")
1938 (plus:DI (ashift:DI (sign_extend:DI
1939 (match_operand:HI 1 "general_operand" "rm"))
1946 return \"add%.w %1,%0\";
1949 (define_insn "adddid_sexthishl32"
1950 [(set (match_operand:DI 0 "register_operand" "+do")
1951 (plus:DI (ashift:DI (sign_extend:DI
1952 (match_operand:HI 1 "general_operand" "rm"))
1955 (clobber (match_scratch:SI 2 "=a"))]
1960 return \"move%.w %1,%2\;add%.l %2,%0\";
1963 (define_insn "adddi_dilshr32"
1964 [(set (match_operand:DI 0 "general_operand" "=ro")
1965 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
1967 (match_operand:DI 2 "general_operand" "0")))]
1972 if (GET_CODE (operands[0]) == REG)
1973 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1975 operands[0] = adj_offsettable_operand (operands[0], 4);
1976 return \"add%.l %1,%0\";
1979 (define_insn "adddi_dishl32"
1980 [(set (match_operand:DI 0 "general_operand" "=ro")
1981 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro")
1983 (match_operand:DI 2 "general_operand" "0")))]
1988 if (GET_CODE (operands[1]) == REG)
1989 operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1991 operands[1] = adj_offsettable_operand (operands[1], 4);
1992 return \"add%.l %1,%0\";
1995 (define_insn "adddi_mem"
1996 [(set (match_operand:DI 0 "general_operand" "=m")
1997 (plus:DI (match_operand:DI 1 "general_operand" "%0")
1998 (match_operand:DI 2 "general_operand" "d")))
1999 (clobber (match_scratch:SI 3 "=d"))]
2004 operands[1] = adj_offsettable_operand (operands[0], 4);
2005 operands[4] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
2006 return \"add%.l %4,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
2009 (define_insn "adddi3"
2010 [(set (match_operand:DI 0 "general_operand" "=d,d,d,<")
2011 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0")
2012 (match_operand:DI 2 "general_operand" "ao,>,d,<")))]
2016 if (which_alternative == 3)
2017 return \"add%.l %2,%0\;addx%.l %2,%0\";
2018 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
2019 if (which_alternative == 1)
2022 return \"add%.l %2,%0\;add%.l %2,%1\;negx%.l %0\;neg%.l %0\";
2024 if (GET_CODE (operands[2]) == REG)
2025 operands[3] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
2027 operands[3] = adj_offsettable_operand (operands[2], 4);
2028 if (which_alternative == 2)
2029 return \"add%.l %3,%1\;addx%.l %2,%0\";
2031 /* negx + neg simulates (non-existent) addx #0 */
2032 /* TODO : this should work also for CONST operands[2] */
2033 return \"add%.l %3,%1\;negx%.l %0\;neg%.l %0\;add%.l %2,%0\";
2036 ;; Note that the middle two alternatives are near-duplicates
2037 ;; in order to handle insns generated by reload.
2038 ;; This is needed since they are not themselves reloaded,
2039 ;; so commutativity won't apply to them.
2040 (define_insn "addsi3"
2041 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
2042 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2043 (match_operand:SI 2 "general_operand" "dIKLs,rJK,a,mrIKLs")))]
2047 if (! operands_match_p (operands[0], operands[1]))
2049 if (!ADDRESS_REG_P (operands[1]))
2051 rtx tmp = operands[1];
2053 operands[1] = operands[2];
2057 /* These insns can result from reloads to access
2058 stack slots over 64k from the frame pointer. */
2059 if (GET_CODE (operands[2]) == CONST_INT
2060 && INTVAL (operands[2]) + 0x8000 >= (unsigned) 0x10000)
2061 return \"move%.l %2,%0\;add%.l %1,%0\";
2063 if (GET_CODE (operands[2]) == REG)
2064 return \"lea 0(%1,%2.l),%0\";
2066 return \"lea %c2(%1),%0\";
2069 if (GET_CODE (operands[2]) == REG)
2070 return \"lea (%1,%2.l),%0\";
2072 return \"lea (%c2,%1),%0\";
2073 #else /* not MOTOROLA (MIT syntax) */
2074 if (GET_CODE (operands[2]) == REG)
2075 return \"lea %1@(0,%2:l),%0\";
2077 return \"lea %1@(%c2),%0\";
2078 #endif /* not MOTOROLA */
2079 #endif /* not SGS */
2081 if (GET_CODE (operands[2]) == CONST_INT)
2084 if (INTVAL (operands[2]) > 0
2085 && INTVAL (operands[2]) <= 8)
2086 return (ADDRESS_REG_P (operands[0])
2088 : \"addq%.l %2,%0\");
2089 if (INTVAL (operands[2]) < 0
2090 && INTVAL (operands[2]) >= -8)
2092 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2093 - INTVAL (operands[2]));
2094 return (ADDRESS_REG_P (operands[0])
2096 : \"subq%.l %2,%0\");
2098 /* On everything except the 68000 it is faster to use two
2099 addqw instructions to add a small integer (8 < N <= 16)
2100 to an address register. Likewise for subqw.*/
2101 if (INTVAL (operands[2]) > 8
2102 && INTVAL (operands[2]) <= 16
2103 && ADDRESS_REG_P (operands[0])
2106 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 8);
2107 return \"addq%.w %#8,%0\;addq%.w %2,%0\";
2109 if (INTVAL (operands[2]) < -8
2110 && INTVAL (operands[2]) >= -16
2111 && ADDRESS_REG_P (operands[0])
2114 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2115 - INTVAL (operands[2]) - 8);
2116 return \"subq%.w %#8,%0\;subq%.w %2,%0\";
2119 if (ADDRESS_REG_P (operands[0])
2120 && INTVAL (operands[2]) >= -0x8000
2121 && INTVAL (operands[2]) < 0x8000)
2122 return \"add%.w %2,%0\";
2124 return \"add%.l %2,%0\";
2128 [(set (match_operand:SI 0 "general_operand" "=a")
2129 (plus:SI (match_operand:SI 1 "general_operand" "0")
2131 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2135 (define_insn "addhi3"
2136 [(set (match_operand:HI 0 "general_operand" "=m,r")
2137 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2138 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2143 if (GET_CODE (operands[2]) == CONST_INT)
2145 /* If the constant would be a negative number when interpreted as
2146 HImode, make it negative. This is usually, but not always, done
2147 elsewhere in the compiler. First check for constants out of range,
2148 which could confuse us. */
2150 if (INTVAL (operands[2]) >= 32768)
2151 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2152 INTVAL (operands[2]) - 65536);
2154 if (INTVAL (operands[2]) > 0
2155 && INTVAL (operands[2]) <= 8)
2156 return \"addq%.w %2,%0\";
2157 if (INTVAL (operands[2]) < 0
2158 && INTVAL (operands[2]) >= -8)
2160 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2161 - INTVAL (operands[2]));
2162 return \"subq%.w %2,%0\";
2164 /* On everything except the 68000 it is faster to use two
2165 addqw instructions to add a small integer (8 < N <= 16)
2166 to an address register. Likewise for subqw. */
2167 if (INTVAL (operands[2]) > 8
2168 && INTVAL (operands[2]) <= 16
2169 && ADDRESS_REG_P (operands[0])
2172 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 8);
2173 return \"addq%.w %#8,%0\;addq%.w %2,%0\";
2175 if (INTVAL (operands[2]) < -8
2176 && INTVAL (operands[2]) >= -16
2177 && ADDRESS_REG_P (operands[0])
2180 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2181 - INTVAL (operands[2]) - 8);
2182 return \"subq%.w %#8,%0\;subq%.w %2,%0\";
2186 return \"add%.w %2,%0\";
2189 ;; These insns must use MATCH_DUP instead of the more expected
2190 ;; use of a matching constraint because the "output" here is also
2191 ;; an input, so you can't use the matching constraint. That also means
2192 ;; that you can't use the "%", so you need patterns with the matched
2193 ;; operand in both positions.
2196 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2197 (plus:HI (match_dup 0)
2198 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2203 if (GET_CODE (operands[1]) == CONST_INT)
2205 /* If the constant would be a negative number when interpreted as
2206 HImode, make it negative. This is usually, but not always, done
2207 elsewhere in the compiler. First check for constants out of range,
2208 which could confuse us. */
2210 if (INTVAL (operands[1]) >= 32768)
2211 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2212 INTVAL (operands[1]) - 65536);
2214 if (INTVAL (operands[1]) > 0
2215 && INTVAL (operands[1]) <= 8)
2216 return \"addq%.w %1,%0\";
2217 if (INTVAL (operands[1]) < 0
2218 && INTVAL (operands[1]) >= -8)
2220 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2221 - INTVAL (operands[1]));
2222 return \"subq%.w %1,%0\";
2224 /* On everything except the 68000 it is faster to use two
2225 addqw instructions to add a small integer (8 < N <= 16)
2226 to an address register. Likewise for subqw. */
2227 if (INTVAL (operands[1]) > 8
2228 && INTVAL (operands[1]) <= 16
2229 && ADDRESS_REG_P (operands[0])
2232 operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8);
2233 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2235 if (INTVAL (operands[1]) < -8
2236 && INTVAL (operands[1]) >= -16
2237 && ADDRESS_REG_P (operands[0])
2240 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2241 - INTVAL (operands[1]) - 8);
2242 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2246 return \"add%.w %1,%0\";
2250 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2251 (plus:HI (match_operand:HI 1 "general_operand" "dn,rmn")
2257 if (GET_CODE (operands[1]) == CONST_INT)
2259 /* If the constant would be a negative number when interpreted as
2260 HImode, make it negative. This is usually, but not always, done
2261 elsewhere in the compiler. First check for constants out of range,
2262 which could confuse us. */
2264 if (INTVAL (operands[1]) >= 32768)
2265 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2266 INTVAL (operands[1]) - 65536);
2268 if (INTVAL (operands[1]) > 0
2269 && INTVAL (operands[1]) <= 8)
2270 return \"addq%.w %1,%0\";
2271 if (INTVAL (operands[1]) < 0
2272 && INTVAL (operands[1]) >= -8)
2274 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2275 - INTVAL (operands[1]));
2276 return \"subq%.w %1,%0\";
2278 /* On everything except the 68000 it is faster to use two
2279 addqw instructions to add a small integer (8 < N <= 16)
2280 to an address register. Likewise for subqw. */
2281 if (INTVAL (operands[1]) > 8
2282 && INTVAL (operands[1]) <= 16
2283 && ADDRESS_REG_P (operands[0])
2286 operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8);
2287 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2289 if (INTVAL (operands[1]) < -8
2290 && INTVAL (operands[1]) >= -16
2291 && ADDRESS_REG_P (operands[0])
2294 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2295 - INTVAL (operands[1]) - 8);
2296 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2300 return \"add%.w %1,%0\";
2303 (define_insn "addqi3"
2304 [(set (match_operand:QI 0 "general_operand" "=m,d")
2305 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2306 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2311 if (GET_CODE (operands[2]) == CONST_INT)
2313 if (INTVAL (operands[2]) >= 128)
2314 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2315 INTVAL (operands[2]) - 256);
2317 if (INTVAL (operands[2]) > 0
2318 && INTVAL (operands[2]) <= 8)
2319 return \"addq%.b %2,%0\";
2320 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2322 operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2]));
2323 return \"subq%.b %2,%0\";
2327 return \"add%.b %2,%0\";
2331 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2332 (plus:QI (match_dup 0)
2333 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2338 if (GET_CODE (operands[1]) == CONST_INT)
2340 if (INTVAL (operands[1]) >= 128)
2341 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2342 INTVAL (operands[1]) - 256);
2344 if (INTVAL (operands[1]) > 0
2345 && INTVAL (operands[1]) <= 8)
2346 return \"addq%.b %1,%0\";
2347 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2349 operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]));
2350 return \"subq%.b %1,%0\";
2354 return \"add%.b %1,%0\";
2358 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2359 (plus:QI (match_operand:QI 1 "general_operand" "dn,dmn")
2365 if (GET_CODE (operands[1]) == CONST_INT)
2367 if (INTVAL (operands[1]) >= 128)
2368 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2369 INTVAL (operands[1]) - 256);
2371 if (INTVAL (operands[1]) > 0
2372 && INTVAL (operands[1]) <= 8)
2373 return \"addq%.b %1,%0\";
2374 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2376 operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]));
2377 return \"subq%.b %1,%0\";
2381 return \"add%.b %1,%0\";
2384 (define_expand "adddf3"
2385 [(set (match_operand:DF 0 "general_operand" "")
2386 (plus:DF (match_operand:DF 1 "general_operand" "")
2387 (match_operand:DF 2 "general_operand" "")))]
2388 "TARGET_68881 || TARGET_FPA"
2392 [(set (match_operand:DF 0 "general_operand" "=x,y")
2393 (plus:DF (match_operand:DF 1 "general_operand" "%xH,y")
2394 (match_operand:DF 2 "general_operand" "xH,dmF")))]
2398 if (rtx_equal_p (operands[0], operands[1]))
2399 return \"fpadd%.d %y2,%0\";
2400 if (rtx_equal_p (operands[0], operands[2]))
2401 return \"fpadd%.d %y1,%0\";
2402 if (which_alternative == 0)
2403 return \"fpadd3%.d %w2,%w1,%0\";
2404 return \"fpadd3%.d %x2,%x1,%0\";
2408 [(set (match_operand:DF 0 "general_operand" "=f")
2409 (plus:DF (match_operand:DF 1 "general_operand" "%0")
2410 (match_operand:DF 2 "general_operand" "fmG")))]
2414 if (REG_P (operands[2]))
2415 return \"f%&add%.x %2,%0\";
2416 return \"f%&add%.d %f2,%0\";
2419 (define_expand "addsf3"
2420 [(set (match_operand:SF 0 "general_operand" "")
2421 (plus:SF (match_operand:SF 1 "general_operand" "")
2422 (match_operand:SF 2 "general_operand" "")))]
2423 "TARGET_68881 || TARGET_FPA"
2427 [(set (match_operand:SF 0 "general_operand" "=x,y")
2428 (plus:SF (match_operand:SF 1 "general_operand" "%xH,y")
2429 (match_operand:SF 2 "general_operand" "xH,rmF")))]
2433 if (rtx_equal_p (operands[0], operands[1]))
2434 return \"fpadd%.s %w2,%0\";
2435 if (rtx_equal_p (operands[0], operands[2]))
2436 return \"fpadd%.s %w1,%0\";
2437 if (which_alternative == 0)
2438 return \"fpadd3%.s %w2,%w1,%0\";
2439 return \"fpadd3%.s %2,%1,%0\";
2443 [(set (match_operand:SF 0 "general_operand" "=f")
2444 (plus:SF (match_operand:SF 1 "general_operand" "%0")
2445 (match_operand:SF 2 "general_operand" "fdmF")))]
2449 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2450 return \"f%$add%.x %2,%0\";
2451 return \"f%$add%.s %f2,%0\";
2454 ;; subtract instructions
2456 (define_insn "subdia_sexthishl32"
2457 [(set (match_operand:DI 0 "register_operand" "+a")
2458 (minus:DI (match_dup 0)
2459 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm"))
2465 return \"sub%.w %1,%0\";
2468 (define_insn "subdid_sexthishl32"
2469 [(set (match_operand:DI 0 "register_operand" "+do")
2470 (minus:DI (match_dup 0)
2471 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm"))
2473 (clobber (match_scratch:SI 2 "=a"))]
2478 return \"move%.w %1,%2\;sub%.l %2,%0\";
2481 (define_insn "subdi_dishl32"
2482 [(set (match_operand:DI 0 "register_operand" "+d")
2483 (minus:DI (match_dup 0)
2484 (ashift:DI (match_operand:DI 1 "register_operand" "d")
2490 operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2491 return \"sub%.l %1,%0\";
2494 (define_insn "subdi_mem"
2495 [(set (match_operand:DI 0 "general_operand" "=m")
2496 (minus:DI (match_operand:DI 1 "general_operand" "0")
2497 (match_operand:DI 2 "general_operand" "d")))
2498 (clobber (match_scratch:SI 3 "=d"))]
2503 operands[1] = adj_offsettable_operand (operands[0], 4);
2504 operands[4] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
2505 return \"sub%.l %4,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
2508 (define_insn "subdi3"
2509 [(set (match_operand:DI 0 "general_operand" "=d,d,d,<")
2510 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2511 (match_operand:DI 2 "general_operand" "ao,>,d,<")))]
2515 if (which_alternative == 3)
2516 return \"sub%.l %2,%0\;subx%.l %2,%0\";
2517 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
2518 if (which_alternative == 1)
2521 return \"neg%.l %0\;add%.l %2,%0\;sub%.l %2,%1\;negx%.l %0\";
2523 if (GET_CODE (operands[2]) == REG)
2524 operands[3] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
2526 operands[3] = adj_offsettable_operand (operands[2], 4);
2527 if (which_alternative == 2)
2528 return \"sub%.l %3,%1\;subx%.l %2,%0\";
2530 /* neg + negx simulates (non-existent) subx #0 */
2531 /* TODO : this should work also for CONST operands[2] */
2532 return \"neg%.l %0\;sub%.l %3,%1\;negx%.l %0\;sub%.l %2,%0\";
2535 (define_insn "subsi3"
2536 [(set (match_operand:SI 0 "general_operand" "=m,r")
2537 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
2538 (match_operand:SI 2 "general_operand" "ds,mrs")))]
2543 [(set (match_operand:SI 0 "general_operand" "=a")
2544 (minus:SI (match_operand:SI 1 "general_operand" "0")
2546 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2550 (define_insn "subhi3"
2551 [(set (match_operand:HI 0 "general_operand" "=m,r")
2552 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2553 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2558 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2559 (minus:HI (match_dup 0)
2560 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2564 (define_insn "subqi3"
2565 [(set (match_operand:QI 0 "general_operand" "=m,d")
2566 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2567 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2572 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2573 (minus:QI (match_dup 0)
2574 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2578 (define_expand "subdf3"
2579 [(set (match_operand:DF 0 "general_operand" "")
2580 (minus:DF (match_operand:DF 1 "general_operand" "")
2581 (match_operand:DF 2 "general_operand" "")))]
2582 "TARGET_68881 || TARGET_FPA"
2586 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
2587 (minus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF")
2588 (match_operand:DF 2 "general_operand" "xH,dmF,0")))]
2592 if (rtx_equal_p (operands[0], operands[2]))
2593 return \"fprsub%.d %y1,%0\";
2594 if (rtx_equal_p (operands[0], operands[1]))
2595 return \"fpsub%.d %y2,%0\";
2596 if (which_alternative == 0)
2597 return \"fpsub3%.d %w2,%w1,%0\";
2598 return \"fpsub3%.d %x2,%x1,%0\";
2602 [(set (match_operand:DF 0 "general_operand" "=f")
2603 (minus:DF (match_operand:DF 1 "general_operand" "0")
2604 (match_operand:DF 2 "general_operand" "fmG")))]
2608 if (REG_P (operands[2]))
2609 return \"f%&sub%.x %2,%0\";
2610 return \"f%&sub%.d %f2,%0\";
2613 (define_expand "subsf3"
2614 [(set (match_operand:SF 0 "general_operand" "")
2615 (minus:SF (match_operand:SF 1 "general_operand" "")
2616 (match_operand:SF 2 "general_operand" "")))]
2617 "TARGET_68881 || TARGET_FPA"
2621 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
2622 (minus:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
2623 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
2627 if (rtx_equal_p (operands[0], operands[2]))
2628 return \"fprsub%.s %w1,%0\";
2629 if (rtx_equal_p (operands[0], operands[1]))
2630 return \"fpsub%.s %w2,%0\";
2631 if (which_alternative == 0)
2632 return \"fpsub3%.s %w2,%w1,%0\";
2633 return \"fpsub3%.s %2,%1,%0\";
2637 [(set (match_operand:SF 0 "general_operand" "=f")
2638 (minus:SF (match_operand:SF 1 "general_operand" "0")
2639 (match_operand:SF 2 "general_operand" "fdmF")))]
2643 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2644 return \"f%$sub%.x %2,%0\";
2645 return \"f%$sub%.s %f2,%0\";
2648 ;; multiply instructions
2650 (define_insn "mulhi3"
2651 [(set (match_operand:HI 0 "general_operand" "=d")
2652 (mult:HI (match_operand:HI 1 "general_operand" "%0")
2653 (match_operand:HI 2 "general_operand" "dmn")))]
2657 #if defined(MOTOROLA) && !defined(CRDS)
2658 return \"muls%.w %2,%0\";
2660 return \"muls %2,%0\";
2664 (define_insn "mulhisi3"
2665 [(set (match_operand:SI 0 "general_operand" "=d")
2666 (mult:SI (sign_extend:SI
2667 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2669 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
2673 #if defined(MOTOROLA) && !defined(CRDS)
2674 return \"muls%.w %2,%0\";
2676 return \"muls %2,%0\";
2681 [(set (match_operand:SI 0 "general_operand" "=d")
2682 (mult:SI (sign_extend:SI
2683 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2684 (match_operand:SI 2 "const_int_operand" "n")))]
2685 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
2688 #if defined(MOTOROLA) && !defined(CRDS)
2689 return \"muls%.w %2,%0\";
2691 return \"muls %2,%0\";
2695 (define_insn "mulsi3"
2696 [(set (match_operand:SI 0 "general_operand" "=d")
2697 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2698 (match_operand:SI 2 "general_operand" "dmsK")))]
2702 (define_insn "umulhisi3"
2703 [(set (match_operand:SI 0 "general_operand" "=d")
2704 (mult:SI (zero_extend:SI
2705 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2707 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
2711 #if defined(MOTOROLA) && !defined(CRDS)
2712 return \"mulu%.w %2,%0\";
2714 return \"mulu %2,%0\";
2719 [(set (match_operand:SI 0 "general_operand" "=d")
2720 (mult:SI (zero_extend:SI
2721 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2722 (match_operand:SI 2 "const_int_operand" "n")))]
2723 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
2726 #if defined(MOTOROLA) && !defined(CRDS)
2727 return \"mulu%.w %2,%0\";
2729 return \"mulu %2,%0\";
2733 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
2734 ;; proper matching constraint. This is because the matching is between
2735 ;; the high-numbered word of the DImode operand[0] and operand[1].
2736 (define_expand "umulsidi3"
2738 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
2739 (mult:SI (match_operand:SI 1 "register_operand" "")
2740 (match_operand:SI 2 "nonimmediate_operand" "")))
2741 (set (subreg:SI (match_dup 0) 0)
2742 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2743 (zero_extend:DI (match_dup 2)))
2744 (const_int 32))))])]
2749 [(set (match_operand:SI 0 "register_operand" "=d")
2750 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2751 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2752 (set (match_operand:SI 3 "register_operand" "=d")
2753 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2754 (zero_extend:DI (match_dup 2)))
2759 ; Match immediate case. For 2.4 only match things < 2^31.
2760 ; It's tricky with larger values in these patterns since we need to match
2761 ; values between the two parallel multiplies, between a CONST_DOUBLE and
2764 [(set (match_operand:SI 0 "register_operand" "=d")
2765 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2766 (match_operand:SI 2 "const_int_operand" "n")))
2767 (set (match_operand:SI 3 "register_operand" "=d")
2768 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2772 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
2775 (define_expand "mulsidi3"
2777 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
2778 (mult:SI (match_operand:SI 1 "register_operand" "")
2779 (match_operand:SI 2 "nonimmediate_operand" "")))
2780 (set (subreg:SI (match_dup 0) 0)
2781 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2782 (sign_extend:DI (match_dup 2)))
2783 (const_int 32))))])]
2788 [(set (match_operand:SI 0 "register_operand" "=d")
2789 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2790 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2791 (set (match_operand:SI 3 "register_operand" "=d")
2792 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2793 (sign_extend:DI (match_dup 2)))
2799 [(set (match_operand:SI 0 "register_operand" "=d")
2800 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2801 (match_operand:SI 2 "const_int_operand" "n")))
2802 (set (match_operand:SI 3 "register_operand" "=d")
2803 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2807 /* This test is a noop on 32 bit machines,
2808 but important for a cross-compiler hosted on 64-bit machines. */
2809 && INTVAL (operands[2]) <= 0x7fffffff
2810 && INTVAL (operands[2]) >= -0x80000000"
2813 (define_expand "umulsi3_highpart"
2815 [(set (match_operand:SI 0 "register_operand" "")
2818 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
2819 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
2821 (clobber (match_dup 3))])]
2825 operands[3] = gen_reg_rtx (SImode);
2826 if (CONSTANT_P (operands[2]))
2828 /* We have to rearrange the operand order for the matching constraints. */
2829 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
2830 operands[1], operands[2]));
2836 [(set (match_operand:SI 0 "register_operand" "=d")
2839 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
2840 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
2842 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2846 (define_insn "const_umulsi3_highpart"
2847 [(set (match_operand:SI 0 "register_operand" "=d")
2850 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
2851 (match_operand:DI 3 "immediate_operand" "i"))
2853 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2857 (define_expand "smulsi3_highpart"
2859 [(set (match_operand:SI 0 "register_operand" "")
2862 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
2863 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
2865 (clobber (match_dup 3))])]
2869 operands[3] = gen_reg_rtx (SImode);
2870 if (CONSTANT_P (operands[2]))
2872 /* We have to rearrange the operand order for the matching constraints. */
2873 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
2874 operands[1], operands[2]));
2880 [(set (match_operand:SI 0 "register_operand" "=d")
2883 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
2884 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
2886 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2890 (define_insn "const_smulsi3_highpart"
2891 [(set (match_operand:SI 0 "register_operand" "=d")
2894 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
2895 (match_operand:DI 3 "immediate_operand" "i"))
2897 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2901 (define_expand "muldf3"
2902 [(set (match_operand:DF 0 "general_operand" "")
2903 (mult:DF (match_operand:DF 1 "general_operand" "")
2904 (match_operand:DF 2 "general_operand" "")))]
2905 "TARGET_68881 || TARGET_FPA"
2909 [(set (match_operand:DF 0 "general_operand" "=x,y")
2910 (mult:DF (match_operand:DF 1 "general_operand" "%xH,y")
2911 (match_operand:DF 2 "general_operand" "xH,rmF")))]
2915 if (rtx_equal_p (operands[1], operands[2]))
2916 return \"fpsqr%.d %y1,%0\";
2917 if (rtx_equal_p (operands[0], operands[1]))
2918 return \"fpmul%.d %y2,%0\";
2919 if (rtx_equal_p (operands[0], operands[2]))
2920 return \"fpmul%.d %y1,%0\";
2921 if (which_alternative == 0)
2922 return \"fpmul3%.d %w2,%w1,%0\";
2923 return \"fpmul3%.d %x2,%x1,%0\";
2927 [(set (match_operand:DF 0 "general_operand" "=f")
2928 (mult:DF (match_operand:DF 1 "general_operand" "%0")
2929 (match_operand:DF 2 "general_operand" "fmG")))]
2933 if (GET_CODE (operands[2]) == CONST_DOUBLE
2934 && floating_exact_log2 (operands[2]) && !TARGET_68040)
2936 int i = floating_exact_log2 (operands[2]);
2937 operands[2] = gen_rtx (CONST_INT, VOIDmode, i);
2938 return \"fscale%.l %2,%0\";
2940 if (REG_P (operands[2]))
2941 return \"f%&mul%.x %2,%0\";
2942 return \"f%&mul%.d %f2,%0\";
2945 (define_expand "mulsf3"
2946 [(set (match_operand:SF 0 "general_operand" "")
2947 (mult:SF (match_operand:SF 1 "general_operand" "")
2948 (match_operand:SF 2 "general_operand" "")))]
2949 "TARGET_68881 || TARGET_FPA"
2953 [(set (match_operand:SF 0 "general_operand" "=x,y")
2954 (mult:SF (match_operand:SF 1 "general_operand" "%xH,y")
2955 (match_operand:SF 2 "general_operand" "xH,rmF")))]
2959 if (rtx_equal_p (operands[1], operands[2]))
2960 return \"fpsqr%.s %w1,%0\";
2961 if (rtx_equal_p (operands[0], operands[1]))
2962 return \"fpmul%.s %w2,%0\";
2963 if (rtx_equal_p (operands[0], operands[2]))
2964 return \"fpmul%.s %w1,%0\";
2965 if (which_alternative == 0)
2966 return \"fpmul3%.s %w2,%w1,%0\";
2967 return \"fpmul3%.s %2,%1,%0\";
2971 [(set (match_operand:SF 0 "general_operand" "=f")
2972 (mult:SF (match_operand:SF 1 "general_operand" "%0")
2973 (match_operand:SF 2 "general_operand" "fdmF")))]
2977 #ifdef FSGLMUL_USE_S
2978 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2979 return (TARGET_68040_ONLY
2980 ? \"fsmul%.s %2,%0\"
2981 : \"fsglmul%.s %2,%0\");
2983 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2984 return (TARGET_68040_ONLY
2985 ? \"fsmul%.x %2,%0\"
2986 : \"fsglmul%.x %2,%0\");
2988 return (TARGET_68040_ONLY
2989 ? \"fsmul%.s %f2,%0\"
2990 : \"fsglmul%.s %f2,%0\");
2993 ;; divide instructions
2995 (define_insn "divhi3"
2996 [(set (match_operand:HI 0 "general_operand" "=d")
2997 (div:HI (match_operand:HI 1 "general_operand" "0")
2998 (match_operand:HI 2 "general_operand" "dmn")))]
3003 return \"ext%.l %0\;divs%.w %2,%0\";
3005 return \"extl %0\;divs %2,%0\";
3009 ;; These patterns don't work because the divs instruction is undefined if
3010 ;; the quotient is more than 16 bits. This valid C would be miscompiled:
3011 ;; int n; short d; unsigned short q; ... q = (unsigned int) (n / d);
3012 ;; Imagine what happens when n = 100000 and d = 1.
3013 ;;(define_insn "divhisi3"
3014 ;; [(set (match_operand:HI 0 "general_operand" "=d")
3017 ;; (match_operand:SI 1 "general_operand" "0")
3018 ;; (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))]
3023 ;; return \"divs%.w %2,%0\";
3025 ;; return \"divs %2,%0\";
3030 ;; [(set (match_operand:HI 0 "general_operand" "=d")
3031 ;; (truncate:HI (div:SI (match_operand:SI 1 "general_operand" "0")
3032 ;; (match_operand:SI 2 "const_int_operand" "n"))))]
3037 ;; return \"divs%.w %2,%0\";
3039 ;; return \"divs %2,%0\";
3043 (define_insn "udivhi3"
3044 [(set (match_operand:HI 0 "general_operand" "=d")
3045 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3046 (match_operand:HI 2 "general_operand" "dmn")))]
3051 return \"and%.l %#0xFFFF,%0\;divu%.w %2,%0\";
3053 return \"andl %#0xFFFF,%0\;divu %2,%0\";
3057 ;; See comment before divhisi3 why these are commented out.
3058 ;;(define_insn "udivhisi3"
3059 ;; [(set (match_operand:HI 0 "general_operand" "=d")
3062 ;; (match_operand:SI 1 "general_operand" "0")
3063 ;; (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))]
3068 ;; return \"divu%.w %2,%0\";
3070 ;; return \"divu %2,%0\";
3075 ;; [(set (match_operand:HI 0 "general_operand" "=d")
3076 ;; (truncate:HI (udiv:SI (match_operand:SI 1 "general_operand" "0")
3077 ;; (match_operand:SI 2 "const_int_operand" "n"))))]
3082 ;; return \"divu%.w %2,%0\";
3084 ;; return \"divu %2,%0\";
3088 (define_expand "divdf3"
3089 [(set (match_operand:DF 0 "general_operand" "")
3090 (div:DF (match_operand:DF 1 "general_operand" "")
3091 (match_operand:DF 2 "general_operand" "")))]
3092 "TARGET_68881 || TARGET_FPA"
3096 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
3097 (div:DF (match_operand:DF 1 "general_operand" "xH,y,rmF")
3098 (match_operand:DF 2 "general_operand" "xH,rmF,0")))]
3102 if (rtx_equal_p (operands[0], operands[2]))
3103 return \"fprdiv%.d %y1,%0\";
3104 if (rtx_equal_p (operands[0], operands[1]))
3105 return \"fpdiv%.d %y2,%0\";
3106 if (which_alternative == 0)
3107 return \"fpdiv3%.d %w2,%w1,%0\";
3108 return \"fpdiv3%.d %x2,%x1,%x0\";
3112 [(set (match_operand:DF 0 "general_operand" "=f")
3113 (div:DF (match_operand:DF 1 "general_operand" "0")
3114 (match_operand:DF 2 "general_operand" "fmG")))]
3118 if (REG_P (operands[2]))
3119 return \"f%&div%.x %2,%0\";
3120 return \"f%&div%.d %f2,%0\";
3123 (define_expand "divsf3"
3124 [(set (match_operand:SF 0 "general_operand" "")
3125 (div:SF (match_operand:SF 1 "general_operand" "")
3126 (match_operand:SF 2 "general_operand" "")))]
3127 "TARGET_68881 || TARGET_FPA"
3131 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
3132 (div:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
3133 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
3137 if (rtx_equal_p (operands[0], operands[1]))
3138 return \"fpdiv%.s %w2,%0\";
3139 if (rtx_equal_p (operands[0], operands[2]))
3140 return \"fprdiv%.s %w1,%0\";
3141 if (which_alternative == 0)
3142 return \"fpdiv3%.s %w2,%w1,%0\";
3143 return \"fpdiv3%.s %2,%1,%0\";
3147 [(set (match_operand:SF 0 "general_operand" "=f")
3148 (div:SF (match_operand:SF 1 "general_operand" "0")
3149 (match_operand:SF 2 "general_operand" "fdmF")))]
3153 #ifdef FSGLDIV_USE_S
3154 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3155 return (TARGET_68040_ONLY
3156 ? \"fsdiv%.s %2,%0\"
3157 : \"fsgldiv%.s %2,%0\");
3159 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3160 return (TARGET_68040_ONLY
3161 ? \"fsdiv%.x %2,%0\"
3162 : \"fsgldiv%.x %2,%0\");
3164 return (TARGET_68040_ONLY
3165 ? \"fsdiv%.s %f2,%0\"
3166 : \"fsgldiv%.s %f2,%0\");
3169 ;; Remainder instructions.
3171 (define_insn "modhi3"
3172 [(set (match_operand:HI 0 "general_operand" "=d")
3173 (mod:HI (match_operand:HI 1 "general_operand" "0")
3174 (match_operand:HI 2 "general_operand" "dmn")))]
3178 /* The swap insn produces cc's that don't correspond to the result. */
3181 return \"ext%.l %0\;divs%.w %2,%0\;swap %0\";
3183 return \"extl %0\;divs %2,%0\;swap %0\";
3187 ;; See comment before divhisi3 why these are commented out.
3188 ;;(define_insn "modhisi3"
3189 ;; [(set (match_operand:HI 0 "general_operand" "=d")
3192 ;; (match_operand:SI 1 "general_operand" "0")
3193 ;; (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))]
3197 ;; /* The swap insn produces cc's that don't correspond to the result. */
3200 ;; return \"divs%.w %2,%0\;swap %0\";
3202 ;; return \"divs %2,%0\;swap %0\";
3207 ;; [(set (match_operand:HI 0 "general_operand" "=d")
3208 ;; (truncate:HI (mod:SI (match_operand:SI 1 "general_operand" "0")
3209 ;; (match_operand:SI 2 "const_int_operand" "n"))))]
3213 ;; /* The swap insn produces cc's that don't correspond to the result. */
3216 ;; return \"divs%.w %2,%0\;swap %0\";
3218 ;; return \"divs %2,%0\;swap %0\";
3222 (define_insn "umodhi3"
3223 [(set (match_operand:HI 0 "general_operand" "=d")
3224 (umod:HI (match_operand:HI 1 "general_operand" "0")
3225 (match_operand:HI 2 "general_operand" "dmn")))]
3229 /* The swap insn produces cc's that don't correspond to the result. */
3232 return \"and%.l %#0xFFFF,%0\;divu%.w %2,%0\;swap %0\";
3234 return \"andl %#0xFFFF,%0\;divu %2,%0\;swap %0\";
3238 ;; See comment before divhisi3 why these are commented out.
3239 ;;(define_insn "umodhisi3"
3240 ;; [(set (match_operand:HI 0 "general_operand" "=d")
3243 ;; (match_operand:SI 1 "general_operand" "0")
3244 ;; (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))]
3248 ;; /* The swap insn produces cc's that don't correspond to the result. */
3251 ;; return \"divu%.w %2,%0\;swap %0\";
3253 ;; return \"divu %2,%0\;swap %0\";
3258 ;; [(set (match_operand:HI 0 "general_operand" "=d")
3259 ;; (truncate:HI (umod:SI (match_operand:SI 1 "general_operand" "0")
3260 ;; (match_operand:SI 2 "const_int_operand" "n"))))]
3264 ;; /* The swap insn produces cc's that don't correspond to the result. */
3267 ;; return \"divu%.w %2,%0\;swap %0\";
3269 ;; return \"divu %2,%0\;swap %0\";
3273 (define_insn "divmodsi4"
3274 [(set (match_operand:SI 0 "general_operand" "=d")
3275 (div:SI (match_operand:SI 1 "general_operand" "0")
3276 (match_operand:SI 2 "general_operand" "dmsK")))
3277 (set (match_operand:SI 3 "general_operand" "=d")
3278 (mod:SI (match_dup 1) (match_dup 2)))]
3282 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3283 return \"divs%.l %2,%0\";
3285 return \"divsl%.l %2,%3:%0\";
3288 (define_insn "udivmodsi4"
3289 [(set (match_operand:SI 0 "general_operand" "=d")
3290 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3291 (match_operand:SI 2 "general_operand" "dmsK")))
3292 (set (match_operand:SI 3 "general_operand" "=d")
3293 (umod:SI (match_dup 1) (match_dup 2)))]
3297 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3298 return \"divu%.l %2,%0\";
3300 return \"divul%.l %2,%3:%0\";
3303 ;; logical-and instructions
3305 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3306 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3307 ;; can't allocate pseudos into it.
3308 (define_insn "andsi3"
3309 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3310 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3311 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
3316 if (GET_CODE (operands[2]) == CONST_INT
3317 && (INTVAL (operands[2]) | 0xffff) == 0xffffffff
3318 && (DATA_REG_P (operands[0])
3319 || offsettable_memref_p (operands[0])))
3321 if (GET_CODE (operands[0]) != REG)
3322 operands[0] = adj_offsettable_operand (operands[0], 2);
3323 operands[2] = gen_rtx (CONST_INT, VOIDmode,
3324 INTVAL (operands[2]) & 0xffff);
3325 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3327 if (operands[2] == const0_rtx)
3328 return \"clr%.w %0\";
3329 return \"and%.w %2,%0\";
3331 if (GET_CODE (operands[2]) == CONST_INT
3332 && (logval = exact_log2 (~ INTVAL (operands[2]))) >= 0
3333 && (DATA_REG_P (operands[0])
3334 || offsettable_memref_p (operands[0])))
3336 if (DATA_REG_P (operands[0]))
3338 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval);
3342 operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
3343 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8);
3345 /* This does not set condition codes in a standard way. */
3347 return \"bclr %1,%0\";
3349 return \"and%.l %2,%0\";
3352 (define_insn "andhi3"
3353 [(set (match_operand:HI 0 "general_operand" "=m,d")
3354 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3355 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3360 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3361 (and:HI (match_dup 0)
3362 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3367 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3368 (and:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3373 (define_insn "andqi3"
3374 [(set (match_operand:QI 0 "general_operand" "=m,d")
3375 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3376 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3381 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3382 (and:QI (match_dup 0)
3383 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3388 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3389 (and:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3394 ;; inclusive-or instructions
3396 (define_insn "iorsi3"
3397 [(set (match_operand:SI 0 "general_operand" "=m,d")
3398 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3399 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
3403 register int logval;
3404 if (GET_CODE (operands[2]) == CONST_INT
3405 && INTVAL (operands[2]) >> 16 == 0
3406 && (DATA_REG_P (operands[0])
3407 || offsettable_memref_p (operands[0])))
3409 if (GET_CODE (operands[0]) != REG)
3410 operands[0] = adj_offsettable_operand (operands[0], 2);
3411 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3413 return \"or%.w %2,%0\";
3415 if (GET_CODE (operands[2]) == CONST_INT
3416 && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
3417 && (DATA_REG_P (operands[0])
3418 || offsettable_memref_p (operands[0])))
3420 if (DATA_REG_P (operands[0]))
3422 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval);
3426 operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
3427 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8);
3430 return \"bset %1,%0\";
3432 return \"or%.l %2,%0\";
3435 (define_insn "iorhi3"
3436 [(set (match_operand:HI 0 "general_operand" "=m,d")
3437 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3438 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3443 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3444 (ior:HI (match_dup 0)
3445 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3450 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3451 (ior:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3456 (define_insn "iorqi3"
3457 [(set (match_operand:QI 0 "general_operand" "=m,d")
3458 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3459 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3464 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3465 (ior:QI (match_dup 0)
3466 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3471 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3472 (ior:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3478 [(set (match_operand:SI 0 "general_operand" "=o,d")
3479 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3480 (match_operand:SI 2 "general_operand" "0,0")))]
3487 byte_mode = (GET_MODE(operands[1]) == QImode);
3488 if (GET_CODE (operands[0]) == MEM)
3489 operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
3491 return \"or%.b %1,%0\";
3493 return \"or%.w %1,%0\";
3498 (define_insn "xorsi3"
3499 [(set (match_operand:SI 0 "general_operand" "=do,m")
3500 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3501 (match_operand:SI 2 "general_operand" "di,dKs")))]
3505 if (GET_CODE (operands[2]) == CONST_INT
3506 && INTVAL (operands[2]) >> 16 == 0
3507 && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0])))
3509 if (! DATA_REG_P (operands[0]))
3510 operands[0] = adj_offsettable_operand (operands[0], 2);
3511 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3513 return \"eor%.w %2,%0\";
3515 return \"eor%.l %2,%0\";
3518 (define_insn "xorhi3"
3519 [(set (match_operand:HI 0 "general_operand" "=dm")
3520 (xor:HI (match_operand:HI 1 "general_operand" "%0")
3521 (match_operand:HI 2 "general_operand" "dn")))]
3526 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3527 (xor:HI (match_dup 0)
3528 (match_operand:HI 1 "general_operand" "dn")))]
3534 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3535 (xor:HI (match_operand:HI 1 "general_operand" "dn")
3540 (define_insn "xorqi3"
3541 [(set (match_operand:QI 0 "general_operand" "=dm")
3542 (xor:QI (match_operand:QI 1 "general_operand" "%0")
3543 (match_operand:QI 2 "general_operand" "dn")))]
3548 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
3549 (xor:QI (match_dup 0)
3550 (match_operand:QI 1 "general_operand" "dn")))]
3555 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
3556 (xor:QI (match_operand:QI 1 "general_operand" "dn")
3561 ;; negation instructions
3563 (define_insn "negdi2"
3564 [(set (match_operand:DI 0 "general_operand" "=d*ao,<")
3565 (neg:DI (match_operand:DI 1 "general_operand" "0,0")))]
3569 if (which_alternative == 1)
3570 return \"neg%.l %0\;negx%.l %0\";
3571 if (GET_CODE (operands[0]) == REG)
3572 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3574 operands[1] = adj_offsettable_operand (operands[0], 4);
3575 if (ADDRESS_REG_P (operands[0]))
3576 return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
3578 return \"neg%.l %1\;negx%.l %0\";
3581 (define_insn "negsi2"
3582 [(set (match_operand:SI 0 "general_operand" "=dm")
3583 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3587 (define_insn "neghi2"
3588 [(set (match_operand:HI 0 "general_operand" "=dm")
3589 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
3594 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3595 (neg:HI (match_dup 0)))]
3599 (define_insn "negqi2"
3600 [(set (match_operand:QI 0 "general_operand" "=dm")
3601 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
3606 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
3607 (neg:QI (match_dup 0)))]
3611 ;; If using software floating point, just flip the sign bit.
3613 (define_expand "negsf2"
3614 [(set (match_operand:SF 0 "general_operand" "")
3615 (neg:SF (match_operand:SF 1 "general_operand" "")))]
3619 if (!TARGET_FPA && !TARGET_68881)
3624 target = operand_subword_force (operands[0], 0, SFmode);
3625 result = expand_binop (SImode, xor_optab,
3626 operand_subword_force (operands[1], 0, SFmode),
3627 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
3631 if (result != target)
3632 emit_move_insn (result, target);
3634 /* Make a place for REG_EQUAL. */
3635 emit_move_insn (operands[0], operands[0]);
3641 [(set (match_operand:SF 0 "general_operand" "=x,y")
3642 (neg:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
3647 [(set (match_operand:SF 0 "general_operand" "=f,d")
3648 (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))]
3652 if (DATA_REG_P (operands[0]))
3654 operands[1] = gen_rtx (CONST_INT, VOIDmode, 31);
3655 return \"bchg %1,%0\";
3657 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3658 return \"f%$neg%.x %1,%0\";
3659 return \"f%$neg%.s %f1,%0\";
3662 (define_expand "negdf2"
3663 [(set (match_operand:DF 0 "general_operand" "")
3664 (neg:DF (match_operand:DF 1 "general_operand" "")))]
3668 if (!TARGET_FPA && !TARGET_68881)
3675 target = operand_subword (operands[0], 0, 1, DFmode);
3676 result = expand_binop (SImode, xor_optab,
3677 operand_subword_force (operands[1], 0, DFmode),
3678 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
3682 if (result != target)
3683 emit_move_insn (result, target);
3685 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
3686 operand_subword_force (operands[1], 1, DFmode));
3688 insns = get_insns ();
3691 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
3697 [(set (match_operand:DF 0 "general_operand" "=x,y")
3698 (neg:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
3703 [(set (match_operand:DF 0 "general_operand" "=f,d")
3704 (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
3708 if (DATA_REG_P (operands[0]))
3710 operands[1] = gen_rtx (CONST_INT, VOIDmode, 31);
3711 return \"bchg %1,%0\";
3713 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3714 return \"f%&neg%.x %1,%0\";
3715 return \"f%&neg%.d %f1,%0\";
3718 ;; Sqrt instruction for the 68881
3720 (define_insn "sqrtsf2"
3721 [(set (match_operand:SF 0 "general_operand" "=f")
3722 (sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
3726 if (FP_REG_P (operands[1]))
3727 return \"fsqrt%.x %1,%0\";
3729 return \"fsqrt%.s %1,%0\";
3732 (define_insn "sqrtdf2"
3733 [(set (match_operand:DF 0 "general_operand" "=f")
3734 (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
3738 if (FP_REG_P (operands[1]))
3739 return \"fsqrt%.x %1,%0\";
3741 return \"fsqrt%.d %1,%0\";
3744 ;; Absolute value instructions
3745 ;; If using software floating point, just zero the sign bit.
3747 (define_expand "abssf2"
3748 [(set (match_operand:SF 0 "general_operand" "")
3749 (abs:SF (match_operand:SF 1 "general_operand" "")))]
3753 if (!TARGET_FPA && !TARGET_68881)
3758 target = operand_subword_force (operands[0], 0, SFmode);
3759 result = expand_binop (SImode, and_optab,
3760 operand_subword_force (operands[1], 0, SFmode),
3761 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
3765 if (result != target)
3766 emit_move_insn (result, target);
3768 /* Make a place for REG_EQUAL. */
3769 emit_move_insn (operands[0], operands[0]);
3775 [(set (match_operand:SF 0 "general_operand" "=x,y")
3776 (abs:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
3781 [(set (match_operand:SF 0 "general_operand" "=f")
3782 (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
3786 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3787 return \"f%$abs%.x %1,%0\";
3788 return \"f%$abs%.s %f1,%0\";
3791 (define_expand "absdf2"
3792 [(set (match_operand:DF 0 "general_operand" "")
3793 (abs:DF (match_operand:DF 1 "general_operand" "")))]
3797 if (!TARGET_FPA && !TARGET_68881)
3804 target = operand_subword (operands[0], 0, 1, DFmode);
3805 result = expand_binop (SImode, and_optab,
3806 operand_subword_force (operands[1], 0, DFmode),
3807 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
3811 if (result != target)
3812 emit_move_insn (result, target);
3814 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
3815 operand_subword_force (operands[1], 1, DFmode));
3817 insns = get_insns ();
3820 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
3826 [(set (match_operand:DF 0 "general_operand" "=x,y")
3827 (abs:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
3832 [(set (match_operand:DF 0 "general_operand" "=f")
3833 (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
3837 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3838 return \"f%&abs%.x %1,%0\";
3839 return \"f%&abs%.d %f1,%0\";
3842 ;; one complement instructions
3844 (define_insn "one_cmplsi2"
3845 [(set (match_operand:SI 0 "general_operand" "=dm")
3846 (not:SI (match_operand:SI 1 "general_operand" "0")))]
3850 (define_insn "one_cmplhi2"
3851 [(set (match_operand:HI 0 "general_operand" "=dm")
3852 (not:HI (match_operand:HI 1 "general_operand" "0")))]
3857 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3858 (not:HI (match_dup 0)))]
3862 (define_insn "one_cmplqi2"
3863 [(set (match_operand:QI 0 "general_operand" "=dm")
3864 (not:QI (match_operand:QI 1 "general_operand" "0")))]
3869 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
3870 (not:QI (match_dup 0)))]
3874 ;; arithmetic shift instructions
3875 ;; We don't need the shift memory by 1 bit instruction
3877 (define_insn "ashldi_sexthi"
3878 [(set (match_operand:DI 0 "general_operand" "=*da")
3879 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm"))
3885 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3886 if (DATA_REG_P (operands[0]))
3887 return \"move%.w %1,%0\;ext%.l %0\;clr%.l %2\";
3889 return \"move%.w %1,%0\;sub%.l %2,%2\";
3892 (define_insn "ashldi_const32"
3893 [(set (match_operand:DI 0 "general_operand" "=ro,<,>")
3894 (ashift:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
3900 if (GET_CODE (operands[1]) == REG)
3901 operands[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
3903 operands[3] = adj_offsettable_operand (operands[1], 4);
3904 if (which_alternative == 1)
3905 return \"clr%.l %0\;move%.l %3,%0\";
3906 if (which_alternative == 2)
3907 return \"move%.l %3,%0\;clr%.l %0\";
3908 if (GET_CODE (operands[0]) == REG)
3909 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3911 operands[2] = adj_offsettable_operand (operands[0], 4);
3912 if (ADDRESS_REG_P (operands[2]))
3913 return \"move%.l %3,%0\;sub%.l %2,%2\";
3915 return \"move%.l %3,%0\;clr%.l %2\";
3918 (define_insn "ashldi_const"
3919 [(set (match_operand:DI 0 "general_operand" "=d")
3920 (ashift:DI (match_operand:DI 1 "general_operand" "0")
3921 (match_operand 2 "const_int_operand" "n")))]
3922 "(INTVAL (operands[2]) == 1
3923 || INTVAL (operands[2]) == 2 || INTVAL (operands[2]) == 3)"
3926 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3927 if (INTVAL (operands[2]) == 1)
3928 return \"add%.l %1,%1\;addx%.l %0,%0\";
3929 else if (INTVAL (operands[2]) == 2)
3930 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
3931 else/* if (INTVAL (operands[2]) == 3)*/
3932 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
3935 (define_expand "ashldi3"
3936 [(set (match_operand:DI 0 "general_operand" "=rm")
3937 (ashift:DI (match_operand:DI 1 "general_operand" "rm")
3938 (match_operand 2 "const_int_operand" "n")))]
3942 if (GET_CODE (operands[2]) != CONST_INT
3943 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 32
3944 && INTVAL (operands[2]) != 2 && INTVAL (operands[2]) != 3))
3948 ;; On all 68k models, this makes faster code in a special case.
3951 [(set (match_operand:SI 0 "register_operand" "=d")
3952 (ashift:SI (match_operand:SI 1 "register_operand" "0")
3958 return \"swap %0\;clr%.w %0\";
3961 ;; On the 68000, this makes faster code in a special case.
3964 [(set (match_operand:SI 0 "register_operand" "=d")
3965 (ashift:SI (match_operand:SI 1 "register_operand" "0")
3966 (match_operand:SI 2 "const_int_operand" "n")))]
3968 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
3973 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
3974 return \"asl%.w %2,%0\;swap %0\;clr%.w %0\";
3977 (define_insn "ashlsi3"
3978 [(set (match_operand:SI 0 "register_operand" "=d")
3979 (ashift:SI (match_operand:SI 1 "register_operand" "0")
3980 (match_operand:SI 2 "general_operand" "dI")))]
3984 if (operands[2] == const1_rtx)
3985 return \"add%.l %0,%0\";
3986 return \"asl%.l %2,%0\";
3989 (define_insn "ashlhi3"
3990 [(set (match_operand:HI 0 "register_operand" "=d")
3991 (ashift:HI (match_operand:HI 1 "register_operand" "0")
3992 (match_operand:HI 2 "general_operand" "dI")))]
3997 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
3998 (ashift:HI (match_dup 0)
3999 (match_operand:HI 1 "general_operand" "dI")))]
4003 (define_insn "ashlqi3"
4004 [(set (match_operand:QI 0 "register_operand" "=d")
4005 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4006 (match_operand:QI 2 "general_operand" "dI")))]
4011 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4012 (ashift:QI (match_dup 0)
4013 (match_operand:QI 1 "general_operand" "dI")))]
4017 ;; On all 68k models, this makes faster code in a special case.
4020 [(set (match_operand:SI 0 "register_operand" "=d")
4021 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4024 "swap %0\;ext%.l %0")
4026 ;; On the 68000, this makes faster code in a special case.
4029 [(set (match_operand:SI 0 "register_operand" "=d")
4030 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4031 (match_operand:SI 2 "const_int_operand" "n")))]
4033 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4036 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4037 return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
4040 (define_insn "subreg1ashrdi_const32"
4041 [(set (match_operand:SI 0 "general_operand" "=rm")
4042 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4043 (const_int 32)) 1))]
4047 return \"move%.l %1,%0\";
4050 (define_insn "ashrdi_const32"
4051 [(set (match_operand:DI 0 "general_operand" "=d")
4052 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4058 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4060 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
4062 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
4065 (define_insn "ashrdi_const32_mem"
4066 [(set (match_operand:DI 0 "general_operand" "=o,<")
4067 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro")
4069 (clobber (match_scratch:SI 2 "=d,d"))]
4074 if (which_alternative == 1)
4075 operands[3] = operands[0];
4077 operands[3] = adj_offsettable_operand (operands[0], 4);
4079 return \"move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0\";
4081 return \"move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\";
4084 (define_insn "ashrdi_const"
4085 [(set (match_operand:DI 0 "general_operand" "=d")
4086 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
4087 (match_operand 2 "const_int_operand" "n")))]
4088 "(INTVAL (operands[2]) == 1
4089 || INTVAL (operands[2]) == 2 || INTVAL (operands[2]) == 3)"
4092 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4094 if (INTVAL (operands[2]) == 1)
4095 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
4096 else if (INTVAL (operands[2]) == 2)
4097 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4098 else/* if (INTVAL (operands[2]) == 3)*/
4099 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4102 (define_expand "ashrdi3"
4103 [(set (match_operand:DI 0 "general_operand" "=rm")
4104 (ashiftrt:DI (match_operand:DI 1 "general_operand" "rm")
4105 (match_operand 2 "const_int_operand" "n")))]
4109 if (GET_CODE (operands[2]) != CONST_INT
4110 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 32
4111 && INTVAL (operands[2]) != 2 && INTVAL (operands[2]) != 3))
4115 (define_insn "ashrsi3"
4116 [(set (match_operand:SI 0 "register_operand" "=d")
4117 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4118 (match_operand:SI 2 "general_operand" "dI")))]
4122 (define_insn "ashrhi3"
4123 [(set (match_operand:HI 0 "register_operand" "=d")
4124 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4125 (match_operand:HI 2 "general_operand" "dI")))]
4130 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4131 (ashiftrt:HI (match_dup 0)
4132 (match_operand:HI 1 "general_operand" "dI")))]
4136 (define_insn "ashrqi3"
4137 [(set (match_operand:QI 0 "register_operand" "=d")
4138 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4139 (match_operand:QI 2 "general_operand" "dI")))]
4144 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4145 (ashiftrt:QI (match_dup 0)
4146 (match_operand:QI 1 "general_operand" "dI")))]
4150 ;; logical shift instructions
4152 (define_insn "subreg1lshrdi_const32"
4153 [(set (match_operand:SI 0 "general_operand" "=rm")
4154 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4155 (const_int 32)) 1))]
4159 return \"move%.l %1,%0\";
4162 (define_insn "lshrdi_const32"
4163 [(set (match_operand:DI 0 "general_operand" "=ro,<,>")
4164 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
4170 if (which_alternative == 1)
4171 return \"move%.l %1,%0\;clr%.l %0\";
4172 if (which_alternative == 2)
4173 return \"clr%.l %0\;move%.l %1,%0\";
4174 if (GET_CODE (operands[0]) == REG)
4175 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4177 operands[2] = adj_offsettable_operand (operands[0], 4);
4178 if (GET_CODE (operands[1]) == REG)
4179 operands[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4181 operands[3] = adj_offsettable_operand (operands[1], 4);
4182 if (ADDRESS_REG_P (operands[0]))
4183 return \"move%.l %1,%2\;sub%.l %0,%0\";
4185 return \"move%.l %1,%2\;clr%.l %0\";
4188 (define_insn "lshrdi_const"
4189 [(set (match_operand:DI 0 "general_operand" "=d")
4190 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
4191 (match_operand 2 "const_int_operand" "n")))]
4192 "(INTVAL (operands[2]) == 1
4193 || INTVAL (operands[2]) == 2 || INTVAL (operands[2]) == 3)"
4197 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4198 if (INTVAL (operands[2]) == 1)
4199 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4200 else if (INTVAL (operands[2]) == 2)
4201 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4202 else /*if (INTVAL (operands[2]) == 3)*/
4203 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4206 (define_expand "lshrdi3"
4207 [(set (match_operand:DI 0 "general_operand" "=rm")
4208 (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
4209 (match_operand 2 "const_int_operand" "n")))]
4213 if (GET_CODE (operands[2]) != CONST_INT
4214 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 32
4215 && INTVAL (operands[2]) != 2 && INTVAL (operands[2]) != 3))
4219 ;; On all 68k models, this makes faster code in a special case.
4221 (define_insn "lshrsi_31"
4222 [(set (match_operand:SI 0 "register_operand" "=d")
4223 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4228 #if defined(MOTOROLA) && !defined(CRDS)
4229 return \"roxl%.l %#1,%0\;moveq%.l %#0,%d0\;roxl%.l %#1,%0\";
4231 return \"roxl%.l %#1,%0\;moveq %#0,%d0\;roxl%.l %#1,%0\";
4235 ;; On all 68k models, this makes faster code in a special case.
4237 (define_insn "lshrsi_16"
4238 [(set (match_operand:SI 0 "register_operand" "=d")
4239 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4245 return \"clr%.w %0\;swap %0\";
4248 ;; On the 68000, this makes faster code in a special case.
4250 (define_insn "lshrsi_17_24"
4251 [(set (match_operand:SI 0 "register_operand" "=d")
4252 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4253 (match_operand:SI 2 "const_int_operand" "n")))]
4255 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4258 /* I think lsr%.w sets the CC properly. */
4259 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4260 return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\";
4263 (define_insn "lshrsi3"
4264 [(set (match_operand:SI 0 "register_operand" "=d")
4265 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4266 (match_operand:SI 2 "general_operand" "dI")))]
4270 (define_insn "lshrhi3"
4271 [(set (match_operand:HI 0 "register_operand" "=d")
4272 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
4273 (match_operand:HI 2 "general_operand" "dI")))]
4278 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4279 (lshiftrt:HI (match_dup 0)
4280 (match_operand:HI 1 "general_operand" "dI")))]
4284 (define_insn "lshrqi3"
4285 [(set (match_operand:QI 0 "register_operand" "=d")
4286 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
4287 (match_operand:QI 2 "general_operand" "dI")))]
4292 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4293 (lshiftrt:QI (match_dup 0)
4294 (match_operand:QI 1 "general_operand" "dI")))]
4298 ;; rotate instructions
4300 (define_insn "rotlsi3"
4301 [(set (match_operand:SI 0 "register_operand" "=d")
4302 (rotate:SI (match_operand:SI 1 "register_operand" "0")
4303 (match_operand:SI 2 "general_operand" "dI")))]
4307 (define_insn "rotlhi3"
4308 [(set (match_operand:HI 0 "register_operand" "=d")
4309 (rotate:HI (match_operand:HI 1 "register_operand" "0")
4310 (match_operand:HI 2 "general_operand" "dI")))]
4316 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4317 (rotate:HI (match_dup 0)
4318 (match_operand:HI 1 "general_operand" "dI")))]
4322 (define_insn "rotlqi3"
4323 [(set (match_operand:QI 0 "register_operand" "=d")
4324 (rotate:QI (match_operand:QI 1 "register_operand" "0")
4325 (match_operand:QI 2 "general_operand" "dI")))]
4330 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4331 (rotate:QI (match_dup 0)
4332 (match_operand:QI 1 "general_operand" "dI")))]
4336 (define_insn "rotrsi3"
4337 [(set (match_operand:SI 0 "register_operand" "=d")
4338 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
4339 (match_operand:SI 2 "general_operand" "dI")))]
4343 (define_insn "rotrhi3"
4344 [(set (match_operand:HI 0 "register_operand" "=d")
4345 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
4346 (match_operand:HI 2 "general_operand" "dI")))]
4351 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4352 (rotatert:HI (match_dup 0)
4353 (match_operand:HI 1 "general_operand" "dI")))]
4357 (define_insn "rotrqi3"
4358 [(set (match_operand:QI 0 "register_operand" "=d")
4359 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
4360 (match_operand:QI 2 "general_operand" "dI")))]
4365 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4366 (rotatert:QI (match_dup 0)
4367 (match_operand:QI 1 "general_operand" "dI")))]
4372 ;; Bit set/clear in memory byte.
4374 ;; set bit, bit number is int
4375 (define_insn "bsetmemqi"
4376 [(set (match_operand:QI 0 "memory_operand" "+m")
4377 (ior:QI (subreg:QI (ashift:SI (const_int 1)
4378 (match_operand:SI 1 "general_operand" "d")) 0)
4384 return \"bset %1,%0\";
4387 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
4389 [(set (match_operand:QI 0 "memory_operand" "+m")
4390 (ior:QI (subreg:QI (ashift:SI (const_int 1)
4391 (match_operator:SI 2 "extend_operator"
4392 [(match_operand 1 "general_operand" "d")])) 0)
4398 return \"bset %1,%0\";
4401 ;; clear bit, bit number is int
4402 (define_insn "bclrmemqi"
4403 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
4405 (minus:SI (const_int 7)
4406 (match_operand:SI 1 "general_operand" "d")))
4412 return \"bclr %1,%0\";
4415 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
4417 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
4419 (minus:SI (const_int 7)
4420 (match_operator:SI 2 "extend_operator"
4421 [(match_operand 1 "general_operand" "d")])))
4427 return \"bclr %1,%0\";
4430 ;; Special cases of bit-field insns which we should
4431 ;; recognize in preference to the general case.
4432 ;; These handle aligned 8-bit and 16-bit fields,
4433 ;; which can usually be done with move instructions.
4436 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4437 ; alignment of structure members is specified.
4439 ; The move is allowed to be odd byte aligned, because that's still faster
4440 ; than an odd byte aligned bit field instruction.
4443 [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o")
4445 (match_operand:SI 2 "const_int_operand" "n"))
4446 (match_operand:SI 3 "general_operand" "rmi"))]
4447 "TARGET_68020 && TARGET_BITFIELD
4448 && (INTVAL (operands[2]) % 8) == 0
4449 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
4453 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
4455 return \"move%.l %3,%0\";
4459 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+do")
4460 (match_operand:SI 1 "const_int_operand" "n")
4461 (match_operand:SI 2 "const_int_operand" "n"))
4462 (match_operand:SI 3 "register_operand" "d"))]
4463 "TARGET_68020 && TARGET_BITFIELD
4464 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
4465 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
4466 && (GET_CODE (operands[0]) == REG
4467 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
4470 if (REG_P (operands[0]))
4472 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
4473 return \"bfins %3,%0{%b2:%b1}\";
4477 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
4479 if (GET_CODE (operands[3]) == MEM)
4480 operands[3] = adj_offsettable_operand (operands[3],
4481 (32 - INTVAL (operands[1])) / 8);
4482 if (INTVAL (operands[1]) == 8)
4483 return \"move%.b %3,%0\";
4484 return \"move%.w %3,%0\";
4489 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4490 ; alignment of structure members is specified.
4492 ; The move is allowed to be odd byte aligned, because that's still faster
4493 ; than an odd byte aligned bit field instruction.
4496 [(set (match_operand:SI 0 "general_operand" "=rm")
4497 (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o")
4499 (match_operand:SI 3 "const_int_operand" "n")))]
4500 "TARGET_68020 && TARGET_BITFIELD
4501 && (INTVAL (operands[3]) % 8) == 0
4502 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
4506 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
4508 return \"move%.l %1,%0\";
4512 [(set (match_operand:SI 0 "general_operand" "=&d")
4513 (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do")
4514 (match_operand:SI 2 "const_int_operand" "n")
4515 (match_operand:SI 3 "const_int_operand" "n")))]
4516 "TARGET_68020 && TARGET_BITFIELD
4517 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
4518 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
4519 && (GET_CODE (operands[1]) == REG
4520 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
4523 cc_status.flags |= CC_NOT_NEGATIVE;
4524 if (REG_P (operands[1]))
4526 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
4527 return \"bfextu %1{%b3:%b2},%0\";
4531 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
4533 output_asm_insn (\"clr%.l %0\", operands);
4534 if (GET_CODE (operands[0]) == MEM)
4535 operands[0] = adj_offsettable_operand (operands[0],
4536 (32 - INTVAL (operands[1])) / 8);
4537 if (INTVAL (operands[2]) == 8)
4538 return \"move%.b %1,%0\";
4539 return \"move%.w %1,%0\";
4543 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4544 ; alignment of structure members is specified.
4546 ; The move is allowed to be odd byte aligned, because that's still faster
4547 ; than an odd byte aligned bit field instruction.
4550 [(set (match_operand:SI 0 "general_operand" "=rm")
4551 (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o")
4553 (match_operand:SI 3 "const_int_operand" "n")))]
4554 "TARGET_68020 && TARGET_BITFIELD
4555 && (INTVAL (operands[3]) % 8) == 0
4556 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
4560 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
4562 return \"move%.l %1,%0\";
4566 [(set (match_operand:SI 0 "general_operand" "=d")
4567 (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do")
4568 (match_operand:SI 2 "const_int_operand" "n")
4569 (match_operand:SI 3 "const_int_operand" "n")))]
4570 "TARGET_68020 && TARGET_BITFIELD
4571 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
4572 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
4573 && (GET_CODE (operands[1]) == REG
4574 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
4577 if (REG_P (operands[1]))
4579 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
4580 return \"bfexts %1{%b3:%b2},%0\";
4584 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
4586 if (INTVAL (operands[2]) == 8)
4587 return \"move%.b %1,%0\;extb%.l %0\";
4588 return \"move%.w %1,%0\;ext%.l %0\";
4591 ;; Bit field instructions, general cases.
4592 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
4593 ;; so that its address is reloaded.
4596 [(set (match_operand:SI 0 "general_operand" "=d,d")
4597 (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o,d")
4598 (match_operand:SI 2 "general_operand" "di,di")
4599 (match_operand:SI 3 "general_operand" "di,di")))]
4600 "TARGET_68020 && TARGET_BITFIELD"
4601 "bfexts %1{%b3:%b2},%0")
4603 (define_insn "extzv"
4604 [(set (match_operand:SI 0 "general_operand" "=d,d")
4605 (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o,d")
4606 (match_operand:SI 2 "general_operand" "di,di")
4607 (match_operand:SI 3 "general_operand" "di,di")))]
4608 "TARGET_68020 && TARGET_BITFIELD"
4611 if (GET_CODE (operands[2]) == CONST_INT)
4613 if (INTVAL (operands[2]) != 32)
4614 cc_status.flags |= CC_NOT_NEGATIVE;
4620 return \"bfextu %1{%b3:%b2},%0\";
4624 [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
4625 (match_operand:SI 1 "general_operand" "di,di")
4626 (match_operand:SI 2 "general_operand" "di,di"))
4627 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
4628 (match_operand 3 "const_int_operand" "n,n")))]
4629 "TARGET_68020 && TARGET_BITFIELD
4630 && (INTVAL (operands[3]) == -1
4631 || (GET_CODE (operands[1]) == CONST_INT
4632 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
4636 return \"bfchg %0{%b2:%b1}\";
4640 [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
4641 (match_operand:SI 1 "general_operand" "di,di")
4642 (match_operand:SI 2 "general_operand" "di,di"))
4644 "TARGET_68020 && TARGET_BITFIELD"
4648 return \"bfclr %0{%b2:%b1}\";
4652 [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
4653 (match_operand:SI 1 "general_operand" "di,di")
4654 (match_operand:SI 2 "general_operand" "di,di"))
4656 "TARGET_68020 && TARGET_BITFIELD"
4660 return \"bfset %0{%b2:%b1}\";
4664 [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
4665 (match_operand:SI 1 "general_operand" "di,di")
4666 (match_operand:SI 2 "general_operand" "di,di"))
4667 (match_operand:SI 3 "register_operand" "d,d"))]
4668 "TARGET_68020 && TARGET_BITFIELD"
4669 "bfins %3,%0{%b2:%b1}")
4671 ;; Now recognize bit field insns that operate on registers
4672 ;; (or at least were intended to do so).
4675 [(set (match_operand:SI 0 "general_operand" "=d")
4676 (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "d")
4677 (match_operand:SI 2 "general_operand" "di")
4678 (match_operand:SI 3 "general_operand" "di")))]
4679 "TARGET_68020 && TARGET_BITFIELD"
4680 "bfexts %1{%b3:%b2},%0")
4683 [(set (match_operand:SI 0 "general_operand" "=d")
4684 (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "d")
4685 (match_operand:SI 2 "general_operand" "di")
4686 (match_operand:SI 3 "general_operand" "di")))]
4687 "TARGET_68020 && TARGET_BITFIELD"
4690 if (GET_CODE (operands[2]) == CONST_INT)
4692 if (INTVAL (operands[2]) != 32)
4693 cc_status.flags |= CC_NOT_NEGATIVE;
4699 return \"bfextu %1{%b3:%b2},%0\";
4703 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")
4704 (match_operand:SI 1 "general_operand" "di")
4705 (match_operand:SI 2 "general_operand" "di"))
4707 "TARGET_68020 && TARGET_BITFIELD"
4711 return \"bfclr %0{%b2:%b1}\";
4715 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")
4716 (match_operand:SI 1 "general_operand" "di")
4717 (match_operand:SI 2 "general_operand" "di"))
4719 "TARGET_68020 && TARGET_BITFIELD"
4723 return \"bfset %0{%b2:%b1}\";
4727 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")
4728 (match_operand:SI 1 "general_operand" "di")
4729 (match_operand:SI 2 "general_operand" "di"))
4730 (match_operand:SI 3 "register_operand" "d"))]
4731 "TARGET_68020 && TARGET_BITFIELD"
4735 /* These special cases are now recognized by a specific pattern. */
4736 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
4737 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
4738 return \"move%.w %3,%0\";
4739 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
4740 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
4741 return \"move%.b %3,%0\";
4743 return \"bfins %3,%0{%b2:%b1}\";
4746 ;; Special patterns for optimizing bit-field instructions.
4750 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
4751 (match_operand:SI 1 "const_int_operand" "n")
4752 (match_operand:SI 2 "general_operand" "di")))]
4753 "TARGET_68020 && TARGET_BITFIELD"
4756 if (operands[1] == const1_rtx
4757 && GET_CODE (operands[2]) == CONST_INT)
4759 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
4760 return output_btst (operands,
4761 gen_rtx (CONST_INT, VOIDmode,
4762 width - INTVAL (operands[2])),
4765 /* Pass 1000 as SIGNPOS argument so that btst will
4766 not think we are testing the sign bit for an `and'
4767 and assume that nonzero implies a negative result. */
4769 if (INTVAL (operands[1]) != 32)
4770 cc_status.flags = CC_NOT_NEGATIVE;
4771 return \"bftst %0{%b2:%b1}\";
4775 ;;; now handle the register cases
4778 (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "d")
4779 (match_operand:SI 1 "const_int_operand" "n")
4780 (match_operand:SI 2 "general_operand" "di")))]
4781 "TARGET_68020 && TARGET_BITFIELD"
4784 if (operands[1] == const1_rtx
4785 && GET_CODE (operands[2]) == CONST_INT)
4787 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
4788 return output_btst (operands,
4789 gen_rtx (CONST_INT, VOIDmode,
4790 width - INTVAL (operands[2])),
4793 /* Pass 1000 as SIGNPOS argument so that btst will
4794 not think we are testing the sign bit for an `and'
4795 and assume that nonzero implies a negative result. */
4797 if (INTVAL (operands[1]) != 32)
4798 cc_status.flags = CC_NOT_NEGATIVE;
4799 return \"bftst %0{%b2:%b1}\";
4803 [(set (match_operand:QI 0 "general_operand" "=d")
4804 (eq:QI (cc0) (const_int 0)))]
4807 cc_status = cc_prev_status;
4808 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
4812 [(set (match_operand:QI 0 "general_operand" "=d")
4813 (ne:QI (cc0) (const_int 0)))]
4816 cc_status = cc_prev_status;
4817 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
4821 [(set (match_operand:QI 0 "general_operand" "=d")
4822 (gt:QI (cc0) (const_int 0)))]
4825 cc_status = cc_prev_status;
4826 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
4830 [(set (match_operand:QI 0 "general_operand" "=d")
4831 (gtu:QI (cc0) (const_int 0)))]
4833 "* cc_status = cc_prev_status;
4834 return \"shi %0\"; ")
4837 [(set (match_operand:QI 0 "general_operand" "=d")
4838 (lt:QI (cc0) (const_int 0)))]
4840 "* cc_status = cc_prev_status;
4841 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
4844 [(set (match_operand:QI 0 "general_operand" "=d")
4845 (ltu:QI (cc0) (const_int 0)))]
4847 "* cc_status = cc_prev_status;
4848 return \"scs %0\"; ")
4851 [(set (match_operand:QI 0 "general_operand" "=d")
4852 (ge:QI (cc0) (const_int 0)))]
4854 "* cc_status = cc_prev_status;
4855 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
4858 [(set (match_operand:QI 0 "general_operand" "=d")
4859 (geu:QI (cc0) (const_int 0)))]
4861 "* cc_status = cc_prev_status;
4862 return \"scc %0\"; ")
4865 [(set (match_operand:QI 0 "general_operand" "=d")
4866 (le:QI (cc0) (const_int 0)))]
4869 cc_status = cc_prev_status;
4870 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
4874 [(set (match_operand:QI 0 "general_operand" "=d")
4875 (leu:QI (cc0) (const_int 0)))]
4877 "* cc_status = cc_prev_status;
4878 return \"sls %0\"; ")
4880 ;; Basic conditional jump instructions.
4884 (if_then_else (eq (cc0)
4886 (label_ref (match_operand 0 "" ""))
4892 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
4894 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
4900 (if_then_else (ne (cc0)
4902 (label_ref (match_operand 0 "" ""))
4908 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
4910 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
4916 (if_then_else (gt (cc0)
4918 (label_ref (match_operand 0 "" ""))
4923 OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0);
4925 OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0);
4931 (if_then_else (gtu (cc0)
4933 (label_ref (match_operand 0 "" ""))
4938 return \"jbhi %l0\";
4946 (if_then_else (lt (cc0)
4948 (label_ref (match_operand 0 "" ""))
4953 OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\");
4955 OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\");
4961 (if_then_else (ltu (cc0)
4963 (label_ref (match_operand 0 "" ""))
4968 return \"jbcs %l0\";
4976 (if_then_else (ge (cc0)
4978 (label_ref (match_operand 0 "" ""))
4983 OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\");
4985 OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\");
4991 (if_then_else (geu (cc0)
4993 (label_ref (match_operand 0 "" ""))
4998 return \"jbcc %l0\";
5006 (if_then_else (le (cc0)
5008 (label_ref (match_operand 0 "" ""))
5013 OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0);
5015 OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0);
5021 (if_then_else (leu (cc0)
5023 (label_ref (match_operand 0 "" ""))
5028 return \"jbls %l0\";
5034 ;; Negated conditional jump instructions.
5038 (if_then_else (eq (cc0)
5041 (label_ref (match_operand 0 "" ""))))]
5046 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
5048 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
5054 (if_then_else (ne (cc0)
5057 (label_ref (match_operand 0 "" ""))))]
5062 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
5064 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
5070 (if_then_else (gt (cc0)
5073 (label_ref (match_operand 0 "" ""))))]
5077 OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0);
5079 OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0);
5085 (if_then_else (gtu (cc0)
5088 (label_ref (match_operand 0 "" ""))))]
5092 return \"jbls %l0\";
5100 (if_then_else (lt (cc0)
5103 (label_ref (match_operand 0 "" ""))))]
5107 OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\");
5109 OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\");
5115 (if_then_else (ltu (cc0)
5118 (label_ref (match_operand 0 "" ""))))]
5122 return \"jbcc %l0\";
5130 (if_then_else (ge (cc0)
5133 (label_ref (match_operand 0 "" ""))))]
5137 OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\");
5139 OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\");
5145 (if_then_else (geu (cc0)
5148 (label_ref (match_operand 0 "" ""))))]
5152 return \"jbcs %l0\";
5160 (if_then_else (le (cc0)
5163 (label_ref (match_operand 0 "" ""))))]
5167 OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0);
5169 OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0);
5175 (if_then_else (leu (cc0)
5178 (label_ref (match_operand 0 "" ""))))]
5182 return \"jbhi %l0\";
5188 ;; Unconditional and other jump instructions
5191 (label_ref (match_operand 0 "" "")))]
5195 return \"jbra %l0\";
5201 ;; We support two different ways of handling dispatch tables.
5202 ;; The NeXT uses absolute tables, and other machines use relative.
5203 ;; This define_expand can generate either kind.
5204 (define_expand "tablejump"
5205 [(parallel [(set (pc) (match_operand 0 "" ""))
5206 (use (label_ref (match_operand 1 "" "")))])]
5210 #ifdef CASE_VECTOR_PC_RELATIVE
5211 operands[0] = gen_rtx (PLUS, SImode, pc_rtx,
5212 gen_rtx (SIGN_EXTEND, SImode, operands[0]));
5216 ;; Jump to variable address from dispatch table of absolute addresses.
5218 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
5219 (use (label_ref (match_operand 1 "" "")))]
5223 return \"jmp (%0)\";
5229 ;; Jump to variable address from dispatch table of relative addresses.
5233 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
5234 (use (label_ref (match_operand 1 "" "")))]
5237 #ifdef ASM_RETURN_CASE_JUMP
5238 ASM_RETURN_CASE_JUMP;
5241 #ifdef ASM_OUTPUT_CASE_LABEL
5242 return \"jmp 6(%%pc,%0.w)\";
5245 return \"jmp 2(pc,%0.w)\";
5247 return \"jmp 2(%%pc,%0.w)\";
5248 #endif /* end !CRDS */
5252 return \"jmp (2,pc,%0.w)\";
5254 return \"jmp pc@(2,%0:w)\";
5260 ;; Decrement-and-branch insns.
5264 (ne (match_operand:HI 0 "general_operand" "+g")
5266 (label_ref (match_operand 1 "" ""))
5269 (plus:HI (match_dup 0)
5275 if (DATA_REG_P (operands[0]))
5276 return \"dbra %0,%l1\";
5277 if (GET_CODE (operands[0]) == MEM)
5281 return \"sub%.w %#1,%0\;jbcc %l1\";
5283 return \"subq%.w %#1,%0\;jbcc %l1\";
5285 #else /* not MOTOROLA */
5286 return \"subqw %#1,%0\;jcc %l1\";
5290 #ifdef SGS_CMP_ORDER
5292 return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
5294 return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
5296 #else /* not SGS_CMP_ORDER */
5297 return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
5299 #else /* not MOTOROLA */
5300 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
5307 (ne (match_operand:SI 0 "general_operand" "+g")
5309 (label_ref (match_operand 1 "" ""))
5312 (plus:SI (match_dup 0)
5320 if (DATA_REG_P (operands[0]))
5321 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
5322 if (GET_CODE (operands[0]) == MEM)
5323 return \"sub%.l %#1,%0\;jbcc %l1\";
5325 if (DATA_REG_P (operands[0]))
5326 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
5327 if (GET_CODE (operands[0]) == MEM)
5328 return \"subq%.l %#1,%0\;jbcc %l1\";
5329 #endif /* NO_ADDSUB_Q */
5330 #ifdef SGS_CMP_ORDER
5332 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
5334 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
5336 #else /* not SGS_CMP_ORDER */
5337 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
5338 #endif /* not SGS_CMP_ORDER */
5339 #else /* not MOTOROLA */
5340 if (DATA_REG_P (operands[0]))
5341 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
5342 if (GET_CODE (operands[0]) == MEM)
5343 return \"subql %#1,%0\;jcc %l1\";
5344 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
5345 #endif /* not MOTOROLA */
5348 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
5353 (ge (plus:HI (match_operand:HI 0 "general_operand" "+g")
5356 (label_ref (match_operand 1 "" ""))
5359 (plus:HI (match_dup 0)
5361 "find_reg_note (insn, REG_NONNEG, 0)"
5367 if (DATA_REG_P (operands[0]))
5368 return \"dbra %0,%l1\";
5369 if (GET_CODE (operands[0]) == MEM)
5370 return \"sub%.w %#1,%0\;jbcc %l1\";
5372 if (DATA_REG_P (operands[0]))
5373 return \"dbra %0,%l1\";
5374 if (GET_CODE (operands[0]) == MEM)
5375 return \"subq%.w %#1,%0\;jbcc %l1\";
5377 #ifdef SGS_CMP_ORDER
5379 return \"sub.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
5381 return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
5383 #else /* not SGS_CMP_ORDER */
5384 return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\";
5385 #endif /* not SGS_CMP_ORDER */
5386 #else /* not MOTOROLA */
5387 if (DATA_REG_P (operands[0]))
5388 return \"dbra %0,%l1\";
5389 if (GET_CODE (operands[0]) == MEM)
5390 return \"subqw %#1,%0\;jcc %l1\";
5391 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
5392 #endif /* not MOTOROLA */
5395 (define_insn "decrement_and_branch_until_zero"
5398 (ge (plus:SI (match_operand:SI 0 "general_operand" "+g")
5401 (label_ref (match_operand 1 "" ""))
5404 (plus:SI (match_dup 0)
5406 "find_reg_note (insn, REG_NONNEG, 0)"
5412 if (DATA_REG_P (operands[0]))
5413 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
5414 if (GET_CODE (operands[0]) == MEM)
5415 return \"sub%.l %#1,%0\;jbcc %l1\";
5417 if (DATA_REG_P (operands[0]))
5418 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
5419 if (GET_CODE (operands[0]) == MEM)
5420 return \"subq%.l %#1,%0\;jbcc %l1\";
5422 #ifdef SGS_CMP_ORDER
5424 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
5426 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
5428 #else /* not SGS_CMP_ORDER */
5429 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
5430 #endif /* not SGS_CMP_ORDER */
5431 #else /* not MOTOROLA */
5432 if (DATA_REG_P (operands[0]))
5433 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
5434 if (GET_CODE (operands[0]) == MEM)
5435 return \"subql %#1,%0\;jcc %l1\";
5436 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
5437 #endif /* not MOTOROLA */
5441 ;; PIC calls are handled by loading the address of the function into a
5442 ;; register (via movsi), then emitting a register indirect call using
5443 ;; the "jsr" function call syntax.
5445 ;; It is important to note that the "jsr" syntax is always used for
5446 ;; PIC calls, even on machines in which GCC normally uses the "jbsr"
5447 ;; syntax for non-PIC calls. This keeps at least 1 assembler (Sun)
5448 ;; from emitting incorrect code for a PIC call.
5450 ;; We have different patterns for PIC calls and non-PIC calls. The
5451 ;; different patterns are only used to choose the right syntax
5452 ;; ("jsr" vs "jbsr").
5454 ;; On svr4 m68k, PIC stuff is done differently. To be able to support
5455 ;; dynamic linker LAZY BINDING, all the procedure calls need to go
5456 ;; through the PLT (Procedure Linkage Table) section in PIC mode. The
5457 ;; svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it
5458 ;; will create the correct relocation entry (R_68K_PLT32) for `FUNC',
5459 ;; that tells the linker editor to create an entry for `FUNC' in PLT
5460 ;; section at link time. However, all global objects reference are still
5461 ;; done by using `OBJ@GOT'. So, the goal here is to output the function
5462 ;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'.
5463 ;; We need to have a way to differentiate these two different operands.
5465 ;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate
5466 ;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs
5467 ;; to be changed to recognize function calls symbol_ref operand as a legal
5468 ;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will
5469 ;; avoid the compiler to load this symbol_ref operand into a register.
5470 ;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly
5471 ;; since the value is a PC relative offset, not a real address.
5473 ;; All global objects are treated in the similar way as in SUN3. The only
5474 ;; difference is: on m68k svr4, the reference of such global object needs
5475 ;; to end with a suffix "@GOT" so the assembler and linker know to create
5476 ;; an entry for it in GOT (Global Offset Table) section. This is done in
5479 ;; Call subroutine with no return value.
5480 (define_expand "call"
5481 [(call (match_operand:QI 0 "memory_operand" "")
5482 (match_operand:SI 1 "general_operand" ""))]
5483 ;; Operand 1 not really used on the m68000.
5488 if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
5490 SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
5492 operands[0] = gen_rtx (MEM, GET_MODE (operands[0]),
5493 force_reg (Pmode, XEXP (operands[0], 0)));
5497 ;; This is a normal call sequence.
5499 [(call (match_operand:QI 0 "memory_operand" "o")
5500 (match_operand:SI 1 "general_operand" "g"))]
5501 ;; Operand 1 not really used on the m68000.
5507 if (GET_CODE (operands[0]) == MEM
5508 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
5517 ;; This is a PIC call sequence.
5519 [(call (match_operand:QI 0 "memory_operand" "o")
5520 (match_operand:SI 1 "general_operand" "g"))]
5521 ;; Operand 1 not really used on the m68000.
5526 if (GET_CODE (operands[0]) == MEM
5527 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
5529 return \"bsr.l %0\";
5531 return \"bsr %0@PLTPC\";
5537 ;; Call subroutine, returning value in operand 0
5538 ;; (which must be a hard register).
5539 ;; See comments before "call" regarding PIC calls.
5540 (define_expand "call_value"
5541 [(set (match_operand 0 "" "")
5542 (call (match_operand:QI 1 "memory_operand" "")
5543 (match_operand:SI 2 "general_operand" "")))]
5544 ;; Operand 2 not really used on the m68000.
5548 if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
5550 SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
5552 operands[1] = gen_rtx (MEM, GET_MODE (operands[1]),
5553 force_reg (Pmode, XEXP (operands[1], 0)));
5557 ;; This is a normal call_value
5559 [(set (match_operand 0 "" "=rf")
5560 (call (match_operand:QI 1 "memory_operand" "o")
5561 (match_operand:SI 2 "general_operand" "g")))]
5562 ;; Operand 2 not really used on the m68000.
5567 if (GET_CODE (operands[1]) == MEM
5568 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
5577 ;; This is a PIC call_value
5579 [(set (match_operand 0 "" "=rf")
5580 (call (match_operand:QI 1 "memory_operand" "o")
5581 (match_operand:SI 2 "general_operand" "g")))]
5582 ;; Operand 2 not really used on the m68000.
5586 if (GET_CODE (operands[1]) == MEM
5587 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
5589 return \"bsr.l %1\";
5591 return \"bsr %1@PLTPC\";
5597 ;; Call subroutine returning any type.
5599 (define_expand "untyped_call"
5600 [(parallel [(call (match_operand 0 "" "")
5602 (match_operand 1 "" "")
5603 (match_operand 2 "" "")])]
5604 "NEEDS_UNTYPED_CALL"
5609 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
5611 for (i = 0; i < XVECLEN (operands[2], 0); i++)
5613 rtx set = XVECEXP (operands[2], 0, i);
5614 emit_move_insn (SET_DEST (set), SET_SRC (set));
5617 /* The optimizer does not know that the call sets the function value
5618 registers we stored in the result block. We avoid problems by
5619 claiming that all hard registers are used and clobbered at this
5621 emit_insn (gen_blockage ());
5626 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
5627 ;; all of memory. This blocks insns from being moved across this point.
5629 (define_insn "blockage"
5630 [(unspec_volatile [(const_int 0)] 0)]
5639 (define_insn "probe"
5644 operands[0] = gen_rtx (PLUS, SImode, stack_pointer_rtx,
5645 gen_rtx (CONST_INT, VOIDmode, NEED_PROBE));
5646 return \"tstl %a0\";
5649 ;; Used for frameless functions which save no regs and allocate no locals.
5650 (define_insn "return"
5655 if (current_function_pops_args == 0)
5657 operands[0] = gen_rtx (CONST_INT, VOIDmode, current_function_pops_args);
5661 (define_insn "indirect_jump"
5662 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
5666 ;; This should not be used unless the add/sub insns can't be.
5669 [(set (match_operand:SI 0 "general_operand" "=a")
5670 (match_operand:QI 1 "address_operand" "p"))]
5675 /* Recognize an insn that refers to a table of offsets. Such an insn will
5676 need to refer to a label on the insn. So output one. Use the
5677 label-number of the table of offsets to generate this label. This code,
5678 and similar code above, assumes that there will be at most one reference
5680 if (GET_CODE (operands[1]) == PLUS
5681 && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
5682 && GET_CODE (XEXP (operands[1], 0)) != PLUS)
5684 rtx labelref = XEXP (operands[1], 1);
5685 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
5687 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
5688 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
5690 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
5691 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
5692 #endif /* not SGS */
5693 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
5694 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
5695 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
5696 #ifdef SGS_SWITCH_TABLES
5697 /* Set flag saying we need to define the symbol
5698 LD%n (with value L%n-LI%n) at the end of the switch table. */
5699 switch_table_difference_label_flag = 1;
5700 #endif /* SGS_SWITCH_TABLES */
5701 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
5703 #endif /* SGS_NO_LI */
5705 return \"lea %a1,%0\";
5708 ;; This is the first machine-dependent peephole optimization.
5709 ;; It is useful when a floating value is returned from a function call
5710 ;; and then is moved into an FP register.
5711 ;; But it is mainly intended to test the support for these optimizations.
5714 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
5715 (set (match_operand:DF 0 "register_operand" "=f")
5716 (match_operand:DF 1 "register_operand" "ad"))]
5717 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
5721 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
5722 output_asm_insn (\"move%.l %1,%@\", xoperands);
5723 output_asm_insn (\"move%.l %1,%-\", operands);
5724 return \"fmove%.d %+,%0\";
5728 ;; Optimize a stack-adjust followed by a push of an argument.
5729 ;; This is said to happen frequently with -msoft-float
5730 ;; when there are consecutive library calls.
5733 [(set (reg:SI 15) (plus:SI (reg:SI 15)
5734 (match_operand:SI 0 "const_int_operand" "n")))
5735 (set (match_operand:SF 1 "push_operand" "=m")
5736 (match_operand:SF 2 "general_operand" "rmfF"))]
5737 "INTVAL (operands[0]) >= 4
5738 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
5741 if (INTVAL (operands[0]) > 4)
5744 xoperands[0] = stack_pointer_rtx;
5745 xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4);
5747 if (INTVAL (xoperands[1]) <= 8)
5748 output_asm_insn (\"addq%.w %1,%0\", xoperands);
5749 else if (INTVAL (xoperands[1]) <= 16 && TARGET_68020)
5751 xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
5752 INTVAL (xoperands[1]) - 8);
5753 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
5757 if (INTVAL (xoperands[1]) <= 0x7FFF)
5758 output_asm_insn (\"add%.w %1,%0\", xoperands);
5760 output_asm_insn (\"add%.l %1,%0\", xoperands);
5762 if (FP_REG_P (operands[2]))
5763 return \"fmove%.s %2,%@\";
5764 return \"move%.l %2,%@\";
5767 ;; Speed up stack adjust followed by a fullword fixedpoint push.
5770 [(set (reg:SI 15) (plus:SI (reg:SI 15)
5771 (match_operand:SI 0 "const_int_operand" "n")))
5772 (set (match_operand:SI 1 "push_operand" "=m")
5773 (match_operand:SI 2 "general_operand" "g"))]
5774 "INTVAL (operands[0]) >= 4
5775 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
5778 if (INTVAL (operands[0]) > 4)
5781 xoperands[0] = stack_pointer_rtx;
5782 xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4);
5784 if (INTVAL (xoperands[1]) <= 8)
5785 output_asm_insn (\"addq%.w %1,%0\", xoperands);
5786 else if (INTVAL (xoperands[1]) <= 16 && TARGET_68020)
5788 xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
5789 INTVAL (xoperands[1]) - 8);
5790 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
5794 if (INTVAL (xoperands[1]) <= 0x7FFF)
5795 output_asm_insn (\"add%.w %1,%0\", xoperands);
5797 output_asm_insn (\"add%.l %1,%0\", xoperands);
5799 if (operands[2] == const0_rtx)
5800 return \"clr%.l %@\";
5801 return \"move%.l %2,%@\";
5804 ;; Speed up pushing a single byte but leaving four bytes of space.
5807 [(set (mem:QI (pre_dec:SI (reg:SI 15)))
5808 (match_operand:QI 1 "general_operand" "dami"))
5809 (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))]
5810 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
5815 if (GET_CODE (operands[1]) == REG)
5816 return \"move%.l %1,%-\";
5818 xoperands[1] = operands[1];
5820 = gen_rtx (MEM, QImode,
5821 gen_rtx (PLUS, VOIDmode, stack_pointer_rtx,
5822 gen_rtx (CONST_INT, VOIDmode, 3)));
5823 xoperands[3] = stack_pointer_rtx;
5824 output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
5829 [(set (match_operand:SI 0 "register_operand" "=d")
5831 (set (strict_low_part (subreg:HI (match_dup 0) 0))
5832 (match_operand:HI 1 "general_operand" "rmn"))]
5833 "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
5836 if (GET_CODE (operands[1]) == CONST_INT)
5838 if (operands[1] == const0_rtx
5839 && (DATA_REG_P (operands[0])
5840 || GET_CODE (operands[0]) == MEM)
5841 /* clr insns on 68000 read before writing.
5842 This isn't so on the 68010, but we have no alternative for it. */
5844 || !(GET_CODE (operands[0]) == MEM
5845 && MEM_VOLATILE_P (operands[0]))))
5846 return \"clr%.w %0\";
5848 return \"move%.w %1,%0\";
5856 ;; jCC label ; abnormal loop termination
5857 ;; dbra dN, loop ; normal loop termination
5865 ;; Which moves the jCC condition outside the inner loop for free.
5868 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
5869 [(cc0) (const_int 0)])
5870 (label_ref (match_operand 2 "" ""))
5875 (ge (plus:HI (match_operand:HI 0 "register_operand" "+d")
5878 (label_ref (match_operand 1 "" ""))
5881 (plus:HI (match_dup 0)
5883 "DATA_REG_P (operands[0])"
5887 output_dbcc_and_branch (operands);
5892 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
5893 [(cc0) (const_int 0)])
5894 (label_ref (match_operand 2 "" ""))
5899 (ge (plus:SI (match_operand:SI 0 "register_operand" "+d")
5902 (label_ref (match_operand 1 "" ""))
5905 (plus:SI (match_dup 0)
5907 "DATA_REG_P (operands[0])"
5911 output_dbcc_and_branch (operands);
5916 ;; FPA multiply and add.
5918 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
5919 (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%x,dmF,y")
5920 (match_operand:DF 2 "general_operand" "xH,y,y"))
5921 (match_operand:DF 3 "general_operand" "xH,y,dmF")))]
5924 fpma%.d %1,%w2,%w3,%0
5925 fpma%.d %x1,%x2,%x3,%0
5926 fpma%.d %x1,%x2,%x3,%0")
5929 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
5930 (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%x,ydmF,y")
5931 (match_operand:SF 2 "general_operand" "xH,y,ydmF"))
5932 (match_operand:SF 3 "general_operand" "xH,ydmF,ydmF")))]
5935 fpma%.s %1,%w2,%w3,%0
5937 fpma%.s %1,%2,%3,%0")
5939 ;; FPA Multiply and subtract
5941 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
5942 (minus:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
5943 (mult:DF (match_operand:DF 2 "general_operand" "%xH,y,y")
5944 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
5947 fpms%.d %3,%w2,%w1,%0
5948 fpms%.d %x3,%2,%x1,%0
5949 fpms%.d %x3,%2,%x1,%0")
5952 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
5953 (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
5954 (mult:SF (match_operand:SF 2 "general_operand" "%xH,rmF,y")
5955 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
5958 fpms%.s %3,%w2,%w1,%0
5960 fpms%.s %3,%2,%1,%0")
5963 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
5964 (minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
5965 (match_operand:DF 2 "general_operand" "x,y,rmF"))
5966 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
5969 fpmr%.d %2,%w1,%w3,%0
5970 fpmr%.d %x2,%1,%x3,%0
5971 fpmr%.d %x2,%1,%x3,%0")
5974 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
5975 (minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
5976 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
5977 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
5980 fpmr%.s %2,%w1,%w3,%0
5981 fpmr%.s %x2,%1,%x3,%0
5982 fpmr%.s %x2,%1,%x3,%0")
5984 ;; FPA Add and multiply
5986 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
5987 (mult:DF (plus:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
5988 (match_operand:DF 2 "general_operand" "x,y,rmF"))
5989 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
5992 fpam%.d %2,%w1,%w3,%0
5993 fpam%.d %x2,%1,%x3,%0
5994 fpam%.d %x2,%1,%x3,%0")
5997 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
5998 (mult:SF (plus:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
5999 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
6000 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
6003 fpam%.s %2,%w1,%w3,%0
6004 fpam%.s %x2,%1,%x3,%0
6005 fpam%.s %x2,%1,%x3,%0")
6007 ;;FPA Subtract and multiply
6009 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6010 (mult:DF (minus:DF (match_operand:DF 1 "general_operand" "xH,y,y")
6011 (match_operand:DF 2 "general_operand" "x,y,rmF"))
6012 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
6015 fpsm%.d %2,%w1,%w3,%0
6016 fpsm%.d %x2,%1,%x3,%0
6017 fpsm%.d %x2,%1,%x3,%0")
6020 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6021 (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
6022 (minus:DF (match_operand:DF 2 "general_operand" "xH,y,y")
6023 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
6026 fpsm%.d %3,%w2,%w1,%0
6027 fpsm%.d %x3,%2,%x1,%0
6028 fpsm%.d %x3,%2,%x1,%0")
6031 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6032 (mult:SF (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,y")
6033 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
6034 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
6037 fpsm%.s %2,%w1,%w3,%0
6038 fpsm%.s %x2,%1,%x3,%0
6039 fpsm%.s %x2,%1,%x3,%0")
6042 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6043 (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
6044 (minus:SF (match_operand:SF 2 "general_operand" "xH,rmF,y")
6045 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
6048 fpsm%.s %3,%w2,%w1,%0
6049 fpsm%.s %x3,%2,%x1,%0
6050 fpsm%.s %x3,%2,%x1,%0")
6052 (define_insn "tstxf"
6054 (match_operand:XF 0 "nonimmediate_operand" "fm"))]
6058 cc_status.flags = CC_IN_68881;
6059 return \"ftst%.x %0\";
6063 (define_expand "cmpxf"
6065 (compare (match_operand:XF 0 "general_operand" "f,mG")
6066 (match_operand:XF 1 "general_operand" "fmG,f")))]
6070 if (CONSTANT_P (operands[0]))
6071 operands[0] = force_const_mem (XFmode, operands[0]);
6072 if (CONSTANT_P (operands[1]))
6073 operands[1] = force_const_mem (XFmode, operands[1]);
6078 (compare (match_operand:XF 0 "nonimmediate_operand" "f,mG")
6079 (match_operand:XF 1 "nonimmediate_operand" "fmG,f")))]
6083 cc_status.flags = CC_IN_68881;
6084 #ifdef SGS_CMP_ORDER
6085 if (REG_P (operands[0]))
6087 if (REG_P (operands[1]))
6088 return \"fcmp%.x %0,%1\";
6090 return \"fcmp%.x %0,%f1\";
6092 cc_status.flags |= CC_REVERSED;
6093 return \"fcmp%.x %1,%f0\";
6095 if (REG_P (operands[0]))
6097 if (REG_P (operands[1]))
6098 return \"fcmp%.x %1,%0\";
6100 return \"fcmp%.x %f1,%0\";
6102 cc_status.flags |= CC_REVERSED;
6103 return \"fcmp%.x %f0,%1\";
6107 (define_insn "extendsfxf2"
6108 [(set (match_operand:XF 0 "general_operand" "=fm,f")
6109 (float_extend:XF (match_operand:SF 1 "general_operand" "f,m")))]
6113 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
6115 if (REGNO (operands[0]) == REGNO (operands[1]))
6117 /* Extending float to double in an fp-reg is a no-op.
6118 NOTICE_UPDATE_CC has already assumed that the
6119 cc will be set. So cancel what it did. */
6120 cc_status = cc_prev_status;
6123 return \"f%$move%.x %1,%0\";
6125 if (FP_REG_P (operands[0]))
6126 return \"f%$move%.s %f1,%0\";
6127 return \"fmove%.x %f1,%0\";
6131 (define_insn "extenddfxf2"
6132 [(set (match_operand:XF 0 "general_operand" "=fm,f")
6134 (match_operand:DF 1 "general_operand" "f,m")))]
6138 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
6140 if (REGNO (operands[0]) == REGNO (operands[1]))
6142 /* Extending float to double in an fp-reg is a no-op.
6143 NOTICE_UPDATE_CC has already assumed that the
6144 cc will be set. So cancel what it did. */
6145 cc_status = cc_prev_status;
6148 return \"fmove%.x %1,%0\";
6150 if (FP_REG_P (operands[0]))
6151 return \"f%&move%.d %f1,%0\";
6152 return \"fmove%.x %f1,%0\";
6155 (define_insn "truncxfdf2"
6156 [(set (match_operand:DF 0 "general_operand" "=m,!r")
6158 (match_operand:XF 1 "general_operand" "f,f")))]
6162 if (REG_P (operands[0]))
6164 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
6165 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
6166 return \"move%.l %+,%0\";
6168 return \"fmove%.d %f1,%0\";
6171 (define_insn "truncxfsf2"
6172 [(set (match_operand:SF 0 "general_operand" "=dm")
6174 (match_operand:XF 1 "general_operand" "f")))]
6178 (define_insn "floatsixf2"
6179 [(set (match_operand:XF 0 "general_operand" "=f")
6180 (float:XF (match_operand:SI 1 "general_operand" "dmi")))]
6184 (define_insn "floathixf2"
6185 [(set (match_operand:XF 0 "general_operand" "=f")
6186 (float:XF (match_operand:HI 1 "general_operand" "dmn")))]
6190 (define_insn "floatqixf2"
6191 [(set (match_operand:XF 0 "general_operand" "=f")
6192 (float:XF (match_operand:QI 1 "general_operand" "dmn")))]
6196 (define_insn "ftruncxf2"
6197 [(set (match_operand:XF 0 "general_operand" "=f")
6198 (fix:XF (match_operand:XF 1 "general_operand" "fFm")))]
6202 if (FP_REG_P (operands[1]))
6203 return \"fintrz%.x %f1,%0\";
6204 return \"fintrz%.x %f1,%0\";
6207 (define_insn "fixxfqi2"
6208 [(set (match_operand:QI 0 "general_operand" "=dm")
6209 (fix:QI (match_operand:XF 1 "general_operand" "f")))]
6213 (define_insn "fixxfhi2"
6214 [(set (match_operand:HI 0 "general_operand" "=dm")
6215 (fix:HI (match_operand:XF 1 "general_operand" "f")))]
6219 (define_insn "fixxfsi2"
6220 [(set (match_operand:SI 0 "general_operand" "=dm")
6221 (fix:SI (match_operand:XF 1 "general_operand" "f")))]
6225 (define_expand "addxf3"
6226 [(set (match_operand:XF 0 "general_operand" "")
6227 (plus:XF (match_operand:XF 1 "general_operand" "")
6228 (match_operand:XF 2 "general_operand" "")))]
6232 if (CONSTANT_P (operands[1]))
6233 operands[1] = force_const_mem (XFmode, operands[1]);
6234 if (CONSTANT_P (operands[2]))
6235 operands[2] = force_const_mem (XFmode, operands[2]);
6239 [(set (match_operand:XF 0 "general_operand" "=f")
6240 (plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
6241 (match_operand:XF 2 "nonimmediate_operand" "fmG")))]
6245 if (REG_P (operands[2]))
6246 return \"fadd%.x %2,%0\";
6247 return \"fadd%.x %f2,%0\";
6250 (define_expand "subxf3"
6251 [(set (match_operand:XF 0 "general_operand" "")
6252 (minus:XF (match_operand:XF 1 "general_operand" "")
6253 (match_operand:XF 2 "general_operand" "")))]
6257 if (CONSTANT_P (operands[1]))
6258 operands[1] = force_const_mem (XFmode, operands[1]);
6259 if (CONSTANT_P (operands[2]))
6260 operands[2] = force_const_mem (XFmode, operands[2]);
6264 [(set (match_operand:XF 0 "general_operand" "=f")
6265 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
6266 (match_operand:XF 2 "nonimmediate_operand" "fmG")))]
6270 if (REG_P (operands[2]))
6271 return \"fsub%.x %2,%0\";
6272 return \"fsub%.x %f2,%0\";
6275 (define_expand "mulxf3"
6276 [(set (match_operand:XF 0 "general_operand" "")
6277 (mult:XF (match_operand:XF 1 "general_operand" "")
6278 (match_operand:XF 2 "general_operand" "")))]
6282 if (CONSTANT_P (operands[1]))
6283 operands[1] = force_const_mem (XFmode, operands[1]);
6284 if (CONSTANT_P (operands[2]))
6285 operands[2] = force_const_mem (XFmode, operands[2]);
6289 [(set (match_operand:XF 0 "general_operand" "=f")
6290 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
6291 (match_operand:XF 2 "nonimmediate_operand" "fmG")))]
6295 if (REG_P (operands[2]))
6296 return \"fmul%.x %2,%0\";
6297 return \"fmul%.x %f2,%0\";
6300 (define_expand "divxf3"
6301 [(set (match_operand:XF 0 "general_operand" "")
6302 (div:XF (match_operand:XF 1 "general_operand" "")
6303 (match_operand:XF 2 "general_operand" "")))]
6307 if (CONSTANT_P (operands[1]))
6308 operands[1] = force_const_mem (XFmode, operands[1]);
6309 if (CONSTANT_P (operands[2]))
6310 operands[2] = force_const_mem (XFmode, operands[2]);
6314 [(set (match_operand:XF 0 "general_operand" "=f")
6315 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
6316 (match_operand:XF 2 "nonimmediate_operand" "fmG")))]
6320 if (REG_P (operands[2]))
6321 return \"fdiv%.x %2,%0\";
6322 return \"fdiv%.x %f2,%0\";
6325 (define_expand "negxf2"
6326 [(set (match_operand:XF 0 "general_operand" "")
6327 (neg:XF (match_operand:XF 1 "general_operand" "")))]
6331 /* ??? There isn't an FPA define_insn so we could handle it here too.
6332 For now we don't (paranoia). */
6333 if (!TARGET_FPA && !TARGET_68881)
6340 target = operand_subword (operands[0], 0, 1, XFmode);
6341 result = expand_binop (SImode, xor_optab,
6342 operand_subword_force (operands[1], 0, XFmode),
6343 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
6347 if (result != target)
6348 emit_move_insn (result, target);
6350 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
6351 operand_subword_force (operands[1], 1, XFmode));
6352 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
6353 operand_subword_force (operands[1], 2, XFmode));
6355 insns = get_insns ();
6358 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
6363 (define_insn "negxf2_68881"
6364 [(set (match_operand:XF 0 "general_operand" "=f")
6365 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "fmF")))]
6369 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
6370 return \"fneg%.x %1,%0\";
6371 return \"fneg%.x %f1,%0\";
6374 (define_expand "absxf2"
6375 [(set (match_operand:XF 0 "general_operand" "")
6376 (abs:XF (match_operand:XF 1 "general_operand" "")))]
6380 /* ??? There isn't an FPA define_insn so we could handle it here too.
6381 For now we don't (paranoia). */
6382 if (!TARGET_FPA && !TARGET_68881)
6389 target = operand_subword (operands[0], 0, 1, XFmode);
6390 result = expand_binop (SImode, and_optab,
6391 operand_subword_force (operands[1], 0, XFmode),
6392 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
6396 if (result != target)
6397 emit_move_insn (result, target);
6399 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
6400 operand_subword_force (operands[1], 1, XFmode));
6401 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
6402 operand_subword_force (operands[1], 2, XFmode));
6404 insns = get_insns ();
6407 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
6412 (define_insn "absxf2_68881"
6413 [(set (match_operand:XF 0 "general_operand" "=f")
6414 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "fmF")))]
6418 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
6419 return \"fabs%.x %1,%0\";
6420 return \"fabs%.x %f1,%0\";
6423 (define_insn "sqrtxf2"
6424 [(set (match_operand:XF 0 "general_operand" "=f")
6425 (sqrt:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
6429 return \"fsqrt%.x %1,%0\";
6432 (define_insn "sinsf2"
6433 [(set (match_operand:SF 0 "general_operand" "=f")
6434 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 1))]
6435 "TARGET_68881 && flag_fast_math"
6438 if (FP_REG_P (operands[1]))
6439 return \"fsin%.x %1,%0\";
6441 return \"fsin%.s %1,%0\";
6444 (define_insn "sindf2"
6445 [(set (match_operand:DF 0 "general_operand" "=f")
6446 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 1))]
6447 "TARGET_68881 && flag_fast_math"
6450 if (FP_REG_P (operands[1]))
6451 return \"fsin%.x %1,%0\";
6453 return \"fsin%.d %1,%0\";
6456 (define_insn "sinxf2"
6457 [(set (match_operand:XF 0 "general_operand" "=f")
6458 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 1))]
6459 "TARGET_68881 && flag_fast_math"
6462 return \"fsin%.x %1,%0\";
6465 (define_insn "cossf2"
6466 [(set (match_operand:SF 0 "general_operand" "=f")
6467 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 2))]
6468 "TARGET_68881 && flag_fast_math"
6471 if (FP_REG_P (operands[1]))
6472 return \"fcos%.x %1,%0\";
6474 return \"fcos%.s %1,%0\";
6477 (define_insn "cosdf2"
6478 [(set (match_operand:DF 0 "general_operand" "=f")
6479 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 2))]
6480 "TARGET_68881 && flag_fast_math"
6483 if (FP_REG_P (operands[1]))
6484 return \"fcos%.x %1,%0\";
6486 return \"fcos%.d %1,%0\";
6489 (define_insn "cosxf2"
6490 [(set (match_operand:XF 0 "general_operand" "=f")
6491 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 2))]
6492 "TARGET_68881 && flag_fast_math"
6495 return \"fcos%.x %1,%0\";