1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 88, 93-98, 1999 Free Software Foundation, Inc.
4 ;; This file is part of GNU CC.
6 ;; GNU CC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GNU CC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GNU CC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
19 ;; Boston, MA 02111-1307, USA.
21 ;;- Information about MCF5200 port.
23 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
24 ;;- 68k ISA. Differences include reduced support for byte and word
25 ;;- operands and the removal of BCD, bitfield, rotate, and integer
26 ;;- divide instructions. The TARGET_5200 flag turns the use of the
27 ;;- removed opcodes and addressing modes off.
31 ;;- instruction definitions
33 ;;- @@The original PO technology requires these to be ordered by speed,
34 ;;- @@ so that assigner will pick the fastest.
36 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
38 ;;- When naming insn's (operand 0 of define_insn) be careful about using
39 ;;- names from other targets machine descriptions.
41 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
42 ;;- updates for most instructions.
44 ;;- Operand classes for the register allocator:
45 ;;- 'a' one of the address registers can be used.
46 ;;- 'd' one of the data registers can be used.
47 ;;- 'f' one of the m68881 registers can be used
48 ;;- 'r' either a data or an address register can be used.
49 ;;- 'x' if one of the Sun FPA registers
50 ;;- 'y' if one of the Low Sun FPA registers (fpa0-fpa15).
52 ;;- Immediate Floating point operator constraints
53 ;;- 'G' a floating point constant that is *NOT* one of the standard
54 ;; 68881 constant values (to force calling output_move_const_double
55 ;; to get it from rom if it is a 68881 constant).
56 ;;- 'H' one of the standard FPA constant values
58 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
61 ;;- Immediate integer operand constraints:
63 ;;- 'J' -32768 .. 32767
64 ;;- 'K' all integers EXCEPT -128 .. 127
66 ;;- 'M' all integers EXCEPT -256 .. 255
72 ;;- "%." size separator ("." or "") move%.l d0,d1
73 ;;- "%#" immediate separator ("#" or "") move%.l %#0,d0
74 ;;- "%-" push operand "sp@-" move%.l d0,%-
75 ;;- "%+" pop operand "sp@+" move%.l d0,%+
76 ;;- "%@" top of stack "sp@" move%.l d0,%@
77 ;;- "%!" fpcr register
78 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
79 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
82 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
83 ;; operand 1 is the argument for `sin'.
84 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
85 ;; operand 1 is the argument for `cos'.
87 ;;- Information about 68040 port.
89 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
90 ;;- be emulated in software by the OS. It is faster to avoid these
91 ;;- instructions and issue a library call rather than trapping into
92 ;;- the kernel. The affected instructions are fintrz and fscale. The
93 ;;- TARGET_68040 flag turns the use of the opcodes off.
95 ;;- The '040 also implements a set of new floating-point instructions
96 ;;- which specify the rounding precision in the opcode. This finally
97 ;;- permit the 68k series to be truly IEEE compliant, and solves all
98 ;;- issues of excess precision accumulating in the extended registers.
99 ;;- By default, GCC does not use these instructions, since such code will
100 ;;- not run on an '030. To use these instructions, use the -m68040-only
101 ;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY,
102 ;;- you can make these instructions the default.
104 ;;- These new instructions aren't directly in the md. They are brought
105 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
108 ;;- Information about 68060 port.
110 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
111 ;;- be emulated in software by the OS. It is faster to avoid these
112 ;;- instructions and issue a library call rather than trapping into
113 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
114 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
115 ;;- fscale. The TARGET_68060 flag turns the use of the opcodes off.
117 ;;- FPA port explanation:
119 ;;- Usage of the Sun FPA and the 68881 together
121 ;;- The current port of gcc to the sun fpa disallows use of the m68881
122 ;;- instructions completely if code is targeted for the fpa. This is
123 ;;- for the following reasons:
125 ;;- 1) Expressing the preference hierarchy (ie. use the fpa if you
126 ;;- can, the 68881 otherwise, and data registers only if you are
127 ;;- forced to it) is a bitch with the current constraint scheme,
128 ;;- especially since it would have to work for any combination of
131 ;;- 2) There are no instructions to move between the two types of
132 ;;- registers; the stack must be used as an intermediary.
134 ;;- It could indeed be done; I think the best way would be to have
135 ;;- separate patterns for TARGET_FPA (which implies a 68881),
136 ;;- TARGET_68881, and no floating point co-processor. Use
137 ;;- define_expands for all of the named instruction patterns, and
138 ;;- include code in the FPA instruction to deal with the 68881 with
139 ;;- preferences specifically set to favor the fpa. Some of this has
140 ;;- already been done:
142 ;;- 1) Separation of most of the patterns out into a TARGET_FPA
143 ;;- case and a TARGET_68881 case (the exceptions are the patterns
144 ;;- which would need one define_expand and three define_insn's under
145 ;;- it (with a lot of duplicate code between them) to replace the
146 ;;- current single define_insn. These are mov{[ds]f,[ds]i} and the
147 ;;- first two patterns in the md.
149 ;;- Some would still have to be done:
151 ;;- 1) Add code to the fpa patterns which correspond to 68881
152 ;;- patterns to deal with the 68881 case (including preferences!).
153 ;;- What you might actually do here is combine the fpa and 68881 code
154 ;;- back together into one pattern for those instructions where it's
155 ;;- absolutely necessary and save yourself some duplicate code. I'm
156 ;;- not completely sure as to whether you could get away with doing
157 ;;- this only for the mov* insns, or if you'd have to do it for all
159 ;;- 2) Add code to the mov{[ds]f,[ds]i} instructions to handle
160 ;;- moving between fpa regs and 68881 regs.
162 ;;- Since the fpa is more powerful than the 68881 and also has more
163 ;;- registers, and since I think the resultant md would be medium ugly
164 ;;- (lot's of duplicate code, ugly constraint strings), I elected not
165 ;;- to do this change.
167 ;;- Another reason why someone *might* want to do the change is to
168 ;;- control which register classes are accessed in a slightly cleaner
169 ;;- way than I have. See the blurb on CONDITIONAL_REGISTER_USAGE in
170 ;;- the internals manual.
172 ;;- Yet another reason why someone might want to do this change is to
173 ;;- allow use of some of the 68881 insns which have no equivalent on
174 ;;- the fpa. The sqrt instruction comes fairly quickly to mind.
176 ;;- If this is ever done, don't forget to change sun3.h so that
177 ;;- it *will* define __HAVE_68881__ when the FPA is in use.
179 ;;- Condition code hack
181 ;;- When a floating point compare is done in the fpa, the resulting
182 ;;- condition codes are left in the fpastatus register. The values in
183 ;;- this register must be moved into the 68000 cc register before any
184 ;;- jump is executed. Once this has been done, regular jump
185 ;;- instructions are fine (ie. floating point jumps are not necessary.
186 ;;- They are only done if the cc is in the 68881).
188 ;;- The instructions that move the fpastatus register to the 68000
189 ;;- register clobber a data register (the move cannot be done direct).
190 ;;- These instructions might be bundled either with the compare
191 ;;- instruction, or the branch instruction. If we were using both the
192 ;;- fpa and the 68881 together, we would wish to only mark the
193 ;;- register clobbered if we were doing the compare in the fpa, but I
194 ;;- think that that decision (whether to clobber the register or not)
195 ;;- must be done before register allocation (makes sense) and hence we
196 ;;- can't know if the floating point compare will be done in the fpa
197 ;;- or the fp. So whenever we are asked for code that uses the fpa,
198 ;;- we will mark a data register as clobbered. This is reasonable, as
199 ;;- almost all floating point compare operations done with fpa code
200 ;;- enabled will be done in the fpa. It's even more reasonable since
201 ;;- we decided to make the 68881 and the fpa mutually exclusive.
203 ;;- We place to code to move the fpastatus register inside of a
204 ;;- define_expand so that we can do it conditionally based on whether
205 ;;- we are targeting an fpa or not.
207 ;;- This still leaves us with the question of where we wish to put the
208 ;;- code to move the fpastatus reg. If we put it in the compare
209 ;;- instruction, we can restrict the clobbering of the register to
210 ;;- floating point compares, but we can't take advantage of floating
211 ;;- point subtracts & etc. that alter the fpastatus register. If we
212 ;;- put it in the branch instruction, all branches compiled with fpa
213 ;;- code enabled will clobber a data register, but we will be able to
214 ;;- take advantage of fpa subtracts. This balance favors putting the
215 ;;- code in with the compare instruction.
217 ;;- Note that if some enterprising hacker should decide to switch
218 ;;- this, he'll need to modify the code in NOTICE_UPDATE_CC.
220 ;;- Usage of the top 16 fpa registers
222 ;;- The only locations which we may transfer fpa registers 16-31 from
223 ;;- or to are the fpa registers 0-15. (68000 registers and memory
224 ;;- locations are impossible). This causes problems in gcc, which
225 ;;- assumes that mov?? instructions require no additional registers
226 ;;- (see section 11.7) and since floating point moves *must* be
227 ;;- supported into general registers (see section 12.3 under
228 ;;- HARD_REGNO_OK_FOR_MODE_P) from anywhere.
230 ;;- My solution was to reserve fpa0 for moves into or out of these top
231 ;;- 16 registers and to disparage the choice to reload into or out of
232 ;;- these registers as much as I could. That alternative is always
233 ;;- last in the list, so it will not be used unless all else fails. I
234 ;;- will note that according to my current information, sun's compiler
235 ;;- doesn't use these top 16 registers at all.
237 ;;- There is another possible way to do it. I *believe* that if you
238 ;;- make absolutely sure that the code will not be executed in the
239 ;;- reload pass, you can support the mov?? names with define_expands
240 ;;- which require new registers. This may be possible by the
241 ;;- appropriate juggling of constraints. I may come back to this later.
243 ;;- Usage of constant RAM
245 ;;- This has been handled correctly (I believe) but the way I've done
246 ;;- it could use a little explanation. The constant RAM can only be
247 ;;- accessed when the instruction is in "command register" mode.
248 ;;- "command register" mode means that no accessing of memory or the
249 ;;- 68000 registers is being done. This can be expressed easily in
250 ;;- constraints, so generally the mode of the instruction is
251 ;;- determined by a branch off of which_alternative. In outputting
252 ;;- instructions, a 'w' means to output an access to the constant ram
253 ;;- (if the arg is CONST_DOUBLE and is one of the available
254 ;;- constants), and 'x' means to output a register pair (if the arg is
255 ;;- a 68000 register) and a 'y' is the combination of the above two
256 ;;- processes. You use a 'y' in two operand DF instructions where you
257 ;;- *know* the other operand is an fpa register, you use an 'x' in DF
258 ;;- instructions where the arg might be a 68000 register and the
259 ;;- instruction is *not* in "command register" mode, and you use a 'w'
260 ;;- in two situations: 1) The instruction *is* in command register
261 ;;- mode (and hence won't be accessing 68000 registers), or 2) The
262 ;;- instruction is a two operand SF instruction where you know the
263 ;;- other operand is an fpa register.
265 ;;- Optimization issues
267 ;;- I actually think that I've included all of the fpa instructions
268 ;;- that should be included. Note that if someone is interested in
269 ;;- doing serious floating point work on the sun fpa, I would advise
270 ;;- the use of the "asm" instruction in gcc to allow you to use the
271 ;;- sin, cos, and exponential functions on the fpa board.
273 ;;- END FPA Explanation Section.
276 ;;- Some of these insn's are composites of several m68000 op codes.
277 ;;- The assembler (or final @@??) insures that the appropriate one is
281 [(set (match_operand:DF 0 "push_operand" "=m")
282 (match_operand:DF 1 "general_operand" "ro<>fyE"))]
286 if (FP_REG_P (operands[1]))
287 return \"fmove%.d %f1,%0\";
288 if (FPA_REG_P (operands[1]))
289 return \"fpmove%.d %1, %x0\";
290 return output_move_double (operands);
293 (define_insn "pushdi"
294 [(set (match_operand:DI 0 "push_operand" "=m")
295 (match_operand:DI 1 "general_operand" "ro<>Fyi"))]
299 return output_move_double (operands);
302 ;; We don't want to allow a constant operand for test insns because
303 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
304 ;; be folded while optimizing anyway.
306 (define_expand "tstdi"
307 [(parallel [(set (cc0)
308 (match_operand:DI 0 "nonimmediate_operand" ""))
309 (clobber (match_scratch:SI 1 ""))
310 (clobber (match_scratch:DI 2 ""))])]
312 "m68k_last_compare_had_fp_operands = 0;")
316 (match_operand:DI 0 "nonimmediate_operand" "am,d"))
317 (clobber (match_scratch:SI 1 "=X,d"))
318 (clobber (match_scratch:DI 2 "=d,X"))]
322 if (which_alternative == 0)
326 xoperands[0] = operands[2];
327 xoperands[1] = operands[0];
328 output_move_double (xoperands);
329 cc_status.flags |= CC_REVERSED;
330 return \"neg%.l %R2\;negx%.l %2\";
332 if (find_reg_note (insn, REG_DEAD, operands[0]))
334 cc_status.flags |= CC_REVERSED;
335 return \"neg%.l %R0\;negx%.l %0\";
339 ** 'sub' clears %1, and also clears the X cc bit
340 ** 'tst' sets the Z cc bit according to the low part of the DImode operand
341 ** 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part
343 return \"sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0\";
346 (define_expand "tstsi"
348 (match_operand:SI 0 "nonimmediate_operand" ""))]
350 "m68k_last_compare_had_fp_operands = 0;")
354 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
359 /* ISI's assembler fails to handle tstl a0. */
360 if (! ADDRESS_REG_P (operands[0]))
362 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
364 return \"tst%.l %0\";
365 /* If you think that the 68020 does not support tstl a0,
366 reread page B-167 of the 68020 manual more carefully. */
367 /* On an address reg, cmpw may replace cmpl. */
369 return \"cmp%.w %0,%#0\";
371 return \"cmp%.w %#0,%0\";
375 ;; This can't use an address register, because comparisons
376 ;; with address registers as second operand always test the whole word.
377 (define_expand "tsthi"
379 (match_operand:HI 0 "nonimmediate_operand" ""))]
381 "m68k_last_compare_had_fp_operands = 0;")
385 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
389 (define_expand "tstqi"
391 (match_operand:QI 0 "nonimmediate_operand" ""))]
393 "m68k_last_compare_had_fp_operands = 0;")
397 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
401 (define_expand "tstsf"
403 (match_operand:SF 0 "general_operand" ""))]
404 "TARGET_68881 || TARGET_FPA"
407 m68k_last_compare_had_fp_operands = 1;
410 emit_insn (gen_tstsf_fpa (operands[0]));
415 (define_insn "tstsf_fpa"
417 (match_operand:SF 0 "general_operand" "xmdF"))
418 (clobber (match_scratch:SI 1 "=d"))]
420 "fptst%.s %x0\;fpmove fpastatus,%1\;movw %1,cc")
424 (match_operand:SF 0 "general_operand" "fdm"))]
428 cc_status.flags = CC_IN_68881;
429 if (FP_REG_P (operands[0]))
430 return \"ftst%.x %0\";
431 return \"ftst%.s %0\";
434 (define_expand "tstdf"
436 (match_operand:DF 0 "general_operand" ""))]
437 "TARGET_68881 || TARGET_FPA"
440 m68k_last_compare_had_fp_operands = 1;
443 emit_insn (gen_tstsf_fpa (operands[0]));
448 (define_insn "tstdf_fpa"
450 (match_operand:DF 0 "general_operand" "xrmF"))
451 (clobber (match_scratch:SI 1 "=d"))]
453 "fptst%.d %x0\;fpmove fpastatus,%1\;movw %1,cc")
457 (match_operand:DF 0 "general_operand" "fm"))]
461 cc_status.flags = CC_IN_68881;
462 if (FP_REG_P (operands[0]))
463 return \"ftst%.x %0\";
464 return \"ftst%.d %0\";
467 ;; compare instructions.
469 (define_expand "cmpdi"
472 (compare (match_operand:DI 0 "nonimmediate_operand" "")
473 (match_operand:DI 1 "general_operand" "")))
474 (clobber (match_dup 2))])]
476 "m68k_last_compare_had_fp_operands = 0; operands[2] = gen_reg_rtx (DImode);")
480 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
481 (match_operand:DI 2 "general_operand" "d,0")))
482 (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
486 if (rtx_equal_p (operands[0], operands[1]))
487 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
490 cc_status.flags |= CC_REVERSED;
491 return \"sub%.l %R1,%R0\;subx%.l %1,%0\";
495 ;; This is the second "hook" for PIC code (in addition to movsi). See
496 ;; comment of movsi for a description of PIC handling.
497 (define_expand "cmpsi"
499 (compare (match_operand:SI 0 "nonimmediate_operand" "")
500 (match_operand:SI 1 "general_operand" "")))]
504 m68k_last_compare_had_fp_operands = 0;
505 if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
507 /* The source is an address which requires PIC relocation.
508 Call legitimize_pic_address with the source, mode, and a relocation
509 register (a new pseudo, or the final destination if reload_in_progress
510 is set). Then fall through normally */
511 extern rtx legitimize_pic_address();
512 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
513 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
517 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
520 (compare (match_operand:SI 0 "nonimmediate_operand" "rKT,rKs,mSr,mSa,>")
521 (match_operand:SI 1 "general_src_operand" "mSr,mSa,KTr,Ksr,>")))]
525 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
527 return \"cmpm%.l %0,%1\";
529 return \"cmpm%.l %1,%0\";
531 if (REG_P (operands[1])
532 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
533 { cc_status.flags |= CC_REVERSED;
535 return \"cmp%.l %d1,%d0\";
537 return \"cmp%.l %d0,%d1\";
540 if (ADDRESS_REG_P (operands[0])
541 && GET_CODE (operands[1]) == CONST_INT
542 && INTVAL (operands[1]) < 0x8000
543 && INTVAL (operands[1]) >= -0x8000)
546 return \"cmp%.w %0,%1\";
548 return \"cmp%.w %1,%0\";
552 return \"cmp%.l %d0,%d1\";
554 return \"cmp%.l %d1,%d0\";
560 (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
561 (match_operand:SI 1 "general_operand" "r,mrKs")))]
565 if (REG_P (operands[1])
566 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
567 { cc_status.flags |= CC_REVERSED;
569 return \"cmp%.l %d1,%d0\";
571 return \"cmp%.l %d0,%d1\";
575 return \"cmp%.l %d0,%d1\";
577 return \"cmp%.l %d1,%d0\";
581 (define_expand "cmphi"
583 (compare (match_operand:HI 0 "nonimmediate_src_operand" "")
584 (match_operand:HI 1 "general_src_operand" "")))]
586 "m68k_last_compare_had_fp_operands = 0;")
590 (compare (match_operand:HI 0 "nonimmediate_src_operand" "rnmS,d,n,mS,>")
591 (match_operand:HI 1 "general_src_operand" "d,rnmS,mS,n,>")))]
595 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
597 return \"cmpm%.w %0,%1\";
599 return \"cmpm%.w %1,%0\";
601 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
602 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
603 { cc_status.flags |= CC_REVERSED;
605 return \"cmp%.w %d1,%d0\";
607 return \"cmp%.w %d0,%d1\";
611 return \"cmp%.w %d0,%d1\";
613 return \"cmp%.w %d1,%d0\";
617 (define_expand "cmpqi"
619 (compare (match_operand:QI 0 "nonimmediate_src_operand" "")
620 (match_operand:QI 1 "general_src_operand" "")))]
622 "m68k_last_compare_had_fp_operands = 0;")
626 (compare (match_operand:QI 0 "nonimmediate_src_operand" "dn,dmS,>")
627 (match_operand:QI 1 "general_src_operand" "dmS,nd,>")))]
631 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
633 return \"cmpm%.b %0,%1\";
635 return \"cmpm%.b %1,%0\";
637 if (REG_P (operands[1])
638 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
639 { cc_status.flags |= CC_REVERSED;
641 return \"cmp%.b %d1,%d0\";
643 return \"cmp%.b %d0,%d1\";
647 return \"cmp%.b %d0,%d1\";
649 return \"cmp%.b %d1,%d0\";
653 (define_expand "cmpdf"
655 (compare (match_operand:DF 0 "general_operand" "")
656 (match_operand:DF 1 "general_operand" "")))]
657 "TARGET_68881 || TARGET_FPA"
660 m68k_last_compare_had_fp_operands = 1;
663 emit_insn (gen_cmpdf_fpa (operands[0], operands[1]));
668 (define_insn "cmpdf_fpa"
670 (compare (match_operand:DF 0 "general_operand" "x,y")
671 (match_operand:DF 1 "general_operand" "xH,rmF")))
672 (clobber (match_scratch:SI 2 "=d,d"))]
674 "fpcmp%.d %y1,%0\;fpmove fpastatus,%2\;movw %2,cc")
678 (compare (match_operand:DF 0 "general_operand" "f,mG")
679 (match_operand:DF 1 "general_operand" "fmG,f")))]
683 cc_status.flags = CC_IN_68881;
685 if (REG_P (operands[0]))
687 if (REG_P (operands[1]))
688 return \"fcmp%.x %0,%1\";
690 return \"fcmp%.d %0,%f1\";
692 cc_status.flags |= CC_REVERSED;
693 return \"fcmp%.d %1,%f0\";
695 if (REG_P (operands[0]))
697 if (REG_P (operands[1]))
698 return \"fcmp%.x %1,%0\";
700 return \"fcmp%.d %f1,%0\";
702 cc_status.flags |= CC_REVERSED;
703 return \"fcmp%.d %f0,%1\";
707 (define_expand "cmpsf"
709 (compare (match_operand:SF 0 "general_operand" "")
710 (match_operand:SF 1 "general_operand" "")))]
711 "TARGET_68881 || TARGET_FPA"
714 m68k_last_compare_had_fp_operands = 1;
717 emit_insn (gen_cmpsf_fpa (operands[0], operands[1]));
722 (define_insn "cmpsf_fpa"
724 (compare (match_operand:SF 0 "general_operand" "x,y")
725 (match_operand:SF 1 "general_operand" "xH,rmF")))
726 (clobber (match_scratch:SI 2 "=d,d"))]
728 "fpcmp%.s %w1,%x0\;fpmove fpastatus,%2\;movw %2,cc")
732 (compare (match_operand:SF 0 "general_operand" "f,mdG")
733 (match_operand:SF 1 "general_operand" "fmdG,f")))]
737 cc_status.flags = CC_IN_68881;
739 if (FP_REG_P (operands[0]))
741 if (FP_REG_P (operands[1]))
742 return \"fcmp%.x %0,%1\";
744 return \"fcmp%.s %0,%f1\";
746 cc_status.flags |= CC_REVERSED;
747 return \"fcmp%.s %1,%f0\";
749 if (FP_REG_P (operands[0]))
751 if (FP_REG_P (operands[1]))
752 return \"fcmp%.x %1,%0\";
754 return \"fcmp%.s %f1,%0\";
756 cc_status.flags |= CC_REVERSED;
757 return \"fcmp%.s %f0,%1\";
761 ;; Recognizers for btst instructions.
763 ;; Coldfire/5200 only allows "<Q>" type addresses when the bit position is
764 ;; specified as a constant, so we must disable all patterns that may extract
765 ;; from a MEM at a constant bit position if we can't use this as a constraint.
768 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_src_operand" "oS")
770 (minus:SI (const_int 7)
771 (match_operand:SI 1 "general_operand" "di"))))]
773 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
775 ;; This is the same as the above pattern except for the constraints. The 'i'
779 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
781 (minus:SI (const_int 7)
782 (match_operand:SI 1 "general_operand" "d"))))]
784 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
787 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
789 (minus:SI (const_int 31)
790 (match_operand:SI 1 "general_operand" "di"))))]
792 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
794 ;; The following two patterns are like the previous two
795 ;; except that they use the fact that bit-number operands
796 ;; are automatically masked to 3 or 5 bits.
799 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
801 (minus:SI (const_int 7)
803 (match_operand:SI 1 "register_operand" "d")
806 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
809 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
811 (minus:SI (const_int 31)
813 (match_operand:SI 1 "register_operand" "d")
816 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
818 ;; Nonoffsettable mem refs are ok in this one pattern
819 ;; since we don't try to adjust them.
821 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
823 (match_operand:SI 1 "const_int_operand" "n")))]
824 "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_5200"
827 operands[1] = GEN_INT (7 - INTVAL (operands[1]));
828 return output_btst (operands, operands[1], operands[0], insn, 7);
832 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
834 (match_operand:SI 1 "const_int_operand" "n")))]
838 if (GET_CODE (operands[0]) == MEM)
840 operands[0] = adj_offsettable_operand (operands[0],
841 INTVAL (operands[1]) / 8);
842 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
843 return output_btst (operands, operands[1], operands[0], insn, 7);
845 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
846 return output_btst (operands, operands[1], operands[0], insn, 31);
849 ;; This is the same as the above pattern except for the constraints.
850 ;; The 'o' has been replaced with 'Q'.
853 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ")
855 (match_operand:SI 1 "const_int_operand" "n")))]
859 if (GET_CODE (operands[0]) == MEM)
861 operands[0] = adj_offsettable_operand (operands[0],
862 INTVAL (operands[1]) / 8);
863 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
864 return output_btst (operands, operands[1], operands[0], insn, 7);
866 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
867 return output_btst (operands, operands[1], operands[0], insn, 31);
873 ;; A special case in which it is not desirable
874 ;; to reload the constant into a data register.
875 (define_insn "pushexthisi_const"
876 [(set (match_operand:SI 0 "push_operand" "=m")
877 (match_operand:SI 1 "const_int_operand" "J"))]
878 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
881 if (operands[1] == const0_rtx)
882 return \"clr%.l %0\";
887 ;(define_insn "swapsi"
888 ; [(set (match_operand:SI 0 "general_operand" "+r")
889 ; (match_operand:SI 1 "general_operand" "+r"))
890 ; (set (match_dup 1) (match_dup 0))]
894 ;; Special case of fullword move when source is zero.
895 ;; The reason this is special is to avoid loading a zero
896 ;; into a data reg with moveq in order to store it elsewhere.
898 (define_insn "movsi_const0"
899 [(set (match_operand:SI 0 "general_operand" "=g")
901 ;; clr insns on 68000 read before writing.
902 ;; This isn't so on the 68010, but we have no TARGET_68010.
903 "((TARGET_68020 || TARGET_5200)
904 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
907 if (ADDRESS_REG_P (operands[0]))
909 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
910 if (!TARGET_68040 && !TARGET_68060)
911 return \"sub%.l %0,%0\";
916 /* Many SGS assemblers croak on size specifiers for constants. */
919 return \"lea 0.w,%0\";
922 return \"lea 0:w,%0\";
926 /* moveq is faster on the 68000. */
927 if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_5200))
928 #if defined(MOTOROLA) && !defined(CRDS)
929 return \"moveq%.l %#0,%0\";
931 return \"moveq %#0,%0\";
933 return \"clr%.l %0\";
936 ;; General case of fullword move.
938 ;; This is the main "hook" for PIC code. When generating
939 ;; PIC, movsi is responsible for determining when the source address
940 ;; needs PIC relocation and appropriately calling legitimize_pic_address
941 ;; to perform the actual relocation.
943 ;; In both the PIC and non-PIC cases the patterns generated will
944 ;; matched by the next define_insn.
945 (define_expand "movsi"
946 [(set (match_operand:SI 0 "general_operand" "")
947 (match_operand:SI 1 "general_operand" ""))]
951 if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
953 /* The source is an address which requires PIC relocation.
954 Call legitimize_pic_address with the source, mode, and a relocation
955 register (a new pseudo, or the final destination if reload_in_progress
956 is set). Then fall through normally */
957 extern rtx legitimize_pic_address();
958 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
959 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
961 else if (flag_pic && TARGET_PCREL && ! reload_in_progress)
963 /* Don't allow writes to memory except via a register;
964 the m68k doesn't consider PC-relative addresses to be writable. */
965 if (symbolic_operand (operands[0], SImode))
966 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
967 else if (GET_CODE (operands[0]) == MEM
968 && symbolic_operand (XEXP (operands[0], 0), SImode))
969 operands[0] = gen_rtx (MEM, SImode,
970 force_reg (SImode, XEXP (operands[0], 0)));
974 ;; General case of fullword move. The register constraints
975 ;; force integer constants in range for a moveq to be reloaded
976 ;; if they are headed for memory.
978 ;; Notes: make sure no alternative allows g vs g.
979 ;; We don't allow f-regs since fixed point cannot go in them.
980 ;; We do allow y and x regs since fixed point is allowed in them.
981 [(set (match_operand:SI 0 "general_operand" "=g,d,a<,y,!*x*r*m")
982 (match_operand:SI 1 "general_src_operand" "daymSKT,n,i,g,*x*r*m"))]
987 if (which_alternative == 4)
988 return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\";
989 if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0]))
990 return \"fpmove%.l %x1,%x0\";
991 return output_move_simode (operands);
995 [(set (match_operand:SI 0 "general_operand" "=r<Q>,g")
996 (match_operand:SI 1 "general_operand" "g,r<Q>"))]
998 "* return output_move_simode (operands);")
1000 ;; Special case of fullword move, where we need to get a non-GOT PIC
1001 ;; reference into an address register.
1003 [(set (match_operand:SI 0 "general_operand" "=a<")
1004 (match_operand:SI 1 "pcrel_address" ""))]
1008 if (push_operand (operands[0], SImode))
1010 return \"lea %a1,%0\";
1013 (define_expand "movhi"
1014 [(set (match_operand:HI 0 "general_operand" "")
1015 (match_operand:HI 1 "general_operand" ""))]
1020 [(set (match_operand:HI 0 "general_operand" "=g")
1021 (match_operand:HI 1 "general_src_operand" "gS"))]
1023 "* return output_move_himode (operands);")
1026 [(set (match_operand:HI 0 "general_operand" "=r<Q>,g")
1027 (match_operand:HI 1 "general_operand" "g,r<Q>"))]
1029 "* return output_move_himode (operands);")
1031 (define_expand "movstricthi"
1032 [(set (strict_low_part (match_operand:HI 0 "general_operand" ""))
1033 (match_operand:HI 1 "general_src_operand" ""))]
1038 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
1039 (match_operand:HI 1 "general_src_operand" "rmSn"))]
1041 "* return output_move_stricthi (operands);")
1044 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+d,m"))
1045 (match_operand:HI 1 "general_src_operand" "rmn,r"))]
1047 "* return output_move_stricthi (operands);")
1049 (define_expand "movqi"
1050 [(set (match_operand:QI 0 "general_operand" "")
1051 (match_operand:QI 1 "general_src_operand" ""))]
1056 [(set (match_operand:QI 0 "general_operand" "=d,*a,m")
1057 (match_operand:QI 1 "general_src_operand" "dmSi*a,di*a,dmSi"))]
1059 "* return output_move_qimode (operands);")
1062 [(set (match_operand:QI 0 "general_operand" "=d<Q>,dm,d*a")
1063 (match_operand:QI 1 "general_src_operand" "dmi,d<Q>,di*a"))]
1065 "* return output_move_qimode (operands);")
1067 (define_expand "movstrictqi"
1068 [(set (strict_low_part (match_operand:QI 0 "general_operand" ""))
1069 (match_operand:QI 1 "general_src_operand" ""))]
1074 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
1075 (match_operand:QI 1 "general_src_operand" "dmSn"))]
1077 "* return output_move_strictqi (operands);")
1080 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+d,m"))
1081 (match_operand:QI 1 "general_src_operand" "dmn,d"))]
1083 "* return output_move_strictqi (operands);")
1085 (define_expand "movsf"
1086 [(set (match_operand:SF 0 "general_operand" "")
1087 (match_operand:SF 1 "general_operand" ""))]
1092 [(set (match_operand:SF 0 "general_operand" "=rmf,x,y,rm,!x,!rm")
1093 (match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))]
1094 ; [(set (match_operand:SF 0 "general_operand" "=rmf")
1095 ; (match_operand:SF 1 "general_operand" "rmfF"))]
1099 if (which_alternative >= 4)
1100 return \"fpmove%.s %1,fpa0\;fpmove%.s fpa0,%0\";
1101 if (FPA_REG_P (operands[0]))
1103 if (FPA_REG_P (operands[1]))
1104 return \"fpmove%.s %x1,%x0\";
1105 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1106 return output_move_const_single (operands);
1107 else if (FP_REG_P (operands[1]))
1108 return \"fmove%.s %1,sp@-\;fpmove%.d sp@+, %0\";
1109 return \"fpmove%.s %x1,%x0\";
1111 if (FPA_REG_P (operands[1]))
1113 if (FP_REG_P (operands[0]))
1114 return \"fpmove%.s %x1,sp@-\;fmove%.s sp@+,%0\";
1116 return \"fpmove%.s %x1,%x0\";
1118 if (FP_REG_P (operands[0]))
1120 if (FP_REG_P (operands[1]))
1121 return \"f%$move%.x %1,%0\";
1122 else if (ADDRESS_REG_P (operands[1]))
1123 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
1124 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1125 return output_move_const_single (operands);
1126 return \"f%$move%.s %f1,%0\";
1128 if (FP_REG_P (operands[1]))
1130 if (ADDRESS_REG_P (operands[0]))
1131 return \"fmove%.s %1,%-\;move%.l %+,%0\";
1132 return \"fmove%.s %f1,%0\";
1134 if (operands[1] == CONST0_RTX (SFmode)
1135 /* clr insns on 68000 read before writing.
1136 This isn't so on the 68010, but we have no TARGET_68010. */
1137 && ((TARGET_68020 || TARGET_5200)
1138 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1140 if (ADDRESS_REG_P (operands[0]))
1142 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
1143 if (!TARGET_68040 && !TARGET_68060)
1144 return \"sub%.l %0,%0\";
1149 /* Many SGS assemblers croak on size specifiers for constants. */
1150 return \"lea 0,%0\";
1152 return \"lea 0.w,%0\";
1155 return \"lea 0:w,%0\";
1159 /* moveq is faster on the 68000. */
1160 if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_5200))
1162 #if defined(MOTOROLA) && !defined(CRDS)
1163 return \"moveq%.l %#0,%0\";
1165 return \"moveq %#0,%0\";
1168 return \"clr%.l %0\";
1170 return \"move%.l %1,%0\";
1174 [(set (match_operand:SF 0 "general_operand" "=r,g")
1175 (match_operand:SF 1 "general_operand" "g,r"))]
1177 "* return \"move%.l %1,%0\";")
1179 (define_expand "movdf"
1180 [(set (match_operand:DF 0 "general_operand" "")
1181 (match_operand:DF 1 "general_operand" ""))]
1186 [(set (match_operand:DF 0 "general_operand"
1187 "=*rm,*rf,*rf,&*rof<>,y,*rm,x,!x,!*rm")
1188 (match_operand:DF 1 "general_operand"
1189 "*rf,m,0,*rofE<>,*rmE,y,xH,*rm,x"))]
1190 ; [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>")
1191 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
1195 if (which_alternative == 7)
1196 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1197 if (FPA_REG_P (operands[0]))
1199 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1200 return output_move_const_double (operands);
1201 if (FP_REG_P (operands[1]))
1202 return \"fmove%.d %1,sp@-\;fpmove%.d sp@+,%x0\";
1203 return \"fpmove%.d %x1,%x0\";
1205 else if (FPA_REG_P (operands[1]))
1207 if (FP_REG_P(operands[0]))
1208 return \"fpmove%.d %x1,sp@-\;fmoved sp@+,%0\";
1210 return \"fpmove%.d %x1,%x0\";
1212 if (FP_REG_P (operands[0]))
1214 if (FP_REG_P (operands[1]))
1215 return \"f%&move%.x %1,%0\";
1216 if (REG_P (operands[1]))
1219 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1220 output_asm_insn (\"move%.l %1,%-\", xoperands);
1221 output_asm_insn (\"move%.l %1,%-\", operands);
1222 return \"f%&move%.d %+,%0\";
1224 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1225 return output_move_const_double (operands);
1226 return \"f%&move%.d %f1,%0\";
1228 else if (FP_REG_P (operands[1]))
1230 if (REG_P (operands[0]))
1232 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1233 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1234 return \"move%.l %+,%0\";
1237 return \"fmove%.d %f1,%0\";
1239 return output_move_double (operands);
1243 [(set (match_operand:DF 0 "general_operand" "=r,g")
1244 (match_operand:DF 1 "general_operand" "g,r"))]
1246 "* return output_move_double (operands);")
1248 (define_expand "movxf"
1249 [(set (match_operand:XF 0 "nonimmediate_operand" "")
1250 (match_operand:XF 1 "general_operand" ""))]
1254 if (CONSTANT_P (operands[1]))
1256 operands[1] = force_const_mem (XFmode, operands[1]);
1257 if (! memory_address_p (XFmode, XEXP (operands[1], 0))
1258 && ! reload_in_progress)
1259 operands[1] = change_address (operands[1], XFmode,
1260 XEXP (operands[1], 0));
1262 if (flag_pic && TARGET_PCREL && ! reload_in_progress)
1264 /* Don't allow writes to memory except via a register;
1265 the m68k doesn't consider PC-relative addresses to be writable. */
1266 if (GET_CODE (operands[0]) == MEM
1267 && symbolic_operand (XEXP (operands[0], 0), SImode))
1268 operands[0] = gen_rtx (MEM, XFmode,
1269 force_reg (SImode, XEXP (operands[0], 0)));
1274 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f,!r")
1275 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r,!r"))]
1279 if (FP_REG_P (operands[0]))
1281 if (FP_REG_P (operands[1]))
1282 return \"fmove%.x %1,%0\";
1283 if (REG_P (operands[1]))
1286 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1287 output_asm_insn (\"move%.l %1,%-\", xoperands);
1288 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1289 output_asm_insn (\"move%.l %1,%-\", xoperands);
1290 output_asm_insn (\"move%.l %1,%-\", operands);
1291 return \"fmove%.x %+,%0\";
1293 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1294 return \"fmove%.x %1,%0\";
1295 return \"fmove%.x %f1,%0\";
1297 if (FP_REG_P (operands[1]))
1299 if (REG_P (operands[0]))
1301 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1302 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1303 output_asm_insn (\"move%.l %+,%0\", operands);
1304 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1305 return \"move%.l %+,%0\";
1307 /* Must be memory destination. */
1308 return \"fmove%.x %f1,%0\";
1310 return output_move_double (operands);
1315 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1316 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1317 "! TARGET_68881 && ! TARGET_5200"
1320 if (FP_REG_P (operands[0]))
1322 if (FP_REG_P (operands[1]))
1323 return \"fmove%.x %1,%0\";
1324 if (REG_P (operands[1]))
1327 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1328 output_asm_insn (\"move%.l %1,%-\", xoperands);
1329 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1330 output_asm_insn (\"move%.l %1,%-\", xoperands);
1331 output_asm_insn (\"move%.l %1,%-\", operands);
1332 return \"fmove%.x %+,%0\";
1334 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1335 return \"fmove%.x %1,%0\";
1336 return \"fmove%.x %f1,%0\";
1338 if (FP_REG_P (operands[1]))
1340 if (REG_P (operands[0]))
1342 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1343 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1344 output_asm_insn (\"move%.l %+,%0\", operands);
1345 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1346 return \"move%.l %+,%0\";
1349 return \"fmove%.x %f1,%0\";
1351 return output_move_double (operands);
1356 [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
1357 (match_operand:XF 1 "nonimmediate_operand" "g,r"))]
1358 "! TARGET_68881 && TARGET_5200"
1359 "* return output_move_double (operands);")
1361 (define_expand "movdi"
1362 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1363 [(set (match_operand:DI 0 "general_operand" "")
1364 (match_operand:DI 1 "general_operand" ""))]
1368 ;; movdi can apply to fp regs in some cases
1370 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1371 [(set (match_operand:DI 0 "general_operand" "=rm,r,&ro<>,y,rm,!*x,!rm")
1372 (match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))]
1373 ; [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm")
1374 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))]
1375 ; [(set (match_operand:DI 0 "general_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1376 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1380 if (which_alternative == 8)
1381 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1382 if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
1383 return \"fpmove%.d %x1,%x0\";
1384 if (FP_REG_P (operands[0]))
1386 if (FP_REG_P (operands[1]))
1387 return \"fmove%.x %1,%0\";
1388 if (REG_P (operands[1]))
1391 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1392 output_asm_insn (\"move%.l %1,%-\", xoperands);
1393 output_asm_insn (\"move%.l %1,%-\", operands);
1394 return \"fmove%.d %+,%0\";
1396 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1397 return output_move_const_double (operands);
1398 return \"fmove%.d %f1,%0\";
1400 else if (FP_REG_P (operands[1]))
1402 if (REG_P (operands[0]))
1404 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1405 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1406 return \"move%.l %+,%0\";
1409 return \"fmove%.d %f1,%0\";
1411 return output_move_double (operands);
1415 [(set (match_operand:DI 0 "general_operand" "=r,g")
1416 (match_operand:DI 1 "general_operand" "g,r"))]
1418 "* return output_move_double (operands);")
1420 ;; Thus goes after the move instructions
1421 ;; because the move instructions are better (require no spilling)
1422 ;; when they can apply. It goes before the add/sub insns
1423 ;; so we will prefer it to them.
1425 (define_insn "pushasi"
1426 [(set (match_operand:SI 0 "push_operand" "=m")
1427 (match_operand:SI 1 "address_operand" "p"))]
1431 ;; truncation instructions
1432 (define_insn "truncsiqi2"
1433 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1435 (match_operand:SI 1 "general_src_operand" "doJS,i")))]
1439 if (GET_CODE (operands[0]) == REG)
1441 /* Must clear condition codes, since the move.l bases them on
1442 the entire 32 bits, not just the desired 8 bits. */
1444 return \"move%.l %1,%0\";
1446 if (GET_CODE (operands[1]) == MEM)
1447 operands[1] = adj_offsettable_operand (operands[1], 3);
1448 return \"move%.b %1,%0\";
1451 (define_insn "trunchiqi2"
1452 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1454 (match_operand:HI 1 "general_src_operand" "doJS,i")))]
1458 if (GET_CODE (operands[0]) == REG
1459 && (GET_CODE (operands[1]) == MEM
1460 || GET_CODE (operands[1]) == CONST_INT))
1462 /* Must clear condition codes, since the move.w bases them on
1463 the entire 16 bits, not just the desired 8 bits. */
1465 return \"move%.w %1,%0\";
1467 if (GET_CODE (operands[0]) == REG)
1469 /* Must clear condition codes, since the move.l bases them on
1470 the entire 32 bits, not just the desired 8 bits. */
1472 return \"move%.l %1,%0\";
1474 if (GET_CODE (operands[1]) == MEM)
1475 operands[1] = adj_offsettable_operand (operands[1], 1);
1476 return \"move%.b %1,%0\";
1479 (define_insn "truncsihi2"
1480 [(set (match_operand:HI 0 "general_operand" "=dm,d")
1482 (match_operand:SI 1 "general_src_operand" "roJS,i")))]
1486 if (GET_CODE (operands[0]) == REG)
1488 /* Must clear condition codes, since the move.l bases them on
1489 the entire 32 bits, not just the desired 8 bits. */
1491 return \"move%.l %1,%0\";
1493 if (GET_CODE (operands[1]) == MEM)
1494 operands[1] = adj_offsettable_operand (operands[1], 2);
1495 return \"move%.w %1,%0\";
1498 ;; zero extension instructions
1500 (define_insn "zero_extendqidi2"
1501 [(set (match_operand:DI 0 "general_operand" "=&d")
1502 (zero_extend:DI (match_operand:QI 1 "general_operand" "dm")))]
1507 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1508 return \"moveq %#0,%0\;moveq %#0,%2\;move%.b %1,%2\";
1511 (define_insn "zero_extendhidi2"
1512 [(set (match_operand:DI 0 "general_operand" "=&d")
1513 (zero_extend:DI (match_operand:HI 1 "general_operand" "rm")))]
1518 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1519 return \"moveq %#0,%0\;moveq %#0,%2\;move%.w %1,%2\";
1522 ;; this is the canonical form for (lshiftrt:DI x 32)
1523 (define_insn "zero_extendsidi2"
1524 [(set (match_operand:DI 0 "general_operand" "rm")
1525 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
1530 if (GET_CODE (operands[0]) == REG)
1531 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1532 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1533 return \"move%.l %1,%0\;clr%.l %0\";
1534 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1535 return \"clr%.l %0\;move%.l %1,%0\";
1537 operands[2] = adj_offsettable_operand (operands[0], 4);
1538 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[2]) != REG
1539 || REGNO (operands[1]) != REGNO (operands[2]))
1540 output_asm_insn (\"move%.l %1,%2\", operands);
1541 if (ADDRESS_REG_P (operands[0]))
1542 return \"sub%.l %0,%0\";
1544 return \"clr%.l %0\";
1547 (define_expand "zero_extendhisi2"
1548 [(set (match_operand:SI 0 "register_operand" "")
1550 (set (strict_low_part (match_dup 2))
1551 (match_operand:HI 1 "general_operand" ""))]
1555 operands[1] = make_safe_from (operands[1], operands[0]);
1556 if (GET_CODE (operands[0]) == SUBREG)
1557 operands[2] = gen_rtx_SUBREG (HImode, SUBREG_REG (operands[0]),
1558 SUBREG_WORD (operands[0]));
1560 operands[2] = gen_rtx_SUBREG (HImode, operands[0], 0);
1563 (define_expand "zero_extendqihi2"
1564 [(set (match_operand:HI 0 "register_operand" "")
1566 (set (strict_low_part (match_dup 2))
1567 (match_operand:QI 1 "general_operand" ""))]
1571 operands[1] = make_safe_from (operands[1], operands[0]);
1572 if (GET_CODE (operands[0]) == SUBREG)
1573 operands[2] = gen_rtx_SUBREG (QImode, SUBREG_REG (operands[0]),
1574 SUBREG_WORD (operands[0]));
1576 operands[2] = gen_rtx_SUBREG (QImode, operands[0], 0);
1579 (define_expand "zero_extendqisi2"
1580 [(set (match_operand:SI 0 "register_operand" "")
1582 (set (strict_low_part (match_dup 2))
1583 (match_operand:QI 1 "general_operand" ""))]
1587 operands[1] = make_safe_from (operands[1], operands[0]);
1588 if (GET_CODE (operands[0]) == SUBREG)
1589 operands[2] = gen_rtx_SUBREG (QImode, SUBREG_REG (operands[0]),
1590 SUBREG_WORD (operands[0]));
1592 operands[2] = gen_rtx_SUBREG (QImode, operands[0], 0);
1595 ;; Patterns to recognize zero-extend insns produced by the combiner.
1596 ;; We don't allow both operands in memory, because of aliasing problems.
1597 ;; Explicitly disallow two memory operands via the condition since reloading
1598 ;; of this case will result in worse code than the uncombined patterns.
1601 [(set (match_operand:SI 0 "general_operand" "=do<>,d<")
1602 (zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "r,mS")))]
1603 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1606 if (DATA_REG_P (operands[0]))
1608 if (GET_CODE (operands[1]) == REG
1609 && REGNO (operands[0]) == REGNO (operands[1]))
1610 return \"and%.l %#0xFFFF,%0\";
1611 if (reg_mentioned_p (operands[0], operands[1]))
1612 return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\";
1613 return \"clr%.l %0\;move%.w %1,%0\";
1615 else if (GET_CODE (operands[0]) == MEM
1616 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1617 return \"move%.w %1,%0\;clr%.w %0\";
1618 else if (GET_CODE (operands[0]) == MEM
1619 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1620 return \"clr%.w %0\;move%.w %1,%0\";
1623 output_asm_insn (\"clr%.w %0\", operands);
1624 operands[0] = adj_offsettable_operand (operands[0], 2);
1625 return \"move%.w %1,%0\";
1630 [(set (match_operand:HI 0 "general_operand" "=do<>,d")
1631 (zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "d,mS")))]
1632 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1635 if (DATA_REG_P (operands[0]))
1637 if (GET_CODE (operands[1]) == REG
1638 && REGNO (operands[0]) == REGNO (operands[1]))
1639 return (!TARGET_5200 ? \"and%.w %#0xFF,%0\" : \"and%.l %#0xFF,%0\");
1640 if (reg_mentioned_p (operands[0], operands[1]))
1641 return (!TARGET_5200 ? \"move%.b %1,%0\;and%.w %#0xFF,%0\"
1642 : \"move%.b %1,%0\;and%.l %#0xFF,%0\");
1643 return \"clr%.w %0\;move%.b %1,%0\";
1645 else if (GET_CODE (operands[0]) == MEM
1646 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1648 if (REGNO (XEXP (XEXP (operands[0], 0), 0))
1649 == STACK_POINTER_REGNUM)
1651 output_asm_insn (\"clr%.w %-\", operands);
1652 operands[0] = gen_rtx_MEM (GET_MODE (operands[0]),
1653 plus_constant (stack_pointer_rtx, 1));
1654 return \"move%.b %1,%0\";
1657 return \"move%.b %1,%0\;clr%.b %0\";
1659 else if (GET_CODE (operands[0]) == MEM
1660 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1661 return \"clr%.b %0\;move%.b %1,%0\";
1664 output_asm_insn (\"clr%.b %0\", operands);
1665 operands[0] = adj_offsettable_operand (operands[0], 1);
1666 return \"move%.b %1,%0\";
1671 [(set (match_operand:SI 0 "general_operand" "=do<>,d")
1672 (zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "d,mS")))]
1673 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1676 if (DATA_REG_P (operands[0]))
1678 if (GET_CODE (operands[1]) == REG
1679 && REGNO (operands[0]) == REGNO (operands[1]))
1680 return \"and%.l %#0xFF,%0\";
1681 if (reg_mentioned_p (operands[0], operands[1]))
1682 return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
1683 return \"clr%.l %0\;move%.b %1,%0\";
1685 else if (GET_CODE (operands[0]) == MEM
1686 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1688 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1691 return \"clr%.l -(%0)\;move%.b %1,3(%0)\";
1693 return \"clr%.l -(%0)\;move%.b %1,(3,%0)\";
1696 return \"clrl %0@-\;moveb %1,%0@(3)\";
1699 else if (GET_CODE (operands[0]) == MEM
1700 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1702 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1705 return \"clr%.l (%0)+\;move%.b %1,-1(%0)\";
1707 return \"clr%.l (%0)+\;move%.b %1,(-1,%0)\";
1710 return \"clrl %0@+\;moveb %1,%0@(-1)\";
1715 output_asm_insn (\"clr%.l %0\", operands);
1716 operands[0] = adj_offsettable_operand (operands[0], 3);
1717 return \"move%.b %1,%0\";
1721 ;; sign extension instructions
1723 (define_insn "extendqidi2"
1724 [(set (match_operand:DI 0 "general_operand" "=d")
1725 (sign_extend:DI (match_operand:QI 1 "general_src_operand" "rmS")))]
1730 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1731 if (TARGET_68020 || TARGET_5200)
1732 return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
1734 return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
1737 (define_insn "extendhidi2"
1738 [(set (match_operand:DI 0 "general_operand" "=d")
1740 (match_operand:HI 1 "general_src_operand" "rmS")))]
1745 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1746 if (TARGET_68020 || TARGET_5200)
1747 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
1749 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
1752 (define_insn "extendsidi2"
1753 [(set (match_operand:DI 0 "general_operand" "=d")
1755 (match_operand:SI 1 "general_operand" "rm")))]
1760 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1761 if (TARGET_68020 || TARGET_5200)
1762 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
1764 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
1767 ;; Special case when one can avoid register clobbering, copy and test
1768 ;; Maybe there is a way to make that the general case, by forcing the
1769 ;; result of the SI tree to be in the lower register of the DI target
1771 (define_insn "extendplussidi"
1772 [(set (match_operand:DI 0 "register_operand" "=d")
1773 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1774 (match_operand:SI 2 "general_operand" "rmn"))))]
1779 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1780 if (GET_CODE (operands[1]) == CONST_INT
1781 && (unsigned) INTVAL (operands[1]) > 8)
1783 rtx tmp = operands[1];
1785 operands[1] = operands[2];
1788 if (GET_CODE (operands[1]) == REG
1789 && REGNO (operands[1]) == REGNO (operands[3]))
1790 output_asm_insn (\"add%.l %2,%3\", operands);
1792 output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands);
1793 if (TARGET_68020 || TARGET_5200)
1794 return \"smi %0\;extb%.l %0\";
1796 return \"smi %0\;ext%.w %0\;ext%.l %0\";
1799 (define_insn "extendhisi2"
1800 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1802 (match_operand:HI 1 "nonimmediate_src_operand" "0,rmS")))]
1806 if (ADDRESS_REG_P (operands[0]))
1807 return \"move%.w %1,%0\";
1808 return \"ext%.l %0\";
1811 (define_insn "extendqihi2"
1812 [(set (match_operand:HI 0 "general_operand" "=d")
1813 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1817 (define_insn "extendqisi2"
1818 [(set (match_operand:SI 0 "general_operand" "=d")
1819 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1820 "TARGET_68020 || TARGET_5200"
1823 ;; Conversions between float and double.
1825 (define_expand "extendsfdf2"
1826 [(set (match_operand:DF 0 "general_operand" "")
1828 (match_operand:SF 1 "general_operand" "")))]
1829 "TARGET_68881 || TARGET_FPA"
1833 [(set (match_operand:DF 0 "general_operand" "=x,y")
1835 (match_operand:SF 1 "general_operand" "xH,rmF")))]
1840 [(set (match_operand:DF 0 "general_operand" "=*fdm,f")
1842 (match_operand:SF 1 "general_operand" "f,dmF")))]
1846 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1848 if (REGNO (operands[0]) == REGNO (operands[1]))
1850 /* Extending float to double in an fp-reg is a no-op.
1851 NOTICE_UPDATE_CC has already assumed that the
1852 cc will be set. So cancel what it did. */
1853 cc_status = cc_prev_status;
1856 return \"f%&move%.x %1,%0\";
1858 if (FP_REG_P (operands[0]))
1859 return \"f%&move%.s %f1,%0\";
1860 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1862 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1863 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1864 return \"move%.l %+,%0\";
1866 return \"fmove%.d %f1,%0\";
1869 ;; This cannot output into an f-reg because there is no way to be
1870 ;; sure of truncating in that case.
1871 ;; But on the Sun FPA, we can be sure.
1872 (define_expand "truncdfsf2"
1873 [(set (match_operand:SF 0 "general_operand" "")
1875 (match_operand:DF 1 "general_operand" "")))]
1876 "TARGET_68881 || TARGET_FPA"
1880 [(set (match_operand:SF 0 "general_operand" "=x,y")
1882 (match_operand:DF 1 "general_operand" "xH,rmF")))]
1886 ;; On the '040 we can truncate in a register accurately and easily.
1888 [(set (match_operand:SF 0 "general_operand" "=f")
1890 (match_operand:DF 1 "general_operand" "fmG")))]
1894 if (FP_REG_P (operands[1]))
1895 return \"f%$move%.x %1,%0\";
1896 return \"f%$move%.d %f1,%0\";
1900 [(set (match_operand:SF 0 "general_operand" "=dm")
1902 (match_operand:DF 1 "general_operand" "f")))]
1906 ;; Conversion between fixed point and floating point.
1907 ;; Note that among the fix-to-float insns
1908 ;; the ones that start with SImode come first.
1909 ;; That is so that an operand that is a CONST_INT
1910 ;; (and therefore lacks a specific machine mode).
1911 ;; will be recognized as SImode (which is always valid)
1912 ;; rather than as QImode or HImode.
1914 (define_expand "floatsisf2"
1915 [(set (match_operand:SF 0 "general_operand" "")
1916 (float:SF (match_operand:SI 1 "general_operand" "")))]
1917 "TARGET_68881 || TARGET_FPA"
1921 [(set (match_operand:SF 0 "general_operand" "=y,x")
1922 (float:SF (match_operand:SI 1 "general_operand" "rmi,x")))]
1927 [(set (match_operand:SF 0 "general_operand" "=f")
1928 (float:SF (match_operand:SI 1 "general_operand" "dmi")))]
1932 (define_expand "floatsidf2"
1933 [(set (match_operand:DF 0 "general_operand" "")
1934 (float:DF (match_operand:SI 1 "general_operand" "")))]
1935 "TARGET_68881 || TARGET_FPA"
1939 [(set (match_operand:DF 0 "general_operand" "=y,x")
1940 (float:DF (match_operand:SI 1 "general_operand" "rmi,x")))]
1945 [(set (match_operand:DF 0 "general_operand" "=f")
1946 (float:DF (match_operand:SI 1 "general_operand" "dmi")))]
1950 (define_insn "floathisf2"
1951 [(set (match_operand:SF 0 "general_operand" "=f")
1952 (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
1956 (define_insn "floathidf2"
1957 [(set (match_operand:DF 0 "general_operand" "=f")
1958 (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
1962 (define_insn "floatqisf2"
1963 [(set (match_operand:SF 0 "general_operand" "=f")
1964 (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
1968 (define_insn "floatqidf2"
1969 [(set (match_operand:DF 0 "general_operand" "=f")
1970 (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
1974 ;; New routines to convert floating-point values to integers
1975 ;; to be used on the '040. These should be faster than trapping
1976 ;; into the kernel to emulate fintrz. They should also be faster
1977 ;; than calling the subroutines fixsfsi or fixdfsi.
1979 (define_insn "fix_truncdfsi2"
1980 [(set (match_operand:SI 0 "general_operand" "=dm")
1981 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1982 (clobber (match_scratch:SI 2 "=d"))
1983 (clobber (match_scratch:SI 3 "=d"))]
1984 "TARGET_68881 && TARGET_68040"
1988 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\";
1991 (define_insn "fix_truncdfhi2"
1992 [(set (match_operand:HI 0 "general_operand" "=dm")
1993 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1994 (clobber (match_scratch:SI 2 "=d"))
1995 (clobber (match_scratch:SI 3 "=d"))]
1996 "TARGET_68881 && TARGET_68040"
2000 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\";
2003 (define_insn "fix_truncdfqi2"
2004 [(set (match_operand:QI 0 "general_operand" "=dm")
2005 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
2006 (clobber (match_scratch:SI 2 "=d"))
2007 (clobber (match_scratch:SI 3 "=d"))]
2008 "TARGET_68881 && TARGET_68040"
2012 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\";
2015 ;; Convert a float to a float whose value is an integer.
2016 ;; This is the first stage of converting it to an integer type.
2018 (define_insn "ftruncdf2"
2019 [(set (match_operand:DF 0 "general_operand" "=f")
2020 (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
2021 "TARGET_68881 && !TARGET_68040"
2024 if (FP_REG_P (operands[1]))
2025 return \"fintrz%.x %f1,%0\";
2026 return \"fintrz%.d %f1,%0\";
2029 (define_insn "ftruncsf2"
2030 [(set (match_operand:SF 0 "general_operand" "=f")
2031 (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
2032 "TARGET_68881 && !TARGET_68040"
2035 if (FP_REG_P (operands[1]))
2036 return \"fintrz%.x %f1,%0\";
2037 return \"fintrz%.s %f1,%0\";
2040 ;; Convert a float whose value is an integer
2041 ;; to an actual integer. Second stage of converting float to integer type.
2042 (define_insn "fixsfqi2"
2043 [(set (match_operand:QI 0 "general_operand" "=dm")
2044 (fix:QI (match_operand:SF 1 "general_operand" "f")))]
2048 (define_insn "fixsfhi2"
2049 [(set (match_operand:HI 0 "general_operand" "=dm")
2050 (fix:HI (match_operand:SF 1 "general_operand" "f")))]
2054 (define_insn "fixsfsi2"
2055 [(set (match_operand:SI 0 "general_operand" "=dm")
2056 (fix:SI (match_operand:SF 1 "general_operand" "f")))]
2060 (define_insn "fixdfqi2"
2061 [(set (match_operand:QI 0 "general_operand" "=dm")
2062 (fix:QI (match_operand:DF 1 "general_operand" "f")))]
2066 (define_insn "fixdfhi2"
2067 [(set (match_operand:HI 0 "general_operand" "=dm")
2068 (fix:HI (match_operand:DF 1 "general_operand" "f")))]
2072 (define_insn "fixdfsi2"
2073 [(set (match_operand:SI 0 "general_operand" "=dm")
2074 (fix:SI (match_operand:DF 1 "general_operand" "f")))]
2078 ;; Convert a float to an integer.
2079 ;; On the Sun FPA, this is done in one step.
2082 [(set (match_operand:SI 0 "general_operand" "=x,y")
2083 (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "xH,rmF"))))]
2088 [(set (match_operand:SI 0 "general_operand" "=x,y")
2089 (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "xH,rmF"))))]
2095 (define_insn "adddi_lshrdi_63"
2096 [(set (match_operand:DI 0 "general_operand" "=d")
2097 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
2100 (clobber (match_scratch:SI 2 "=d"))]
2104 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2105 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
2107 \"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0\";
2108 if (GET_CODE (operands[1]) == REG)
2109 operands[4] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2110 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
2111 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2112 operands[4] = operands[1];
2114 operands[4] = adj_offsettable_operand (operands[1], 4);
2115 if (GET_CODE (operands[1]) == MEM
2116 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2117 output_asm_insn (\"move%.l %4,%3\", operands);
2118 output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
2119 if (TARGET_68020 || TARGET_5200)
2120 output_asm_insn (\"extb%.l %2\", operands);
2122 output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
2123 if (GET_CODE (operands[1]) != MEM
2124 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
2125 output_asm_insn (\"move%.l %4,%3\", operands);
2126 return \"sub%.l %2,%3\;subx%.l %2,%0\";
2129 (define_insn "adddi_sexthishl32"
2130 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2131 (plus:DI (ashift:DI (sign_extend:DI
2132 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
2134 (match_operand:DI 2 "general_operand" "0,0,0,0")))
2135 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2140 if (ADDRESS_REG_P (operands[0]))
2141 return \"add%.w %1,%0\";
2142 else if (ADDRESS_REG_P (operands[3]))
2143 return \"move%.w %1,%3\;add%.l %3,%0\";
2145 return \"move%.w %1,%3\;ext%.l %3\;add%.l %3,%0\";
2148 (define_insn "adddi_dilshr32"
2149 [(set (match_operand:DI 0 "general_operand" "=d,o")
2150 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2151 ;; (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
2152 ;; (const_int 32))))]
2153 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,r")
2155 (match_operand:DI 2 "general_operand" "0,0")))]
2160 if (GET_CODE (operands[0]) == REG)
2161 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2163 operands[2] = adj_offsettable_operand (operands[0], 4);
2164 return \"add%.l %1,%2\;negx%.l %0\;neg%.l %0\";
2167 (define_insn "adddi_dishl32"
2168 [(set (match_operand:DI 0 "general_operand" "=r,o")
2169 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2170 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2171 ;; (const_int 32))))]
2172 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro,r")
2174 (match_operand:DI 2 "general_operand" "0,0")))]
2179 if (GET_CODE (operands[1]) == REG)
2180 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2182 operands[1] = adj_offsettable_operand (operands[1], 4);
2183 return \"add%.l %1,%0\";
2186 (define_insn "adddi3"
2187 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2188 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0,0")
2189 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2190 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2194 if (DATA_REG_P (operands[0]))
2196 if (DATA_REG_P (operands[2]))
2197 return \"add%.l %R2,%R0\;addx%.l %2,%0\";
2198 else if (GET_CODE (operands[2]) == MEM
2199 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2201 return \"move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0\";
2206 if (GET_CODE (operands[2]) == REG)
2207 operands[1] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2208 else if (GET_CODE (operands[2]) == CONST_DOUBLE)
2210 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
2211 operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
2213 else if (GET_CODE (operands[2]) == CONST_INT)
2215 operands[1] = operands[2];
2216 operands[2] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx;
2219 operands[1] = adj_offsettable_operand (operands[2], 4);
2220 xoperands[0] = operands[3];
2221 if (GET_CODE (operands[1]) == CONST_INT
2222 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2223 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2225 xoperands[1] = operands[2];
2226 output_asm_insn (output_move_simode (xoperands), xoperands);
2227 if (GET_CODE (operands[1]) == CONST_INT)
2229 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2232 return \"add%.l %1,%R0\;addx%.l %3,%0\";
2234 return \"addq%.l %1,%R0\;addx%.l %3,%0\";
2237 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2239 operands[1] = GEN_INT (-INTVAL (operands[1]));
2241 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2243 return \"subq%.l %1,%R0\;subx%.l %3,%0\";
2247 return \"add%.l %1,%R0\;addx%.l %3,%0\";
2250 else if (GET_CODE (operands[0]) == MEM)
2252 if (GET_CODE (operands[2]) == MEM
2253 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2254 return \"add%.l %2,%0\;addx%.l %2,%0\";
2256 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2259 = gen_rtx_MEM (SImode,
2260 gen_rtx_PLUS (VOIDmode, XEXP(operands[0], 0),
2262 return \"move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1\";
2264 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2266 operands[1] = XEXP(operands[0], 0);
2267 return \"add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
2271 operands[1] = adj_offsettable_operand (operands[0], 4);
2272 return \"add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
2279 (define_insn "addsi_lshrsi_31"
2280 [(set (match_operand:SI 0 "general_operand" "=dm")
2281 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
2287 operands[2] = operands[0];
2288 operands[3] = gen_label_rtx();
2289 if (GET_CODE (operands[0]) == MEM)
2291 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2292 operands[0] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2293 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2294 operands[2] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2296 output_asm_insn (\"move%.l %1,%0\", operands);
2298 output_asm_insn (\"jbpl %l3\", operands);
2300 output_asm_insn (\"jpl %l3\", operands);
2303 output_asm_insn (\"addq%.l %#1,%2\", operands);
2305 output_asm_insn (\"add%.l %#1,%2\", operands);
2307 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
2308 CODE_LABEL_NUMBER (operands[3]));
2312 (define_expand "addsi3"
2313 [(set (match_operand:SI 0 "general_operand" "")
2314 (plus:SI (match_operand:SI 1 "general_operand" "")
2315 (match_operand:SI 2 "general_src_operand" "")))]
2319 ;; Note that the middle two alternatives are near-duplicates
2320 ;; in order to handle insns generated by reload.
2321 ;; This is needed since they are not themselves reloaded,
2322 ;; so commutativity won't apply to them.
2323 (define_insn "*addsi3_internal"
2324 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,d,a")
2325 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0,0")
2326 (match_operand:SI 2 "general_src_operand" "dIKLT,rJK,a,mSrIKLT,mSrIKLs")))]
2330 "* return output_addsi3 (operands);")
2332 (define_insn "*addsi3_5200"
2333 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
2334 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2335 (match_operand:SI 2 "general_src_operand" "d,rJK,a,mrIKLs")))]
2337 "* return output_addsi3 (operands);")
2340 [(set (match_operand:SI 0 "general_operand" "=a")
2341 (plus:SI (match_operand:SI 1 "general_operand" "0")
2343 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2347 (define_insn "addhi3"
2348 [(set (match_operand:HI 0 "general_operand" "=m,r")
2349 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2350 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2354 if (GET_CODE (operands[2]) == CONST_INT)
2357 /* If the constant would be a negative number when interpreted as
2358 HImode, make it negative. This is usually, but not always, done
2359 elsewhere in the compiler. First check for constants out of range,
2360 which could confuse us. */
2362 if (INTVAL (operands[2]) >= 32768)
2363 operands[2] = GEN_INT (INTVAL (operands[2]) - 65536);
2365 if (INTVAL (operands[2]) > 0
2366 && INTVAL (operands[2]) <= 8)
2367 return \"addq%.w %2,%0\";
2368 if (INTVAL (operands[2]) < 0
2369 && INTVAL (operands[2]) >= -8)
2371 operands[2] = GEN_INT (-INTVAL (operands[2]));
2372 return \"subq%.w %2,%0\";
2374 /* On the CPU32 it is faster to use two addqw instructions to
2375 add a small integer (8 < N <= 16) to a register.
2376 Likewise for subqw. */
2377 if (TARGET_CPU32 && REG_P (operands[0]))
2379 if (INTVAL (operands[2]) > 8
2380 && INTVAL (operands[2]) <= 16)
2382 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
2383 return \"addq%.w %#8,%0\;addq%.w %2,%0\";
2385 if (INTVAL (operands[2]) < -8
2386 && INTVAL (operands[2]) >= -16)
2388 operands[2] = GEN_INT (-INTVAL (operands[2]) - 8);
2389 return \"subq%.w %#8,%0\;subq%.w %2,%0\";
2393 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2395 return \"lea (%c2,%0),%0\";
2397 return \"lea %0@(%c2),%0\";
2400 return \"add%.w %2,%0\";
2403 ;; These insns must use MATCH_DUP instead of the more expected
2404 ;; use of a matching constraint because the "output" here is also
2405 ;; an input, so you can't use the matching constraint. That also means
2406 ;; that you can't use the "%", so you need patterns with the matched
2407 ;; operand in both positions.
2410 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2411 (plus:HI (match_dup 0)
2412 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2416 if (GET_CODE (operands[1]) == CONST_INT)
2419 /* If the constant would be a negative number when interpreted as
2420 HImode, make it negative. This is usually, but not always, done
2421 elsewhere in the compiler. First check for constants out of range,
2422 which could confuse us. */
2424 if (INTVAL (operands[1]) >= 32768)
2425 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2427 if (INTVAL (operands[1]) > 0
2428 && INTVAL (operands[1]) <= 8)
2429 return \"addq%.w %1,%0\";
2430 if (INTVAL (operands[1]) < 0
2431 && INTVAL (operands[1]) >= -8)
2433 operands[1] = GEN_INT (-INTVAL (operands[1]));
2434 return \"subq%.w %1,%0\";
2436 /* On the CPU32 it is faster to use two addqw instructions to
2437 add a small integer (8 < N <= 16) to a register.
2438 Likewise for subqw. */
2439 if (TARGET_CPU32 && REG_P (operands[0]))
2441 if (INTVAL (operands[1]) > 8
2442 && INTVAL (operands[1]) <= 16)
2444 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2445 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2447 if (INTVAL (operands[1]) < -8
2448 && INTVAL (operands[1]) >= -16)
2450 operands[1] = GEN_INT (-INTVAL (operands[1]) - 8);
2451 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2455 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2457 return \"lea (%c1,%0),%0\";
2459 return \"lea %0@(%c1),%0\";
2462 return \"add%.w %1,%0\";
2466 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2467 (plus:HI (match_operand:HI 1 "general_src_operand" "dn,rmSn")
2472 if (GET_CODE (operands[1]) == CONST_INT)
2475 /* If the constant would be a negative number when interpreted as
2476 HImode, make it negative. This is usually, but not always, done
2477 elsewhere in the compiler. First check for constants out of range,
2478 which could confuse us. */
2480 if (INTVAL (operands[1]) >= 32768)
2481 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2483 if (INTVAL (operands[1]) > 0
2484 && INTVAL (operands[1]) <= 8)
2485 return \"addq%.w %1,%0\";
2486 if (INTVAL (operands[1]) < 0
2487 && INTVAL (operands[1]) >= -8)
2489 operands[1] = GEN_INT (-INTVAL (operands[1]));
2490 return \"subq%.w %1,%0\";
2492 /* On the CPU32 it is faster to use two addqw instructions to
2493 add a small integer (8 < N <= 16) to a register.
2494 Likewise for subqw. */
2495 if (TARGET_CPU32 && REG_P (operands[0]))
2497 if (INTVAL (operands[1]) > 8
2498 && INTVAL (operands[1]) <= 16)
2500 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2501 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2503 if (INTVAL (operands[1]) < -8
2504 && INTVAL (operands[1]) >= -16)
2506 operands[1] = GEN_INT (-INTVAL (operands[1]) - 8);
2507 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2511 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2513 return \"lea (%c1,%0),%0\";
2515 return \"lea %0@(%c1),%0\";
2518 return \"add%.w %1,%0\";
2521 (define_insn "addqi3"
2522 [(set (match_operand:QI 0 "general_operand" "=m,d")
2523 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2524 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2529 if (GET_CODE (operands[2]) == CONST_INT)
2531 if (INTVAL (operands[2]) >= 128)
2532 operands[2] = GEN_INT (INTVAL (operands[2]) - 256);
2534 if (INTVAL (operands[2]) > 0
2535 && INTVAL (operands[2]) <= 8)
2536 return \"addq%.b %2,%0\";
2537 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2539 operands[2] = GEN_INT (-INTVAL (operands[2]));
2540 return \"subq%.b %2,%0\";
2544 return \"add%.b %2,%0\";
2548 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2549 (plus:QI (match_dup 0)
2550 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2555 if (GET_CODE (operands[1]) == CONST_INT)
2557 if (INTVAL (operands[1]) >= 128)
2558 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2560 if (INTVAL (operands[1]) > 0
2561 && INTVAL (operands[1]) <= 8)
2562 return \"addq%.b %1,%0\";
2563 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2565 operands[1] = GEN_INT (-INTVAL (operands[1]));
2566 return \"subq%.b %1,%0\";
2570 return \"add%.b %1,%0\";
2574 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2575 (plus:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
2581 if (GET_CODE (operands[1]) == CONST_INT)
2583 if (INTVAL (operands[1]) >= 128)
2584 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2586 if (INTVAL (operands[1]) > 0
2587 && INTVAL (operands[1]) <= 8)
2588 return \"addq%.b %1,%0\";
2589 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2591 operands[1] = GEN_INT (-INTVAL (operands[1]));
2592 return \"subq%.b %1,%0\";
2596 return \"add%.b %1,%0\";
2599 (define_expand "adddf3"
2600 [(set (match_operand:DF 0 "general_operand" "")
2601 (plus:DF (match_operand:DF 1 "general_operand" "")
2602 (match_operand:DF 2 "general_operand" "")))]
2603 "TARGET_68881 || TARGET_FPA"
2607 [(set (match_operand:DF 0 "general_operand" "=x,y")
2608 (plus:DF (match_operand:DF 1 "general_operand" "%xH,y")
2609 (match_operand:DF 2 "general_operand" "xH,dmF")))]
2613 if (rtx_equal_p (operands[0], operands[1]))
2614 return \"fpadd%.d %y2,%0\";
2615 if (rtx_equal_p (operands[0], operands[2]))
2616 return \"fpadd%.d %y1,%0\";
2617 if (which_alternative == 0)
2618 return \"fpadd3%.d %w2,%w1,%0\";
2619 return \"fpadd3%.d %x2,%x1,%0\";
2623 [(set (match_operand:DF 0 "general_operand" "=f")
2624 (plus:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2625 (match_operand:DF 1 "general_operand" "0")))]
2630 [(set (match_operand:DF 0 "general_operand" "=f")
2631 (plus:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2632 (match_operand:DF 1 "general_operand" "0")))]
2637 [(set (match_operand:DF 0 "general_operand" "=f")
2638 (plus:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2639 (match_operand:DF 1 "general_operand" "0")))]
2644 [(set (match_operand:DF 0 "general_operand" "=f")
2645 (plus:DF (match_operand:DF 1 "general_operand" "%0")
2646 (match_operand:DF 2 "general_operand" "fmG")))]
2650 if (REG_P (operands[2]))
2651 return \"f%&add%.x %2,%0\";
2652 return \"f%&add%.d %f2,%0\";
2655 (define_expand "addsf3"
2656 [(set (match_operand:SF 0 "general_operand" "")
2657 (plus:SF (match_operand:SF 1 "general_operand" "")
2658 (match_operand:SF 2 "general_operand" "")))]
2659 "TARGET_68881 || TARGET_FPA"
2663 [(set (match_operand:SF 0 "general_operand" "=x,y")
2664 (plus:SF (match_operand:SF 1 "general_operand" "%xH,y")
2665 (match_operand:SF 2 "general_operand" "xH,rmF")))]
2669 if (rtx_equal_p (operands[0], operands[1]))
2670 return \"fpadd%.s %w2,%0\";
2671 if (rtx_equal_p (operands[0], operands[2]))
2672 return \"fpadd%.s %w1,%0\";
2673 if (which_alternative == 0)
2674 return \"fpadd3%.s %w2,%w1,%0\";
2675 return \"fpadd3%.s %2,%1,%0\";
2679 [(set (match_operand:SF 0 "general_operand" "=f")
2680 (plus:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2681 (match_operand:SF 1 "general_operand" "0")))]
2686 [(set (match_operand:SF 0 "general_operand" "=f")
2687 (plus:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
2688 (match_operand:SF 1 "general_operand" "0")))]
2693 [(set (match_operand:SF 0 "general_operand" "=f")
2694 (plus:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
2695 (match_operand:SF 1 "general_operand" "0")))]
2700 [(set (match_operand:SF 0 "general_operand" "=f")
2701 (plus:SF (match_operand:SF 1 "general_operand" "%0")
2702 (match_operand:SF 2 "general_operand" "fdmF")))]
2706 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2707 return \"f%$add%.x %2,%0\";
2708 return \"f%$add%.s %f2,%0\";
2711 ;; subtract instructions
2713 (define_insn "subdi_sexthishl32"
2714 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2715 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2716 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2718 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2723 if (ADDRESS_REG_P (operands[0]))
2724 return \"sub%.w %2,%0\";
2725 else if (ADDRESS_REG_P (operands[3]))
2726 return \"move%.w %2,%3\;sub%.l %3,%0\";
2728 return \"move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0\";
2731 (define_insn "subdi_dishl32"
2732 [(set (match_operand:DI 0 "general_operand" "+ro")
2733 (minus:DI (match_dup 0)
2734 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2740 if (GET_CODE (operands[1]) == REG)
2741 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2743 operands[1] = adj_offsettable_operand (operands[1], 4);
2744 return \"sub%.l %1,%0\";
2747 (define_insn "subdi3"
2748 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2749 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0,0")
2750 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2751 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2755 if (DATA_REG_P (operands[0]))
2757 if (DATA_REG_P (operands[2]))
2758 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
2759 else if (GET_CODE (operands[2]) == MEM
2760 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2762 return \"move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0\";
2767 if (GET_CODE (operands[2]) == REG)
2768 operands[1] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2769 else if (GET_CODE (operands[2]) == CONST_DOUBLE)
2771 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
2772 operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
2774 else if (GET_CODE (operands[2]) == CONST_INT)
2776 operands[1] = operands[2];
2777 operands[2] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx;
2780 operands[1] = adj_offsettable_operand (operands[2], 4);
2781 xoperands[0] = operands[3];
2782 if (GET_CODE (operands[1]) == CONST_INT
2783 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2784 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2786 xoperands[1] = operands[2];
2787 output_asm_insn (output_move_simode (xoperands), xoperands);
2788 if (GET_CODE (operands[1]) == CONST_INT)
2790 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2793 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2795 return \"subq%.l %1,%R0\;subx%.l %3,%0\";
2798 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2800 operands[1] = GEN_INT (-INTVAL (operands[1]));
2802 return \"add%.l %1,%R0\;addx%.l %3,%0\";
2804 return \"addq%.l %1,%R0\;addx%.l %3,%0\";
2808 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2811 else if (GET_CODE (operands[0]) == MEM)
2813 if (GET_CODE (operands[2]) == MEM
2814 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2815 return \"sub%.l %2,%0\;subx%.l %2,%0\";
2817 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2820 = gen_rtx_MEM (SImode,
2821 gen_rtx_PLUS (VOIDmode, XEXP(operands[0], 0),
2823 return \"move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1\";
2825 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2827 operands[1] = XEXP(operands[0], 0);
2828 return \"sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
2832 operands[1] = adj_offsettable_operand (operands[0], 4);
2833 return \"sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
2840 (define_insn "subsi3"
2841 [(set (match_operand:SI 0 "general_operand" "=m,d,a")
2842 (minus:SI (match_operand:SI 1 "general_operand" "0,0,0")
2843 (match_operand:SI 2 "general_src_operand" "dT,mSrT,mSrs")))]
2848 [(set (match_operand:SI 0 "general_operand" "=a")
2849 (minus:SI (match_operand:SI 1 "general_operand" "0")
2851 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2855 (define_insn "subhi3"
2856 [(set (match_operand:HI 0 "general_operand" "=m,r")
2857 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2858 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2863 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2864 (minus:HI (match_dup 0)
2865 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2869 (define_insn "subqi3"
2870 [(set (match_operand:QI 0 "general_operand" "=m,d")
2871 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2872 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2877 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2878 (minus:QI (match_dup 0)
2879 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2883 (define_expand "subdf3"
2884 [(set (match_operand:DF 0 "general_operand" "")
2885 (minus:DF (match_operand:DF 1 "general_operand" "")
2886 (match_operand:DF 2 "general_operand" "")))]
2887 "TARGET_68881 || TARGET_FPA"
2891 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
2892 (minus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF")
2893 (match_operand:DF 2 "general_operand" "xH,dmF,0")))]
2897 if (rtx_equal_p (operands[0], operands[2]))
2898 return \"fprsub%.d %y1,%0\";
2899 if (rtx_equal_p (operands[0], operands[1]))
2900 return \"fpsub%.d %y2,%0\";
2901 if (which_alternative == 0)
2902 return \"fpsub3%.d %w2,%w1,%0\";
2903 return \"fpsub3%.d %x2,%x1,%0\";
2907 [(set (match_operand:DF 0 "general_operand" "=f")
2908 (minus:DF (match_operand:DF 1 "general_operand" "0")
2909 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
2914 [(set (match_operand:DF 0 "general_operand" "=f")
2915 (minus:DF (match_operand:DF 1 "general_operand" "0")
2916 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
2921 [(set (match_operand:DF 0 "general_operand" "=f")
2922 (minus:DF (match_operand:DF 1 "general_operand" "0")
2923 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
2928 [(set (match_operand:DF 0 "general_operand" "=f")
2929 (minus:DF (match_operand:DF 1 "general_operand" "0")
2930 (match_operand:DF 2 "general_operand" "fmG")))]
2934 if (REG_P (operands[2]))
2935 return \"f%&sub%.x %2,%0\";
2936 return \"f%&sub%.d %f2,%0\";
2939 (define_expand "subsf3"
2940 [(set (match_operand:SF 0 "general_operand" "")
2941 (minus:SF (match_operand:SF 1 "general_operand" "")
2942 (match_operand:SF 2 "general_operand" "")))]
2943 "TARGET_68881 || TARGET_FPA"
2947 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
2948 (minus:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
2949 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
2953 if (rtx_equal_p (operands[0], operands[2]))
2954 return \"fprsub%.s %w1,%0\";
2955 if (rtx_equal_p (operands[0], operands[1]))
2956 return \"fpsub%.s %w2,%0\";
2957 if (which_alternative == 0)
2958 return \"fpsub3%.s %w2,%w1,%0\";
2959 return \"fpsub3%.s %2,%1,%0\";
2963 [(set (match_operand:SF 0 "general_operand" "=f")
2964 (minus:SF (match_operand:SF 1 "general_operand" "0")
2965 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
2970 [(set (match_operand:SF 0 "general_operand" "=f")
2971 (minus:SF (match_operand:SF 1 "general_operand" "0")
2972 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
2977 [(set (match_operand:SF 0 "general_operand" "=f")
2978 (minus:SF (match_operand:SF 1 "general_operand" "0")
2979 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
2984 [(set (match_operand:SF 0 "general_operand" "=f")
2985 (minus:SF (match_operand:SF 1 "general_operand" "0")
2986 (match_operand:SF 2 "general_operand" "fdmF")))]
2990 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2991 return \"f%$sub%.x %2,%0\";
2992 return \"f%$sub%.s %f2,%0\";
2995 ;; multiply instructions
2997 (define_insn "mulhi3"
2998 [(set (match_operand:HI 0 "general_operand" "=d")
2999 (mult:HI (match_operand:HI 1 "general_operand" "%0")
3000 (match_operand:HI 2 "general_src_operand" "dmSn")))]
3004 #if defined(MOTOROLA) && !defined(CRDS)
3005 return \"muls%.w %2,%0\";
3007 return \"muls %2,%0\";
3011 (define_insn "mulhisi3"
3012 [(set (match_operand:SI 0 "general_operand" "=d")
3013 (mult:SI (sign_extend:SI
3014 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3016 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
3020 #if defined(MOTOROLA) && !defined(CRDS)
3021 return \"muls%.w %2,%0\";
3023 return \"muls %2,%0\";
3028 [(set (match_operand:SI 0 "general_operand" "=d")
3029 (mult:SI (sign_extend:SI
3030 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3031 (match_operand:SI 2 "const_int_operand" "n")))]
3032 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
3035 #if defined(MOTOROLA) && !defined(CRDS)
3036 return \"muls%.w %2,%0\";
3038 return \"muls %2,%0\";
3042 (define_expand "mulsi3"
3043 [(set (match_operand:SI 0 "general_operand" "")
3044 (mult:SI (match_operand:SI 1 "general_operand" "")
3045 (match_operand:SI 2 "general_operand" "")))]
3046 "TARGET_68020 || TARGET_5200"
3050 [(set (match_operand:SI 0 "general_operand" "=d")
3051 (mult:SI (match_operand:SI 1 "general_operand" "%0")
3052 (match_operand:SI 2 "general_src_operand" "dmSTK")))]
3058 [(set (match_operand:SI 0 "general_operand" "=d")
3059 (mult:SI (match_operand:SI 1 "general_operand" "%0")
3060 (match_operand:SI 2 "general_operand" "d<Q>")))]
3064 (define_insn "umulhisi3"
3065 [(set (match_operand:SI 0 "general_operand" "=d")
3066 (mult:SI (zero_extend:SI
3067 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3069 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
3073 #if defined(MOTOROLA) && !defined(CRDS)
3074 return \"mulu%.w %2,%0\";
3076 return \"mulu %2,%0\";
3081 [(set (match_operand:SI 0 "general_operand" "=d")
3082 (mult:SI (zero_extend:SI
3083 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3084 (match_operand:SI 2 "const_int_operand" "n")))]
3085 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
3088 #if defined(MOTOROLA) && !defined(CRDS)
3089 return \"mulu%.w %2,%0\";
3091 return \"mulu %2,%0\";
3095 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
3096 ;; proper matching constraint. This is because the matching is between
3097 ;; the high-numbered word of the DImode operand[0] and operand[1].
3098 (define_expand "umulsidi3"
3100 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
3101 (mult:SI (match_operand:SI 1 "register_operand" "")
3102 (match_operand:SI 2 "nonimmediate_operand" "")))
3103 (set (subreg:SI (match_dup 0) 0)
3104 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3105 (zero_extend:DI (match_dup 2)))
3106 (const_int 32))))])]
3107 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3111 [(set (match_operand:SI 0 "register_operand" "=d")
3112 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3113 (match_operand:SI 2 "nonimmediate_operand" "dm")))
3114 (set (match_operand:SI 3 "register_operand" "=d")
3115 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3116 (zero_extend:DI (match_dup 2)))
3118 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3121 ; Match immediate case. For 2.4 only match things < 2^31.
3122 ; It's tricky with larger values in these patterns since we need to match
3123 ; values between the two parallel multiplies, between a CONST_DOUBLE and
3126 [(set (match_operand:SI 0 "register_operand" "=d")
3127 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3128 (match_operand:SI 2 "const_int_operand" "n")))
3129 (set (match_operand:SI 3 "register_operand" "=d")
3130 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3133 "TARGET_68020 && !TARGET_68060 && !TARGET_5200
3134 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
3137 (define_expand "mulsidi3"
3139 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
3140 (mult:SI (match_operand:SI 1 "register_operand" "")
3141 (match_operand:SI 2 "nonimmediate_operand" "")))
3142 (set (subreg:SI (match_dup 0) 0)
3143 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3144 (sign_extend:DI (match_dup 2)))
3145 (const_int 32))))])]
3146 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3150 [(set (match_operand:SI 0 "register_operand" "=d")
3151 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3152 (match_operand:SI 2 "nonimmediate_operand" "dm")))
3153 (set (match_operand:SI 3 "register_operand" "=d")
3154 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3155 (sign_extend:DI (match_dup 2)))
3157 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3161 [(set (match_operand:SI 0 "register_operand" "=d")
3162 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3163 (match_operand:SI 2 "const_sint32_operand" "")))
3164 (set (match_operand:SI 3 "register_operand" "=d")
3165 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3168 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3171 (define_expand "umulsi3_highpart"
3173 [(set (match_operand:SI 0 "register_operand" "")
3176 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
3177 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
3179 (clobber (match_dup 3))])]
3180 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3183 operands[3] = gen_reg_rtx (SImode);
3184 if (GET_CODE (operands[2]) == CONST_INT
3185 || GET_CODE (operands[2]) == CONST_DOUBLE)
3187 if (! const_uint32_operand (operands[2], VOIDmode))
3189 /* We have to adjust the operand order for the matching constraints. */
3190 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
3191 operands[1], operands[2]));
3197 [(set (match_operand:SI 0 "register_operand" "=d")
3200 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3201 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3203 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3204 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3207 (define_insn "const_umulsi3_highpart"
3208 [(set (match_operand:SI 0 "register_operand" "=d")
3211 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
3212 (match_operand 3 "const_uint32_operand" ""))
3214 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3215 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3218 (define_expand "smulsi3_highpart"
3220 [(set (match_operand:SI 0 "register_operand" "")
3223 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
3224 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
3226 (clobber (match_dup 3))])]
3227 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3230 operands[3] = gen_reg_rtx (SImode);
3231 if (GET_CODE (operands[2]) == CONST_INT
3232 || GET_CODE (operands[2]) == CONST_DOUBLE)
3234 if (! const_sint32_operand (operands[2], VOIDmode))
3236 /* We have to adjust the operand order for the matching constraints. */
3237 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
3238 operands[1], operands[2]));
3244 [(set (match_operand:SI 0 "register_operand" "=d")
3247 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3248 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3250 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3251 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3254 (define_insn "const_smulsi3_highpart"
3255 [(set (match_operand:SI 0 "register_operand" "=d")
3258 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
3259 (match_operand 3 "const_sint32_operand" ""))
3261 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3262 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3265 (define_expand "muldf3"
3266 [(set (match_operand:DF 0 "general_operand" "")
3267 (mult:DF (match_operand:DF 1 "general_operand" "")
3268 (match_operand:DF 2 "general_operand" "")))]
3269 "TARGET_68881 || TARGET_FPA"
3273 [(set (match_operand:DF 0 "general_operand" "=x,y")
3274 (mult:DF (match_operand:DF 1 "general_operand" "%xH,y")
3275 (match_operand:DF 2 "general_operand" "xH,rmF")))]
3279 if (rtx_equal_p (operands[1], operands[2]))
3280 return \"fpsqr%.d %y1,%0\";
3281 if (rtx_equal_p (operands[0], operands[1]))
3282 return \"fpmul%.d %y2,%0\";
3283 if (rtx_equal_p (operands[0], operands[2]))
3284 return \"fpmul%.d %y1,%0\";
3285 if (which_alternative == 0)
3286 return \"fpmul3%.d %w2,%w1,%0\";
3287 return \"fpmul3%.d %x2,%x1,%0\";
3291 [(set (match_operand:DF 0 "general_operand" "=f")
3292 (mult:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
3293 (match_operand:DF 1 "general_operand" "0")))]
3298 [(set (match_operand:DF 0 "general_operand" "=f")
3299 (mult:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
3300 (match_operand:DF 1 "general_operand" "0")))]
3305 [(set (match_operand:DF 0 "general_operand" "=f")
3306 (mult:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
3307 (match_operand:DF 1 "general_operand" "0")))]
3312 [(set (match_operand:DF 0 "general_operand" "=f")
3313 (mult:DF (match_operand:DF 1 "general_operand" "%0")
3314 (match_operand:DF 2 "general_operand" "fmG")))]
3318 if (GET_CODE (operands[2]) == CONST_DOUBLE
3319 && floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
3321 int i = floating_exact_log2 (operands[2]);
3322 operands[2] = GEN_INT (i);
3323 return \"fscale%.l %2,%0\";
3325 if (REG_P (operands[2]))
3326 return \"f%&mul%.x %2,%0\";
3327 return \"f%&mul%.d %f2,%0\";
3330 (define_expand "mulsf3"
3331 [(set (match_operand:SF 0 "general_operand" "")
3332 (mult:SF (match_operand:SF 1 "general_operand" "")
3333 (match_operand:SF 2 "general_operand" "")))]
3334 "TARGET_68881 || TARGET_FPA"
3338 [(set (match_operand:SF 0 "general_operand" "=x,y")
3339 (mult:SF (match_operand:SF 1 "general_operand" "%xH,y")
3340 (match_operand:SF 2 "general_operand" "xH,rmF")))]
3344 if (rtx_equal_p (operands[1], operands[2]))
3345 return \"fpsqr%.s %w1,%0\";
3346 if (rtx_equal_p (operands[0], operands[1]))
3347 return \"fpmul%.s %w2,%0\";
3348 if (rtx_equal_p (operands[0], operands[2]))
3349 return \"fpmul%.s %w1,%0\";
3350 if (which_alternative == 0)
3351 return \"fpmul3%.s %w2,%w1,%0\";
3352 return \"fpmul3%.s %2,%1,%0\";
3356 [(set (match_operand:SF 0 "general_operand" "=f")
3357 (mult:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
3358 (match_operand:SF 1 "general_operand" "0")))]
3362 return (TARGET_68040_ONLY
3363 ? \"fsmul%.l %2,%0\"
3364 : \"fsglmul%.l %2,%0\");
3368 [(set (match_operand:SF 0 "general_operand" "=f")
3369 (mult:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
3370 (match_operand:SF 1 "general_operand" "0")))]
3374 return (TARGET_68040_ONLY
3375 ? \"fsmul%.w %2,%0\"
3376 : \"fsglmul%.w %2,%0\");
3380 [(set (match_operand:SF 0 "general_operand" "=f")
3381 (mult:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
3382 (match_operand:SF 1 "general_operand" "0")))]
3386 return (TARGET_68040_ONLY
3387 ? \"fsmul%.b %2,%0\"
3388 : \"fsglmul%.b %2,%0\");
3392 [(set (match_operand:SF 0 "general_operand" "=f")
3393 (mult:SF (match_operand:SF 1 "general_operand" "%0")
3394 (match_operand:SF 2 "general_operand" "fdmF")))]
3398 #ifdef FSGLMUL_USE_S
3399 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3400 return (TARGET_68040_ONLY
3401 ? \"fsmul%.s %2,%0\"
3402 : \"fsglmul%.s %2,%0\");
3404 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3405 return (TARGET_68040_ONLY
3406 ? \"fsmul%.x %2,%0\"
3407 : \"fsglmul%.x %2,%0\");
3409 return (TARGET_68040_ONLY
3410 ? \"fsmul%.s %f2,%0\"
3411 : \"fsglmul%.s %f2,%0\");
3414 ;; divide instructions
3416 (define_expand "divdf3"
3417 [(set (match_operand:DF 0 "general_operand" "")
3418 (div:DF (match_operand:DF 1 "general_operand" "")
3419 (match_operand:DF 2 "general_operand" "")))]
3420 "TARGET_68881 || TARGET_FPA"
3424 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
3425 (div:DF (match_operand:DF 1 "general_operand" "xH,y,rmF")
3426 (match_operand:DF 2 "general_operand" "xH,rmF,0")))]
3430 if (rtx_equal_p (operands[0], operands[2]))
3431 return \"fprdiv%.d %y1,%0\";
3432 if (rtx_equal_p (operands[0], operands[1]))
3433 return \"fpdiv%.d %y2,%0\";
3434 if (which_alternative == 0)
3435 return \"fpdiv3%.d %w2,%w1,%0\";
3436 return \"fpdiv3%.d %x2,%x1,%x0\";
3440 [(set (match_operand:DF 0 "general_operand" "=f")
3441 (div:DF (match_operand:DF 1 "general_operand" "0")
3442 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
3447 [(set (match_operand:DF 0 "general_operand" "=f")
3448 (div:DF (match_operand:DF 1 "general_operand" "0")
3449 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
3454 [(set (match_operand:DF 0 "general_operand" "=f")
3455 (div:DF (match_operand:DF 1 "general_operand" "0")
3456 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
3461 [(set (match_operand:DF 0 "general_operand" "=f")
3462 (div:DF (match_operand:DF 1 "general_operand" "0")
3463 (match_operand:DF 2 "general_operand" "fmG")))]
3467 if (REG_P (operands[2]))
3468 return \"f%&div%.x %2,%0\";
3469 return \"f%&div%.d %f2,%0\";
3472 (define_expand "divsf3"
3473 [(set (match_operand:SF 0 "general_operand" "")
3474 (div:SF (match_operand:SF 1 "general_operand" "")
3475 (match_operand:SF 2 "general_operand" "")))]
3476 "TARGET_68881 || TARGET_FPA"
3480 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
3481 (div:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
3482 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
3486 if (rtx_equal_p (operands[0], operands[1]))
3487 return \"fpdiv%.s %w2,%0\";
3488 if (rtx_equal_p (operands[0], operands[2]))
3489 return \"fprdiv%.s %w1,%0\";
3490 if (which_alternative == 0)
3491 return \"fpdiv3%.s %w2,%w1,%0\";
3492 return \"fpdiv3%.s %2,%1,%0\";
3496 [(set (match_operand:SF 0 "general_operand" "=f")
3497 (div:SF (match_operand:SF 1 "general_operand" "0")
3498 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
3502 return (TARGET_68040_ONLY
3503 ? \"fsdiv%.l %2,%0\"
3504 : \"fsgldiv%.l %2,%0\");
3508 [(set (match_operand:SF 0 "general_operand" "=f")
3509 (div:SF (match_operand:SF 1 "general_operand" "0")
3510 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
3514 return (TARGET_68040_ONLY
3515 ? \"fsdiv%.w %2,%0\"
3516 : \"fsgldiv%.w %2,%0\");
3520 [(set (match_operand:SF 0 "general_operand" "=f")
3521 (div:SF (match_operand:SF 1 "general_operand" "0")
3522 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
3526 return (TARGET_68040_ONLY
3527 ? \"fsdiv%.b %2,%0\"
3528 : \"fsgldiv%.b %2,%0\");
3532 [(set (match_operand:SF 0 "general_operand" "=f")
3533 (div:SF (match_operand:SF 1 "general_operand" "0")
3534 (match_operand:SF 2 "general_operand" "fdmF")))]
3538 #ifdef FSGLDIV_USE_S
3539 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3540 return (TARGET_68040_ONLY
3541 ? \"fsdiv%.s %2,%0\"
3542 : \"fsgldiv%.s %2,%0\");
3544 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3545 return (TARGET_68040_ONLY
3546 ? \"fsdiv%.x %2,%0\"
3547 : \"fsgldiv%.x %2,%0\");
3549 return (TARGET_68040_ONLY
3550 ? \"fsdiv%.s %f2,%0\"
3551 : \"fsgldiv%.s %f2,%0\");
3554 ;; Remainder instructions.
3556 (define_insn "divmodsi4"
3557 [(set (match_operand:SI 0 "general_operand" "=d")
3558 (div:SI (match_operand:SI 1 "general_operand" "0")
3559 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3560 (set (match_operand:SI 3 "general_operand" "=d")
3561 (mod:SI (match_dup 1) (match_dup 2)))]
3562 "TARGET_68020 && !TARGET_5200"
3565 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3566 return \"divs%.l %2,%0\";
3568 return \"divsl%.l %2,%3:%0\";
3571 (define_insn "udivmodsi4"
3572 [(set (match_operand:SI 0 "general_operand" "=d")
3573 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3574 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3575 (set (match_operand:SI 3 "general_operand" "=d")
3576 (umod:SI (match_dup 1) (match_dup 2)))]
3577 "TARGET_68020 && !TARGET_5200"
3580 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3581 return \"divu%.l %2,%0\";
3583 return \"divul%.l %2,%3:%0\";
3586 (define_insn "divmodhi4"
3587 [(set (match_operand:HI 0 "general_operand" "=d")
3588 (div:HI (match_operand:HI 1 "general_operand" "0")
3589 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3590 (set (match_operand:HI 3 "general_operand" "=d")
3591 (mod:HI (match_dup 1) (match_dup 2)))]
3596 output_asm_insn (\"ext%.l %0\;divs%.w %2,%0\", operands);
3598 output_asm_insn (\"extl %0\;divs %2,%0\", operands);
3600 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3603 return \"move%.l %0,%3\;swap %3\";
3609 (define_insn "udivmodhi4"
3610 [(set (match_operand:HI 0 "general_operand" "=d")
3611 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3612 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3613 (set (match_operand:HI 3 "general_operand" "=d")
3614 (umod:HI (match_dup 1) (match_dup 2)))]
3619 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu%.w %2,%0\", operands);
3621 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu %2,%0\", operands);
3623 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3626 return \"move%.l %0,%3\;swap %3\";
3632 ;; logical-and instructions
3634 ;; "anddi3" is mainly here to help combine().
3635 (define_insn "anddi3"
3636 [(set (match_operand:DI 0 "general_operand" "=o,d")
3637 (and:DI (match_operand:DI 1 "general_operand" "%0,0")
3638 (match_operand:DI 2 "general_operand" "dn,don")))]
3643 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3644 if (GET_CODE (operands[2]) == CONST_DOUBLE
3645 || GET_CODE (operands[2]) == CONST_INT)
3649 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3651 hi = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
3652 lo = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3657 hi = INTVAL (lo) < 0 ? constm1_rtx : const0_rtx;
3659 switch (INTVAL (hi))
3662 output_asm_insn (\"clr%.l %0\", operands);
3670 xoperands[0] = operands[0];
3672 output_asm_insn (output_andsi3 (xoperands), xoperands);
3675 if (GET_CODE (operands[0]) == REG)
3676 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3678 operands[0] = adj_offsettable_operand (operands[0], 4);
3679 switch (INTVAL (lo))
3682 output_asm_insn (\"clr%.l %0\", operands);
3690 xoperands[0] = operands[0];
3692 output_asm_insn (output_andsi3 (xoperands), xoperands);
3697 if (GET_CODE (operands[0]) != REG)
3699 operands[1] = adj_offsettable_operand (operands[0], 4);
3700 return \"and%.l %2,%0\;and%.l %R2,%1\";
3702 if (GET_CODE (operands[2]) != REG)
3704 operands[1] = adj_offsettable_operand (operands[2], 4);
3705 return \"and%.l %2,%0\;and%.l %1,%R0\";
3707 return \"and%.l %2,%0\;and%.l %R2,%R0\";
3710 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3711 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3712 ;; can't allocate pseudos into it.
3714 (define_expand "andsi3"
3715 [(set (match_operand:SI 0 "not_sp_operand" "")
3716 (and:SI (match_operand:SI 1 "general_operand" "")
3717 (match_operand:SI 2 "general_src_operand" "")))]
3721 (define_insn "andsi3_internal"
3722 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3723 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3724 (match_operand:SI 2 "general_src_operand" "dKT,dmSM")))]
3728 return output_andsi3 (operands);
3731 (define_insn "andsi3_5200"
3732 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3733 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3734 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3738 (define_insn "andhi3"
3739 [(set (match_operand:HI 0 "general_operand" "=m,d")
3740 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3741 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3746 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3747 (and:HI (match_dup 0)
3748 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3753 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3754 (and:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3759 (define_insn "andqi3"
3760 [(set (match_operand:QI 0 "general_operand" "=m,d")
3761 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3762 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3767 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3768 (and:QI (match_dup 0)
3769 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3774 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3775 (and:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3780 ;; inclusive-or instructions
3782 (define_insn "iordi_zext"
3783 [(set (match_operand:DI 0 "general_operand" "=o,d")
3784 (ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn"))
3785 (match_operand:DI 2 "general_operand" "0,0")))]
3792 if (GET_CODE (operands[0]) == REG)
3793 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3795 operands[0] = adj_offsettable_operand (operands[0], 4);
3796 if (GET_MODE (operands[1]) == SImode)
3797 return \"or%.l %1,%0\";
3798 byte_mode = (GET_MODE (operands[1]) == QImode);
3799 if (GET_CODE (operands[0]) == MEM)
3800 operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
3802 return \"or%.b %1,%0\";
3804 return \"or%.w %1,%0\";
3807 ;; "iordi3" is mainly here to help combine().
3808 (define_insn "iordi3"
3809 [(set (match_operand:DI 0 "general_operand" "=o,d")
3810 (ior:DI (match_operand:DI 1 "general_operand" "%0,0")
3811 (match_operand:DI 2 "general_operand" "dn,don")))]
3816 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3817 if (GET_CODE (operands[2]) == CONST_DOUBLE
3818 || GET_CODE (operands[2]) == CONST_INT)
3822 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3824 hi = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
3825 lo = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3830 hi = INTVAL (lo) < 0 ? constm1_rtx : const0_rtx;
3832 switch (INTVAL (hi))
3837 /* FIXME : a scratch register would be welcome here if operand[0]
3838 is not a register */
3839 output_asm_insn (\"move%.l %#-1,%0\", operands);
3845 xoperands[0] = operands[0];
3847 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3850 if (GET_CODE (operands[0]) == REG)
3851 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3853 operands[0] = adj_offsettable_operand (operands[0], 4);
3854 switch (INTVAL (lo))
3859 /* FIXME : a scratch register would be welcome here if operand[0]
3860 is not a register */
3861 output_asm_insn (\"move%.l %#-1,%R0\", operands);
3867 xoperands[0] = operands[0];
3869 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3874 if (GET_CODE (operands[0]) != REG)
3876 operands[1] = adj_offsettable_operand (operands[0], 4);
3877 return \"or%.l %2,%0\;or%.l %R2,%1\";
3879 if (GET_CODE (operands[2]) != REG)
3881 operands[1] = adj_offsettable_operand (operands[2], 4);
3882 return \"or%.l %2,%0\;or%.l %1,%R0\";
3884 return \"or%.l %2,%0\;or%.l %R2,%R0\";
3887 (define_expand "iorsi3"
3888 [(set (match_operand:SI 0 "general_operand" "")
3889 (ior:SI (match_operand:SI 1 "general_operand" "")
3890 (match_operand:SI 2 "general_src_operand" "")))]
3894 (define_insn "iorsi3_internal"
3895 [(set (match_operand:SI 0 "general_operand" "=m,d")
3896 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3897 (match_operand:SI 2 "general_src_operand" "dKT,dmSMT")))]
3901 return output_iorsi3 (operands);
3904 (define_insn "iorsi3_5200"
3905 [(set (match_operand:SI 0 "general_operand" "=m,d")
3906 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3907 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3911 (define_insn "iorhi3"
3912 [(set (match_operand:HI 0 "general_operand" "=m,d")
3913 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3914 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3919 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3920 (ior:HI (match_dup 0)
3921 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3926 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3927 (ior:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3932 (define_insn "iorqi3"
3933 [(set (match_operand:QI 0 "general_operand" "=m,d")
3934 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3935 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3940 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3941 (ior:QI (match_dup 0)
3942 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3947 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3948 (ior:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3953 ;; On all 68k models, this makes faster code in a special case.
3954 ;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
3956 (define_insn "iorsi_zexthi_ashl16"
3957 [(set (match_operand:SI 0 "general_operand" "=&d")
3958 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "rmn"))
3959 (ashift:SI (match_operand:SI 2 "general_operand" "or")
3965 if (GET_CODE (operands[2]) != REG)
3966 operands[2] = adj_offsettable_operand (operands[2], 2);
3967 if (GET_CODE (operands[2]) != REG
3968 || REGNO (operands[2]) != REGNO (operands[0]))
3969 output_asm_insn (\"move%.w %2,%0\", operands);
3970 return \"swap %0\;mov%.w %1,%0\";
3973 (define_insn "iorsi_zext"
3974 [(set (match_operand:SI 0 "general_operand" "=o,d")
3975 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3976 (match_operand:SI 2 "general_operand" "0,0")))]
3983 byte_mode = (GET_MODE (operands[1]) == QImode);
3984 if (GET_CODE (operands[0]) == MEM)
3985 operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
3987 return \"or%.b %1,%0\";
3989 return \"or%.w %1,%0\";
3994 ;; "xordi3" is mainly here to help combine().
3995 (define_insn "xordi3"
3996 [(set (match_operand:DI 0 "general_operand" "=od")
3997 (xor:DI (match_operand:DI 1 "general_operand" "%0")
3998 (match_operand:DI 2 "general_operand" "dn")))]
4003 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
4004 if (GET_CODE (operands[2]) == CONST_DOUBLE
4005 || GET_CODE (operands[2]) == CONST_INT)
4009 if (GET_CODE (operands[2]) == CONST_DOUBLE)
4011 hi = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
4012 lo = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
4017 hi = INTVAL (lo) < 0 ? constm1_rtx : const0_rtx;
4019 switch (INTVAL (hi))
4024 output_asm_insn (\"not%.l %0\", operands);
4027 /* FIXME : a scratch register would be welcome here if
4028 -128 <= INTVAL (hi) < -1 */
4032 xoperands[0] = operands[0];
4034 output_asm_insn (output_xorsi3 (xoperands), xoperands);
4037 if (GET_CODE (operands[0]) == REG)
4038 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4040 operands[0] = adj_offsettable_operand (operands[0], 4);
4041 switch (INTVAL (lo))
4046 output_asm_insn (\"not%.l %0\", operands);
4049 /* FIXME : a scratch register would be welcome here if
4050 -128 <= INTVAL (lo) < -1 */
4052 /* FIXME : this should be merged with xorsi3 */
4056 xoperands[0] = operands[0];
4058 output_asm_insn (output_xorsi3 (xoperands), xoperands);
4063 if (GET_CODE (operands[0]) != REG)
4065 operands[1] = adj_offsettable_operand (operands[0], 4);
4066 return \"eor%.l %2,%0\;eor%.l %R2,%1\";
4068 if (GET_CODE (operands[2]) != REG)
4070 operands[1] = adj_offsettable_operand (operands[2], 4);
4071 return \"eor%.l %2,%0\;eor%.l %1,%R0\";
4073 return \"eor%.l %2,%0\;eor%.l %R2,%R0\";
4076 (define_expand "xorsi3"
4077 [(set (match_operand:SI 0 "general_operand" "")
4078 (xor:SI (match_operand:SI 1 "general_operand" "")
4079 (match_operand:SI 2 "general_operand" "")))]
4083 (define_insn "xorsi3_internal"
4084 [(set (match_operand:SI 0 "general_operand" "=do,m")
4085 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
4086 (match_operand:SI 2 "general_operand" "di,dKT")))]
4091 return output_xorsi3 (operands);
4094 (define_insn "xorsi3_5200"
4095 [(set (match_operand:SI 0 "general_operand" "=dm,d")
4096 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
4097 (match_operand:SI 2 "general_operand" "d,Ks")))]
4101 (define_insn "xorhi3"
4102 [(set (match_operand:HI 0 "general_operand" "=dm")
4103 (xor:HI (match_operand:HI 1 "general_operand" "%0")
4104 (match_operand:HI 2 "general_operand" "dn")))]
4109 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4110 (xor:HI (match_dup 0)
4111 (match_operand:HI 1 "general_operand" "dn")))]
4116 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4117 (xor:HI (match_operand:HI 1 "general_operand" "dn")
4122 (define_insn "xorqi3"
4123 [(set (match_operand:QI 0 "general_operand" "=dm")
4124 (xor:QI (match_operand:QI 1 "general_operand" "%0")
4125 (match_operand:QI 2 "general_operand" "dn")))]
4130 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4131 (xor:QI (match_dup 0)
4132 (match_operand:QI 1 "general_operand" "dn")))]
4137 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4138 (xor:QI (match_operand:QI 1 "general_operand" "dn")
4143 ;; negation instructions
4145 (define_expand "negdi2"
4146 [(set (match_operand:DI 0 "general_operand" "")
4147 (neg:DI (match_operand:DI 1 "general_operand" "")))]
4152 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
4154 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
4158 (define_insn "negdi2_internal"
4159 [(set (match_operand:DI 0 "general_operand" "=<,do,!*a")
4160 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
4164 if (which_alternative == 0)
4165 return \"neg%.l %0\;negx%.l %0\";
4166 if (GET_CODE (operands[0]) == REG)
4167 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4169 operands[1] = adj_offsettable_operand (operands[0], 4);
4170 if (ADDRESS_REG_P (operands[0]))
4171 return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
4173 return \"neg%.l %1\;negx%.l %0\";
4176 (define_insn "negdi2_5200"
4177 [(set (match_operand:DI 0 "general_operand" "=d")
4178 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
4182 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4183 return \"neg%.l %1\;negx%.l %0\";
4186 (define_expand "negsi2"
4187 [(set (match_operand:SI 0 "general_operand" "")
4188 (neg:SI (match_operand:SI 1 "general_operand" "")))]
4193 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
4195 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
4199 (define_insn "negsi2_internal"
4200 [(set (match_operand:SI 0 "general_operand" "=dm")
4201 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4205 (define_insn "negsi2_5200"
4206 [(set (match_operand:SI 0 "general_operand" "=d")
4207 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4211 (define_insn "neghi2"
4212 [(set (match_operand:HI 0 "general_operand" "=dm")
4213 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
4218 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4219 (neg:HI (match_dup 0)))]
4223 (define_insn "negqi2"
4224 [(set (match_operand:QI 0 "general_operand" "=dm")
4225 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
4230 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4231 (neg:QI (match_dup 0)))]
4235 ;; If using software floating point, just flip the sign bit.
4237 (define_expand "negsf2"
4238 [(set (match_operand:SF 0 "general_operand" "")
4239 (neg:SF (match_operand:SF 1 "general_operand" "")))]
4243 if (!TARGET_FPA && !TARGET_68881)
4248 target = operand_subword_force (operands[0], 0, SFmode);
4249 result = expand_binop (SImode, xor_optab,
4250 operand_subword_force (operands[1], 0, SFmode),
4251 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
4255 if (result != target)
4256 emit_move_insn (result, target);
4258 /* Make a place for REG_EQUAL. */
4259 emit_move_insn (operands[0], operands[0]);
4265 [(set (match_operand:SF 0 "general_operand" "=x,y")
4266 (neg:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4271 [(set (match_operand:SF 0 "general_operand" "=f,d")
4272 (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))]
4276 if (DATA_REG_P (operands[0]))
4278 operands[1] = GEN_INT (31);
4279 return \"bchg %1,%0\";
4281 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4282 return \"f%$neg%.x %1,%0\";
4283 return \"f%$neg%.s %f1,%0\";
4286 (define_expand "negdf2"
4287 [(set (match_operand:DF 0 "general_operand" "")
4288 (neg:DF (match_operand:DF 1 "general_operand" "")))]
4292 if (!TARGET_FPA && !TARGET_68881)
4299 target = operand_subword (operands[0], 0, 1, DFmode);
4300 result = expand_binop (SImode, xor_optab,
4301 operand_subword_force (operands[1], 0, DFmode),
4302 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
4306 if (result != target)
4307 emit_move_insn (result, target);
4309 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4310 operand_subword_force (operands[1], 1, DFmode));
4312 insns = get_insns ();
4315 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4321 [(set (match_operand:DF 0 "general_operand" "=x,y")
4322 (neg:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4327 [(set (match_operand:DF 0 "general_operand" "=f,d")
4328 (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
4332 if (DATA_REG_P (operands[0]))
4334 operands[1] = GEN_INT (31);
4335 return \"bchg %1,%0\";
4337 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4338 return \"f%&neg%.x %1,%0\";
4339 return \"f%&neg%.d %f1,%0\";
4342 ;; Sqrt instruction for the 68881
4344 (define_insn "sqrtsf2"
4345 [(set (match_operand:SF 0 "general_operand" "=f")
4346 (sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
4350 if (FP_REG_P (operands[1]))
4351 return \"f%$sqrt%.x %1,%0\";
4353 return \"f%$sqrt%.s %1,%0\";
4356 (define_insn "sqrtdf2"
4357 [(set (match_operand:DF 0 "general_operand" "=f")
4358 (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
4362 if (FP_REG_P (operands[1]))
4363 return \"f%&sqrt%.x %1,%0\";
4365 return \"f%&sqrt%.d %1,%0\";
4368 ;; Absolute value instructions
4369 ;; If using software floating point, just zero the sign bit.
4371 (define_expand "abssf2"
4372 [(set (match_operand:SF 0 "general_operand" "")
4373 (abs:SF (match_operand:SF 1 "general_operand" "")))]
4377 if (!TARGET_FPA && !TARGET_68881)
4382 target = operand_subword_force (operands[0], 0, SFmode);
4383 result = expand_binop (SImode, and_optab,
4384 operand_subword_force (operands[1], 0, SFmode),
4385 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
4389 if (result != target)
4390 emit_move_insn (result, target);
4392 /* Make a place for REG_EQUAL. */
4393 emit_move_insn (operands[0], operands[0]);
4399 [(set (match_operand:SF 0 "general_operand" "=x,y")
4400 (abs:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4405 [(set (match_operand:SF 0 "general_operand" "=f")
4406 (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
4410 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4411 return \"f%$abs%.x %1,%0\";
4412 return \"f%$abs%.s %f1,%0\";
4415 (define_expand "absdf2"
4416 [(set (match_operand:DF 0 "general_operand" "")
4417 (abs:DF (match_operand:DF 1 "general_operand" "")))]
4421 if (!TARGET_FPA && !TARGET_68881)
4428 target = operand_subword (operands[0], 0, 1, DFmode);
4429 result = expand_binop (SImode, and_optab,
4430 operand_subword_force (operands[1], 0, DFmode),
4431 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
4435 if (result != target)
4436 emit_move_insn (result, target);
4438 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4439 operand_subword_force (operands[1], 1, DFmode));
4441 insns = get_insns ();
4444 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4450 [(set (match_operand:DF 0 "general_operand" "=x,y")
4451 (abs:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4456 [(set (match_operand:DF 0 "general_operand" "=f")
4457 (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
4461 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4462 return \"f%&abs%.x %1,%0\";
4463 return \"f%&abs%.d %f1,%0\";
4466 ;; one complement instructions
4468 ;; "one_cmpldi2" is mainly here to help combine().
4469 (define_insn "one_cmpldi2"
4470 [(set (match_operand:DI 0 "general_operand" "=dm")
4471 (not:DI (match_operand:DI 1 "general_operand" "0")))]
4476 if (GET_CODE (operands[0]) == REG)
4477 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4478 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
4479 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4480 operands[1] = operands[0];
4482 operands[1] = adj_offsettable_operand (operands[0], 4);
4483 return \"not%.l %1\;not%.l %0\";
4486 (define_expand "one_cmplsi2"
4487 [(set (match_operand:SI 0 "general_operand" "")
4488 (not:SI (match_operand:SI 1 "general_operand" "")))]
4493 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
4495 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
4499 (define_insn "one_cmplsi2_internal"
4500 [(set (match_operand:SI 0 "general_operand" "=dm")
4501 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4505 (define_insn "one_cmplsi2_5200"
4506 [(set (match_operand:SI 0 "general_operand" "=d")
4507 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4511 (define_insn "one_cmplhi2"
4512 [(set (match_operand:HI 0 "general_operand" "=dm")
4513 (not:HI (match_operand:HI 1 "general_operand" "0")))]
4518 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4519 (not:HI (match_dup 0)))]
4523 (define_insn "one_cmplqi2"
4524 [(set (match_operand:QI 0 "general_operand" "=dm")
4525 (not:QI (match_operand:QI 1 "general_operand" "0")))]
4530 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4531 (not:QI (match_dup 0)))]
4535 ;; arithmetic shift instructions
4536 ;; We don't need the shift memory by 1 bit instruction
4538 (define_insn "ashldi_extsi"
4539 [(set (match_operand:DI 0 "general_operand" "=ro")
4541 (match_operator:DI 2 "extend_operator"
4542 [(match_operand:SI 1 "general_operand" "rm")])
4548 if (GET_CODE (operands[0]) == REG)
4549 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4551 operands[2] = adj_offsettable_operand (operands[0], 4);
4552 if (ADDRESS_REG_P (operands[0]))
4553 return \"move%.l %1,%0\;sub%.l %2,%2\";
4555 return \"move%.l %1,%0\;clr%.l %2\";
4558 (define_insn "ashldi_sexthi"
4559 [(set (match_operand:DI 0 "general_operand" "=m,a*d")
4560 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
4562 (clobber (match_scratch:SI 2 "=a,X"))]
4567 if (GET_CODE (operands[0]) == MEM)
4569 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4570 return \"clr%.l %0\;move%.w %1,%2\;move%.l %2,%0\";
4571 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4572 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %0\";
4575 operands[3] = adj_offsettable_operand (operands[0], 4);
4576 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %3\";
4579 else if (DATA_REG_P (operands[0]))
4580 return \"move%.w %1,%0\;ext%.l %0\;clr%.l %R0\";
4582 return \"move%.w %1,%0\;sub%.l %R0,%R0\";
4585 (define_insn "ashldi_const32"
4586 [(set (match_operand:DI 0 "general_operand" "=rm")
4587 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
4593 if (GET_CODE (operands[1]) == REG)
4594 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4596 operands[3] = adj_offsettable_operand (operands[1], 4);
4597 if (GET_CODE (operands[0]) == REG)
4598 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4599 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4600 return \"clr%.l %0\;move%.l %3,%0\";
4601 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4602 return \"move%.l %3,%0\;clr%.l %0\";
4604 operands[2] = adj_offsettable_operand (operands[0], 4);
4605 if (ADDRESS_REG_P (operands[2]))
4606 return \"move%.l %3,%0\;sub%.l %2,%2\";
4608 return \"move%.l %3,%0\;clr%.l %2\";
4611 ;; The predicate below must be general_operand, because ashldi3 allows that
4612 (define_insn "ashldi_const"
4613 [(set (match_operand:DI 0 "general_operand" "=d")
4614 (ashift:DI (match_operand:DI 1 "general_operand" "0")
4615 (match_operand 2 "const_int_operand" "n")))]
4617 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4618 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4619 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4622 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4623 if (INTVAL (operands[2]) == 1)
4624 return \"add%.l %1,%1\;addx%.l %0,%0\";
4625 else if (INTVAL (operands[2]) == 8)
4626 return \"rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1\";
4627 else if (INTVAL (operands[2]) == 16)
4628 return \"swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1\";
4629 else if (INTVAL (operands[2]) == 48)
4630 return \"mov%.l %1,%0\;swap %0\;clr%.l %1\;clr%.w %0\";
4631 else if (INTVAL (operands[2]) == 2)
4632 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4633 else if (INTVAL (operands[2]) == 3)
4634 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4635 else /* 32 < INTVAL (operands[2]) <= 63 */
4637 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4638 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asl%.l %2,%1\" :
4639 \"moveq %2,%0\;asl%.l %0,%1\", operands);
4640 return \"mov%.l %1,%0\;moveq %#0,%1\";
4644 (define_expand "ashldi3"
4645 [(set (match_operand:DI 0 "general_operand" "")
4646 (ashift:DI (match_operand:DI 1 "general_operand" "")
4647 (match_operand 2 "const_int_operand" "")))]
4651 /* ??? This is a named pattern like this is not allowed to FAIL based
4653 if (GET_CODE (operands[2]) != CONST_INT
4654 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4655 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4656 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4660 ;; On most 68k models, this makes faster code in a special case.
4662 (define_insn "ashlsi_16"
4663 [(set (match_operand:SI 0 "register_operand" "=d")
4664 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4670 return \"swap %0\;clr%.w %0\";
4673 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
4674 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
4676 ;; On the 68000, this makes faster code in a special case.
4678 (define_insn "ashlsi_17_24"
4679 [(set (match_operand:SI 0 "register_operand" "=d")
4680 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4681 (match_operand:SI 2 "const_int_operand" "n")))]
4682 "(! TARGET_68020 && !TARGET_5200
4683 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4688 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4689 return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\";
4692 (define_insn "ashlsi3"
4693 [(set (match_operand:SI 0 "register_operand" "=d")
4694 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4695 (match_operand:SI 2 "general_operand" "dI")))]
4699 if (operands[2] == const1_rtx)
4701 cc_status.flags = CC_NO_OVERFLOW;
4702 return \"add%.l %0,%0\";
4704 return \"lsl%.l %2,%0\";
4707 (define_insn "ashlhi3"
4708 [(set (match_operand:HI 0 "register_operand" "=d")
4709 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4710 (match_operand:HI 2 "general_operand" "dI")))]
4715 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4716 (ashift:HI (match_dup 0)
4717 (match_operand:HI 1 "general_operand" "dI")))]
4721 (define_insn "ashlqi3"
4722 [(set (match_operand:QI 0 "register_operand" "=d")
4723 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4724 (match_operand:QI 2 "general_operand" "dI")))]
4729 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4730 (ashift:QI (match_dup 0)
4731 (match_operand:QI 1 "general_operand" "dI")))]
4735 ;; On most 68k models, this makes faster code in a special case.
4737 (define_insn "ashrsi_16"
4738 [(set (match_operand:SI 0 "register_operand" "=d")
4739 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4742 "swap %0\;ext%.l %0")
4744 ;; On the 68000, this makes faster code in a special case.
4747 [(set (match_operand:SI 0 "register_operand" "=d")
4748 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4749 (match_operand:SI 2 "const_int_operand" "n")))]
4750 "(! TARGET_68020 && !TARGET_5200
4751 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4754 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4755 return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
4758 (define_insn "subreghi1ashrdi_const32"
4759 [(set (match_operand:HI 0 "general_operand" "=rm")
4760 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4761 (const_int 32)) 1))]
4765 if (GET_CODE (operands[1]) != REG)
4766 operands[1] = adj_offsettable_operand (operands[1], 2);
4767 return \"move%.w %1,%0\";
4770 (define_insn "subregsi1ashrdi_const32"
4771 [(set (match_operand:SI 0 "general_operand" "=rm")
4772 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4773 (const_int 32)) 1))]
4777 return \"move%.l %1,%0\";
4780 (define_insn "ashrdi_const32"
4781 [(set (match_operand:DI 0 "register_operand" "=d")
4782 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4788 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4790 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
4792 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
4795 (define_insn "ashrdi_const32_mem"
4796 [(set (match_operand:DI 0 "general_operand" "=o,<")
4797 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro")
4799 (clobber (match_scratch:SI 2 "=d,d"))]
4804 if (which_alternative == 1)
4805 operands[3] = operands[0];
4807 operands[3] = adj_offsettable_operand (operands[0], 4);
4809 return \"move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0\";
4811 return \"move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\";
4814 ;; The predicate below must be general_operand, because ashrdi3 allows that
4815 (define_insn "ashrdi_const"
4816 [(set (match_operand:DI 0 "general_operand" "=d")
4817 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
4818 (match_operand 2 "const_int_operand" "n")))]
4820 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4821 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4822 || INTVAL (operands[2]) == 31
4823 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4826 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4827 if (INTVAL (operands[2]) == 63)
4828 return \"add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1\";
4830 if (INTVAL (operands[2]) == 1)
4831 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
4832 else if (INTVAL (operands[2]) == 8)
4833 return \"move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1\";
4834 else if (INTVAL (operands[2]) == 16)
4835 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;ext%.l %0\";
4836 else if (INTVAL (operands[2]) == 48)
4837 return \"swap %0\;ext%.l %0\;move%.l %0,%1\;smi %0\;ext%.w %0\";
4838 else if (INTVAL (operands[2]) == 31)
4839 return \"add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0\";
4840 else if (INTVAL (operands[2]) == 2)
4841 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4842 else if (INTVAL (operands[2]) == 3)
4843 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4844 else /* 32 < INTVAL (operands[2]) <= 63 */
4846 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4847 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asr%.l %2,%0\" :
4848 \"moveq %2,%1\;asr%.l %1,%0\", operands);
4849 output_asm_insn (\"mov%.l %0,%1\;smi %0\", operands);
4850 return INTVAL (operands[2]) >= 15 ? \"ext%.w %d0\" :
4851 TARGET_68020 ? \"extb%.l %0\" : \"ext%.w %0\;ext%.l %0\";
4855 (define_expand "ashrdi3"
4856 [(set (match_operand:DI 0 "general_operand" "")
4857 (ashiftrt:DI (match_operand:DI 1 "general_operand" "")
4858 (match_operand 2 "const_int_operand" "")))]
4862 /* ??? This is a named pattern like this is not allowed to FAIL based
4864 if (GET_CODE (operands[2]) != CONST_INT
4865 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4866 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4867 && (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63)))
4871 ;; On all 68k models, this makes faster code in a special case.
4873 (define_insn "ashrsi_31"
4874 [(set (match_operand:SI 0 "register_operand" "=d")
4875 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4880 return \"add%.l %0,%0\;subx%.l %0,%0\";
4883 (define_insn "ashrsi3"
4884 [(set (match_operand:SI 0 "register_operand" "=d")
4885 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4886 (match_operand:SI 2 "general_operand" "dI")))]
4890 (define_insn "ashrhi3"
4891 [(set (match_operand:HI 0 "register_operand" "=d")
4892 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4893 (match_operand:HI 2 "general_operand" "dI")))]
4898 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4899 (ashiftrt:HI (match_dup 0)
4900 (match_operand:HI 1 "general_operand" "dI")))]
4904 (define_insn "ashrqi3"
4905 [(set (match_operand:QI 0 "register_operand" "=d")
4906 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4907 (match_operand:QI 2 "general_operand" "dI")))]
4912 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4913 (ashiftrt:QI (match_dup 0)
4914 (match_operand:QI 1 "general_operand" "dI")))]
4918 ;; logical shift instructions
4920 ;; commented out because of reload problems in 950612-1.c
4923 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4924 ;; (const_int 32)) 1))
4925 ;; (set (match_operand:SI 1 "general_operand" "=dm")
4926 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
4927 ;; (const_int 32)) 1))]
4931 ;; return \"move%.l %0,%1\";
4936 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4937 ;; (const_int 32)) 0))
4938 ;; (set (match_operand:DI 1 "general_operand" "=do")
4939 ;; (lshiftrt:DI (match_dup 0)
4940 ;; (const_int 32)))]
4944 ;; if (GET_CODE (operands[1]) == REG)
4945 ;; operands[2] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4947 ;; operands[2] = adj_offsettable_operand (operands[1], 4);
4948 ;; return \"move%.l %0,%2\;clr%.l %1\";
4951 (define_insn "subreg1lshrdi_const32"
4952 [(set (match_operand:SI 0 "general_operand" "=rm")
4953 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4954 (const_int 32)) 1))]
4958 return \"move%.l %1,%0\";
4961 (define_insn "lshrdi_const32"
4962 [(set (match_operand:DI 0 "general_operand" "=ro,<,>")
4963 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
4969 if (which_alternative == 1)
4970 return \"move%.l %1,%0\;clr%.l %0\";
4971 if (which_alternative == 2)
4972 return \"clr%.l %0\;move%.l %1,%0\";
4973 if (GET_CODE (operands[0]) == REG)
4974 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4976 operands[2] = adj_offsettable_operand (operands[0], 4);
4977 if (GET_CODE (operands[1]) == REG)
4978 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4980 operands[3] = adj_offsettable_operand (operands[1], 4);
4981 if (ADDRESS_REG_P (operands[0]))
4982 return \"move%.l %1,%2\;sub%.l %0,%0\";
4984 return \"move%.l %1,%2\;clr%.l %0\";
4987 ;; The predicate below must be general_operand, because lshrdi3 allows that
4988 (define_insn "lshrdi_const"
4989 [(set (match_operand:DI 0 "general_operand" "=d")
4990 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
4991 (match_operand 2 "const_int_operand" "n")))]
4993 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4994 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4995 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4998 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4999 if (INTVAL (operands[2]) == 63)
5000 return \"add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1\";
5002 if (INTVAL (operands[2]) == 1)
5003 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
5004 else if (INTVAL (operands[2]) == 8)
5005 return \"move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1\";
5006 else if (INTVAL (operands[2]) == 16)
5007 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0\";
5008 else if (INTVAL (operands[2]) == 48)
5009 return \"move%.l %0,%1\;clr%.w %1\;clr%.l %0\;swap %1\";
5010 else if (INTVAL (operands[2]) == 2)
5011 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
5012 else if (INTVAL (operands[2]) == 3)
5013 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
5014 else /* 32 < INTVAL (operands[2]) <= 63 */
5016 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
5017 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"lsr%.l %2,%0\" :
5018 \"moveq %2,%1\;lsr%.l %1,%0\", operands);
5019 return \"mov%.l %0,%1\;moveq %#0,%0\";
5023 (define_expand "lshrdi3"
5024 [(set (match_operand:DI 0 "general_operand" "")
5025 (lshiftrt:DI (match_operand:DI 1 "general_operand" "")
5026 (match_operand 2 "const_int_operand" "")))]
5030 /* ??? This is a named pattern like this is not allowed to FAIL based
5032 if (GET_CODE (operands[2]) != CONST_INT
5033 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
5034 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
5035 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
5039 ;; On all 68k models, this makes faster code in a special case.
5041 (define_insn "lshrsi_31"
5042 [(set (match_operand:SI 0 "register_operand" "=d")
5043 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5048 return \"add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0\";
5051 ;; On most 68k models, this makes faster code in a special case.
5053 (define_insn "lshrsi_16"
5054 [(set (match_operand:SI 0 "register_operand" "=d")
5055 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5061 return \"clr%.w %0\;swap %0\";
5064 ;; On the 68000, this makes faster code in a special case.
5066 (define_insn "lshrsi_17_24"
5067 [(set (match_operand:SI 0 "register_operand" "=d")
5068 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5069 (match_operand:SI 2 "const_int_operand" "n")))]
5070 "(! TARGET_68020 && !TARGET_5200
5071 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
5074 /* I think lsr%.w sets the CC properly. */
5075 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
5076 return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\";
5079 (define_insn "lshrsi3"
5080 [(set (match_operand:SI 0 "register_operand" "=d")
5081 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5082 (match_operand:SI 2 "general_operand" "dI")))]
5086 (define_insn "lshrhi3"
5087 [(set (match_operand:HI 0 "register_operand" "=d")
5088 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
5089 (match_operand:HI 2 "general_operand" "dI")))]
5094 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5095 (lshiftrt:HI (match_dup 0)
5096 (match_operand:HI 1 "general_operand" "dI")))]
5100 (define_insn "lshrqi3"
5101 [(set (match_operand:QI 0 "register_operand" "=d")
5102 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
5103 (match_operand:QI 2 "general_operand" "dI")))]
5108 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5109 (lshiftrt:QI (match_dup 0)
5110 (match_operand:QI 1 "general_operand" "dI")))]
5114 ;; rotate instructions
5116 (define_insn "rotlsi3"
5117 [(set (match_operand:SI 0 "register_operand" "=d")
5118 (rotate:SI (match_operand:SI 1 "register_operand" "0")
5119 (match_operand:SI 2 "general_operand" "dINO")))]
5123 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
5125 else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
5127 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
5128 return \"ror%.l %2,%0\";
5131 return \"rol%.l %2,%0\";
5134 (define_insn "rotlhi3"
5135 [(set (match_operand:HI 0 "register_operand" "=d")
5136 (rotate:HI (match_operand:HI 1 "register_operand" "0")
5137 (match_operand:HI 2 "general_operand" "dIP")))]
5141 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
5143 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
5144 return \"ror%.w %2,%0\";
5147 return \"rol%.w %2,%0\";
5151 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5152 (rotate:HI (match_dup 0)
5153 (match_operand:HI 1 "general_operand" "dIP")))]
5157 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
5159 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
5160 return \"ror%.w %2,%0\";
5163 return \"rol%.w %2,%0\";
5166 (define_insn "rotlqi3"
5167 [(set (match_operand:QI 0 "register_operand" "=d")
5168 (rotate:QI (match_operand:QI 1 "register_operand" "0")
5169 (match_operand:QI 2 "general_operand" "dI")))]
5173 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
5175 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
5176 return \"ror%.b %2,%0\";
5179 return \"rol%.b %2,%0\";
5183 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5184 (rotate:QI (match_dup 0)
5185 (match_operand:QI 1 "general_operand" "dI")))]
5189 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
5191 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
5192 return \"ror%.b %2,%0\";
5195 return \"rol%.b %2,%0\";
5198 (define_insn "rotrsi3"
5199 [(set (match_operand:SI 0 "register_operand" "=d")
5200 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
5201 (match_operand:SI 2 "general_operand" "dI")))]
5205 (define_insn "rotrhi3"
5206 [(set (match_operand:HI 0 "register_operand" "=d")
5207 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
5208 (match_operand:HI 2 "general_operand" "dI")))]
5213 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5214 (rotatert:HI (match_dup 0)
5215 (match_operand:HI 1 "general_operand" "dI")))]
5219 (define_insn "rotrqi3"
5220 [(set (match_operand:QI 0 "register_operand" "=d")
5221 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
5222 (match_operand:QI 2 "general_operand" "dI")))]
5227 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5228 (rotatert:QI (match_dup 0)
5229 (match_operand:QI 1 "general_operand" "dI")))]
5234 ;; Bit set/clear in memory byte.
5236 ;; set bit, bit number is int
5237 (define_insn "bsetmemqi"
5238 [(set (match_operand:QI 0 "memory_operand" "+m")
5239 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5240 (match_operand:SI 1 "general_operand" "d")) 0)
5246 return \"bset %1,%0\";
5249 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
5251 [(set (match_operand:QI 0 "memory_operand" "+m")
5252 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5253 (match_operator:SI 2 "extend_operator"
5254 [(match_operand 1 "general_operand" "d")])) 0)
5260 return \"bset %1,%0\";
5263 ;; clear bit, bit number is int
5264 (define_insn "bclrmemqi"
5265 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5267 (minus:SI (const_int 7)
5268 (match_operand:SI 1 "general_operand" "d")))
5274 return \"bclr %1,%0\";
5277 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
5279 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5281 (minus:SI (const_int 7)
5282 (match_operator:SI 2 "extend_operator"
5283 [(match_operand 1 "general_operand" "d")])))
5289 return \"bclr %1,%0\";
5292 ;; Special cases of bit-field insns which we should
5293 ;; recognize in preference to the general case.
5294 ;; These handle aligned 8-bit and 16-bit fields,
5295 ;; which can usually be done with move instructions.
5298 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5299 ; alignment of structure members is specified.
5301 ; The move is allowed to be odd byte aligned, because that's still faster
5302 ; than an odd byte aligned bit field instruction.
5305 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5307 (match_operand:SI 2 "const_int_operand" "n"))
5308 (match_operand:SI 3 "general_src_operand" "rmSi"))]
5309 "TARGET_68020 && TARGET_BITFIELD
5310 && (INTVAL (operands[2]) % 8) == 0
5311 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
5315 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
5317 return \"move%.l %3,%0\";
5321 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
5322 (match_operand:SI 1 "const_int_operand" "n")
5323 (match_operand:SI 2 "const_int_operand" "n"))
5324 (match_operand:SI 3 "register_operand" "d"))]
5325 "TARGET_68020 && TARGET_BITFIELD
5326 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
5327 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
5328 && (GET_CODE (operands[0]) == REG
5329 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
5332 if (REG_P (operands[0]))
5334 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
5335 return \"bfins %3,%0{%b2:%b1}\";
5339 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
5341 if (GET_CODE (operands[3]) == MEM)
5342 operands[3] = adj_offsettable_operand (operands[3],
5343 (32 - INTVAL (operands[1])) / 8);
5344 if (INTVAL (operands[1]) == 8)
5345 return \"move%.b %3,%0\";
5346 return \"move%.w %3,%0\";
5351 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5352 ; alignment of structure members is specified.
5354 ; The move is allowed to be odd byte aligned, because that's still faster
5355 ; than an odd byte aligned bit field instruction.
5358 [(set (match_operand:SI 0 "general_operand" "=rm")
5359 (zero_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
5361 (match_operand:SI 3 "const_int_operand" "n")))]
5362 "TARGET_68020 && TARGET_BITFIELD
5363 && (INTVAL (operands[3]) % 8) == 0
5364 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5368 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5370 return \"move%.l %1,%0\";
5374 [(set (match_operand:SI 0 "general_operand" "=&d")
5375 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
5376 (match_operand:SI 2 "const_int_operand" "n")
5377 (match_operand:SI 3 "const_int_operand" "n")))]
5378 "TARGET_68020 && TARGET_BITFIELD
5379 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5380 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5381 && (GET_CODE (operands[1]) == REG
5382 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5385 cc_status.flags |= CC_NOT_NEGATIVE;
5386 if (REG_P (operands[1]))
5388 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5389 return \"bfextu %1{%b3:%b2},%0\";
5393 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5395 output_asm_insn (\"clr%.l %0\", operands);
5396 if (GET_CODE (operands[0]) == MEM)
5397 operands[0] = adj_offsettable_operand (operands[0],
5398 (32 - INTVAL (operands[1])) / 8);
5399 if (INTVAL (operands[2]) == 8)
5400 return \"move%.b %1,%0\";
5401 return \"move%.w %1,%0\";
5405 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5406 ; alignment of structure members is specified.
5408 ; The move is allowed to be odd byte aligned, because that's still faster
5409 ; than an odd byte aligned bit field instruction.
5412 [(set (match_operand:SI 0 "general_operand" "=rm")
5413 (sign_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
5415 (match_operand:SI 3 "const_int_operand" "n")))]
5416 "TARGET_68020 && TARGET_BITFIELD
5417 && (INTVAL (operands[3]) % 8) == 0
5418 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5422 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5424 return \"move%.l %1,%0\";
5428 [(set (match_operand:SI 0 "general_operand" "=d")
5429 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
5430 (match_operand:SI 2 "const_int_operand" "n")
5431 (match_operand:SI 3 "const_int_operand" "n")))]
5432 "TARGET_68020 && TARGET_BITFIELD
5433 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5434 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5435 && (GET_CODE (operands[1]) == REG
5436 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5439 if (REG_P (operands[1]))
5441 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5442 return \"bfexts %1{%b3:%b2},%0\";
5446 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5448 if (INTVAL (operands[2]) == 8)
5449 return \"move%.b %1,%0\;extb%.l %0\";
5450 return \"move%.w %1,%0\;ext%.l %0\";
5453 ;; Bit field instructions, general cases.
5454 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
5455 ;; so that its address is reloaded.
5457 (define_expand "extv"
5458 [(set (match_operand:SI 0 "general_operand" "")
5459 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
5460 (match_operand:SI 2 "general_operand" "")
5461 (match_operand:SI 3 "general_operand" "")))]
5462 "TARGET_68020 && TARGET_BITFIELD"
5466 [(set (match_operand:SI 0 "general_operand" "=d")
5467 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5468 (match_operand:SI 2 "general_operand" "di")
5469 (match_operand:SI 3 "general_operand" "di")))]
5470 "TARGET_68020 && TARGET_BITFIELD"
5471 "bfexts %1{%b3:%b2},%0")
5473 (define_expand "extzv"
5474 [(set (match_operand:SI 0 "general_operand" "")
5475 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
5476 (match_operand:SI 2 "general_operand" "")
5477 (match_operand:SI 3 "general_operand" "")))]
5478 "TARGET_68020 && TARGET_BITFIELD"
5482 [(set (match_operand:SI 0 "general_operand" "=d,d")
5483 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
5484 (match_operand:SI 2 "general_operand" "di,di")
5485 (match_operand:SI 3 "general_operand" "di,di")))]
5486 "TARGET_68020 && TARGET_BITFIELD"
5489 if (GET_CODE (operands[2]) == CONST_INT)
5491 if (INTVAL (operands[2]) != 32)
5492 cc_status.flags |= CC_NOT_NEGATIVE;
5498 return \"bfextu %1{%b3:%b2},%0\";
5502 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5503 (match_operand:SI 1 "general_operand" "di")
5504 (match_operand:SI 2 "general_operand" "di"))
5505 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
5506 (match_operand 3 "const_int_operand" "n")))]
5507 "TARGET_68020 && TARGET_BITFIELD
5508 && (INTVAL (operands[3]) == -1
5509 || (GET_CODE (operands[1]) == CONST_INT
5510 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
5514 return \"bfchg %0{%b2:%b1}\";
5518 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5519 (match_operand:SI 1 "general_operand" "di")
5520 (match_operand:SI 2 "general_operand" "di"))
5522 "TARGET_68020 && TARGET_BITFIELD"
5526 return \"bfclr %0{%b2:%b1}\";
5530 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5531 (match_operand:SI 1 "general_operand" "di")
5532 (match_operand:SI 2 "general_operand" "di"))
5534 "TARGET_68020 && TARGET_BITFIELD"
5538 return \"bfset %0{%b2:%b1}\";
5541 (define_expand "insv"
5542 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
5543 (match_operand:SI 1 "general_operand" "")
5544 (match_operand:SI 2 "general_operand" ""))
5545 (match_operand:SI 3 "register_operand" ""))]
5546 "TARGET_68020 && TARGET_BITFIELD"
5550 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5551 (match_operand:SI 1 "general_operand" "di")
5552 (match_operand:SI 2 "general_operand" "di"))
5553 (match_operand:SI 3 "register_operand" "d"))]
5554 "TARGET_68020 && TARGET_BITFIELD"
5555 "bfins %3,%0{%b2:%b1}")
5557 ;; Now recognize bit field insns that operate on registers
5558 ;; (or at least were intended to do so).
5561 [(set (match_operand:SI 0 "general_operand" "=d")
5562 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5563 (match_operand:SI 2 "general_operand" "di")
5564 (match_operand:SI 3 "general_operand" "di")))]
5565 "TARGET_68020 && TARGET_BITFIELD"
5566 "bfexts %1{%b3:%b2},%0")
5569 [(set (match_operand:SI 0 "general_operand" "=d")
5570 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5571 (match_operand:SI 2 "general_operand" "di")
5572 (match_operand:SI 3 "general_operand" "di")))]
5573 "TARGET_68020 && TARGET_BITFIELD"
5576 if (GET_CODE (operands[2]) == CONST_INT)
5578 if (INTVAL (operands[2]) != 32)
5579 cc_status.flags |= CC_NOT_NEGATIVE;
5585 return \"bfextu %1{%b3:%b2},%0\";
5589 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5590 (match_operand:SI 1 "general_operand" "di")
5591 (match_operand:SI 2 "general_operand" "di"))
5593 "TARGET_68020 && TARGET_BITFIELD"
5597 return \"bfclr %0{%b2:%b1}\";
5601 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5602 (match_operand:SI 1 "general_operand" "di")
5603 (match_operand:SI 2 "general_operand" "di"))
5605 "TARGET_68020 && TARGET_BITFIELD"
5609 return \"bfset %0{%b2:%b1}\";
5613 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5614 (match_operand:SI 1 "general_operand" "di")
5615 (match_operand:SI 2 "general_operand" "di"))
5616 (match_operand:SI 3 "register_operand" "d"))]
5617 "TARGET_68020 && TARGET_BITFIELD"
5621 /* These special cases are now recognized by a specific pattern. */
5622 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5623 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5624 return \"move%.w %3,%0\";
5625 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5626 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
5627 return \"move%.b %3,%0\";
5629 return \"bfins %3,%0{%b2:%b1}\";
5632 ;; Special patterns for optimizing bit-field instructions.
5636 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5637 (match_operand:SI 1 "const_int_operand" "n")
5638 (match_operand:SI 2 "general_operand" "di")))]
5639 "TARGET_68020 && TARGET_BITFIELD"
5642 if (operands[1] == const1_rtx
5643 && GET_CODE (operands[2]) == CONST_INT)
5645 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5646 return output_btst (operands,
5647 GEN_INT (width - INTVAL (operands[2])),
5650 /* Pass 1000 as SIGNPOS argument so that btst will
5651 not think we are testing the sign bit for an `and'
5652 and assume that nonzero implies a negative result. */
5654 if (INTVAL (operands[1]) != 32)
5655 cc_status.flags = CC_NOT_NEGATIVE;
5656 return \"bftst %0{%b2:%b1}\";
5660 ;;; now handle the register cases
5663 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5664 (match_operand:SI 1 "const_int_operand" "n")
5665 (match_operand:SI 2 "general_operand" "di")))]
5666 "TARGET_68020 && TARGET_BITFIELD"
5669 if (operands[1] == const1_rtx
5670 && GET_CODE (operands[2]) == CONST_INT)
5672 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5673 return output_btst (operands,
5674 GEN_INT (width - INTVAL (operands[2])),
5677 /* Pass 1000 as SIGNPOS argument so that btst will
5678 not think we are testing the sign bit for an `and'
5679 and assume that nonzero implies a negative result. */
5681 if (INTVAL (operands[1]) != 32)
5682 cc_status.flags = CC_NOT_NEGATIVE;
5683 return \"bftst %0{%b2:%b1}\";
5686 (define_insn "scc0_di"
5687 [(set (match_operand:QI 0 "general_operand" "=dm")
5688 (match_operator 1 "valid_dbcc_comparison_p"
5689 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5693 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5696 (define_insn "scc0_di_5200"
5697 [(set (match_operand:QI 0 "general_operand" "=d")
5698 (match_operator 1 "valid_dbcc_comparison_p"
5699 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5703 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5706 (define_insn "scc_di"
5707 [(set (match_operand:QI 0 "general_operand" "=dm,dm")
5708 (match_operator 1 "valid_dbcc_comparison_p"
5709 [(match_operand:DI 2 "general_operand" "ro,r")
5710 (match_operand:DI 3 "general_operand" "r,ro")]))]
5714 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5717 (define_insn "scc_di_5200"
5718 [(set (match_operand:QI 0 "general_operand" "=d,d")
5719 (match_operator 1 "valid_dbcc_comparison_p"
5720 [(match_operand:DI 2 "general_operand" "ro,r")
5721 (match_operand:DI 3 "general_operand" "r,ro")]))]
5725 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5728 ;; Note that operand 0 of an SCC insn is supported in the hardware as
5729 ;; memory, but we cannot allow it to be in memory in case the address
5730 ;; needs to be reloaded.
5732 (define_expand "seq"
5733 [(set (match_operand:QI 0 "register_operand" "")
5734 (eq:QI (cc0) (const_int 0)))]
5738 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5740 m68k_last_compare_had_fp_operands = 0;
5746 [(set (match_operand:QI 0 "register_operand" "=d")
5747 (eq:QI (cc0) (const_int 0)))]
5750 cc_status = cc_prev_status;
5751 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5754 (define_expand "sne"
5755 [(set (match_operand:QI 0 "register_operand" "")
5756 (ne:QI (cc0) (const_int 0)))]
5760 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5762 m68k_last_compare_had_fp_operands = 0;
5768 [(set (match_operand:QI 0 "register_operand" "=d")
5769 (ne:QI (cc0) (const_int 0)))]
5772 cc_status = cc_prev_status;
5773 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5776 (define_expand "sgt"
5777 [(set (match_operand:QI 0 "register_operand" "")
5778 (gt:QI (cc0) (const_int 0)))]
5782 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5784 m68k_last_compare_had_fp_operands = 0;
5790 [(set (match_operand:QI 0 "register_operand" "=d")
5791 (gt:QI (cc0) (const_int 0)))]
5794 cc_status = cc_prev_status;
5795 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5798 (define_expand "sgtu"
5799 [(set (match_operand:QI 0 "register_operand" "")
5800 (gtu:QI (cc0) (const_int 0)))]
5805 [(set (match_operand:QI 0 "register_operand" "=d")
5806 (gtu:QI (cc0) (const_int 0)))]
5809 cc_status = cc_prev_status;
5810 return \"shi %0\"; ")
5812 (define_expand "slt"
5813 [(set (match_operand:QI 0 "register_operand" "")
5814 (lt:QI (cc0) (const_int 0)))]
5818 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5820 m68k_last_compare_had_fp_operands = 0;
5826 [(set (match_operand:QI 0 "register_operand" "=d")
5827 (lt:QI (cc0) (const_int 0)))]
5830 cc_status = cc_prev_status;
5831 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5833 (define_expand "sltu"
5834 [(set (match_operand:QI 0 "register_operand" "")
5835 (ltu:QI (cc0) (const_int 0)))]
5840 [(set (match_operand:QI 0 "register_operand" "=d")
5841 (ltu:QI (cc0) (const_int 0)))]
5844 cc_status = cc_prev_status;
5845 return \"scs %0\"; ")
5847 (define_expand "sge"
5848 [(set (match_operand:QI 0 "register_operand" "")
5849 (ge:QI (cc0) (const_int 0)))]
5853 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5855 m68k_last_compare_had_fp_operands = 0;
5861 [(set (match_operand:QI 0 "register_operand" "=d")
5862 (ge:QI (cc0) (const_int 0)))]
5865 cc_status = cc_prev_status;
5866 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5868 (define_expand "sgeu"
5869 [(set (match_operand:QI 0 "register_operand" "")
5870 (geu:QI (cc0) (const_int 0)))]
5875 [(set (match_operand:QI 0 "register_operand" "=d")
5876 (geu:QI (cc0) (const_int 0)))]
5879 cc_status = cc_prev_status;
5880 return \"scc %0\"; ")
5882 (define_expand "sle"
5883 [(set (match_operand:QI 0 "register_operand" "")
5884 (le:QI (cc0) (const_int 0)))]
5888 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5890 m68k_last_compare_had_fp_operands = 0;
5896 [(set (match_operand:QI 0 "register_operand" "=d")
5897 (le:QI (cc0) (const_int 0)))]
5900 cc_status = cc_prev_status;
5901 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5904 (define_expand "sleu"
5905 [(set (match_operand:QI 0 "register_operand" "")
5906 (leu:QI (cc0) (const_int 0)))]
5911 [(set (match_operand:QI 0 "register_operand" "=d")
5912 (leu:QI (cc0) (const_int 0)))]
5915 cc_status = cc_prev_status;
5916 return \"sls %0\"; ")
5918 ;; Basic conditional jump instructions.
5920 (define_insn "beq0_di"
5922 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
5924 (label_ref (match_operand 1 "" ","))
5926 (clobber (match_scratch:SI 2 "=d,d"))]
5931 if (which_alternative == 1)
5933 return \"move%.l %0,%2\;or%.l %0,%2\;jbeq %l1\";
5935 return \"move%.l %0,%2\;or%.l %0,%2\;jeq %l1\";
5937 if ((cc_prev_status.value1
5938 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5939 || (cc_prev_status.value2
5940 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5942 cc_status = cc_prev_status;
5944 return \"jbeq %l1\";
5949 if (GET_CODE (operands[0]) == REG)
5950 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
5952 operands[3] = adj_offsettable_operand (operands[0], 4);
5953 if (! ADDRESS_REG_P (operands[0]))
5955 if (reg_overlap_mentioned_p (operands[2], operands[0]))
5957 if (reg_overlap_mentioned_p (operands[2], operands[3]))
5960 return \"or%.l %0,%2\;jbeq %l1\";
5962 return \"or%.l %0,%2\;jeq %l1\";
5968 return \"or%.l %3,%2\;jbeq %l1\";
5970 return \"or%.l %3,%2\;jeq %l1\";
5975 return \"move%.l %0,%2\;or%.l %3,%2\;jbeq %l1\";
5977 return \"move%.l %0,%2\;or%.l %3,%2\;jeq %l1\";
5980 operands[4] = gen_label_rtx();
5981 if (TARGET_68020 || TARGET_5200)
5984 output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands);
5986 output_asm_insn (\"tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1\", operands);
5992 #ifdef SGS_CMP_ORDER
5993 output_asm_insn (\"cmp%.w %0,%#0\;jbne %l4\;cmp%.w %3,%#0\;jbeq %l1\", operands);
5995 output_asm_insn (\"cmp%.w %#0,%0\;jbne %l4\;cmp%.w %#0,%3\;jbeq %l1\", operands);
5998 output_asm_insn (\"cmp%.w %#0,%0\;jne %l4\;cmp%.w %#0,%3\;jeq %l1\", operands);
6001 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
6002 CODE_LABEL_NUMBER (operands[4]));
6006 (define_insn "bne0_di"
6008 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
6010 (label_ref (match_operand 1 "" ","))
6012 (clobber (match_scratch:SI 2 "=d,X"))]
6016 if ((cc_prev_status.value1
6017 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6018 || (cc_prev_status.value2
6019 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6021 cc_status = cc_prev_status;
6023 return \"jbne %l1\";
6029 if (GET_CODE (operands[0]) == REG)
6030 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
6032 operands[3] = adj_offsettable_operand (operands[0], 4);
6033 if (!ADDRESS_REG_P (operands[0]))
6035 if (reg_overlap_mentioned_p (operands[2], operands[0]))
6037 if (reg_overlap_mentioned_p (operands[2], operands[3]))
6040 return \"or%.l %0,%2\;jbne %l1\";
6042 return \"or%.l %0,%2\;jne %l1\";
6048 return \"or%.l %3,%2\;jbne %l1\";
6050 return \"or%.l %3,%2\;jne %l1\";
6055 return \"move%.l %0,%2\;or%.l %3,%2\;jbne %l1\";
6057 return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\";
6060 if (TARGET_68020 || TARGET_5200)
6063 return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\";
6065 return \"tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1\";
6071 #ifdef SGS_CMP_ORDER
6072 return \"cmp%.w %0,%#0\;jbne %l1\;cmp%.w %3,%#0\;jbne %l1\";
6074 return \"cmp%.w %#0,%0\;jbne %l1\;cmp%.w %#0,%3\;jbne %l1\";
6077 return \"cmp%.w %#0,%0\;jne %l1\;cmp%.w %#0,%3\;jne %l1\";
6082 (define_insn "bge0_di"
6084 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
6086 (label_ref (match_operand 1 "" ""))
6091 if ((cc_prev_status.value1
6092 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6093 || (cc_prev_status.value2
6094 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6096 cc_status = cc_prev_status;
6097 if (cc_status.flags & CC_REVERSED)
6100 return \"jble %l1\";
6108 return \"jbpl %l1\";
6115 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
6116 output_asm_insn(\"tst%.l %0\", operands);
6119 /* On an address reg, cmpw may replace cmpl. */
6120 #ifdef SGS_CMP_ORDER
6121 output_asm_insn(\"cmp%.w %0,%#0\", operands);
6123 output_asm_insn(\"cmp%.w %#0,%0\", operands);
6128 return \"jbpl %l1\";
6134 (define_insn "blt0_di"
6136 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
6138 (label_ref (match_operand 1 "" ""))
6143 if ((cc_prev_status.value1
6144 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6145 || (cc_prev_status.value2
6146 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6148 cc_status = cc_prev_status;
6149 if (cc_status.flags & CC_REVERSED)
6152 return \"jbgt %l1\";
6160 return \"jbmi %l1\";
6167 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
6168 output_asm_insn(\"tst%.l %0\", operands);
6171 /* On an address reg, cmpw may replace cmpl. */
6172 #ifdef SGS_CMP_ORDER
6173 output_asm_insn(\"cmp%.w %0,%#0\", operands);
6175 output_asm_insn(\"cmp%.w %#0,%0\", operands);
6180 return \"jbmi %l1\";
6188 (if_then_else (eq (cc0)
6190 (label_ref (match_operand 0 "" ""))
6196 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6198 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6204 (if_then_else (ne (cc0)
6206 (label_ref (match_operand 0 "" ""))
6212 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6214 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6220 (if_then_else (gt (cc0)
6222 (label_ref (match_operand 0 "" ""))
6227 OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0);
6229 OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0);
6235 (if_then_else (gtu (cc0)
6237 (label_ref (match_operand 0 "" ""))
6242 return \"jbhi %l0\";
6250 (if_then_else (lt (cc0)
6252 (label_ref (match_operand 0 "" ""))
6257 OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\");
6259 OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\");
6265 (if_then_else (ltu (cc0)
6267 (label_ref (match_operand 0 "" ""))
6272 return \"jbcs %l0\";
6280 (if_then_else (ge (cc0)
6282 (label_ref (match_operand 0 "" ""))
6287 OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\");
6289 OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\");
6295 (if_then_else (geu (cc0)
6297 (label_ref (match_operand 0 "" ""))
6302 return \"jbcc %l0\";
6310 (if_then_else (le (cc0)
6312 (label_ref (match_operand 0 "" ""))
6317 OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0);
6319 OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0);
6325 (if_then_else (leu (cc0)
6327 (label_ref (match_operand 0 "" ""))
6332 return \"jbls %l0\";
6338 ;; Negated conditional jump instructions.
6342 (if_then_else (eq (cc0)
6345 (label_ref (match_operand 0 "" ""))))]
6350 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6352 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6358 (if_then_else (ne (cc0)
6361 (label_ref (match_operand 0 "" ""))))]
6366 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6368 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6374 (if_then_else (gt (cc0)
6377 (label_ref (match_operand 0 "" ""))))]
6381 OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0);
6383 OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0);
6389 (if_then_else (gtu (cc0)
6392 (label_ref (match_operand 0 "" ""))))]
6396 return \"jbls %l0\";
6404 (if_then_else (lt (cc0)
6407 (label_ref (match_operand 0 "" ""))))]
6411 OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\");
6413 OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\");
6419 (if_then_else (ltu (cc0)
6422 (label_ref (match_operand 0 "" ""))))]
6426 return \"jbcc %l0\";
6434 (if_then_else (ge (cc0)
6437 (label_ref (match_operand 0 "" ""))))]
6441 OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\");
6443 OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\");
6449 (if_then_else (geu (cc0)
6452 (label_ref (match_operand 0 "" ""))))]
6456 return \"jbcs %l0\";
6464 (if_then_else (le (cc0)
6467 (label_ref (match_operand 0 "" ""))))]
6471 OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0);
6473 OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0);
6479 (if_then_else (leu (cc0)
6482 (label_ref (match_operand 0 "" ""))))]
6486 return \"jbhi %l0\";
6492 ;; Unconditional and other jump instructions
6495 (label_ref (match_operand 0 "" "")))]
6499 return \"jbra %l0\";
6505 ;; We support two different ways of handling dispatch tables.
6506 ;; The NeXT uses absolute tables, and other machines use relative.
6507 ;; This define_expand can generate either kind.
6508 (define_expand "tablejump"
6509 [(parallel [(set (pc) (match_operand 0 "" ""))
6510 (use (label_ref (match_operand 1 "" "")))])]
6514 #ifdef CASE_VECTOR_PC_RELATIVE
6515 operands[0] = gen_rtx_PLUS (SImode, pc_rtx,
6516 gen_rtx_SIGN_EXTEND (SImode, operands[0]));
6520 ;; Jump to variable address from dispatch table of absolute addresses.
6522 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
6523 (use (label_ref (match_operand 1 "" "")))]
6527 return \"jmp (%0)\";
6533 ;; Jump to variable address from dispatch table of relative addresses.
6537 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
6538 (use (label_ref (match_operand 1 "" "")))]
6541 #ifdef ASM_RETURN_CASE_JUMP
6542 ASM_RETURN_CASE_JUMP;
6545 #ifdef ASM_OUTPUT_CASE_LABEL
6547 return \"ext%.l %0\;jmp 6(%%pc,%0.l)\";
6549 return \"jmp 6(%%pc,%0.w)\";
6554 return \"ext%.l %0\;jmp 2(pc,%0.l)\";
6556 return \"extl %0\;jmp 2(%%pc,%0.l)\";
6557 #endif /* end !CRDS */
6562 return \"jmp 2(pc,%0.w)\";
6564 return \"jmp 2(%%pc,%0.w)\";
6565 #endif /* end !CRDS */
6572 return \"ext%.l %0\;jmp (2,pc,%0.l)\";
6574 return \"extl %0\;jmp pc@(2,%0:l)\";
6580 return \"jmp (2,pc,%0.w)\";
6582 return \"jmp pc@(2,%0:w)\";
6589 ;; Decrement-and-branch insns.
6593 (ne (match_operand:HI 0 "general_operand" "+d*g")
6595 (label_ref (match_operand 1 "" ""))
6598 (plus:HI (match_dup 0)
6604 if (DATA_REG_P (operands[0]))
6605 return \"dbra %0,%l1\";
6606 if (GET_CODE (operands[0]) == MEM)
6610 return \"sub%.w %#1,%0\;jbcc %l1\";
6612 return \"subq%.w %#1,%0\;jbcc %l1\";
6614 #else /* not MOTOROLA */
6615 return \"subqw %#1,%0\;jcc %l1\";
6619 #ifdef SGS_CMP_ORDER
6621 return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6623 return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6625 #else /* not SGS_CMP_ORDER */
6626 return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
6628 #else /* not MOTOROLA */
6629 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6636 (ne (match_operand:SI 0 "general_operand" "+d*g")
6638 (label_ref (match_operand 1 "" ""))
6641 (plus:SI (match_dup 0)
6649 if (DATA_REG_P (operands[0]))
6650 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6651 if (GET_CODE (operands[0]) == MEM)
6652 return \"sub%.l %#1,%0\;jbcc %l1\";
6654 if (DATA_REG_P (operands[0]))
6655 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6656 if (GET_CODE (operands[0]) == MEM)
6657 return \"subq%.l %#1,%0\;jbcc %l1\";
6658 #endif /* NO_ADDSUB_Q */
6659 #ifdef SGS_CMP_ORDER
6661 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6663 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6665 #else /* not SGS_CMP_ORDER */
6666 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6667 #endif /* not SGS_CMP_ORDER */
6668 #else /* not MOTOROLA */
6669 if (DATA_REG_P (operands[0]))
6670 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6671 if (GET_CODE (operands[0]) == MEM)
6672 return \"subql %#1,%0\;jcc %l1\";
6673 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6674 #endif /* not MOTOROLA */
6677 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
6682 (ge (plus:HI (match_operand:HI 0 "general_operand" "+d*am")
6685 (label_ref (match_operand 1 "" ""))
6688 (plus:HI (match_dup 0)
6690 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6696 if (DATA_REG_P (operands[0]))
6697 return \"dbra %0,%l1\";
6698 if (GET_CODE (operands[0]) == MEM)
6699 return \"sub%.w %#1,%0\;jbcc %l1\";
6701 if (DATA_REG_P (operands[0]))
6702 return \"dbra %0,%l1\";
6703 if (GET_CODE (operands[0]) == MEM)
6704 return \"subq%.w %#1,%0\;jbcc %l1\";
6706 #ifdef SGS_CMP_ORDER
6708 return \"sub.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6710 return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6712 #else /* not SGS_CMP_ORDER */
6713 return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\";
6714 #endif /* not SGS_CMP_ORDER */
6715 #else /* not MOTOROLA */
6716 if (DATA_REG_P (operands[0]))
6717 return \"dbra %0,%l1\";
6718 if (GET_CODE (operands[0]) == MEM)
6719 return \"subqw %#1,%0\;jcc %l1\";
6720 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6721 #endif /* not MOTOROLA */
6724 (define_expand "decrement_and_branch_until_zero"
6725 [(parallel [(set (pc)
6727 (ge (plus:SI (match_operand:SI 0 "general_operand" "")
6730 (label_ref (match_operand 1 "" ""))
6733 (plus:SI (match_dup 0)
6741 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
6744 (label_ref (match_operand 1 "" ""))
6747 (plus:SI (match_dup 0)
6749 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6755 if (DATA_REG_P (operands[0]))
6756 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6757 if (GET_CODE (operands[0]) == MEM)
6758 return \"sub%.l %#1,%0\;jbcc %l1\";
6760 if (DATA_REG_P (operands[0]))
6761 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6762 if (GET_CODE (operands[0]) == MEM)
6763 return \"subq%.l %#1,%0\;jbcc %l1\";
6765 #ifdef SGS_CMP_ORDER
6767 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6769 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6771 #else /* not SGS_CMP_ORDER */
6772 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6773 #endif /* not SGS_CMP_ORDER */
6774 #else /* not MOTOROLA */
6775 if (DATA_REG_P (operands[0]))
6776 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6777 if (GET_CODE (operands[0]) == MEM)
6778 return \"subql %#1,%0\;jcc %l1\";
6779 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6780 #endif /* not MOTOROLA */
6784 ;; For PIC calls, in order to be able to support
6785 ;; dynamic linker LAZY BINDING, all the procedure calls need to go
6786 ;; through the PLT (Procedure Linkage Table) section in PIC mode.
6788 ;; PIC calls are handled by loading the address of the function into a
6789 ;; register (via movsi), then emitting a register indirect call using
6790 ;; the "jsr" function call syntax.
6792 ;; When outputting MIT syntax (e.g. on Suns), we add a bogus extra
6793 ;; operand to the jbsr statement to indicate that this call should
6794 ;; go through the PLT (why? because this is the way that Sun does it).
6796 ;; We have different patterns for PIC calls and non-PIC calls. The
6797 ;; different patterns are only used to choose the right syntax.
6799 ;; The svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it
6800 ;; will create the correct relocation entry (R_68K_PLT32) for `FUNC',
6801 ;; that tells the linker editor to create an entry for `FUNC' in PLT
6802 ;; section at link time. However, all global objects reference are still
6803 ;; done by using `OBJ@GOT'. So, the goal here is to output the function
6804 ;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'.
6805 ;; We need to have a way to differentiate these two different operands.
6807 ;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate
6808 ;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs
6809 ;; to be changed to recognize function calls symbol_ref operand as a valid
6810 ;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will
6811 ;; avoid the compiler to load this symbol_ref operand into a register.
6812 ;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly
6813 ;; since the value is a PC relative offset, not a real address.
6815 ;; All global objects are treated in the similar way as in SUN3. The only
6816 ;; difference is: on m68k svr4, the reference of such global object needs
6817 ;; to end with a suffix "@GOT" so the assembler and linker know to create
6818 ;; an entry for it in GOT (Global Offset Table) section. This is done in
6821 ;; Call subroutine with no return value.
6822 (define_expand "call"
6823 [(call (match_operand:QI 0 "memory_operand" "")
6824 (match_operand:SI 1 "general_operand" ""))]
6825 ;; Operand 1 not really used on the m68000.
6830 if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6831 SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
6834 ;; This is a normal call sequence.
6836 [(call (match_operand:QI 0 "memory_operand" "o")
6837 (match_operand:SI 1 "general_operand" "g"))]
6838 ;; Operand 1 not really used on the m68000.
6842 #if defined (MOTOROLA) && !defined (USE_GAS)
6844 if (GET_CODE (operands[0]) == MEM
6845 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6854 ;; This is a PIC call sequence.
6856 [(call (match_operand:QI 0 "memory_operand" "o")
6857 (match_operand:SI 1 "general_operand" "g"))]
6858 ;; Operand 1 not really used on the m68000.
6862 if (GET_CODE (operands[0]) == MEM
6863 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6865 if (TARGET_PCREL) return \"bsr.l %o0\";
6868 return \"bsr.l %0\";
6871 return \"bsr.l %0@PLTPC\";
6873 return \"bsr %0@PLTPC\";
6878 return \"bsr.l %0\";
6880 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC,
6881 GAS just plain ignores it. FIXME: not anymore, gas doesnt! */
6882 return \"jbsr %0,a1\";
6889 ;; Call subroutine, returning value in operand 0
6890 ;; (which must be a hard register).
6891 ;; See comments before "call" regarding PIC calls.
6892 (define_expand "call_value"
6893 [(set (match_operand 0 "" "")
6894 (call (match_operand:QI 1 "memory_operand" "")
6895 (match_operand:SI 2 "general_operand" "")))]
6896 ;; Operand 2 not really used on the m68000.
6900 if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6901 SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
6904 ;; This is a normal call_value
6906 [(set (match_operand 0 "" "=rf")
6907 (call (match_operand:QI 1 "memory_operand" "o")
6908 (match_operand:SI 2 "general_operand" "g")))]
6909 ;; Operand 2 not really used on the m68000.
6912 #if defined (MOTOROLA) && !defined (USE_GAS)
6914 if (GET_CODE (operands[1]) == MEM
6915 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6924 ;; This is a PIC call_value
6926 [(set (match_operand 0 "" "=rf")
6927 (call (match_operand:QI 1 "memory_operand" "o")
6928 (match_operand:SI 2 "general_operand" "g")))]
6929 ;; Operand 2 not really used on the m68000.
6932 if (GET_CODE (operands[1]) == MEM
6933 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6935 if (TARGET_PCREL) return \"bsr.l %o1\";
6938 return \"bsr.l %1\";
6941 return \"bsr.l %1@PLTPC\";
6943 return \"bsr %1@PLTPC\";
6948 return \"bsr.l %1\";
6950 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC
6951 GAS just plain ignores it. FIXME: Not anymore, gas doesnt! */
6952 return \"jbsr %1,a1\";
6959 ;; Call subroutine returning any type.
6961 (define_expand "untyped_call"
6962 [(parallel [(call (match_operand 0 "" "")
6964 (match_operand 1 "" "")
6965 (match_operand 2 "" "")])]
6966 "NEEDS_UNTYPED_CALL"
6971 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
6973 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6975 rtx set = XVECEXP (operands[2], 0, i);
6976 emit_move_insn (SET_DEST (set), SET_SRC (set));
6979 /* The optimizer does not know that the call sets the function value
6980 registers we stored in the result block. We avoid problems by
6981 claiming that all hard registers are used and clobbered at this
6983 emit_insn (gen_blockage ());
6988 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6989 ;; all of memory. This blocks insns from being moved across this point.
6991 (define_insn "blockage"
6992 [(unspec_volatile [(const_int 0)] 0)]
7001 (define_insn "probe"
7006 operands[0] = gen_rtx_PLUS (SImode, stack_pointer_rtx,
7007 GEN_INT (NEED_PROBE));
7008 return \"tstl %a0\";
7011 ;; Used for frameless functions which save no regs and allocate no locals.
7012 (define_insn "return"
7017 if (current_function_pops_args == 0)
7019 operands[0] = GEN_INT (current_function_pops_args);
7023 (define_insn "indirect_jump"
7024 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
7028 ;; This should not be used unless the add/sub insns can't be.
7031 [(set (match_operand:SI 0 "general_operand" "=a")
7032 (match_operand:QI 1 "address_operand" "p"))]
7037 /* Recognize an insn that refers to a table of offsets. Such an insn will
7038 need to refer to a label on the insn. So output one. Use the
7039 label-number of the table of offsets to generate this label. This code,
7040 and similar code above, assumes that there will be at most one reference
7042 if (GET_CODE (operands[1]) == PLUS
7043 && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
7044 && GET_CODE (XEXP (operands[1], 0)) != PLUS)
7046 rtx labelref = XEXP (operands[1], 1);
7047 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
7049 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
7050 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
7052 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
7053 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
7054 #endif /* not SGS */
7055 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
7056 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
7057 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
7058 #ifdef SGS_SWITCH_TABLES
7059 /* Set flag saying we need to define the symbol
7060 LD%n (with value L%n-LI%n) at the end of the switch table. */
7061 switch_table_difference_label_flag = 1;
7062 #endif /* SGS_SWITCH_TABLES */
7063 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
7065 #endif /* SGS_NO_LI */
7067 return \"lea %a1,%0\";
7070 ;; This is the first machine-dependent peephole optimization.
7071 ;; It is useful when a floating value is returned from a function call
7072 ;; and then is moved into an FP register.
7073 ;; But it is mainly intended to test the support for these optimizations.
7076 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
7077 (set (match_operand:DF 0 "register_operand" "=f")
7078 (match_operand:DF 1 "register_operand" "ad"))]
7079 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
7083 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7084 output_asm_insn (\"move%.l %1,%@\", xoperands);
7085 output_asm_insn (\"move%.l %1,%-\", operands);
7086 return \"fmove%.d %+,%0\";
7090 ;; Optimize a stack-adjust followed by a push of an argument.
7091 ;; This is said to happen frequently with -msoft-float
7092 ;; when there are consecutive library calls.
7095 [(set (reg:SI 15) (plus:SI (reg:SI 15)
7096 (match_operand:SI 0 "const_int_operand" "n")))
7097 (set (match_operand:SF 1 "push_operand" "=m")
7098 (match_operand:SF 2 "general_operand" "rmfF"))]
7099 "INTVAL (operands[0]) >= 4
7100 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
7103 if (INTVAL (operands[0]) > 4)
7106 xoperands[0] = stack_pointer_rtx;
7107 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
7109 if (INTVAL (xoperands[1]) <= 8)
7112 output_asm_insn (\"addq%.w %1,%0\", xoperands);
7114 output_asm_insn (\"addq%.l %1,%0\", xoperands);
7116 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
7118 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
7119 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
7123 if (INTVAL (xoperands[1]) <= 0x7FFF)
7126 output_asm_insn (\"add%.w %1,%0\", xoperands);
7129 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
7131 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
7135 output_asm_insn (\"add%.l %1,%0\", xoperands);
7137 if (FP_REG_P (operands[2]))
7138 return \"fmove%.s %2,%@\";
7139 return \"move%.l %2,%@\";
7142 ;; Speed up stack adjust followed by a fullword fixedpoint push.
7145 [(set (reg:SI 15) (plus:SI (reg:SI 15)
7146 (match_operand:SI 0 "const_int_operand" "n")))
7147 (set (match_operand:SI 1 "push_operand" "=m")
7148 (match_operand:SI 2 "general_operand" "g"))]
7149 "INTVAL (operands[0]) >= 4
7150 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
7153 if (INTVAL (operands[0]) > 4)
7156 xoperands[0] = stack_pointer_rtx;
7157 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
7159 if (INTVAL (xoperands[1]) <= 8)
7162 output_asm_insn (\"addq%.w %1,%0\", xoperands);
7164 output_asm_insn (\"addq%.l %1,%0\", xoperands);
7166 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
7168 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
7169 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
7173 if (INTVAL (xoperands[1]) <= 0x7FFF)
7176 output_asm_insn (\"add%.w %1,%0\", xoperands);
7180 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
7182 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
7187 output_asm_insn (\"add%.l %1,%0\", xoperands);
7189 if (operands[2] == const0_rtx)
7190 return \"clr%.l %@\";
7191 return \"move%.l %2,%@\";
7194 ;; Speed up pushing a single byte but leaving four bytes of space.
7197 [(set (mem:QI (pre_dec:SI (reg:SI 15)))
7198 (match_operand:QI 1 "general_operand" "dami"))
7199 (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))]
7200 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
7205 if (GET_CODE (operands[1]) == REG)
7206 return \"move%.l %1,%-\";
7208 xoperands[1] = operands[1];
7210 = gen_rtx_MEM (QImode,
7211 gen_rtx_PLUS (VOIDmode, stack_pointer_rtx,
7213 xoperands[3] = stack_pointer_rtx;
7215 output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
7217 output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands);
7222 [(set (match_operand:SI 0 "register_operand" "=d")
7224 (set (strict_low_part (subreg:HI (match_dup 0) 0))
7225 (match_operand:HI 1 "general_operand" "rmn"))]
7226 "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
7229 if (GET_CODE (operands[1]) == CONST_INT)
7231 if (operands[1] == const0_rtx
7232 && (DATA_REG_P (operands[0])
7233 || GET_CODE (operands[0]) == MEM)
7234 /* clr insns on 68000 read before writing.
7235 This isn't so on the 68010, but we have no TARGET_68010. */
7236 && ((TARGET_68020 || TARGET_5200)
7237 || !(GET_CODE (operands[0]) == MEM
7238 && MEM_VOLATILE_P (operands[0]))))
7239 return \"clr%.w %0\";
7241 return \"move%.w %1,%0\";
7249 ;; jCC label ; abnormal loop termination
7250 ;; dbra dN, loop ; normal loop termination
7258 ;; Which moves the jCC condition outside the inner loop for free.
7261 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7262 [(cc0) (const_int 0)])
7263 (label_ref (match_operand 2 "" ""))
7268 (ge (plus:HI (match_operand:HI 0 "register_operand" "+d")
7271 (label_ref (match_operand 1 "" ""))
7274 (plus:HI (match_dup 0)
7276 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7280 output_dbcc_and_branch (operands);
7285 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7286 [(cc0) (const_int 0)])
7287 (label_ref (match_operand 2 "" ""))
7292 (ge (plus:SI (match_operand:SI 0 "register_operand" "+d")
7295 (label_ref (match_operand 1 "" ""))
7298 (plus:SI (match_dup 0)
7300 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7304 output_dbcc_and_branch (operands);
7309 ;; FPA multiply and add.
7311 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7312 (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%x,dmF,y")
7313 (match_operand:DF 2 "general_operand" "xH,y,y"))
7314 (match_operand:DF 3 "general_operand" "xH,y,dmF")))]
7317 fpma%.d %1,%w2,%w3,%0
7318 fpma%.d %x1,%x2,%x3,%0
7319 fpma%.d %x1,%x2,%x3,%0")
7322 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7323 (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%x,ydmF,y")
7324 (match_operand:SF 2 "general_operand" "xH,y,ydmF"))
7325 (match_operand:SF 3 "general_operand" "xH,ydmF,ydmF")))]
7328 fpma%.s %1,%w2,%w3,%0
7330 fpma%.s %1,%2,%3,%0")
7332 ;; FPA Multiply and subtract
7334 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7335 (minus:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
7336 (mult:DF (match_operand:DF 2 "general_operand" "%xH,y,y")
7337 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
7340 fpms%.d %3,%w2,%w1,%0
7341 fpms%.d %x3,%2,%x1,%0
7342 fpms%.d %x3,%2,%x1,%0")
7345 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7346 (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
7347 (mult:SF (match_operand:SF 2 "general_operand" "%xH,rmF,y")
7348 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
7351 fpms%.s %3,%w2,%w1,%0
7353 fpms%.s %3,%2,%1,%0")
7356 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7357 (minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
7358 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7359 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7362 fpmr%.d %2,%w1,%w3,%0
7363 fpmr%.d %x2,%1,%x3,%0
7364 fpmr%.d %x2,%1,%x3,%0")
7367 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7368 (minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
7369 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7370 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7373 fpmr%.s %2,%w1,%w3,%0
7374 fpmr%.s %x2,%1,%x3,%0
7375 fpmr%.s %x2,%1,%x3,%0")
7377 ;; FPA Add and multiply
7379 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7380 (mult:DF (plus:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
7381 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7382 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7385 fpam%.d %2,%w1,%w3,%0
7386 fpam%.d %x2,%1,%x3,%0
7387 fpam%.d %x2,%1,%x3,%0")
7390 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7391 (mult:SF (plus:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
7392 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7393 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7396 fpam%.s %2,%w1,%w3,%0
7397 fpam%.s %x2,%1,%x3,%0
7398 fpam%.s %x2,%1,%x3,%0")
7400 ;;FPA Subtract and multiply
7402 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7403 (mult:DF (minus:DF (match_operand:DF 1 "general_operand" "xH,y,y")
7404 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7405 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7408 fpsm%.d %2,%w1,%w3,%0
7409 fpsm%.d %x2,%1,%x3,%0
7410 fpsm%.d %x2,%1,%x3,%0")
7413 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7414 (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
7415 (minus:DF (match_operand:DF 2 "general_operand" "xH,y,y")
7416 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
7419 fpsm%.d %3,%w2,%w1,%0
7420 fpsm%.d %x3,%2,%x1,%0
7421 fpsm%.d %x3,%2,%x1,%0")
7424 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7425 (mult:SF (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,y")
7426 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7427 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7430 fpsm%.s %2,%w1,%w3,%0
7431 fpsm%.s %x2,%1,%x3,%0
7432 fpsm%.s %x2,%1,%x3,%0")
7435 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7436 (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
7437 (minus:SF (match_operand:SF 2 "general_operand" "xH,rmF,y")
7438 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
7441 fpsm%.s %3,%w2,%w1,%0
7442 fpsm%.s %x3,%2,%x1,%0
7443 fpsm%.s %x3,%2,%x1,%0")
7445 (define_expand "tstxf"
7447 (match_operand:XF 0 "nonimmediate_operand" ""))]
7449 "m68k_last_compare_had_fp_operands = 1;")
7453 (match_operand:XF 0 "nonimmediate_operand" "fm"))]
7457 cc_status.flags = CC_IN_68881;
7458 return \"ftst%.x %0\";
7461 (define_expand "cmpxf"
7463 (compare (match_operand:XF 0 "nonimmediate_operand" "")
7464 (match_operand:XF 1 "nonimmediate_operand" "")))]
7466 "m68k_last_compare_had_fp_operands = 1;")
7470 (compare (match_operand:XF 0 "nonimmediate_operand" "f,m")
7471 (match_operand:XF 1 "nonimmediate_operand" "fm,f")))]
7475 cc_status.flags = CC_IN_68881;
7476 #ifdef SGS_CMP_ORDER
7477 if (REG_P (operands[0]))
7479 if (REG_P (operands[1]))
7480 return \"fcmp%.x %0,%1\";
7482 return \"fcmp%.x %0,%f1\";
7484 cc_status.flags |= CC_REVERSED;
7485 return \"fcmp%.x %1,%f0\";
7487 if (REG_P (operands[0]))
7489 if (REG_P (operands[1]))
7490 return \"fcmp%.x %1,%0\";
7492 return \"fcmp%.x %f1,%0\";
7494 cc_status.flags |= CC_REVERSED;
7495 return \"fcmp%.x %f0,%1\";
7499 (define_insn "extendsfxf2"
7500 [(set (match_operand:XF 0 "general_operand" "=fm,f")
7501 (float_extend:XF (match_operand:SF 1 "general_operand" "f,rmF")))]
7505 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7507 if (REGNO (operands[0]) == REGNO (operands[1]))
7509 /* Extending float to double in an fp-reg is a no-op.
7510 NOTICE_UPDATE_CC has already assumed that the
7511 cc will be set. So cancel what it did. */
7512 cc_status = cc_prev_status;
7515 return \"f%$move%.x %1,%0\";
7517 if (FP_REG_P (operands[0]))
7519 if (FP_REG_P (operands[1]))
7520 return \"f%$move%.x %1,%0\";
7521 else if (ADDRESS_REG_P (operands[1]))
7522 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
7523 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
7524 return output_move_const_single (operands);
7525 return \"f%$move%.s %f1,%0\";
7527 return \"fmove%.x %f1,%0\";
7531 (define_insn "extenddfxf2"
7532 [(set (match_operand:XF 0 "general_operand" "=fm,f")
7534 (match_operand:DF 1 "general_operand" "f,rmE")))]
7538 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7540 if (REGNO (operands[0]) == REGNO (operands[1]))
7542 /* Extending float to double in an fp-reg is a no-op.
7543 NOTICE_UPDATE_CC has already assumed that the
7544 cc will be set. So cancel what it did. */
7545 cc_status = cc_prev_status;
7548 return \"fmove%.x %1,%0\";
7550 if (FP_REG_P (operands[0]))
7552 if (REG_P (operands[1]))
7555 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
7556 output_asm_insn (\"move%.l %1,%-\", xoperands);
7557 output_asm_insn (\"move%.l %1,%-\", operands);
7558 return \"f%&move%.d %+,%0\";
7560 if (GET_CODE (operands[1]) == CONST_DOUBLE)
7561 return output_move_const_double (operands);
7562 return \"f%&move%.d %f1,%0\";
7564 return \"fmove%.x %f1,%0\";
7567 (define_insn "truncxfdf2"
7568 [(set (match_operand:DF 0 "general_operand" "=m,!r")
7570 (match_operand:XF 1 "general_operand" "f,f")))]
7574 if (REG_P (operands[0]))
7576 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
7577 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
7578 return \"move%.l %+,%0\";
7580 return \"fmove%.d %f1,%0\";
7583 (define_insn "truncxfsf2"
7584 [(set (match_operand:SF 0 "general_operand" "=dm")
7586 (match_operand:XF 1 "general_operand" "f")))]
7590 (define_insn "floatsixf2"
7591 [(set (match_operand:XF 0 "general_operand" "=f")
7592 (float:XF (match_operand:SI 1 "general_operand" "dmi")))]
7596 (define_insn "floathixf2"
7597 [(set (match_operand:XF 0 "general_operand" "=f")
7598 (float:XF (match_operand:HI 1 "general_operand" "dmn")))]
7602 (define_insn "floatqixf2"
7603 [(set (match_operand:XF 0 "general_operand" "=f")
7604 (float:XF (match_operand:QI 1 "general_operand" "dmn")))]
7608 (define_insn "ftruncxf2"
7609 [(set (match_operand:XF 0 "general_operand" "=f")
7610 (fix:XF (match_operand:XF 1 "general_operand" "fFm")))]
7614 if (FP_REG_P (operands[1]))
7615 return \"fintrz%.x %f1,%0\";
7616 return \"fintrz%.x %f1,%0\";
7619 (define_insn "fixxfqi2"
7620 [(set (match_operand:QI 0 "general_operand" "=dm")
7621 (fix:QI (match_operand:XF 1 "general_operand" "f")))]
7625 (define_insn "fixxfhi2"
7626 [(set (match_operand:HI 0 "general_operand" "=dm")
7627 (fix:HI (match_operand:XF 1 "general_operand" "f")))]
7631 (define_insn "fixxfsi2"
7632 [(set (match_operand:SI 0 "general_operand" "=dm")
7633 (fix:SI (match_operand:XF 1 "general_operand" "f")))]
7638 [(set (match_operand:XF 0 "general_operand" "=f")
7639 (plus:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7640 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7645 [(set (match_operand:XF 0 "general_operand" "=f")
7646 (plus:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7647 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7652 [(set (match_operand:XF 0 "general_operand" "=f")
7653 (plus:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7654 (match_operand:XF 1 "general_operand" "0")))]
7658 (define_insn "addxf3"
7659 [(set (match_operand:XF 0 "general_operand" "=f")
7660 (plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7661 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7665 if (REG_P (operands[2]))
7666 return \"fadd%.x %2,%0\";
7667 return \"fadd%.x %f2,%0\";
7671 [(set (match_operand:XF 0 "general_operand" "=f")
7672 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7673 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7678 [(set (match_operand:XF 0 "general_operand" "=f")
7679 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7680 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7685 [(set (match_operand:XF 0 "general_operand" "=f")
7686 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7687 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7691 (define_insn "subxf3"
7692 [(set (match_operand:XF 0 "general_operand" "=f")
7693 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7694 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7698 if (REG_P (operands[2]))
7699 return \"fsub%.x %2,%0\";
7700 return \"fsub%.x %f2,%0\";
7704 [(set (match_operand:XF 0 "general_operand" "=f")
7705 (mult:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7706 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7711 [(set (match_operand:XF 0 "general_operand" "=f")
7712 (mult:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7713 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7718 [(set (match_operand:XF 0 "general_operand" "=f")
7719 (mult:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7720 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7724 (define_insn "mulxf3"
7725 [(set (match_operand:XF 0 "general_operand" "=f")
7726 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7727 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7731 if (REG_P (operands[2]))
7732 return \"fmul%.x %2,%0\";
7733 return \"fmul%.x %f2,%0\";
7737 [(set (match_operand:XF 0 "general_operand" "=f")
7738 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7739 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7744 [(set (match_operand:XF 0 "general_operand" "=f")
7745 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7746 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7751 [(set (match_operand:XF 0 "general_operand" "=f")
7752 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7753 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7757 (define_insn "divxf3"
7758 [(set (match_operand:XF 0 "general_operand" "=f")
7759 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7760 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7764 if (REG_P (operands[2]))
7765 return \"fdiv%.x %2,%0\";
7766 return \"fdiv%.x %f2,%0\";
7769 (define_expand "negxf2"
7770 [(set (match_operand:XF 0 "general_operand" "")
7771 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7775 /* ??? There isn't an FPA define_insn so we could handle it here too.
7776 For now we don't (paranoia). */
7784 target = operand_subword (operands[0], 0, 1, XFmode);
7785 result = expand_binop (SImode, xor_optab,
7786 operand_subword_force (operands[1], 0, XFmode),
7787 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
7791 if (result != target)
7792 emit_move_insn (result, target);
7794 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7795 operand_subword_force (operands[1], 1, XFmode));
7796 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7797 operand_subword_force (operands[1], 2, XFmode));
7799 insns = get_insns ();
7802 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7807 (define_insn "negxf2_68881"
7808 [(set (match_operand:XF 0 "general_operand" "=f")
7809 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7813 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7814 return \"fneg%.x %1,%0\";
7815 return \"fneg%.x %f1,%0\";
7818 (define_expand "absxf2"
7819 [(set (match_operand:XF 0 "general_operand" "")
7820 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7824 /* ??? There isn't an FPA define_insn so we could handle it here too.
7825 For now we don't (paranoia). */
7833 target = operand_subword (operands[0], 0, 1, XFmode);
7834 result = expand_binop (SImode, and_optab,
7835 operand_subword_force (operands[1], 0, XFmode),
7836 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
7840 if (result != target)
7841 emit_move_insn (result, target);
7843 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7844 operand_subword_force (operands[1], 1, XFmode));
7845 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7846 operand_subword_force (operands[1], 2, XFmode));
7848 insns = get_insns ();
7851 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7856 (define_insn "absxf2_68881"
7857 [(set (match_operand:XF 0 "general_operand" "=f")
7858 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7862 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7863 return \"fabs%.x %1,%0\";
7864 return \"fabs%.x %f1,%0\";
7867 (define_insn "sqrtxf2"
7868 [(set (match_operand:XF 0 "general_operand" "=f")
7869 (sqrt:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7873 (define_insn "sinsf2"
7874 [(set (match_operand:SF 0 "general_operand" "=f")
7875 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 1))]
7876 "TARGET_68881 && flag_fast_math"
7879 if (FP_REG_P (operands[1]))
7880 return \"fsin%.x %1,%0\";
7882 return \"fsin%.s %1,%0\";
7885 (define_insn "sindf2"
7886 [(set (match_operand:DF 0 "general_operand" "=f")
7887 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 1))]
7888 "TARGET_68881 && flag_fast_math"
7891 if (FP_REG_P (operands[1]))
7892 return \"fsin%.x %1,%0\";
7894 return \"fsin%.d %1,%0\";
7897 (define_insn "sinxf2"
7898 [(set (match_operand:XF 0 "general_operand" "=f")
7899 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 1))]
7900 "TARGET_68881 && flag_fast_math"
7903 (define_insn "cossf2"
7904 [(set (match_operand:SF 0 "general_operand" "=f")
7905 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 2))]
7906 "TARGET_68881 && flag_fast_math"
7909 if (FP_REG_P (operands[1]))
7910 return \"fcos%.x %1,%0\";
7912 return \"fcos%.s %1,%0\";
7915 (define_insn "cosdf2"
7916 [(set (match_operand:DF 0 "general_operand" "=f")
7917 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 2))]
7918 "TARGET_68881 && flag_fast_math"
7921 if (FP_REG_P (operands[1]))
7922 return \"fcos%.x %1,%0\";
7924 return \"fcos%.d %1,%0\";
7927 (define_insn "cosxf2"
7928 [(set (match_operand:XF 0 "general_operand" "=f")
7929 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 2))]
7930 "TARGET_68881 && flag_fast_math"