1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 88, 93-98, 1999 Free Software Foundation, Inc.
4 ;; This file is part of GNU CC.
6 ;; GNU CC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GNU CC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GNU CC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
19 ;; Boston, MA 02111-1307, USA.
21 ;;- Information about MCF5200 port.
23 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
24 ;;- 68k ISA. Differences include reduced support for byte and word
25 ;;- operands and the removal of BCD, bitfield, rotate, and integer
26 ;;- divide instructions. The TARGET_5200 flag turns the use of the
27 ;;- removed opcodes and addressing modes off.
31 ;;- instruction definitions
33 ;;- @@The original PO technology requires these to be ordered by speed,
34 ;;- @@ so that assigner will pick the fastest.
36 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
38 ;;- When naming insn's (operand 0 of define_insn) be careful about using
39 ;;- names from other targets machine descriptions.
41 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
42 ;;- updates for most instructions.
44 ;;- Operand classes for the register allocator:
45 ;;- 'a' one of the address registers can be used.
46 ;;- 'd' one of the data registers can be used.
47 ;;- 'f' one of the m68881 registers can be used
48 ;;- 'r' either a data or an address register can be used.
49 ;;- 'x' if one of the Sun FPA registers
50 ;;- 'y' if one of the Low Sun FPA registers (fpa0-fpa15).
52 ;;- Immediate Floating point operator constraints
53 ;;- 'G' a floating point constant that is *NOT* one of the standard
54 ;; 68881 constant values (to force calling output_move_const_double
55 ;; to get it from rom if it is a 68881 constant).
56 ;;- 'H' one of the standard FPA constant values
58 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
61 ;;- Immediate integer operand constraints:
63 ;;- 'J' -32768 .. 32767
64 ;;- 'K' all integers EXCEPT -128 .. 127
66 ;;- 'M' all integers EXCEPT -256 .. 255
72 ;;- "%." size separator ("." or "") move%.l d0,d1
73 ;;- "%#" immediate separator ("#" or "") move%.l %#0,d0
74 ;;- "%-" push operand "sp@-" move%.l d0,%-
75 ;;- "%+" pop operand "sp@+" move%.l d0,%+
76 ;;- "%@" top of stack "sp@" move%.l d0,%@
77 ;;- "%!" fpcr register
78 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
79 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
82 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
83 ;; operand 1 is the argument for `sin'.
84 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
85 ;; operand 1 is the argument for `cos'.
87 ;;- Information about 68040 port.
89 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
90 ;;- be emulated in software by the OS. It is faster to avoid these
91 ;;- instructions and issue a library call rather than trapping into
92 ;;- the kernel. The affected instructions are fintrz and fscale. The
93 ;;- TARGET_68040 flag turns the use of the opcodes off.
95 ;;- The '040 also implements a set of new floating-point instructions
96 ;;- which specify the rounding precision in the opcode. This finally
97 ;;- permit the 68k series to be truly IEEE compliant, and solves all
98 ;;- issues of excess precision accumulating in the extended registers.
99 ;;- By default, GCC does not use these instructions, since such code will
100 ;;- not run on an '030. To use these instructions, use the -m68040-only
101 ;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY,
102 ;;- you can make these instructions the default.
104 ;;- These new instructions aren't directly in the md. They are brought
105 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
108 ;;- Information about 68060 port.
110 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
111 ;;- be emulated in software by the OS. It is faster to avoid these
112 ;;- instructions and issue a library call rather than trapping into
113 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
114 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
115 ;;- fscale. The TARGET_68060 flag turns the use of the opcodes off.
117 ;;- FPA port explanation:
119 ;;- Usage of the Sun FPA and the 68881 together
121 ;;- The current port of gcc to the sun fpa disallows use of the m68881
122 ;;- instructions completely if code is targeted for the fpa. This is
123 ;;- for the following reasons:
125 ;;- 1) Expressing the preference hierarchy (ie. use the fpa if you
126 ;;- can, the 68881 otherwise, and data registers only if you are
127 ;;- forced to it) is a bitch with the current constraint scheme,
128 ;;- especially since it would have to work for any combination of
131 ;;- 2) There are no instructions to move between the two types of
132 ;;- registers; the stack must be used as an intermediary.
134 ;;- It could indeed be done; I think the best way would be to have
135 ;;- separate patterns for TARGET_FPA (which implies a 68881),
136 ;;- TARGET_68881, and no floating point co-processor. Use
137 ;;- define_expands for all of the named instruction patterns, and
138 ;;- include code in the FPA instruction to deal with the 68881 with
139 ;;- preferences specifically set to favor the fpa. Some of this has
140 ;;- already been done:
142 ;;- 1) Separation of most of the patterns out into a TARGET_FPA
143 ;;- case and a TARGET_68881 case (the exceptions are the patterns
144 ;;- which would need one define_expand and three define_insn's under
145 ;;- it (with a lot of duplicate code between them) to replace the
146 ;;- current single define_insn. These are mov{[ds]f,[ds]i} and the
147 ;;- first two patterns in the md.
149 ;;- Some would still have to be done:
151 ;;- 1) Add code to the fpa patterns which correspond to 68881
152 ;;- patterns to deal with the 68881 case (including preferences!).
153 ;;- What you might actually do here is combine the fpa and 68881 code
154 ;;- back together into one pattern for those instructions where it's
155 ;;- absolutely necessary and save yourself some duplicate code. I'm
156 ;;- not completely sure as to whether you could get away with doing
157 ;;- this only for the mov* insns, or if you'd have to do it for all
159 ;;- 2) Add code to the mov{[ds]f,[ds]i} instructions to handle
160 ;;- moving between fpa regs and 68881 regs.
162 ;;- Since the fpa is more powerful than the 68881 and also has more
163 ;;- registers, and since I think the resultant md would be medium ugly
164 ;;- (lot's of duplicate code, ugly constraint strings), I elected not
165 ;;- to do this change.
167 ;;- Another reason why someone *might* want to do the change is to
168 ;;- control which register classes are accessed in a slightly cleaner
169 ;;- way than I have. See the blurb on CONDITIONAL_REGISTER_USAGE in
170 ;;- the internals manual.
172 ;;- Yet another reason why someone might want to do this change is to
173 ;;- allow use of some of the 68881 insns which have no equivalent on
174 ;;- the fpa. The sqrt instruction comes fairly quickly to mind.
176 ;;- If this is ever done, don't forget to change sun3.h so that
177 ;;- it *will* define __HAVE_68881__ when the FPA is in use.
179 ;;- Condition code hack
181 ;;- When a floating point compare is done in the fpa, the resulting
182 ;;- condition codes are left in the fpastatus register. The values in
183 ;;- this register must be moved into the 68000 cc register before any
184 ;;- jump is executed. Once this has been done, regular jump
185 ;;- instructions are fine (ie. floating point jumps are not necessary.
186 ;;- They are only done if the cc is in the 68881).
188 ;;- The instructions that move the fpastatus register to the 68000
189 ;;- register clobber a data register (the move cannot be done direct).
190 ;;- These instructions might be bundled either with the compare
191 ;;- instruction, or the branch instruction. If we were using both the
192 ;;- fpa and the 68881 together, we would wish to only mark the
193 ;;- register clobbered if we were doing the compare in the fpa, but I
194 ;;- think that that decision (whether to clobber the register or not)
195 ;;- must be done before register allocation (makes sense) and hence we
196 ;;- can't know if the floating point compare will be done in the fpa
197 ;;- or the fp. So whenever we are asked for code that uses the fpa,
198 ;;- we will mark a data register as clobbered. This is reasonable, as
199 ;;- almost all floating point compare operations done with fpa code
200 ;;- enabled will be done in the fpa. It's even more reasonable since
201 ;;- we decided to make the 68881 and the fpa mutually exclusive.
203 ;;- We place to code to move the fpastatus register inside of a
204 ;;- define_expand so that we can do it conditionally based on whether
205 ;;- we are targeting an fpa or not.
207 ;;- This still leaves us with the question of where we wish to put the
208 ;;- code to move the fpastatus reg. If we put it in the compare
209 ;;- instruction, we can restrict the clobbering of the register to
210 ;;- floating point compares, but we can't take advantage of floating
211 ;;- point subtracts & etc. that alter the fpastatus register. If we
212 ;;- put it in the branch instruction, all branches compiled with fpa
213 ;;- code enabled will clobber a data register, but we will be able to
214 ;;- take advantage of fpa subtracts. This balance favors putting the
215 ;;- code in with the compare instruction.
217 ;;- Note that if some enterprising hacker should decide to switch
218 ;;- this, he'll need to modify the code in NOTICE_UPDATE_CC.
220 ;;- Usage of the top 16 fpa registers
222 ;;- The only locations which we may transfer fpa registers 16-31 from
223 ;;- or to are the fpa registers 0-15. (68000 registers and memory
224 ;;- locations are impossible). This causes problems in gcc, which
225 ;;- assumes that mov?? instructions require no additional registers
226 ;;- (see section 11.7) and since floating point moves *must* be
227 ;;- supported into general registers (see section 12.3 under
228 ;;- HARD_REGNO_OK_FOR_MODE_P) from anywhere.
230 ;;- My solution was to reserve fpa0 for moves into or out of these top
231 ;;- 16 registers and to disparage the choice to reload into or out of
232 ;;- these registers as much as I could. That alternative is always
233 ;;- last in the list, so it will not be used unless all else fails. I
234 ;;- will note that according to my current information, sun's compiler
235 ;;- doesn't use these top 16 registers at all.
237 ;;- There is another possible way to do it. I *believe* that if you
238 ;;- make absolutely sure that the code will not be executed in the
239 ;;- reload pass, you can support the mov?? names with define_expands
240 ;;- which require new registers. This may be possible by the
241 ;;- appropriate juggling of constraints. I may come back to this later.
243 ;;- Usage of constant RAM
245 ;;- This has been handled correctly (I believe) but the way I've done
246 ;;- it could use a little explanation. The constant RAM can only be
247 ;;- accessed when the instruction is in "command register" mode.
248 ;;- "command register" mode means that no accessing of memory or the
249 ;;- 68000 registers is being done. This can be expressed easily in
250 ;;- constraints, so generally the mode of the instruction is
251 ;;- determined by a branch off of which_alternative. In outputting
252 ;;- instructions, a 'w' means to output an access to the constant ram
253 ;;- (if the arg is CONST_DOUBLE and is one of the available
254 ;;- constants), and 'x' means to output a register pair (if the arg is
255 ;;- a 68000 register) and a 'y' is the combination of the above two
256 ;;- processes. You use a 'y' in two operand DF instructions where you
257 ;;- *know* the other operand is an fpa register, you use an 'x' in DF
258 ;;- instructions where the arg might be a 68000 register and the
259 ;;- instruction is *not* in "command register" mode, and you use a 'w'
260 ;;- in two situations: 1) The instruction *is* in command register
261 ;;- mode (and hence won't be accessing 68000 registers), or 2) The
262 ;;- instruction is a two operand SF instruction where you know the
263 ;;- other operand is an fpa register.
265 ;;- Optimization issues
267 ;;- I actually think that I've included all of the fpa instructions
268 ;;- that should be included. Note that if someone is interested in
269 ;;- doing serious floating point work on the sun fpa, I would advise
270 ;;- the use of the "asm" instruction in gcc to allow you to use the
271 ;;- sin, cos, and exponential functions on the fpa board.
273 ;;- END FPA Explanation Section.
276 ;;- Some of these insn's are composites of several m68000 op codes.
277 ;;- The assembler (or final @@??) insures that the appropriate one is
281 [(set (match_operand:DF 0 "push_operand" "=m")
282 (match_operand:DF 1 "general_operand" "ro<>fyE"))]
286 if (FP_REG_P (operands[1]))
287 return \"fmove%.d %f1,%0\";
288 if (FPA_REG_P (operands[1]))
289 return \"fpmove%.d %1, %x0\";
290 return output_move_double (operands);
293 (define_insn "pushdi"
294 [(set (match_operand:DI 0 "push_operand" "=m")
295 (match_operand:DI 1 "general_operand" "ro<>Fyi"))]
299 return output_move_double (operands);
302 ;; We don't want to allow a constant operand for test insns because
303 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
304 ;; be folded while optimizing anyway.
306 (define_expand "tstdi"
307 [(parallel [(set (cc0)
308 (match_operand:DI 0 "nonimmediate_operand" ""))
309 (clobber (match_scratch:SI 1 ""))
310 (clobber (match_scratch:DI 2 ""))])]
312 "m68k_last_compare_had_fp_operands = 0;")
316 (match_operand:DI 0 "nonimmediate_operand" "am,d"))
317 (clobber (match_scratch:SI 1 "=X,d"))
318 (clobber (match_scratch:DI 2 "=d,X"))]
322 if (which_alternative == 0)
326 xoperands[0] = operands[2];
327 xoperands[1] = operands[0];
328 output_move_double (xoperands);
329 cc_status.flags |= CC_REVERSED;
330 return \"neg%.l %R2\;negx%.l %2\";
332 if (find_reg_note (insn, REG_DEAD, operands[0]))
334 cc_status.flags |= CC_REVERSED;
335 return \"neg%.l %R0\;negx%.l %0\";
339 ** 'sub' clears %1, and also clears the X cc bit
340 ** 'tst' sets the Z cc bit according to the low part of the DImode operand
341 ** 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part
343 return \"sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0\";
346 (define_expand "tstsi"
348 (match_operand:SI 0 "nonimmediate_operand" ""))]
350 "m68k_last_compare_had_fp_operands = 0;")
354 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
359 /* ISI's assembler fails to handle tstl a0. */
360 if (! ADDRESS_REG_P (operands[0]))
362 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
364 return \"tst%.l %0\";
365 /* If you think that the 68020 does not support tstl a0,
366 reread page B-167 of the 68020 manual more carefully. */
367 /* On an address reg, cmpw may replace cmpl. */
369 return \"cmp%.w %0,%#0\";
371 return \"cmp%.w %#0,%0\";
375 ;; This can't use an address register, because comparisons
376 ;; with address registers as second operand always test the whole word.
377 (define_expand "tsthi"
379 (match_operand:HI 0 "nonimmediate_operand" ""))]
381 "m68k_last_compare_had_fp_operands = 0;")
385 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
389 (define_expand "tstqi"
391 (match_operand:QI 0 "nonimmediate_operand" ""))]
393 "m68k_last_compare_had_fp_operands = 0;")
397 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
401 (define_expand "tstsf"
403 (match_operand:SF 0 "general_operand" ""))]
404 "TARGET_68881 || TARGET_FPA"
407 m68k_last_compare_had_fp_operands = 1;
410 emit_insn (gen_tstsf_fpa (operands[0]));
415 (define_insn "tstsf_fpa"
417 (match_operand:SF 0 "general_operand" "xmdF"))
418 (clobber (match_scratch:SI 1 "=d"))]
420 "fptst%.s %x0\;fpmove fpastatus,%1\;movw %1,cc")
424 (match_operand:SF 0 "general_operand" "fdm"))]
428 cc_status.flags = CC_IN_68881;
429 if (FP_REG_P (operands[0]))
430 return \"ftst%.x %0\";
431 return \"ftst%.s %0\";
434 (define_expand "tstdf"
436 (match_operand:DF 0 "general_operand" ""))]
437 "TARGET_68881 || TARGET_FPA"
440 m68k_last_compare_had_fp_operands = 1;
443 emit_insn (gen_tstsf_fpa (operands[0]));
448 (define_insn "tstdf_fpa"
450 (match_operand:DF 0 "general_operand" "xrmF"))
451 (clobber (match_scratch:SI 1 "=d"))]
453 "fptst%.d %x0\;fpmove fpastatus,%1\;movw %1,cc")
457 (match_operand:DF 0 "general_operand" "fm"))]
461 cc_status.flags = CC_IN_68881;
462 if (FP_REG_P (operands[0]))
463 return \"ftst%.x %0\";
464 return \"ftst%.d %0\";
467 ;; compare instructions.
469 (define_expand "cmpdi"
472 (compare (match_operand:DI 0 "nonimmediate_operand" "")
473 (match_operand:DI 1 "general_operand" "")))
474 (clobber (match_dup 2))])]
476 "m68k_last_compare_had_fp_operands = 0; operands[2] = gen_reg_rtx (DImode);")
480 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
481 (match_operand:DI 2 "general_operand" "d,0")))
482 (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
486 if (rtx_equal_p (operands[0], operands[1]))
487 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
490 cc_status.flags |= CC_REVERSED;
491 return \"sub%.l %R1,%R0\;subx%.l %1,%0\";
495 ;; This is the second "hook" for PIC code (in addition to movsi). See
496 ;; comment of movsi for a description of PIC handling.
497 (define_expand "cmpsi"
499 (compare (match_operand:SI 0 "nonimmediate_operand" "")
500 (match_operand:SI 1 "general_operand" "")))]
504 m68k_last_compare_had_fp_operands = 0;
505 if (flag_pic && symbolic_operand (operands[1], SImode))
507 /* The source is an address which requires PIC relocation.
508 Call legitimize_pic_address with the source, mode, and a relocation
509 register (a new pseudo, or the final destination if reload_in_progress
510 is set). Then fall through normally */
511 extern rtx legitimize_pic_address();
512 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
513 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
517 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
520 (compare (match_operand:SI 0 "nonimmediate_operand" "rKs,mr,>")
521 (match_operand:SI 1 "general_operand" "mr,rKs,>")))]
525 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
527 return \"cmpm%.l %0,%1\";
529 return \"cmpm%.l %1,%0\";
531 if (REG_P (operands[1])
532 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
533 { cc_status.flags |= CC_REVERSED;
535 return \"cmp%.l %d1,%d0\";
537 return \"cmp%.l %d0,%d1\";
541 return \"cmp%.l %d0,%d1\";
543 return \"cmp%.l %d1,%d0\";
549 (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
550 (match_operand:SI 1 "general_operand" "r,mrKs")))]
554 if (REG_P (operands[1])
555 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
556 { cc_status.flags |= CC_REVERSED;
558 return \"cmp%.l %d1,%d0\";
560 return \"cmp%.l %d0,%d1\";
564 return \"cmp%.l %d0,%d1\";
566 return \"cmp%.l %d1,%d0\";
570 (define_expand "cmphi"
572 (compare (match_operand:HI 0 "nonimmediate_operand" "")
573 (match_operand:HI 1 "general_operand" "")))]
575 "m68k_last_compare_had_fp_operands = 0;")
579 (compare (match_operand:HI 0 "nonimmediate_operand" "rnm,d,n,m,>")
580 (match_operand:HI 1 "general_operand" "d,rnm,m,n,>")))]
584 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
586 return \"cmpm%.w %0,%1\";
588 return \"cmpm%.w %1,%0\";
590 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
591 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
592 { cc_status.flags |= CC_REVERSED;
594 return \"cmp%.w %d1,%d0\";
596 return \"cmp%.w %d0,%d1\";
600 return \"cmp%.w %d0,%d1\";
602 return \"cmp%.w %d1,%d0\";
606 (define_expand "cmpqi"
608 (compare (match_operand:QI 0 "nonimmediate_operand" "")
609 (match_operand:QI 1 "general_operand" "")))]
611 "m68k_last_compare_had_fp_operands = 0;")
615 (compare (match_operand:QI 0 "nonimmediate_operand" "dn,md,>")
616 (match_operand:QI 1 "general_operand" "dm,nd,>")))]
620 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
622 return \"cmpm%.b %0,%1\";
624 return \"cmpm%.b %1,%0\";
626 if (REG_P (operands[1])
627 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
628 { cc_status.flags |= CC_REVERSED;
630 return \"cmp%.b %d1,%d0\";
632 return \"cmp%.b %d0,%d1\";
636 return \"cmp%.b %d0,%d1\";
638 return \"cmp%.b %d1,%d0\";
642 (define_expand "cmpdf"
644 (compare (match_operand:DF 0 "general_operand" "")
645 (match_operand:DF 1 "general_operand" "")))]
646 "TARGET_68881 || TARGET_FPA"
649 m68k_last_compare_had_fp_operands = 1;
652 emit_insn (gen_cmpdf_fpa (operands[0], operands[1]));
657 (define_insn "cmpdf_fpa"
659 (compare (match_operand:DF 0 "general_operand" "x,y")
660 (match_operand:DF 1 "general_operand" "xH,rmF")))
661 (clobber (match_scratch:SI 2 "=d,d"))]
663 "fpcmp%.d %y1,%0\;fpmove fpastatus,%2\;movw %2,cc")
667 (compare (match_operand:DF 0 "general_operand" "f,mG")
668 (match_operand:DF 1 "general_operand" "fmG,f")))]
672 cc_status.flags = CC_IN_68881;
674 if (REG_P (operands[0]))
676 if (REG_P (operands[1]))
677 return \"fcmp%.x %0,%1\";
679 return \"fcmp%.d %0,%f1\";
681 cc_status.flags |= CC_REVERSED;
682 return \"fcmp%.d %1,%f0\";
684 if (REG_P (operands[0]))
686 if (REG_P (operands[1]))
687 return \"fcmp%.x %1,%0\";
689 return \"fcmp%.d %f1,%0\";
691 cc_status.flags |= CC_REVERSED;
692 return \"fcmp%.d %f0,%1\";
696 (define_expand "cmpsf"
698 (compare (match_operand:SF 0 "general_operand" "")
699 (match_operand:SF 1 "general_operand" "")))]
700 "TARGET_68881 || TARGET_FPA"
703 m68k_last_compare_had_fp_operands = 1;
706 emit_insn (gen_cmpsf_fpa (operands[0], operands[1]));
711 (define_insn "cmpsf_fpa"
713 (compare (match_operand:SF 0 "general_operand" "x,y")
714 (match_operand:SF 1 "general_operand" "xH,rmF")))
715 (clobber (match_scratch:SI 2 "=d,d"))]
717 "fpcmp%.s %w1,%x0\;fpmove fpastatus,%2\;movw %2,cc")
721 (compare (match_operand:SF 0 "general_operand" "f,mdG")
722 (match_operand:SF 1 "general_operand" "fmdG,f")))]
726 cc_status.flags = CC_IN_68881;
728 if (FP_REG_P (operands[0]))
730 if (FP_REG_P (operands[1]))
731 return \"fcmp%.x %0,%1\";
733 return \"fcmp%.s %0,%f1\";
735 cc_status.flags |= CC_REVERSED;
736 return \"fcmp%.s %1,%f0\";
738 if (FP_REG_P (operands[0]))
740 if (FP_REG_P (operands[1]))
741 return \"fcmp%.x %1,%0\";
743 return \"fcmp%.s %f1,%0\";
745 cc_status.flags |= CC_REVERSED;
746 return \"fcmp%.s %f0,%1\";
750 ;; Recognizers for btst instructions.
752 ;; Coldfire/5200 only allows "<Q>" type addresses when the bit position is
753 ;; specified as a constant, so we must disable all patterns that may extract
754 ;; from a MEM at a constant bit position if we can't use this as a constraint.
757 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
759 (minus:SI (const_int 7)
760 (match_operand:SI 1 "general_operand" "di"))))]
762 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
764 ;; This is the same as the above pattern except for the constraints. The 'i'
768 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
770 (minus:SI (const_int 7)
771 (match_operand:SI 1 "general_operand" "d"))))]
773 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
776 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
778 (minus:SI (const_int 31)
779 (match_operand:SI 1 "general_operand" "di"))))]
781 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
783 ;; The following two patterns are like the previous two
784 ;; except that they use the fact that bit-number operands
785 ;; are automatically masked to 3 or 5 bits.
788 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
790 (minus:SI (const_int 7)
792 (match_operand:SI 1 "register_operand" "d")
795 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
798 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
800 (minus:SI (const_int 31)
802 (match_operand:SI 1 "register_operand" "d")
805 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
807 ;; Nonoffsettable mem refs are ok in this one pattern
808 ;; since we don't try to adjust them.
810 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
812 (match_operand:SI 1 "const_int_operand" "n")))]
813 "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_5200"
816 operands[1] = GEN_INT (7 - INTVAL (operands[1]));
817 return output_btst (operands, operands[1], operands[0], insn, 7);
821 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
823 (match_operand:SI 1 "const_int_operand" "n")))]
827 if (GET_CODE (operands[0]) == MEM)
829 operands[0] = adj_offsettable_operand (operands[0],
830 INTVAL (operands[1]) / 8);
831 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
832 return output_btst (operands, operands[1], operands[0], insn, 7);
834 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
835 return output_btst (operands, operands[1], operands[0], insn, 31);
838 ;; This is the same as the above pattern except for the constraints.
839 ;; The 'o' has been replaced with 'Q'.
842 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ")
844 (match_operand:SI 1 "const_int_operand" "n")))]
848 if (GET_CODE (operands[0]) == MEM)
850 operands[0] = adj_offsettable_operand (operands[0],
851 INTVAL (operands[1]) / 8);
852 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
853 return output_btst (operands, operands[1], operands[0], insn, 7);
855 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
856 return output_btst (operands, operands[1], operands[0], insn, 31);
862 ;; A special case in which it is not desirable
863 ;; to reload the constant into a data register.
864 (define_insn "pushexthisi_const"
865 [(set (match_operand:SI 0 "push_operand" "=m")
866 (match_operand:SI 1 "const_int_operand" "J"))]
867 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
870 if (operands[1] == const0_rtx)
871 return \"clr%.l %0\";
876 ;(define_insn "swapsi"
877 ; [(set (match_operand:SI 0 "general_operand" "+r")
878 ; (match_operand:SI 1 "general_operand" "+r"))
879 ; (set (match_dup 1) (match_dup 0))]
883 ;; Special case of fullword move when source is zero.
884 ;; The reason this is special is to avoid loading a zero
885 ;; into a data reg with moveq in order to store it elsewhere.
887 (define_insn "movsi_const0"
888 [(set (match_operand:SI 0 "general_operand" "=g")
890 ;; clr insns on 68000 read before writing.
891 ;; This isn't so on the 68010, but we have no TARGET_68010.
892 "((TARGET_68020 || TARGET_5200)
893 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
896 if (ADDRESS_REG_P (operands[0]))
898 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
899 if (!TARGET_68040 && !TARGET_68060)
900 return \"sub%.l %0,%0\";
905 /* Many SGS assemblers croak on size specifiers for constants. */
908 return \"lea 0.w,%0\";
911 return \"lea 0:w,%0\";
915 /* moveq is faster on the 68000. */
916 if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_5200))
917 #if defined(MOTOROLA) && !defined(CRDS)
918 return \"moveq%.l %#0,%0\";
920 return \"moveq %#0,%0\";
922 return \"clr%.l %0\";
925 ;; General case of fullword move.
927 ;; This is the main "hook" for PIC code. When generating
928 ;; PIC, movsi is responsible for determining when the source address
929 ;; needs PIC relocation and appropriately calling legitimize_pic_address
930 ;; to perform the actual relocation.
932 ;; In both the PIC and non-PIC cases the patterns generated will
933 ;; matched by the next define_insn.
934 (define_expand "movsi"
935 [(set (match_operand:SI 0 "general_operand" "")
936 (match_operand:SI 1 "general_operand" ""))]
940 if (flag_pic && symbolic_operand (operands[1], SImode))
942 /* The source is an address which requires PIC relocation.
943 Call legitimize_pic_address with the source, mode, and a relocation
944 register (a new pseudo, or the final destination if reload_in_progress
945 is set). Then fall through normally */
946 extern rtx legitimize_pic_address();
947 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
948 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
952 ;; General case of fullword move. The register constraints
953 ;; force integer constants in range for a moveq to be reloaded
954 ;; if they are headed for memory.
956 ;; Notes: make sure no alternative allows g vs g.
957 ;; We don't allow f-regs since fixed point cannot go in them.
958 ;; We do allow y and x regs since fixed point is allowed in them.
959 [(set (match_operand:SI 0 "general_operand" "=g,da,y,!*x*r*m")
960 (match_operand:SI 1 "general_operand" "daymKs,i,g,*x*r*m"))]
964 if (which_alternative == 3)
965 return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\";
966 if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0]))
967 return \"fpmove%.l %x1,%x0\";
968 return output_move_simode (operands);
972 [(set (match_operand:SI 0 "general_operand" "=r<Q>,g")
973 (match_operand:SI 1 "general_operand" "g,r<Q>"))]
975 "* return output_move_simode (operands);")
977 (define_expand "movhi"
978 [(set (match_operand:HI 0 "general_operand" "")
979 (match_operand:HI 1 "general_operand" ""))]
984 [(set (match_operand:HI 0 "general_operand" "=g")
985 (match_operand:HI 1 "general_operand" "g"))]
987 "* return output_move_himode (operands);")
990 [(set (match_operand:HI 0 "general_operand" "=r<Q>,g")
991 (match_operand:HI 1 "general_operand" "g,r<Q>"))]
993 "* return output_move_himode (operands);")
995 (define_expand "movstricthi"
996 [(set (strict_low_part (match_operand:HI 0 "general_operand" ""))
997 (match_operand:HI 1 "general_operand" ""))]
1002 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
1003 (match_operand:HI 1 "general_operand" "rmn"))]
1005 "* return output_move_stricthi (operands);")
1008 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+d,m"))
1009 (match_operand:HI 1 "general_operand" "rmn,r"))]
1011 "* return output_move_stricthi (operands);")
1013 (define_expand "movqi"
1014 [(set (match_operand:QI 0 "general_operand" "")
1015 (match_operand:QI 1 "general_operand" ""))]
1020 [(set (match_operand:QI 0 "general_operand" "=d,*a,m")
1021 (match_operand:QI 1 "general_operand" "dmi*a,di*a,dmi"))]
1023 "* return output_move_qimode (operands);")
1026 [(set (match_operand:QI 0 "general_operand" "=d<Q>,dm,d*a")
1027 (match_operand:QI 1 "general_operand" "dmi,d<Q>,di*a"))]
1029 "* return output_move_qimode (operands);")
1031 (define_expand "movstrictqi"
1032 [(set (strict_low_part (match_operand:QI 0 "general_operand" ""))
1033 (match_operand:QI 1 "general_operand" ""))]
1038 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
1039 (match_operand:QI 1 "general_operand" "dmn"))]
1041 "* return output_move_strictqi (operands);")
1044 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+d,m"))
1045 (match_operand:QI 1 "general_operand" "dmn,d"))]
1047 "* return output_move_strictqi (operands);")
1049 (define_expand "movsf"
1050 [(set (match_operand:SF 0 "general_operand" "")
1051 (match_operand:SF 1 "general_operand" ""))]
1056 [(set (match_operand:SF 0 "general_operand" "=rmf,x,y,rm,!x,!rm")
1057 (match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))]
1058 ; [(set (match_operand:SF 0 "general_operand" "=rmf")
1059 ; (match_operand:SF 1 "general_operand" "rmfF"))]
1063 if (which_alternative >= 4)
1064 return \"fpmove%.s %1,fpa0\;fpmove%.s fpa0,%0\";
1065 if (FPA_REG_P (operands[0]))
1067 if (FPA_REG_P (operands[1]))
1068 return \"fpmove%.s %x1,%x0\";
1069 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1070 return output_move_const_single (operands);
1071 else if (FP_REG_P (operands[1]))
1072 return \"fmove%.s %1,sp@-\;fpmove%.d sp@+, %0\";
1073 return \"fpmove%.s %x1,%x0\";
1075 if (FPA_REG_P (operands[1]))
1077 if (FP_REG_P (operands[0]))
1078 return \"fpmove%.s %x1,sp@-\;fmove%.s sp@+,%0\";
1080 return \"fpmove%.s %x1,%x0\";
1082 if (FP_REG_P (operands[0]))
1084 if (FP_REG_P (operands[1]))
1085 return \"f%$move%.x %1,%0\";
1086 else if (ADDRESS_REG_P (operands[1]))
1087 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
1088 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1089 return output_move_const_single (operands);
1090 return \"f%$move%.s %f1,%0\";
1092 if (FP_REG_P (operands[1]))
1094 if (ADDRESS_REG_P (operands[0]))
1095 return \"fmove%.s %1,%-\;move%.l %+,%0\";
1096 return \"fmove%.s %f1,%0\";
1098 if (operands[1] == CONST0_RTX (SFmode)
1099 /* clr insns on 68000 read before writing.
1100 This isn't so on the 68010, but we have no TARGET_68010. */
1101 && ((TARGET_68020 || TARGET_5200)
1102 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1104 if (ADDRESS_REG_P (operands[0]))
1106 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
1107 if (!TARGET_68040 && !TARGET_68060)
1108 return \"sub%.l %0,%0\";
1113 /* Many SGS assemblers croak on size specifiers for constants. */
1114 return \"lea 0,%0\";
1116 return \"lea 0.w,%0\";
1119 return \"lea 0:w,%0\";
1123 /* moveq is faster on the 68000. */
1124 if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_5200))
1126 #if defined(MOTOROLA) && !defined(CRDS)
1127 return \"moveq%.l %#0,%0\";
1129 return \"moveq %#0,%0\";
1132 return \"clr%.l %0\";
1134 return \"move%.l %1,%0\";
1138 [(set (match_operand:SF 0 "general_operand" "=r,g")
1139 (match_operand:SF 1 "general_operand" "g,r"))]
1141 "* return \"move%.l %1,%0\";")
1143 (define_expand "movdf"
1144 [(set (match_operand:DF 0 "general_operand" "")
1145 (match_operand:DF 1 "general_operand" ""))]
1150 [(set (match_operand:DF 0 "general_operand"
1151 "=*rm,*rf,*rf,&*rof<>,y,*rm,x,!x,!*rm")
1152 (match_operand:DF 1 "general_operand"
1153 "*rf,m,0,*rofE<>,*rmE,y,xH,*rm,x"))]
1154 ; [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>")
1155 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
1159 if (which_alternative == 7)
1160 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1161 if (FPA_REG_P (operands[0]))
1163 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1164 return output_move_const_double (operands);
1165 if (FP_REG_P (operands[1]))
1166 return \"fmove%.d %1,sp@-\;fpmove%.d sp@+,%x0\";
1167 return \"fpmove%.d %x1,%x0\";
1169 else if (FPA_REG_P (operands[1]))
1171 if (FP_REG_P(operands[0]))
1172 return \"fpmove%.d %x1,sp@-\;fmoved sp@+,%0\";
1174 return \"fpmove%.d %x1,%x0\";
1176 if (FP_REG_P (operands[0]))
1178 if (FP_REG_P (operands[1]))
1179 return \"f%&move%.x %1,%0\";
1180 if (REG_P (operands[1]))
1183 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1184 output_asm_insn (\"move%.l %1,%-\", xoperands);
1185 output_asm_insn (\"move%.l %1,%-\", operands);
1186 return \"f%&move%.d %+,%0\";
1188 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1189 return output_move_const_double (operands);
1190 return \"f%&move%.d %f1,%0\";
1192 else if (FP_REG_P (operands[1]))
1194 if (REG_P (operands[0]))
1196 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1197 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1198 return \"move%.l %+,%0\";
1201 return \"fmove%.d %f1,%0\";
1203 return output_move_double (operands);
1207 [(set (match_operand:DF 0 "general_operand" "=r,g")
1208 (match_operand:DF 1 "general_operand" "g,r"))]
1210 "* return output_move_double (operands);")
1212 (define_expand "movxf"
1213 [(set (match_operand:XF 0 "nonimmediate_operand" "")
1214 (match_operand:XF 1 "general_operand" ""))]
1218 if (CONSTANT_P (operands[1]))
1220 operands[1] = force_const_mem (XFmode, operands[1]);
1221 if (! memory_address_p (XFmode, XEXP (operands[1], 0))
1222 && ! reload_in_progress)
1223 operands[1] = change_address (operands[1], XFmode,
1224 XEXP (operands[1], 0));
1229 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f,!r")
1230 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r,!r"))]
1234 if (FP_REG_P (operands[0]))
1236 if (FP_REG_P (operands[1]))
1237 return \"fmove%.x %1,%0\";
1238 if (REG_P (operands[1]))
1241 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1242 output_asm_insn (\"move%.l %1,%-\", xoperands);
1243 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1244 output_asm_insn (\"move%.l %1,%-\", xoperands);
1245 output_asm_insn (\"move%.l %1,%-\", operands);
1246 return \"fmove%.x %+,%0\";
1248 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1249 return \"fmove%.x %1,%0\";
1250 return \"fmove%.x %f1,%0\";
1252 if (FP_REG_P (operands[1]))
1254 if (REG_P (operands[0]))
1256 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1257 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1258 output_asm_insn (\"move%.l %+,%0\", operands);
1259 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1260 return \"move%.l %+,%0\";
1262 /* Must be memory destination. */
1263 return \"fmove%.x %f1,%0\";
1265 return output_move_double (operands);
1270 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1271 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1272 "! TARGET_68881 && ! TARGET_5200"
1275 if (FP_REG_P (operands[0]))
1277 if (FP_REG_P (operands[1]))
1278 return \"fmove%.x %1,%0\";
1279 if (REG_P (operands[1]))
1282 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1283 output_asm_insn (\"move%.l %1,%-\", xoperands);
1284 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1285 output_asm_insn (\"move%.l %1,%-\", xoperands);
1286 output_asm_insn (\"move%.l %1,%-\", operands);
1287 return \"fmove%.x %+,%0\";
1289 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1290 return \"fmove%.x %1,%0\";
1291 return \"fmove%.x %f1,%0\";
1293 if (FP_REG_P (operands[1]))
1295 if (REG_P (operands[0]))
1297 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1298 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1299 output_asm_insn (\"move%.l %+,%0\", operands);
1300 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1301 return \"move%.l %+,%0\";
1304 return \"fmove%.x %f1,%0\";
1306 return output_move_double (operands);
1311 [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
1312 (match_operand:XF 1 "nonimmediate_operand" "g,r"))]
1313 "! TARGET_68881 && TARGET_5200"
1314 "* return output_move_double (operands);")
1316 (define_expand "movdi"
1317 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1318 [(set (match_operand:DI 0 "general_operand" "")
1319 (match_operand:DI 1 "general_operand" ""))]
1323 ;; movdi can apply to fp regs in some cases
1325 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1326 [(set (match_operand:DI 0 "general_operand" "=rm,r,&ro<>,y,rm,!*x,!rm")
1327 (match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))]
1328 ; [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm")
1329 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))]
1330 ; [(set (match_operand:DI 0 "general_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1331 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1335 if (which_alternative == 8)
1336 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1337 if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
1338 return \"fpmove%.d %x1,%x0\";
1339 if (FP_REG_P (operands[0]))
1341 if (FP_REG_P (operands[1]))
1342 return \"fmove%.x %1,%0\";
1343 if (REG_P (operands[1]))
1346 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1347 output_asm_insn (\"move%.l %1,%-\", xoperands);
1348 output_asm_insn (\"move%.l %1,%-\", operands);
1349 return \"fmove%.d %+,%0\";
1351 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1352 return output_move_const_double (operands);
1353 return \"fmove%.d %f1,%0\";
1355 else if (FP_REG_P (operands[1]))
1357 if (REG_P (operands[0]))
1359 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1360 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1361 return \"move%.l %+,%0\";
1364 return \"fmove%.d %f1,%0\";
1366 return output_move_double (operands);
1370 [(set (match_operand:DI 0 "general_operand" "=r,g")
1371 (match_operand:DI 1 "general_operand" "g,r"))]
1373 "* return output_move_double (operands);")
1375 ;; Thus goes after the move instructions
1376 ;; because the move instructions are better (require no spilling)
1377 ;; when they can apply. It goes before the add/sub insns
1378 ;; so we will prefer it to them.
1380 (define_insn "pushasi"
1381 [(set (match_operand:SI 0 "push_operand" "=m")
1382 (match_operand:SI 1 "address_operand" "p"))]
1386 ;; truncation instructions
1387 (define_insn "truncsiqi2"
1388 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1390 (match_operand:SI 1 "general_operand" "doJ,i")))]
1394 if (GET_CODE (operands[0]) == REG)
1396 /* Must clear condition codes, since the move.l bases them on
1397 the entire 32 bits, not just the desired 8 bits. */
1399 return \"move%.l %1,%0\";
1401 if (GET_CODE (operands[1]) == MEM)
1402 operands[1] = adj_offsettable_operand (operands[1], 3);
1403 return \"move%.b %1,%0\";
1406 (define_insn "trunchiqi2"
1407 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1409 (match_operand:HI 1 "general_operand" "doJ,i")))]
1413 if (GET_CODE (operands[0]) == REG
1414 && (GET_CODE (operands[1]) == MEM
1415 || GET_CODE (operands[1]) == CONST_INT))
1417 /* Must clear condition codes, since the move.w bases them on
1418 the entire 16 bits, not just the desired 8 bits. */
1420 return \"move%.w %1,%0\";
1422 if (GET_CODE (operands[0]) == REG)
1424 /* Must clear condition codes, since the move.l bases them on
1425 the entire 32 bits, not just the desired 8 bits. */
1427 return \"move%.l %1,%0\";
1429 if (GET_CODE (operands[1]) == MEM)
1430 operands[1] = adj_offsettable_operand (operands[1], 1);
1431 return \"move%.b %1,%0\";
1434 (define_insn "truncsihi2"
1435 [(set (match_operand:HI 0 "general_operand" "=dm,d")
1437 (match_operand:SI 1 "general_operand" "roJ,i")))]
1441 if (GET_CODE (operands[0]) == REG)
1443 /* Must clear condition codes, since the move.l bases them on
1444 the entire 32 bits, not just the desired 8 bits. */
1446 return \"move%.l %1,%0\";
1448 if (GET_CODE (operands[1]) == MEM)
1449 operands[1] = adj_offsettable_operand (operands[1], 2);
1450 return \"move%.w %1,%0\";
1453 ;; zero extension instructions
1455 (define_insn "zero_extendqidi2"
1456 [(set (match_operand:DI 0 "general_operand" "=&d")
1457 (zero_extend:DI (match_operand:QI 1 "general_operand" "dm")))]
1462 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1463 return \"moveq %#0,%0\;moveq %#0,%2\;move%.b %1,%2\";
1466 (define_insn "zero_extendhidi2"
1467 [(set (match_operand:DI 0 "general_operand" "=&d")
1468 (zero_extend:DI (match_operand:HI 1 "general_operand" "rm")))]
1473 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1474 return \"moveq %#0,%0\;moveq %#0,%2\;move%.w %1,%2\";
1477 ;; this is the canonical form for (lshiftrt:DI x 32)
1478 (define_insn "zero_extendsidi2"
1479 [(set (match_operand:DI 0 "general_operand" "rm")
1480 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
1485 if (GET_CODE (operands[0]) == REG)
1486 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1487 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1488 return \"move%.l %1,%0\;clr%.l %0\";
1489 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1490 return \"clr%.l %0\;move%.l %1,%0\";
1492 operands[2] = adj_offsettable_operand (operands[0], 4);
1493 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[2]) != REG
1494 || REGNO (operands[1]) != REGNO (operands[2]))
1495 output_asm_insn (\"move%.l %1,%2\", operands);
1496 if (ADDRESS_REG_P (operands[0]))
1497 return \"sub%.l %0,%0\";
1499 return \"clr%.l %0\";
1502 (define_expand "zero_extendhisi2"
1503 [(set (match_operand:SI 0 "register_operand" "")
1505 (set (strict_low_part (match_dup 2))
1506 (match_operand:HI 1 "general_operand" ""))]
1510 operands[1] = make_safe_from (operands[1], operands[0]);
1511 if (GET_CODE (operands[0]) == SUBREG)
1512 operands[2] = gen_rtx_SUBREG (HImode, SUBREG_REG (operands[0]),
1513 SUBREG_WORD (operands[0]));
1515 operands[2] = gen_rtx_SUBREG (HImode, operands[0], 0);
1518 (define_expand "zero_extendqihi2"
1519 [(set (match_operand:HI 0 "register_operand" "")
1521 (set (strict_low_part (match_dup 2))
1522 (match_operand:QI 1 "general_operand" ""))]
1526 operands[1] = make_safe_from (operands[1], operands[0]);
1527 if (GET_CODE (operands[0]) == SUBREG)
1528 operands[2] = gen_rtx_SUBREG (QImode, SUBREG_REG (operands[0]),
1529 SUBREG_WORD (operands[0]));
1531 operands[2] = gen_rtx_SUBREG (QImode, operands[0], 0);
1534 (define_expand "zero_extendqisi2"
1535 [(set (match_operand:SI 0 "register_operand" "")
1537 (set (strict_low_part (match_dup 2))
1538 (match_operand:QI 1 "general_operand" ""))]
1542 operands[1] = make_safe_from (operands[1], operands[0]);
1543 if (GET_CODE (operands[0]) == SUBREG)
1544 operands[2] = gen_rtx_SUBREG (QImode, SUBREG_REG (operands[0]),
1545 SUBREG_WORD (operands[0]));
1547 operands[2] = gen_rtx_SUBREG (QImode, operands[0], 0);
1550 ;; Patterns to recognize zero-extend insns produced by the combiner.
1551 ;; We don't allow both operands in memory, because of aliasing problems.
1552 ;; Explicitly disallow two memory operands via the condition since reloading
1553 ;; of this case will result in worse code than the uncombined patterns.
1556 [(set (match_operand:SI 0 "general_operand" "=do<>,d<")
1557 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1558 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1561 if (DATA_REG_P (operands[0]))
1563 if (GET_CODE (operands[1]) == REG
1564 && REGNO (operands[0]) == REGNO (operands[1]))
1565 return \"and%.l %#0xFFFF,%0\";
1566 if (reg_mentioned_p (operands[0], operands[1]))
1567 return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\";
1568 return \"clr%.l %0\;move%.w %1,%0\";
1570 else if (GET_CODE (operands[0]) == MEM
1571 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1572 return \"move%.w %1,%0\;clr%.w %0\";
1573 else if (GET_CODE (operands[0]) == MEM
1574 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1575 return \"clr%.w %0\;move%.w %1,%0\";
1578 output_asm_insn (\"clr%.w %0\", operands);
1579 operands[0] = adj_offsettable_operand (operands[0], 2);
1580 return \"move%.w %1,%0\";
1585 [(set (match_operand:HI 0 "general_operand" "=do<>,d")
1586 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1587 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1590 if (DATA_REG_P (operands[0]))
1592 if (GET_CODE (operands[1]) == REG
1593 && REGNO (operands[0]) == REGNO (operands[1]))
1594 return (!TARGET_5200 ? \"and%.w %#0xFF,%0\" : \"and%.l %#0xFF,%0\");
1595 if (reg_mentioned_p (operands[0], operands[1]))
1596 return (!TARGET_5200 ? \"move%.b %1,%0\;and%.w %#0xFF,%0\"
1597 : \"move%.b %1,%0\;and%.l %#0xFF,%0\");
1598 return \"clr%.w %0\;move%.b %1,%0\";
1600 else if (GET_CODE (operands[0]) == MEM
1601 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1603 if (REGNO (XEXP (XEXP (operands[0], 0), 0))
1604 == STACK_POINTER_REGNUM)
1606 output_asm_insn (\"clr%.w %-\", operands);
1607 operands[0] = gen_rtx_MEM (GET_MODE (operands[0]),
1608 plus_constant (stack_pointer_rtx, 1));
1609 return \"move%.b %1,%0\";
1612 return \"move%.b %1,%0\;clr%.b %0\";
1614 else if (GET_CODE (operands[0]) == MEM
1615 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1616 return \"clr%.b %0\;move%.b %1,%0\";
1619 output_asm_insn (\"clr%.b %0\", operands);
1620 operands[0] = adj_offsettable_operand (operands[0], 1);
1621 return \"move%.b %1,%0\";
1626 [(set (match_operand:SI 0 "general_operand" "=do<>,d")
1627 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1628 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1631 if (DATA_REG_P (operands[0]))
1633 if (GET_CODE (operands[1]) == REG
1634 && REGNO (operands[0]) == REGNO (operands[1]))
1635 return \"and%.l %#0xFF,%0\";
1636 if (reg_mentioned_p (operands[0], operands[1]))
1637 return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
1638 return \"clr%.l %0\;move%.b %1,%0\";
1640 else if (GET_CODE (operands[0]) == MEM
1641 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1643 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1646 return \"clr%.l -(%0)\;move%.b %1,3(%0)\";
1648 return \"clr%.l -(%0)\;move%.b %1,(3,%0)\";
1651 return \"clrl %0@-\;moveb %1,%0@(3)\";
1654 else if (GET_CODE (operands[0]) == MEM
1655 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1657 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1660 return \"clr%.l (%0)+\;move%.b %1,-1(%0)\";
1662 return \"clr%.l (%0)+\;move%.b %1,(-1,%0)\";
1665 return \"clrl %0@+\;moveb %1,%0@(-1)\";
1670 output_asm_insn (\"clr%.l %0\", operands);
1671 operands[0] = adj_offsettable_operand (operands[0], 3);
1672 return \"move%.b %1,%0\";
1676 ;; sign extension instructions
1678 (define_insn "extendqidi2"
1679 [(set (match_operand:DI 0 "general_operand" "=d")
1680 (sign_extend:DI (match_operand:QI 1 "general_operand" "dm")))]
1685 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1686 if (TARGET_68020 || TARGET_5200)
1687 return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
1689 return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
1692 (define_insn "extendhidi2"
1693 [(set (match_operand:DI 0 "general_operand" "=d")
1695 (match_operand:HI 1 "general_operand" "rm")))]
1700 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1701 if (TARGET_68020 || TARGET_5200)
1702 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
1704 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
1707 (define_insn "extendsidi2"
1708 [(set (match_operand:DI 0 "general_operand" "=d")
1710 (match_operand:SI 1 "general_operand" "rm")))]
1715 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1716 if (TARGET_68020 || TARGET_5200)
1717 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
1719 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
1722 ;; Special case when one can avoid register clobbering, copy and test
1723 ;; Maybe there is a way to make that the general case, by forcing the
1724 ;; result of the SI tree to be in the lower register of the DI target
1726 (define_insn "extendplussidi"
1727 [(set (match_operand:DI 0 "register_operand" "=d")
1728 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1729 (match_operand:SI 2 "general_operand" "rmn"))))]
1734 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1735 if (GET_CODE (operands[1]) == CONST_INT
1736 && (unsigned) INTVAL (operands[1]) > 8)
1738 rtx tmp = operands[1];
1740 operands[1] = operands[2];
1743 if (GET_CODE (operands[1]) == REG
1744 && REGNO (operands[1]) == REGNO (operands[3]))
1745 output_asm_insn (\"add%.l %2,%3\", operands);
1747 output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands);
1748 if (TARGET_68020 || TARGET_5200)
1749 return \"smi %0\;extb%.l %0\";
1751 return \"smi %0\;ext%.w %0\;ext%.l %0\";
1754 (define_insn "extendhisi2"
1755 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1757 (match_operand:HI 1 "nonimmediate_operand" "0,rm")))]
1761 if (ADDRESS_REG_P (operands[0]))
1762 return \"move%.w %1,%0\";
1763 return \"ext%.l %0\";
1766 (define_insn "extendqihi2"
1767 [(set (match_operand:HI 0 "general_operand" "=d")
1768 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1772 (define_insn "extendqisi2"
1773 [(set (match_operand:SI 0 "general_operand" "=d")
1774 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1775 "TARGET_68020 || TARGET_5200"
1778 ;; Conversions between float and double.
1780 (define_expand "extendsfdf2"
1781 [(set (match_operand:DF 0 "general_operand" "")
1783 (match_operand:SF 1 "general_operand" "")))]
1784 "TARGET_68881 || TARGET_FPA"
1788 [(set (match_operand:DF 0 "general_operand" "=x,y")
1790 (match_operand:SF 1 "general_operand" "xH,rmF")))]
1795 [(set (match_operand:DF 0 "general_operand" "=*fdm,f")
1797 (match_operand:SF 1 "general_operand" "f,dmF")))]
1801 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1803 if (REGNO (operands[0]) == REGNO (operands[1]))
1805 /* Extending float to double in an fp-reg is a no-op.
1806 NOTICE_UPDATE_CC has already assumed that the
1807 cc will be set. So cancel what it did. */
1808 cc_status = cc_prev_status;
1811 return \"f%&move%.x %1,%0\";
1813 if (FP_REG_P (operands[0]))
1814 return \"f%&move%.s %f1,%0\";
1815 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1817 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1818 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1819 return \"move%.l %+,%0\";
1821 return \"fmove%.d %f1,%0\";
1824 ;; This cannot output into an f-reg because there is no way to be
1825 ;; sure of truncating in that case.
1826 ;; But on the Sun FPA, we can be sure.
1827 (define_expand "truncdfsf2"
1828 [(set (match_operand:SF 0 "general_operand" "")
1830 (match_operand:DF 1 "general_operand" "")))]
1831 "TARGET_68881 || TARGET_FPA"
1835 [(set (match_operand:SF 0 "general_operand" "=x,y")
1837 (match_operand:DF 1 "general_operand" "xH,rmF")))]
1841 ;; On the '040 we can truncate in a register accurately and easily.
1843 [(set (match_operand:SF 0 "general_operand" "=f")
1845 (match_operand:DF 1 "general_operand" "fmG")))]
1849 if (FP_REG_P (operands[1]))
1850 return \"f%$move%.x %1,%0\";
1851 return \"f%$move%.d %f1,%0\";
1855 [(set (match_operand:SF 0 "general_operand" "=dm")
1857 (match_operand:DF 1 "general_operand" "f")))]
1861 ;; Conversion between fixed point and floating point.
1862 ;; Note that among the fix-to-float insns
1863 ;; the ones that start with SImode come first.
1864 ;; That is so that an operand that is a CONST_INT
1865 ;; (and therefore lacks a specific machine mode).
1866 ;; will be recognized as SImode (which is always valid)
1867 ;; rather than as QImode or HImode.
1869 (define_expand "floatsisf2"
1870 [(set (match_operand:SF 0 "general_operand" "")
1871 (float:SF (match_operand:SI 1 "general_operand" "")))]
1872 "TARGET_68881 || TARGET_FPA"
1876 [(set (match_operand:SF 0 "general_operand" "=y,x")
1877 (float:SF (match_operand:SI 1 "general_operand" "rmi,x")))]
1882 [(set (match_operand:SF 0 "general_operand" "=f")
1883 (float:SF (match_operand:SI 1 "general_operand" "dmi")))]
1887 (define_expand "floatsidf2"
1888 [(set (match_operand:DF 0 "general_operand" "")
1889 (float:DF (match_operand:SI 1 "general_operand" "")))]
1890 "TARGET_68881 || TARGET_FPA"
1894 [(set (match_operand:DF 0 "general_operand" "=y,x")
1895 (float:DF (match_operand:SI 1 "general_operand" "rmi,x")))]
1900 [(set (match_operand:DF 0 "general_operand" "=f")
1901 (float:DF (match_operand:SI 1 "general_operand" "dmi")))]
1905 (define_insn "floathisf2"
1906 [(set (match_operand:SF 0 "general_operand" "=f")
1907 (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
1911 (define_insn "floathidf2"
1912 [(set (match_operand:DF 0 "general_operand" "=f")
1913 (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
1917 (define_insn "floatqisf2"
1918 [(set (match_operand:SF 0 "general_operand" "=f")
1919 (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
1923 (define_insn "floatqidf2"
1924 [(set (match_operand:DF 0 "general_operand" "=f")
1925 (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
1929 ;; New routines to convert floating-point values to integers
1930 ;; to be used on the '040. These should be faster than trapping
1931 ;; into the kernel to emulate fintrz. They should also be faster
1932 ;; than calling the subroutines fixsfsi or fixdfsi.
1934 (define_insn "fix_truncdfsi2"
1935 [(set (match_operand:SI 0 "general_operand" "=dm")
1936 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1937 (clobber (match_scratch:SI 2 "=d"))
1938 (clobber (match_scratch:SI 3 "=d"))]
1939 "TARGET_68881 && TARGET_68040"
1943 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\";
1946 (define_insn "fix_truncdfhi2"
1947 [(set (match_operand:HI 0 "general_operand" "=dm")
1948 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1949 (clobber (match_scratch:SI 2 "=d"))
1950 (clobber (match_scratch:SI 3 "=d"))]
1951 "TARGET_68881 && TARGET_68040"
1955 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\";
1958 (define_insn "fix_truncdfqi2"
1959 [(set (match_operand:QI 0 "general_operand" "=dm")
1960 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1961 (clobber (match_scratch:SI 2 "=d"))
1962 (clobber (match_scratch:SI 3 "=d"))]
1963 "TARGET_68881 && TARGET_68040"
1967 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\";
1970 ;; Convert a float to a float whose value is an integer.
1971 ;; This is the first stage of converting it to an integer type.
1973 (define_insn "ftruncdf2"
1974 [(set (match_operand:DF 0 "general_operand" "=f")
1975 (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
1976 "TARGET_68881 && !TARGET_68040"
1979 if (FP_REG_P (operands[1]))
1980 return \"fintrz%.x %f1,%0\";
1981 return \"fintrz%.d %f1,%0\";
1984 (define_insn "ftruncsf2"
1985 [(set (match_operand:SF 0 "general_operand" "=f")
1986 (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
1987 "TARGET_68881 && !TARGET_68040"
1990 if (FP_REG_P (operands[1]))
1991 return \"fintrz%.x %f1,%0\";
1992 return \"fintrz%.s %f1,%0\";
1995 ;; Convert a float whose value is an integer
1996 ;; to an actual integer. Second stage of converting float to integer type.
1997 (define_insn "fixsfqi2"
1998 [(set (match_operand:QI 0 "general_operand" "=dm")
1999 (fix:QI (match_operand:SF 1 "general_operand" "f")))]
2003 (define_insn "fixsfhi2"
2004 [(set (match_operand:HI 0 "general_operand" "=dm")
2005 (fix:HI (match_operand:SF 1 "general_operand" "f")))]
2009 (define_insn "fixsfsi2"
2010 [(set (match_operand:SI 0 "general_operand" "=dm")
2011 (fix:SI (match_operand:SF 1 "general_operand" "f")))]
2015 (define_insn "fixdfqi2"
2016 [(set (match_operand:QI 0 "general_operand" "=dm")
2017 (fix:QI (match_operand:DF 1 "general_operand" "f")))]
2021 (define_insn "fixdfhi2"
2022 [(set (match_operand:HI 0 "general_operand" "=dm")
2023 (fix:HI (match_operand:DF 1 "general_operand" "f")))]
2027 (define_insn "fixdfsi2"
2028 [(set (match_operand:SI 0 "general_operand" "=dm")
2029 (fix:SI (match_operand:DF 1 "general_operand" "f")))]
2033 ;; Convert a float to an integer.
2034 ;; On the Sun FPA, this is done in one step.
2037 [(set (match_operand:SI 0 "general_operand" "=x,y")
2038 (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "xH,rmF"))))]
2043 [(set (match_operand:SI 0 "general_operand" "=x,y")
2044 (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "xH,rmF"))))]
2050 (define_insn "adddi_lshrdi_63"
2051 [(set (match_operand:DI 0 "general_operand" "=d")
2052 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
2055 (clobber (match_scratch:SI 2 "=d"))]
2059 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2060 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
2062 \"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0\";
2063 if (GET_CODE (operands[1]) == REG)
2064 operands[4] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2065 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
2066 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2067 operands[4] = operands[1];
2069 operands[4] = adj_offsettable_operand (operands[1], 4);
2070 if (GET_CODE (operands[1]) == MEM
2071 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2072 output_asm_insn (\"move%.l %4,%3\", operands);
2073 output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
2074 if (TARGET_68020 || TARGET_5200)
2075 output_asm_insn (\"extb%.l %2\", operands);
2077 output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
2078 if (GET_CODE (operands[1]) != MEM
2079 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
2080 output_asm_insn (\"move%.l %4,%3\", operands);
2081 return \"sub%.l %2,%3\;subx%.l %2,%0\";
2084 (define_insn "adddi_sexthishl32"
2085 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2086 (plus:DI (ashift:DI (sign_extend:DI
2087 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
2089 (match_operand:DI 2 "general_operand" "0,0,0,0")))
2090 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2095 if (ADDRESS_REG_P (operands[0]))
2096 return \"add%.w %1,%0\";
2097 else if (ADDRESS_REG_P (operands[3]))
2098 return \"move%.w %1,%3\;add%.l %3,%0\";
2100 return \"move%.w %1,%3\;ext%.l %3\;add%.l %3,%0\";
2103 (define_insn "adddi_dilshr32"
2104 [(set (match_operand:DI 0 "general_operand" "=d,o")
2105 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2106 ;; (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
2107 ;; (const_int 32))))]
2108 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,r")
2110 (match_operand:DI 2 "general_operand" "0,0")))]
2115 if (GET_CODE (operands[0]) == REG)
2116 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2118 operands[2] = adj_offsettable_operand (operands[0], 4);
2119 return \"add%.l %1,%2\;negx%.l %0\;neg%.l %0\";
2122 (define_insn "adddi_dishl32"
2123 [(set (match_operand:DI 0 "general_operand" "=r,o")
2124 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2125 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2126 ;; (const_int 32))))]
2127 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro,r")
2129 (match_operand:DI 2 "general_operand" "0,0")))]
2134 if (GET_CODE (operands[1]) == REG)
2135 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2137 operands[1] = adj_offsettable_operand (operands[1], 4);
2138 return \"add%.l %1,%0\";
2141 (define_insn "adddi3"
2142 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2143 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0,0")
2144 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2145 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2149 if (DATA_REG_P (operands[0]))
2151 if (DATA_REG_P (operands[2]))
2152 return \"add%.l %R2,%R0\;addx%.l %2,%0\";
2153 else if (GET_CODE (operands[2]) == MEM
2154 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2156 return \"move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0\";
2161 if (GET_CODE (operands[2]) == REG)
2162 operands[1] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2163 else if (GET_CODE (operands[2]) == CONST_DOUBLE)
2165 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
2166 operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
2168 else if (GET_CODE (operands[2]) == CONST_INT)
2170 operands[1] = operands[2];
2171 operands[2] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx;
2174 operands[1] = adj_offsettable_operand (operands[2], 4);
2175 xoperands[0] = operands[3];
2176 if (GET_CODE (operands[1]) == CONST_INT
2177 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2178 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2180 xoperands[1] = operands[2];
2181 output_asm_insn (output_move_simode (xoperands), xoperands);
2182 if (GET_CODE (operands[1]) == CONST_INT)
2184 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2187 return \"add%.l %1,%R0\;addx%.l %3,%0\";
2189 return \"addq%.l %1,%R0\;addx%.l %3,%0\";
2192 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2194 operands[1] = GEN_INT (-INTVAL (operands[1]));
2196 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2198 return \"subq%.l %1,%R0\;subx%.l %3,%0\";
2202 return \"add%.l %1,%R0\;addx%.l %3,%0\";
2205 else if (GET_CODE (operands[0]) == MEM)
2207 if (GET_CODE (operands[2]) == MEM
2208 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2209 return \"add%.l %2,%0\;addx%.l %2,%0\";
2211 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2214 = gen_rtx_MEM (SImode,
2215 gen_rtx_PLUS (VOIDmode, XEXP(operands[0], 0),
2217 return \"move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1\";
2219 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2221 operands[1] = XEXP(operands[0], 0);
2222 return \"add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
2226 operands[1] = adj_offsettable_operand (operands[0], 4);
2227 return \"add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
2234 (define_insn "addsi_lshrsi_31"
2235 [(set (match_operand:SI 0 "general_operand" "=dm")
2236 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
2242 operands[2] = operands[0];
2243 operands[3] = gen_label_rtx();
2244 if (GET_CODE (operands[0]) == MEM)
2246 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2247 operands[0] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2248 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2249 operands[2] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2251 output_asm_insn (\"move%.l %1,%0\", operands);
2253 output_asm_insn (\"jbpl %l3\", operands);
2255 output_asm_insn (\"jpl %l3\", operands);
2258 output_asm_insn (\"addq%.l %#1,%2\", operands);
2260 output_asm_insn (\"add%.l %#1,%2\", operands);
2262 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
2263 CODE_LABEL_NUMBER (operands[3]));
2267 (define_expand "addsi3"
2268 [(set (match_operand:SI 0 "general_operand" "")
2269 (plus:SI (match_operand:SI 1 "general_operand" "")
2270 (match_operand:SI 2 "general_operand" "")))]
2274 ;; Note that the middle two alternatives are near-duplicates
2275 ;; in order to handle insns generated by reload.
2276 ;; This is needed since they are not themselves reloaded,
2277 ;; so commutativity won't apply to them.
2278 (define_insn "*addsi3_internal"
2279 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
2280 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2281 (match_operand:SI 2 "general_operand" "dIKLs,rJK,a,mrIKLs")))]
2283 "* return output_addsi3 (operands);")
2285 (define_insn "*addsi3_5200"
2286 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
2287 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2288 (match_operand:SI 2 "general_operand" "d,rJK,a,mrIKLs")))]
2290 "* return output_addsi3 (operands);")
2293 [(set (match_operand:SI 0 "general_operand" "=a")
2294 (plus:SI (match_operand:SI 1 "general_operand" "0")
2296 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2300 (define_insn "addhi3"
2301 [(set (match_operand:HI 0 "general_operand" "=m,r")
2302 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2303 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2307 if (GET_CODE (operands[2]) == CONST_INT)
2310 /* If the constant would be a negative number when interpreted as
2311 HImode, make it negative. This is usually, but not always, done
2312 elsewhere in the compiler. First check for constants out of range,
2313 which could confuse us. */
2315 if (INTVAL (operands[2]) >= 32768)
2316 operands[2] = GEN_INT (INTVAL (operands[2]) - 65536);
2318 if (INTVAL (operands[2]) > 0
2319 && INTVAL (operands[2]) <= 8)
2320 return \"addq%.w %2,%0\";
2321 if (INTVAL (operands[2]) < 0
2322 && INTVAL (operands[2]) >= -8)
2324 operands[2] = GEN_INT (-INTVAL (operands[2]));
2325 return \"subq%.w %2,%0\";
2327 /* On the CPU32 it is faster to use two addqw instructions to
2328 add a small integer (8 < N <= 16) to a register.
2329 Likewise for subqw. */
2330 if (TARGET_CPU32 && REG_P (operands[0]))
2332 if (INTVAL (operands[2]) > 8
2333 && INTVAL (operands[2]) <= 16)
2335 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
2336 return \"addq%.w %#8,%0\;addq%.w %2,%0\";
2338 if (INTVAL (operands[2]) < -8
2339 && INTVAL (operands[2]) >= -16)
2341 operands[2] = GEN_INT (-INTVAL (operands[2]) - 8);
2342 return \"subq%.w %#8,%0\;subq%.w %2,%0\";
2346 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2348 return \"lea (%c2,%0),%0\";
2350 return \"lea %0@(%c2),%0\";
2353 return \"add%.w %2,%0\";
2356 ;; These insns must use MATCH_DUP instead of the more expected
2357 ;; use of a matching constraint because the "output" here is also
2358 ;; an input, so you can't use the matching constraint. That also means
2359 ;; that you can't use the "%", so you need patterns with the matched
2360 ;; operand in both positions.
2363 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2364 (plus:HI (match_dup 0)
2365 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2369 if (GET_CODE (operands[1]) == CONST_INT)
2372 /* If the constant would be a negative number when interpreted as
2373 HImode, make it negative. This is usually, but not always, done
2374 elsewhere in the compiler. First check for constants out of range,
2375 which could confuse us. */
2377 if (INTVAL (operands[1]) >= 32768)
2378 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2380 if (INTVAL (operands[1]) > 0
2381 && INTVAL (operands[1]) <= 8)
2382 return \"addq%.w %1,%0\";
2383 if (INTVAL (operands[1]) < 0
2384 && INTVAL (operands[1]) >= -8)
2386 operands[1] = GEN_INT (-INTVAL (operands[1]));
2387 return \"subq%.w %1,%0\";
2389 /* On the CPU32 it is faster to use two addqw instructions to
2390 add a small integer (8 < N <= 16) to a register.
2391 Likewise for subqw. */
2392 if (TARGET_CPU32 && REG_P (operands[0]))
2394 if (INTVAL (operands[1]) > 8
2395 && INTVAL (operands[1]) <= 16)
2397 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2398 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2400 if (INTVAL (operands[1]) < -8
2401 && INTVAL (operands[1]) >= -16)
2403 operands[1] = GEN_INT (-INTVAL (operands[1]) - 8);
2404 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2408 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2410 return \"lea (%c1,%0),%0\";
2412 return \"lea %0@(%c1),%0\";
2415 return \"add%.w %1,%0\";
2419 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2420 (plus:HI (match_operand:HI 1 "general_operand" "dn,rmn")
2425 if (GET_CODE (operands[1]) == CONST_INT)
2428 /* If the constant would be a negative number when interpreted as
2429 HImode, make it negative. This is usually, but not always, done
2430 elsewhere in the compiler. First check for constants out of range,
2431 which could confuse us. */
2433 if (INTVAL (operands[1]) >= 32768)
2434 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2436 if (INTVAL (operands[1]) > 0
2437 && INTVAL (operands[1]) <= 8)
2438 return \"addq%.w %1,%0\";
2439 if (INTVAL (operands[1]) < 0
2440 && INTVAL (operands[1]) >= -8)
2442 operands[1] = GEN_INT (-INTVAL (operands[1]));
2443 return \"subq%.w %1,%0\";
2445 /* On the CPU32 it is faster to use two addqw instructions to
2446 add a small integer (8 < N <= 16) to a register.
2447 Likewise for subqw. */
2448 if (TARGET_CPU32 && REG_P (operands[0]))
2450 if (INTVAL (operands[1]) > 8
2451 && INTVAL (operands[1]) <= 16)
2453 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2454 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2456 if (INTVAL (operands[1]) < -8
2457 && INTVAL (operands[1]) >= -16)
2459 operands[1] = GEN_INT (-INTVAL (operands[1]) - 8);
2460 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2464 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2466 return \"lea (%c1,%0),%0\";
2468 return \"lea %0@(%c1),%0\";
2471 return \"add%.w %1,%0\";
2474 (define_insn "addqi3"
2475 [(set (match_operand:QI 0 "general_operand" "=m,d")
2476 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2477 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2482 if (GET_CODE (operands[2]) == CONST_INT)
2484 if (INTVAL (operands[2]) >= 128)
2485 operands[2] = GEN_INT (INTVAL (operands[2]) - 256);
2487 if (INTVAL (operands[2]) > 0
2488 && INTVAL (operands[2]) <= 8)
2489 return \"addq%.b %2,%0\";
2490 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2492 operands[2] = GEN_INT (-INTVAL (operands[2]));
2493 return \"subq%.b %2,%0\";
2497 return \"add%.b %2,%0\";
2501 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2502 (plus:QI (match_dup 0)
2503 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2508 if (GET_CODE (operands[1]) == CONST_INT)
2510 if (INTVAL (operands[1]) >= 128)
2511 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2513 if (INTVAL (operands[1]) > 0
2514 && INTVAL (operands[1]) <= 8)
2515 return \"addq%.b %1,%0\";
2516 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2518 operands[1] = GEN_INT (-INTVAL (operands[1]));
2519 return \"subq%.b %1,%0\";
2523 return \"add%.b %1,%0\";
2527 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2528 (plus:QI (match_operand:QI 1 "general_operand" "dn,dmn")
2534 if (GET_CODE (operands[1]) == CONST_INT)
2536 if (INTVAL (operands[1]) >= 128)
2537 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2539 if (INTVAL (operands[1]) > 0
2540 && INTVAL (operands[1]) <= 8)
2541 return \"addq%.b %1,%0\";
2542 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2544 operands[1] = GEN_INT (-INTVAL (operands[1]));
2545 return \"subq%.b %1,%0\";
2549 return \"add%.b %1,%0\";
2552 (define_expand "adddf3"
2553 [(set (match_operand:DF 0 "general_operand" "")
2554 (plus:DF (match_operand:DF 1 "general_operand" "")
2555 (match_operand:DF 2 "general_operand" "")))]
2556 "TARGET_68881 || TARGET_FPA"
2560 [(set (match_operand:DF 0 "general_operand" "=x,y")
2561 (plus:DF (match_operand:DF 1 "general_operand" "%xH,y")
2562 (match_operand:DF 2 "general_operand" "xH,dmF")))]
2566 if (rtx_equal_p (operands[0], operands[1]))
2567 return \"fpadd%.d %y2,%0\";
2568 if (rtx_equal_p (operands[0], operands[2]))
2569 return \"fpadd%.d %y1,%0\";
2570 if (which_alternative == 0)
2571 return \"fpadd3%.d %w2,%w1,%0\";
2572 return \"fpadd3%.d %x2,%x1,%0\";
2576 [(set (match_operand:DF 0 "general_operand" "=f")
2577 (plus:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2578 (match_operand:DF 1 "general_operand" "0")))]
2583 [(set (match_operand:DF 0 "general_operand" "=f")
2584 (plus:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2585 (match_operand:DF 1 "general_operand" "0")))]
2590 [(set (match_operand:DF 0 "general_operand" "=f")
2591 (plus:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2592 (match_operand:DF 1 "general_operand" "0")))]
2597 [(set (match_operand:DF 0 "general_operand" "=f")
2598 (plus:DF (match_operand:DF 1 "general_operand" "%0")
2599 (match_operand:DF 2 "general_operand" "fmG")))]
2603 if (REG_P (operands[2]))
2604 return \"f%&add%.x %2,%0\";
2605 return \"f%&add%.d %f2,%0\";
2608 (define_expand "addsf3"
2609 [(set (match_operand:SF 0 "general_operand" "")
2610 (plus:SF (match_operand:SF 1 "general_operand" "")
2611 (match_operand:SF 2 "general_operand" "")))]
2612 "TARGET_68881 || TARGET_FPA"
2616 [(set (match_operand:SF 0 "general_operand" "=x,y")
2617 (plus:SF (match_operand:SF 1 "general_operand" "%xH,y")
2618 (match_operand:SF 2 "general_operand" "xH,rmF")))]
2622 if (rtx_equal_p (operands[0], operands[1]))
2623 return \"fpadd%.s %w2,%0\";
2624 if (rtx_equal_p (operands[0], operands[2]))
2625 return \"fpadd%.s %w1,%0\";
2626 if (which_alternative == 0)
2627 return \"fpadd3%.s %w2,%w1,%0\";
2628 return \"fpadd3%.s %2,%1,%0\";
2632 [(set (match_operand:SF 0 "general_operand" "=f")
2633 (plus:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2634 (match_operand:SF 1 "general_operand" "0")))]
2639 [(set (match_operand:SF 0 "general_operand" "=f")
2640 (plus:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
2641 (match_operand:SF 1 "general_operand" "0")))]
2646 [(set (match_operand:SF 0 "general_operand" "=f")
2647 (plus:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
2648 (match_operand:SF 1 "general_operand" "0")))]
2653 [(set (match_operand:SF 0 "general_operand" "=f")
2654 (plus:SF (match_operand:SF 1 "general_operand" "%0")
2655 (match_operand:SF 2 "general_operand" "fdmF")))]
2659 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2660 return \"f%$add%.x %2,%0\";
2661 return \"f%$add%.s %f2,%0\";
2664 ;; subtract instructions
2666 (define_insn "subdi_sexthishl32"
2667 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2668 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2669 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2671 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2676 if (ADDRESS_REG_P (operands[0]))
2677 return \"sub%.w %2,%0\";
2678 else if (ADDRESS_REG_P (operands[3]))
2679 return \"move%.w %2,%3\;sub%.l %3,%0\";
2681 return \"move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0\";
2684 (define_insn "subdi_dishl32"
2685 [(set (match_operand:DI 0 "general_operand" "+ro")
2686 (minus:DI (match_dup 0)
2687 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2693 if (GET_CODE (operands[1]) == REG)
2694 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2696 operands[1] = adj_offsettable_operand (operands[1], 4);
2697 return \"sub%.l %1,%0\";
2700 (define_insn "subdi3"
2701 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2702 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0,0")
2703 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2704 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2708 if (DATA_REG_P (operands[0]))
2710 if (DATA_REG_P (operands[2]))
2711 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
2712 else if (GET_CODE (operands[2]) == MEM
2713 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2715 return \"move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0\";
2720 if (GET_CODE (operands[2]) == REG)
2721 operands[1] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2722 else if (GET_CODE (operands[2]) == CONST_DOUBLE)
2724 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
2725 operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
2727 else if (GET_CODE (operands[2]) == CONST_INT)
2729 operands[1] = operands[2];
2730 operands[2] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx;
2733 operands[1] = adj_offsettable_operand (operands[2], 4);
2734 xoperands[0] = operands[3];
2735 if (GET_CODE (operands[1]) == CONST_INT
2736 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2737 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2739 xoperands[1] = operands[2];
2740 output_asm_insn (output_move_simode (xoperands), xoperands);
2741 if (GET_CODE (operands[1]) == CONST_INT)
2743 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2746 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2748 return \"subq%.l %1,%R0\;subx%.l %3,%0\";
2751 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2753 operands[1] = GEN_INT (-INTVAL (operands[1]));
2755 return \"add%.l %1,%R0\;addx%.l %3,%0\";
2757 return \"addq%.l %1,%R0\;addx%.l %3,%0\";
2761 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2764 else if (GET_CODE (operands[0]) == MEM)
2766 if (GET_CODE (operands[2]) == MEM
2767 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2768 return \"sub%.l %2,%0\;subx%.l %2,%0\";
2770 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2773 = gen_rtx_MEM (SImode,
2774 gen_rtx_PLUS (VOIDmode, XEXP(operands[0], 0),
2776 return \"move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1\";
2778 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2780 operands[1] = XEXP(operands[0], 0);
2781 return \"sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
2785 operands[1] = adj_offsettable_operand (operands[0], 4);
2786 return \"sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
2793 (define_insn "subsi3"
2794 [(set (match_operand:SI 0 "general_operand" "=m,r")
2795 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
2796 (match_operand:SI 2 "general_operand" "ds,mrs")))]
2801 [(set (match_operand:SI 0 "general_operand" "=a")
2802 (minus:SI (match_operand:SI 1 "general_operand" "0")
2804 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2808 (define_insn "subhi3"
2809 [(set (match_operand:HI 0 "general_operand" "=m,r")
2810 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2811 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2816 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2817 (minus:HI (match_dup 0)
2818 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2822 (define_insn "subqi3"
2823 [(set (match_operand:QI 0 "general_operand" "=m,d")
2824 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2825 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2830 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2831 (minus:QI (match_dup 0)
2832 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2836 (define_expand "subdf3"
2837 [(set (match_operand:DF 0 "general_operand" "")
2838 (minus:DF (match_operand:DF 1 "general_operand" "")
2839 (match_operand:DF 2 "general_operand" "")))]
2840 "TARGET_68881 || TARGET_FPA"
2844 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
2845 (minus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF")
2846 (match_operand:DF 2 "general_operand" "xH,dmF,0")))]
2850 if (rtx_equal_p (operands[0], operands[2]))
2851 return \"fprsub%.d %y1,%0\";
2852 if (rtx_equal_p (operands[0], operands[1]))
2853 return \"fpsub%.d %y2,%0\";
2854 if (which_alternative == 0)
2855 return \"fpsub3%.d %w2,%w1,%0\";
2856 return \"fpsub3%.d %x2,%x1,%0\";
2860 [(set (match_operand:DF 0 "general_operand" "=f")
2861 (minus:DF (match_operand:DF 1 "general_operand" "0")
2862 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
2867 [(set (match_operand:DF 0 "general_operand" "=f")
2868 (minus:DF (match_operand:DF 1 "general_operand" "0")
2869 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
2874 [(set (match_operand:DF 0 "general_operand" "=f")
2875 (minus:DF (match_operand:DF 1 "general_operand" "0")
2876 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
2881 [(set (match_operand:DF 0 "general_operand" "=f")
2882 (minus:DF (match_operand:DF 1 "general_operand" "0")
2883 (match_operand:DF 2 "general_operand" "fmG")))]
2887 if (REG_P (operands[2]))
2888 return \"f%&sub%.x %2,%0\";
2889 return \"f%&sub%.d %f2,%0\";
2892 (define_expand "subsf3"
2893 [(set (match_operand:SF 0 "general_operand" "")
2894 (minus:SF (match_operand:SF 1 "general_operand" "")
2895 (match_operand:SF 2 "general_operand" "")))]
2896 "TARGET_68881 || TARGET_FPA"
2900 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
2901 (minus:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
2902 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
2906 if (rtx_equal_p (operands[0], operands[2]))
2907 return \"fprsub%.s %w1,%0\";
2908 if (rtx_equal_p (operands[0], operands[1]))
2909 return \"fpsub%.s %w2,%0\";
2910 if (which_alternative == 0)
2911 return \"fpsub3%.s %w2,%w1,%0\";
2912 return \"fpsub3%.s %2,%1,%0\";
2916 [(set (match_operand:SF 0 "general_operand" "=f")
2917 (minus:SF (match_operand:SF 1 "general_operand" "0")
2918 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
2923 [(set (match_operand:SF 0 "general_operand" "=f")
2924 (minus:SF (match_operand:SF 1 "general_operand" "0")
2925 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
2930 [(set (match_operand:SF 0 "general_operand" "=f")
2931 (minus:SF (match_operand:SF 1 "general_operand" "0")
2932 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
2937 [(set (match_operand:SF 0 "general_operand" "=f")
2938 (minus:SF (match_operand:SF 1 "general_operand" "0")
2939 (match_operand:SF 2 "general_operand" "fdmF")))]
2943 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2944 return \"f%$sub%.x %2,%0\";
2945 return \"f%$sub%.s %f2,%0\";
2948 ;; multiply instructions
2950 (define_insn "mulhi3"
2951 [(set (match_operand:HI 0 "general_operand" "=d")
2952 (mult:HI (match_operand:HI 1 "general_operand" "%0")
2953 (match_operand:HI 2 "general_operand" "dmn")))]
2957 #if defined(MOTOROLA) && !defined(CRDS)
2958 return \"muls%.w %2,%0\";
2960 return \"muls %2,%0\";
2964 (define_insn "mulhisi3"
2965 [(set (match_operand:SI 0 "general_operand" "=d")
2966 (mult:SI (sign_extend:SI
2967 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2969 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
2973 #if defined(MOTOROLA) && !defined(CRDS)
2974 return \"muls%.w %2,%0\";
2976 return \"muls %2,%0\";
2981 [(set (match_operand:SI 0 "general_operand" "=d")
2982 (mult:SI (sign_extend:SI
2983 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2984 (match_operand:SI 2 "const_int_operand" "n")))]
2985 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
2988 #if defined(MOTOROLA) && !defined(CRDS)
2989 return \"muls%.w %2,%0\";
2991 return \"muls %2,%0\";
2995 (define_expand "mulsi3"
2996 [(set (match_operand:SI 0 "general_operand" "")
2997 (mult:SI (match_operand:SI 1 "general_operand" "")
2998 (match_operand:SI 2 "general_operand" "")))]
2999 "TARGET_68020 || TARGET_5200"
3003 [(set (match_operand:SI 0 "general_operand" "=d")
3004 (mult:SI (match_operand:SI 1 "general_operand" "%0")
3005 (match_operand:SI 2 "general_operand" "dmsK")))]
3010 [(set (match_operand:SI 0 "general_operand" "=d")
3011 (mult:SI (match_operand:SI 1 "general_operand" "%0")
3012 (match_operand:SI 2 "general_operand" "d<Q>")))]
3016 (define_insn "umulhisi3"
3017 [(set (match_operand:SI 0 "general_operand" "=d")
3018 (mult:SI (zero_extend:SI
3019 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3021 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
3025 #if defined(MOTOROLA) && !defined(CRDS)
3026 return \"mulu%.w %2,%0\";
3028 return \"mulu %2,%0\";
3033 [(set (match_operand:SI 0 "general_operand" "=d")
3034 (mult:SI (zero_extend:SI
3035 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3036 (match_operand:SI 2 "const_int_operand" "n")))]
3037 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
3040 #if defined(MOTOROLA) && !defined(CRDS)
3041 return \"mulu%.w %2,%0\";
3043 return \"mulu %2,%0\";
3047 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
3048 ;; proper matching constraint. This is because the matching is between
3049 ;; the high-numbered word of the DImode operand[0] and operand[1].
3050 (define_expand "umulsidi3"
3052 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
3053 (mult:SI (match_operand:SI 1 "register_operand" "")
3054 (match_operand:SI 2 "nonimmediate_operand" "")))
3055 (set (subreg:SI (match_dup 0) 0)
3056 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3057 (zero_extend:DI (match_dup 2)))
3058 (const_int 32))))])]
3059 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3063 [(set (match_operand:SI 0 "register_operand" "=d")
3064 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3065 (match_operand:SI 2 "nonimmediate_operand" "dm")))
3066 (set (match_operand:SI 3 "register_operand" "=d")
3067 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3068 (zero_extend:DI (match_dup 2)))
3070 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3073 ; Match immediate case. For 2.4 only match things < 2^31.
3074 ; It's tricky with larger values in these patterns since we need to match
3075 ; values between the two parallel multiplies, between a CONST_DOUBLE and
3078 [(set (match_operand:SI 0 "register_operand" "=d")
3079 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3080 (match_operand:SI 2 "const_int_operand" "n")))
3081 (set (match_operand:SI 3 "register_operand" "=d")
3082 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3085 "TARGET_68020 && !TARGET_68060 && !TARGET_5200
3086 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
3089 (define_expand "mulsidi3"
3091 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
3092 (mult:SI (match_operand:SI 1 "register_operand" "")
3093 (match_operand:SI 2 "nonimmediate_operand" "")))
3094 (set (subreg:SI (match_dup 0) 0)
3095 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3096 (sign_extend:DI (match_dup 2)))
3097 (const_int 32))))])]
3098 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3102 [(set (match_operand:SI 0 "register_operand" "=d")
3103 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3104 (match_operand:SI 2 "nonimmediate_operand" "dm")))
3105 (set (match_operand:SI 3 "register_operand" "=d")
3106 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3107 (sign_extend:DI (match_dup 2)))
3109 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3113 [(set (match_operand:SI 0 "register_operand" "=d")
3114 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3115 (match_operand:SI 2 "const_sint32_operand" "")))
3116 (set (match_operand:SI 3 "register_operand" "=d")
3117 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3120 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3123 (define_expand "umulsi3_highpart"
3125 [(set (match_operand:SI 0 "register_operand" "")
3128 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
3129 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
3131 (clobber (match_dup 3))])]
3132 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3135 operands[3] = gen_reg_rtx (SImode);
3136 if (GET_CODE (operands[2]) == CONST_INT
3137 || GET_CODE (operands[2]) == CONST_DOUBLE)
3139 if (! const_uint32_operand (operands[2], VOIDmode))
3141 /* We have to adjust the operand order for the matching constraints. */
3142 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
3143 operands[1], operands[2]));
3149 [(set (match_operand:SI 0 "register_operand" "=d")
3152 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3153 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3155 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3156 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3159 (define_insn "const_umulsi3_highpart"
3160 [(set (match_operand:SI 0 "register_operand" "=d")
3163 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
3164 (match_operand 3 "const_uint32_operand" ""))
3166 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3167 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3170 (define_expand "smulsi3_highpart"
3172 [(set (match_operand:SI 0 "register_operand" "")
3175 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
3176 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
3178 (clobber (match_dup 3))])]
3179 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3182 operands[3] = gen_reg_rtx (SImode);
3183 if (GET_CODE (operands[2]) == CONST_INT
3184 || GET_CODE (operands[2]) == CONST_DOUBLE)
3186 if (! const_sint32_operand (operands[2], VOIDmode))
3188 /* We have to adjust the operand order for the matching constraints. */
3189 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
3190 operands[1], operands[2]));
3196 [(set (match_operand:SI 0 "register_operand" "=d")
3199 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3200 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3202 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3203 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3206 (define_insn "const_smulsi3_highpart"
3207 [(set (match_operand:SI 0 "register_operand" "=d")
3210 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
3211 (match_operand 3 "const_sint32_operand" ""))
3213 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3214 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3217 (define_expand "muldf3"
3218 [(set (match_operand:DF 0 "general_operand" "")
3219 (mult:DF (match_operand:DF 1 "general_operand" "")
3220 (match_operand:DF 2 "general_operand" "")))]
3221 "TARGET_68881 || TARGET_FPA"
3225 [(set (match_operand:DF 0 "general_operand" "=x,y")
3226 (mult:DF (match_operand:DF 1 "general_operand" "%xH,y")
3227 (match_operand:DF 2 "general_operand" "xH,rmF")))]
3231 if (rtx_equal_p (operands[1], operands[2]))
3232 return \"fpsqr%.d %y1,%0\";
3233 if (rtx_equal_p (operands[0], operands[1]))
3234 return \"fpmul%.d %y2,%0\";
3235 if (rtx_equal_p (operands[0], operands[2]))
3236 return \"fpmul%.d %y1,%0\";
3237 if (which_alternative == 0)
3238 return \"fpmul3%.d %w2,%w1,%0\";
3239 return \"fpmul3%.d %x2,%x1,%0\";
3243 [(set (match_operand:DF 0 "general_operand" "=f")
3244 (mult:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
3245 (match_operand:DF 1 "general_operand" "0")))]
3250 [(set (match_operand:DF 0 "general_operand" "=f")
3251 (mult:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
3252 (match_operand:DF 1 "general_operand" "0")))]
3257 [(set (match_operand:DF 0 "general_operand" "=f")
3258 (mult:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
3259 (match_operand:DF 1 "general_operand" "0")))]
3264 [(set (match_operand:DF 0 "general_operand" "=f")
3265 (mult:DF (match_operand:DF 1 "general_operand" "%0")
3266 (match_operand:DF 2 "general_operand" "fmG")))]
3270 if (GET_CODE (operands[2]) == CONST_DOUBLE
3271 && floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
3273 int i = floating_exact_log2 (operands[2]);
3274 operands[2] = GEN_INT (i);
3275 return \"fscale%.l %2,%0\";
3277 if (REG_P (operands[2]))
3278 return \"f%&mul%.x %2,%0\";
3279 return \"f%&mul%.d %f2,%0\";
3282 (define_expand "mulsf3"
3283 [(set (match_operand:SF 0 "general_operand" "")
3284 (mult:SF (match_operand:SF 1 "general_operand" "")
3285 (match_operand:SF 2 "general_operand" "")))]
3286 "TARGET_68881 || TARGET_FPA"
3290 [(set (match_operand:SF 0 "general_operand" "=x,y")
3291 (mult:SF (match_operand:SF 1 "general_operand" "%xH,y")
3292 (match_operand:SF 2 "general_operand" "xH,rmF")))]
3296 if (rtx_equal_p (operands[1], operands[2]))
3297 return \"fpsqr%.s %w1,%0\";
3298 if (rtx_equal_p (operands[0], operands[1]))
3299 return \"fpmul%.s %w2,%0\";
3300 if (rtx_equal_p (operands[0], operands[2]))
3301 return \"fpmul%.s %w1,%0\";
3302 if (which_alternative == 0)
3303 return \"fpmul3%.s %w2,%w1,%0\";
3304 return \"fpmul3%.s %2,%1,%0\";
3308 [(set (match_operand:SF 0 "general_operand" "=f")
3309 (mult:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
3310 (match_operand:SF 1 "general_operand" "0")))]
3314 return (TARGET_68040_ONLY
3315 ? \"fsmul%.l %2,%0\"
3316 : \"fsglmul%.l %2,%0\");
3320 [(set (match_operand:SF 0 "general_operand" "=f")
3321 (mult:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
3322 (match_operand:SF 1 "general_operand" "0")))]
3326 return (TARGET_68040_ONLY
3327 ? \"fsmul%.w %2,%0\"
3328 : \"fsglmul%.w %2,%0\");
3332 [(set (match_operand:SF 0 "general_operand" "=f")
3333 (mult:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
3334 (match_operand:SF 1 "general_operand" "0")))]
3338 return (TARGET_68040_ONLY
3339 ? \"fsmul%.b %2,%0\"
3340 : \"fsglmul%.b %2,%0\");
3344 [(set (match_operand:SF 0 "general_operand" "=f")
3345 (mult:SF (match_operand:SF 1 "general_operand" "%0")
3346 (match_operand:SF 2 "general_operand" "fdmF")))]
3350 #ifdef FSGLMUL_USE_S
3351 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3352 return (TARGET_68040_ONLY
3353 ? \"fsmul%.s %2,%0\"
3354 : \"fsglmul%.s %2,%0\");
3356 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3357 return (TARGET_68040_ONLY
3358 ? \"fsmul%.x %2,%0\"
3359 : \"fsglmul%.x %2,%0\");
3361 return (TARGET_68040_ONLY
3362 ? \"fsmul%.s %f2,%0\"
3363 : \"fsglmul%.s %f2,%0\");
3366 ;; divide instructions
3368 (define_expand "divdf3"
3369 [(set (match_operand:DF 0 "general_operand" "")
3370 (div:DF (match_operand:DF 1 "general_operand" "")
3371 (match_operand:DF 2 "general_operand" "")))]
3372 "TARGET_68881 || TARGET_FPA"
3376 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
3377 (div:DF (match_operand:DF 1 "general_operand" "xH,y,rmF")
3378 (match_operand:DF 2 "general_operand" "xH,rmF,0")))]
3382 if (rtx_equal_p (operands[0], operands[2]))
3383 return \"fprdiv%.d %y1,%0\";
3384 if (rtx_equal_p (operands[0], operands[1]))
3385 return \"fpdiv%.d %y2,%0\";
3386 if (which_alternative == 0)
3387 return \"fpdiv3%.d %w2,%w1,%0\";
3388 return \"fpdiv3%.d %x2,%x1,%x0\";
3392 [(set (match_operand:DF 0 "general_operand" "=f")
3393 (div:DF (match_operand:DF 1 "general_operand" "0")
3394 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
3399 [(set (match_operand:DF 0 "general_operand" "=f")
3400 (div:DF (match_operand:DF 1 "general_operand" "0")
3401 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
3406 [(set (match_operand:DF 0 "general_operand" "=f")
3407 (div:DF (match_operand:DF 1 "general_operand" "0")
3408 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
3413 [(set (match_operand:DF 0 "general_operand" "=f")
3414 (div:DF (match_operand:DF 1 "general_operand" "0")
3415 (match_operand:DF 2 "general_operand" "fmG")))]
3419 if (REG_P (operands[2]))
3420 return \"f%&div%.x %2,%0\";
3421 return \"f%&div%.d %f2,%0\";
3424 (define_expand "divsf3"
3425 [(set (match_operand:SF 0 "general_operand" "")
3426 (div:SF (match_operand:SF 1 "general_operand" "")
3427 (match_operand:SF 2 "general_operand" "")))]
3428 "TARGET_68881 || TARGET_FPA"
3432 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
3433 (div:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
3434 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
3438 if (rtx_equal_p (operands[0], operands[1]))
3439 return \"fpdiv%.s %w2,%0\";
3440 if (rtx_equal_p (operands[0], operands[2]))
3441 return \"fprdiv%.s %w1,%0\";
3442 if (which_alternative == 0)
3443 return \"fpdiv3%.s %w2,%w1,%0\";
3444 return \"fpdiv3%.s %2,%1,%0\";
3448 [(set (match_operand:SF 0 "general_operand" "=f")
3449 (div:SF (match_operand:SF 1 "general_operand" "0")
3450 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
3454 return (TARGET_68040_ONLY
3455 ? \"fsdiv%.l %2,%0\"
3456 : \"fsgldiv%.l %2,%0\");
3460 [(set (match_operand:SF 0 "general_operand" "=f")
3461 (div:SF (match_operand:SF 1 "general_operand" "0")
3462 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
3466 return (TARGET_68040_ONLY
3467 ? \"fsdiv%.w %2,%0\"
3468 : \"fsgldiv%.w %2,%0\");
3472 [(set (match_operand:SF 0 "general_operand" "=f")
3473 (div:SF (match_operand:SF 1 "general_operand" "0")
3474 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
3478 return (TARGET_68040_ONLY
3479 ? \"fsdiv%.b %2,%0\"
3480 : \"fsgldiv%.b %2,%0\");
3484 [(set (match_operand:SF 0 "general_operand" "=f")
3485 (div:SF (match_operand:SF 1 "general_operand" "0")
3486 (match_operand:SF 2 "general_operand" "fdmF")))]
3490 #ifdef FSGLDIV_USE_S
3491 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3492 return (TARGET_68040_ONLY
3493 ? \"fsdiv%.s %2,%0\"
3494 : \"fsgldiv%.s %2,%0\");
3496 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3497 return (TARGET_68040_ONLY
3498 ? \"fsdiv%.x %2,%0\"
3499 : \"fsgldiv%.x %2,%0\");
3501 return (TARGET_68040_ONLY
3502 ? \"fsdiv%.s %f2,%0\"
3503 : \"fsgldiv%.s %f2,%0\");
3506 ;; Remainder instructions.
3508 (define_insn "divmodsi4"
3509 [(set (match_operand:SI 0 "general_operand" "=d")
3510 (div:SI (match_operand:SI 1 "general_operand" "0")
3511 (match_operand:SI 2 "general_operand" "dmsK")))
3512 (set (match_operand:SI 3 "general_operand" "=d")
3513 (mod:SI (match_dup 1) (match_dup 2)))]
3514 "TARGET_68020 && !TARGET_5200"
3517 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3518 return \"divs%.l %2,%0\";
3520 return \"divsl%.l %2,%3:%0\";
3523 (define_insn "udivmodsi4"
3524 [(set (match_operand:SI 0 "general_operand" "=d")
3525 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3526 (match_operand:SI 2 "general_operand" "dmsK")))
3527 (set (match_operand:SI 3 "general_operand" "=d")
3528 (umod:SI (match_dup 1) (match_dup 2)))]
3529 "TARGET_68020 && !TARGET_5200"
3532 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3533 return \"divu%.l %2,%0\";
3535 return \"divul%.l %2,%3:%0\";
3538 (define_insn "divmodhi4"
3539 [(set (match_operand:HI 0 "general_operand" "=d")
3540 (div:HI (match_operand:HI 1 "general_operand" "0")
3541 (match_operand:HI 2 "general_operand" "dmsK")))
3542 (set (match_operand:HI 3 "general_operand" "=d")
3543 (mod:HI (match_dup 1) (match_dup 2)))]
3548 output_asm_insn (\"ext%.l %0\;divs%.w %2,%0\", operands);
3550 output_asm_insn (\"extl %0\;divs %2,%0\", operands);
3552 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3555 return \"move%.l %0,%3\;swap %3\";
3561 (define_insn "udivmodhi4"
3562 [(set (match_operand:HI 0 "general_operand" "=d")
3563 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3564 (match_operand:HI 2 "general_operand" "dmsK")))
3565 (set (match_operand:HI 3 "general_operand" "=d")
3566 (umod:HI (match_dup 1) (match_dup 2)))]
3571 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu%.w %2,%0\", operands);
3573 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu %2,%0\", operands);
3575 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3578 return \"move%.l %0,%3\;swap %3\";
3584 ;; logical-and instructions
3586 ;; "anddi3" is mainly here to help combine().
3587 (define_insn "anddi3"
3588 [(set (match_operand:DI 0 "general_operand" "=o,d")
3589 (and:DI (match_operand:DI 1 "general_operand" "%0,0")
3590 (match_operand:DI 2 "general_operand" "dn,don")))]
3595 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3596 if (GET_CODE (operands[2]) == CONST_DOUBLE
3597 || GET_CODE (operands[2]) == CONST_INT)
3601 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3603 hi = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
3604 lo = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3609 hi = INTVAL (lo) < 0 ? constm1_rtx : const0_rtx;
3611 switch (INTVAL (hi))
3614 output_asm_insn (\"clr%.l %0\", operands);
3622 xoperands[0] = operands[0];
3624 output_asm_insn (output_andsi3 (xoperands), xoperands);
3627 if (GET_CODE (operands[0]) == REG)
3628 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3630 operands[0] = adj_offsettable_operand (operands[0], 4);
3631 switch (INTVAL (lo))
3634 output_asm_insn (\"clr%.l %0\", operands);
3642 xoperands[0] = operands[0];
3644 output_asm_insn (output_andsi3 (xoperands), xoperands);
3649 if (GET_CODE (operands[0]) != REG)
3651 operands[1] = adj_offsettable_operand (operands[0], 4);
3652 return \"and%.l %2,%0\;and%.l %R2,%1\";
3654 if (GET_CODE (operands[2]) != REG)
3656 operands[1] = adj_offsettable_operand (operands[2], 4);
3657 return \"and%.l %2,%0\;and%.l %1,%R0\";
3659 return \"and%.l %2,%0\;and%.l %R2,%R0\";
3662 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3663 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3664 ;; can't allocate pseudos into it.
3666 (define_expand "andsi3"
3667 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3668 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3669 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3673 (define_insn "andsi3_internal"
3674 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3675 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3676 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3680 return output_andsi3 (operands);
3683 (define_insn "andsi3_5200"
3684 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3685 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3686 (match_operand:SI 2 "general_operand" "d,dmsK")))]
3690 (define_insn "andhi3"
3691 [(set (match_operand:HI 0 "general_operand" "=m,d")
3692 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3693 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3698 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3699 (and:HI (match_dup 0)
3700 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3705 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3706 (and:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3711 (define_insn "andqi3"
3712 [(set (match_operand:QI 0 "general_operand" "=m,d")
3713 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3714 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3719 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3720 (and:QI (match_dup 0)
3721 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3726 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3727 (and:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3732 ;; inclusive-or instructions
3734 (define_insn "iordi_zext"
3735 [(set (match_operand:DI 0 "general_operand" "=o,d")
3736 (ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn"))
3737 (match_operand:DI 2 "general_operand" "0,0")))]
3744 if (GET_CODE (operands[0]) == REG)
3745 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3747 operands[0] = adj_offsettable_operand (operands[0], 4);
3748 if (GET_MODE (operands[1]) == SImode)
3749 return \"or%.l %1,%0\";
3750 byte_mode = (GET_MODE (operands[1]) == QImode);
3751 if (GET_CODE (operands[0]) == MEM)
3752 operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
3754 return \"or%.b %1,%0\";
3756 return \"or%.w %1,%0\";
3759 ;; "iordi3" is mainly here to help combine().
3760 (define_insn "iordi3"
3761 [(set (match_operand:DI 0 "general_operand" "=o,d")
3762 (ior:DI (match_operand:DI 1 "general_operand" "%0,0")
3763 (match_operand:DI 2 "general_operand" "dn,don")))]
3768 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3769 if (GET_CODE (operands[2]) == CONST_DOUBLE
3770 || GET_CODE (operands[2]) == CONST_INT)
3774 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3776 hi = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
3777 lo = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3782 hi = INTVAL (lo) < 0 ? constm1_rtx : const0_rtx;
3784 switch (INTVAL (hi))
3789 /* FIXME : a scratch register would be welcome here if operand[0]
3790 is not a register */
3791 output_asm_insn (\"move%.l %#-1,%0\", operands);
3797 xoperands[0] = operands[0];
3799 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3802 if (GET_CODE (operands[0]) == REG)
3803 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3805 operands[0] = adj_offsettable_operand (operands[0], 4);
3806 switch (INTVAL (lo))
3811 /* FIXME : a scratch register would be welcome here if operand[0]
3812 is not a register */
3813 output_asm_insn (\"move%.l %#-1,%R0\", operands);
3819 xoperands[0] = operands[0];
3821 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3826 if (GET_CODE (operands[0]) != REG)
3828 operands[1] = adj_offsettable_operand (operands[0], 4);
3829 return \"or%.l %2,%0\;or%.l %R2,%1\";
3831 if (GET_CODE (operands[2]) != REG)
3833 operands[1] = adj_offsettable_operand (operands[2], 4);
3834 return \"or%.l %2,%0\;or%.l %1,%R0\";
3836 return \"or%.l %2,%0\;or%.l %R2,%R0\";
3839 (define_expand "iorsi3"
3840 [(set (match_operand:SI 0 "general_operand" "")
3841 (ior:SI (match_operand:SI 1 "general_operand" "")
3842 (match_operand:SI 2 "general_operand" "")))]
3846 (define_insn "iorsi3_internal"
3847 [(set (match_operand:SI 0 "general_operand" "=m,d")
3848 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3849 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3853 return output_iorsi3 (operands);
3856 (define_insn "iorsi3_5200"
3857 [(set (match_operand:SI 0 "general_operand" "=m,d")
3858 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3859 (match_operand:SI 2 "general_operand" "d,dmsK")))]
3863 (define_insn "iorhi3"
3864 [(set (match_operand:HI 0 "general_operand" "=m,d")
3865 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3866 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3871 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3872 (ior:HI (match_dup 0)
3873 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3878 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3879 (ior:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3884 (define_insn "iorqi3"
3885 [(set (match_operand:QI 0 "general_operand" "=m,d")
3886 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3887 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3892 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3893 (ior:QI (match_dup 0)
3894 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3899 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3900 (ior:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3905 ;; On all 68k models, this makes faster code in a special case.
3906 ;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
3908 (define_insn "iorsi_zexthi_ashl16"
3909 [(set (match_operand:SI 0 "general_operand" "=&d")
3910 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "rmn"))
3911 (ashift:SI (match_operand:SI 2 "general_operand" "or")
3917 if (GET_CODE (operands[2]) != REG)
3918 operands[2] = adj_offsettable_operand (operands[2], 2);
3919 if (GET_CODE (operands[2]) != REG
3920 || REGNO (operands[2]) != REGNO (operands[0]))
3921 output_asm_insn (\"move%.w %2,%0\", operands);
3922 return \"swap %0\;mov%.w %1,%0\";
3925 (define_insn "iorsi_zext"
3926 [(set (match_operand:SI 0 "general_operand" "=o,d")
3927 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3928 (match_operand:SI 2 "general_operand" "0,0")))]
3935 byte_mode = (GET_MODE (operands[1]) == QImode);
3936 if (GET_CODE (operands[0]) == MEM)
3937 operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
3939 return \"or%.b %1,%0\";
3941 return \"or%.w %1,%0\";
3946 ;; "xordi3" is mainly here to help combine().
3947 (define_insn "xordi3"
3948 [(set (match_operand:DI 0 "general_operand" "=od")
3949 (xor:DI (match_operand:DI 1 "general_operand" "%0")
3950 (match_operand:DI 2 "general_operand" "dn")))]
3955 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3956 if (GET_CODE (operands[2]) == CONST_DOUBLE
3957 || GET_CODE (operands[2]) == CONST_INT)
3961 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3963 hi = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
3964 lo = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3969 hi = INTVAL (lo) < 0 ? constm1_rtx : const0_rtx;
3971 switch (INTVAL (hi))
3976 output_asm_insn (\"not%.l %0\", operands);
3979 /* FIXME : a scratch register would be welcome here if
3980 -128 <= INTVAL (hi) < -1 */
3984 xoperands[0] = operands[0];
3986 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3989 if (GET_CODE (operands[0]) == REG)
3990 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3992 operands[0] = adj_offsettable_operand (operands[0], 4);
3993 switch (INTVAL (lo))
3998 output_asm_insn (\"not%.l %0\", operands);
4001 /* FIXME : a scratch register would be welcome here if
4002 -128 <= INTVAL (lo) < -1 */
4004 /* FIXME : this should be merged with xorsi3 */
4008 xoperands[0] = operands[0];
4010 output_asm_insn (output_xorsi3 (xoperands), xoperands);
4015 if (GET_CODE (operands[0]) != REG)
4017 operands[1] = adj_offsettable_operand (operands[0], 4);
4018 return \"eor%.l %2,%0\;eor%.l %R2,%1\";
4020 if (GET_CODE (operands[2]) != REG)
4022 operands[1] = adj_offsettable_operand (operands[2], 4);
4023 return \"eor%.l %2,%0\;eor%.l %1,%R0\";
4025 return \"eor%.l %2,%0\;eor%.l %R2,%R0\";
4028 (define_expand "xorsi3"
4029 [(set (match_operand:SI 0 "general_operand" "")
4030 (xor:SI (match_operand:SI 1 "general_operand" "")
4031 (match_operand:SI 2 "general_operand" "")))]
4035 (define_insn "xorsi3_internal"
4036 [(set (match_operand:SI 0 "general_operand" "=do,m")
4037 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
4038 (match_operand:SI 2 "general_operand" "di,dKs")))]
4042 return output_xorsi3 (operands);
4045 (define_insn "xorsi3_5200"
4046 [(set (match_operand:SI 0 "general_operand" "=dm,d")
4047 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
4048 (match_operand:SI 2 "general_operand" "d,Ks")))]
4052 (define_insn "xorhi3"
4053 [(set (match_operand:HI 0 "general_operand" "=dm")
4054 (xor:HI (match_operand:HI 1 "general_operand" "%0")
4055 (match_operand:HI 2 "general_operand" "dn")))]
4060 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4061 (xor:HI (match_dup 0)
4062 (match_operand:HI 1 "general_operand" "dn")))]
4067 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4068 (xor:HI (match_operand:HI 1 "general_operand" "dn")
4073 (define_insn "xorqi3"
4074 [(set (match_operand:QI 0 "general_operand" "=dm")
4075 (xor:QI (match_operand:QI 1 "general_operand" "%0")
4076 (match_operand:QI 2 "general_operand" "dn")))]
4081 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4082 (xor:QI (match_dup 0)
4083 (match_operand:QI 1 "general_operand" "dn")))]
4088 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4089 (xor:QI (match_operand:QI 1 "general_operand" "dn")
4094 ;; negation instructions
4096 (define_expand "negdi2"
4097 [(set (match_operand:DI 0 "general_operand" "")
4098 (neg:DI (match_operand:DI 1 "general_operand" "")))]
4103 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
4105 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
4109 (define_insn "negdi2_internal"
4110 [(set (match_operand:DI 0 "general_operand" "=<,do,!*a")
4111 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
4115 if (which_alternative == 0)
4116 return \"neg%.l %0\;negx%.l %0\";
4117 if (GET_CODE (operands[0]) == REG)
4118 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4120 operands[1] = adj_offsettable_operand (operands[0], 4);
4121 if (ADDRESS_REG_P (operands[0]))
4122 return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
4124 return \"neg%.l %1\;negx%.l %0\";
4127 (define_insn "negdi2_5200"
4128 [(set (match_operand:DI 0 "general_operand" "=d")
4129 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
4133 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4134 return \"neg%.l %1\;negx%.l %0\";
4137 (define_expand "negsi2"
4138 [(set (match_operand:SI 0 "general_operand" "")
4139 (neg:SI (match_operand:SI 1 "general_operand" "")))]
4144 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
4146 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
4150 (define_insn "negsi2_internal"
4151 [(set (match_operand:SI 0 "general_operand" "=dm")
4152 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4156 (define_insn "negsi2_5200"
4157 [(set (match_operand:SI 0 "general_operand" "=d")
4158 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4162 (define_insn "neghi2"
4163 [(set (match_operand:HI 0 "general_operand" "=dm")
4164 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
4169 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4170 (neg:HI (match_dup 0)))]
4174 (define_insn "negqi2"
4175 [(set (match_operand:QI 0 "general_operand" "=dm")
4176 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
4181 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4182 (neg:QI (match_dup 0)))]
4186 ;; If using software floating point, just flip the sign bit.
4188 (define_expand "negsf2"
4189 [(set (match_operand:SF 0 "general_operand" "")
4190 (neg:SF (match_operand:SF 1 "general_operand" "")))]
4194 if (!TARGET_FPA && !TARGET_68881)
4199 target = operand_subword_force (operands[0], 0, SFmode);
4200 result = expand_binop (SImode, xor_optab,
4201 operand_subword_force (operands[1], 0, SFmode),
4202 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
4206 if (result != target)
4207 emit_move_insn (result, target);
4209 /* Make a place for REG_EQUAL. */
4210 emit_move_insn (operands[0], operands[0]);
4216 [(set (match_operand:SF 0 "general_operand" "=x,y")
4217 (neg:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4222 [(set (match_operand:SF 0 "general_operand" "=f,d")
4223 (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))]
4227 if (DATA_REG_P (operands[0]))
4229 operands[1] = GEN_INT (31);
4230 return \"bchg %1,%0\";
4232 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4233 return \"f%$neg%.x %1,%0\";
4234 return \"f%$neg%.s %f1,%0\";
4237 (define_expand "negdf2"
4238 [(set (match_operand:DF 0 "general_operand" "")
4239 (neg:DF (match_operand:DF 1 "general_operand" "")))]
4243 if (!TARGET_FPA && !TARGET_68881)
4250 target = operand_subword (operands[0], 0, 1, DFmode);
4251 result = expand_binop (SImode, xor_optab,
4252 operand_subword_force (operands[1], 0, DFmode),
4253 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
4257 if (result != target)
4258 emit_move_insn (result, target);
4260 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4261 operand_subword_force (operands[1], 1, DFmode));
4263 insns = get_insns ();
4266 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4272 [(set (match_operand:DF 0 "general_operand" "=x,y")
4273 (neg:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4278 [(set (match_operand:DF 0 "general_operand" "=f,d")
4279 (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
4283 if (DATA_REG_P (operands[0]))
4285 operands[1] = GEN_INT (31);
4286 return \"bchg %1,%0\";
4288 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4289 return \"f%&neg%.x %1,%0\";
4290 return \"f%&neg%.d %f1,%0\";
4293 ;; Sqrt instruction for the 68881
4295 (define_insn "sqrtsf2"
4296 [(set (match_operand:SF 0 "general_operand" "=f")
4297 (sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
4301 if (FP_REG_P (operands[1]))
4302 return \"f%$sqrt%.x %1,%0\";
4304 return \"f%$sqrt%.s %1,%0\";
4307 (define_insn "sqrtdf2"
4308 [(set (match_operand:DF 0 "general_operand" "=f")
4309 (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
4313 if (FP_REG_P (operands[1]))
4314 return \"f%&sqrt%.x %1,%0\";
4316 return \"f%&sqrt%.d %1,%0\";
4319 ;; Absolute value instructions
4320 ;; If using software floating point, just zero the sign bit.
4322 (define_expand "abssf2"
4323 [(set (match_operand:SF 0 "general_operand" "")
4324 (abs:SF (match_operand:SF 1 "general_operand" "")))]
4328 if (!TARGET_FPA && !TARGET_68881)
4333 target = operand_subword_force (operands[0], 0, SFmode);
4334 result = expand_binop (SImode, and_optab,
4335 operand_subword_force (operands[1], 0, SFmode),
4336 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
4340 if (result != target)
4341 emit_move_insn (result, target);
4343 /* Make a place for REG_EQUAL. */
4344 emit_move_insn (operands[0], operands[0]);
4350 [(set (match_operand:SF 0 "general_operand" "=x,y")
4351 (abs:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4356 [(set (match_operand:SF 0 "general_operand" "=f")
4357 (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
4361 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4362 return \"f%$abs%.x %1,%0\";
4363 return \"f%$abs%.s %f1,%0\";
4366 (define_expand "absdf2"
4367 [(set (match_operand:DF 0 "general_operand" "")
4368 (abs:DF (match_operand:DF 1 "general_operand" "")))]
4372 if (!TARGET_FPA && !TARGET_68881)
4379 target = operand_subword (operands[0], 0, 1, DFmode);
4380 result = expand_binop (SImode, and_optab,
4381 operand_subword_force (operands[1], 0, DFmode),
4382 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
4386 if (result != target)
4387 emit_move_insn (result, target);
4389 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4390 operand_subword_force (operands[1], 1, DFmode));
4392 insns = get_insns ();
4395 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4401 [(set (match_operand:DF 0 "general_operand" "=x,y")
4402 (abs:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4407 [(set (match_operand:DF 0 "general_operand" "=f")
4408 (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
4412 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4413 return \"f%&abs%.x %1,%0\";
4414 return \"f%&abs%.d %f1,%0\";
4417 ;; one complement instructions
4419 ;; "one_cmpldi2" is mainly here to help combine().
4420 (define_insn "one_cmpldi2"
4421 [(set (match_operand:DI 0 "general_operand" "=dm")
4422 (not:DI (match_operand:DI 1 "general_operand" "0")))]
4427 if (GET_CODE (operands[0]) == REG)
4428 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4429 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
4430 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4431 operands[1] = operands[0];
4433 operands[1] = adj_offsettable_operand (operands[0], 4);
4434 return \"not%.l %1\;not%.l %0\";
4437 (define_expand "one_cmplsi2"
4438 [(set (match_operand:SI 0 "general_operand" "")
4439 (not:SI (match_operand:SI 1 "general_operand" "")))]
4444 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
4446 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
4450 (define_insn "one_cmplsi2_internal"
4451 [(set (match_operand:SI 0 "general_operand" "=dm")
4452 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4456 (define_insn "one_cmplsi2_5200"
4457 [(set (match_operand:SI 0 "general_operand" "=d")
4458 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4462 (define_insn "one_cmplhi2"
4463 [(set (match_operand:HI 0 "general_operand" "=dm")
4464 (not:HI (match_operand:HI 1 "general_operand" "0")))]
4469 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4470 (not:HI (match_dup 0)))]
4474 (define_insn "one_cmplqi2"
4475 [(set (match_operand:QI 0 "general_operand" "=dm")
4476 (not:QI (match_operand:QI 1 "general_operand" "0")))]
4481 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4482 (not:QI (match_dup 0)))]
4486 ;; arithmetic shift instructions
4487 ;; We don't need the shift memory by 1 bit instruction
4489 (define_insn "ashldi_extsi"
4490 [(set (match_operand:DI 0 "general_operand" "=ro")
4492 (match_operator:DI 2 "extend_operator"
4493 [(match_operand:SI 1 "general_operand" "rm")])
4499 if (GET_CODE (operands[0]) == REG)
4500 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4502 operands[2] = adj_offsettable_operand (operands[0], 4);
4503 if (ADDRESS_REG_P (operands[0]))
4504 return \"move%.l %1,%0\;sub%.l %2,%2\";
4506 return \"move%.l %1,%0\;clr%.l %2\";
4509 (define_insn "ashldi_sexthi"
4510 [(set (match_operand:DI 0 "general_operand" "=m,a*d")
4511 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
4513 (clobber (match_scratch:SI 2 "=a,X"))]
4518 if (GET_CODE (operands[0]) == MEM)
4520 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4521 return \"clr%.l %0\;move%.w %1,%2\;move%.l %2,%0\";
4522 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4523 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %0\";
4526 operands[3] = adj_offsettable_operand (operands[0], 4);
4527 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %3\";
4530 else if (DATA_REG_P (operands[0]))
4531 return \"move%.w %1,%0\;ext%.l %0\;clr%.l %R0\";
4533 return \"move%.w %1,%0\;sub%.l %R0,%R0\";
4536 (define_insn "ashldi_const32"
4537 [(set (match_operand:DI 0 "general_operand" "=rm")
4538 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
4544 if (GET_CODE (operands[1]) == REG)
4545 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4547 operands[3] = adj_offsettable_operand (operands[1], 4);
4548 if (GET_CODE (operands[0]) == REG)
4549 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4550 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4551 return \"clr%.l %0\;move%.l %3,%0\";
4552 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4553 return \"move%.l %3,%0\;clr%.l %0\";
4555 operands[2] = adj_offsettable_operand (operands[0], 4);
4556 if (ADDRESS_REG_P (operands[2]))
4557 return \"move%.l %3,%0\;sub%.l %2,%2\";
4559 return \"move%.l %3,%0\;clr%.l %2\";
4562 ;; The predicate below must be general_operand, because ashldi3 allows that
4563 (define_insn "ashldi_const"
4564 [(set (match_operand:DI 0 "general_operand" "=d")
4565 (ashift:DI (match_operand:DI 1 "general_operand" "0")
4566 (match_operand 2 "const_int_operand" "n")))]
4568 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4569 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4570 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4573 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4574 if (INTVAL (operands[2]) == 1)
4575 return \"add%.l %1,%1\;addx%.l %0,%0\";
4576 else if (INTVAL (operands[2]) == 8)
4577 return \"rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1\";
4578 else if (INTVAL (operands[2]) == 16)
4579 return \"swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1\";
4580 else if (INTVAL (operands[2]) == 48)
4581 return \"mov%.l %1,%0\;swap %0\;clr%.l %1\;clr%.w %0\";
4582 else if (INTVAL (operands[2]) == 2)
4583 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4584 else if (INTVAL (operands[2]) == 3)
4585 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4586 else /* 32 < INTVAL (operands[2]) <= 63 */
4588 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4589 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asl%.l %2,%1\" :
4590 \"moveq %2,%0\;asl%.l %0,%1\", operands);
4591 return \"mov%.l %1,%0\;moveq %#0,%1\";
4595 (define_expand "ashldi3"
4596 [(set (match_operand:DI 0 "general_operand" "")
4597 (ashift:DI (match_operand:DI 1 "general_operand" "")
4598 (match_operand 2 "const_int_operand" "")))]
4602 /* ??? This is a named pattern like this is not allowed to FAIL based
4604 if (GET_CODE (operands[2]) != CONST_INT
4605 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4606 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4607 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4611 ;; On most 68k models, this makes faster code in a special case.
4613 (define_insn "ashlsi_16"
4614 [(set (match_operand:SI 0 "register_operand" "=d")
4615 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4621 return \"swap %0\;clr%.w %0\";
4624 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
4625 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
4627 ;; On the 68000, this makes faster code in a special case.
4629 (define_insn "ashlsi_17_24"
4630 [(set (match_operand:SI 0 "register_operand" "=d")
4631 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4632 (match_operand:SI 2 "const_int_operand" "n")))]
4633 "(! TARGET_68020 && !TARGET_5200
4634 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4639 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4640 return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\";
4643 (define_insn "ashlsi3"
4644 [(set (match_operand:SI 0 "register_operand" "=d")
4645 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4646 (match_operand:SI 2 "general_operand" "dI")))]
4650 if (operands[2] == const1_rtx)
4652 cc_status.flags = CC_NO_OVERFLOW;
4653 return \"add%.l %0,%0\";
4655 return \"lsl%.l %2,%0\";
4658 (define_insn "ashlhi3"
4659 [(set (match_operand:HI 0 "register_operand" "=d")
4660 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4661 (match_operand:HI 2 "general_operand" "dI")))]
4666 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4667 (ashift:HI (match_dup 0)
4668 (match_operand:HI 1 "general_operand" "dI")))]
4672 (define_insn "ashlqi3"
4673 [(set (match_operand:QI 0 "register_operand" "=d")
4674 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4675 (match_operand:QI 2 "general_operand" "dI")))]
4680 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4681 (ashift:QI (match_dup 0)
4682 (match_operand:QI 1 "general_operand" "dI")))]
4686 ;; On most 68k models, this makes faster code in a special case.
4688 (define_insn "ashrsi_16"
4689 [(set (match_operand:SI 0 "register_operand" "=d")
4690 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4693 "swap %0\;ext%.l %0")
4695 ;; On the 68000, this makes faster code in a special case.
4698 [(set (match_operand:SI 0 "register_operand" "=d")
4699 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4700 (match_operand:SI 2 "const_int_operand" "n")))]
4701 "(! TARGET_68020 && !TARGET_5200
4702 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4705 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4706 return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
4709 (define_insn "subreghi1ashrdi_const32"
4710 [(set (match_operand:HI 0 "general_operand" "=rm")
4711 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4712 (const_int 32)) 1))]
4716 if (GET_CODE (operands[1]) != REG)
4717 operands[1] = adj_offsettable_operand (operands[1], 2);
4718 return \"move%.w %1,%0\";
4721 (define_insn "subregsi1ashrdi_const32"
4722 [(set (match_operand:SI 0 "general_operand" "=rm")
4723 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4724 (const_int 32)) 1))]
4728 return \"move%.l %1,%0\";
4731 (define_insn "ashrdi_const32"
4732 [(set (match_operand:DI 0 "register_operand" "=d")
4733 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4739 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4741 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
4743 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
4746 (define_insn "ashrdi_const32_mem"
4747 [(set (match_operand:DI 0 "general_operand" "=o,<")
4748 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro")
4750 (clobber (match_scratch:SI 2 "=d,d"))]
4755 if (which_alternative == 1)
4756 operands[3] = operands[0];
4758 operands[3] = adj_offsettable_operand (operands[0], 4);
4760 return \"move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0\";
4762 return \"move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\";
4765 ;; The predicate below must be general_operand, because ashrdi3 allows that
4766 (define_insn "ashrdi_const"
4767 [(set (match_operand:DI 0 "general_operand" "=d")
4768 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
4769 (match_operand 2 "const_int_operand" "n")))]
4771 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4772 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4773 || INTVAL (operands[2]) == 31
4774 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4777 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4778 if (INTVAL (operands[2]) == 63)
4779 return \"add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1\";
4781 if (INTVAL (operands[2]) == 1)
4782 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
4783 else if (INTVAL (operands[2]) == 8)
4784 return \"move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1\";
4785 else if (INTVAL (operands[2]) == 16)
4786 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;ext%.l %0\";
4787 else if (INTVAL (operands[2]) == 48)
4788 return \"swap %0\;ext%.l %0\;move%.l %0,%1\;smi %0\;ext%.w %0\";
4789 else if (INTVAL (operands[2]) == 31)
4790 return \"add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0\";
4791 else if (INTVAL (operands[2]) == 2)
4792 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4793 else if (INTVAL (operands[2]) == 3)
4794 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4795 else /* 32 < INTVAL (operands[2]) <= 63 */
4797 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4798 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asr%.l %2,%0\" :
4799 \"moveq %2,%1\;asr%.l %1,%0\", operands);
4800 output_asm_insn (\"mov%.l %0,%1\;smi %0\", operands);
4801 return INTVAL (operands[2]) >= 15 ? \"ext%.w %d0\" :
4802 TARGET_68020 ? \"extb%.l %0\" : \"ext%.w %0\;ext%.l %0\";
4806 (define_expand "ashrdi3"
4807 [(set (match_operand:DI 0 "general_operand" "")
4808 (ashiftrt:DI (match_operand:DI 1 "general_operand" "")
4809 (match_operand 2 "const_int_operand" "")))]
4813 /* ??? This is a named pattern like this is not allowed to FAIL based
4815 if (GET_CODE (operands[2]) != CONST_INT
4816 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4817 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4818 && (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63)))
4822 ;; On all 68k models, this makes faster code in a special case.
4824 (define_insn "ashrsi_31"
4825 [(set (match_operand:SI 0 "register_operand" "=d")
4826 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4831 return \"add%.l %0,%0\;subx%.l %0,%0\";
4834 (define_insn "ashrsi3"
4835 [(set (match_operand:SI 0 "register_operand" "=d")
4836 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4837 (match_operand:SI 2 "general_operand" "dI")))]
4841 (define_insn "ashrhi3"
4842 [(set (match_operand:HI 0 "register_operand" "=d")
4843 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4844 (match_operand:HI 2 "general_operand" "dI")))]
4849 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4850 (ashiftrt:HI (match_dup 0)
4851 (match_operand:HI 1 "general_operand" "dI")))]
4855 (define_insn "ashrqi3"
4856 [(set (match_operand:QI 0 "register_operand" "=d")
4857 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4858 (match_operand:QI 2 "general_operand" "dI")))]
4863 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4864 (ashiftrt:QI (match_dup 0)
4865 (match_operand:QI 1 "general_operand" "dI")))]
4869 ;; logical shift instructions
4871 ;; commented out because of reload problems in 950612-1.c
4874 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4875 ;; (const_int 32)) 1))
4876 ;; (set (match_operand:SI 1 "general_operand" "=dm")
4877 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
4878 ;; (const_int 32)) 1))]
4882 ;; return \"move%.l %0,%1\";
4887 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4888 ;; (const_int 32)) 0))
4889 ;; (set (match_operand:DI 1 "general_operand" "=do")
4890 ;; (lshiftrt:DI (match_dup 0)
4891 ;; (const_int 32)))]
4895 ;; if (GET_CODE (operands[1]) == REG)
4896 ;; operands[2] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4898 ;; operands[2] = adj_offsettable_operand (operands[1], 4);
4899 ;; return \"move%.l %0,%2\;clr%.l %1\";
4902 (define_insn "subreg1lshrdi_const32"
4903 [(set (match_operand:SI 0 "general_operand" "=rm")
4904 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4905 (const_int 32)) 1))]
4909 return \"move%.l %1,%0\";
4912 (define_insn "lshrdi_const32"
4913 [(set (match_operand:DI 0 "general_operand" "=ro,<,>")
4914 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
4920 if (which_alternative == 1)
4921 return \"move%.l %1,%0\;clr%.l %0\";
4922 if (which_alternative == 2)
4923 return \"clr%.l %0\;move%.l %1,%0\";
4924 if (GET_CODE (operands[0]) == REG)
4925 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4927 operands[2] = adj_offsettable_operand (operands[0], 4);
4928 if (GET_CODE (operands[1]) == REG)
4929 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4931 operands[3] = adj_offsettable_operand (operands[1], 4);
4932 if (ADDRESS_REG_P (operands[0]))
4933 return \"move%.l %1,%2\;sub%.l %0,%0\";
4935 return \"move%.l %1,%2\;clr%.l %0\";
4938 ;; The predicate below must be general_operand, because lshrdi3 allows that
4939 (define_insn "lshrdi_const"
4940 [(set (match_operand:DI 0 "general_operand" "=d")
4941 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
4942 (match_operand 2 "const_int_operand" "n")))]
4944 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4945 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4946 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4949 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4950 if (INTVAL (operands[2]) == 63)
4951 return \"add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1\";
4953 if (INTVAL (operands[2]) == 1)
4954 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4955 else if (INTVAL (operands[2]) == 8)
4956 return \"move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1\";
4957 else if (INTVAL (operands[2]) == 16)
4958 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0\";
4959 else if (INTVAL (operands[2]) == 48)
4960 return \"move%.l %0,%1\;clr%.w %1\;clr%.l %0\;swap %1\";
4961 else if (INTVAL (operands[2]) == 2)
4962 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4963 else if (INTVAL (operands[2]) == 3)
4964 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4965 else /* 32 < INTVAL (operands[2]) <= 63 */
4967 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4968 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"lsr%.l %2,%0\" :
4969 \"moveq %2,%1\;lsr%.l %1,%0\", operands);
4970 return \"mov%.l %0,%1\;moveq %#0,%0\";
4974 (define_expand "lshrdi3"
4975 [(set (match_operand:DI 0 "general_operand" "")
4976 (lshiftrt:DI (match_operand:DI 1 "general_operand" "")
4977 (match_operand 2 "const_int_operand" "")))]
4981 /* ??? This is a named pattern like this is not allowed to FAIL based
4983 if (GET_CODE (operands[2]) != CONST_INT
4984 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4985 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4986 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4990 ;; On all 68k models, this makes faster code in a special case.
4992 (define_insn "lshrsi_31"
4993 [(set (match_operand:SI 0 "register_operand" "=d")
4994 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4999 return \"add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0\";
5002 ;; On most 68k models, this makes faster code in a special case.
5004 (define_insn "lshrsi_16"
5005 [(set (match_operand:SI 0 "register_operand" "=d")
5006 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5012 return \"clr%.w %0\;swap %0\";
5015 ;; On the 68000, this makes faster code in a special case.
5017 (define_insn "lshrsi_17_24"
5018 [(set (match_operand:SI 0 "register_operand" "=d")
5019 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5020 (match_operand:SI 2 "const_int_operand" "n")))]
5021 "(! TARGET_68020 && !TARGET_5200
5022 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
5025 /* I think lsr%.w sets the CC properly. */
5026 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
5027 return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\";
5030 (define_insn "lshrsi3"
5031 [(set (match_operand:SI 0 "register_operand" "=d")
5032 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5033 (match_operand:SI 2 "general_operand" "dI")))]
5037 (define_insn "lshrhi3"
5038 [(set (match_operand:HI 0 "register_operand" "=d")
5039 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
5040 (match_operand:HI 2 "general_operand" "dI")))]
5045 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5046 (lshiftrt:HI (match_dup 0)
5047 (match_operand:HI 1 "general_operand" "dI")))]
5051 (define_insn "lshrqi3"
5052 [(set (match_operand:QI 0 "register_operand" "=d")
5053 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
5054 (match_operand:QI 2 "general_operand" "dI")))]
5059 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5060 (lshiftrt:QI (match_dup 0)
5061 (match_operand:QI 1 "general_operand" "dI")))]
5065 ;; rotate instructions
5067 (define_insn "rotlsi3"
5068 [(set (match_operand:SI 0 "register_operand" "=d")
5069 (rotate:SI (match_operand:SI 1 "register_operand" "0")
5070 (match_operand:SI 2 "general_operand" "dINO")))]
5074 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
5076 else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
5078 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
5079 return \"ror%.l %2,%0\";
5082 return \"rol%.l %2,%0\";
5085 (define_insn "rotlhi3"
5086 [(set (match_operand:HI 0 "register_operand" "=d")
5087 (rotate:HI (match_operand:HI 1 "register_operand" "0")
5088 (match_operand:HI 2 "general_operand" "dIP")))]
5092 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
5094 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
5095 return \"ror%.w %2,%0\";
5098 return \"rol%.w %2,%0\";
5102 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5103 (rotate:HI (match_dup 0)
5104 (match_operand:HI 1 "general_operand" "dIP")))]
5108 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
5110 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
5111 return \"ror%.w %2,%0\";
5114 return \"rol%.w %2,%0\";
5117 (define_insn "rotlqi3"
5118 [(set (match_operand:QI 0 "register_operand" "=d")
5119 (rotate:QI (match_operand:QI 1 "register_operand" "0")
5120 (match_operand:QI 2 "general_operand" "dI")))]
5124 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
5126 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
5127 return \"ror%.b %2,%0\";
5130 return \"rol%.b %2,%0\";
5134 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5135 (rotate:QI (match_dup 0)
5136 (match_operand:QI 1 "general_operand" "dI")))]
5140 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
5142 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
5143 return \"ror%.b %2,%0\";
5146 return \"rol%.b %2,%0\";
5149 (define_insn "rotrsi3"
5150 [(set (match_operand:SI 0 "register_operand" "=d")
5151 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
5152 (match_operand:SI 2 "general_operand" "dI")))]
5156 (define_insn "rotrhi3"
5157 [(set (match_operand:HI 0 "register_operand" "=d")
5158 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
5159 (match_operand:HI 2 "general_operand" "dI")))]
5164 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5165 (rotatert:HI (match_dup 0)
5166 (match_operand:HI 1 "general_operand" "dI")))]
5170 (define_insn "rotrqi3"
5171 [(set (match_operand:QI 0 "register_operand" "=d")
5172 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
5173 (match_operand:QI 2 "general_operand" "dI")))]
5178 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5179 (rotatert:QI (match_dup 0)
5180 (match_operand:QI 1 "general_operand" "dI")))]
5185 ;; Bit set/clear in memory byte.
5187 ;; set bit, bit number is int
5188 (define_insn "bsetmemqi"
5189 [(set (match_operand:QI 0 "memory_operand" "+m")
5190 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5191 (match_operand:SI 1 "general_operand" "d")) 0)
5197 return \"bset %1,%0\";
5200 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
5202 [(set (match_operand:QI 0 "memory_operand" "+m")
5203 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5204 (match_operator:SI 2 "extend_operator"
5205 [(match_operand 1 "general_operand" "d")])) 0)
5211 return \"bset %1,%0\";
5214 ;; clear bit, bit number is int
5215 (define_insn "bclrmemqi"
5216 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5218 (minus:SI (const_int 7)
5219 (match_operand:SI 1 "general_operand" "d")))
5225 return \"bclr %1,%0\";
5228 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
5230 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5232 (minus:SI (const_int 7)
5233 (match_operator:SI 2 "extend_operator"
5234 [(match_operand 1 "general_operand" "d")])))
5240 return \"bclr %1,%0\";
5243 ;; Special cases of bit-field insns which we should
5244 ;; recognize in preference to the general case.
5245 ;; These handle aligned 8-bit and 16-bit fields,
5246 ;; which can usually be done with move instructions.
5249 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5250 ; alignment of structure members is specified.
5252 ; The move is allowed to be odd byte aligned, because that's still faster
5253 ; than an odd byte aligned bit field instruction.
5256 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5258 (match_operand:SI 2 "const_int_operand" "n"))
5259 (match_operand:SI 3 "general_operand" "rmi"))]
5260 "TARGET_68020 && TARGET_BITFIELD
5261 && (INTVAL (operands[2]) % 8) == 0
5262 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
5266 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
5268 return \"move%.l %3,%0\";
5272 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
5273 (match_operand:SI 1 "const_int_operand" "n")
5274 (match_operand:SI 2 "const_int_operand" "n"))
5275 (match_operand:SI 3 "register_operand" "d"))]
5276 "TARGET_68020 && TARGET_BITFIELD
5277 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
5278 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
5279 && (GET_CODE (operands[0]) == REG
5280 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
5283 if (REG_P (operands[0]))
5285 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
5286 return \"bfins %3,%0{%b2:%b1}\";
5290 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
5292 if (GET_CODE (operands[3]) == MEM)
5293 operands[3] = adj_offsettable_operand (operands[3],
5294 (32 - INTVAL (operands[1])) / 8);
5295 if (INTVAL (operands[1]) == 8)
5296 return \"move%.b %3,%0\";
5297 return \"move%.w %3,%0\";
5302 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5303 ; alignment of structure members is specified.
5305 ; The move is allowed to be odd byte aligned, because that's still faster
5306 ; than an odd byte aligned bit field instruction.
5309 [(set (match_operand:SI 0 "general_operand" "=rm")
5310 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o")
5312 (match_operand:SI 3 "const_int_operand" "n")))]
5313 "TARGET_68020 && TARGET_BITFIELD
5314 && (INTVAL (operands[3]) % 8) == 0
5315 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5319 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5321 return \"move%.l %1,%0\";
5325 [(set (match_operand:SI 0 "general_operand" "=&d")
5326 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
5327 (match_operand:SI 2 "const_int_operand" "n")
5328 (match_operand:SI 3 "const_int_operand" "n")))]
5329 "TARGET_68020 && TARGET_BITFIELD
5330 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5331 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5332 && (GET_CODE (operands[1]) == REG
5333 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5336 cc_status.flags |= CC_NOT_NEGATIVE;
5337 if (REG_P (operands[1]))
5339 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5340 return \"bfextu %1{%b3:%b2},%0\";
5344 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5346 output_asm_insn (\"clr%.l %0\", operands);
5347 if (GET_CODE (operands[0]) == MEM)
5348 operands[0] = adj_offsettable_operand (operands[0],
5349 (32 - INTVAL (operands[1])) / 8);
5350 if (INTVAL (operands[2]) == 8)
5351 return \"move%.b %1,%0\";
5352 return \"move%.w %1,%0\";
5356 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5357 ; alignment of structure members is specified.
5359 ; The move is allowed to be odd byte aligned, because that's still faster
5360 ; than an odd byte aligned bit field instruction.
5363 [(set (match_operand:SI 0 "general_operand" "=rm")
5364 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5366 (match_operand:SI 3 "const_int_operand" "n")))]
5367 "TARGET_68020 && TARGET_BITFIELD
5368 && (INTVAL (operands[3]) % 8) == 0
5369 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5373 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5375 return \"move%.l %1,%0\";
5379 [(set (match_operand:SI 0 "general_operand" "=d")
5380 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
5381 (match_operand:SI 2 "const_int_operand" "n")
5382 (match_operand:SI 3 "const_int_operand" "n")))]
5383 "TARGET_68020 && TARGET_BITFIELD
5384 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5385 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5386 && (GET_CODE (operands[1]) == REG
5387 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5390 if (REG_P (operands[1]))
5392 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5393 return \"bfexts %1{%b3:%b2},%0\";
5397 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5399 if (INTVAL (operands[2]) == 8)
5400 return \"move%.b %1,%0\;extb%.l %0\";
5401 return \"move%.w %1,%0\;ext%.l %0\";
5404 ;; Bit field instructions, general cases.
5405 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
5406 ;; so that its address is reloaded.
5408 (define_expand "extv"
5409 [(set (match_operand:SI 0 "general_operand" "")
5410 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
5411 (match_operand:SI 2 "general_operand" "")
5412 (match_operand:SI 3 "general_operand" "")))]
5413 "TARGET_68020 && TARGET_BITFIELD"
5417 [(set (match_operand:SI 0 "general_operand" "=d")
5418 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5419 (match_operand:SI 2 "general_operand" "di")
5420 (match_operand:SI 3 "general_operand" "di")))]
5421 "TARGET_68020 && TARGET_BITFIELD"
5422 "bfexts %1{%b3:%b2},%0")
5424 (define_expand "extzv"
5425 [(set (match_operand:SI 0 "general_operand" "")
5426 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
5427 (match_operand:SI 2 "general_operand" "")
5428 (match_operand:SI 3 "general_operand" "")))]
5429 "TARGET_68020 && TARGET_BITFIELD"
5433 [(set (match_operand:SI 0 "general_operand" "=d,d")
5434 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
5435 (match_operand:SI 2 "general_operand" "di,di")
5436 (match_operand:SI 3 "general_operand" "di,di")))]
5437 "TARGET_68020 && TARGET_BITFIELD"
5440 if (GET_CODE (operands[2]) == CONST_INT)
5442 if (INTVAL (operands[2]) != 32)
5443 cc_status.flags |= CC_NOT_NEGATIVE;
5449 return \"bfextu %1{%b3:%b2},%0\";
5453 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5454 (match_operand:SI 1 "general_operand" "di")
5455 (match_operand:SI 2 "general_operand" "di"))
5456 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
5457 (match_operand 3 "const_int_operand" "n")))]
5458 "TARGET_68020 && TARGET_BITFIELD
5459 && (INTVAL (operands[3]) == -1
5460 || (GET_CODE (operands[1]) == CONST_INT
5461 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
5465 return \"bfchg %0{%b2:%b1}\";
5469 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5470 (match_operand:SI 1 "general_operand" "di")
5471 (match_operand:SI 2 "general_operand" "di"))
5473 "TARGET_68020 && TARGET_BITFIELD"
5477 return \"bfclr %0{%b2:%b1}\";
5481 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5482 (match_operand:SI 1 "general_operand" "di")
5483 (match_operand:SI 2 "general_operand" "di"))
5485 "TARGET_68020 && TARGET_BITFIELD"
5489 return \"bfset %0{%b2:%b1}\";
5492 (define_expand "insv"
5493 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
5494 (match_operand:SI 1 "general_operand" "")
5495 (match_operand:SI 2 "general_operand" ""))
5496 (match_operand:SI 3 "register_operand" ""))]
5497 "TARGET_68020 && TARGET_BITFIELD"
5501 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5502 (match_operand:SI 1 "general_operand" "di")
5503 (match_operand:SI 2 "general_operand" "di"))
5504 (match_operand:SI 3 "register_operand" "d"))]
5505 "TARGET_68020 && TARGET_BITFIELD"
5506 "bfins %3,%0{%b2:%b1}")
5508 ;; Now recognize bit field insns that operate on registers
5509 ;; (or at least were intended to do so).
5512 [(set (match_operand:SI 0 "general_operand" "=d")
5513 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5514 (match_operand:SI 2 "general_operand" "di")
5515 (match_operand:SI 3 "general_operand" "di")))]
5516 "TARGET_68020 && TARGET_BITFIELD"
5517 "bfexts %1{%b3:%b2},%0")
5520 [(set (match_operand:SI 0 "general_operand" "=d")
5521 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5522 (match_operand:SI 2 "general_operand" "di")
5523 (match_operand:SI 3 "general_operand" "di")))]
5524 "TARGET_68020 && TARGET_BITFIELD"
5527 if (GET_CODE (operands[2]) == CONST_INT)
5529 if (INTVAL (operands[2]) != 32)
5530 cc_status.flags |= CC_NOT_NEGATIVE;
5536 return \"bfextu %1{%b3:%b2},%0\";
5540 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5541 (match_operand:SI 1 "general_operand" "di")
5542 (match_operand:SI 2 "general_operand" "di"))
5544 "TARGET_68020 && TARGET_BITFIELD"
5548 return \"bfclr %0{%b2:%b1}\";
5552 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5553 (match_operand:SI 1 "general_operand" "di")
5554 (match_operand:SI 2 "general_operand" "di"))
5556 "TARGET_68020 && TARGET_BITFIELD"
5560 return \"bfset %0{%b2:%b1}\";
5564 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5565 (match_operand:SI 1 "general_operand" "di")
5566 (match_operand:SI 2 "general_operand" "di"))
5567 (match_operand:SI 3 "register_operand" "d"))]
5568 "TARGET_68020 && TARGET_BITFIELD"
5572 /* These special cases are now recognized by a specific pattern. */
5573 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5574 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5575 return \"move%.w %3,%0\";
5576 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5577 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
5578 return \"move%.b %3,%0\";
5580 return \"bfins %3,%0{%b2:%b1}\";
5583 ;; Special patterns for optimizing bit-field instructions.
5587 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5588 (match_operand:SI 1 "const_int_operand" "n")
5589 (match_operand:SI 2 "general_operand" "di")))]
5590 "TARGET_68020 && TARGET_BITFIELD"
5593 if (operands[1] == const1_rtx
5594 && GET_CODE (operands[2]) == CONST_INT)
5596 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5597 return output_btst (operands,
5598 GEN_INT (width - INTVAL (operands[2])),
5601 /* Pass 1000 as SIGNPOS argument so that btst will
5602 not think we are testing the sign bit for an `and'
5603 and assume that nonzero implies a negative result. */
5605 if (INTVAL (operands[1]) != 32)
5606 cc_status.flags = CC_NOT_NEGATIVE;
5607 return \"bftst %0{%b2:%b1}\";
5611 ;;; now handle the register cases
5614 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5615 (match_operand:SI 1 "const_int_operand" "n")
5616 (match_operand:SI 2 "general_operand" "di")))]
5617 "TARGET_68020 && TARGET_BITFIELD"
5620 if (operands[1] == const1_rtx
5621 && GET_CODE (operands[2]) == CONST_INT)
5623 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5624 return output_btst (operands,
5625 GEN_INT (width - INTVAL (operands[2])),
5628 /* Pass 1000 as SIGNPOS argument so that btst will
5629 not think we are testing the sign bit for an `and'
5630 and assume that nonzero implies a negative result. */
5632 if (INTVAL (operands[1]) != 32)
5633 cc_status.flags = CC_NOT_NEGATIVE;
5634 return \"bftst %0{%b2:%b1}\";
5637 (define_insn "scc0_di"
5638 [(set (match_operand:QI 0 "general_operand" "=dm")
5639 (match_operator 1 "valid_dbcc_comparison_p"
5640 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5644 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5647 (define_insn "scc0_di_5200"
5648 [(set (match_operand:QI 0 "general_operand" "=d")
5649 (match_operator 1 "valid_dbcc_comparison_p"
5650 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5654 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5657 (define_insn "scc_di"
5658 [(set (match_operand:QI 0 "general_operand" "=dm,dm")
5659 (match_operator 1 "valid_dbcc_comparison_p"
5660 [(match_operand:DI 2 "general_operand" "ro,r")
5661 (match_operand:DI 3 "general_operand" "r,ro")]))]
5665 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5668 (define_insn "scc_di_5200"
5669 [(set (match_operand:QI 0 "general_operand" "=d,d")
5670 (match_operator 1 "valid_dbcc_comparison_p"
5671 [(match_operand:DI 2 "general_operand" "ro,r")
5672 (match_operand:DI 3 "general_operand" "r,ro")]))]
5676 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5679 ;; Note that operand 0 of an SCC insn is supported in the hardware as
5680 ;; memory, but we cannot allow it to be in memory in case the address
5681 ;; needs to be reloaded.
5683 (define_expand "seq"
5684 [(set (match_operand:QI 0 "register_operand" "")
5685 (eq:QI (cc0) (const_int 0)))]
5689 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5691 m68k_last_compare_had_fp_operands = 0;
5697 [(set (match_operand:QI 0 "register_operand" "=d")
5698 (eq:QI (cc0) (const_int 0)))]
5701 cc_status = cc_prev_status;
5702 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5705 (define_expand "sne"
5706 [(set (match_operand:QI 0 "register_operand" "")
5707 (ne:QI (cc0) (const_int 0)))]
5711 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5713 m68k_last_compare_had_fp_operands = 0;
5719 [(set (match_operand:QI 0 "register_operand" "=d")
5720 (ne:QI (cc0) (const_int 0)))]
5723 cc_status = cc_prev_status;
5724 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5727 (define_expand "sgt"
5728 [(set (match_operand:QI 0 "register_operand" "")
5729 (gt:QI (cc0) (const_int 0)))]
5733 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5735 m68k_last_compare_had_fp_operands = 0;
5741 [(set (match_operand:QI 0 "register_operand" "=d")
5742 (gt:QI (cc0) (const_int 0)))]
5745 cc_status = cc_prev_status;
5746 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5749 (define_expand "sgtu"
5750 [(set (match_operand:QI 0 "register_operand" "")
5751 (gtu:QI (cc0) (const_int 0)))]
5756 [(set (match_operand:QI 0 "register_operand" "=d")
5757 (gtu:QI (cc0) (const_int 0)))]
5760 cc_status = cc_prev_status;
5761 return \"shi %0\"; ")
5763 (define_expand "slt"
5764 [(set (match_operand:QI 0 "register_operand" "")
5765 (lt:QI (cc0) (const_int 0)))]
5769 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5771 m68k_last_compare_had_fp_operands = 0;
5777 [(set (match_operand:QI 0 "register_operand" "=d")
5778 (lt:QI (cc0) (const_int 0)))]
5781 cc_status = cc_prev_status;
5782 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5784 (define_expand "sltu"
5785 [(set (match_operand:QI 0 "register_operand" "")
5786 (ltu:QI (cc0) (const_int 0)))]
5791 [(set (match_operand:QI 0 "register_operand" "=d")
5792 (ltu:QI (cc0) (const_int 0)))]
5795 cc_status = cc_prev_status;
5796 return \"scs %0\"; ")
5798 (define_expand "sge"
5799 [(set (match_operand:QI 0 "register_operand" "")
5800 (ge:QI (cc0) (const_int 0)))]
5804 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5806 m68k_last_compare_had_fp_operands = 0;
5812 [(set (match_operand:QI 0 "register_operand" "=d")
5813 (ge:QI (cc0) (const_int 0)))]
5816 cc_status = cc_prev_status;
5817 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5819 (define_expand "sgeu"
5820 [(set (match_operand:QI 0 "register_operand" "")
5821 (geu:QI (cc0) (const_int 0)))]
5826 [(set (match_operand:QI 0 "register_operand" "=d")
5827 (geu:QI (cc0) (const_int 0)))]
5830 cc_status = cc_prev_status;
5831 return \"scc %0\"; ")
5833 (define_expand "sle"
5834 [(set (match_operand:QI 0 "register_operand" "")
5835 (le:QI (cc0) (const_int 0)))]
5839 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5841 m68k_last_compare_had_fp_operands = 0;
5847 [(set (match_operand:QI 0 "register_operand" "=d")
5848 (le:QI (cc0) (const_int 0)))]
5851 cc_status = cc_prev_status;
5852 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5855 (define_expand "sleu"
5856 [(set (match_operand:QI 0 "register_operand" "")
5857 (leu:QI (cc0) (const_int 0)))]
5862 [(set (match_operand:QI 0 "register_operand" "=d")
5863 (leu:QI (cc0) (const_int 0)))]
5866 cc_status = cc_prev_status;
5867 return \"sls %0\"; ")
5869 ;; Basic conditional jump instructions.
5871 (define_insn "beq0_di"
5873 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
5875 (label_ref (match_operand 1 "" ","))
5877 (clobber (match_scratch:SI 2 "=d,d"))]
5882 if (which_alternative == 1)
5884 return \"move%.l %0,%2\;or%.l %0,%2\;jbeq %l1\";
5886 return \"move%.l %0,%2\;or%.l %0,%2\;jeq %l1\";
5888 if ((cc_prev_status.value1
5889 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5890 || (cc_prev_status.value2
5891 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5893 cc_status = cc_prev_status;
5895 return \"jbeq %l1\";
5900 if (GET_CODE (operands[0]) == REG)
5901 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
5903 operands[3] = adj_offsettable_operand (operands[0], 4);
5904 if (! ADDRESS_REG_P (operands[0]))
5906 if (reg_overlap_mentioned_p (operands[2], operands[0]))
5908 if (reg_overlap_mentioned_p (operands[2], operands[3]))
5911 return \"or%.l %0,%2\;jbeq %l1\";
5913 return \"or%.l %0,%2\;jeq %l1\";
5919 return \"or%.l %3,%2\;jbeq %l1\";
5921 return \"or%.l %3,%2\;jeq %l1\";
5926 return \"move%.l %0,%2\;or%.l %3,%2\;jbeq %l1\";
5928 return \"move%.l %0,%2\;or%.l %3,%2\;jeq %l1\";
5931 operands[4] = gen_label_rtx();
5932 if (TARGET_68020 || TARGET_5200)
5935 output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands);
5937 output_asm_insn (\"tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1\", operands);
5943 #ifdef SGS_CMP_ORDER
5944 output_asm_insn (\"cmp%.w %0,%#0\;jbne %l4\;cmp%.w %3,%#0\;jbeq %l1\", operands);
5946 output_asm_insn (\"cmp%.w %#0,%0\;jbne %l4\;cmp%.w %#0,%3\;jbeq %l1\", operands);
5949 output_asm_insn (\"cmp%.w %#0,%0\;jne %l4\;cmp%.w %#0,%3\;jeq %l1\", operands);
5952 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5953 CODE_LABEL_NUMBER (operands[4]));
5957 (define_insn "bne0_di"
5959 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
5961 (label_ref (match_operand 1 "" ","))
5963 (clobber (match_scratch:SI 2 "=d,X"))]
5967 if ((cc_prev_status.value1
5968 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5969 || (cc_prev_status.value2
5970 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5972 cc_status = cc_prev_status;
5974 return \"jbne %l1\";
5980 if (GET_CODE (operands[0]) == REG)
5981 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
5983 operands[3] = adj_offsettable_operand (operands[0], 4);
5984 if (!ADDRESS_REG_P (operands[0]))
5986 if (reg_overlap_mentioned_p (operands[2], operands[0]))
5988 if (reg_overlap_mentioned_p (operands[2], operands[3]))
5991 return \"or%.l %0,%2\;jbne %l1\";
5993 return \"or%.l %0,%2\;jne %l1\";
5999 return \"or%.l %3,%2\;jbne %l1\";
6001 return \"or%.l %3,%2\;jne %l1\";
6006 return \"move%.l %0,%2\;or%.l %3,%2\;jbne %l1\";
6008 return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\";
6011 if (TARGET_68020 || TARGET_5200)
6014 return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\";
6016 return \"tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1\";
6022 #ifdef SGS_CMP_ORDER
6023 return \"cmp%.w %0,%#0\;jbne %l1\;cmp%.w %3,%#0\;jbne %l1\";
6025 return \"cmp%.w %#0,%0\;jbne %l1\;cmp%.w %#0,%3\;jbne %l1\";
6028 return \"cmp%.w %#0,%0\;jne %l1\;cmp%.w %#0,%3\;jne %l1\";
6033 (define_insn "bge0_di"
6035 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
6037 (label_ref (match_operand 1 "" ""))
6042 if ((cc_prev_status.value1
6043 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6044 || (cc_prev_status.value2
6045 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6047 cc_status = cc_prev_status;
6048 if (cc_status.flags & CC_REVERSED)
6051 return \"jble %l1\";
6059 return \"jbpl %l1\";
6066 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
6067 output_asm_insn(\"tst%.l %0\", operands);
6070 /* On an address reg, cmpw may replace cmpl. */
6071 #ifdef SGS_CMP_ORDER
6072 output_asm_insn(\"cmp%.w %0,%#0\", operands);
6074 output_asm_insn(\"cmp%.w %#0,%0\", operands);
6079 return \"jbpl %l1\";
6085 (define_insn "blt0_di"
6087 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
6089 (label_ref (match_operand 1 "" ""))
6094 if ((cc_prev_status.value1
6095 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6096 || (cc_prev_status.value2
6097 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6099 cc_status = cc_prev_status;
6100 if (cc_status.flags & CC_REVERSED)
6103 return \"jbgt %l1\";
6111 return \"jbmi %l1\";
6118 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
6119 output_asm_insn(\"tst%.l %0\", operands);
6122 /* On an address reg, cmpw may replace cmpl. */
6123 #ifdef SGS_CMP_ORDER
6124 output_asm_insn(\"cmp%.w %0,%#0\", operands);
6126 output_asm_insn(\"cmp%.w %#0,%0\", operands);
6131 return \"jbmi %l1\";
6139 (if_then_else (eq (cc0)
6141 (label_ref (match_operand 0 "" ""))
6147 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6149 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6155 (if_then_else (ne (cc0)
6157 (label_ref (match_operand 0 "" ""))
6163 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6165 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6171 (if_then_else (gt (cc0)
6173 (label_ref (match_operand 0 "" ""))
6178 OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0);
6180 OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0);
6186 (if_then_else (gtu (cc0)
6188 (label_ref (match_operand 0 "" ""))
6193 return \"jbhi %l0\";
6201 (if_then_else (lt (cc0)
6203 (label_ref (match_operand 0 "" ""))
6208 OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\");
6210 OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\");
6216 (if_then_else (ltu (cc0)
6218 (label_ref (match_operand 0 "" ""))
6223 return \"jbcs %l0\";
6231 (if_then_else (ge (cc0)
6233 (label_ref (match_operand 0 "" ""))
6238 OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\");
6240 OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\");
6246 (if_then_else (geu (cc0)
6248 (label_ref (match_operand 0 "" ""))
6253 return \"jbcc %l0\";
6261 (if_then_else (le (cc0)
6263 (label_ref (match_operand 0 "" ""))
6268 OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0);
6270 OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0);
6276 (if_then_else (leu (cc0)
6278 (label_ref (match_operand 0 "" ""))
6283 return \"jbls %l0\";
6289 ;; Negated conditional jump instructions.
6293 (if_then_else (eq (cc0)
6296 (label_ref (match_operand 0 "" ""))))]
6301 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6303 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6309 (if_then_else (ne (cc0)
6312 (label_ref (match_operand 0 "" ""))))]
6317 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6319 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6325 (if_then_else (gt (cc0)
6328 (label_ref (match_operand 0 "" ""))))]
6332 OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0);
6334 OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0);
6340 (if_then_else (gtu (cc0)
6343 (label_ref (match_operand 0 "" ""))))]
6347 return \"jbls %l0\";
6355 (if_then_else (lt (cc0)
6358 (label_ref (match_operand 0 "" ""))))]
6362 OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\");
6364 OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\");
6370 (if_then_else (ltu (cc0)
6373 (label_ref (match_operand 0 "" ""))))]
6377 return \"jbcc %l0\";
6385 (if_then_else (ge (cc0)
6388 (label_ref (match_operand 0 "" ""))))]
6392 OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\");
6394 OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\");
6400 (if_then_else (geu (cc0)
6403 (label_ref (match_operand 0 "" ""))))]
6407 return \"jbcs %l0\";
6415 (if_then_else (le (cc0)
6418 (label_ref (match_operand 0 "" ""))))]
6422 OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0);
6424 OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0);
6430 (if_then_else (leu (cc0)
6433 (label_ref (match_operand 0 "" ""))))]
6437 return \"jbhi %l0\";
6443 ;; Unconditional and other jump instructions
6446 (label_ref (match_operand 0 "" "")))]
6450 return \"jbra %l0\";
6456 ;; We support two different ways of handling dispatch tables.
6457 ;; The NeXT uses absolute tables, and other machines use relative.
6458 ;; This define_expand can generate either kind.
6459 (define_expand "tablejump"
6460 [(parallel [(set (pc) (match_operand 0 "" ""))
6461 (use (label_ref (match_operand 1 "" "")))])]
6465 #ifdef CASE_VECTOR_PC_RELATIVE
6466 operands[0] = gen_rtx_PLUS (SImode, pc_rtx,
6467 gen_rtx_SIGN_EXTEND (SImode, operands[0]));
6471 ;; Jump to variable address from dispatch table of absolute addresses.
6473 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
6474 (use (label_ref (match_operand 1 "" "")))]
6478 return \"jmp (%0)\";
6484 ;; Jump to variable address from dispatch table of relative addresses.
6488 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
6489 (use (label_ref (match_operand 1 "" "")))]
6492 #ifdef ASM_RETURN_CASE_JUMP
6493 ASM_RETURN_CASE_JUMP;
6496 #ifdef ASM_OUTPUT_CASE_LABEL
6498 return \"ext%.l %0\;jmp 6(%%pc,%0.l)\";
6500 return \"jmp 6(%%pc,%0.w)\";
6505 return \"ext%.l %0\;jmp 2(pc,%0.l)\";
6507 return \"extl %0\;jmp 2(%%pc,%0.l)\";
6508 #endif /* end !CRDS */
6513 return \"jmp 2(pc,%0.w)\";
6515 return \"jmp 2(%%pc,%0.w)\";
6516 #endif /* end !CRDS */
6523 return \"ext%.l %0\;jmp (2,pc,%0.l)\";
6525 return \"extl %0\;jmp pc@(2,%0:l)\";
6531 return \"jmp (2,pc,%0.w)\";
6533 return \"jmp pc@(2,%0:w)\";
6540 ;; Decrement-and-branch insns.
6544 (ne (match_operand:HI 0 "general_operand" "+d*g")
6546 (label_ref (match_operand 1 "" ""))
6549 (plus:HI (match_dup 0)
6555 if (DATA_REG_P (operands[0]))
6556 return \"dbra %0,%l1\";
6557 if (GET_CODE (operands[0]) == MEM)
6561 return \"sub%.w %#1,%0\;jbcc %l1\";
6563 return \"subq%.w %#1,%0\;jbcc %l1\";
6565 #else /* not MOTOROLA */
6566 return \"subqw %#1,%0\;jcc %l1\";
6570 #ifdef SGS_CMP_ORDER
6572 return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6574 return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6576 #else /* not SGS_CMP_ORDER */
6577 return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
6579 #else /* not MOTOROLA */
6580 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6587 (ne (match_operand:SI 0 "general_operand" "+d*g")
6589 (label_ref (match_operand 1 "" ""))
6592 (plus:SI (match_dup 0)
6600 if (DATA_REG_P (operands[0]))
6601 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6602 if (GET_CODE (operands[0]) == MEM)
6603 return \"sub%.l %#1,%0\;jbcc %l1\";
6605 if (DATA_REG_P (operands[0]))
6606 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6607 if (GET_CODE (operands[0]) == MEM)
6608 return \"subq%.l %#1,%0\;jbcc %l1\";
6609 #endif /* NO_ADDSUB_Q */
6610 #ifdef SGS_CMP_ORDER
6612 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6614 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6616 #else /* not SGS_CMP_ORDER */
6617 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6618 #endif /* not SGS_CMP_ORDER */
6619 #else /* not MOTOROLA */
6620 if (DATA_REG_P (operands[0]))
6621 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6622 if (GET_CODE (operands[0]) == MEM)
6623 return \"subql %#1,%0\;jcc %l1\";
6624 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6625 #endif /* not MOTOROLA */
6628 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
6633 (ge (plus:HI (match_operand:HI 0 "general_operand" "+d*am")
6636 (label_ref (match_operand 1 "" ""))
6639 (plus:HI (match_dup 0)
6641 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6647 if (DATA_REG_P (operands[0]))
6648 return \"dbra %0,%l1\";
6649 if (GET_CODE (operands[0]) == MEM)
6650 return \"sub%.w %#1,%0\;jbcc %l1\";
6652 if (DATA_REG_P (operands[0]))
6653 return \"dbra %0,%l1\";
6654 if (GET_CODE (operands[0]) == MEM)
6655 return \"subq%.w %#1,%0\;jbcc %l1\";
6657 #ifdef SGS_CMP_ORDER
6659 return \"sub.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6661 return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6663 #else /* not SGS_CMP_ORDER */
6664 return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\";
6665 #endif /* not SGS_CMP_ORDER */
6666 #else /* not MOTOROLA */
6667 if (DATA_REG_P (operands[0]))
6668 return \"dbra %0,%l1\";
6669 if (GET_CODE (operands[0]) == MEM)
6670 return \"subqw %#1,%0\;jcc %l1\";
6671 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6672 #endif /* not MOTOROLA */
6675 (define_expand "decrement_and_branch_until_zero"
6676 [(parallel [(set (pc)
6678 (ge (plus:SI (match_operand:SI 0 "general_operand" "")
6681 (label_ref (match_operand 1 "" ""))
6684 (plus:SI (match_dup 0)
6692 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
6695 (label_ref (match_operand 1 "" ""))
6698 (plus:SI (match_dup 0)
6700 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6706 if (DATA_REG_P (operands[0]))
6707 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6708 if (GET_CODE (operands[0]) == MEM)
6709 return \"sub%.l %#1,%0\;jbcc %l1\";
6711 if (DATA_REG_P (operands[0]))
6712 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6713 if (GET_CODE (operands[0]) == MEM)
6714 return \"subq%.l %#1,%0\;jbcc %l1\";
6716 #ifdef SGS_CMP_ORDER
6718 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6720 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6722 #else /* not SGS_CMP_ORDER */
6723 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6724 #endif /* not SGS_CMP_ORDER */
6725 #else /* not MOTOROLA */
6726 if (DATA_REG_P (operands[0]))
6727 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6728 if (GET_CODE (operands[0]) == MEM)
6729 return \"subql %#1,%0\;jcc %l1\";
6730 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6731 #endif /* not MOTOROLA */
6735 ;; For PIC calls, in order to be able to support
6736 ;; dynamic linker LAZY BINDING, all the procedure calls need to go
6737 ;; through the PLT (Procedure Linkage Table) section in PIC mode.
6739 ;; PIC calls are handled by loading the address of the function into a
6740 ;; register (via movsi), then emitting a register indirect call using
6741 ;; the "jsr" function call syntax.
6743 ;; When outputting MIT syntax (e.g. on Suns), we add a bogus extra
6744 ;; operand to the jbsr statement to indicate that this call should
6745 ;; go through the PLT (why? because this is the way that Sun does it).
6747 ;; We have different patterns for PIC calls and non-PIC calls. The
6748 ;; different patterns are only used to choose the right syntax.
6750 ;; The svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it
6751 ;; will create the correct relocation entry (R_68K_PLT32) for `FUNC',
6752 ;; that tells the linker editor to create an entry for `FUNC' in PLT
6753 ;; section at link time. However, all global objects reference are still
6754 ;; done by using `OBJ@GOT'. So, the goal here is to output the function
6755 ;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'.
6756 ;; We need to have a way to differentiate these two different operands.
6758 ;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate
6759 ;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs
6760 ;; to be changed to recognize function calls symbol_ref operand as a valid
6761 ;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will
6762 ;; avoid the compiler to load this symbol_ref operand into a register.
6763 ;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly
6764 ;; since the value is a PC relative offset, not a real address.
6766 ;; All global objects are treated in the similar way as in SUN3. The only
6767 ;; difference is: on m68k svr4, the reference of such global object needs
6768 ;; to end with a suffix "@GOT" so the assembler and linker know to create
6769 ;; an entry for it in GOT (Global Offset Table) section. This is done in
6772 ;; Call subroutine with no return value.
6773 (define_expand "call"
6774 [(call (match_operand:QI 0 "memory_operand" "")
6775 (match_operand:SI 1 "general_operand" ""))]
6776 ;; Operand 1 not really used on the m68000.
6781 if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6782 SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
6785 ;; This is a normal call sequence.
6787 [(call (match_operand:QI 0 "memory_operand" "o")
6788 (match_operand:SI 1 "general_operand" "g"))]
6789 ;; Operand 1 not really used on the m68000.
6793 #if defined (MOTOROLA) && !defined (USE_GAS)
6795 if (GET_CODE (operands[0]) == MEM
6796 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6805 ;; This is a PIC call sequence.
6807 [(call (match_operand:QI 0 "memory_operand" "o")
6808 (match_operand:SI 1 "general_operand" "g"))]
6809 ;; Operand 1 not really used on the m68000.
6813 if (GET_CODE (operands[0]) == MEM
6814 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6817 return \"bsr.l %0\";
6820 return \"bsr.l %0@PLTPC\";
6822 return \"bsr %0@PLTPC\";
6826 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC,
6827 GAS just plain ignores it. */
6828 return \"jbsr %0,a1\";
6833 ;; Call subroutine, returning value in operand 0
6834 ;; (which must be a hard register).
6835 ;; See comments before "call" regarding PIC calls.
6836 (define_expand "call_value"
6837 [(set (match_operand 0 "" "")
6838 (call (match_operand:QI 1 "memory_operand" "")
6839 (match_operand:SI 2 "general_operand" "")))]
6840 ;; Operand 2 not really used on the m68000.
6844 if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6845 SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
6848 ;; This is a normal call_value
6850 [(set (match_operand 0 "" "=rf")
6851 (call (match_operand:QI 1 "memory_operand" "o")
6852 (match_operand:SI 2 "general_operand" "g")))]
6853 ;; Operand 2 not really used on the m68000.
6856 #if defined (MOTOROLA) && !defined (USE_GAS)
6858 if (GET_CODE (operands[1]) == MEM
6859 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6868 ;; This is a PIC call_value
6870 [(set (match_operand 0 "" "=rf")
6871 (call (match_operand:QI 1 "memory_operand" "o")
6872 (match_operand:SI 2 "general_operand" "g")))]
6873 ;; Operand 2 not really used on the m68000.
6876 if (GET_CODE (operands[1]) == MEM
6877 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6881 return \"bsr.l %1\";
6884 return \"bsr.l %1@PLTPC\";
6886 return \"bsr %1@PLTPC\";
6890 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC
6891 GAS just plain ignores it. */
6892 return \"jbsr %1,a1\";
6898 ;; Call subroutine returning any type.
6900 (define_expand "untyped_call"
6901 [(parallel [(call (match_operand 0 "" "")
6903 (match_operand 1 "" "")
6904 (match_operand 2 "" "")])]
6905 "NEEDS_UNTYPED_CALL"
6910 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
6912 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6914 rtx set = XVECEXP (operands[2], 0, i);
6915 emit_move_insn (SET_DEST (set), SET_SRC (set));
6918 /* The optimizer does not know that the call sets the function value
6919 registers we stored in the result block. We avoid problems by
6920 claiming that all hard registers are used and clobbered at this
6922 emit_insn (gen_blockage ());
6927 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6928 ;; all of memory. This blocks insns from being moved across this point.
6930 (define_insn "blockage"
6931 [(unspec_volatile [(const_int 0)] 0)]
6940 (define_insn "probe"
6945 operands[0] = gen_rtx_PLUS (SImode, stack_pointer_rtx,
6946 GEN_INT (NEED_PROBE));
6947 return \"tstl %a0\";
6950 ;; Used for frameless functions which save no regs and allocate no locals.
6951 (define_insn "return"
6956 if (current_function_pops_args == 0)
6958 operands[0] = GEN_INT (current_function_pops_args);
6962 (define_insn "indirect_jump"
6963 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
6967 ;; This should not be used unless the add/sub insns can't be.
6970 [(set (match_operand:SI 0 "general_operand" "=a")
6971 (match_operand:QI 1 "address_operand" "p"))]
6976 /* Recognize an insn that refers to a table of offsets. Such an insn will
6977 need to refer to a label on the insn. So output one. Use the
6978 label-number of the table of offsets to generate this label. This code,
6979 and similar code above, assumes that there will be at most one reference
6981 if (GET_CODE (operands[1]) == PLUS
6982 && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
6983 && GET_CODE (XEXP (operands[1], 0)) != PLUS)
6985 rtx labelref = XEXP (operands[1], 1);
6986 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
6988 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
6989 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6991 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
6992 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6993 #endif /* not SGS */
6994 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
6995 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
6996 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6997 #ifdef SGS_SWITCH_TABLES
6998 /* Set flag saying we need to define the symbol
6999 LD%n (with value L%n-LI%n) at the end of the switch table. */
7000 switch_table_difference_label_flag = 1;
7001 #endif /* SGS_SWITCH_TABLES */
7002 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
7004 #endif /* SGS_NO_LI */
7006 return \"lea %a1,%0\";
7009 ;; This is the first machine-dependent peephole optimization.
7010 ;; It is useful when a floating value is returned from a function call
7011 ;; and then is moved into an FP register.
7012 ;; But it is mainly intended to test the support for these optimizations.
7015 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
7016 (set (match_operand:DF 0 "register_operand" "=f")
7017 (match_operand:DF 1 "register_operand" "ad"))]
7018 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
7022 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7023 output_asm_insn (\"move%.l %1,%@\", xoperands);
7024 output_asm_insn (\"move%.l %1,%-\", operands);
7025 return \"fmove%.d %+,%0\";
7029 ;; Optimize a stack-adjust followed by a push of an argument.
7030 ;; This is said to happen frequently with -msoft-float
7031 ;; when there are consecutive library calls.
7034 [(set (reg:SI 15) (plus:SI (reg:SI 15)
7035 (match_operand:SI 0 "const_int_operand" "n")))
7036 (set (match_operand:SF 1 "push_operand" "=m")
7037 (match_operand:SF 2 "general_operand" "rmfF"))]
7038 "INTVAL (operands[0]) >= 4
7039 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
7042 if (INTVAL (operands[0]) > 4)
7045 xoperands[0] = stack_pointer_rtx;
7046 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
7048 if (INTVAL (xoperands[1]) <= 8)
7051 output_asm_insn (\"addq%.w %1,%0\", xoperands);
7053 output_asm_insn (\"addq%.l %1,%0\", xoperands);
7055 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
7057 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
7058 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
7062 if (INTVAL (xoperands[1]) <= 0x7FFF)
7065 output_asm_insn (\"add%.w %1,%0\", xoperands);
7068 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
7070 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
7074 output_asm_insn (\"add%.l %1,%0\", xoperands);
7076 if (FP_REG_P (operands[2]))
7077 return \"fmove%.s %2,%@\";
7078 return \"move%.l %2,%@\";
7081 ;; Speed up stack adjust followed by a fullword fixedpoint push.
7084 [(set (reg:SI 15) (plus:SI (reg:SI 15)
7085 (match_operand:SI 0 "const_int_operand" "n")))
7086 (set (match_operand:SI 1 "push_operand" "=m")
7087 (match_operand:SI 2 "general_operand" "g"))]
7088 "INTVAL (operands[0]) >= 4
7089 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
7092 if (INTVAL (operands[0]) > 4)
7095 xoperands[0] = stack_pointer_rtx;
7096 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
7098 if (INTVAL (xoperands[1]) <= 8)
7101 output_asm_insn (\"addq%.w %1,%0\", xoperands);
7103 output_asm_insn (\"addq%.l %1,%0\", xoperands);
7105 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
7107 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
7108 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
7112 if (INTVAL (xoperands[1]) <= 0x7FFF)
7115 output_asm_insn (\"add%.w %1,%0\", xoperands);
7119 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
7121 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
7126 output_asm_insn (\"add%.l %1,%0\", xoperands);
7128 if (operands[2] == const0_rtx)
7129 return \"clr%.l %@\";
7130 return \"move%.l %2,%@\";
7133 ;; Speed up pushing a single byte but leaving four bytes of space.
7136 [(set (mem:QI (pre_dec:SI (reg:SI 15)))
7137 (match_operand:QI 1 "general_operand" "dami"))
7138 (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))]
7139 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
7144 if (GET_CODE (operands[1]) == REG)
7145 return \"move%.l %1,%-\";
7147 xoperands[1] = operands[1];
7149 = gen_rtx_MEM (QImode,
7150 gen_rtx_PLUS (VOIDmode, stack_pointer_rtx,
7152 xoperands[3] = stack_pointer_rtx;
7154 output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
7156 output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands);
7161 [(set (match_operand:SI 0 "register_operand" "=d")
7163 (set (strict_low_part (subreg:HI (match_dup 0) 0))
7164 (match_operand:HI 1 "general_operand" "rmn"))]
7165 "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
7168 if (GET_CODE (operands[1]) == CONST_INT)
7170 if (operands[1] == const0_rtx
7171 && (DATA_REG_P (operands[0])
7172 || GET_CODE (operands[0]) == MEM)
7173 /* clr insns on 68000 read before writing.
7174 This isn't so on the 68010, but we have no TARGET_68010. */
7175 && ((TARGET_68020 || TARGET_5200)
7176 || !(GET_CODE (operands[0]) == MEM
7177 && MEM_VOLATILE_P (operands[0]))))
7178 return \"clr%.w %0\";
7180 return \"move%.w %1,%0\";
7188 ;; jCC label ; abnormal loop termination
7189 ;; dbra dN, loop ; normal loop termination
7197 ;; Which moves the jCC condition outside the inner loop for free.
7200 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7201 [(cc0) (const_int 0)])
7202 (label_ref (match_operand 2 "" ""))
7207 (ge (plus:HI (match_operand:HI 0 "register_operand" "+d")
7210 (label_ref (match_operand 1 "" ""))
7213 (plus:HI (match_dup 0)
7215 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7219 output_dbcc_and_branch (operands);
7224 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7225 [(cc0) (const_int 0)])
7226 (label_ref (match_operand 2 "" ""))
7231 (ge (plus:SI (match_operand:SI 0 "register_operand" "+d")
7234 (label_ref (match_operand 1 "" ""))
7237 (plus:SI (match_dup 0)
7239 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7243 output_dbcc_and_branch (operands);
7248 ;; FPA multiply and add.
7250 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7251 (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%x,dmF,y")
7252 (match_operand:DF 2 "general_operand" "xH,y,y"))
7253 (match_operand:DF 3 "general_operand" "xH,y,dmF")))]
7256 fpma%.d %1,%w2,%w3,%0
7257 fpma%.d %x1,%x2,%x3,%0
7258 fpma%.d %x1,%x2,%x3,%0")
7261 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7262 (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%x,ydmF,y")
7263 (match_operand:SF 2 "general_operand" "xH,y,ydmF"))
7264 (match_operand:SF 3 "general_operand" "xH,ydmF,ydmF")))]
7267 fpma%.s %1,%w2,%w3,%0
7269 fpma%.s %1,%2,%3,%0")
7271 ;; FPA Multiply and subtract
7273 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7274 (minus:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
7275 (mult:DF (match_operand:DF 2 "general_operand" "%xH,y,y")
7276 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
7279 fpms%.d %3,%w2,%w1,%0
7280 fpms%.d %x3,%2,%x1,%0
7281 fpms%.d %x3,%2,%x1,%0")
7284 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7285 (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
7286 (mult:SF (match_operand:SF 2 "general_operand" "%xH,rmF,y")
7287 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
7290 fpms%.s %3,%w2,%w1,%0
7292 fpms%.s %3,%2,%1,%0")
7295 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7296 (minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
7297 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7298 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7301 fpmr%.d %2,%w1,%w3,%0
7302 fpmr%.d %x2,%1,%x3,%0
7303 fpmr%.d %x2,%1,%x3,%0")
7306 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7307 (minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
7308 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7309 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7312 fpmr%.s %2,%w1,%w3,%0
7313 fpmr%.s %x2,%1,%x3,%0
7314 fpmr%.s %x2,%1,%x3,%0")
7316 ;; FPA Add and multiply
7318 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7319 (mult:DF (plus:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
7320 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7321 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7324 fpam%.d %2,%w1,%w3,%0
7325 fpam%.d %x2,%1,%x3,%0
7326 fpam%.d %x2,%1,%x3,%0")
7329 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7330 (mult:SF (plus:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
7331 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7332 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7335 fpam%.s %2,%w1,%w3,%0
7336 fpam%.s %x2,%1,%x3,%0
7337 fpam%.s %x2,%1,%x3,%0")
7339 ;;FPA Subtract and multiply
7341 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7342 (mult:DF (minus:DF (match_operand:DF 1 "general_operand" "xH,y,y")
7343 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7344 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7347 fpsm%.d %2,%w1,%w3,%0
7348 fpsm%.d %x2,%1,%x3,%0
7349 fpsm%.d %x2,%1,%x3,%0")
7352 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7353 (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
7354 (minus:DF (match_operand:DF 2 "general_operand" "xH,y,y")
7355 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
7358 fpsm%.d %3,%w2,%w1,%0
7359 fpsm%.d %x3,%2,%x1,%0
7360 fpsm%.d %x3,%2,%x1,%0")
7363 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7364 (mult:SF (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,y")
7365 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7366 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7369 fpsm%.s %2,%w1,%w3,%0
7370 fpsm%.s %x2,%1,%x3,%0
7371 fpsm%.s %x2,%1,%x3,%0")
7374 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7375 (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
7376 (minus:SF (match_operand:SF 2 "general_operand" "xH,rmF,y")
7377 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
7380 fpsm%.s %3,%w2,%w1,%0
7381 fpsm%.s %x3,%2,%x1,%0
7382 fpsm%.s %x3,%2,%x1,%0")
7384 (define_expand "tstxf"
7386 (match_operand:XF 0 "nonimmediate_operand" ""))]
7388 "m68k_last_compare_had_fp_operands = 1;")
7392 (match_operand:XF 0 "nonimmediate_operand" "fm"))]
7396 cc_status.flags = CC_IN_68881;
7397 return \"ftst%.x %0\";
7400 (define_expand "cmpxf"
7402 (compare (match_operand:XF 0 "nonimmediate_operand" "")
7403 (match_operand:XF 1 "nonimmediate_operand" "")))]
7405 "m68k_last_compare_had_fp_operands = 1;")
7409 (compare (match_operand:XF 0 "nonimmediate_operand" "f,m")
7410 (match_operand:XF 1 "nonimmediate_operand" "fm,f")))]
7414 cc_status.flags = CC_IN_68881;
7415 #ifdef SGS_CMP_ORDER
7416 if (REG_P (operands[0]))
7418 if (REG_P (operands[1]))
7419 return \"fcmp%.x %0,%1\";
7421 return \"fcmp%.x %0,%f1\";
7423 cc_status.flags |= CC_REVERSED;
7424 return \"fcmp%.x %1,%f0\";
7426 if (REG_P (operands[0]))
7428 if (REG_P (operands[1]))
7429 return \"fcmp%.x %1,%0\";
7431 return \"fcmp%.x %f1,%0\";
7433 cc_status.flags |= CC_REVERSED;
7434 return \"fcmp%.x %f0,%1\";
7438 (define_insn "extendsfxf2"
7439 [(set (match_operand:XF 0 "general_operand" "=fm,f")
7440 (float_extend:XF (match_operand:SF 1 "general_operand" "f,rmF")))]
7444 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7446 if (REGNO (operands[0]) == REGNO (operands[1]))
7448 /* Extending float to double in an fp-reg is a no-op.
7449 NOTICE_UPDATE_CC has already assumed that the
7450 cc will be set. So cancel what it did. */
7451 cc_status = cc_prev_status;
7454 return \"f%$move%.x %1,%0\";
7456 if (FP_REG_P (operands[0]))
7458 if (FP_REG_P (operands[1]))
7459 return \"f%$move%.x %1,%0\";
7460 else if (ADDRESS_REG_P (operands[1]))
7461 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
7462 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
7463 return output_move_const_single (operands);
7464 return \"f%$move%.s %f1,%0\";
7466 return \"fmove%.x %f1,%0\";
7470 (define_insn "extenddfxf2"
7471 [(set (match_operand:XF 0 "general_operand" "=fm,f")
7473 (match_operand:DF 1 "general_operand" "f,rmE")))]
7477 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7479 if (REGNO (operands[0]) == REGNO (operands[1]))
7481 /* Extending float to double in an fp-reg is a no-op.
7482 NOTICE_UPDATE_CC has already assumed that the
7483 cc will be set. So cancel what it did. */
7484 cc_status = cc_prev_status;
7487 return \"fmove%.x %1,%0\";
7489 if (FP_REG_P (operands[0]))
7491 if (REG_P (operands[1]))
7494 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
7495 output_asm_insn (\"move%.l %1,%-\", xoperands);
7496 output_asm_insn (\"move%.l %1,%-\", operands);
7497 return \"f%&move%.d %+,%0\";
7499 if (GET_CODE (operands[1]) == CONST_DOUBLE)
7500 return output_move_const_double (operands);
7501 return \"f%&move%.d %f1,%0\";
7503 return \"fmove%.x %f1,%0\";
7506 (define_insn "truncxfdf2"
7507 [(set (match_operand:DF 0 "general_operand" "=m,!r")
7509 (match_operand:XF 1 "general_operand" "f,f")))]
7513 if (REG_P (operands[0]))
7515 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
7516 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
7517 return \"move%.l %+,%0\";
7519 return \"fmove%.d %f1,%0\";
7522 (define_insn "truncxfsf2"
7523 [(set (match_operand:SF 0 "general_operand" "=dm")
7525 (match_operand:XF 1 "general_operand" "f")))]
7529 (define_insn "floatsixf2"
7530 [(set (match_operand:XF 0 "general_operand" "=f")
7531 (float:XF (match_operand:SI 1 "general_operand" "dmi")))]
7535 (define_insn "floathixf2"
7536 [(set (match_operand:XF 0 "general_operand" "=f")
7537 (float:XF (match_operand:HI 1 "general_operand" "dmn")))]
7541 (define_insn "floatqixf2"
7542 [(set (match_operand:XF 0 "general_operand" "=f")
7543 (float:XF (match_operand:QI 1 "general_operand" "dmn")))]
7547 (define_insn "ftruncxf2"
7548 [(set (match_operand:XF 0 "general_operand" "=f")
7549 (fix:XF (match_operand:XF 1 "general_operand" "fFm")))]
7553 if (FP_REG_P (operands[1]))
7554 return \"fintrz%.x %f1,%0\";
7555 return \"fintrz%.x %f1,%0\";
7558 (define_insn "fixxfqi2"
7559 [(set (match_operand:QI 0 "general_operand" "=dm")
7560 (fix:QI (match_operand:XF 1 "general_operand" "f")))]
7564 (define_insn "fixxfhi2"
7565 [(set (match_operand:HI 0 "general_operand" "=dm")
7566 (fix:HI (match_operand:XF 1 "general_operand" "f")))]
7570 (define_insn "fixxfsi2"
7571 [(set (match_operand:SI 0 "general_operand" "=dm")
7572 (fix:SI (match_operand:XF 1 "general_operand" "f")))]
7577 [(set (match_operand:XF 0 "general_operand" "=f")
7578 (plus:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7579 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7584 [(set (match_operand:XF 0 "general_operand" "=f")
7585 (plus:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7586 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7591 [(set (match_operand:XF 0 "general_operand" "=f")
7592 (plus:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7593 (match_operand:XF 1 "general_operand" "0")))]
7597 (define_insn "addxf3"
7598 [(set (match_operand:XF 0 "general_operand" "=f")
7599 (plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7600 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7604 if (REG_P (operands[2]))
7605 return \"fadd%.x %2,%0\";
7606 return \"fadd%.x %f2,%0\";
7610 [(set (match_operand:XF 0 "general_operand" "=f")
7611 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7612 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7617 [(set (match_operand:XF 0 "general_operand" "=f")
7618 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7619 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7624 [(set (match_operand:XF 0 "general_operand" "=f")
7625 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7626 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7630 (define_insn "subxf3"
7631 [(set (match_operand:XF 0 "general_operand" "=f")
7632 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7633 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7637 if (REG_P (operands[2]))
7638 return \"fsub%.x %2,%0\";
7639 return \"fsub%.x %f2,%0\";
7643 [(set (match_operand:XF 0 "general_operand" "=f")
7644 (mult:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7645 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7650 [(set (match_operand:XF 0 "general_operand" "=f")
7651 (mult:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7652 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7657 [(set (match_operand:XF 0 "general_operand" "=f")
7658 (mult:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7659 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7663 (define_insn "mulxf3"
7664 [(set (match_operand:XF 0 "general_operand" "=f")
7665 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7666 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7670 if (REG_P (operands[2]))
7671 return \"fmul%.x %2,%0\";
7672 return \"fmul%.x %f2,%0\";
7676 [(set (match_operand:XF 0 "general_operand" "=f")
7677 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7678 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7683 [(set (match_operand:XF 0 "general_operand" "=f")
7684 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7685 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7690 [(set (match_operand:XF 0 "general_operand" "=f")
7691 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7692 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7696 (define_insn "divxf3"
7697 [(set (match_operand:XF 0 "general_operand" "=f")
7698 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7699 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7703 if (REG_P (operands[2]))
7704 return \"fdiv%.x %2,%0\";
7705 return \"fdiv%.x %f2,%0\";
7708 (define_expand "negxf2"
7709 [(set (match_operand:XF 0 "general_operand" "")
7710 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7714 /* ??? There isn't an FPA define_insn so we could handle it here too.
7715 For now we don't (paranoia). */
7723 target = operand_subword (operands[0], 0, 1, XFmode);
7724 result = expand_binop (SImode, xor_optab,
7725 operand_subword_force (operands[1], 0, XFmode),
7726 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
7730 if (result != target)
7731 emit_move_insn (result, target);
7733 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7734 operand_subword_force (operands[1], 1, XFmode));
7735 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7736 operand_subword_force (operands[1], 2, XFmode));
7738 insns = get_insns ();
7741 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7746 (define_insn "negxf2_68881"
7747 [(set (match_operand:XF 0 "general_operand" "=f")
7748 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7752 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7753 return \"fneg%.x %1,%0\";
7754 return \"fneg%.x %f1,%0\";
7757 (define_expand "absxf2"
7758 [(set (match_operand:XF 0 "general_operand" "")
7759 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7763 /* ??? There isn't an FPA define_insn so we could handle it here too.
7764 For now we don't (paranoia). */
7772 target = operand_subword (operands[0], 0, 1, XFmode);
7773 result = expand_binop (SImode, and_optab,
7774 operand_subword_force (operands[1], 0, XFmode),
7775 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
7779 if (result != target)
7780 emit_move_insn (result, target);
7782 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7783 operand_subword_force (operands[1], 1, XFmode));
7784 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7785 operand_subword_force (operands[1], 2, XFmode));
7787 insns = get_insns ();
7790 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7795 (define_insn "absxf2_68881"
7796 [(set (match_operand:XF 0 "general_operand" "=f")
7797 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7801 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7802 return \"fabs%.x %1,%0\";
7803 return \"fabs%.x %f1,%0\";
7806 (define_insn "sqrtxf2"
7807 [(set (match_operand:XF 0 "general_operand" "=f")
7808 (sqrt:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7812 (define_insn "sinsf2"
7813 [(set (match_operand:SF 0 "general_operand" "=f")
7814 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 1))]
7815 "TARGET_68881 && flag_fast_math"
7818 if (FP_REG_P (operands[1]))
7819 return \"fsin%.x %1,%0\";
7821 return \"fsin%.s %1,%0\";
7824 (define_insn "sindf2"
7825 [(set (match_operand:DF 0 "general_operand" "=f")
7826 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 1))]
7827 "TARGET_68881 && flag_fast_math"
7830 if (FP_REG_P (operands[1]))
7831 return \"fsin%.x %1,%0\";
7833 return \"fsin%.d %1,%0\";
7836 (define_insn "sinxf2"
7837 [(set (match_operand:XF 0 "general_operand" "=f")
7838 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 1))]
7839 "TARGET_68881 && flag_fast_math"
7842 (define_insn "cossf2"
7843 [(set (match_operand:SF 0 "general_operand" "=f")
7844 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 2))]
7845 "TARGET_68881 && flag_fast_math"
7848 if (FP_REG_P (operands[1]))
7849 return \"fcos%.x %1,%0\";
7851 return \"fcos%.s %1,%0\";
7854 (define_insn "cosdf2"
7855 [(set (match_operand:DF 0 "general_operand" "=f")
7856 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 2))]
7857 "TARGET_68881 && flag_fast_math"
7860 if (FP_REG_P (operands[1]))
7861 return \"fcos%.x %1,%0\";
7863 return \"fcos%.d %1,%0\";
7866 (define_insn "cosxf2"
7867 [(set (match_operand:XF 0 "general_operand" "=f")
7868 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 2))]
7869 "TARGET_68881 && flag_fast_math"