1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2001, 2002
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;;- Information about MCF5200 port.
24 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
25 ;;- 68k ISA. Differences include reduced support for byte and word
26 ;;- operands and the removal of BCD, bitfield, rotate, and integer
27 ;;- divide instructions. The TARGET_5200 flag turns the use of the
28 ;;- removed opcodes and addressing modes off.
32 ;;- instruction definitions
34 ;;- @@The original PO technology requires these to be ordered by speed,
35 ;;- @@ so that assigner will pick the fastest.
37 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
39 ;;- When naming insn's (operand 0 of define_insn) be careful about using
40 ;;- names from other targets machine descriptions.
42 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
43 ;;- updates for most instructions.
45 ;;- Operand classes for the register allocator:
46 ;;- 'a' one of the address registers can be used.
47 ;;- 'd' one of the data registers can be used.
48 ;;- 'f' one of the m68881 registers can be used
49 ;;- 'r' either a data or an address register can be used.
50 ;;- 'x' if one of the Sun FPA registers
51 ;;- 'y' if one of the Low Sun FPA registers (fpa0-fpa15).
53 ;;- Immediate Floating point operator constraints
54 ;;- 'G' a floating point constant that is *NOT* one of the standard
55 ;; 68881 constant values (to force calling output_move_const_double
56 ;; to get it from rom if it is a 68881 constant).
57 ;;- 'H' one of the standard FPA constant values
59 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
62 ;;- Immediate integer operand constraints:
64 ;;- 'J' -32768 .. 32767
65 ;;- 'K' all integers EXCEPT -128 .. 127
67 ;;- 'M' all integers EXCEPT -256 .. 255
73 ;;- "%." size separator ("." or "") move%.l d0,d1
74 ;;- "%#" immediate separator ("#" or "") move%.l %#0,d0
75 ;;- "%-" push operand "sp@-" move%.l d0,%-
76 ;;- "%+" pop operand "sp@+" move%.l d0,%+
77 ;;- "%@" top of stack "sp@" move%.l d0,%@
78 ;;- "%!" fpcr register
79 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
80 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
83 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
84 ;; operand 1 is the argument for `sin'.
85 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
86 ;; operand 1 is the argument for `cos'.
88 ;;- Information about 68040 port.
90 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
91 ;;- be emulated in software by the OS. It is faster to avoid these
92 ;;- instructions and issue a library call rather than trapping into
93 ;;- the kernel. The affected instructions are fintrz and fscale. The
94 ;;- TARGET_68040 flag turns the use of the opcodes off.
96 ;;- The '040 also implements a set of new floating-point instructions
97 ;;- which specify the rounding precision in the opcode. This finally
98 ;;- permit the 68k series to be truly IEEE compliant, and solves all
99 ;;- issues of excess precision accumulating in the extended registers.
100 ;;- By default, GCC does not use these instructions, since such code will
101 ;;- not run on an '030. To use these instructions, use the -m68040-only
102 ;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY,
103 ;;- you can make these instructions the default.
105 ;;- These new instructions aren't directly in the md. They are brought
106 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
109 ;;- Information about 68060 port.
111 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
112 ;;- be emulated in software by the OS. It is faster to avoid these
113 ;;- instructions and issue a library call rather than trapping into
114 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
115 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
116 ;;- fscale. The TARGET_68060 flag turns the use of the opcodes off.
118 ;;- FPA port explanation:
120 ;;- Usage of the Sun FPA and the 68881 together
122 ;;- The current port of gcc to the sun fpa disallows use of the m68881
123 ;;- instructions completely if code is targeted for the fpa. This is
124 ;;- for the following reasons:
126 ;;- 1) Expressing the preference hierarchy (ie. use the fpa if you
127 ;;- can, the 68881 otherwise, and data registers only if you are
128 ;;- forced to it) is a bitch with the current constraint scheme,
129 ;;- especially since it would have to work for any combination of
132 ;;- 2) There are no instructions to move between the two types of
133 ;;- registers; the stack must be used as an intermediary.
135 ;;- It could indeed be done; I think the best way would be to have
136 ;;- separate patterns for TARGET_FPA (which implies a 68881),
137 ;;- TARGET_68881, and no floating point co-processor. Use
138 ;;- define_expands for all of the named instruction patterns, and
139 ;;- include code in the FPA instruction to deal with the 68881 with
140 ;;- preferences specifically set to favor the fpa. Some of this has
141 ;;- already been done:
143 ;;- 1) Separation of most of the patterns out into a TARGET_FPA
144 ;;- case and a TARGET_68881 case (the exceptions are the patterns
145 ;;- which would need one define_expand and three define_insn's under
146 ;;- it (with a lot of duplicate code between them) to replace the
147 ;;- current single define_insn. These are mov{[ds]f,[ds]i} and the
148 ;;- first two patterns in the md.
150 ;;- Some would still have to be done:
152 ;;- 1) Add code to the fpa patterns which correspond to 68881
153 ;;- patterns to deal with the 68881 case (including preferences!).
154 ;;- What you might actually do here is combine the fpa and 68881 code
155 ;;- back together into one pattern for those instructions where it's
156 ;;- absolutely necessary and save yourself some duplicate code. I'm
157 ;;- not completely sure as to whether you could get away with doing
158 ;;- this only for the mov* insns, or if you'd have to do it for all
160 ;;- 2) Add code to the mov{[ds]f,[ds]i} instructions to handle
161 ;;- moving between fpa regs and 68881 regs.
163 ;;- Since the fpa is more powerful than the 68881 and also has more
164 ;;- registers, and since I think the resultant md would be medium ugly
165 ;;- (lot's of duplicate code, ugly constraint strings), I elected not
166 ;;- to do this change.
168 ;;- Another reason why someone *might* want to do the change is to
169 ;;- control which register classes are accessed in a slightly cleaner
170 ;;- way than I have. See the blurb on CONDITIONAL_REGISTER_USAGE in
171 ;;- the internals manual.
173 ;;- Yet another reason why someone might want to do this change is to
174 ;;- allow use of some of the 68881 insns which have no equivalent on
175 ;;- the fpa. The sqrt instruction comes fairly quickly to mind.
177 ;;- If this is ever done, don't forget to change sun3.h so that
178 ;;- it *will* define __HAVE_68881__ when the FPA is in use.
180 ;;- Condition code hack
182 ;;- When a floating point compare is done in the fpa, the resulting
183 ;;- condition codes are left in the fpastatus register. The values in
184 ;;- this register must be moved into the 68000 cc register before any
185 ;;- jump is executed. Once this has been done, regular jump
186 ;;- instructions are fine (ie. floating point jumps are not necessary.
187 ;;- They are only done if the cc is in the 68881).
189 ;;- The instructions that move the fpastatus register to the 68000
190 ;;- register clobber a data register (the move cannot be done direct).
191 ;;- These instructions might be bundled either with the compare
192 ;;- instruction, or the branch instruction. If we were using both the
193 ;;- fpa and the 68881 together, we would wish to only mark the
194 ;;- register clobbered if we were doing the compare in the fpa, but I
195 ;;- think that that decision (whether to clobber the register or not)
196 ;;- must be done before register allocation (makes sense) and hence we
197 ;;- can't know if the floating point compare will be done in the fpa
198 ;;- or the fp. So whenever we are asked for code that uses the fpa,
199 ;;- we will mark a data register as clobbered. This is reasonable, as
200 ;;- almost all floating point compare operations done with fpa code
201 ;;- enabled will be done in the fpa. It's even more reasonable since
202 ;;- we decided to make the 68881 and the fpa mutually exclusive.
204 ;;- We place to code to move the fpastatus register inside of a
205 ;;- define_expand so that we can do it conditionally based on whether
206 ;;- we are targeting an fpa or not.
208 ;;- This still leaves us with the question of where we wish to put the
209 ;;- code to move the fpastatus reg. If we put it in the compare
210 ;;- instruction, we can restrict the clobbering of the register to
211 ;;- floating point compares, but we can't take advantage of floating
212 ;;- point subtracts & etc. that alter the fpastatus register. If we
213 ;;- put it in the branch instruction, all branches compiled with fpa
214 ;;- code enabled will clobber a data register, but we will be able to
215 ;;- take advantage of fpa subtracts. This balance favors putting the
216 ;;- code in with the compare instruction.
218 ;;- Note that if some enterprising hacker should decide to switch
219 ;;- this, he'll need to modify the code in NOTICE_UPDATE_CC.
221 ;;- Usage of the top 16 fpa registers
223 ;;- The only locations which we may transfer fpa registers 16-31 from
224 ;;- or to are the fpa registers 0-15. (68000 registers and memory
225 ;;- locations are impossible). This causes problems in gcc, which
226 ;;- assumes that mov?? instructions require no additional registers
227 ;;- (see section 11.7) and since floating point moves *must* be
228 ;;- supported into general registers (see section 12.3 under
229 ;;- HARD_REGNO_OK_FOR_MODE_P) from anywhere.
231 ;;- My solution was to reserve fpa0 for moves into or out of these top
232 ;;- 16 registers and to disparage the choice to reload into or out of
233 ;;- these registers as much as I could. That alternative is always
234 ;;- last in the list, so it will not be used unless all else fails. I
235 ;;- will note that according to my current information, sun's compiler
236 ;;- doesn't use these top 16 registers at all.
238 ;;- There is another possible way to do it. I *believe* that if you
239 ;;- make absolutely sure that the code will not be executed in the
240 ;;- reload pass, you can support the mov?? names with define_expands
241 ;;- which require new registers. This may be possible by the
242 ;;- appropriate juggling of constraints. I may come back to this later.
244 ;;- Usage of constant RAM
246 ;;- This has been handled correctly (I believe) but the way I've done
247 ;;- it could use a little explanation. The constant RAM can only be
248 ;;- accessed when the instruction is in "command register" mode.
249 ;;- "command register" mode means that no accessing of memory or the
250 ;;- 68000 registers is being done. This can be expressed easily in
251 ;;- constraints, so generally the mode of the instruction is
252 ;;- determined by a branch off of which_alternative. In outputting
253 ;;- instructions, a 'w' means to output an access to the constant ram
254 ;;- (if the arg is CONST_DOUBLE and is one of the available
255 ;;- constants), and 'x' means to output a register pair (if the arg is
256 ;;- a 68000 register) and a 'y' is the combination of the above two
257 ;;- processes. You use a 'y' in two operand DF instructions where you
258 ;;- *know* the other operand is an fpa register, you use an 'x' in DF
259 ;;- instructions where the arg might be a 68000 register and the
260 ;;- instruction is *not* in "command register" mode, and you use a 'w'
261 ;;- in two situations: 1) The instruction *is* in command register
262 ;;- mode (and hence won't be accessing 68000 registers), or 2) The
263 ;;- instruction is a two operand SF instruction where you know the
264 ;;- other operand is an fpa register.
266 ;;- Optimization issues
268 ;;- I actually think that I've included all of the fpa instructions
269 ;;- that should be included. Note that if someone is interested in
270 ;;- doing serious floating point work on the sun fpa, I would advise
271 ;;- the use of the "asm" instruction in gcc to allow you to use the
272 ;;- sin, cos, and exponential functions on the fpa board.
274 ;;- END FPA Explanation Section.
277 ;;- Some of these insn's are composites of several m68000 op codes.
278 ;;- The assembler (or final @@??) insures that the appropriate one is
282 [(set (match_operand:DF 0 "push_operand" "=m")
283 (match_operand:DF 1 "general_operand" "ro<>fyE"))]
287 if (FP_REG_P (operands[1]))
288 return \"fmove%.d %f1,%0\";
289 if (FPA_REG_P (operands[1]))
290 return \"fpmove%.d %1, %x0\";
291 return output_move_double (operands);
294 (define_insn "pushdi"
295 [(set (match_operand:DI 0 "push_operand" "=m")
296 (match_operand:DI 1 "general_operand" "ro<>Fyi"))]
300 return output_move_double (operands);
303 ;; We don't want to allow a constant operand for test insns because
304 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
305 ;; be folded while optimizing anyway.
307 (define_expand "tstdi"
308 [(parallel [(set (cc0)
309 (match_operand:DI 0 "nonimmediate_operand" ""))
310 (clobber (match_scratch:SI 1 ""))
311 (clobber (match_scratch:DI 2 ""))])]
313 "m68k_last_compare_had_fp_operands = 0;")
317 (match_operand:DI 0 "nonimmediate_operand" "am,d"))
318 (clobber (match_scratch:SI 1 "=X,d"))
319 (clobber (match_scratch:DI 2 "=d,X"))]
323 if (which_alternative == 0)
327 xoperands[0] = operands[2];
328 xoperands[1] = operands[0];
329 output_move_double (xoperands);
330 cc_status.flags |= CC_REVERSED;
331 return \"neg%.l %R2\;negx%.l %2\";
333 if (find_reg_note (insn, REG_DEAD, operands[0]))
335 cc_status.flags |= CC_REVERSED;
336 return \"neg%.l %R0\;negx%.l %0\";
340 ** 'sub' clears %1, and also clears the X cc bit
341 ** 'tst' sets the Z cc bit according to the low part of the DImode operand
342 ** 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part
344 return \"sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0\";
347 (define_expand "tstsi"
349 (match_operand:SI 0 "nonimmediate_operand" ""))]
351 "m68k_last_compare_had_fp_operands = 0;")
355 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
360 /* ISI's assembler fails to handle tstl a0. */
361 if (! ADDRESS_REG_P (operands[0]))
363 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
365 return \"tst%.l %0\";
366 /* If you think that the 68020 does not support tstl a0,
367 reread page B-167 of the 68020 manual more carefully. */
368 /* On an address reg, cmpw may replace cmpl. */
370 return \"cmp%.w %0,%#0\";
372 return \"cmp%.w %#0,%0\";
376 ;; This can't use an address register, because comparisons
377 ;; with address registers as second operand always test the whole word.
378 (define_expand "tsthi"
380 (match_operand:HI 0 "nonimmediate_operand" ""))]
382 "m68k_last_compare_had_fp_operands = 0;")
386 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
390 (define_expand "tstqi"
392 (match_operand:QI 0 "nonimmediate_operand" ""))]
394 "m68k_last_compare_had_fp_operands = 0;")
398 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
402 (define_expand "tstsf"
404 (match_operand:SF 0 "general_operand" ""))]
405 "TARGET_68881 || TARGET_FPA"
408 m68k_last_compare_had_fp_operands = 1;
411 emit_insn (gen_tstsf_fpa (operands[0]));
416 (define_insn "tstsf_fpa"
418 (match_operand:SF 0 "general_operand" "xmdF"))
419 (clobber (match_scratch:SI 1 "=d"))]
421 "fptst%.s %x0\;fpmove fpastatus,%1\;movw %1,cc")
425 (match_operand:SF 0 "general_operand" "fdm"))]
429 cc_status.flags = CC_IN_68881;
430 if (FP_REG_P (operands[0]))
431 return \"ftst%.x %0\";
432 return \"ftst%.s %0\";
435 (define_expand "tstdf"
437 (match_operand:DF 0 "general_operand" ""))]
438 "TARGET_68881 || TARGET_FPA"
441 m68k_last_compare_had_fp_operands = 1;
444 emit_insn (gen_tstsf_fpa (operands[0]));
449 (define_insn "tstdf_fpa"
451 (match_operand:DF 0 "general_operand" "xrmF"))
452 (clobber (match_scratch:SI 1 "=d"))]
454 "fptst%.d %x0\;fpmove fpastatus,%1\;movw %1,cc")
458 (match_operand:DF 0 "general_operand" "fm"))]
462 cc_status.flags = CC_IN_68881;
463 if (FP_REG_P (operands[0]))
464 return \"ftst%.x %0\";
465 return \"ftst%.d %0\";
468 ;; compare instructions.
470 (define_expand "cmpdi"
473 (compare (match_operand:DI 0 "nonimmediate_operand" "")
474 (match_operand:DI 1 "general_operand" "")))
475 (clobber (match_dup 2))])]
477 "m68k_last_compare_had_fp_operands = 0; operands[2] = gen_reg_rtx (DImode);")
481 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
482 (match_operand:DI 2 "general_operand" "d,0")))
483 (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
487 if (rtx_equal_p (operands[0], operands[1]))
488 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
491 cc_status.flags |= CC_REVERSED;
492 return \"sub%.l %R1,%R0\;subx%.l %1,%0\";
496 ;; This is the second "hook" for PIC code (in addition to movsi). See
497 ;; comment of movsi for a description of PIC handling.
498 (define_expand "cmpsi"
500 (compare (match_operand:SI 0 "nonimmediate_operand" "")
501 (match_operand:SI 1 "general_operand" "")))]
505 m68k_last_compare_had_fp_operands = 0;
506 if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
508 /* The source is an address which requires PIC relocation.
509 Call legitimize_pic_address with the source, mode, and a relocation
510 register (a new pseudo, or the final destination if reload_in_progress
511 is set). Then fall through normally */
512 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
513 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
517 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
520 (compare (match_operand:SI 0 "nonimmediate_operand" "rKT,rKs,mSr,mSa,>")
521 (match_operand:SI 1 "general_src_operand" "mSr,mSa,KTr,Ksr,>")))]
525 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
527 return \"cmpm%.l %0,%1\";
529 return \"cmpm%.l %1,%0\";
531 if (REG_P (operands[1])
532 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
533 { cc_status.flags |= CC_REVERSED;
535 return \"cmp%.l %d1,%d0\";
537 return \"cmp%.l %d0,%d1\";
540 if (ADDRESS_REG_P (operands[0])
541 && GET_CODE (operands[1]) == CONST_INT
542 && INTVAL (operands[1]) < 0x8000
543 && INTVAL (operands[1]) >= -0x8000)
546 return \"cmp%.w %0,%1\";
548 return \"cmp%.w %1,%0\";
552 return \"cmp%.l %d0,%d1\";
554 return \"cmp%.l %d1,%d0\";
560 (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
561 (match_operand:SI 1 "general_operand" "r,mrKs")))]
565 if (REG_P (operands[1])
566 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
567 { cc_status.flags |= CC_REVERSED;
569 return \"cmp%.l %d1,%d0\";
571 return \"cmp%.l %d0,%d1\";
575 return \"cmp%.l %d0,%d1\";
577 return \"cmp%.l %d1,%d0\";
581 (define_expand "cmphi"
583 (compare (match_operand:HI 0 "nonimmediate_src_operand" "")
584 (match_operand:HI 1 "general_src_operand" "")))]
586 "m68k_last_compare_had_fp_operands = 0;")
590 (compare (match_operand:HI 0 "nonimmediate_src_operand" "rnmS,d,n,mS,>")
591 (match_operand:HI 1 "general_src_operand" "d,rnmS,mS,n,>")))]
595 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
597 return \"cmpm%.w %0,%1\";
599 return \"cmpm%.w %1,%0\";
601 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
602 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
603 { cc_status.flags |= CC_REVERSED;
605 return \"cmp%.w %d1,%d0\";
607 return \"cmp%.w %d0,%d1\";
611 return \"cmp%.w %d0,%d1\";
613 return \"cmp%.w %d1,%d0\";
617 (define_expand "cmpqi"
619 (compare (match_operand:QI 0 "nonimmediate_src_operand" "")
620 (match_operand:QI 1 "general_src_operand" "")))]
622 "m68k_last_compare_had_fp_operands = 0;")
626 (compare (match_operand:QI 0 "nonimmediate_src_operand" "dn,dmS,>")
627 (match_operand:QI 1 "general_src_operand" "dmS,nd,>")))]
631 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
633 return \"cmpm%.b %0,%1\";
635 return \"cmpm%.b %1,%0\";
637 if (REG_P (operands[1])
638 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
639 { cc_status.flags |= CC_REVERSED;
641 return \"cmp%.b %d1,%d0\";
643 return \"cmp%.b %d0,%d1\";
647 return \"cmp%.b %d0,%d1\";
649 return \"cmp%.b %d1,%d0\";
653 (define_expand "cmpdf"
655 (compare (match_operand:DF 0 "general_operand" "")
656 (match_operand:DF 1 "general_operand" "")))]
657 "TARGET_68881 || TARGET_FPA"
660 m68k_last_compare_had_fp_operands = 1;
663 emit_insn (gen_cmpdf_fpa (operands[0], operands[1]));
668 (define_insn "cmpdf_fpa"
670 (compare (match_operand:DF 0 "general_operand" "x,y")
671 (match_operand:DF 1 "general_operand" "xH,rmF")))
672 (clobber (match_scratch:SI 2 "=d,d"))]
674 "fpcmp%.d %y1,%0\;fpmove fpastatus,%2\;movw %2,cc")
678 (compare (match_operand:DF 0 "general_operand" "f,mG")
679 (match_operand:DF 1 "general_operand" "fmG,f")))]
683 cc_status.flags = CC_IN_68881;
685 if (REG_P (operands[0]))
687 if (REG_P (operands[1]))
688 return \"fcmp%.x %0,%1\";
690 return \"fcmp%.d %0,%f1\";
692 cc_status.flags |= CC_REVERSED;
693 return \"fcmp%.d %1,%f0\";
695 if (REG_P (operands[0]))
697 if (REG_P (operands[1]))
698 return \"fcmp%.x %1,%0\";
700 return \"fcmp%.d %f1,%0\";
702 cc_status.flags |= CC_REVERSED;
703 return \"fcmp%.d %f0,%1\";
707 (define_expand "cmpsf"
709 (compare (match_operand:SF 0 "general_operand" "")
710 (match_operand:SF 1 "general_operand" "")))]
711 "TARGET_68881 || TARGET_FPA"
714 m68k_last_compare_had_fp_operands = 1;
717 emit_insn (gen_cmpsf_fpa (operands[0], operands[1]));
722 (define_insn "cmpsf_fpa"
724 (compare (match_operand:SF 0 "general_operand" "x,y")
725 (match_operand:SF 1 "general_operand" "xH,rmF")))
726 (clobber (match_scratch:SI 2 "=d,d"))]
728 "fpcmp%.s %w1,%x0\;fpmove fpastatus,%2\;movw %2,cc")
732 (compare (match_operand:SF 0 "general_operand" "f,mdG")
733 (match_operand:SF 1 "general_operand" "fmdG,f")))]
737 cc_status.flags = CC_IN_68881;
739 if (FP_REG_P (operands[0]))
741 if (FP_REG_P (operands[1]))
742 return \"fcmp%.x %0,%1\";
744 return \"fcmp%.s %0,%f1\";
746 cc_status.flags |= CC_REVERSED;
747 return \"fcmp%.s %1,%f0\";
749 if (FP_REG_P (operands[0]))
751 if (FP_REG_P (operands[1]))
752 return \"fcmp%.x %1,%0\";
754 return \"fcmp%.s %f1,%0\";
756 cc_status.flags |= CC_REVERSED;
757 return \"fcmp%.s %f0,%1\";
761 ;; Recognizers for btst instructions.
763 ;; Coldfire/5200 only allows "<Q>" type addresses when the bit position is
764 ;; specified as a constant, so we must disable all patterns that may extract
765 ;; from a MEM at a constant bit position if we can't use this as a constraint.
768 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_src_operand" "oS")
770 (minus:SI (const_int 7)
771 (match_operand:SI 1 "general_operand" "di"))))]
773 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
775 ;; This is the same as the above pattern except for the constraints. The 'i'
779 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
781 (minus:SI (const_int 7)
782 (match_operand:SI 1 "general_operand" "d"))))]
784 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
787 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
789 (minus:SI (const_int 31)
790 (match_operand:SI 1 "general_operand" "di"))))]
792 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
794 ;; The following two patterns are like the previous two
795 ;; except that they use the fact that bit-number operands
796 ;; are automatically masked to 3 or 5 bits.
799 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
801 (minus:SI (const_int 7)
803 (match_operand:SI 1 "register_operand" "d")
806 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
809 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
811 (minus:SI (const_int 31)
813 (match_operand:SI 1 "register_operand" "d")
816 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
818 ;; Nonoffsettable mem refs are ok in this one pattern
819 ;; since we don't try to adjust them.
821 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
823 (match_operand:SI 1 "const_int_operand" "n")))]
824 "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_5200"
827 operands[1] = GEN_INT (7 - INTVAL (operands[1]));
828 return output_btst (operands, operands[1], operands[0], insn, 7);
832 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
834 (match_operand:SI 1 "const_int_operand" "n")))]
838 if (GET_CODE (operands[0]) == MEM)
840 operands[0] = adjust_address (operands[0], QImode,
841 INTVAL (operands[1]) / 8);
842 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
843 return output_btst (operands, operands[1], operands[0], insn, 7);
845 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
846 return output_btst (operands, operands[1], operands[0], insn, 31);
849 ;; This is the same as the above pattern except for the constraints.
850 ;; The 'o' has been replaced with 'Q'.
853 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ")
855 (match_operand:SI 1 "const_int_operand" "n")))]
859 if (GET_CODE (operands[0]) == MEM)
861 operands[0] = adjust_address (operands[0], QImode,
862 INTVAL (operands[1]) / 8);
863 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
864 return output_btst (operands, operands[1], operands[0], insn, 7);
866 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
867 return output_btst (operands, operands[1], operands[0], insn, 31);
873 ;; A special case in which it is not desirable
874 ;; to reload the constant into a data register.
875 (define_insn "pushexthisi_const"
876 [(set (match_operand:SI 0 "push_operand" "=m")
877 (match_operand:SI 1 "const_int_operand" "J"))]
878 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
881 if (operands[1] == const0_rtx)
882 return \"clr%.l %0\";
887 ;(define_insn "swapsi"
888 ; [(set (match_operand:SI 0 "nonimmediate_operand" "+r")
889 ; (match_operand:SI 1 "general_operand" "+r"))
890 ; (set (match_dup 1) (match_dup 0))]
894 ;; Special case of fullword move when source is zero.
895 ;; The reason this is special is to avoid loading a zero
896 ;; into a data reg with moveq in order to store it elsewhere.
898 (define_insn "movsi_const0"
899 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
901 ;; clr insns on 68000 read before writing.
902 ;; This isn't so on the 68010, but we have no TARGET_68010.
903 "((TARGET_68020 || TARGET_5200)
904 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
907 if (ADDRESS_REG_P (operands[0]))
909 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
910 if (!TARGET_68040 && !TARGET_68060)
911 return \"sub%.l %0,%0\";
916 /* Many SGS assemblers croak on size specifiers for constants. */
919 return \"lea 0.w,%0\";
922 return \"lea 0:w,%0\";
926 /* moveq is faster on the 68000. */
927 if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_5200))
928 #if defined(MOTOROLA) && !defined(CRDS)
929 return \"moveq%.l %#0,%0\";
931 return \"moveq %#0,%0\";
933 return \"clr%.l %0\";
936 ;; General case of fullword move.
938 ;; This is the main "hook" for PIC code. When generating
939 ;; PIC, movsi is responsible for determining when the source address
940 ;; needs PIC relocation and appropriately calling legitimize_pic_address
941 ;; to perform the actual relocation.
943 ;; In both the PIC and non-PIC cases the patterns generated will
944 ;; matched by the next define_insn.
945 (define_expand "movsi"
946 [(set (match_operand:SI 0 "nonimmediate_operand" "")
947 (match_operand:SI 1 "general_operand" ""))]
951 if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
953 /* The source is an address which requires PIC relocation.
954 Call legitimize_pic_address with the source, mode, and a relocation
955 register (a new pseudo, or the final destination if reload_in_progress
956 is set). Then fall through normally */
957 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
958 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
960 else if (flag_pic && TARGET_PCREL && ! reload_in_progress)
962 /* Don't allow writes to memory except via a register;
963 the m68k doesn't consider PC-relative addresses to be writable. */
964 if (symbolic_operand (operands[0], SImode))
965 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
966 else if (GET_CODE (operands[0]) == MEM
967 && symbolic_operand (XEXP (operands[0], 0), SImode))
968 operands[0] = gen_rtx (MEM, SImode,
969 force_reg (SImode, XEXP (operands[0], 0)));
973 ;; General case of fullword move. The register constraints
974 ;; force integer constants in range for a moveq to be reloaded
975 ;; if they are headed for memory.
977 ;; Notes: make sure no alternative allows g vs g.
978 ;; We don't allow f-regs since fixed point cannot go in them.
979 ;; We do allow y and x regs since fixed point is allowed in them.
980 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d,a<,y,!*x*r*m")
981 (match_operand:SI 1 "general_src_operand" "daymSKT,n,i,g,*x*r*m"))]
986 if (which_alternative == 4)
987 return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\";
988 if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0]))
989 return \"fpmove%.l %x1,%x0\";
990 return output_move_simode (operands);
994 [(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g")
995 (match_operand:SI 1 "general_operand" "g,r<Q>"))]
997 "* return output_move_simode (operands);")
999 ;; Special case of fullword move, where we need to get a non-GOT PIC
1000 ;; reference into an address register.
1002 [(set (match_operand:SI 0 "nonimmediate_operand" "=a<")
1003 (match_operand:SI 1 "pcrel_address" ""))]
1007 if (push_operand (operands[0], SImode))
1009 return \"lea %a1,%0\";
1012 (define_expand "movhi"
1013 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1014 (match_operand:HI 1 "general_operand" ""))]
1019 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
1020 (match_operand:HI 1 "general_src_operand" "gS"))]
1022 "* return output_move_himode (operands);")
1025 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<Q>,g")
1026 (match_operand:HI 1 "general_operand" "g,r<Q>"))]
1028 "* return output_move_himode (operands);")
1030 (define_expand "movstricthi"
1031 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
1032 (match_operand:HI 1 "general_src_operand" ""))]
1037 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
1038 (match_operand:HI 1 "general_src_operand" "rmSn"))]
1040 "* return output_move_stricthi (operands);")
1043 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+d,m"))
1044 (match_operand:HI 1 "general_src_operand" "rmn,r"))]
1046 "* return output_move_stricthi (operands);")
1048 (define_expand "movqi"
1049 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1050 (match_operand:QI 1 "general_src_operand" ""))]
1055 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,*a,m")
1056 (match_operand:QI 1 "general_src_operand" "dmSi*a,di*a,dmSi"))]
1058 "* return output_move_qimode (operands);")
1061 [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>,dm,d*a")
1062 (match_operand:QI 1 "general_src_operand" "dmi,d<Q>,di*a"))]
1064 "* return output_move_qimode (operands);")
1066 (define_expand "movstrictqi"
1067 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
1068 (match_operand:QI 1 "general_src_operand" ""))]
1073 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
1074 (match_operand:QI 1 "general_src_operand" "dmSn"))]
1076 "* return output_move_strictqi (operands);")
1079 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+d,m"))
1080 (match_operand:QI 1 "general_src_operand" "dmn,d"))]
1082 "* return output_move_strictqi (operands);")
1084 (define_expand "pushqi1"
1085 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int -2)))
1086 (set (mem:QI (plus:SI (reg:SI 15) (const_int 1)))
1087 (match_operand:QI 0 "general_operand" ""))]
1091 (define_expand "movsf"
1092 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1093 (match_operand:SF 1 "general_operand" ""))]
1098 [(set (match_operand:SF 0 "nonimmediate_operand" "=rmf,x,y,rm,!x,!rm")
1099 (match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))]
1100 ; [(set (match_operand:SF 0 "nonimmediate_operand" "=rmf")
1101 ; (match_operand:SF 1 "general_operand" "rmfF"))]
1105 if (which_alternative >= 4)
1106 return \"fpmove%.s %1,fpa0\;fpmove%.s fpa0,%0\";
1107 if (FPA_REG_P (operands[0]))
1109 if (FPA_REG_P (operands[1]))
1110 return \"fpmove%.s %x1,%x0\";
1111 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1112 return output_move_const_single (operands);
1113 else if (FP_REG_P (operands[1]))
1114 return \"fmove%.s %1,sp@-\;fpmove%.d sp@+, %0\";
1115 return \"fpmove%.s %x1,%x0\";
1117 if (FPA_REG_P (operands[1]))
1119 if (FP_REG_P (operands[0]))
1120 return \"fpmove%.s %x1,sp@-\;fmove%.s sp@+,%0\";
1122 return \"fpmove%.s %x1,%x0\";
1124 if (FP_REG_P (operands[0]))
1126 if (FP_REG_P (operands[1]))
1127 return \"f%$move%.x %1,%0\";
1128 else if (ADDRESS_REG_P (operands[1]))
1129 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
1130 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1131 return output_move_const_single (operands);
1132 return \"f%$move%.s %f1,%0\";
1134 if (FP_REG_P (operands[1]))
1136 if (ADDRESS_REG_P (operands[0]))
1137 return \"fmove%.s %1,%-\;move%.l %+,%0\";
1138 return \"fmove%.s %f1,%0\";
1140 if (operands[1] == CONST0_RTX (SFmode)
1141 /* clr insns on 68000 read before writing.
1142 This isn't so on the 68010, but we have no TARGET_68010. */
1143 && ((TARGET_68020 || TARGET_5200)
1144 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1146 if (ADDRESS_REG_P (operands[0]))
1148 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
1149 if (!TARGET_68040 && !TARGET_68060)
1150 return \"sub%.l %0,%0\";
1155 /* Many SGS assemblers croak on size specifiers for constants. */
1156 return \"lea 0,%0\";
1158 return \"lea 0.w,%0\";
1161 return \"lea 0:w,%0\";
1165 /* moveq is faster on the 68000. */
1166 if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_5200))
1168 #if defined(MOTOROLA) && !defined(CRDS)
1169 return \"moveq%.l %#0,%0\";
1171 return \"moveq %#0,%0\";
1174 return \"clr%.l %0\";
1176 return \"move%.l %1,%0\";
1180 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,g")
1181 (match_operand:SF 1 "general_operand" "g,r"))]
1183 "* return \"move%.l %1,%0\";")
1185 (define_expand "movdf"
1186 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1187 (match_operand:DF 1 "general_operand" ""))]
1192 [(set (match_operand:DF 0 "nonimmediate_operand"
1193 "=*rm,*rf,*rf,&*rof<>,y,*rm,x,!x,!*rm")
1194 (match_operand:DF 1 "general_operand"
1195 "*rf,m,0,*rofE<>,*rmE,y,xH,*rm,x"))]
1196 ; [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,&rf,&rof<>")
1197 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
1201 if (which_alternative == 7)
1202 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1203 if (FPA_REG_P (operands[0]))
1205 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1206 return output_move_const_double (operands);
1207 if (FP_REG_P (operands[1]))
1208 return \"fmove%.d %1,sp@-\;fpmove%.d sp@+,%x0\";
1209 return \"fpmove%.d %x1,%x0\";
1211 else if (FPA_REG_P (operands[1]))
1213 if (FP_REG_P(operands[0]))
1214 return \"fpmove%.d %x1,sp@-\;fmoved sp@+,%0\";
1216 return \"fpmove%.d %x1,%x0\";
1218 if (FP_REG_P (operands[0]))
1220 if (FP_REG_P (operands[1]))
1221 return \"f%&move%.x %1,%0\";
1222 if (REG_P (operands[1]))
1225 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1226 output_asm_insn (\"move%.l %1,%-\", xoperands);
1227 output_asm_insn (\"move%.l %1,%-\", operands);
1228 return \"f%&move%.d %+,%0\";
1230 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1231 return output_move_const_double (operands);
1232 return \"f%&move%.d %f1,%0\";
1234 else if (FP_REG_P (operands[1]))
1236 if (REG_P (operands[0]))
1238 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1239 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1240 return \"move%.l %+,%0\";
1243 return \"fmove%.d %f1,%0\";
1245 return output_move_double (operands);
1249 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,g")
1250 (match_operand:DF 1 "general_operand" "g,r"))]
1252 "* return output_move_double (operands);")
1254 (define_expand "movxf"
1255 [(set (match_operand:XF 0 "nonimmediate_operand" "")
1256 (match_operand:XF 1 "general_operand" ""))]
1260 if (CONSTANT_P (operands[1]))
1262 operands[1] = force_const_mem (XFmode, operands[1]);
1263 if (! memory_address_p (XFmode, XEXP (operands[1], 0))
1264 && ! reload_in_progress)
1265 operands[1] = adjust_address (operands[1], XFmode, 0);
1267 if (flag_pic && TARGET_PCREL && ! reload_in_progress)
1269 /* Don't allow writes to memory except via a register;
1270 the m68k doesn't consider PC-relative addresses to be writable. */
1271 if (GET_CODE (operands[0]) == MEM
1272 && symbolic_operand (XEXP (operands[0], 0), SImode))
1273 operands[0] = gen_rtx (MEM, XFmode,
1274 force_reg (SImode, XEXP (operands[0], 0)));
1279 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f,!r")
1280 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r,!r"))]
1284 if (FP_REG_P (operands[0]))
1286 if (FP_REG_P (operands[1]))
1287 return \"fmove%.x %1,%0\";
1288 if (REG_P (operands[1]))
1291 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1292 output_asm_insn (\"move%.l %1,%-\", xoperands);
1293 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1294 output_asm_insn (\"move%.l %1,%-\", xoperands);
1295 output_asm_insn (\"move%.l %1,%-\", operands);
1296 return \"fmove%.x %+,%0\";
1298 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1299 return \"fmove%.x %1,%0\";
1300 return \"fmove%.x %f1,%0\";
1302 if (FP_REG_P (operands[1]))
1304 if (REG_P (operands[0]))
1306 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1307 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1308 output_asm_insn (\"move%.l %+,%0\", operands);
1309 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1310 return \"move%.l %+,%0\";
1312 /* Must be memory destination. */
1313 return \"fmove%.x %f1,%0\";
1315 return output_move_double (operands);
1320 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1321 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1322 "! TARGET_68881 && ! TARGET_5200"
1325 if (FP_REG_P (operands[0]))
1327 if (FP_REG_P (operands[1]))
1328 return \"fmove%.x %1,%0\";
1329 if (REG_P (operands[1]))
1332 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1333 output_asm_insn (\"move%.l %1,%-\", xoperands);
1334 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1335 output_asm_insn (\"move%.l %1,%-\", xoperands);
1336 output_asm_insn (\"move%.l %1,%-\", operands);
1337 return \"fmove%.x %+,%0\";
1339 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1340 return \"fmove%.x %1,%0\";
1341 return \"fmove%.x %f1,%0\";
1343 if (FP_REG_P (operands[1]))
1345 if (REG_P (operands[0]))
1347 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1348 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1349 output_asm_insn (\"move%.l %+,%0\", operands);
1350 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1351 return \"move%.l %+,%0\";
1354 return \"fmove%.x %f1,%0\";
1356 return output_move_double (operands);
1361 [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
1362 (match_operand:XF 1 "nonimmediate_operand" "g,r"))]
1363 "! TARGET_68881 && TARGET_5200"
1364 "* return output_move_double (operands);")
1366 (define_expand "movdi"
1367 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1368 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1369 (match_operand:DI 1 "general_operand" ""))]
1373 ;; movdi can apply to fp regs in some cases
1375 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1376 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r,&ro<>,y,rm,!*x,!rm")
1377 (match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))]
1378 ; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm")
1379 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))]
1380 ; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1381 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1385 if (which_alternative == 8)
1386 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1387 if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
1388 return \"fpmove%.d %x1,%x0\";
1389 if (FP_REG_P (operands[0]))
1391 if (FP_REG_P (operands[1]))
1392 return \"fmove%.x %1,%0\";
1393 if (REG_P (operands[1]))
1396 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1397 output_asm_insn (\"move%.l %1,%-\", xoperands);
1398 output_asm_insn (\"move%.l %1,%-\", operands);
1399 return \"fmove%.d %+,%0\";
1401 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1402 return output_move_const_double (operands);
1403 return \"fmove%.d %f1,%0\";
1405 else if (FP_REG_P (operands[1]))
1407 if (REG_P (operands[0]))
1409 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1410 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1411 return \"move%.l %+,%0\";
1414 return \"fmove%.d %f1,%0\";
1416 return output_move_double (operands);
1420 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,g")
1421 (match_operand:DI 1 "general_operand" "g,r"))]
1423 "* return output_move_double (operands);")
1425 ;; Thus goes after the move instructions
1426 ;; because the move instructions are better (require no spilling)
1427 ;; when they can apply. It goes before the add/sub insns
1428 ;; so we will prefer it to them.
1430 (define_insn "pushasi"
1431 [(set (match_operand:SI 0 "push_operand" "=m")
1432 (match_operand:SI 1 "address_operand" "p"))]
1436 ;; truncation instructions
1437 (define_insn "truncsiqi2"
1438 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d")
1440 (match_operand:SI 1 "general_src_operand" "doJS,i")))]
1444 if (GET_CODE (operands[0]) == REG)
1446 /* Must clear condition codes, since the move.l bases them on
1447 the entire 32 bits, not just the desired 8 bits. */
1449 return \"move%.l %1,%0\";
1451 if (GET_CODE (operands[1]) == MEM)
1452 operands[1] = adjust_address (operands[1], QImode, 3);
1453 return \"move%.b %1,%0\";
1456 (define_insn "trunchiqi2"
1457 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d")
1459 (match_operand:HI 1 "general_src_operand" "doJS,i")))]
1463 if (GET_CODE (operands[0]) == REG
1464 && (GET_CODE (operands[1]) == MEM
1465 || GET_CODE (operands[1]) == CONST_INT))
1467 /* Must clear condition codes, since the move.w bases them on
1468 the entire 16 bits, not just the desired 8 bits. */
1470 return \"move%.w %1,%0\";
1472 if (GET_CODE (operands[0]) == REG)
1474 /* Must clear condition codes, since the move.l bases them on
1475 the entire 32 bits, not just the desired 8 bits. */
1477 return \"move%.l %1,%0\";
1479 if (GET_CODE (operands[1]) == MEM)
1480 operands[1] = adjust_address (operands[1], QImode, 1);
1481 return \"move%.b %1,%0\";
1484 (define_insn "truncsihi2"
1485 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm,d")
1487 (match_operand:SI 1 "general_src_operand" "roJS,i")))]
1491 if (GET_CODE (operands[0]) == REG)
1493 /* Must clear condition codes, since the move.l bases them on
1494 the entire 32 bits, not just the desired 8 bits. */
1496 return \"move%.l %1,%0\";
1498 if (GET_CODE (operands[1]) == MEM)
1499 operands[1] = adjust_address (operands[1], QImode, 2);
1500 return \"move%.w %1,%0\";
1503 ;; zero extension instructions
1505 (define_insn "zero_extendqidi2"
1506 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
1507 (zero_extend:DI (match_operand:QI 1 "general_operand" "dm")))]
1512 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1513 return \"moveq %#0,%0\;moveq %#0,%2\;move%.b %1,%2\";
1516 (define_insn "zero_extendhidi2"
1517 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
1518 (zero_extend:DI (match_operand:HI 1 "general_operand" "rm")))]
1523 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1524 return \"moveq %#0,%0\;moveq %#0,%2\;move%.w %1,%2\";
1527 ;; this is the canonical form for (lshiftrt:DI x 32)
1528 (define_expand "zero_extendsidi2"
1529 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1530 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))]
1534 (define_insn "*zero_extendsidi2_cf"
1535 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,m")
1536 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm,r")))]
1541 if (GET_CODE (operands[0]) == REG)
1542 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1543 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1544 return \"move%.l %1,%0\;clr%.l %0\";
1545 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1546 return \"clr%.l %0\;move%.l %1,%0\";
1548 operands[2] = adjust_address (operands[0], SImode, 4);
1549 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[2]) != REG
1550 || REGNO (operands[1]) != REGNO (operands[2]))
1551 output_asm_insn (\"move%.l %1,%2\", operands);
1552 if (ADDRESS_REG_P (operands[0]))
1553 return \"sub%.l %0,%0\";
1555 return \"clr%.l %0\";
1558 (define_insn "*zero_extendsidi2"
1559 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
1560 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
1565 if (GET_CODE (operands[0]) == REG)
1566 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1567 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1568 return \"move%.l %1,%0\;clr%.l %0\";
1569 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1570 return \"clr%.l %0\;move%.l %1,%0\";
1572 operands[2] = adjust_address (operands[0], SImode, 4);
1573 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[2]) != REG
1574 || REGNO (operands[1]) != REGNO (operands[2]))
1575 output_asm_insn (\"move%.l %1,%2\", operands);
1576 if (ADDRESS_REG_P (operands[0]))
1577 return \"sub%.l %0,%0\";
1579 return \"clr%.l %0\";
1582 (define_expand "zero_extendhisi2"
1583 [(set (match_operand:SI 0 "register_operand" "")
1585 (set (strict_low_part (match_dup 2))
1586 (match_operand:HI 1 "general_operand" ""))]
1590 operands[1] = make_safe_from (operands[1], operands[0]);
1591 operands[2] = gen_lowpart (HImode, operands[0]);
1594 (define_expand "zero_extendqihi2"
1595 [(set (match_operand:HI 0 "register_operand" "")
1597 (set (strict_low_part (match_dup 2))
1598 (match_operand:QI 1 "general_operand" ""))]
1602 operands[1] = make_safe_from (operands[1], operands[0]);
1603 operands[2] = gen_lowpart (QImode, operands[0]);
1606 (define_expand "zero_extendqisi2"
1607 [(set (match_operand:SI 0 "register_operand" "")
1609 (set (strict_low_part (match_dup 2))
1610 (match_operand:QI 1 "general_operand" ""))]
1614 operands[1] = make_safe_from (operands[1], operands[0]);
1615 operands[2] = gen_lowpart (QImode, operands[0]);
1618 ;; Patterns to recognize zero-extend insns produced by the combiner.
1619 ;; We don't allow both operands in memory, because of aliasing problems.
1620 ;; Explicitly disallow two memory operands via the condition since reloading
1621 ;; of this case will result in worse code than the uncombined patterns.
1624 [(set (match_operand:SI 0 "nonimmediate_operand" "=do<>,d<")
1625 (zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "r,mS")))]
1626 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1629 if (DATA_REG_P (operands[0]))
1631 if (GET_CODE (operands[1]) == REG
1632 && REGNO (operands[0]) == REGNO (operands[1]))
1633 return \"and%.l %#0xFFFF,%0\";
1634 if (reg_mentioned_p (operands[0], operands[1]))
1635 return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\";
1636 return \"clr%.l %0\;move%.w %1,%0\";
1638 else if (GET_CODE (operands[0]) == MEM
1639 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1640 return \"move%.w %1,%0\;clr%.w %0\";
1641 else if (GET_CODE (operands[0]) == MEM
1642 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1643 return \"clr%.w %0\;move%.w %1,%0\";
1646 output_asm_insn (\"clr%.w %0\", operands);
1647 operands[0] = adjust_address (operands[0], HImode, 2);
1648 return \"move%.w %1,%0\";
1653 [(set (match_operand:HI 0 "nonimmediate_operand" "=do<>,d")
1654 (zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "d,mS")))]
1655 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1658 if (DATA_REG_P (operands[0]))
1660 if (GET_CODE (operands[1]) == REG
1661 && REGNO (operands[0]) == REGNO (operands[1]))
1662 return (!TARGET_5200 ? \"and%.w %#0xFF,%0\" : \"and%.l %#0xFF,%0\");
1663 if (reg_mentioned_p (operands[0], operands[1]))
1664 return (!TARGET_5200 ? \"move%.b %1,%0\;and%.w %#0xFF,%0\"
1665 : \"move%.b %1,%0\;and%.l %#0xFF,%0\");
1666 return \"clr%.w %0\;move%.b %1,%0\";
1668 else if (GET_CODE (operands[0]) == MEM
1669 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1671 if (REGNO (XEXP (XEXP (operands[0], 0), 0))
1672 == STACK_POINTER_REGNUM)
1674 output_asm_insn (\"clr%.w %-\", operands);
1675 operands[0] = gen_rtx_MEM (GET_MODE (operands[0]),
1676 plus_constant (stack_pointer_rtx, 1));
1677 return \"move%.b %1,%0\";
1680 return \"move%.b %1,%0\;clr%.b %0\";
1682 else if (GET_CODE (operands[0]) == MEM
1683 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1684 return \"clr%.b %0\;move%.b %1,%0\";
1687 output_asm_insn (\"clr%.b %0\", operands);
1688 operands[0] = adjust_address (operands[0], QImode, 1);
1689 return \"move%.b %1,%0\";
1694 [(set (match_operand:SI 0 "nonimmediate_operand" "=do<>,d")
1695 (zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "d,mS")))]
1696 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1699 if (DATA_REG_P (operands[0]))
1701 if (GET_CODE (operands[1]) == REG
1702 && REGNO (operands[0]) == REGNO (operands[1]))
1703 return \"and%.l %#0xFF,%0\";
1704 if (reg_mentioned_p (operands[0], operands[1]))
1705 return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
1706 return \"clr%.l %0\;move%.b %1,%0\";
1708 else if (GET_CODE (operands[0]) == MEM
1709 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1711 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1714 return \"clr%.l -(%0)\;move%.b %1,3(%0)\";
1716 return \"clr%.l -(%0)\;move%.b %1,(3,%0)\";
1719 return \"clrl %0@-\;moveb %1,%0@(3)\";
1722 else if (GET_CODE (operands[0]) == MEM
1723 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1725 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1728 return \"clr%.l (%0)+\;move%.b %1,-1(%0)\";
1730 return \"clr%.l (%0)+\;move%.b %1,(-1,%0)\";
1733 return \"clrl %0@+\;moveb %1,%0@(-1)\";
1738 output_asm_insn (\"clr%.l %0\", operands);
1739 operands[0] = adjust_address (operands[0], QImode, 3);
1740 return \"move%.b %1,%0\";
1744 ;; sign extension instructions
1746 (define_insn "extendqidi2"
1747 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1748 (sign_extend:DI (match_operand:QI 1 "general_src_operand" "rmS")))]
1753 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1754 if (TARGET_68020 || TARGET_5200)
1755 return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
1757 return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
1760 (define_insn "extendhidi2"
1761 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1763 (match_operand:HI 1 "general_src_operand" "rmS")))]
1768 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1769 if (TARGET_68020 || TARGET_5200)
1770 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
1772 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
1775 (define_insn "extendsidi2"
1776 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1778 (match_operand:SI 1 "general_operand" "rm")))]
1783 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1784 if (TARGET_68020 || TARGET_5200)
1785 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
1787 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
1790 ;; Special case when one can avoid register clobbering, copy and test
1791 ;; Maybe there is a way to make that the general case, by forcing the
1792 ;; result of the SI tree to be in the lower register of the DI target
1794 (define_insn "extendplussidi"
1795 [(set (match_operand:DI 0 "register_operand" "=d")
1796 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1797 (match_operand:SI 2 "general_operand" "rmn"))))]
1802 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1803 if (GET_CODE (operands[1]) == CONST_INT
1804 && (unsigned) INTVAL (operands[1]) > 8)
1806 rtx tmp = operands[1];
1808 operands[1] = operands[2];
1811 if (GET_CODE (operands[1]) == REG
1812 && REGNO (operands[1]) == REGNO (operands[3]))
1813 output_asm_insn (\"add%.l %2,%3\", operands);
1815 output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands);
1816 if (TARGET_68020 || TARGET_5200)
1817 return \"smi %0\;extb%.l %0\";
1819 return \"smi %0\;ext%.w %0\;ext%.l %0\";
1822 (define_insn "extendhisi2"
1823 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,a")
1825 (match_operand:HI 1 "nonimmediate_src_operand" "0,rmS")))]
1829 if (ADDRESS_REG_P (operands[0]))
1830 return \"move%.w %1,%0\";
1831 return \"ext%.l %0\";
1834 (define_insn "extendqihi2"
1835 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
1836 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1840 (define_insn "extendqisi2"
1841 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
1842 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1843 "TARGET_68020 || TARGET_5200"
1846 ;; Conversions between float and double.
1848 (define_expand "extendsfdf2"
1849 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1851 (match_operand:SF 1 "general_operand" "")))]
1852 "TARGET_68881 || TARGET_FPA"
1856 [(set (match_operand:DF 0 "nonimmediate_operand" "=x,y")
1858 (match_operand:SF 1 "general_operand" "xH,rmF")))]
1863 [(set (match_operand:DF 0 "nonimmediate_operand" "=*fdm,f")
1865 (match_operand:SF 1 "general_operand" "f,dmF")))]
1869 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1871 if (REGNO (operands[0]) == REGNO (operands[1]))
1873 /* Extending float to double in an fp-reg is a no-op.
1874 NOTICE_UPDATE_CC has already assumed that the
1875 cc will be set. So cancel what it did. */
1876 cc_status = cc_prev_status;
1879 return \"f%&move%.x %1,%0\";
1881 if (FP_REG_P (operands[0]))
1882 return \"f%&move%.s %f1,%0\";
1883 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1885 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1886 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1887 return \"move%.l %+,%0\";
1889 return \"fmove%.d %f1,%0\";
1892 ;; This cannot output into an f-reg because there is no way to be
1893 ;; sure of truncating in that case.
1894 ;; But on the Sun FPA, we can be sure.
1895 (define_expand "truncdfsf2"
1896 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1898 (match_operand:DF 1 "general_operand" "")))]
1899 "TARGET_68881 || TARGET_FPA"
1903 [(set (match_operand:SF 0 "nonimmediate_operand" "=x,y")
1905 (match_operand:DF 1 "general_operand" "xH,rmF")))]
1909 ;; On the '040 we can truncate in a register accurately and easily.
1911 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1913 (match_operand:DF 1 "general_operand" "fmG")))]
1917 if (FP_REG_P (operands[1]))
1918 return \"f%$move%.x %1,%0\";
1919 return \"f%$move%.d %f1,%0\";
1923 [(set (match_operand:SF 0 "nonimmediate_operand" "=dm")
1925 (match_operand:DF 1 "general_operand" "f")))]
1929 ;; Conversion between fixed point and floating point.
1930 ;; Note that among the fix-to-float insns
1931 ;; the ones that start with SImode come first.
1932 ;; That is so that an operand that is a CONST_INT
1933 ;; (and therefore lacks a specific machine mode).
1934 ;; will be recognized as SImode (which is always valid)
1935 ;; rather than as QImode or HImode.
1937 (define_expand "floatsisf2"
1938 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1939 (float:SF (match_operand:SI 1 "general_operand" "")))]
1940 "TARGET_68881 || TARGET_FPA"
1944 [(set (match_operand:SF 0 "nonimmediate_operand" "=y,x")
1945 (float:SF (match_operand:SI 1 "general_operand" "rmi,x")))]
1950 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1951 (float:SF (match_operand:SI 1 "general_operand" "dmi")))]
1955 (define_expand "floatsidf2"
1956 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1957 (float:DF (match_operand:SI 1 "general_operand" "")))]
1958 "TARGET_68881 || TARGET_FPA"
1962 [(set (match_operand:DF 0 "nonimmediate_operand" "=y,x")
1963 (float:DF (match_operand:SI 1 "general_operand" "rmi,x")))]
1968 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
1969 (float:DF (match_operand:SI 1 "general_operand" "dmi")))]
1973 (define_insn "floathisf2"
1974 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1975 (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
1979 (define_insn "floathidf2"
1980 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
1981 (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
1985 (define_insn "floatqisf2"
1986 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1987 (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
1991 (define_insn "floatqidf2"
1992 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
1993 (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
1997 ;; New routines to convert floating-point values to integers
1998 ;; to be used on the '040. These should be faster than trapping
1999 ;; into the kernel to emulate fintrz. They should also be faster
2000 ;; than calling the subroutines fixsfsi or fixdfsi.
2002 (define_insn "fix_truncdfsi2"
2003 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
2004 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
2005 (clobber (match_scratch:SI 2 "=d"))
2006 (clobber (match_scratch:SI 3 "=d"))]
2007 "TARGET_68881 && TARGET_68040"
2011 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\";
2014 (define_insn "fix_truncdfhi2"
2015 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
2016 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
2017 (clobber (match_scratch:SI 2 "=d"))
2018 (clobber (match_scratch:SI 3 "=d"))]
2019 "TARGET_68881 && TARGET_68040"
2023 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\";
2026 (define_insn "fix_truncdfqi2"
2027 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
2028 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
2029 (clobber (match_scratch:SI 2 "=d"))
2030 (clobber (match_scratch:SI 3 "=d"))]
2031 "TARGET_68881 && TARGET_68040"
2035 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\";
2038 ;; Convert a float to a float whose value is an integer.
2039 ;; This is the first stage of converting it to an integer type.
2041 (define_insn "ftruncdf2"
2042 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2043 (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
2044 "TARGET_68881 && !TARGET_68040"
2047 if (FP_REG_P (operands[1]))
2048 return \"fintrz%.x %f1,%0\";
2049 return \"fintrz%.d %f1,%0\";
2052 (define_insn "ftruncsf2"
2053 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2054 (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
2055 "TARGET_68881 && !TARGET_68040"
2058 if (FP_REG_P (operands[1]))
2059 return \"fintrz%.x %f1,%0\";
2060 return \"fintrz%.s %f1,%0\";
2063 ;; Convert a float whose value is an integer
2064 ;; to an actual integer. Second stage of converting float to integer type.
2065 (define_insn "fixsfqi2"
2066 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
2067 (fix:QI (match_operand:SF 1 "general_operand" "f")))]
2071 (define_insn "fixsfhi2"
2072 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
2073 (fix:HI (match_operand:SF 1 "general_operand" "f")))]
2077 (define_insn "fixsfsi2"
2078 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
2079 (fix:SI (match_operand:SF 1 "general_operand" "f")))]
2083 (define_insn "fixdfqi2"
2084 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
2085 (fix:QI (match_operand:DF 1 "general_operand" "f")))]
2089 (define_insn "fixdfhi2"
2090 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
2091 (fix:HI (match_operand:DF 1 "general_operand" "f")))]
2095 (define_insn "fixdfsi2"
2096 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
2097 (fix:SI (match_operand:DF 1 "general_operand" "f")))]
2101 ;; Convert a float to an integer.
2102 ;; On the Sun FPA, this is done in one step.
2105 [(set (match_operand:SI 0 "nonimmediate_operand" "=x,y")
2106 (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "xH,rmF"))))]
2111 [(set (match_operand:SI 0 "nonimmediate_operand" "=x,y")
2112 (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "xH,rmF"))))]
2118 (define_insn "adddi_lshrdi_63"
2119 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
2120 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
2123 (clobber (match_scratch:SI 2 "=d"))]
2127 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2128 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
2130 \"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0\";
2131 if (GET_CODE (operands[1]) == REG)
2132 operands[4] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2133 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
2134 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2135 operands[4] = operands[1];
2137 operands[4] = adjust_address (operands[1], SImode, 4);
2138 if (GET_CODE (operands[1]) == MEM
2139 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2140 output_asm_insn (\"move%.l %4,%3\", operands);
2141 output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
2142 if (TARGET_68020 || TARGET_5200)
2143 output_asm_insn (\"extb%.l %2\", operands);
2145 output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
2146 if (GET_CODE (operands[1]) != MEM
2147 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
2148 output_asm_insn (\"move%.l %4,%3\", operands);
2149 return \"sub%.l %2,%3\;subx%.l %2,%0\";
2152 (define_insn "adddi_sexthishl32"
2153 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,a,*d,*d")
2154 (plus:DI (ashift:DI (sign_extend:DI
2155 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
2157 (match_operand:DI 2 "general_operand" "0,0,0,0")))
2158 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2163 if (ADDRESS_REG_P (operands[0]))
2164 return \"add%.w %1,%0\";
2165 else if (ADDRESS_REG_P (operands[3]))
2166 return \"move%.w %1,%3\;add%.l %3,%0\";
2168 return \"move%.w %1,%3\;ext%.l %3\;add%.l %3,%0\";
2171 (define_insn "adddi_dilshr32"
2172 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,o")
2173 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2174 ;; (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
2175 ;; (const_int 32))))]
2176 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,d")
2178 (match_operand:DI 2 "general_operand" "0,0")))]
2183 if (GET_CODE (operands[0]) == REG)
2184 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2186 operands[2] = adjust_address (operands[0], SImode, 4);
2187 return \"add%.l %1,%2\;negx%.l %0\;neg%.l %0\";
2190 (define_insn "adddi_dishl32"
2191 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
2192 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2193 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2194 ;; (const_int 32))))]
2195 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro,d")
2197 (match_operand:DI 2 "general_operand" "0,0")))]
2202 if (GET_CODE (operands[1]) == REG)
2203 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2205 operands[1] = adjust_address (operands[1], SImode, 4);
2206 return \"add%.l %1,%0\";
2209 (define_insn "adddi3"
2210 [(set (match_operand:DI 0 "nonimmediate_operand" "=<,o<>,d,d,d")
2211 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0,0")
2212 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2213 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2217 if (DATA_REG_P (operands[0]))
2219 if (DATA_REG_P (operands[2]))
2220 return \"add%.l %R2,%R0\;addx%.l %2,%0\";
2221 else if (GET_CODE (operands[2]) == MEM
2222 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2223 return \"move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0\";
2229 if (GET_CODE (operands[2]) == REG)
2231 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2234 else if (CONSTANT_P (operands[2]))
2235 split_double (operands[2], &high, &low);
2238 low = adjust_address (operands[2], SImode, 4);
2242 operands[1] = low, operands[2] = high;
2243 xoperands[0] = operands[3];
2244 if (GET_CODE (operands[1]) == CONST_INT
2245 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2246 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2248 xoperands[1] = operands[2];
2250 output_asm_insn (output_move_simode (xoperands), xoperands);
2251 if (GET_CODE (operands[1]) == CONST_INT)
2253 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2256 return \"add%.l %1,%R0\;addx%.l %3,%0\";
2258 return \"addq%.l %1,%R0\;addx%.l %3,%0\";
2261 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2263 operands[1] = GEN_INT (-INTVAL (operands[1]));
2265 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2267 return \"subq%.l %1,%R0\;subx%.l %3,%0\";
2271 return \"add%.l %1,%R0\;addx%.l %3,%0\";
2274 else if (GET_CODE (operands[0]) == MEM)
2276 if (GET_CODE (operands[2]) == MEM
2277 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2278 return \"add%.l %2,%0\;addx%.l %2,%0\";
2280 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2282 operands[1] = gen_rtx_MEM (SImode,
2283 plus_constant (XEXP(operands[0], 0), -8));
2284 return \"move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1\";
2286 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2288 operands[1] = XEXP(operands[0], 0);
2289 return \"add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
2293 operands[1] = adjust_address (operands[0], SImode, 4);
2294 return \"add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
2301 (define_insn "addsi_lshrsi_31"
2302 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
2303 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
2309 operands[2] = operands[0];
2310 operands[3] = gen_label_rtx();
2311 if (GET_CODE (operands[0]) == MEM)
2313 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2314 operands[0] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2315 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2316 operands[2] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2318 output_asm_insn (\"move%.l %1,%0\", operands);
2320 output_asm_insn (\"jbpl %l3\", operands);
2322 output_asm_insn (\"jpl %l3\", operands);
2325 output_asm_insn (\"addq%.l %#1,%2\", operands);
2327 output_asm_insn (\"add%.l %#1,%2\", operands);
2329 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2330 CODE_LABEL_NUMBER (operands[3]));
2334 (define_expand "addsi3"
2335 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2336 (plus:SI (match_operand:SI 1 "general_operand" "")
2337 (match_operand:SI 2 "general_src_operand" "")))]
2341 ;; Note that the middle two alternatives are near-duplicates
2342 ;; in order to handle insns generated by reload.
2343 ;; This is needed since they are not themselves reloaded,
2344 ;; so commutativity won't apply to them.
2345 (define_insn "*addsi3_internal"
2346 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,d,a")
2347 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0,0")
2348 (match_operand:SI 2 "general_src_operand" "dIKLT,rJK,a,mSrIKLT,mSrIKLs")))]
2352 "* return output_addsi3 (operands);")
2354 (define_insn "*addsi3_5200"
2355 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,r")
2356 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2357 (match_operand:SI 2 "general_src_operand" "d,rJK,a,mrIKLs")))]
2359 "* return output_addsi3 (operands);")
2362 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
2363 (plus:SI (match_operand:SI 1 "general_operand" "0")
2365 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2369 (define_insn "addhi3"
2370 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
2371 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2372 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2376 if (GET_CODE (operands[2]) == CONST_INT)
2379 /* If the constant would be a negative number when interpreted as
2380 HImode, make it negative. This is usually, but not always, done
2381 elsewhere in the compiler. First check for constants out of range,
2382 which could confuse us. */
2384 if (INTVAL (operands[2]) >= 32768)
2385 operands[2] = GEN_INT (INTVAL (operands[2]) - 65536);
2387 if (INTVAL (operands[2]) > 0
2388 && INTVAL (operands[2]) <= 8)
2389 return \"addq%.w %2,%0\";
2390 if (INTVAL (operands[2]) < 0
2391 && INTVAL (operands[2]) >= -8)
2393 operands[2] = GEN_INT (- INTVAL (operands[2]));
2394 return \"subq%.w %2,%0\";
2396 /* On the CPU32 it is faster to use two addqw instructions to
2397 add a small integer (8 < N <= 16) to a register.
2398 Likewise for subqw. */
2399 if (TARGET_CPU32 && REG_P (operands[0]))
2401 if (INTVAL (operands[2]) > 8
2402 && INTVAL (operands[2]) <= 16)
2404 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
2405 return \"addq%.w %#8,%0\;addq%.w %2,%0\";
2407 if (INTVAL (operands[2]) < -8
2408 && INTVAL (operands[2]) >= -16)
2410 operands[2] = GEN_INT (- INTVAL (operands[2]) - 8);
2411 return \"subq%.w %#8,%0\;subq%.w %2,%0\";
2415 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2417 return \"lea (%c2,%0),%0\";
2419 return \"lea %0@(%c2),%0\";
2422 return \"add%.w %2,%0\";
2425 ;; These insns must use MATCH_DUP instead of the more expected
2426 ;; use of a matching constraint because the "output" here is also
2427 ;; an input, so you can't use the matching constraint. That also means
2428 ;; that you can't use the "%", so you need patterns with the matched
2429 ;; operand in both positions.
2432 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2433 (plus:HI (match_dup 0)
2434 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2438 if (GET_CODE (operands[1]) == CONST_INT)
2441 /* If the constant would be a negative number when interpreted as
2442 HImode, make it negative. This is usually, but not always, done
2443 elsewhere in the compiler. First check for constants out of range,
2444 which could confuse us. */
2446 if (INTVAL (operands[1]) >= 32768)
2447 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2449 if (INTVAL (operands[1]) > 0
2450 && INTVAL (operands[1]) <= 8)
2451 return \"addq%.w %1,%0\";
2452 if (INTVAL (operands[1]) < 0
2453 && INTVAL (operands[1]) >= -8)
2455 operands[1] = GEN_INT (- INTVAL (operands[1]));
2456 return \"subq%.w %1,%0\";
2458 /* On the CPU32 it is faster to use two addqw instructions to
2459 add a small integer (8 < N <= 16) to a register.
2460 Likewise for subqw. */
2461 if (TARGET_CPU32 && REG_P (operands[0]))
2463 if (INTVAL (operands[1]) > 8
2464 && INTVAL (operands[1]) <= 16)
2466 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2467 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2469 if (INTVAL (operands[1]) < -8
2470 && INTVAL (operands[1]) >= -16)
2472 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
2473 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2477 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2479 return \"lea (%c1,%0),%0\";
2481 return \"lea %0@(%c1),%0\";
2484 return \"add%.w %1,%0\";
2488 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2489 (plus:HI (match_operand:HI 1 "general_src_operand" "dn,rmSn")
2494 if (GET_CODE (operands[1]) == CONST_INT)
2497 /* If the constant would be a negative number when interpreted as
2498 HImode, make it negative. This is usually, but not always, done
2499 elsewhere in the compiler. First check for constants out of range,
2500 which could confuse us. */
2502 if (INTVAL (operands[1]) >= 32768)
2503 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2505 if (INTVAL (operands[1]) > 0
2506 && INTVAL (operands[1]) <= 8)
2507 return \"addq%.w %1,%0\";
2508 if (INTVAL (operands[1]) < 0
2509 && INTVAL (operands[1]) >= -8)
2511 operands[1] = GEN_INT (- INTVAL (operands[1]));
2512 return \"subq%.w %1,%0\";
2514 /* On the CPU32 it is faster to use two addqw instructions to
2515 add a small integer (8 < N <= 16) to a register.
2516 Likewise for subqw. */
2517 if (TARGET_CPU32 && REG_P (operands[0]))
2519 if (INTVAL (operands[1]) > 8
2520 && INTVAL (operands[1]) <= 16)
2522 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2523 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2525 if (INTVAL (operands[1]) < -8
2526 && INTVAL (operands[1]) >= -16)
2528 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
2529 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2533 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2535 return \"lea (%c1,%0),%0\";
2537 return \"lea %0@(%c1),%0\";
2540 return \"add%.w %1,%0\";
2543 (define_insn "addqi3"
2544 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
2545 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2546 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2551 if (GET_CODE (operands[2]) == CONST_INT)
2553 if (INTVAL (operands[2]) >= 128)
2554 operands[2] = GEN_INT (INTVAL (operands[2]) - 256);
2556 if (INTVAL (operands[2]) > 0
2557 && INTVAL (operands[2]) <= 8)
2558 return \"addq%.b %2,%0\";
2559 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2561 operands[2] = GEN_INT (- INTVAL (operands[2]));
2562 return \"subq%.b %2,%0\";
2566 return \"add%.b %2,%0\";
2570 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2571 (plus:QI (match_dup 0)
2572 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2577 if (GET_CODE (operands[1]) == CONST_INT)
2579 if (INTVAL (operands[1]) >= 128)
2580 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2582 if (INTVAL (operands[1]) > 0
2583 && INTVAL (operands[1]) <= 8)
2584 return \"addq%.b %1,%0\";
2585 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2587 operands[1] = GEN_INT (- INTVAL (operands[1]));
2588 return \"subq%.b %1,%0\";
2592 return \"add%.b %1,%0\";
2596 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2597 (plus:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
2603 if (GET_CODE (operands[1]) == CONST_INT)
2605 if (INTVAL (operands[1]) >= 128)
2606 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2608 if (INTVAL (operands[1]) > 0
2609 && INTVAL (operands[1]) <= 8)
2610 return \"addq%.b %1,%0\";
2611 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2613 operands[1] = GEN_INT (- INTVAL (operands[1]));
2614 return \"subq%.b %1,%0\";
2618 return \"add%.b %1,%0\";
2621 (define_expand "adddf3"
2622 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2623 (plus:DF (match_operand:DF 1 "general_operand" "")
2624 (match_operand:DF 2 "general_operand" "")))]
2625 "TARGET_68881 || TARGET_FPA"
2629 [(set (match_operand:DF 0 "nonimmediate_operand" "=x,y")
2630 (plus:DF (match_operand:DF 1 "general_operand" "%xH,y")
2631 (match_operand:DF 2 "general_operand" "xH,dmF")))]
2635 if (rtx_equal_p (operands[0], operands[1]))
2636 return \"fpadd%.d %y2,%0\";
2637 if (rtx_equal_p (operands[0], operands[2]))
2638 return \"fpadd%.d %y1,%0\";
2639 if (which_alternative == 0)
2640 return \"fpadd3%.d %w2,%w1,%0\";
2641 return \"fpadd3%.d %x2,%x1,%0\";
2645 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2646 (plus:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2647 (match_operand:DF 1 "general_operand" "0")))]
2652 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2653 (plus:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2654 (match_operand:DF 1 "general_operand" "0")))]
2659 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2660 (plus:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2661 (match_operand:DF 1 "general_operand" "0")))]
2666 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2667 (plus:DF (match_operand:DF 1 "general_operand" "%0")
2668 (match_operand:DF 2 "general_operand" "fmG")))]
2672 if (REG_P (operands[2]))
2673 return \"f%&add%.x %2,%0\";
2674 return \"f%&add%.d %f2,%0\";
2677 (define_expand "addsf3"
2678 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2679 (plus:SF (match_operand:SF 1 "general_operand" "")
2680 (match_operand:SF 2 "general_operand" "")))]
2681 "TARGET_68881 || TARGET_FPA"
2685 [(set (match_operand:SF 0 "nonimmediate_operand" "=x,y")
2686 (plus:SF (match_operand:SF 1 "general_operand" "%xH,y")
2687 (match_operand:SF 2 "general_operand" "xH,rmF")))]
2691 if (rtx_equal_p (operands[0], operands[1]))
2692 return \"fpadd%.s %w2,%0\";
2693 if (rtx_equal_p (operands[0], operands[2]))
2694 return \"fpadd%.s %w1,%0\";
2695 if (which_alternative == 0)
2696 return \"fpadd3%.s %w2,%w1,%0\";
2697 return \"fpadd3%.s %2,%1,%0\";
2701 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2702 (plus:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2703 (match_operand:SF 1 "general_operand" "0")))]
2708 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2709 (plus:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
2710 (match_operand:SF 1 "general_operand" "0")))]
2715 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2716 (plus:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
2717 (match_operand:SF 1 "general_operand" "0")))]
2722 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2723 (plus:SF (match_operand:SF 1 "general_operand" "%0")
2724 (match_operand:SF 2 "general_operand" "fdmF")))]
2728 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2729 return \"f%$add%.x %2,%0\";
2730 return \"f%$add%.s %f2,%0\";
2733 ;; subtract instructions
2735 (define_insn "subdi_sexthishl32"
2736 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,a,*d,*d")
2737 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2738 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2740 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2745 if (ADDRESS_REG_P (operands[0]))
2746 return \"sub%.w %2,%0\";
2747 else if (ADDRESS_REG_P (operands[3]))
2748 return \"move%.w %2,%3\;sub%.l %3,%0\";
2750 return \"move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0\";
2753 (define_insn "subdi_dishl32"
2754 [(set (match_operand:DI 0 "nonimmediate_operand" "+ro")
2755 (minus:DI (match_dup 0)
2756 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2762 if (GET_CODE (operands[1]) == REG)
2763 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2765 operands[1] = adjust_address (operands[1], SImode, 4);
2766 return \"sub%.l %1,%0\";
2769 (define_insn "subdi3"
2770 [(set (match_operand:DI 0 "nonimmediate_operand" "=<,o<>,d,d,d")
2771 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0,0")
2772 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2773 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2777 if (DATA_REG_P (operands[0]))
2779 if (DATA_REG_P (operands[2]))
2780 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
2781 else if (GET_CODE (operands[2]) == MEM
2782 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2784 return \"move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0\";
2791 if (GET_CODE (operands[2]) == REG)
2793 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2796 else if (CONSTANT_P (operands[2]))
2797 split_double (operands[2], &high, &low);
2800 low = adjust_address (operands[2], SImode, 4);
2804 operands[1] = low, operands[2] = high;
2805 xoperands[0] = operands[3];
2806 if (GET_CODE (operands[1]) == CONST_INT
2807 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2808 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2810 xoperands[1] = operands[2];
2812 output_asm_insn (output_move_simode (xoperands), xoperands);
2813 if (GET_CODE (operands[1]) == CONST_INT)
2815 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2818 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2820 return \"subq%.l %1,%R0\;subx%.l %3,%0\";
2823 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2825 operands[1] = GEN_INT (-INTVAL (operands[1]));
2827 return \"add%.l %1,%R0\;addx%.l %3,%0\";
2829 return \"addq%.l %1,%R0\;addx%.l %3,%0\";
2833 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2836 else if (GET_CODE (operands[0]) == MEM)
2838 if (GET_CODE (operands[2]) == MEM
2839 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2840 return \"sub%.l %2,%0\;subx%.l %2,%0\";
2842 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2845 = gen_rtx_MEM (SImode, plus_constant (XEXP (operands[0], 0), -8));
2846 return \"move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1\";
2848 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2850 operands[1] = XEXP(operands[0], 0);
2851 return \"sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
2855 operands[1] = adjust_address (operands[0], SImode, 4);
2856 return \"sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
2863 (define_insn "subsi3"
2864 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d,a")
2865 (minus:SI (match_operand:SI 1 "general_operand" "0,0,0")
2866 (match_operand:SI 2 "general_src_operand" "dT,mSrT,mSrs")))]
2871 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
2872 (minus:SI (match_operand:SI 1 "general_operand" "0")
2874 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2878 (define_insn "subhi3"
2879 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
2880 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2881 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2886 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2887 (minus:HI (match_dup 0)
2888 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2892 (define_insn "subqi3"
2893 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
2894 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2895 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2900 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2901 (minus:QI (match_dup 0)
2902 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2906 (define_expand "subdf3"
2907 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2908 (minus:DF (match_operand:DF 1 "general_operand" "")
2909 (match_operand:DF 2 "general_operand" "")))]
2910 "TARGET_68881 || TARGET_FPA"
2914 [(set (match_operand:DF 0 "nonimmediate_operand" "=x,y,y")
2915 (minus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF")
2916 (match_operand:DF 2 "general_operand" "xH,dmF,0")))]
2920 if (rtx_equal_p (operands[0], operands[2]))
2921 return \"fprsub%.d %y1,%0\";
2922 if (rtx_equal_p (operands[0], operands[1]))
2923 return \"fpsub%.d %y2,%0\";
2924 if (which_alternative == 0)
2925 return \"fpsub3%.d %w2,%w1,%0\";
2926 return \"fpsub3%.d %x2,%x1,%0\";
2930 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2931 (minus:DF (match_operand:DF 1 "general_operand" "0")
2932 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
2937 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2938 (minus:DF (match_operand:DF 1 "general_operand" "0")
2939 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
2944 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2945 (minus:DF (match_operand:DF 1 "general_operand" "0")
2946 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
2951 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2952 (minus:DF (match_operand:DF 1 "general_operand" "0")
2953 (match_operand:DF 2 "general_operand" "fmG")))]
2957 if (REG_P (operands[2]))
2958 return \"f%&sub%.x %2,%0\";
2959 return \"f%&sub%.d %f2,%0\";
2962 (define_expand "subsf3"
2963 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2964 (minus:SF (match_operand:SF 1 "general_operand" "")
2965 (match_operand:SF 2 "general_operand" "")))]
2966 "TARGET_68881 || TARGET_FPA"
2970 [(set (match_operand:SF 0 "nonimmediate_operand" "=x,y,y")
2971 (minus:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
2972 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
2976 if (rtx_equal_p (operands[0], operands[2]))
2977 return \"fprsub%.s %w1,%0\";
2978 if (rtx_equal_p (operands[0], operands[1]))
2979 return \"fpsub%.s %w2,%0\";
2980 if (which_alternative == 0)
2981 return \"fpsub3%.s %w2,%w1,%0\";
2982 return \"fpsub3%.s %2,%1,%0\";
2986 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2987 (minus:SF (match_operand:SF 1 "general_operand" "0")
2988 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
2993 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2994 (minus:SF (match_operand:SF 1 "general_operand" "0")
2995 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
3000 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3001 (minus:SF (match_operand:SF 1 "general_operand" "0")
3002 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
3007 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3008 (minus:SF (match_operand:SF 1 "general_operand" "0")
3009 (match_operand:SF 2 "general_operand" "fdmF")))]
3013 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3014 return \"f%$sub%.x %2,%0\";
3015 return \"f%$sub%.s %f2,%0\";
3018 ;; multiply instructions
3020 (define_insn "mulhi3"
3021 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
3022 (mult:HI (match_operand:HI 1 "general_operand" "%0")
3023 (match_operand:HI 2 "general_src_operand" "dmSn")))]
3027 #if defined(MOTOROLA) && !defined(CRDS)
3028 return \"muls%.w %2,%0\";
3030 return \"muls %2,%0\";
3034 (define_insn "mulhisi3"
3035 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3036 (mult:SI (sign_extend:SI
3037 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3039 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
3043 #if defined(MOTOROLA) && !defined(CRDS)
3044 return \"muls%.w %2,%0\";
3046 return \"muls %2,%0\";
3051 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3052 (mult:SI (sign_extend:SI
3053 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3054 (match_operand:SI 2 "const_int_operand" "n")))]
3055 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
3058 #if defined(MOTOROLA) && !defined(CRDS)
3059 return \"muls%.w %2,%0\";
3061 return \"muls %2,%0\";
3065 (define_expand "mulsi3"
3066 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3067 (mult:SI (match_operand:SI 1 "general_operand" "")
3068 (match_operand:SI 2 "general_operand" "")))]
3069 "TARGET_68020 || TARGET_5200"
3073 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3074 (mult:SI (match_operand:SI 1 "general_operand" "%0")
3075 (match_operand:SI 2 "general_src_operand" "dmSTK")))]
3081 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3082 (mult:SI (match_operand:SI 1 "general_operand" "%0")
3083 (match_operand:SI 2 "general_operand" "d<Q>")))]
3087 (define_insn "umulhisi3"
3088 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3089 (mult:SI (zero_extend:SI
3090 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3092 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
3096 #if defined(MOTOROLA) && !defined(CRDS)
3097 return \"mulu%.w %2,%0\";
3099 return \"mulu %2,%0\";
3104 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3105 (mult:SI (zero_extend:SI
3106 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3107 (match_operand:SI 2 "const_int_operand" "n")))]
3108 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
3111 #if defined(MOTOROLA) && !defined(CRDS)
3112 return \"mulu%.w %2,%0\";
3114 return \"mulu %2,%0\";
3118 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
3119 ;; proper matching constraint. This is because the matching is between
3120 ;; the high-numbered word of the DImode operand[0] and operand[1].
3121 (define_expand "umulsidi3"
3123 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
3124 (mult:SI (match_operand:SI 1 "register_operand" "")
3125 (match_operand:SI 2 "register_operand" "")))
3126 (set (subreg:SI (match_dup 0) 0)
3127 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3128 (zero_extend:DI (match_dup 2)))
3129 (const_int 32))))])]
3130 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3134 [(set (match_operand:SI 0 "register_operand" "=d")
3135 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3136 (match_operand:SI 2 "nonimmediate_operand" "dm")))
3137 (set (match_operand:SI 3 "register_operand" "=d")
3138 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3139 (zero_extend:DI (match_dup 2)))
3141 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3144 ; Match immediate case. For 2.4 only match things < 2^31.
3145 ; It's tricky with larger values in these patterns since we need to match
3146 ; values between the two parallel multiplies, between a CONST_DOUBLE and
3149 [(set (match_operand:SI 0 "register_operand" "=d")
3150 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3151 (match_operand:SI 2 "const_int_operand" "n")))
3152 (set (match_operand:SI 3 "register_operand" "=d")
3153 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3156 "TARGET_68020 && !TARGET_68060 && !TARGET_5200
3157 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
3160 (define_expand "mulsidi3"
3162 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
3163 (mult:SI (match_operand:SI 1 "register_operand" "")
3164 (match_operand:SI 2 "register_operand" "")))
3165 (set (subreg:SI (match_dup 0) 0)
3166 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3167 (sign_extend:DI (match_dup 2)))
3168 (const_int 32))))])]
3169 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3173 [(set (match_operand:SI 0 "register_operand" "=d")
3174 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3175 (match_operand:SI 2 "nonimmediate_operand" "dm")))
3176 (set (match_operand:SI 3 "register_operand" "=d")
3177 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3178 (sign_extend:DI (match_dup 2)))
3180 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3184 [(set (match_operand:SI 0 "register_operand" "=d")
3185 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3186 (match_operand:SI 2 "const_int_operand" "n")))
3187 (set (match_operand:SI 3 "register_operand" "=d")
3188 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3191 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3194 (define_expand "umulsi3_highpart"
3196 [(set (match_operand:SI 0 "register_operand" "")
3199 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
3200 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
3202 (clobber (match_dup 3))])]
3203 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3206 operands[3] = gen_reg_rtx (SImode);
3208 if (GET_CODE (operands[2]) == CONST_INT)
3210 operands[2] = immed_double_const (INTVAL (operands[2]) & 0xffffffff,
3213 /* We have to adjust the operand order for the matching constraints. */
3214 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
3215 operands[1], operands[2]));
3221 [(set (match_operand:SI 0 "register_operand" "=d")
3224 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3225 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3227 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3228 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3231 (define_insn "const_umulsi3_highpart"
3232 [(set (match_operand:SI 0 "register_operand" "=d")
3235 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
3236 (match_operand:DI 3 "const_uint32_operand" "n"))
3238 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3239 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3242 (define_expand "smulsi3_highpart"
3244 [(set (match_operand:SI 0 "register_operand" "")
3247 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
3248 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
3250 (clobber (match_dup 3))])]
3251 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3254 operands[3] = gen_reg_rtx (SImode);
3255 if (GET_CODE (operands[2]) == CONST_INT)
3257 /* We have to adjust the operand order for the matching constraints. */
3258 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
3259 operands[1], operands[2]));
3265 [(set (match_operand:SI 0 "register_operand" "=d")
3268 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3269 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3271 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3272 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3275 (define_insn "const_smulsi3_highpart"
3276 [(set (match_operand:SI 0 "register_operand" "=d")
3279 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
3280 (match_operand:DI 3 "const_sint32_operand" "n"))
3282 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3283 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3286 (define_expand "muldf3"
3287 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3288 (mult:DF (match_operand:DF 1 "general_operand" "")
3289 (match_operand:DF 2 "general_operand" "")))]
3290 "TARGET_68881 || TARGET_FPA"
3294 [(set (match_operand:DF 0 "nonimmediate_operand" "=x,y")
3295 (mult:DF (match_operand:DF 1 "general_operand" "%xH,y")
3296 (match_operand:DF 2 "general_operand" "xH,rmF")))]
3300 if (rtx_equal_p (operands[1], operands[2]))
3301 return \"fpsqr%.d %y1,%0\";
3302 if (rtx_equal_p (operands[0], operands[1]))
3303 return \"fpmul%.d %y2,%0\";
3304 if (rtx_equal_p (operands[0], operands[2]))
3305 return \"fpmul%.d %y1,%0\";
3306 if (which_alternative == 0)
3307 return \"fpmul3%.d %w2,%w1,%0\";
3308 return \"fpmul3%.d %x2,%x1,%0\";
3312 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3313 (mult:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
3314 (match_operand:DF 1 "general_operand" "0")))]
3319 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3320 (mult:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
3321 (match_operand:DF 1 "general_operand" "0")))]
3326 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3327 (mult:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
3328 (match_operand:DF 1 "general_operand" "0")))]
3333 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3334 (mult:DF (match_operand:DF 1 "general_operand" "%0")
3335 (match_operand:DF 2 "general_operand" "fmG")))]
3339 if (GET_CODE (operands[2]) == CONST_DOUBLE
3340 && floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
3342 int i = floating_exact_log2 (operands[2]);
3343 operands[2] = GEN_INT (i);
3344 return \"fscale%.l %2,%0\";
3346 if (REG_P (operands[2]))
3347 return \"f%&mul%.x %2,%0\";
3348 return \"f%&mul%.d %f2,%0\";
3351 (define_expand "mulsf3"
3352 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3353 (mult:SF (match_operand:SF 1 "general_operand" "")
3354 (match_operand:SF 2 "general_operand" "")))]
3355 "TARGET_68881 || TARGET_FPA"
3359 [(set (match_operand:SF 0 "nonimmediate_operand" "=x,y")
3360 (mult:SF (match_operand:SF 1 "general_operand" "%xH,y")
3361 (match_operand:SF 2 "general_operand" "xH,rmF")))]
3365 if (rtx_equal_p (operands[1], operands[2]))
3366 return \"fpsqr%.s %w1,%0\";
3367 if (rtx_equal_p (operands[0], operands[1]))
3368 return \"fpmul%.s %w2,%0\";
3369 if (rtx_equal_p (operands[0], operands[2]))
3370 return \"fpmul%.s %w1,%0\";
3371 if (which_alternative == 0)
3372 return \"fpmul3%.s %w2,%w1,%0\";
3373 return \"fpmul3%.s %2,%1,%0\";
3377 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3378 (mult:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
3379 (match_operand:SF 1 "general_operand" "0")))]
3383 return (TARGET_68040_ONLY
3384 ? \"fsmul%.l %2,%0\"
3385 : \"fsglmul%.l %2,%0\");
3389 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3390 (mult:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
3391 (match_operand:SF 1 "general_operand" "0")))]
3395 return (TARGET_68040_ONLY
3396 ? \"fsmul%.w %2,%0\"
3397 : \"fsglmul%.w %2,%0\");
3401 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3402 (mult:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
3403 (match_operand:SF 1 "general_operand" "0")))]
3407 return (TARGET_68040_ONLY
3408 ? \"fsmul%.b %2,%0\"
3409 : \"fsglmul%.b %2,%0\");
3413 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3414 (mult:SF (match_operand:SF 1 "general_operand" "%0")
3415 (match_operand:SF 2 "general_operand" "fdmF")))]
3419 #ifdef FSGLMUL_USE_S
3420 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3421 return (TARGET_68040_ONLY
3422 ? \"fsmul%.s %2,%0\"
3423 : \"fsglmul%.s %2,%0\");
3425 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3426 return (TARGET_68040_ONLY
3427 ? \"fsmul%.x %2,%0\"
3428 : \"fsglmul%.x %2,%0\");
3430 return (TARGET_68040_ONLY
3431 ? \"fsmul%.s %f2,%0\"
3432 : \"fsglmul%.s %f2,%0\");
3435 ;; divide instructions
3437 (define_expand "divdf3"
3438 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3439 (div:DF (match_operand:DF 1 "general_operand" "")
3440 (match_operand:DF 2 "general_operand" "")))]
3441 "TARGET_68881 || TARGET_FPA"
3445 [(set (match_operand:DF 0 "nonimmediate_operand" "=x,y,y")
3446 (div:DF (match_operand:DF 1 "general_operand" "xH,y,rmF")
3447 (match_operand:DF 2 "general_operand" "xH,rmF,0")))]
3451 if (rtx_equal_p (operands[0], operands[2]))
3452 return \"fprdiv%.d %y1,%0\";
3453 if (rtx_equal_p (operands[0], operands[1]))
3454 return \"fpdiv%.d %y2,%0\";
3455 if (which_alternative == 0)
3456 return \"fpdiv3%.d %w2,%w1,%0\";
3457 return \"fpdiv3%.d %x2,%x1,%x0\";
3461 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3462 (div:DF (match_operand:DF 1 "general_operand" "0")
3463 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
3468 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3469 (div:DF (match_operand:DF 1 "general_operand" "0")
3470 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
3475 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3476 (div:DF (match_operand:DF 1 "general_operand" "0")
3477 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
3482 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3483 (div:DF (match_operand:DF 1 "general_operand" "0")
3484 (match_operand:DF 2 "general_operand" "fmG")))]
3488 if (REG_P (operands[2]))
3489 return \"f%&div%.x %2,%0\";
3490 return \"f%&div%.d %f2,%0\";
3493 (define_expand "divsf3"
3494 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3495 (div:SF (match_operand:SF 1 "general_operand" "")
3496 (match_operand:SF 2 "general_operand" "")))]
3497 "TARGET_68881 || TARGET_FPA"
3501 [(set (match_operand:SF 0 "nonimmediate_operand" "=x,y,y")
3502 (div:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
3503 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
3507 if (rtx_equal_p (operands[0], operands[1]))
3508 return \"fpdiv%.s %w2,%0\";
3509 if (rtx_equal_p (operands[0], operands[2]))
3510 return \"fprdiv%.s %w1,%0\";
3511 if (which_alternative == 0)
3512 return \"fpdiv3%.s %w2,%w1,%0\";
3513 return \"fpdiv3%.s %2,%1,%0\";
3517 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3518 (div:SF (match_operand:SF 1 "general_operand" "0")
3519 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
3523 return (TARGET_68040_ONLY
3524 ? \"fsdiv%.l %2,%0\"
3525 : \"fsgldiv%.l %2,%0\");
3529 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3530 (div:SF (match_operand:SF 1 "general_operand" "0")
3531 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
3535 return (TARGET_68040_ONLY
3536 ? \"fsdiv%.w %2,%0\"
3537 : \"fsgldiv%.w %2,%0\");
3541 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3542 (div:SF (match_operand:SF 1 "general_operand" "0")
3543 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
3547 return (TARGET_68040_ONLY
3548 ? \"fsdiv%.b %2,%0\"
3549 : \"fsgldiv%.b %2,%0\");
3553 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3554 (div:SF (match_operand:SF 1 "general_operand" "0")
3555 (match_operand:SF 2 "general_operand" "fdmF")))]
3559 #ifdef FSGLDIV_USE_S
3560 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3561 return (TARGET_68040_ONLY
3562 ? \"fsdiv%.s %2,%0\"
3563 : \"fsgldiv%.s %2,%0\");
3565 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3566 return (TARGET_68040_ONLY
3567 ? \"fsdiv%.x %2,%0\"
3568 : \"fsgldiv%.x %2,%0\");
3570 return (TARGET_68040_ONLY
3571 ? \"fsdiv%.s %f2,%0\"
3572 : \"fsgldiv%.s %f2,%0\");
3575 ;; Remainder instructions.
3577 (define_insn "divmodsi4"
3578 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3579 (div:SI (match_operand:SI 1 "general_operand" "0")
3580 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3581 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3582 (mod:SI (match_dup 1) (match_dup 2)))]
3583 "TARGET_68020 && !TARGET_5200"
3586 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3587 return \"divs%.l %2,%0\";
3589 return \"divsl%.l %2,%3:%0\";
3592 (define_insn "udivmodsi4"
3593 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3594 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3595 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3596 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3597 (umod:SI (match_dup 1) (match_dup 2)))]
3598 "TARGET_68020 && !TARGET_5200"
3601 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3602 return \"divu%.l %2,%0\";
3604 return \"divul%.l %2,%3:%0\";
3607 (define_insn "divmodhi4"
3608 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
3609 (div:HI (match_operand:HI 1 "general_operand" "0")
3610 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3611 (set (match_operand:HI 3 "nonimmediate_operand" "=d")
3612 (mod:HI (match_dup 1) (match_dup 2)))]
3617 output_asm_insn (\"ext%.l %0\;divs%.w %2,%0\", operands);
3619 output_asm_insn (\"extl %0\;divs %2,%0\", operands);
3621 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3624 return \"move%.l %0,%3\;swap %3\";
3630 (define_insn "udivmodhi4"
3631 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
3632 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3633 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3634 (set (match_operand:HI 3 "nonimmediate_operand" "=d")
3635 (umod:HI (match_dup 1) (match_dup 2)))]
3640 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu%.w %2,%0\", operands);
3642 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu %2,%0\", operands);
3644 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3647 return \"move%.l %0,%3\;swap %3\";
3653 ;; logical-and instructions
3655 ;; "anddi3" is mainly here to help combine().
3656 (define_insn "anddi3"
3657 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3658 (and:DI (match_operand:DI 1 "general_operand" "%0,0")
3659 (match_operand:DI 2 "general_operand" "dn,don")))]
3664 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3665 if (CONSTANT_P (operands[2]))
3669 split_double (operands[2], &hi, &lo);
3671 switch (INTVAL (hi))
3674 output_asm_insn (\"clr%.l %0\", operands);
3682 xoperands[0] = operands[0];
3684 output_asm_insn (output_andsi3 (xoperands), xoperands);
3687 if (GET_CODE (operands[0]) == REG)
3688 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3690 operands[0] = adjust_address (operands[0], SImode, 4);
3691 switch (INTVAL (lo))
3694 output_asm_insn (\"clr%.l %0\", operands);
3702 xoperands[0] = operands[0];
3704 output_asm_insn (output_andsi3 (xoperands), xoperands);
3709 if (GET_CODE (operands[0]) != REG)
3711 operands[1] = adjust_address (operands[0], SImode, 4);
3712 return \"and%.l %2,%0\;and%.l %R2,%1\";
3714 if (GET_CODE (operands[2]) != REG)
3716 operands[1] = adjust_address (operands[2], SImode, 4);
3717 return \"and%.l %2,%0\;and%.l %1,%R0\";
3719 return \"and%.l %2,%0\;and%.l %R2,%R0\";
3722 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3723 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3724 ;; can't allocate pseudos into it.
3726 (define_expand "andsi3"
3727 [(set (match_operand:SI 0 "not_sp_operand" "")
3728 (and:SI (match_operand:SI 1 "general_operand" "")
3729 (match_operand:SI 2 "general_src_operand" "")))]
3733 (define_insn "andsi3_internal"
3734 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3735 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3736 (match_operand:SI 2 "general_src_operand" "dKT,dmSM")))]
3740 return output_andsi3 (operands);
3743 (define_insn "andsi3_5200"
3744 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3745 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3746 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3750 (define_insn "andhi3"
3751 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
3752 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3753 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3758 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3759 (and:HI (match_dup 0)
3760 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3765 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3766 (and:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3771 (define_insn "andqi3"
3772 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
3773 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3774 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3779 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3780 (and:QI (match_dup 0)
3781 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3786 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3787 (and:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3792 ;; inclusive-or instructions
3794 (define_insn "iordi_zext"
3795 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3796 (ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn"))
3797 (match_operand:DI 2 "general_operand" "0,0")))]
3804 if (GET_CODE (operands[0]) == REG)
3805 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3807 operands[0] = adjust_address (operands[0], SImode, 4);
3808 if (GET_MODE (operands[1]) == SImode)
3809 return \"or%.l %1,%0\";
3810 byte_mode = (GET_MODE (operands[1]) == QImode);
3811 if (GET_CODE (operands[0]) == MEM)
3812 operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
3815 return \"or%.b %1,%0\";
3817 return \"or%.w %1,%0\";
3820 ;; "iordi3" is mainly here to help combine().
3821 (define_insn "iordi3"
3822 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3823 (ior:DI (match_operand:DI 1 "general_operand" "%0,0")
3824 (match_operand:DI 2 "general_operand" "dn,don")))]
3829 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3830 if (CONSTANT_P (operands[2]))
3834 split_double (operands[2], &hi, &lo);
3836 switch (INTVAL (hi))
3841 /* FIXME : a scratch register would be welcome here if operand[0]
3842 is not a register */
3843 output_asm_insn (\"move%.l %#-1,%0\", operands);
3849 xoperands[0] = operands[0];
3851 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3854 if (GET_CODE (operands[0]) == REG)
3855 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3857 operands[0] = adjust_address (operands[0], SImode, 4);
3858 switch (INTVAL (lo))
3863 /* FIXME : a scratch register would be welcome here if operand[0]
3864 is not a register */
3865 output_asm_insn (\"move%.l %#-1,%R0\", operands);
3871 xoperands[0] = operands[0];
3873 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3878 if (GET_CODE (operands[0]) != REG)
3880 operands[1] = adjust_address (operands[0], SImode, 4);
3881 return \"or%.l %2,%0\;or%.l %R2,%1\";
3883 if (GET_CODE (operands[2]) != REG)
3885 operands[1] = adjust_address (operands[2], SImode, 4);
3886 return \"or%.l %2,%0\;or%.l %1,%R0\";
3888 return \"or%.l %2,%0\;or%.l %R2,%R0\";
3891 (define_expand "iorsi3"
3892 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3893 (ior:SI (match_operand:SI 1 "general_operand" "")
3894 (match_operand:SI 2 "general_src_operand" "")))]
3898 (define_insn "iorsi3_internal"
3899 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
3900 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3901 (match_operand:SI 2 "general_src_operand" "dKT,dmSMT")))]
3905 return output_iorsi3 (operands);
3908 (define_insn "iorsi3_5200"
3909 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
3910 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3911 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3915 (define_insn "iorhi3"
3916 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
3917 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3918 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3923 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3924 (ior:HI (match_dup 0)
3925 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3930 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3931 (ior:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3936 (define_insn "iorqi3"
3937 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
3938 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3939 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3944 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3945 (ior:QI (match_dup 0)
3946 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3951 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3952 (ior:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3957 ;; On all 68k models, this makes faster code in a special case.
3958 ;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
3960 (define_insn "iorsi_zexthi_ashl16"
3961 [(set (match_operand:SI 0 "nonimmediate_operand" "=&d")
3962 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "rmn"))
3963 (ashift:SI (match_operand:SI 2 "general_operand" "or")
3969 if (GET_CODE (operands[2]) != REG)
3970 operands[2] = adjust_address (operands[2], HImode, 2);
3971 if (GET_CODE (operands[2]) != REG
3972 || REGNO (operands[2]) != REGNO (operands[0]))
3973 output_asm_insn (\"move%.w %2,%0\", operands);
3974 return \"swap %0\;mov%.w %1,%0\";
3977 (define_insn "iorsi_zext"
3978 [(set (match_operand:SI 0 "nonimmediate_operand" "=o,d")
3979 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3980 (match_operand:SI 2 "general_operand" "0,0")))]
3987 byte_mode = (GET_MODE (operands[1]) == QImode);
3988 if (GET_CODE (operands[0]) == MEM)
3989 operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
3992 return \"or%.b %1,%0\";
3994 return \"or%.w %1,%0\";
3999 ;; "xordi3" is mainly here to help combine().
4000 (define_insn "xordi3"
4001 [(set (match_operand:DI 0 "nonimmediate_operand" "=od")
4002 (xor:DI (match_operand:DI 1 "general_operand" "%0")
4003 (match_operand:DI 2 "general_operand" "dn")))]
4008 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
4010 if (CONSTANT_P (operands[2]))
4014 split_double (operands[2], &hi, &lo);
4016 switch (INTVAL (hi))
4021 output_asm_insn (\"not%.l %0\", operands);
4024 /* FIXME : a scratch register would be welcome here if
4025 -128 <= INTVAL (hi) < -1 */
4029 xoperands[0] = operands[0];
4031 output_asm_insn (output_xorsi3 (xoperands), xoperands);
4034 if (GET_CODE (operands[0]) == REG)
4035 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4037 operands[0] = adjust_address (operands[0], SImode, 4);
4038 switch (INTVAL (lo))
4043 output_asm_insn (\"not%.l %0\", operands);
4046 /* FIXME : a scratch register would be welcome here if
4047 -128 <= INTVAL (lo) < -1 */
4049 /* FIXME : this should be merged with xorsi3 */
4053 xoperands[0] = operands[0];
4055 output_asm_insn (output_xorsi3 (xoperands), xoperands);
4060 if (GET_CODE (operands[0]) != REG)
4062 operands[1] = adjust_address (operands[0], SImode, 4);
4063 return \"eor%.l %2,%0\;eor%.l %R2,%1\";
4065 if (GET_CODE (operands[2]) != REG)
4067 operands[1] = adjust_address (operands[2], SImode, 4);
4068 return \"eor%.l %2,%0\;eor%.l %1,%R0\";
4070 return \"eor%.l %2,%0\;eor%.l %R2,%R0\";
4073 (define_expand "xorsi3"
4074 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4075 (xor:SI (match_operand:SI 1 "general_operand" "")
4076 (match_operand:SI 2 "general_operand" "")))]
4080 (define_insn "xorsi3_internal"
4081 [(set (match_operand:SI 0 "nonimmediate_operand" "=do,m")
4082 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
4083 (match_operand:SI 2 "general_operand" "di,dKT")))]
4088 return output_xorsi3 (operands);
4091 (define_insn "xorsi3_5200"
4092 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm,d")
4093 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
4094 (match_operand:SI 2 "general_operand" "d,Ks")))]
4098 (define_insn "xorhi3"
4099 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
4100 (xor:HI (match_operand:HI 1 "general_operand" "%0")
4101 (match_operand:HI 2 "general_operand" "dn")))]
4106 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
4107 (xor:HI (match_dup 0)
4108 (match_operand:HI 1 "general_operand" "dn")))]
4113 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
4114 (xor:HI (match_operand:HI 1 "general_operand" "dn")
4119 (define_insn "xorqi3"
4120 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
4121 (xor:QI (match_operand:QI 1 "general_operand" "%0")
4122 (match_operand:QI 2 "general_operand" "dn")))]
4127 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
4128 (xor:QI (match_dup 0)
4129 (match_operand:QI 1 "general_operand" "dn")))]
4134 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
4135 (xor:QI (match_operand:QI 1 "general_operand" "dn")
4140 ;; negation instructions
4142 (define_expand "negdi2"
4143 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4144 (neg:DI (match_operand:DI 1 "general_operand" "")))]
4149 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
4151 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
4155 (define_insn "negdi2_internal"
4156 [(set (match_operand:DI 0 "nonimmediate_operand" "=<,do,!*a")
4157 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
4161 if (which_alternative == 0)
4162 return \"neg%.l %0\;negx%.l %0\";
4163 if (GET_CODE (operands[0]) == REG)
4164 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4166 operands[1] = adjust_address (operands[0], SImode, 4);
4167 if (ADDRESS_REG_P (operands[0]))
4168 return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
4170 return \"neg%.l %1\;negx%.l %0\";
4173 (define_insn "negdi2_5200"
4174 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
4175 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
4179 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4180 return \"neg%.l %1\;negx%.l %0\";
4183 (define_expand "negsi2"
4184 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4185 (neg:SI (match_operand:SI 1 "general_operand" "")))]
4190 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
4192 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
4196 (define_insn "negsi2_internal"
4197 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
4198 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4202 (define_insn "negsi2_5200"
4203 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
4204 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4208 (define_insn "neghi2"
4209 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
4210 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
4215 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
4216 (neg:HI (match_dup 0)))]
4220 (define_insn "negqi2"
4221 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
4222 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
4227 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
4228 (neg:QI (match_dup 0)))]
4232 ;; If using software floating point, just flip the sign bit.
4234 (define_expand "negsf2"
4235 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4236 (neg:SF (match_operand:SF 1 "general_operand" "")))]
4240 if (!TARGET_FPA && !TARGET_68881)
4245 target = operand_subword_force (operands[0], 0, SFmode);
4246 result = expand_binop (SImode, xor_optab,
4247 operand_subword_force (operands[1], 0, SFmode),
4248 GEN_INT (0x80000000), target, 0, OPTAB_WIDEN);
4252 if (result != target)
4253 emit_move_insn (result, target);
4255 /* Make a place for REG_EQUAL. */
4256 emit_move_insn (operands[0], operands[0]);
4262 [(set (match_operand:SF 0 "nonimmediate_operand" "=x,y")
4263 (neg:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4268 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,d")
4269 (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))]
4273 if (DATA_REG_P (operands[0]))
4275 operands[1] = GEN_INT (31);
4276 return \"bchg %1,%0\";
4278 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4279 return \"f%$neg%.x %1,%0\";
4280 return \"f%$neg%.s %f1,%0\";
4283 (define_expand "negdf2"
4284 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4285 (neg:DF (match_operand:DF 1 "general_operand" "")))]
4289 if (!TARGET_FPA && !TARGET_68881)
4296 target = operand_subword (operands[0], 0, 1, DFmode);
4297 result = expand_binop (SImode, xor_optab,
4298 operand_subword_force (operands[1], 0, DFmode),
4299 GEN_INT (0x80000000), target, 0, OPTAB_WIDEN);
4303 if (result != target)
4304 emit_move_insn (result, target);
4306 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4307 operand_subword_force (operands[1], 1, DFmode));
4309 insns = get_insns ();
4312 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4318 [(set (match_operand:DF 0 "nonimmediate_operand" "=x,y")
4319 (neg:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4324 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,d")
4325 (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
4329 if (DATA_REG_P (operands[0]))
4331 operands[1] = GEN_INT (31);
4332 return \"bchg %1,%0\";
4334 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4335 return \"f%&neg%.x %1,%0\";
4336 return \"f%&neg%.d %f1,%0\";
4339 ;; Sqrt instruction for the 68881
4341 (define_insn "sqrtsf2"
4342 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
4343 (sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
4347 if (FP_REG_P (operands[1]))
4348 return \"f%$sqrt%.x %1,%0\";
4350 return \"f%$sqrt%.s %1,%0\";
4353 (define_insn "sqrtdf2"
4354 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
4355 (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
4359 if (FP_REG_P (operands[1]))
4360 return \"f%&sqrt%.x %1,%0\";
4362 return \"f%&sqrt%.d %1,%0\";
4365 ;; Absolute value instructions
4366 ;; If using software floating point, just zero the sign bit.
4368 (define_expand "abssf2"
4369 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4370 (abs:SF (match_operand:SF 1 "general_operand" "")))]
4374 if (!TARGET_FPA && !TARGET_68881)
4379 target = operand_subword_force (operands[0], 0, SFmode);
4380 result = expand_binop (SImode, and_optab,
4381 operand_subword_force (operands[1], 0, SFmode),
4382 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
4386 if (result != target)
4387 emit_move_insn (result, target);
4389 /* Make a place for REG_EQUAL. */
4390 emit_move_insn (operands[0], operands[0]);
4396 [(set (match_operand:SF 0 "nonimmediate_operand" "=x,y")
4397 (abs:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4402 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
4403 (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
4407 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4408 return \"f%$abs%.x %1,%0\";
4409 return \"f%$abs%.s %f1,%0\";
4412 (define_expand "absdf2"
4413 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4414 (abs:DF (match_operand:DF 1 "general_operand" "")))]
4418 if (!TARGET_FPA && !TARGET_68881)
4425 target = operand_subword (operands[0], 0, 1, DFmode);
4426 result = expand_binop (SImode, and_optab,
4427 operand_subword_force (operands[1], 0, DFmode),
4428 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
4432 if (result != target)
4433 emit_move_insn (result, target);
4435 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4436 operand_subword_force (operands[1], 1, DFmode));
4438 insns = get_insns ();
4441 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4447 [(set (match_operand:DF 0 "nonimmediate_operand" "=x,y")
4448 (abs:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4453 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
4454 (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
4458 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4459 return \"f%&abs%.x %1,%0\";
4460 return \"f%&abs%.d %f1,%0\";
4463 ;; one complement instructions
4465 ;; "one_cmpldi2" is mainly here to help combine().
4466 (define_insn "one_cmpldi2"
4467 [(set (match_operand:DI 0 "nonimmediate_operand" "=dm")
4468 (not:DI (match_operand:DI 1 "general_operand" "0")))]
4473 if (GET_CODE (operands[0]) == REG)
4474 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4475 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
4476 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4477 operands[1] = operands[0];
4479 operands[1] = adjust_address (operands[0], SImode, 4);
4480 return \"not%.l %1\;not%.l %0\";
4483 (define_expand "one_cmplsi2"
4484 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4485 (not:SI (match_operand:SI 1 "general_operand" "")))]
4490 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
4492 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
4496 (define_insn "one_cmplsi2_internal"
4497 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
4498 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4502 (define_insn "one_cmplsi2_5200"
4503 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
4504 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4508 (define_insn "one_cmplhi2"
4509 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
4510 (not:HI (match_operand:HI 1 "general_operand" "0")))]
4515 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
4516 (not:HI (match_dup 0)))]
4520 (define_insn "one_cmplqi2"
4521 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
4522 (not:QI (match_operand:QI 1 "general_operand" "0")))]
4527 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
4528 (not:QI (match_dup 0)))]
4532 ;; arithmetic shift instructions
4533 ;; We don't need the shift memory by 1 bit instruction
4535 (define_insn "ashldi_extsi"
4536 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
4538 (match_operator:DI 2 "extend_operator"
4539 [(match_operand:SI 1 "general_operand" "rm")])
4545 if (GET_CODE (operands[0]) == REG)
4546 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4548 operands[2] = adjust_address (operands[0], SImode, 4);
4549 if (ADDRESS_REG_P (operands[0]))
4550 return \"move%.l %1,%0\;sub%.l %2,%2\";
4552 return \"move%.l %1,%0\;clr%.l %2\";
4555 (define_insn "ashldi_sexthi"
4556 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,a*d")
4557 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
4559 (clobber (match_scratch:SI 2 "=a,X"))]
4564 if (GET_CODE (operands[0]) == MEM)
4566 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4567 return \"clr%.l %0\;move%.w %1,%2\;move%.l %2,%0\";
4568 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4569 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %0\";
4572 operands[3] = adjust_address (operands[0], SImode, 4);
4573 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %3\";
4576 else if (DATA_REG_P (operands[0]))
4577 return \"move%.w %1,%0\;ext%.l %0\;clr%.l %R0\";
4579 return \"move%.w %1,%0\;sub%.l %R0,%R0\";
4582 (define_insn "ashldi_const32"
4583 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
4584 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
4590 if (GET_CODE (operands[1]) == REG)
4591 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4593 operands[3] = adjust_address (operands[1], SImode, 4);
4594 if (GET_CODE (operands[0]) == REG)
4595 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4596 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4597 return \"clr%.l %0\;move%.l %3,%0\";
4598 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4599 return \"move%.l %3,%0\;clr%.l %0\";
4601 operands[2] = adjust_address (operands[0], SImode, 4);
4602 if (ADDRESS_REG_P (operands[2]))
4603 return \"move%.l %3,%0\;sub%.l %2,%2\";
4605 return \"move%.l %3,%0\;clr%.l %2\";
4608 ;; The predicate below must be general_operand, because ashldi3 allows that
4609 (define_insn "ashldi_const"
4610 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
4611 (ashift:DI (match_operand:DI 1 "general_operand" "0")
4612 (match_operand 2 "const_int_operand" "n")))]
4614 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4615 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4616 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4619 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4620 if (INTVAL (operands[2]) == 1)
4621 return \"add%.l %1,%1\;addx%.l %0,%0\";
4622 else if (INTVAL (operands[2]) == 8)
4623 return \"rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1\";
4624 else if (INTVAL (operands[2]) == 16)
4625 return \"swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1\";
4626 else if (INTVAL (operands[2]) == 48)
4627 return \"mov%.l %1,%0\;swap %0\;clr%.l %1\;clr%.w %0\";
4628 else if (INTVAL (operands[2]) == 2)
4629 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4630 else if (INTVAL (operands[2]) == 3)
4631 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4632 else /* 32 < INTVAL (operands[2]) <= 63 */
4634 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4635 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asl%.l %2,%1\" :
4636 \"moveq %2,%0\;asl%.l %0,%1\", operands);
4637 return \"mov%.l %1,%0\;moveq %#0,%1\";
4641 (define_expand "ashldi3"
4642 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4643 (ashift:DI (match_operand:DI 1 "general_operand" "")
4644 (match_operand 2 "const_int_operand" "")))]
4648 /* ??? This is a named pattern like this is not allowed to FAIL based
4650 if (GET_CODE (operands[2]) != CONST_INT
4651 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4652 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4653 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4657 ;; On most 68k models, this makes faster code in a special case.
4659 (define_insn "ashlsi_16"
4660 [(set (match_operand:SI 0 "register_operand" "=d")
4661 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4667 return \"swap %0\;clr%.w %0\";
4670 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
4671 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
4673 ;; On the 68000, this makes faster code in a special case.
4675 (define_insn "ashlsi_17_24"
4676 [(set (match_operand:SI 0 "register_operand" "=d")
4677 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4678 (match_operand:SI 2 "const_int_operand" "n")))]
4679 "(! TARGET_68020 && !TARGET_5200
4680 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4685 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4686 return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\";
4689 (define_insn "ashlsi3"
4690 [(set (match_operand:SI 0 "register_operand" "=d")
4691 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4692 (match_operand:SI 2 "general_operand" "dI")))]
4696 if (operands[2] == const1_rtx)
4698 cc_status.flags = CC_NO_OVERFLOW;
4699 return \"add%.l %0,%0\";
4701 return \"lsl%.l %2,%0\";
4704 (define_insn "ashlhi3"
4705 [(set (match_operand:HI 0 "register_operand" "=d")
4706 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4707 (match_operand:HI 2 "general_operand" "dI")))]
4712 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4713 (ashift:HI (match_dup 0)
4714 (match_operand:HI 1 "general_operand" "dI")))]
4718 (define_insn "ashlqi3"
4719 [(set (match_operand:QI 0 "register_operand" "=d")
4720 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4721 (match_operand:QI 2 "general_operand" "dI")))]
4726 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4727 (ashift:QI (match_dup 0)
4728 (match_operand:QI 1 "general_operand" "dI")))]
4732 ;; On most 68k models, this makes faster code in a special case.
4734 (define_insn "ashrsi_16"
4735 [(set (match_operand:SI 0 "register_operand" "=d")
4736 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4739 "swap %0\;ext%.l %0")
4741 ;; On the 68000, this makes faster code in a special case.
4744 [(set (match_operand:SI 0 "register_operand" "=d")
4745 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4746 (match_operand:SI 2 "const_int_operand" "n")))]
4747 "(! TARGET_68020 && !TARGET_5200
4748 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4751 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4752 return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
4755 (define_insn "subreghi1ashrdi_const32"
4756 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
4757 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4758 (const_int 32)) 6))]
4762 if (GET_CODE (operands[1]) != REG)
4763 operands[1] = adjust_address (operands[1], HImode, 2);
4764 return \"move%.w %1,%0\";
4767 (define_insn "subregsi1ashrdi_const32"
4768 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4769 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4770 (const_int 32)) 4))]
4774 return \"move%.l %1,%0\";
4777 (define_insn "ashrdi_const32"
4778 [(set (match_operand:DI 0 "register_operand" "=d")
4779 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4785 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4787 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
4789 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
4792 (define_insn "ashrdi_const32_mem"
4793 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,<")
4794 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro")
4796 (clobber (match_scratch:SI 2 "=d,d"))]
4801 if (which_alternative == 1)
4802 operands[3] = operands[0];
4804 operands[3] = adjust_address (operands[0], SImode, 4);
4806 return \"move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0\";
4808 return \"move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\";
4811 ;; The predicate below must be general_operand, because ashrdi3 allows that
4812 (define_insn "ashrdi_const"
4813 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
4814 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
4815 (match_operand 2 "const_int_operand" "n")))]
4817 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4818 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4819 || INTVAL (operands[2]) == 31
4820 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4823 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4824 if (INTVAL (operands[2]) == 63)
4825 return \"add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1\";
4827 if (INTVAL (operands[2]) == 1)
4828 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
4829 else if (INTVAL (operands[2]) == 8)
4830 return \"move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1\";
4831 else if (INTVAL (operands[2]) == 16)
4832 return \"move%.w %0,%1\;swap %0\;ext%.l %0\;swap %1\";
4833 else if (INTVAL (operands[2]) == 48)
4834 return \"swap %0\;ext%.l %0\;move%.l %0,%1\;smi %0\;ext%.w %0\";
4835 else if (INTVAL (operands[2]) == 31)
4836 return \"add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0\";
4837 else if (INTVAL (operands[2]) == 2)
4838 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4839 else if (INTVAL (operands[2]) == 3)
4840 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4841 else /* 32 < INTVAL (operands[2]) <= 63 */
4843 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4844 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asr%.l %2,%0\" :
4845 \"moveq %2,%1\;asr%.l %1,%0\", operands);
4846 output_asm_insn (\"mov%.l %0,%1\;smi %0\", operands);
4847 return INTVAL (operands[2]) >= 15 ? \"ext%.w %d0\" :
4848 TARGET_68020 ? \"extb%.l %0\" : \"ext%.w %0\;ext%.l %0\";
4852 (define_expand "ashrdi3"
4853 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4854 (ashiftrt:DI (match_operand:DI 1 "general_operand" "")
4855 (match_operand 2 "const_int_operand" "")))]
4859 /* ??? This is a named pattern like this is not allowed to FAIL based
4861 if (GET_CODE (operands[2]) != CONST_INT
4862 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4863 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4864 && (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63)))
4868 ;; On all 68k models, this makes faster code in a special case.
4870 (define_insn "ashrsi_31"
4871 [(set (match_operand:SI 0 "register_operand" "=d")
4872 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4877 return \"add%.l %0,%0\;subx%.l %0,%0\";
4880 (define_insn "ashrsi3"
4881 [(set (match_operand:SI 0 "register_operand" "=d")
4882 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4883 (match_operand:SI 2 "general_operand" "dI")))]
4887 (define_insn "ashrhi3"
4888 [(set (match_operand:HI 0 "register_operand" "=d")
4889 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4890 (match_operand:HI 2 "general_operand" "dI")))]
4895 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4896 (ashiftrt:HI (match_dup 0)
4897 (match_operand:HI 1 "general_operand" "dI")))]
4901 (define_insn "ashrqi3"
4902 [(set (match_operand:QI 0 "register_operand" "=d")
4903 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4904 (match_operand:QI 2 "general_operand" "dI")))]
4909 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4910 (ashiftrt:QI (match_dup 0)
4911 (match_operand:QI 1 "general_operand" "dI")))]
4915 ;; logical shift instructions
4917 ;; commented out because of reload problems in 950612-1.c
4920 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4921 ;; (const_int 32)) 4))
4922 ;; (set (match_operand:SI 1 "nonimmediate_operand" "=dm")
4923 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
4924 ;; (const_int 32)) 4))]
4928 ;; return \"move%.l %0,%1\";
4933 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4934 ;; (const_int 32)) 0))
4935 ;; (set (match_operand:DI 1 "nonimmediate_operand" "=do")
4936 ;; (lshiftrt:DI (match_dup 0)
4937 ;; (const_int 32)))]
4941 ;; if (GET_CODE (operands[1]) == REG)
4942 ;; operands[2] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4944 ;; operands[2] = adjust_address (operands[1], SImode, 4);
4945 ;; return \"move%.l %0,%2\;clr%.l %1\";
4948 (define_insn "subreg1lshrdi_const32"
4949 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4950 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4951 (const_int 32)) 4))]
4955 return \"move%.l %1,%0\";
4958 (define_insn "lshrdi_const32"
4959 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro,<,>")
4960 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
4966 if (which_alternative == 1)
4967 return \"move%.l %1,%0\;clr%.l %0\";
4968 if (which_alternative == 2)
4969 return \"clr%.l %0\;move%.l %1,%0\";
4970 if (GET_CODE (operands[0]) == REG)
4971 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4973 operands[2] = adjust_address (operands[0], SImode, 4);
4974 if (GET_CODE (operands[1]) == REG)
4975 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4977 operands[3] = adjust_address (operands[1], SImode, 4);
4978 if (ADDRESS_REG_P (operands[0]))
4979 return \"move%.l %1,%2\;sub%.l %0,%0\";
4981 return \"move%.l %1,%2\;clr%.l %0\";
4984 ;; The predicate below must be general_operand, because lshrdi3 allows that
4985 (define_insn "lshrdi_const"
4986 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
4987 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
4988 (match_operand 2 "const_int_operand" "n")))]
4990 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4991 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4992 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4995 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4996 if (INTVAL (operands[2]) == 63)
4997 return \"add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1\";
4999 if (INTVAL (operands[2]) == 1)
5000 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
5001 else if (INTVAL (operands[2]) == 8)
5002 return \"move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1\";
5003 else if (INTVAL (operands[2]) == 16)
5004 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0\";
5005 else if (INTVAL (operands[2]) == 48)
5006 return \"move%.l %0,%1\;clr%.w %1\;clr%.l %0\;swap %1\";
5007 else if (INTVAL (operands[2]) == 2)
5008 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
5009 else if (INTVAL (operands[2]) == 3)
5010 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
5011 else /* 32 < INTVAL (operands[2]) <= 63 */
5013 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
5014 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"lsr%.l %2,%0\" :
5015 \"moveq %2,%1\;lsr%.l %1,%0\", operands);
5016 return \"mov%.l %0,%1\;moveq %#0,%0\";
5020 (define_expand "lshrdi3"
5021 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5022 (lshiftrt:DI (match_operand:DI 1 "general_operand" "")
5023 (match_operand 2 "const_int_operand" "")))]
5027 /* ??? This is a named pattern like this is not allowed to FAIL based
5029 if (GET_CODE (operands[2]) != CONST_INT
5030 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
5031 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
5032 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
5036 ;; On all 68k models, this makes faster code in a special case.
5038 (define_insn "lshrsi_31"
5039 [(set (match_operand:SI 0 "register_operand" "=d")
5040 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5045 return \"add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0\";
5048 ;; On most 68k models, this makes faster code in a special case.
5050 (define_insn "lshrsi_16"
5051 [(set (match_operand:SI 0 "register_operand" "=d")
5052 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5058 return \"clr%.w %0\;swap %0\";
5061 ;; On the 68000, this makes faster code in a special case.
5063 (define_insn "lshrsi_17_24"
5064 [(set (match_operand:SI 0 "register_operand" "=d")
5065 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5066 (match_operand:SI 2 "const_int_operand" "n")))]
5067 "(! TARGET_68020 && !TARGET_5200
5068 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
5071 /* I think lsr%.w sets the CC properly. */
5072 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
5073 return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\";
5076 (define_insn "lshrsi3"
5077 [(set (match_operand:SI 0 "register_operand" "=d")
5078 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5079 (match_operand:SI 2 "general_operand" "dI")))]
5083 (define_insn "lshrhi3"
5084 [(set (match_operand:HI 0 "register_operand" "=d")
5085 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
5086 (match_operand:HI 2 "general_operand" "dI")))]
5091 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5092 (lshiftrt:HI (match_dup 0)
5093 (match_operand:HI 1 "general_operand" "dI")))]
5097 (define_insn "lshrqi3"
5098 [(set (match_operand:QI 0 "register_operand" "=d")
5099 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
5100 (match_operand:QI 2 "general_operand" "dI")))]
5105 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5106 (lshiftrt:QI (match_dup 0)
5107 (match_operand:QI 1 "general_operand" "dI")))]
5111 ;; rotate instructions
5113 (define_insn "rotlsi3"
5114 [(set (match_operand:SI 0 "register_operand" "=d")
5115 (rotate:SI (match_operand:SI 1 "register_operand" "0")
5116 (match_operand:SI 2 "general_operand" "dINO")))]
5120 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
5122 else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
5124 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
5125 return \"ror%.l %2,%0\";
5128 return \"rol%.l %2,%0\";
5131 (define_insn "rotlhi3"
5132 [(set (match_operand:HI 0 "register_operand" "=d")
5133 (rotate:HI (match_operand:HI 1 "register_operand" "0")
5134 (match_operand:HI 2 "general_operand" "dIP")))]
5138 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
5140 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
5141 return \"ror%.w %2,%0\";
5144 return \"rol%.w %2,%0\";
5148 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5149 (rotate:HI (match_dup 0)
5150 (match_operand:HI 1 "general_operand" "dIP")))]
5154 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
5156 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
5157 return \"ror%.w %2,%0\";
5160 return \"rol%.w %2,%0\";
5163 (define_insn "rotlqi3"
5164 [(set (match_operand:QI 0 "register_operand" "=d")
5165 (rotate:QI (match_operand:QI 1 "register_operand" "0")
5166 (match_operand:QI 2 "general_operand" "dI")))]
5170 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
5172 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
5173 return \"ror%.b %2,%0\";
5176 return \"rol%.b %2,%0\";
5180 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5181 (rotate:QI (match_dup 0)
5182 (match_operand:QI 1 "general_operand" "dI")))]
5186 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
5188 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
5189 return \"ror%.b %2,%0\";
5192 return \"rol%.b %2,%0\";
5195 (define_insn "rotrsi3"
5196 [(set (match_operand:SI 0 "register_operand" "=d")
5197 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
5198 (match_operand:SI 2 "general_operand" "dI")))]
5202 (define_insn "rotrhi3"
5203 [(set (match_operand:HI 0 "register_operand" "=d")
5204 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
5205 (match_operand:HI 2 "general_operand" "dI")))]
5210 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5211 (rotatert:HI (match_dup 0)
5212 (match_operand:HI 1 "general_operand" "dI")))]
5216 (define_insn "rotrqi3"
5217 [(set (match_operand:QI 0 "register_operand" "=d")
5218 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
5219 (match_operand:QI 2 "general_operand" "dI")))]
5224 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5225 (rotatert:QI (match_dup 0)
5226 (match_operand:QI 1 "general_operand" "dI")))]
5231 ;; Bit set/clear in memory byte.
5233 ;; set bit, bit number is int
5234 (define_insn "bsetmemqi"
5235 [(set (match_operand:QI 0 "memory_operand" "+m")
5236 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5237 (match_operand:SI 1 "general_operand" "d")) 3)
5243 return \"bset %1,%0\";
5246 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
5248 [(set (match_operand:QI 0 "memory_operand" "+m")
5249 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5250 (match_operator:SI 2 "extend_operator"
5251 [(match_operand 1 "general_operand" "d")])) 3)
5257 return \"bset %1,%0\";
5260 ;; clear bit, bit number is int
5261 (define_insn "bclrmemqi"
5262 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5264 (minus:SI (const_int 7)
5265 (match_operand:SI 1 "general_operand" "d")))
5271 return \"bclr %1,%0\";
5274 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
5276 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5278 (minus:SI (const_int 7)
5279 (match_operator:SI 2 "extend_operator"
5280 [(match_operand 1 "general_operand" "d")])))
5286 return \"bclr %1,%0\";
5289 ;; Special cases of bit-field insns which we should
5290 ;; recognize in preference to the general case.
5291 ;; These handle aligned 8-bit and 16-bit fields,
5292 ;; which can usually be done with move instructions.
5295 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5296 ; alignment of structure members is specified.
5298 ; The move is allowed to be odd byte aligned, because that's still faster
5299 ; than an odd byte aligned bit field instruction.
5302 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5304 (match_operand:SI 1 "const_int_operand" "n"))
5305 (match_operand:SI 2 "general_src_operand" "rmSi"))]
5306 "TARGET_68020 && TARGET_BITFIELD
5307 && (INTVAL (operands[1]) % 8) == 0
5308 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
5312 = adjust_address (operands[0], SImode, INTVAL (operands[1]) / 8);
5314 return \"move%.l %2,%0\";
5318 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
5319 (match_operand:SI 1 "const_int_operand" "n")
5320 (match_operand:SI 2 "const_int_operand" "n"))
5321 (match_operand:SI 3 "register_operand" "d"))]
5322 "TARGET_68020 && TARGET_BITFIELD
5323 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
5324 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
5325 && (GET_CODE (operands[0]) == REG
5326 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
5329 if (REG_P (operands[0]))
5331 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
5332 return \"bfins %3,%0{%b2:%b1}\";
5335 operands[0] = adjust_address (operands[0],
5336 INTVAL (operands[1]) == 8 ? QImode : HImode,
5337 INTVAL (operands[2]) / 8);
5339 if (GET_CODE (operands[3]) == MEM)
5340 operands[3] = adjust_address (operands[3],
5341 INTVAL (operands[1]) == 8 ? QImode : HImode,
5342 (32 - INTVAL (operands[1])) / 8);
5344 if (INTVAL (operands[1]) == 8)
5345 return \"move%.b %3,%0\";
5346 return \"move%.w %3,%0\";
5351 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5352 ; alignment of structure members is specified.
5354 ; The move is allowed to be odd byte aligned, because that's still faster
5355 ; than an odd byte aligned bit field instruction.
5358 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5359 (zero_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
5361 (match_operand:SI 2 "const_int_operand" "n")))]
5362 "TARGET_68020 && TARGET_BITFIELD
5363 && (INTVAL (operands[2]) % 8) == 0
5364 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5368 = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8);
5370 return \"move%.l %1,%0\";
5374 [(set (match_operand:SI 0 "nonimmediate_operand" "=&d")
5375 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
5376 (match_operand:SI 2 "const_int_operand" "n")
5377 (match_operand:SI 3 "const_int_operand" "n")))]
5378 "TARGET_68020 && TARGET_BITFIELD
5379 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5380 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5381 && (GET_CODE (operands[1]) == REG
5382 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5385 cc_status.flags |= CC_NOT_NEGATIVE;
5386 if (REG_P (operands[1]))
5388 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5389 return \"bfextu %1{%b3:%b2},%0\";
5393 = adjust_address (operands[1], SImode, INTVAL (operands[3]) / 8);
5395 output_asm_insn (\"clr%.l %0\", operands);
5396 if (GET_CODE (operands[0]) == MEM)
5397 operands[0] = adjust_address (operands[0],
5398 INTVAL (operands[2]) == 8 ? QImode : HImode,
5399 (32 - INTVAL (operands[1])) / 8);
5401 if (INTVAL (operands[2]) == 8)
5402 return \"move%.b %1,%0\";
5403 return \"move%.w %1,%0\";
5407 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5408 ; alignment of structure members is specified.
5410 ; The move is allowed to be odd byte aligned, because that's still faster
5411 ; than an odd byte aligned bit field instruction.
5414 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5415 (sign_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
5417 (match_operand:SI 2 "const_int_operand" "n")))]
5418 "TARGET_68020 && TARGET_BITFIELD
5419 && (INTVAL (operands[2]) % 8) == 0
5420 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5424 = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8);
5426 return \"move%.l %1,%0\";
5430 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5431 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
5432 (match_operand:SI 2 "const_int_operand" "n")
5433 (match_operand:SI 3 "const_int_operand" "n")))]
5434 "TARGET_68020 && TARGET_BITFIELD
5435 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5436 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5437 && (GET_CODE (operands[1]) == REG
5438 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5441 if (REG_P (operands[1]))
5443 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5444 return \"bfexts %1{%b3:%b2},%0\";
5448 = adjust_address (operands[1],
5449 INTVAL (operands[2]) == 8 ? QImode : HImode,
5450 INTVAL (operands[3]) / 8);
5452 if (INTVAL (operands[2]) == 8)
5453 return \"move%.b %1,%0\;extb%.l %0\";
5454 return \"move%.w %1,%0\;ext%.l %0\";
5457 ;; Bit field instructions, general cases.
5458 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
5459 ;; so that its address is reloaded.
5461 (define_expand "extv"
5462 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5463 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
5464 (match_operand:SI 2 "general_operand" "")
5465 (match_operand:SI 3 "general_operand" "")))]
5466 "TARGET_68020 && TARGET_BITFIELD"
5470 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5471 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5472 (match_operand:SI 2 "general_operand" "di")
5473 (match_operand:SI 3 "general_operand" "di")))]
5474 "TARGET_68020 && TARGET_BITFIELD"
5475 "bfexts %1{%b3:%b2},%0")
5477 (define_expand "extzv"
5478 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5479 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
5480 (match_operand:SI 2 "general_operand" "")
5481 (match_operand:SI 3 "general_operand" "")))]
5482 "TARGET_68020 && TARGET_BITFIELD"
5486 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d")
5487 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
5488 (match_operand:SI 2 "general_operand" "di,di")
5489 (match_operand:SI 3 "general_operand" "di,di")))]
5490 "TARGET_68020 && TARGET_BITFIELD"
5493 if (GET_CODE (operands[2]) == CONST_INT)
5495 if (INTVAL (operands[2]) != 32)
5496 cc_status.flags |= CC_NOT_NEGATIVE;
5502 return \"bfextu %1{%b3:%b2},%0\";
5506 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5507 (match_operand:SI 1 "general_operand" "di")
5508 (match_operand:SI 2 "general_operand" "di"))
5509 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
5510 (match_operand 3 "const_int_operand" "n")))]
5511 "TARGET_68020 && TARGET_BITFIELD
5512 && (INTVAL (operands[3]) == -1
5513 || (GET_CODE (operands[1]) == CONST_INT
5514 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
5518 return \"bfchg %0{%b2:%b1}\";
5522 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5523 (match_operand:SI 1 "general_operand" "di")
5524 (match_operand:SI 2 "general_operand" "di"))
5526 "TARGET_68020 && TARGET_BITFIELD"
5530 return \"bfclr %0{%b2:%b1}\";
5534 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5535 (match_operand:SI 1 "general_operand" "di")
5536 (match_operand:SI 2 "general_operand" "di"))
5538 "TARGET_68020 && TARGET_BITFIELD"
5542 return \"bfset %0{%b2:%b1}\";
5545 (define_expand "insv"
5546 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "")
5547 (match_operand:SI 1 "general_operand" "")
5548 (match_operand:SI 2 "general_operand" ""))
5549 (match_operand:SI 3 "register_operand" ""))]
5550 "TARGET_68020 && TARGET_BITFIELD"
5554 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5555 (match_operand:SI 1 "general_operand" "di")
5556 (match_operand:SI 2 "general_operand" "di"))
5557 (match_operand:SI 3 "register_operand" "d"))]
5558 "TARGET_68020 && TARGET_BITFIELD"
5559 "bfins %3,%0{%b2:%b1}")
5561 ;; Now recognize bit field insns that operate on registers
5562 ;; (or at least were intended to do so).
5565 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5566 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5567 (match_operand:SI 2 "general_operand" "di")
5568 (match_operand:SI 3 "general_operand" "di")))]
5569 "TARGET_68020 && TARGET_BITFIELD"
5570 "bfexts %1{%b3:%b2},%0")
5573 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5574 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5575 (match_operand:SI 2 "general_operand" "di")
5576 (match_operand:SI 3 "general_operand" "di")))]
5577 "TARGET_68020 && TARGET_BITFIELD"
5580 if (GET_CODE (operands[2]) == CONST_INT)
5582 if (INTVAL (operands[2]) != 32)
5583 cc_status.flags |= CC_NOT_NEGATIVE;
5589 return \"bfextu %1{%b3:%b2},%0\";
5593 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5594 (match_operand:SI 1 "general_operand" "di")
5595 (match_operand:SI 2 "general_operand" "di"))
5597 "TARGET_68020 && TARGET_BITFIELD"
5601 return \"bfclr %0{%b2:%b1}\";
5605 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5606 (match_operand:SI 1 "general_operand" "di")
5607 (match_operand:SI 2 "general_operand" "di"))
5609 "TARGET_68020 && TARGET_BITFIELD"
5613 return \"bfset %0{%b2:%b1}\";
5617 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5618 (match_operand:SI 1 "general_operand" "di")
5619 (match_operand:SI 2 "general_operand" "di"))
5620 (match_operand:SI 3 "register_operand" "d"))]
5621 "TARGET_68020 && TARGET_BITFIELD"
5625 /* These special cases are now recognized by a specific pattern. */
5626 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5627 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5628 return \"move%.w %3,%0\";
5629 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5630 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
5631 return \"move%.b %3,%0\";
5633 return \"bfins %3,%0{%b2:%b1}\";
5636 ;; Special patterns for optimizing bit-field instructions.
5640 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5641 (match_operand:SI 1 "const_int_operand" "n")
5642 (match_operand:SI 2 "general_operand" "di")))]
5643 "TARGET_68020 && TARGET_BITFIELD"
5646 if (operands[1] == const1_rtx
5647 && GET_CODE (operands[2]) == CONST_INT)
5649 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5650 return output_btst (operands,
5651 GEN_INT (width - INTVAL (operands[2])),
5652 operands[0], insn, 1000);
5653 /* Pass 1000 as SIGNPOS argument so that btst will
5654 not think we are testing the sign bit for an `and'
5655 and assume that nonzero implies a negative result. */
5657 if (INTVAL (operands[1]) != 32)
5658 cc_status.flags = CC_NOT_NEGATIVE;
5659 return \"bftst %0{%b2:%b1}\";
5663 ;;; now handle the register cases
5666 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5667 (match_operand:SI 1 "const_int_operand" "n")
5668 (match_operand:SI 2 "general_operand" "di")))]
5669 "TARGET_68020 && TARGET_BITFIELD"
5672 if (operands[1] == const1_rtx
5673 && GET_CODE (operands[2]) == CONST_INT)
5675 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5676 return output_btst (operands, GEN_INT (width - INTVAL (operands[2])),
5677 operands[0], insn, 1000);
5678 /* Pass 1000 as SIGNPOS argument so that btst will
5679 not think we are testing the sign bit for an `and'
5680 and assume that nonzero implies a negative result. */
5682 if (INTVAL (operands[1]) != 32)
5683 cc_status.flags = CC_NOT_NEGATIVE;
5684 return \"bftst %0{%b2:%b1}\";
5687 (define_insn "scc0_di"
5688 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
5689 (match_operator 1 "valid_dbcc_comparison_p"
5690 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5694 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5697 (define_insn "scc0_di_5200"
5698 [(set (match_operand:QI 0 "nonimmediate_operand" "=d")
5699 (match_operator 1 "valid_dbcc_comparison_p"
5700 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5704 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5707 (define_insn "scc_di"
5708 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,dm")
5709 (match_operator 1 "valid_dbcc_comparison_p"
5710 [(match_operand:DI 2 "general_operand" "ro,r")
5711 (match_operand:DI 3 "general_operand" "r,ro")]))]
5715 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5718 (define_insn "scc_di_5200"
5719 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d")
5720 (match_operator 1 "valid_dbcc_comparison_p"
5721 [(match_operand:DI 2 "general_operand" "ro,r")
5722 (match_operand:DI 3 "general_operand" "r,ro")]))]
5726 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5729 ;; Note that operand 0 of an SCC insn is supported in the hardware as
5730 ;; memory, but we cannot allow it to be in memory in case the address
5731 ;; needs to be reloaded.
5733 (define_expand "seq"
5734 [(set (match_operand:QI 0 "register_operand" "")
5735 (eq:QI (cc0) (const_int 0)))]
5739 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5741 m68k_last_compare_had_fp_operands = 0;
5747 [(set (match_operand:QI 0 "register_operand" "=d")
5748 (eq:QI (cc0) (const_int 0)))]
5751 cc_status = cc_prev_status;
5752 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5755 (define_expand "sne"
5756 [(set (match_operand:QI 0 "register_operand" "")
5757 (ne:QI (cc0) (const_int 0)))]
5761 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5763 m68k_last_compare_had_fp_operands = 0;
5769 [(set (match_operand:QI 0 "register_operand" "=d")
5770 (ne:QI (cc0) (const_int 0)))]
5773 cc_status = cc_prev_status;
5774 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5777 (define_expand "sgt"
5778 [(set (match_operand:QI 0 "register_operand" "")
5779 (gt:QI (cc0) (const_int 0)))]
5783 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5785 m68k_last_compare_had_fp_operands = 0;
5791 [(set (match_operand:QI 0 "register_operand" "=d")
5792 (gt:QI (cc0) (const_int 0)))]
5795 cc_status = cc_prev_status;
5796 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5799 (define_expand "sgtu"
5800 [(set (match_operand:QI 0 "register_operand" "")
5801 (gtu:QI (cc0) (const_int 0)))]
5806 [(set (match_operand:QI 0 "register_operand" "=d")
5807 (gtu:QI (cc0) (const_int 0)))]
5810 cc_status = cc_prev_status;
5811 return \"shi %0\"; ")
5813 (define_expand "slt"
5814 [(set (match_operand:QI 0 "register_operand" "")
5815 (lt:QI (cc0) (const_int 0)))]
5819 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5821 m68k_last_compare_had_fp_operands = 0;
5827 [(set (match_operand:QI 0 "register_operand" "=d")
5828 (lt:QI (cc0) (const_int 0)))]
5831 cc_status = cc_prev_status;
5832 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5834 (define_expand "sltu"
5835 [(set (match_operand:QI 0 "register_operand" "")
5836 (ltu:QI (cc0) (const_int 0)))]
5841 [(set (match_operand:QI 0 "register_operand" "=d")
5842 (ltu:QI (cc0) (const_int 0)))]
5845 cc_status = cc_prev_status;
5846 return \"scs %0\"; ")
5848 (define_expand "sge"
5849 [(set (match_operand:QI 0 "register_operand" "")
5850 (ge:QI (cc0) (const_int 0)))]
5854 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5856 m68k_last_compare_had_fp_operands = 0;
5862 [(set (match_operand:QI 0 "register_operand" "=d")
5863 (ge:QI (cc0) (const_int 0)))]
5866 cc_status = cc_prev_status;
5867 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5869 (define_expand "sgeu"
5870 [(set (match_operand:QI 0 "register_operand" "")
5871 (geu:QI (cc0) (const_int 0)))]
5876 [(set (match_operand:QI 0 "register_operand" "=d")
5877 (geu:QI (cc0) (const_int 0)))]
5880 cc_status = cc_prev_status;
5881 return \"scc %0\"; ")
5883 (define_expand "sle"
5884 [(set (match_operand:QI 0 "register_operand" "")
5885 (le:QI (cc0) (const_int 0)))]
5889 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5891 m68k_last_compare_had_fp_operands = 0;
5897 [(set (match_operand:QI 0 "register_operand" "=d")
5898 (le:QI (cc0) (const_int 0)))]
5901 cc_status = cc_prev_status;
5902 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5905 (define_expand "sleu"
5906 [(set (match_operand:QI 0 "register_operand" "")
5907 (leu:QI (cc0) (const_int 0)))]
5912 [(set (match_operand:QI 0 "register_operand" "=d")
5913 (leu:QI (cc0) (const_int 0)))]
5916 cc_status = cc_prev_status;
5917 return \"sls %0\"; ")
5919 (define_expand "sordered"
5920 [(set (match_operand:QI 0 "register_operand" "")
5921 (ordered:QI (cc0) (const_int 0)))]
5922 "TARGET_68881 && !TARGET_68060"
5924 if (! m68k_last_compare_had_fp_operands)
5926 m68k_last_compare_had_fp_operands = 0;
5929 (define_insn "*sordered_1"
5930 [(set (match_operand:QI 0 "register_operand" "=d")
5931 (ordered:QI (cc0) (const_int 0)))]
5932 "TARGET_68881 && !TARGET_68060"
5934 cc_status = cc_prev_status;
5938 (define_expand "sunordered"
5939 [(set (match_operand:QI 0 "register_operand" "")
5940 (unordered:QI (cc0) (const_int 0)))]
5941 "TARGET_68881 && !TARGET_68060"
5943 if (! m68k_last_compare_had_fp_operands)
5945 m68k_last_compare_had_fp_operands = 0;
5948 (define_insn "*sunordered_1"
5949 [(set (match_operand:QI 0 "register_operand" "=d")
5950 (unordered:QI (cc0) (const_int 0)))]
5951 "TARGET_68881 && !TARGET_68060"
5953 cc_status = cc_prev_status;
5957 (define_expand "suneq"
5958 [(set (match_operand:QI 0 "register_operand" "")
5959 (uneq:QI (cc0) (const_int 0)))]
5960 "TARGET_68881 && !TARGET_68060"
5962 if (! m68k_last_compare_had_fp_operands)
5964 m68k_last_compare_had_fp_operands = 0;
5967 (define_insn "*suneq_1"
5968 [(set (match_operand:QI 0 "register_operand" "=d")
5969 (uneq:QI (cc0) (const_int 0)))]
5970 "TARGET_68881 && !TARGET_68060"
5972 cc_status = cc_prev_status;
5976 (define_expand "sunge"
5977 [(set (match_operand:QI 0 "register_operand" "")
5978 (unge:QI (cc0) (const_int 0)))]
5979 "TARGET_68881 && !TARGET_68060"
5981 if (! m68k_last_compare_had_fp_operands)
5983 m68k_last_compare_had_fp_operands = 0;
5986 (define_insn "*sunge_1"
5987 [(set (match_operand:QI 0 "register_operand" "=d")
5988 (unge:QI (cc0) (const_int 0)))]
5989 "TARGET_68881 && !TARGET_68060"
5991 cc_status = cc_prev_status;
5995 (define_expand "sungt"
5996 [(set (match_operand:QI 0 "register_operand" "")
5997 (ungt:QI (cc0) (const_int 0)))]
5998 "TARGET_68881 && !TARGET_68060"
6000 if (! m68k_last_compare_had_fp_operands)
6002 m68k_last_compare_had_fp_operands = 0;
6005 (define_insn "*sungt_1"
6006 [(set (match_operand:QI 0 "register_operand" "=d")
6007 (ungt:QI (cc0) (const_int 0)))]
6008 "TARGET_68881 && !TARGET_68060"
6010 cc_status = cc_prev_status;
6014 (define_expand "sunle"
6015 [(set (match_operand:QI 0 "register_operand" "")
6016 (unle:QI (cc0) (const_int 0)))]
6017 "TARGET_68881 && !TARGET_68060"
6019 if (! m68k_last_compare_had_fp_operands)
6021 m68k_last_compare_had_fp_operands = 0;
6024 (define_insn "*sunle_1"
6025 [(set (match_operand:QI 0 "register_operand" "=d")
6026 (unle:QI (cc0) (const_int 0)))]
6027 "TARGET_68881 && !TARGET_68060"
6029 cc_status = cc_prev_status;
6033 (define_expand "sunlt"
6034 [(set (match_operand:QI 0 "register_operand" "")
6035 (unlt:QI (cc0) (const_int 0)))]
6036 "TARGET_68881 && !TARGET_68060"
6038 if (! m68k_last_compare_had_fp_operands)
6040 m68k_last_compare_had_fp_operands = 0;
6043 (define_insn "*sunlt_1"
6044 [(set (match_operand:QI 0 "register_operand" "=d")
6045 (unlt:QI (cc0) (const_int 0)))]
6046 "TARGET_68881 && !TARGET_68060"
6048 cc_status = cc_prev_status;
6052 (define_expand "sltgt"
6053 [(set (match_operand:QI 0 "register_operand" "")
6054 (ltgt:QI (cc0) (const_int 0)))]
6055 "TARGET_68881 && !TARGET_68060"
6057 if (! m68k_last_compare_had_fp_operands)
6059 m68k_last_compare_had_fp_operands = 0;
6062 (define_insn "*sltgt_1"
6063 [(set (match_operand:QI 0 "register_operand" "=d")
6064 (ltgt:QI (cc0) (const_int 0)))]
6065 "TARGET_68881 && !TARGET_68060"
6067 cc_status = cc_prev_status;
6071 (define_insn "*fsogt_1"
6072 [(set (match_operand:QI 0 "register_operand" "=d")
6073 (not:QI (unle:QI (cc0) (const_int 0))))]
6074 "TARGET_68881 && !TARGET_68060"
6076 cc_status = cc_prev_status;
6080 (define_insn "*fsoge_1"
6081 [(set (match_operand:QI 0 "register_operand" "=d")
6082 (not:QI (unlt:QI (cc0) (const_int 0))))]
6083 "TARGET_68881 && !TARGET_68060"
6085 cc_status = cc_prev_status;
6089 (define_insn "*fsolt_1"
6090 [(set (match_operand:QI 0 "register_operand" "=d")
6091 (not:QI (unge:QI (cc0) (const_int 0))))]
6092 "TARGET_68881 && !TARGET_68060"
6094 cc_status = cc_prev_status;
6098 (define_insn "*fsole_1"
6099 [(set (match_operand:QI 0 "register_operand" "=d")
6100 (not:QI (ungt:QI (cc0) (const_int 0))))]
6101 "TARGET_68881 && !TARGET_68060"
6103 cc_status = cc_prev_status;
6107 ;; Basic conditional jump instructions.
6109 (define_insn "beq0_di"
6111 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
6113 (label_ref (match_operand 1 "" ","))
6115 (clobber (match_scratch:SI 2 "=d,d"))]
6120 if (which_alternative == 1)
6122 return \"move%.l %0,%2\;or%.l %0,%2\;jbeq %l1\";
6124 return \"move%.l %0,%2\;or%.l %0,%2\;jeq %l1\";
6126 if ((cc_prev_status.value1
6127 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6128 || (cc_prev_status.value2
6129 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6131 cc_status = cc_prev_status;
6133 return \"jbeq %l1\";
6138 if (GET_CODE (operands[0]) == REG)
6139 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
6141 operands[3] = adjust_address (operands[0], SImode, 4);
6142 if (! ADDRESS_REG_P (operands[0]))
6144 if (reg_overlap_mentioned_p (operands[2], operands[0]))
6146 if (reg_overlap_mentioned_p (operands[2], operands[3]))
6149 return \"or%.l %0,%2\;jbeq %l1\";
6151 return \"or%.l %0,%2\;jeq %l1\";
6157 return \"or%.l %3,%2\;jbeq %l1\";
6159 return \"or%.l %3,%2\;jeq %l1\";
6164 return \"move%.l %0,%2\;or%.l %3,%2\;jbeq %l1\";
6166 return \"move%.l %0,%2\;or%.l %3,%2\;jeq %l1\";
6169 operands[4] = gen_label_rtx();
6170 if (TARGET_68020 || TARGET_5200)
6173 output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands);
6175 output_asm_insn (\"tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1\", operands);
6181 #ifdef SGS_CMP_ORDER
6182 output_asm_insn (\"cmp%.w %0,%#0\;jbne %l4\;cmp%.w %3,%#0\;jbeq %l1\", operands);
6184 output_asm_insn (\"cmp%.w %#0,%0\;jbne %l4\;cmp%.w %#0,%3\;jbeq %l1\", operands);
6187 output_asm_insn (\"cmp%.w %#0,%0\;jne %l4\;cmp%.w %#0,%3\;jeq %l1\", operands);
6190 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6191 CODE_LABEL_NUMBER (operands[4]));
6195 (define_insn "bne0_di"
6197 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
6199 (label_ref (match_operand 1 "" ","))
6201 (clobber (match_scratch:SI 2 "=d,X"))]
6205 if ((cc_prev_status.value1
6206 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6207 || (cc_prev_status.value2
6208 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6210 cc_status = cc_prev_status;
6212 return \"jbne %l1\";
6218 if (GET_CODE (operands[0]) == REG)
6219 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
6221 operands[3] = adjust_address (operands[0], SImode, 4);
6222 if (!ADDRESS_REG_P (operands[0]))
6224 if (reg_overlap_mentioned_p (operands[2], operands[0]))
6226 if (reg_overlap_mentioned_p (operands[2], operands[3]))
6229 return \"or%.l %0,%2\;jbne %l1\";
6231 return \"or%.l %0,%2\;jne %l1\";
6237 return \"or%.l %3,%2\;jbne %l1\";
6239 return \"or%.l %3,%2\;jne %l1\";
6244 return \"move%.l %0,%2\;or%.l %3,%2\;jbne %l1\";
6246 return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\";
6249 if (TARGET_68020 || TARGET_5200)
6252 return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\";
6254 return \"tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1\";
6260 #ifdef SGS_CMP_ORDER
6261 return \"cmp%.w %0,%#0\;jbne %l1\;cmp%.w %3,%#0\;jbne %l1\";
6263 return \"cmp%.w %#0,%0\;jbne %l1\;cmp%.w %#0,%3\;jbne %l1\";
6266 return \"cmp%.w %#0,%0\;jne %l1\;cmp%.w %#0,%3\;jne %l1\";
6271 (define_insn "bge0_di"
6273 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
6275 (label_ref (match_operand 1 "" ""))
6280 if ((cc_prev_status.value1
6281 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6282 || (cc_prev_status.value2
6283 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6285 cc_status = cc_prev_status;
6286 if (cc_status.flags & CC_REVERSED)
6289 return \"jble %l1\";
6297 return \"jbpl %l1\";
6304 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
6305 output_asm_insn(\"tst%.l %0\", operands);
6308 /* On an address reg, cmpw may replace cmpl. */
6309 #ifdef SGS_CMP_ORDER
6310 output_asm_insn(\"cmp%.w %0,%#0\", operands);
6312 output_asm_insn(\"cmp%.w %#0,%0\", operands);
6317 return \"jbpl %l1\";
6323 (define_insn "blt0_di"
6325 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
6327 (label_ref (match_operand 1 "" ""))
6332 if ((cc_prev_status.value1
6333 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6334 || (cc_prev_status.value2
6335 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6337 cc_status = cc_prev_status;
6338 if (cc_status.flags & CC_REVERSED)
6341 return \"jbgt %l1\";
6349 return \"jbmi %l1\";
6356 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
6357 output_asm_insn(\"tst%.l %0\", operands);
6360 /* On an address reg, cmpw may replace cmpl. */
6361 #ifdef SGS_CMP_ORDER
6362 output_asm_insn(\"cmp%.w %0,%#0\", operands);
6364 output_asm_insn(\"cmp%.w %#0,%0\", operands);
6369 return \"jbmi %l1\";
6377 (if_then_else (eq (cc0)
6379 (label_ref (match_operand 0 "" ""))
6385 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6387 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6393 (if_then_else (ne (cc0)
6395 (label_ref (match_operand 0 "" ""))
6401 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6403 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6409 (if_then_else (gt (cc0)
6411 (label_ref (match_operand 0 "" ""))
6416 OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0);
6418 OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0);
6424 (if_then_else (gtu (cc0)
6426 (label_ref (match_operand 0 "" ""))
6431 return \"jbhi %l0\";
6439 (if_then_else (lt (cc0)
6441 (label_ref (match_operand 0 "" ""))
6446 OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\");
6448 OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\");
6454 (if_then_else (ltu (cc0)
6456 (label_ref (match_operand 0 "" ""))
6461 return \"jbcs %l0\";
6469 (if_then_else (ge (cc0)
6471 (label_ref (match_operand 0 "" ""))
6476 OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\");
6478 OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\");
6484 (if_then_else (geu (cc0)
6486 (label_ref (match_operand 0 "" ""))
6491 return \"jbcc %l0\";
6499 (if_then_else (le (cc0)
6501 (label_ref (match_operand 0 "" ""))
6506 OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0);
6508 OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0);
6514 (if_then_else (leu (cc0)
6516 (label_ref (match_operand 0 "" ""))
6521 return \"jbls %l0\";
6527 (define_insn "bordered"
6529 (if_then_else (ordered (cc0) (const_int 0))
6530 (label_ref (match_operand 0 "" ""))
6534 if (!(cc_prev_status.flags & CC_IN_68881))
6543 (define_insn "bunordered"
6545 (if_then_else (unordered (cc0) (const_int 0))
6546 (label_ref (match_operand 0 "" ""))
6550 if (!(cc_prev_status.flags & CC_IN_68881))
6559 (define_insn "buneq"
6561 (if_then_else (uneq (cc0) (const_int 0))
6562 (label_ref (match_operand 0 "" ""))
6566 if (!(cc_prev_status.flags & CC_IN_68881))
6575 (define_insn "bunge"
6577 (if_then_else (unge (cc0) (const_int 0))
6578 (label_ref (match_operand 0 "" ""))
6582 if (!(cc_prev_status.flags & CC_IN_68881))
6591 (define_insn "bungt"
6593 (if_then_else (ungt (cc0) (const_int 0))
6594 (label_ref (match_operand 0 "" ""))
6598 if (!(cc_prev_status.flags & CC_IN_68881))
6607 (define_insn "bunle"
6609 (if_then_else (unle (cc0) (const_int 0))
6610 (label_ref (match_operand 0 "" ""))
6614 if (!(cc_prev_status.flags & CC_IN_68881))
6623 (define_insn "bunlt"
6625 (if_then_else (unlt (cc0) (const_int 0))
6626 (label_ref (match_operand 0 "" ""))
6630 if (!(cc_prev_status.flags & CC_IN_68881))
6639 (define_insn "bltgt"
6641 (if_then_else (ltgt (cc0) (const_int 0))
6642 (label_ref (match_operand 0 "" ""))
6646 if (!(cc_prev_status.flags & CC_IN_68881))
6655 ;; Negated conditional jump instructions.
6659 (if_then_else (eq (cc0)
6662 (label_ref (match_operand 0 "" ""))))]
6667 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6669 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6675 (if_then_else (ne (cc0)
6678 (label_ref (match_operand 0 "" ""))))]
6683 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6685 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6691 (if_then_else (gt (cc0)
6694 (label_ref (match_operand 0 "" ""))))]
6698 OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0);
6700 OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0);
6706 (if_then_else (gtu (cc0)
6709 (label_ref (match_operand 0 "" ""))))]
6713 return \"jbls %l0\";
6721 (if_then_else (lt (cc0)
6724 (label_ref (match_operand 0 "" ""))))]
6728 OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\");
6730 OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\");
6736 (if_then_else (ltu (cc0)
6739 (label_ref (match_operand 0 "" ""))))]
6743 return \"jbcc %l0\";
6751 (if_then_else (ge (cc0)
6754 (label_ref (match_operand 0 "" ""))))]
6758 OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\");
6760 OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\");
6766 (if_then_else (geu (cc0)
6769 (label_ref (match_operand 0 "" ""))))]
6773 return \"jbcs %l0\";
6781 (if_then_else (le (cc0)
6784 (label_ref (match_operand 0 "" ""))))]
6788 OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0);
6790 OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0);
6796 (if_then_else (leu (cc0)
6799 (label_ref (match_operand 0 "" ""))))]
6803 return \"jbhi %l0\";
6809 (define_insn "*bordered_rev"
6811 (if_then_else (ordered (cc0) (const_int 0))
6813 (label_ref (match_operand 0 "" ""))))]
6816 if (!(cc_prev_status.flags & CC_IN_68881))
6825 (define_insn "*bunordered_rev"
6827 (if_then_else (unordered (cc0) (const_int 0))
6829 (label_ref (match_operand 0 "" ""))))]
6832 if (!(cc_prev_status.flags & CC_IN_68881))
6841 (define_insn "*buneq_rev"
6843 (if_then_else (uneq (cc0) (const_int 0))
6845 (label_ref (match_operand 0 "" ""))))]
6848 if (!(cc_prev_status.flags & CC_IN_68881))
6857 (define_insn "*bunge_rev"
6859 (if_then_else (unge (cc0) (const_int 0))
6861 (label_ref (match_operand 0 "" ""))))]
6864 if (!(cc_prev_status.flags & CC_IN_68881))
6873 (define_insn "*bunle_rev"
6875 (if_then_else (unle (cc0) (const_int 0))
6877 (label_ref (match_operand 0 "" ""))))]
6880 if (!(cc_prev_status.flags & CC_IN_68881))
6889 (define_insn "*bunlt_rev"
6891 (if_then_else (unlt (cc0) (const_int 0))
6893 (label_ref (match_operand 0 "" ""))))]
6896 if (!(cc_prev_status.flags & CC_IN_68881))
6905 (define_insn "*bltgt_rev"
6907 (if_then_else (ltgt (cc0) (const_int 0))
6909 (label_ref (match_operand 0 "" ""))))]
6912 if (!(cc_prev_status.flags & CC_IN_68881))
6921 ;; Unconditional and other jump instructions
6924 (label_ref (match_operand 0 "" "")))]
6928 return \"jbra %l0\";
6934 ;; We support two different ways of handling dispatch tables.
6935 ;; The NeXT uses absolute tables, and other machines use relative.
6936 ;; This define_expand can generate either kind.
6937 (define_expand "tablejump"
6938 [(parallel [(set (pc) (match_operand 0 "" ""))
6939 (use (label_ref (match_operand 1 "" "")))])]
6943 #ifdef CASE_VECTOR_PC_RELATIVE
6944 operands[0] = gen_rtx_PLUS (SImode, pc_rtx,
6945 gen_rtx_SIGN_EXTEND (SImode, operands[0]));
6949 ;; Jump to variable address from dispatch table of absolute addresses.
6951 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
6952 (use (label_ref (match_operand 1 "" "")))]
6956 return \"jmp (%0)\";
6962 ;; Jump to variable address from dispatch table of relative addresses.
6966 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
6967 (use (label_ref (match_operand 1 "" "")))]
6970 #ifdef ASM_RETURN_CASE_JUMP
6971 ASM_RETURN_CASE_JUMP;
6974 #ifdef ASM_OUTPUT_CASE_LABEL
6977 if (ADDRESS_REG_P (operands[0]))
6978 return \"jmp 6(%%pc,%0.l)\";
6980 return \"ext%.l %0\;jmp 6(%%pc,%0.l)\";
6983 return \"jmp 6(%%pc,%0.w)\";
6987 if (ADDRESS_REG_P (operands[0]))
6990 return \"jmp 2(pc,%0.l)\";
6992 return \"jmp 2(%%pc,%0.l)\";
6993 #endif /* end !CRDS */
6998 return \"ext%.l %0\;jmp 2(pc,%0.l)\";
7000 return \"extl %0\;jmp 2(%%pc,%0.l)\";
7001 #endif /* end !CRDS */
7007 return \"jmp 2(pc,%0.w)\";
7009 return \"jmp 2(%%pc,%0.w)\";
7010 #endif /* end !CRDS */
7016 if (ADDRESS_REG_P (operands[0]))
7019 return \"jmp (2,pc,%0.l)\";
7021 return \"jmp pc@(2,%0:l)\";
7027 return \"ext%.l %0\;jmp (2,pc,%0.l)\";
7029 return \"extl %0\;jmp pc@(2,%0:l)\";
7036 return \"jmp (2,pc,%0.w)\";
7038 return \"jmp pc@(2,%0:w)\";
7045 ;; Decrement-and-branch insns.
7049 (ne (match_operand:HI 0 "nonimmediate_operand" "+d*g")
7051 (label_ref (match_operand 1 "" ""))
7054 (plus:HI (match_dup 0)
7060 if (DATA_REG_P (operands[0]))
7061 return \"dbra %0,%l1\";
7062 if (GET_CODE (operands[0]) == MEM)
7066 return \"sub%.w %#1,%0\;jbcc %l1\";
7068 return \"subq%.w %#1,%0\;jbcc %l1\";
7070 #else /* not MOTOROLA */
7071 return \"subqw %#1,%0\;jcc %l1\";
7075 #ifdef SGS_CMP_ORDER
7077 return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
7079 return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
7081 #else /* not SGS_CMP_ORDER */
7082 return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
7084 #else /* not MOTOROLA */
7085 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
7092 (ne (match_operand:SI 0 "nonimmediate_operand" "+d*g")
7094 (label_ref (match_operand 1 "" ""))
7097 (plus:SI (match_dup 0)
7105 if (DATA_REG_P (operands[0]))
7106 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
7107 if (GET_CODE (operands[0]) == MEM)
7108 return \"sub%.l %#1,%0\;jbcc %l1\";
7110 if (DATA_REG_P (operands[0]))
7111 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
7112 if (GET_CODE (operands[0]) == MEM)
7113 return \"subq%.l %#1,%0\;jbcc %l1\";
7114 #endif /* NO_ADDSUB_Q */
7115 #ifdef SGS_CMP_ORDER
7117 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
7119 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
7121 #else /* not SGS_CMP_ORDER */
7122 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
7123 #endif /* not SGS_CMP_ORDER */
7124 #else /* not MOTOROLA */
7125 if (DATA_REG_P (operands[0]))
7126 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
7127 if (GET_CODE (operands[0]) == MEM)
7128 return \"subql %#1,%0\;jcc %l1\";
7129 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
7130 #endif /* not MOTOROLA */
7133 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
7138 (ge (plus:HI (match_operand:HI 0 "nonimmediate_operand" "+d*am")
7141 (label_ref (match_operand 1 "" ""))
7144 (plus:HI (match_dup 0)
7146 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
7152 if (DATA_REG_P (operands[0]))
7153 return \"dbra %0,%l1\";
7154 if (GET_CODE (operands[0]) == MEM)
7155 return \"sub%.w %#1,%0\;jbcc %l1\";
7157 if (DATA_REG_P (operands[0]))
7158 return \"dbra %0,%l1\";
7159 if (GET_CODE (operands[0]) == MEM)
7160 return \"subq%.w %#1,%0\;jbcc %l1\";
7162 #ifdef SGS_CMP_ORDER
7164 return \"sub.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
7166 return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
7168 #else /* not SGS_CMP_ORDER */
7169 return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\";
7170 #endif /* not SGS_CMP_ORDER */
7171 #else /* not MOTOROLA */
7172 if (DATA_REG_P (operands[0]))
7173 return \"dbra %0,%l1\";
7174 if (GET_CODE (operands[0]) == MEM)
7175 return \"subqw %#1,%0\;jcc %l1\";
7176 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
7177 #endif /* not MOTOROLA */
7180 (define_expand "decrement_and_branch_until_zero"
7181 [(parallel [(set (pc)
7183 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "")
7186 (label_ref (match_operand 1 "" ""))
7189 (plus:SI (match_dup 0)
7197 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+d*am")
7200 (label_ref (match_operand 1 "" ""))
7203 (plus:SI (match_dup 0)
7205 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
7211 if (DATA_REG_P (operands[0]))
7212 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
7213 if (GET_CODE (operands[0]) == MEM)
7214 return \"sub%.l %#1,%0\;jbcc %l1\";
7216 if (DATA_REG_P (operands[0]))
7217 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
7218 if (GET_CODE (operands[0]) == MEM)
7219 return \"subq%.l %#1,%0\;jbcc %l1\";
7221 #ifdef SGS_CMP_ORDER
7223 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
7225 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
7227 #else /* not SGS_CMP_ORDER */
7228 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
7229 #endif /* not SGS_CMP_ORDER */
7230 #else /* not MOTOROLA */
7231 if (DATA_REG_P (operands[0]))
7232 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
7233 if (GET_CODE (operands[0]) == MEM)
7234 return \"subql %#1,%0\;jcc %l1\";
7235 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
7236 #endif /* not MOTOROLA */
7240 ;; For PIC calls, in order to be able to support
7241 ;; dynamic linker LAZY BINDING, all the procedure calls need to go
7242 ;; through the PLT (Procedure Linkage Table) section in PIC mode.
7244 ;; PIC calls are handled by loading the address of the function into a
7245 ;; register (via movsi), then emitting a register indirect call using
7246 ;; the "jsr" function call syntax.
7248 ;; When outputting MIT syntax (e.g. on Suns), we add a bogus extra
7249 ;; operand to the jbsr statement to indicate that this call should
7250 ;; go through the PLT (why? because this is the way that Sun does it).
7252 ;; We have different patterns for PIC calls and non-PIC calls. The
7253 ;; different patterns are only used to choose the right syntax.
7255 ;; The svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it
7256 ;; will create the correct relocation entry (R_68K_PLT32) for `FUNC',
7257 ;; that tells the linker editor to create an entry for `FUNC' in PLT
7258 ;; section at link time. However, all global objects reference are still
7259 ;; done by using `OBJ@GOT'. So, the goal here is to output the function
7260 ;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'.
7261 ;; We need to have a way to differentiate these two different operands.
7263 ;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate
7264 ;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs
7265 ;; to be changed to recognize function calls symbol_ref operand as a valid
7266 ;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will
7267 ;; avoid the compiler to load this symbol_ref operand into a register.
7268 ;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly
7269 ;; since the value is a PC relative offset, not a real address.
7271 ;; All global objects are treated in the similar way as in SUN3. The only
7272 ;; difference is: on m68k svr4, the reference of such global object needs
7273 ;; to end with a suffix "@GOT" so the assembler and linker know to create
7274 ;; an entry for it in GOT (Global Offset Table) section. This is done in
7277 ;; Call subroutine with no return value.
7278 (define_expand "call"
7279 [(call (match_operand:QI 0 "memory_operand" "")
7280 (match_operand:SI 1 "general_operand" ""))]
7281 ;; Operand 1 not really used on the m68000.
7286 if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
7287 SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
7290 ;; This is a normal call sequence.
7292 [(call (match_operand:QI 0 "memory_operand" "o")
7293 (match_operand:SI 1 "general_operand" "g"))]
7294 ;; Operand 1 not really used on the m68000.
7298 #if defined (MOTOROLA) && !defined (USE_GAS)
7300 if (GET_CODE (operands[0]) == MEM
7301 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
7310 ;; This is a PIC call sequence.
7312 [(call (match_operand:QI 0 "memory_operand" "o")
7313 (match_operand:SI 1 "general_operand" "g"))]
7314 ;; Operand 1 not really used on the m68000.
7318 if (GET_CODE (operands[0]) == MEM
7319 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
7321 if (TARGET_PCREL) return \"bsr.l %o0\";
7324 return \"bsr.l %0\";
7327 return \"bsr.l %0@PLTPC\";
7329 return \"bsr %0@PLTPC\";
7334 return \"bsr.l %0\";
7336 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC,
7337 GAS just plain ignores it. FIXME: not anymore, gas doesn't! */
7338 return \"jbsr %0,a1\";
7345 ;; Call subroutine, returning value in operand 0
7346 ;; (which must be a hard register).
7347 ;; See comments before "call" regarding PIC calls.
7348 (define_expand "call_value"
7349 [(set (match_operand 0 "" "")
7350 (call (match_operand:QI 1 "memory_operand" "")
7351 (match_operand:SI 2 "general_operand" "")))]
7352 ;; Operand 2 not really used on the m68000.
7356 if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
7357 SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
7360 ;; This is a normal call_value
7362 [(set (match_operand 0 "" "=rf")
7363 (call (match_operand:QI 1 "memory_operand" "o")
7364 (match_operand:SI 2 "general_operand" "g")))]
7365 ;; Operand 2 not really used on the m68000.
7368 #if defined (MOTOROLA) && !defined (USE_GAS)
7370 if (GET_CODE (operands[1]) == MEM
7371 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
7380 ;; This is a PIC call_value
7382 [(set (match_operand 0 "" "=rf")
7383 (call (match_operand:QI 1 "memory_operand" "o")
7384 (match_operand:SI 2 "general_operand" "g")))]
7385 ;; Operand 2 not really used on the m68000.
7388 if (GET_CODE (operands[1]) == MEM
7389 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
7391 if (TARGET_PCREL) return \"bsr.l %o1\";
7394 return \"bsr.l %1\";
7397 return \"bsr.l %1@PLTPC\";
7399 return \"bsr %1@PLTPC\";
7404 return \"bsr.l %1\";
7406 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC
7407 GAS just plain ignores it. FIXME: Not anymore, gas doesn't! */
7408 return \"jbsr %1,a1\";
7415 ;; Call subroutine returning any type.
7417 (define_expand "untyped_call"
7418 [(parallel [(call (match_operand 0 "" "")
7420 (match_operand 1 "" "")
7421 (match_operand 2 "" "")])]
7422 "NEEDS_UNTYPED_CALL"
7427 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
7429 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7431 rtx set = XVECEXP (operands[2], 0, i);
7432 emit_move_insn (SET_DEST (set), SET_SRC (set));
7435 /* The optimizer does not know that the call sets the function value
7436 registers we stored in the result block. We avoid problems by
7437 claiming that all hard registers are used and clobbered at this
7439 emit_insn (gen_blockage ());
7444 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
7445 ;; all of memory. This blocks insns from being moved across this point.
7447 (define_insn "blockage"
7448 [(unspec_volatile [(const_int 0)] 0)]
7457 (define_insn "probe"
7462 operands[0] = plus_constant (stack_pointer_rtx, NEED_PROBE);
7463 return \"tstl %a0\";
7466 ;; Used for frameless functions which save no regs and allocate no locals.
7467 (define_insn "return"
7472 if (current_function_pops_args == 0)
7474 operands[0] = GEN_INT (current_function_pops_args);
7478 (define_insn "indirect_jump"
7479 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
7483 ;; This should not be used unless the add/sub insns can't be.
7486 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
7487 (match_operand:QI 1 "address_operand" "p"))]
7492 /* Recognize an insn that refers to a table of offsets. Such an insn will
7493 need to refer to a label on the insn. So output one. Use the
7494 label-number of the table of offsets to generate this label. This code,
7495 and similar code above, assumes that there will be at most one reference
7497 if (GET_CODE (operands[1]) == PLUS
7498 && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
7499 && GET_CODE (XEXP (operands[1], 0)) != PLUS)
7501 rtx labelref = XEXP (operands[1], 1);
7502 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
7504 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
7505 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
7507 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
7508 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
7509 #endif /* not SGS */
7510 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
7511 (*targetm.asm_out.internal_label) (asm_out_file, \"LI\",
7512 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
7513 #ifdef SGS_SWITCH_TABLES
7514 /* Set flag saying we need to define the symbol
7515 LD%n (with value L%n-LI%n) at the end of the switch table. */
7516 switch_table_difference_label_flag = 1;
7517 #endif /* SGS_SWITCH_TABLES */
7518 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
7520 #endif /* SGS_NO_LI */
7522 return \"lea %a1,%0\";
7525 ;; This is the first machine-dependent peephole optimization.
7526 ;; It is useful when a floating value is returned from a function call
7527 ;; and then is moved into an FP register.
7528 ;; But it is mainly intended to test the support for these optimizations.
7531 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
7532 (set (match_operand:DF 0 "register_operand" "=f")
7533 (match_operand:DF 1 "register_operand" "ad"))]
7534 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
7538 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7539 output_asm_insn (\"move%.l %1,%@\", xoperands);
7540 output_asm_insn (\"move%.l %1,%-\", operands);
7541 return \"fmove%.d %+,%0\";
7545 ;; Optimize a stack-adjust followed by a push of an argument.
7546 ;; This is said to happen frequently with -msoft-float
7547 ;; when there are consecutive library calls.
7550 [(set (reg:SI 15) (plus:SI (reg:SI 15)
7551 (match_operand:SI 0 "const_int_operand" "n")))
7552 (set (match_operand:SF 1 "push_operand" "=m")
7553 (match_operand:SF 2 "general_operand" "rmfF"))]
7554 "INTVAL (operands[0]) >= 4
7555 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
7558 if (INTVAL (operands[0]) > 4)
7561 xoperands[0] = stack_pointer_rtx;
7562 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
7564 if (INTVAL (xoperands[1]) <= 8)
7567 output_asm_insn (\"addq%.w %1,%0\", xoperands);
7569 output_asm_insn (\"addq%.l %1,%0\", xoperands);
7571 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
7573 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
7574 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
7578 if (INTVAL (xoperands[1]) <= 0x7FFF)
7581 output_asm_insn (\"add%.w %1,%0\", xoperands);
7584 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
7586 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
7590 output_asm_insn (\"add%.l %1,%0\", xoperands);
7592 if (FP_REG_P (operands[2]))
7593 return \"fmove%.s %2,%@\";
7594 return \"move%.l %2,%@\";
7597 ;; Speed up stack adjust followed by a fullword fixedpoint push.
7600 [(set (reg:SI 15) (plus:SI (reg:SI 15)
7601 (match_operand:SI 0 "const_int_operand" "n")))
7602 (set (match_operand:SI 1 "push_operand" "=m")
7603 (match_operand:SI 2 "general_operand" "g"))]
7604 "INTVAL (operands[0]) >= 4
7605 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
7608 if (INTVAL (operands[0]) > 4)
7611 xoperands[0] = stack_pointer_rtx;
7612 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
7614 if (INTVAL (xoperands[1]) <= 8)
7617 output_asm_insn (\"addq%.w %1,%0\", xoperands);
7619 output_asm_insn (\"addq%.l %1,%0\", xoperands);
7621 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
7623 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
7624 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
7628 if (INTVAL (xoperands[1]) <= 0x7FFF)
7631 output_asm_insn (\"add%.w %1,%0\", xoperands);
7635 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
7637 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
7642 output_asm_insn (\"add%.l %1,%0\", xoperands);
7644 if (operands[2] == const0_rtx)
7645 return \"clr%.l %@\";
7646 return \"move%.l %2,%@\";
7649 ;; Speed up pushing a single byte but leaving four bytes of space.
7652 [(set (mem:QI (pre_dec:SI (reg:SI 15)))
7653 (match_operand:QI 1 "general_operand" "dami"))
7654 (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))]
7655 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
7660 if (GET_CODE (operands[1]) == REG)
7661 return \"move%.l %1,%-\";
7663 xoperands[1] = operands[1];
7665 = gen_rtx_MEM (QImode, plus_constant (stack_pointer_rtx, 3));
7666 xoperands[3] = stack_pointer_rtx;
7668 output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
7670 output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands);
7675 [(set (match_operand:SI 0 "register_operand" "=d")
7677 (set (strict_low_part (subreg:HI (match_dup 0) 2))
7678 (match_operand:HI 1 "general_operand" "rmn"))]
7679 "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
7682 if (GET_CODE (operands[1]) == CONST_INT)
7684 if (operands[1] == const0_rtx
7685 && (DATA_REG_P (operands[0])
7686 || GET_CODE (operands[0]) == MEM)
7687 /* clr insns on 68000 read before writing.
7688 This isn't so on the 68010, but we have no TARGET_68010. */
7689 && ((TARGET_68020 || TARGET_5200)
7690 || !(GET_CODE (operands[0]) == MEM
7691 && MEM_VOLATILE_P (operands[0]))))
7692 return \"clr%.w %0\";
7694 return \"move%.w %1,%0\";
7702 ;; jCC label ; abnormal loop termination
7703 ;; dbra dN, loop ; normal loop termination
7711 ;; Which moves the jCC condition outside the inner loop for free.
7715 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7716 [(cc0) (const_int 0)])
7717 (label_ref (match_operand 2 "" ""))
7722 (ne (match_operand:HI 0 "register_operand" "")
7724 (label_ref (match_operand 1 "" ""))
7727 (plus:HI (match_dup 0)
7729 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7733 output_dbcc_and_branch (operands);
7738 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7739 [(cc0) (const_int 0)])
7740 (label_ref (match_operand 2 "" ""))
7745 (ne (match_operand:SI 0 "register_operand" "")
7747 (label_ref (match_operand 1 "" ""))
7750 (plus:SI (match_dup 0)
7752 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7756 output_dbcc_and_branch (operands);
7761 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7762 [(cc0) (const_int 0)])
7763 (label_ref (match_operand 2 "" ""))
7768 (ge (plus:HI (match_operand:HI 0 "register_operand" "")
7771 (label_ref (match_operand 1 "" ""))
7774 (plus:HI (match_dup 0)
7776 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7780 output_dbcc_and_branch (operands);
7785 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7786 [(cc0) (const_int 0)])
7787 (label_ref (match_operand 2 "" ""))
7792 (ge (plus:SI (match_operand:SI 0 "register_operand" "")
7795 (label_ref (match_operand 1 "" ""))
7798 (plus:SI (match_dup 0)
7800 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7804 output_dbcc_and_branch (operands);
7809 ;; FPA multiply and add.
7811 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7812 (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%x,dmF,y")
7813 (match_operand:DF 2 "general_operand" "xH,y,y"))
7814 (match_operand:DF 3 "general_operand" "xH,y,dmF")))]
7817 fpma%.d %1,%w2,%w3,%0
7818 fpma%.d %x1,%x2,%x3,%0
7819 fpma%.d %x1,%x2,%x3,%0")
7822 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7823 (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%x,ydmF,y")
7824 (match_operand:SF 2 "general_operand" "xH,y,ydmF"))
7825 (match_operand:SF 3 "general_operand" "xH,ydmF,ydmF")))]
7828 fpma%.s %1,%w2,%w3,%0
7830 fpma%.s %1,%2,%3,%0")
7832 ;; FPA Multiply and subtract
7834 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7835 (minus:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
7836 (mult:DF (match_operand:DF 2 "general_operand" "%xH,y,y")
7837 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
7840 fpms%.d %3,%w2,%w1,%0
7841 fpms%.d %x3,%2,%x1,%0
7842 fpms%.d %x3,%2,%x1,%0")
7845 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7846 (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
7847 (mult:SF (match_operand:SF 2 "general_operand" "%xH,rmF,y")
7848 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
7851 fpms%.s %3,%w2,%w1,%0
7853 fpms%.s %3,%2,%1,%0")
7856 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7857 (minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
7858 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7859 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7862 fpmr%.d %2,%w1,%w3,%0
7863 fpmr%.d %x2,%1,%x3,%0
7864 fpmr%.d %x2,%1,%x3,%0")
7867 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7868 (minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
7869 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7870 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7873 fpmr%.s %2,%w1,%w3,%0
7874 fpmr%.s %x2,%1,%x3,%0
7875 fpmr%.s %x2,%1,%x3,%0")
7877 ;; FPA Add and multiply
7879 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7880 (mult:DF (plus:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
7881 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7882 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7885 fpam%.d %2,%w1,%w3,%0
7886 fpam%.d %x2,%1,%x3,%0
7887 fpam%.d %x2,%1,%x3,%0")
7890 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7891 (mult:SF (plus:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
7892 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7893 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7896 fpam%.s %2,%w1,%w3,%0
7897 fpam%.s %x2,%1,%x3,%0
7898 fpam%.s %x2,%1,%x3,%0")
7900 ;;FPA Subtract and multiply
7902 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7903 (mult:DF (minus:DF (match_operand:DF 1 "general_operand" "xH,y,y")
7904 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7905 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7908 fpsm%.d %2,%w1,%w3,%0
7909 fpsm%.d %x2,%1,%x3,%0
7910 fpsm%.d %x2,%1,%x3,%0")
7913 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7914 (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
7915 (minus:DF (match_operand:DF 2 "general_operand" "xH,y,y")
7916 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
7919 fpsm%.d %3,%w2,%w1,%0
7920 fpsm%.d %x3,%2,%x1,%0
7921 fpsm%.d %x3,%2,%x1,%0")
7924 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7925 (mult:SF (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,y")
7926 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7927 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7930 fpsm%.s %2,%w1,%w3,%0
7931 fpsm%.s %x2,%1,%x3,%0
7932 fpsm%.s %x2,%1,%x3,%0")
7935 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7936 (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
7937 (minus:SF (match_operand:SF 2 "general_operand" "xH,rmF,y")
7938 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
7941 fpsm%.s %3,%w2,%w1,%0
7942 fpsm%.s %x3,%2,%x1,%0
7943 fpsm%.s %x3,%2,%x1,%0")
7945 (define_expand "tstxf"
7947 (match_operand:XF 0 "nonimmediate_operand" ""))]
7949 "m68k_last_compare_had_fp_operands = 1;")
7953 (match_operand:XF 0 "nonimmediate_operand" "fm"))]
7957 cc_status.flags = CC_IN_68881;
7958 return \"ftst%.x %0\";
7961 (define_expand "cmpxf"
7963 (compare (match_operand:XF 0 "nonimmediate_operand" "")
7964 (match_operand:XF 1 "nonimmediate_operand" "")))]
7966 "m68k_last_compare_had_fp_operands = 1;")
7970 (compare (match_operand:XF 0 "nonimmediate_operand" "f,m")
7971 (match_operand:XF 1 "nonimmediate_operand" "fm,f")))]
7975 cc_status.flags = CC_IN_68881;
7976 #ifdef SGS_CMP_ORDER
7977 if (REG_P (operands[0]))
7979 if (REG_P (operands[1]))
7980 return \"fcmp%.x %0,%1\";
7982 return \"fcmp%.x %0,%f1\";
7984 cc_status.flags |= CC_REVERSED;
7985 return \"fcmp%.x %1,%f0\";
7987 if (REG_P (operands[0]))
7989 if (REG_P (operands[1]))
7990 return \"fcmp%.x %1,%0\";
7992 return \"fcmp%.x %f1,%0\";
7994 cc_status.flags |= CC_REVERSED;
7995 return \"fcmp%.x %f0,%1\";
7999 (define_insn "extendsfxf2"
8000 [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f")
8001 (float_extend:XF (match_operand:SF 1 "general_operand" "f,rmF")))]
8005 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
8007 if (REGNO (operands[0]) == REGNO (operands[1]))
8009 /* Extending float to double in an fp-reg is a no-op.
8010 NOTICE_UPDATE_CC has already assumed that the
8011 cc will be set. So cancel what it did. */
8012 cc_status = cc_prev_status;
8015 return \"f%$move%.x %1,%0\";
8017 if (FP_REG_P (operands[0]))
8019 if (FP_REG_P (operands[1]))
8020 return \"f%$move%.x %1,%0\";
8021 else if (ADDRESS_REG_P (operands[1]))
8022 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
8023 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
8024 return output_move_const_single (operands);
8025 return \"f%$move%.s %f1,%0\";
8027 return \"fmove%.x %f1,%0\";
8031 (define_insn "extenddfxf2"
8032 [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f")
8034 (match_operand:DF 1 "general_operand" "f,rmE")))]
8038 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
8040 if (REGNO (operands[0]) == REGNO (operands[1]))
8042 /* Extending float to double in an fp-reg is a no-op.
8043 NOTICE_UPDATE_CC has already assumed that the
8044 cc will be set. So cancel what it did. */
8045 cc_status = cc_prev_status;
8048 return \"fmove%.x %1,%0\";
8050 if (FP_REG_P (operands[0]))
8052 if (REG_P (operands[1]))
8055 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
8056 output_asm_insn (\"move%.l %1,%-\", xoperands);
8057 output_asm_insn (\"move%.l %1,%-\", operands);
8058 return \"f%&move%.d %+,%0\";
8060 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8061 return output_move_const_double (operands);
8062 return \"f%&move%.d %f1,%0\";
8064 return \"fmove%.x %f1,%0\";
8067 (define_insn "truncxfdf2"
8068 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,!r")
8070 (match_operand:XF 1 "general_operand" "f,f")))]
8074 if (REG_P (operands[0]))
8076 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
8077 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
8078 return \"move%.l %+,%0\";
8080 return \"fmove%.d %f1,%0\";
8083 (define_insn "truncxfsf2"
8084 [(set (match_operand:SF 0 "nonimmediate_operand" "=dm")
8086 (match_operand:XF 1 "general_operand" "f")))]
8090 (define_insn "floatsixf2"
8091 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
8092 (float:XF (match_operand:SI 1 "general_operand" "dmi")))]
8096 (define_insn "floathixf2"
8097 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
8098 (float:XF (match_operand:HI 1 "general_operand" "dmn")))]
8102 (define_insn "floatqixf2"
8103 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
8104 (float:XF (match_operand:QI 1 "general_operand" "dmn")))]
8108 (define_insn "ftruncxf2"
8109 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
8110 (fix:XF (match_operand:XF 1 "general_operand" "fFm")))]
8114 if (FP_REG_P (operands[1]))
8115 return \"fintrz%.x %f1,%0\";
8116 return \"fintrz%.x %f1,%0\";
8119 (define_insn "fixxfqi2"
8120 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
8121 (fix:QI (match_operand:XF 1 "general_operand" "f")))]
8125 (define_insn "fixxfhi2"
8126 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
8127 (fix:HI (match_operand:XF 1 "general_operand" "f")))]
8131 (define_insn "fixxfsi2"
8132 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
8133 (fix:SI (match_operand:XF 1 "general_operand" "f")))]
8138 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
8139 (plus:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
8140 (match_operand:XF 1 "nonimmediate_operand" "0")))]
8145 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
8146 (plus:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
8147 (match_operand:XF 1 "nonimmediate_operand" "0")))]
8152 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
8153 (plus:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
8154 (match_operand:XF 1 "general_operand" "0")))]
8158 (define_insn "addxf3"
8159 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
8160 (plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
8161 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
8165 if (REG_P (operands[2]))
8166 return \"fadd%.x %2,%0\";
8167 return \"fadd%.x %f2,%0\";
8171 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
8172 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
8173 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
8178 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
8179 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
8180 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
8185 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
8186 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
8187 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
8191 (define_insn "subxf3"
8192 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
8193 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
8194 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
8198 if (REG_P (operands[2]))
8199 return \"fsub%.x %2,%0\";
8200 return \"fsub%.x %f2,%0\";
8204 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
8205 (mult:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
8206 (match_operand:XF 1 "nonimmediate_operand" "0")))]
8211 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
8212 (mult:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
8213 (match_operand:XF 1 "nonimmediate_operand" "0")))]
8218 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
8219 (mult:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
8220 (match_operand:XF 1 "nonimmediate_operand" "0")))]
8224 (define_insn "mulxf3"
8225 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
8226 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
8227 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
8231 if (REG_P (operands[2]))
8232 return \"fmul%.x %2,%0\";
8233 return \"fmul%.x %f2,%0\";
8237 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
8238 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
8239 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
8244 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
8245 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
8246 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
8251 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
8252 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
8253 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
8257 (define_insn "divxf3"
8258 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
8259 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
8260 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
8264 if (REG_P (operands[2]))
8265 return \"fdiv%.x %2,%0\";
8266 return \"fdiv%.x %f2,%0\";
8269 (define_expand "negxf2"
8270 [(set (match_operand:XF 0 "nonimmediate_operand" "")
8271 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
8275 /* ??? There isn't an FPA define_insn so we could handle it here too.
8276 For now we don't (paranoia). */
8284 target = operand_subword (operands[0], 0, 1, XFmode);
8285 result = expand_binop (SImode, xor_optab,
8286 operand_subword_force (operands[1], 0, XFmode),
8287 GEN_INT (0x80000000), target, 0, OPTAB_WIDEN);
8291 if (result != target)
8292 emit_move_insn (result, target);
8294 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
8295 operand_subword_force (operands[1], 1, XFmode));
8296 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
8297 operand_subword_force (operands[1], 2, XFmode));
8299 insns = get_insns ();
8302 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
8307 (define_insn "negxf2_68881"
8308 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
8309 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
8313 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
8314 return \"fneg%.x %1,%0\";
8315 return \"fneg%.x %f1,%0\";
8318 (define_expand "absxf2"
8319 [(set (match_operand:XF 0 "nonimmediate_operand" "")
8320 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
8324 /* ??? There isn't an FPA define_insn so we could handle it here too.
8325 For now we don't (paranoia). */
8333 target = operand_subword (operands[0], 0, 1, XFmode);
8334 result = expand_binop (SImode, and_optab,
8335 operand_subword_force (operands[1], 0, XFmode),
8336 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
8340 if (result != target)
8341 emit_move_insn (result, target);
8343 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
8344 operand_subword_force (operands[1], 1, XFmode));
8345 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
8346 operand_subword_force (operands[1], 2, XFmode));
8348 insns = get_insns ();
8351 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
8356 (define_insn "absxf2_68881"
8357 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
8358 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
8362 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
8363 return \"fabs%.x %1,%0\";
8364 return \"fabs%.x %f1,%0\";
8367 (define_insn "sqrtxf2"
8368 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
8369 (sqrt:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
8373 (define_insn "sinsf2"
8374 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
8375 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 1))]
8376 "TARGET_68881 && flag_unsafe_math_optimizations"
8379 if (FP_REG_P (operands[1]))
8380 return \"fsin%.x %1,%0\";
8382 return \"fsin%.s %1,%0\";
8385 (define_insn "sindf2"
8386 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
8387 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 1))]
8388 "TARGET_68881 && flag_unsafe_math_optimizations"
8391 if (FP_REG_P (operands[1]))
8392 return \"fsin%.x %1,%0\";
8394 return \"fsin%.d %1,%0\";
8397 (define_insn "sinxf2"
8398 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
8399 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 1))]
8400 "TARGET_68881 && flag_unsafe_math_optimizations"
8403 (define_insn "cossf2"
8404 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
8405 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 2))]
8406 "TARGET_68881 && flag_unsafe_math_optimizations"
8409 if (FP_REG_P (operands[1]))
8410 return \"fcos%.x %1,%0\";
8412 return \"fcos%.s %1,%0\";
8415 (define_insn "cosdf2"
8416 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
8417 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 2))]
8418 "TARGET_68881 && flag_unsafe_math_optimizations"
8421 if (FP_REG_P (operands[1]))
8422 return \"fcos%.x %1,%0\";
8424 return \"fcos%.d %1,%0\";
8427 (define_insn "cosxf2"
8428 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
8429 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 2))]
8430 "TARGET_68881 && flag_unsafe_math_optimizations"
8434 [(trap_if (const_int -1) (const_int 7))]
8438 (define_insn "conditional_trap"
8439 [(trap_if (match_operator 0 "valid_dbcc_comparison_p"
8440 [(cc0) (const_int 0)])
8441 (match_operand:SI 1 "const_int_operand" "I"))]
8442 "TARGET_68020 && ! flags_in_68881 ()"
8445 switch (GET_CODE (operands[0]))
8447 case EQ: return \"trapeq\";
8448 case NE: return \"trapne\";
8449 case GT: return \"trapgt\";
8450 case GTU: return \"traphi\";
8451 case LT: return \"traplt\";
8452 case LTU: return \"trapcs\";
8453 case GE: return \"trapge\";
8454 case GEU: return \"trapcc\";
8455 case LE: return \"traple\";
8456 case LEU: return \"trapls\";