1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 88, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
4 ;; This file is part of GNU CC.
6 ;; GNU CC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GNU CC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GNU CC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
19 ;; Boston, MA 02111-1307, USA.
21 ;;- Information about MCF5200 port.
23 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
24 ;;- 68k ISA. Differences include reduced support for byte and word
25 ;;- operands and the removal of BCD, bitfield, rotate, and integer
26 ;;- divide instructions. The TARGET_5200 flag turns the use of the
27 ;;- removed opcodes and addressing modes off.
31 ;;- instruction definitions
33 ;;- @@The original PO technology requires these to be ordered by speed,
34 ;;- @@ so that assigner will pick the fastest.
36 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
38 ;;- When naming insn's (operand 0 of define_insn) be careful about using
39 ;;- names from other targets machine descriptions.
41 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
42 ;;- updates for most instructions.
44 ;;- Operand classes for the register allocator:
45 ;;- 'a' one of the address registers can be used.
46 ;;- 'd' one of the data registers can be used.
47 ;;- 'f' one of the m68881 registers can be used
48 ;;- 'r' either a data or an address register can be used.
49 ;;- 'x' if one of the Sun FPA registers
50 ;;- 'y' if one of the Low Sun FPA registers (fpa0-fpa15).
52 ;;- Immediate Floating point operator constraints
53 ;;- 'G' a floating point constant that is *NOT* one of the standard
54 ;; 68881 constant values (to force calling output_move_const_double
55 ;; to get it from rom if it is a 68881 constant).
56 ;;- 'H' one of the standard FPA constant values
58 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
61 ;;- Immediate integer operand constraints:
63 ;;- 'J' -32768 .. 32767
64 ;;- 'K' all integers EXCEPT -128 .. 127
66 ;;- 'M' all integers EXCEPT -256 .. 255
72 ;;- "%." size separator ("." or "") move%.l d0,d1
73 ;;- "%#" immediate separator ("#" or "") move%.l %#0,d0
74 ;;- "%-" push operand "sp@-" move%.l d0,%-
75 ;;- "%+" pop operand "sp@+" move%.l d0,%+
76 ;;- "%@" top of stack "sp@" move%.l d0,%@
77 ;;- "%!" fpcr register
78 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
79 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
82 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
83 ;; operand 1 is the argument for `sin'.
84 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
85 ;; operand 1 is the argument for `cos'.
87 ;;- Information about 68040 port.
89 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
90 ;;- be emulated in software by the OS. It is faster to avoid these
91 ;;- instructions and issue a library call rather than trapping into
92 ;;- the kernel. The affected instructions are fintrz and fscale. The
93 ;;- TARGET_68040 flag turns the use of the opcodes off.
95 ;;- The '040 also implements a set of new floating-point instructions
96 ;;- which specify the rounding precision in the opcode. This finally
97 ;;- permit the 68k series to be truly IEEE compliant, and solves all
98 ;;- issues of excess precision accumulating in the extended registers.
99 ;;- By default, GCC does not use these instructions, since such code will
100 ;;- not run on an '030. To use these instructions, use the -m68040-only
101 ;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY,
102 ;;- you can make these instructions the default.
104 ;;- These new instructions aren't directly in the md. They are brought
105 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
108 ;;- Information about 68060 port.
110 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
111 ;;- be emulated in software by the OS. It is faster to avoid these
112 ;;- instructions and issue a library call rather than trapping into
113 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
114 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
115 ;;- fscale. The TARGET_68060 flag turns the use of the opcodes off.
117 ;;- FPA port explanation:
119 ;;- Usage of the Sun FPA and the 68881 together
121 ;;- The current port of gcc to the sun fpa disallows use of the m68881
122 ;;- instructions completely if code is targeted for the fpa. This is
123 ;;- for the following reasons:
125 ;;- 1) Expressing the preference hierarchy (ie. use the fpa if you
126 ;;- can, the 68881 otherwise, and data registers only if you are
127 ;;- forced to it) is a bitch with the current constraint scheme,
128 ;;- especially since it would have to work for any combination of
131 ;;- 2) There are no instructions to move between the two types of
132 ;;- registers; the stack must be used as an intermediary.
134 ;;- It could indeed be done; I think the best way would be to have
135 ;;- separate patterns for TARGET_FPA (which implies a 68881),
136 ;;- TARGET_68881, and no floating point co-processor. Use
137 ;;- define_expands for all of the named instruction patterns, and
138 ;;- include code in the FPA instruction to deal with the 68881 with
139 ;;- preferences specifically set to favor the fpa. Some of this has
140 ;;- already been done:
142 ;;- 1) Separation of most of the patterns out into a TARGET_FPA
143 ;;- case and a TARGET_68881 case (the exceptions are the patterns
144 ;;- which would need one define_expand and three define_insn's under
145 ;;- it (with a lot of duplicate code between them) to replace the
146 ;;- current single define_insn. These are mov{[ds]f,[ds]i} and the
147 ;;- first two patterns in the md.
149 ;;- Some would still have to be done:
151 ;;- 1) Add code to the fpa patterns which correspond to 68881
152 ;;- patterns to deal with the 68881 case (including preferences!).
153 ;;- What you might actually do here is combine the fpa and 68881 code
154 ;;- back together into one pattern for those instructions where it's
155 ;;- absolutely necessary and save yourself some duplicate code. I'm
156 ;;- not completely sure as to whether you could get away with doing
157 ;;- this only for the mov* insns, or if you'd have to do it for all
159 ;;- 2) Add code to the mov{[ds]f,[ds]i} instructions to handle
160 ;;- moving between fpa regs and 68881 regs.
162 ;;- Since the fpa is more powerful than the 68881 and also has more
163 ;;- registers, and since I think the resultant md would be medium ugly
164 ;;- (lot's of duplicate code, ugly constraint strings), I elected not
165 ;;- to do this change.
167 ;;- Another reason why someone *might* want to do the change is to
168 ;;- control which register classes are accessed in a slightly cleaner
169 ;;- way than I have. See the blurb on CONDITIONAL_REGISTER_USAGE in
170 ;;- the internals manual.
172 ;;- Yet another reason why someone might want to do this change is to
173 ;;- allow use of some of the 68881 insns which have no equivalent on
174 ;;- the fpa. The sqrt instruction comes fairly quickly to mind.
176 ;;- If this is ever done, don't forget to change sun3.h so that
177 ;;- it *will* define __HAVE_68881__ when the FPA is in use.
179 ;;- Condition code hack
181 ;;- When a floating point compare is done in the fpa, the resulting
182 ;;- condition codes are left in the fpastatus register. The values in
183 ;;- this register must be moved into the 68000 cc register before any
184 ;;- jump is executed. Once this has been done, regular jump
185 ;;- instructions are fine (ie. floating point jumps are not necessary.
186 ;;- They are only done if the cc is in the 68881).
188 ;;- The instructions that move the fpastatus register to the 68000
189 ;;- register clobber a data register (the move cannot be done direct).
190 ;;- These instructions might be bundled either with the compare
191 ;;- instruction, or the branch instruction. If we were using both the
192 ;;- fpa and the 68881 together, we would wish to only mark the
193 ;;- register clobbered if we were doing the compare in the fpa, but I
194 ;;- think that that decision (whether to clobber the register or not)
195 ;;- must be done before register allocation (makes sense) and hence we
196 ;;- can't know if the floating point compare will be done in the fpa
197 ;;- or the fp. So whenever we are asked for code that uses the fpa,
198 ;;- we will mark a data register as clobbered. This is reasonable, as
199 ;;- almost all floating point compare operations done with fpa code
200 ;;- enabled will be done in the fpa. It's even more reasonable since
201 ;;- we decided to make the 68881 and the fpa mutually exclusive.
203 ;;- We place to code to move the fpastatus register inside of a
204 ;;- define_expand so that we can do it conditionally based on whether
205 ;;- we are targeting an fpa or not.
207 ;;- This still leaves us with the question of where we wish to put the
208 ;;- code to move the fpastatus reg. If we put it in the compare
209 ;;- instruction, we can restrict the clobbering of the register to
210 ;;- floating point compares, but we can't take advantage of floating
211 ;;- point subtracts & etc. that alter the fpastatus register. If we
212 ;;- put it in the branch instruction, all branches compiled with fpa
213 ;;- code enabled will clobber a data register, but we will be able to
214 ;;- take advantage of fpa subtracts. This balance favors putting the
215 ;;- code in with the compare instruction.
217 ;;- Note that if some enterprising hacker should decide to switch
218 ;;- this, he'll need to modify the code in NOTICE_UPDATE_CC.
220 ;;- Usage of the top 16 fpa registers
222 ;;- The only locations which we may transfer fpa registers 16-31 from
223 ;;- or to are the fpa registers 0-15. (68000 registers and memory
224 ;;- locations are impossible). This causes problems in gcc, which
225 ;;- assumes that mov?? instructions require no additional registers
226 ;;- (see section 11.7) and since floating point moves *must* be
227 ;;- supported into general registers (see section 12.3 under
228 ;;- HARD_REGNO_OK_FOR_MODE_P) from anywhere.
230 ;;- My solution was to reserve fpa0 for moves into or out of these top
231 ;;- 16 registers and to disparage the choice to reload into or out of
232 ;;- these registers as much as I could. That alternative is always
233 ;;- last in the list, so it will not be used unless all else fails. I
234 ;;- will note that according to my current information, sun's compiler
235 ;;- doesn't use these top 16 registers at all.
237 ;;- There is another possible way to do it. I *believe* that if you
238 ;;- make absolutely sure that the code will not be executed in the
239 ;;- reload pass, you can support the mov?? names with define_expands
240 ;;- which require new registers. This may be possible by the
241 ;;- appropriate juggling of constraints. I may come back to this later.
243 ;;- Usage of constant RAM
245 ;;- This has been handled correctly (I believe) but the way I've done
246 ;;- it could use a little explanation. The constant RAM can only be
247 ;;- accessed when the instruction is in "command register" mode.
248 ;;- "command register" mode means that no accessing of memory or the
249 ;;- 68000 registers is being done. This can be expressed easily in
250 ;;- constraints, so generally the mode of the instruction is
251 ;;- determined by a branch off of which_alternative. In outputting
252 ;;- instructions, a 'w' means to output an access to the constant ram
253 ;;- (if the arg is CONST_DOUBLE and is one of the available
254 ;;- constants), and 'x' means to output a register pair (if the arg is
255 ;;- a 68000 register) and a 'y' is the combination of the above two
256 ;;- processes. You use a 'y' in two operand DF instructions where you
257 ;;- *know* the other operand is an fpa register, you use an 'x' in DF
258 ;;- instructions where the arg might be a 68000 register and the
259 ;;- instruction is *not* in "command register" mode, and you use a 'w'
260 ;;- in two situations: 1) The instruction *is* in command register
261 ;;- mode (and hence won't be accessing 68000 registers), or 2) The
262 ;;- instruction is a two operand SF instruction where you know the
263 ;;- other operand is an fpa register.
265 ;;- Optimization issues
267 ;;- I actually think that I've included all of the fpa instructions
268 ;;- that should be included. Note that if someone is interested in
269 ;;- doing serious floating point work on the sun fpa, I would advise
270 ;;- the use of the "asm" instruction in gcc to allow you to use the
271 ;;- sin, cos, and exponential functions on the fpa board.
273 ;;- END FPA Explanation Section.
276 ;;- Some of these insn's are composites of several m68000 op codes.
277 ;;- The assembler (or final @@??) insures that the appropriate one is
281 [(set (match_operand:DF 0 "push_operand" "=m")
282 (match_operand:DF 1 "general_operand" "ro<>fyE"))]
286 if (FP_REG_P (operands[1]))
287 return \"fmove%.d %f1,%0\";
288 if (FPA_REG_P (operands[1]))
289 return \"fpmove%.d %1, %x0\";
290 return output_move_double (operands);
293 (define_insn "pushdi"
294 [(set (match_operand:DI 0 "push_operand" "=m")
295 (match_operand:DI 1 "general_operand" "ro<>Fyi"))]
299 return output_move_double (operands);
302 ;; We don't want to allow a constant operand for test insns because
303 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
304 ;; be folded while optimizing anyway.
306 (define_expand "tstdi"
307 [(parallel [(set (cc0)
308 (match_operand:DI 0 "nonimmediate_operand" ""))
309 (clobber (match_scratch:SI 1 ""))
310 (clobber (match_scratch:DI 2 ""))])]
312 "m68k_last_compare_had_fp_operands = 0;")
316 (match_operand:DI 0 "nonimmediate_operand" "am,d"))
317 (clobber (match_scratch:SI 1 "=X,d"))
318 (clobber (match_scratch:DI 2 "=d,X"))]
322 if (which_alternative == 0)
326 xoperands[0] = operands[2];
327 xoperands[1] = operands[0];
328 output_move_double (xoperands);
329 cc_status.flags |= CC_REVERSED;
330 return \"neg%.l %R2\;negx%.l %2\";
332 if (find_reg_note (insn, REG_DEAD, operands[0]))
334 cc_status.flags |= CC_REVERSED;
335 return \"neg%.l %R0\;negx%.l %0\";
339 ** 'sub' clears %1, and also clears the X cc bit
340 ** 'tst' sets the Z cc bit according to the low part of the DImode operand
341 ** 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part
343 return \"sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0\";
346 (define_expand "tstsi"
348 (match_operand:SI 0 "nonimmediate_operand" ""))]
350 "m68k_last_compare_had_fp_operands = 0;")
354 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
359 /* ISI's assembler fails to handle tstl a0. */
360 if (! ADDRESS_REG_P (operands[0]))
362 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
364 return \"tst%.l %0\";
365 /* If you think that the 68020 does not support tstl a0,
366 reread page B-167 of the 68020 manual more carefully. */
367 /* On an address reg, cmpw may replace cmpl. */
369 return \"cmp%.w %0,%#0\";
371 return \"cmp%.w %#0,%0\";
375 ;; This can't use an address register, because comparisons
376 ;; with address registers as second operand always test the whole word.
377 (define_expand "tsthi"
379 (match_operand:HI 0 "nonimmediate_operand" ""))]
381 "m68k_last_compare_had_fp_operands = 0;")
385 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
389 (define_expand "tstqi"
391 (match_operand:QI 0 "nonimmediate_operand" ""))]
393 "m68k_last_compare_had_fp_operands = 0;")
397 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
401 (define_expand "tstsf"
403 (match_operand:SF 0 "general_operand" ""))]
404 "TARGET_68881 || TARGET_FPA"
407 m68k_last_compare_had_fp_operands = 1;
410 emit_insn (gen_tstsf_fpa (operands[0]));
415 (define_insn "tstsf_fpa"
417 (match_operand:SF 0 "general_operand" "xmdF"))
418 (clobber (match_scratch:SI 1 "=d"))]
420 "fptst%.s %x0\;fpmove fpastatus,%1\;movw %1,cc")
424 (match_operand:SF 0 "general_operand" "fdm"))]
428 cc_status.flags = CC_IN_68881;
429 if (FP_REG_P (operands[0]))
430 return \"ftst%.x %0\";
431 return \"ftst%.s %0\";
434 (define_expand "tstdf"
436 (match_operand:DF 0 "general_operand" ""))]
437 "TARGET_68881 || TARGET_FPA"
440 m68k_last_compare_had_fp_operands = 1;
443 emit_insn (gen_tstsf_fpa (operands[0]));
448 (define_insn "tstdf_fpa"
450 (match_operand:DF 0 "general_operand" "xrmF"))
451 (clobber (match_scratch:SI 1 "=d"))]
453 "fptst%.d %x0\;fpmove fpastatus,%1\;movw %1,cc")
457 (match_operand:DF 0 "general_operand" "fm"))]
461 cc_status.flags = CC_IN_68881;
462 if (FP_REG_P (operands[0]))
463 return \"ftst%.x %0\";
464 return \"ftst%.d %0\";
467 ;; compare instructions.
469 (define_expand "cmpdi"
472 (compare (match_operand:DI 0 "nonimmediate_operand" "")
473 (match_operand:DI 1 "general_operand" "")))
474 (clobber (match_dup 2))])]
476 "m68k_last_compare_had_fp_operands = 0; operands[2] = gen_reg_rtx (DImode);")
480 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
481 (match_operand:DI 2 "general_operand" "d,0")))
482 (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
486 if (rtx_equal_p (operands[0], operands[1]))
487 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
490 cc_status.flags |= CC_REVERSED;
491 return \"sub%.l %R1,%R0\;subx%.l %1,%0\";
495 ;; This is the second "hook" for PIC code (in addition to movsi). See
496 ;; comment of movsi for a description of PIC handling.
497 (define_expand "cmpsi"
499 (compare (match_operand:SI 0 "nonimmediate_operand" "")
500 (match_operand:SI 1 "general_operand" "")))]
504 m68k_last_compare_had_fp_operands = 0;
505 if (flag_pic && symbolic_operand (operands[1], SImode))
507 /* The source is an address which requires PIC relocation.
508 Call legitimize_pic_address with the source, mode, and a relocation
509 register (a new pseudo, or the final destination if reload_in_progress
510 is set). Then fall through normally */
511 extern rtx legitimize_pic_address();
512 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
513 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
517 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
520 (compare (match_operand:SI 0 "nonimmediate_operand" "rKs,mr,>")
521 (match_operand:SI 1 "general_operand" "mr,rKs,>")))]
525 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
527 return \"cmpm%.l %0,%1\";
529 return \"cmpm%.l %1,%0\";
531 if (REG_P (operands[1])
532 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
533 { cc_status.flags |= CC_REVERSED;
535 return \"cmp%.l %d1,%d0\";
537 return \"cmp%.l %d0,%d1\";
541 return \"cmp%.l %d0,%d1\";
543 return \"cmp%.l %d1,%d0\";
549 (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
550 (match_operand:SI 1 "general_operand" "r,mrKs")))]
554 if (REG_P (operands[1])
555 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
556 { cc_status.flags |= CC_REVERSED;
558 return \"cmp%.l %d1,%d0\";
560 return \"cmp%.l %d0,%d1\";
564 return \"cmp%.l %d0,%d1\";
566 return \"cmp%.l %d1,%d0\";
570 (define_expand "cmphi"
572 (compare (match_operand:HI 0 "nonimmediate_operand" "")
573 (match_operand:HI 1 "general_operand" "")))]
575 "m68k_last_compare_had_fp_operands = 0;")
579 (compare (match_operand:HI 0 "nonimmediate_operand" "rnm,d,n,m,>")
580 (match_operand:HI 1 "general_operand" "d,rnm,m,n,>")))]
584 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
586 return \"cmpm%.w %0,%1\";
588 return \"cmpm%.w %1,%0\";
590 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
591 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
592 { cc_status.flags |= CC_REVERSED;
594 return \"cmp%.w %d1,%d0\";
596 return \"cmp%.w %d0,%d1\";
600 return \"cmp%.w %d0,%d1\";
602 return \"cmp%.w %d1,%d0\";
606 (define_expand "cmpqi"
608 (compare (match_operand:QI 0 "nonimmediate_operand" "")
609 (match_operand:QI 1 "general_operand" "")))]
611 "m68k_last_compare_had_fp_operands = 0;")
615 (compare (match_operand:QI 0 "nonimmediate_operand" "dn,md,>")
616 (match_operand:QI 1 "general_operand" "dm,nd,>")))]
620 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
622 return \"cmpm%.b %0,%1\";
624 return \"cmpm%.b %1,%0\";
626 if (REG_P (operands[1])
627 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
628 { cc_status.flags |= CC_REVERSED;
630 return \"cmp%.b %d1,%d0\";
632 return \"cmp%.b %d0,%d1\";
636 return \"cmp%.b %d0,%d1\";
638 return \"cmp%.b %d1,%d0\";
642 (define_expand "cmpdf"
644 (compare (match_operand:DF 0 "general_operand" "")
645 (match_operand:DF 1 "general_operand" "")))]
646 "TARGET_68881 || TARGET_FPA"
649 m68k_last_compare_had_fp_operands = 1;
652 emit_insn (gen_cmpdf_fpa (operands[0], operands[1]));
657 (define_insn "cmpdf_fpa"
659 (compare (match_operand:DF 0 "general_operand" "x,y")
660 (match_operand:DF 1 "general_operand" "xH,rmF")))
661 (clobber (match_scratch:SI 2 "=d,d"))]
663 "fpcmp%.d %y1,%0\;fpmove fpastatus,%2\;movw %2,cc")
667 (compare (match_operand:DF 0 "general_operand" "f,mG")
668 (match_operand:DF 1 "general_operand" "fmG,f")))]
672 cc_status.flags = CC_IN_68881;
674 if (REG_P (operands[0]))
676 if (REG_P (operands[1]))
677 return \"fcmp%.x %0,%1\";
679 return \"fcmp%.d %0,%f1\";
681 cc_status.flags |= CC_REVERSED;
682 return \"fcmp%.d %1,%f0\";
684 if (REG_P (operands[0]))
686 if (REG_P (operands[1]))
687 return \"fcmp%.x %1,%0\";
689 return \"fcmp%.d %f1,%0\";
691 cc_status.flags |= CC_REVERSED;
692 return \"fcmp%.d %f0,%1\";
696 (define_expand "cmpsf"
698 (compare (match_operand:SF 0 "general_operand" "")
699 (match_operand:SF 1 "general_operand" "")))]
700 "TARGET_68881 || TARGET_FPA"
703 m68k_last_compare_had_fp_operands = 1;
706 emit_insn (gen_cmpsf_fpa (operands[0], operands[1]));
711 (define_insn "cmpsf_fpa"
713 (compare (match_operand:SF 0 "general_operand" "x,y")
714 (match_operand:SF 1 "general_operand" "xH,rmF")))
715 (clobber (match_scratch:SI 2 "=d,d"))]
717 "fpcmp%.s %w1,%x0\;fpmove fpastatus,%2\;movw %2,cc")
721 (compare (match_operand:SF 0 "general_operand" "f,mdG")
722 (match_operand:SF 1 "general_operand" "fmdG,f")))]
726 cc_status.flags = CC_IN_68881;
728 if (FP_REG_P (operands[0]))
730 if (FP_REG_P (operands[1]))
731 return \"fcmp%.x %0,%1\";
733 return \"fcmp%.s %0,%f1\";
735 cc_status.flags |= CC_REVERSED;
736 return \"fcmp%.s %1,%f0\";
738 if (FP_REG_P (operands[0]))
740 if (FP_REG_P (operands[1]))
741 return \"fcmp%.x %1,%0\";
743 return \"fcmp%.s %f1,%0\";
745 cc_status.flags |= CC_REVERSED;
746 return \"fcmp%.s %f0,%1\";
750 ;; Recognizers for btst instructions.
752 ;; Coldfire/5200 only allows "<Q>" type addresses when the bit position is
753 ;; specified as a constant, so we must disable all patterns that may extract
754 ;; from a MEM at a constant bit position if we can't use this as a constraint.
757 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
759 (minus:SI (const_int 7)
760 (match_operand:SI 1 "general_operand" "di"))))]
762 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
764 ;; This is the same as the above pattern except for the constraints. The 'i'
768 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
770 (minus:SI (const_int 7)
771 (match_operand:SI 1 "general_operand" "d"))))]
773 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
776 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
778 (minus:SI (const_int 31)
779 (match_operand:SI 1 "general_operand" "di"))))]
781 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
783 ;; The following two patterns are like the previous two
784 ;; except that they use the fact that bit-number operands
785 ;; are automatically masked to 3 or 5 bits.
788 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
790 (minus:SI (const_int 7)
792 (match_operand:SI 1 "register_operand" "d")
795 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
798 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
800 (minus:SI (const_int 31)
802 (match_operand:SI 1 "register_operand" "d")
805 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
807 ;; Nonoffsettable mem refs are ok in this one pattern
808 ;; since we don't try to adjust them.
810 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
812 (match_operand:SI 1 "const_int_operand" "n")))]
813 "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_5200"
816 operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1]));
817 return output_btst (operands, operands[1], operands[0], insn, 7);
821 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
823 (match_operand:SI 1 "const_int_operand" "n")))]
827 if (GET_CODE (operands[0]) == MEM)
829 operands[0] = adj_offsettable_operand (operands[0],
830 INTVAL (operands[1]) / 8);
831 operands[1] = gen_rtx (CONST_INT, VOIDmode,
832 7 - INTVAL (operands[1]) % 8);
833 return output_btst (operands, operands[1], operands[0], insn, 7);
835 operands[1] = gen_rtx (CONST_INT, VOIDmode,
836 31 - INTVAL (operands[1]));
837 return output_btst (operands, operands[1], operands[0], insn, 31);
840 ;; This is the same as the above pattern except for the constraints.
841 ;; The 'o' has been replaced with 'Q'.
844 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ")
846 (match_operand:SI 1 "const_int_operand" "n")))]
850 if (GET_CODE (operands[0]) == MEM)
852 operands[0] = adj_offsettable_operand (operands[0],
853 INTVAL (operands[1]) / 8);
854 operands[1] = gen_rtx (CONST_INT, VOIDmode,
855 7 - INTVAL (operands[1]) % 8);
856 return output_btst (operands, operands[1], operands[0], insn, 7);
858 operands[1] = gen_rtx (CONST_INT, VOIDmode,
859 31 - INTVAL (operands[1]));
860 return output_btst (operands, operands[1], operands[0], insn, 31);
866 ;; A special case in which it is not desirable
867 ;; to reload the constant into a data register.
868 (define_insn "pushexthisi_const"
869 [(set (match_operand:SI 0 "push_operand" "=m")
870 (match_operand:SI 1 "const_int_operand" "J"))]
871 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
874 if (operands[1] == const0_rtx)
875 return \"clr%.l %0\";
880 ;(define_insn "swapsi"
881 ; [(set (match_operand:SI 0 "general_operand" "+r")
882 ; (match_operand:SI 1 "general_operand" "+r"))
883 ; (set (match_dup 1) (match_dup 0))]
887 ;; Special case of fullword move when source is zero.
888 ;; The reason this is special is to avoid loading a zero
889 ;; into a data reg with moveq in order to store it elsewhere.
891 (define_insn "movsi_const0"
892 [(set (match_operand:SI 0 "general_operand" "=g")
894 ;; clr insns on 68000 read before writing.
895 ;; This isn't so on the 68010, but we have no TARGET_68010.
896 "((TARGET_68020 || TARGET_5200)
897 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
900 if (ADDRESS_REG_P (operands[0]))
902 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
903 if (!TARGET_68040 && !TARGET_68060)
904 return \"sub%.l %0,%0\";
909 /* Many SGS assemblers croak on size specifiers for constants. */
912 return \"lea 0.w,%0\";
915 return \"lea 0:w,%0\";
919 /* moveq is faster on the 68000. */
920 if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_5200))
921 #if defined(MOTOROLA) && !defined(CRDS)
922 return \"moveq%.l %#0,%0\";
924 return \"moveq %#0,%0\";
926 return \"clr%.l %0\";
929 ;; General case of fullword move.
931 ;; This is the main "hook" for PIC code. When generating
932 ;; PIC, movsi is responsible for determining when the source address
933 ;; needs PIC relocation and appropriately calling legitimize_pic_address
934 ;; to perform the actual relocation.
936 ;; In both the PIC and non-PIC cases the patterns generated will
937 ;; matched by the next define_insn.
938 (define_expand "movsi"
939 [(set (match_operand:SI 0 "general_operand" "")
940 (match_operand:SI 1 "general_operand" ""))]
944 if (flag_pic && symbolic_operand (operands[1], SImode))
946 /* The source is an address which requires PIC relocation.
947 Call legitimize_pic_address with the source, mode, and a relocation
948 register (a new pseudo, or the final destination if reload_in_progress
949 is set). Then fall through normally */
950 extern rtx legitimize_pic_address();
951 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
952 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
956 ;; General case of fullword move. The register constraints
957 ;; force integer constants in range for a moveq to be reloaded
958 ;; if they are headed for memory.
960 ;; Notes: make sure no alternative allows g vs g.
961 ;; We don't allow f-regs since fixed point cannot go in them.
962 ;; We do allow y and x regs since fixed point is allowed in them.
963 [(set (match_operand:SI 0 "general_operand" "=g,da,y,!*x*r*m")
964 (match_operand:SI 1 "general_operand" "daymKs,i,g,*x*r*m"))]
968 if (which_alternative == 3)
969 return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\";
970 if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0]))
971 return \"fpmove%.l %x1,%x0\";
972 return output_move_simode (operands);
976 [(set (match_operand:SI 0 "general_operand" "=r<Q>,g")
977 (match_operand:SI 1 "general_operand" "g,r<Q>"))]
979 "* return output_move_simode (operands);")
981 (define_expand "movhi"
982 [(set (match_operand:HI 0 "general_operand" "")
983 (match_operand:HI 1 "general_operand" ""))]
988 [(set (match_operand:HI 0 "general_operand" "=g")
989 (match_operand:HI 1 "general_operand" "g"))]
991 "* return output_move_himode (operands);")
994 [(set (match_operand:HI 0 "general_operand" "=r<Q>,g")
995 (match_operand:HI 1 "general_operand" "g,r<Q>"))]
997 "* return output_move_himode (operands);")
999 (define_expand "movstricthi"
1000 [(set (strict_low_part (match_operand:HI 0 "general_operand" ""))
1001 (match_operand:HI 1 "general_operand" ""))]
1006 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
1007 (match_operand:HI 1 "general_operand" "rmn"))]
1009 "* return output_move_stricthi (operands);")
1012 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+d,m"))
1013 (match_operand:HI 1 "general_operand" "rmn,r"))]
1015 "* return output_move_stricthi (operands);")
1017 (define_expand "movqi"
1018 [(set (match_operand:QI 0 "general_operand" "")
1019 (match_operand:QI 1 "general_operand" ""))]
1024 [(set (match_operand:QI 0 "general_operand" "=d,*a,m")
1025 (match_operand:QI 1 "general_operand" "dmi*a,di*a,dmi"))]
1027 "* return output_move_qimode (operands);")
1030 [(set (match_operand:QI 0 "general_operand" "=d*a<Q>,d*am")
1031 (match_operand:QI 1 "general_operand" "d*ami,d*a<Q>"))]
1033 "* return output_move_qimode (operands);")
1035 (define_expand "movstrictqi"
1036 [(set (strict_low_part (match_operand:QI 0 "general_operand" ""))
1037 (match_operand:QI 1 "general_operand" ""))]
1042 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
1043 (match_operand:QI 1 "general_operand" "dmn"))]
1045 "* return output_move_strictqi (operands);")
1048 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+d,m"))
1049 (match_operand:QI 1 "general_operand" "dmn,d"))]
1051 "* return output_move_strictqi (operands);")
1053 (define_expand "movsf"
1054 [(set (match_operand:SF 0 "general_operand" "")
1055 (match_operand:SF 1 "general_operand" ""))]
1060 [(set (match_operand:SF 0 "general_operand" "=rmf,x,y,rm,!x,!rm")
1061 (match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))]
1062 ; [(set (match_operand:SF 0 "general_operand" "=rmf")
1063 ; (match_operand:SF 1 "general_operand" "rmfF"))]
1067 if (which_alternative >= 4)
1068 return \"fpmove%.s %1,fpa0\;fpmove%.s fpa0,%0\";
1069 if (FPA_REG_P (operands[0]))
1071 if (FPA_REG_P (operands[1]))
1072 return \"fpmove%.s %x1,%x0\";
1073 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1074 return output_move_const_single (operands);
1075 else if (FP_REG_P (operands[1]))
1076 return \"fmove%.s %1,sp@-\;fpmove%.d sp@+, %0\";
1077 return \"fpmove%.s %x1,%x0\";
1079 if (FPA_REG_P (operands[1]))
1081 if (FP_REG_P (operands[0]))
1082 return \"fpmove%.s %x1,sp@-\;fmove%.s sp@+,%0\";
1084 return \"fpmove%.s %x1,%x0\";
1086 if (FP_REG_P (operands[0]))
1088 if (FP_REG_P (operands[1]))
1089 return \"f%$move%.x %1,%0\";
1090 else if (ADDRESS_REG_P (operands[1]))
1091 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
1092 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1093 return output_move_const_single (operands);
1094 return \"f%$move%.s %f1,%0\";
1096 if (FP_REG_P (operands[1]))
1098 if (ADDRESS_REG_P (operands[0]))
1099 return \"fmove%.s %1,%-\;move%.l %+,%0\";
1100 return \"fmove%.s %f1,%0\";
1102 return \"move%.l %1,%0\";
1106 [(set (match_operand:SF 0 "general_operand" "=r,g")
1107 (match_operand:SF 1 "general_operand" "g,r"))]
1109 "* return \"move%.l %1,%0\";")
1111 (define_expand "movdf"
1112 [(set (match_operand:DF 0 "general_operand" "")
1113 (match_operand:DF 1 "general_operand" ""))]
1118 [(set (match_operand:DF 0 "general_operand" "=rm,rf,rf,&rof<>,y,rm,x,!x,!rm")
1119 (match_operand:DF 1 "general_operand" "rf,m,0,rofE<>,rmE,y,xH,rm,x"))]
1120 ; [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>")
1121 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
1125 if (which_alternative == 7)
1126 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1127 if (FPA_REG_P (operands[0]))
1129 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1130 return output_move_const_double (operands);
1131 if (FP_REG_P (operands[1]))
1132 return \"fmove%.d %1,sp@-\;fpmove%.d sp@+,%x0\";
1133 return \"fpmove%.d %x1,%x0\";
1135 else if (FPA_REG_P (operands[1]))
1137 if (FP_REG_P(operands[0]))
1138 return \"fpmove%.d %x1,sp@-\;fmoved sp@+,%0\";
1140 return \"fpmove%.d %x1,%x0\";
1142 if (FP_REG_P (operands[0]))
1144 if (FP_REG_P (operands[1]))
1145 return \"f%&move%.x %1,%0\";
1146 if (REG_P (operands[1]))
1149 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1150 output_asm_insn (\"move%.l %1,%-\", xoperands);
1151 output_asm_insn (\"move%.l %1,%-\", operands);
1152 return \"f%&move%.d %+,%0\";
1154 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1155 return output_move_const_double (operands);
1156 return \"f%&move%.d %f1,%0\";
1158 else if (FP_REG_P (operands[1]))
1160 if (REG_P (operands[0]))
1162 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1163 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1164 return \"move%.l %+,%0\";
1167 return \"fmove%.d %f1,%0\";
1169 return output_move_double (operands);
1173 [(set (match_operand:DF 0 "general_operand" "=r,g")
1174 (match_operand:DF 1 "general_operand" "g,r"))]
1176 "* return output_move_double (operands);")
1178 (define_expand "movxf"
1179 [(set (match_operand:XF 0 "nonimmediate_operand" "")
1180 (match_operand:XF 1 "general_operand" ""))]
1184 if (CONSTANT_P (operands[1]))
1186 operands[1] = force_const_mem (XFmode, operands[1]);
1187 if (! memory_address_p (XFmode, XEXP (operands[1], 0))
1188 && ! reload_in_progress)
1189 operands[1] = change_address (operands[1], XFmode,
1190 XEXP (operands[1], 0));
1195 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f")
1196 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r"))]
1200 if (FP_REG_P (operands[0]))
1202 if (FP_REG_P (operands[1]))
1203 return \"fmove%.x %1,%0\";
1204 if (REG_P (operands[1]))
1207 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
1208 output_asm_insn (\"move%.l %1,%-\", xoperands);
1209 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1210 output_asm_insn (\"move%.l %1,%-\", xoperands);
1211 output_asm_insn (\"move%.l %1,%-\", operands);
1212 return \"fmove%.x %+,%0\";
1214 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1215 return \"fmove%.x %1,%0\";
1216 return \"fmove%.x %f1,%0\";
1218 if (REG_P (operands[0]))
1220 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1221 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1222 output_asm_insn (\"move%.l %+,%0\", operands);
1223 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1224 return \"move%.l %+,%0\";
1226 return \"fmove%.x %f1,%0\";
1231 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1232 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1233 "! TARGET_68881 && ! TARGET_5200"
1236 if (FP_REG_P (operands[0]))
1238 if (FP_REG_P (operands[1]))
1239 return \"fmove%.x %1,%0\";
1240 if (REG_P (operands[1]))
1243 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
1244 output_asm_insn (\"move%.l %1,%-\", xoperands);
1245 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1246 output_asm_insn (\"move%.l %1,%-\", xoperands);
1247 output_asm_insn (\"move%.l %1,%-\", operands);
1248 return \"fmove%.x %+,%0\";
1250 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1251 return \"fmove%.x %1,%0\";
1252 return \"fmove%.x %f1,%0\";
1254 if (FP_REG_P (operands[1]))
1256 if (REG_P (operands[0]))
1258 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1259 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1260 output_asm_insn (\"move%.l %+,%0\", operands);
1261 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1262 return \"move%.l %+,%0\";
1265 return \"fmove%.x %f1,%0\";
1267 return output_move_double (operands);
1272 [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
1273 (match_operand:XF 1 "nonimmediate_operand" "g,r"))]
1274 "! TARGET_68881 && TARGET_5200"
1275 "* return output_move_double (operands);")
1277 (define_expand "movdi"
1278 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1279 [(set (match_operand:DI 0 "general_operand" "")
1280 (match_operand:DI 1 "general_operand" ""))]
1284 ;; movdi can apply to fp regs in some cases
1286 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1287 [(set (match_operand:DI 0 "general_operand" "=rm,r,&ro<>,y,rm,!*x,!rm")
1288 (match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))]
1289 ; [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm")
1290 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))]
1291 ; [(set (match_operand:DI 0 "general_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1292 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1296 if (which_alternative == 8)
1297 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1298 if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
1299 return \"fpmove%.d %x1,%x0\";
1300 if (FP_REG_P (operands[0]))
1302 if (FP_REG_P (operands[1]))
1303 return \"fmove%.x %1,%0\";
1304 if (REG_P (operands[1]))
1307 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1308 output_asm_insn (\"move%.l %1,%-\", xoperands);
1309 output_asm_insn (\"move%.l %1,%-\", operands);
1310 return \"fmove%.d %+,%0\";
1312 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1313 return output_move_const_double (operands);
1314 return \"fmove%.d %f1,%0\";
1316 else if (FP_REG_P (operands[1]))
1318 if (REG_P (operands[0]))
1320 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1321 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1322 return \"move%.l %+,%0\";
1325 return \"fmove%.d %f1,%0\";
1327 return output_move_double (operands);
1331 [(set (match_operand:DI 0 "general_operand" "=r,g")
1332 (match_operand:DI 1 "general_operand" "g,r"))]
1334 "* return output_move_double (operands);")
1336 ;; Thus goes after the move instructions
1337 ;; because the move instructions are better (require no spilling)
1338 ;; when they can apply. It goes before the add/sub insns
1339 ;; so we will prefer it to them.
1341 (define_insn "pushasi"
1342 [(set (match_operand:SI 0 "push_operand" "=m")
1343 (match_operand:SI 1 "address_operand" "p"))]
1347 ;; truncation instructions
1348 (define_insn "truncsiqi2"
1349 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1351 (match_operand:SI 1 "general_operand" "doJ,i")))]
1355 if (GET_CODE (operands[0]) == REG)
1357 /* Must clear condition codes, since the move.l bases them on
1358 the entire 32 bits, not just the desired 8 bits. */
1360 return \"move%.l %1,%0\";
1362 if (GET_CODE (operands[1]) == MEM)
1363 operands[1] = adj_offsettable_operand (operands[1], 3);
1364 return \"move%.b %1,%0\";
1367 (define_insn "trunchiqi2"
1368 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1370 (match_operand:HI 1 "general_operand" "doJ,i")))]
1374 if (GET_CODE (operands[0]) == REG
1375 && (GET_CODE (operands[1]) == MEM
1376 || GET_CODE (operands[1]) == CONST_INT))
1378 /* Must clear condition codes, since the move.w bases them on
1379 the entire 16 bits, not just the desired 8 bits. */
1381 return \"move%.w %1,%0\";
1383 if (GET_CODE (operands[0]) == REG)
1385 /* Must clear condition codes, since the move.l bases them on
1386 the entire 32 bits, not just the desired 8 bits. */
1388 return \"move%.l %1,%0\";
1390 if (GET_CODE (operands[1]) == MEM)
1391 operands[1] = adj_offsettable_operand (operands[1], 1);
1392 return \"move%.b %1,%0\";
1395 (define_insn "truncsihi2"
1396 [(set (match_operand:HI 0 "general_operand" "=dm,d")
1398 (match_operand:SI 1 "general_operand" "roJ,i")))]
1402 if (GET_CODE (operands[0]) == REG)
1404 /* Must clear condition codes, since the move.l bases them on
1405 the entire 32 bits, not just the desired 8 bits. */
1407 return \"move%.l %1,%0\";
1409 if (GET_CODE (operands[1]) == MEM)
1410 operands[1] = adj_offsettable_operand (operands[1], 2);
1411 return \"move%.w %1,%0\";
1414 ;; zero extension instructions
1416 ;; this is the canonical form for (lshiftrt:DI x 32)
1417 (define_insn "zero_extendsidi2"
1418 [(set (match_operand:DI 0 "general_operand" "rm")
1419 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
1424 if (GET_CODE (operands[0]) == REG)
1425 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1426 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1427 return \"move%.l %1,%0\;clr%.l %0\";
1428 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1429 return \"clr%.l %0\;move%.l %1,%0\";
1431 operands[2] = adj_offsettable_operand (operands[0], 4);
1432 if (ADDRESS_REG_P (operands[0]))
1433 return \"move%.l %1,%2\;sub%.l %0,%0\";
1435 return \"move%.l %1,%2\;clr%.l %0\";
1438 (define_expand "zero_extendhisi2"
1439 [(set (match_operand:SI 0 "register_operand" "")
1441 (set (strict_low_part (match_dup 2))
1442 (match_operand:HI 1 "general_operand" ""))]
1446 operands[1] = make_safe_from (operands[1], operands[0]);
1447 if (GET_CODE (operands[0]) == SUBREG)
1448 operands[2] = gen_rtx (SUBREG, HImode, SUBREG_REG (operands[0]),
1449 SUBREG_WORD (operands[0]));
1451 operands[2] = gen_rtx (SUBREG, HImode, operands[0], 0);
1454 (define_expand "zero_extendqihi2"
1455 [(set (match_operand:HI 0 "register_operand" "")
1457 (set (strict_low_part (match_dup 2))
1458 (match_operand:QI 1 "general_operand" ""))]
1462 operands[1] = make_safe_from (operands[1], operands[0]);
1463 if (GET_CODE (operands[0]) == SUBREG)
1464 operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]),
1465 SUBREG_WORD (operands[0]));
1467 operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0);
1470 (define_expand "zero_extendqisi2"
1471 [(set (match_operand:SI 0 "register_operand" "")
1473 (set (strict_low_part (match_dup 2))
1474 (match_operand:QI 1 "general_operand" ""))]
1478 operands[1] = make_safe_from (operands[1], operands[0]);
1479 if (GET_CODE (operands[0]) == SUBREG)
1480 operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]),
1481 SUBREG_WORD (operands[0]));
1483 operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0);
1486 ;; Patterns to recognize zero-extend insns produced by the combiner.
1487 ;; We don't allow both operands in memory, because of aliasing problems.
1488 ;; Explicitly disallow two memory operands via the condition since reloading
1489 ;; of this case will result in worse code than the uncombined patterns.
1492 [(set (match_operand:SI 0 "general_operand" "=do<>,d<")
1493 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1494 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1497 if (DATA_REG_P (operands[0]))
1499 if (GET_CODE (operands[1]) == REG
1500 && REGNO (operands[0]) == REGNO (operands[1]))
1501 return \"and%.l %#0xFFFF,%0\";
1502 if (reg_mentioned_p (operands[0], operands[1]))
1503 return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\";
1504 return \"clr%.l %0\;move%.w %1,%0\";
1506 else if (GET_CODE (operands[0]) == MEM
1507 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1508 return \"move%.w %1,%0\;clr%.w %0\";
1509 else if (GET_CODE (operands[0]) == MEM
1510 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1511 return \"clr%.w %0\;move%.w %1,%0\";
1514 output_asm_insn (\"clr%.w %0\", operands);
1515 operands[0] = adj_offsettable_operand (operands[0], 2);
1516 return \"move%.w %1,%0\";
1521 [(set (match_operand:HI 0 "general_operand" "=do<>,d")
1522 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1523 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1526 if (DATA_REG_P (operands[0]))
1528 if (GET_CODE (operands[1]) == REG
1529 && REGNO (operands[0]) == REGNO (operands[1]))
1530 return \"and%.w %#0xFF,%0\";
1531 if (reg_mentioned_p (operands[0], operands[1]))
1532 return \"move%.b %1,%0\;and%.w %#0xFF,%0\";
1533 return \"clr%.w %0\;move%.b %1,%0\";
1535 else if (GET_CODE (operands[0]) == MEM
1536 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1538 if (REGNO (XEXP (XEXP (operands[0], 0), 0))
1539 == STACK_POINTER_REGNUM)
1541 output_asm_insn (\"clr%.w %-\", operands);
1542 operands[0] = gen_rtx (MEM, GET_MODE (operands[0]),
1543 plus_constant (stack_pointer_rtx, 1));
1544 return \"move%.b %1,%0\";
1547 return \"move%.b %1,%0\;clr%.b %0\";
1549 else if (GET_CODE (operands[0]) == MEM
1550 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1551 return \"clr%.b %0\;move%.b %1,%0\";
1554 output_asm_insn (\"clr%.b %0\", operands);
1555 operands[0] = adj_offsettable_operand (operands[0], 1);
1556 return \"move%.b %1,%0\";
1561 [(set (match_operand:SI 0 "general_operand" "=do<>,d")
1562 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1563 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1566 if (DATA_REG_P (operands[0]))
1568 if (GET_CODE (operands[1]) == REG
1569 && REGNO (operands[0]) == REGNO (operands[1]))
1570 return \"and%.l %#0xFF,%0\";
1571 if (reg_mentioned_p (operands[0], operands[1]))
1572 return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
1573 return \"clr%.l %0\;move%.b %1,%0\";
1575 else if (GET_CODE (operands[0]) == MEM
1576 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1578 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1581 return \"clr%.l -(%0)\;move%.b %1,3(%0)\";
1583 return \"clr%.l -(%0)\;move%.b %1,(3,%0)\";
1586 return \"clrl %0@-\;moveb %1,%0@(3)\";
1589 else if (GET_CODE (operands[0]) == MEM
1590 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1592 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1595 return \"clr%.l (%0)+\;move%.b %1,-1(%0)\";
1597 return \"clr%.l (%0)+\;move%.b %1,(-1,%0)\";
1600 return \"clrl %0@+\;moveb %1,%0@(-1)\";
1605 output_asm_insn (\"clr%.l %0\", operands);
1606 operands[0] = adj_offsettable_operand (operands[0], 3);
1607 return \"move%.b %1,%0\";
1611 ;; sign extension instructions
1613 (define_insn "extendqidi2"
1614 [(set (match_operand:DI 0 "general_operand" "=d")
1616 (match_operand:QI 1 "general_operand" "rm")))]
1621 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1622 if (TARGET_68020 || TARGET_5200)
1623 return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
1625 return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
1628 (define_insn "extendhidi2"
1629 [(set (match_operand:DI 0 "general_operand" "=d")
1631 (match_operand:HI 1 "general_operand" "rm")))]
1636 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1637 if (TARGET_68020 || TARGET_5200)
1638 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
1640 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
1643 (define_insn "extendsidi2"
1644 [(set (match_operand:DI 0 "general_operand" "=d")
1646 (match_operand:SI 1 "general_operand" "rm")))]
1651 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1652 if (TARGET_68020 || TARGET_5200)
1653 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
1655 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
1658 ;; Special case when one can avoid register clobbering, copy and test
1659 ;; Maybe there is a way to make that the general case, by forcing the
1660 ;; result of the SI tree to be in the lower register of the DI target
1662 (define_insn "extendplussidi"
1663 [(set (match_operand:DI 0 "register_operand" "=d")
1664 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1665 (match_operand:SI 2 "general_operand" "rmn"))))]
1670 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1671 if (GET_CODE (operands[1]) == CONST_INT
1672 && (unsigned) INTVAL (operands[1]) > 8)
1674 rtx tmp = operands[1];
1676 operands[1] = operands[2];
1679 if (GET_CODE (operands[1]) == REG
1680 && REGNO (operands[1]) == REGNO (operands[3]))
1681 output_asm_insn (\"add%.l %2,%3\", operands);
1683 output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands);
1684 if (TARGET_68020 || TARGET_5200)
1685 return \"smi %0\;extb%.l %0\";
1687 return \"smi %0\;ext%.w %0\;ext%.l %0\";
1690 (define_insn "extendhisi2"
1691 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1693 (match_operand:HI 1 "nonimmediate_operand" "0,rm")))]
1697 if (ADDRESS_REG_P (operands[0]))
1698 return \"move%.w %1,%0\";
1699 return \"ext%.l %0\";
1702 (define_insn "extendqihi2"
1703 [(set (match_operand:HI 0 "general_operand" "=d")
1704 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1708 (define_insn "extendqisi2"
1709 [(set (match_operand:SI 0 "general_operand" "=d")
1710 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1711 "TARGET_68020 || TARGET_5200"
1714 ;; Conversions between float and double.
1716 (define_expand "extendsfdf2"
1717 [(set (match_operand:DF 0 "general_operand" "")
1719 (match_operand:SF 1 "general_operand" "")))]
1720 "TARGET_68881 || TARGET_FPA"
1724 [(set (match_operand:DF 0 "general_operand" "=x,y")
1726 (match_operand:SF 1 "general_operand" "xH,rmF")))]
1731 [(set (match_operand:DF 0 "general_operand" "=*fdm,f")
1733 (match_operand:SF 1 "general_operand" "f,dmF")))]
1737 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1739 if (REGNO (operands[0]) == REGNO (operands[1]))
1741 /* Extending float to double in an fp-reg is a no-op.
1742 NOTICE_UPDATE_CC has already assumed that the
1743 cc will be set. So cancel what it did. */
1744 cc_status = cc_prev_status;
1747 return \"f%&move%.x %1,%0\";
1749 if (FP_REG_P (operands[0]))
1750 return \"f%&move%.s %f1,%0\";
1751 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1753 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1754 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1755 return \"move%.l %+,%0\";
1757 return \"fmove%.d %f1,%0\";
1760 ;; This cannot output into an f-reg because there is no way to be
1761 ;; sure of truncating in that case.
1762 ;; But on the Sun FPA, we can be sure.
1763 (define_expand "truncdfsf2"
1764 [(set (match_operand:SF 0 "general_operand" "")
1766 (match_operand:DF 1 "general_operand" "")))]
1767 "TARGET_68881 || TARGET_FPA"
1771 [(set (match_operand:SF 0 "general_operand" "=x,y")
1773 (match_operand:DF 1 "general_operand" "xH,rmF")))]
1777 ;; On the '040 we can truncate in a register accurately and easily.
1779 [(set (match_operand:SF 0 "general_operand" "=f")
1781 (match_operand:DF 1 "general_operand" "fmG")))]
1785 if (FP_REG_P (operands[1]))
1786 return \"f%$move%.x %1,%0\";
1787 return \"f%$move%.d %f1,%0\";
1791 [(set (match_operand:SF 0 "general_operand" "=dm")
1793 (match_operand:DF 1 "general_operand" "f")))]
1797 ;; Conversion between fixed point and floating point.
1798 ;; Note that among the fix-to-float insns
1799 ;; the ones that start with SImode come first.
1800 ;; That is so that an operand that is a CONST_INT
1801 ;; (and therefore lacks a specific machine mode).
1802 ;; will be recognized as SImode (which is always valid)
1803 ;; rather than as QImode or HImode.
1805 (define_expand "floatsisf2"
1806 [(set (match_operand:SF 0 "general_operand" "")
1807 (float:SF (match_operand:SI 1 "general_operand" "")))]
1808 "TARGET_68881 || TARGET_FPA"
1812 [(set (match_operand:SF 0 "general_operand" "=y,x")
1813 (float:SF (match_operand:SI 1 "general_operand" "rmi,x")))]
1818 [(set (match_operand:SF 0 "general_operand" "=f")
1819 (float:SF (match_operand:SI 1 "general_operand" "dmi")))]
1823 (define_expand "floatsidf2"
1824 [(set (match_operand:DF 0 "general_operand" "")
1825 (float:DF (match_operand:SI 1 "general_operand" "")))]
1826 "TARGET_68881 || TARGET_FPA"
1830 [(set (match_operand:DF 0 "general_operand" "=y,x")
1831 (float:DF (match_operand:SI 1 "general_operand" "rmi,x")))]
1836 [(set (match_operand:DF 0 "general_operand" "=f")
1837 (float:DF (match_operand:SI 1 "general_operand" "dmi")))]
1841 (define_insn "floathisf2"
1842 [(set (match_operand:SF 0 "general_operand" "=f")
1843 (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
1847 (define_insn "floathidf2"
1848 [(set (match_operand:DF 0 "general_operand" "=f")
1849 (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
1853 (define_insn "floatqisf2"
1854 [(set (match_operand:SF 0 "general_operand" "=f")
1855 (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
1859 (define_insn "floatqidf2"
1860 [(set (match_operand:DF 0 "general_operand" "=f")
1861 (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
1865 ;; New routines to convert floating-point values to integers
1866 ;; to be used on the '040. These should be faster than trapping
1867 ;; into the kernel to emulate fintrz. They should also be faster
1868 ;; than calling the subroutines fixsfsi or fixdfsi.
1870 (define_insn "fix_truncdfsi2"
1871 [(set (match_operand:SI 0 "general_operand" "=dm")
1872 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1873 (clobber (match_scratch:SI 2 "=d"))
1874 (clobber (match_scratch:SI 3 "=d"))]
1875 "TARGET_68881 && TARGET_68040"
1879 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\";
1882 (define_insn "fix_truncdfhi2"
1883 [(set (match_operand:HI 0 "general_operand" "=dm")
1884 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1885 (clobber (match_scratch:SI 2 "=d"))
1886 (clobber (match_scratch:SI 3 "=d"))]
1887 "TARGET_68881 && TARGET_68040"
1891 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\";
1894 (define_insn "fix_truncdfqi2"
1895 [(set (match_operand:QI 0 "general_operand" "=dm")
1896 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1897 (clobber (match_scratch:SI 2 "=d"))
1898 (clobber (match_scratch:SI 3 "=d"))]
1899 "TARGET_68881 && TARGET_68040"
1903 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\";
1906 ;; Convert a float to a float whose value is an integer.
1907 ;; This is the first stage of converting it to an integer type.
1909 (define_insn "ftruncdf2"
1910 [(set (match_operand:DF 0 "general_operand" "=f")
1911 (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
1912 "TARGET_68881 && !TARGET_68040"
1915 if (FP_REG_P (operands[1]))
1916 return \"fintrz%.x %f1,%0\";
1917 return \"fintrz%.d %f1,%0\";
1920 (define_insn "ftruncsf2"
1921 [(set (match_operand:SF 0 "general_operand" "=f")
1922 (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
1923 "TARGET_68881 && !TARGET_68040"
1926 if (FP_REG_P (operands[1]))
1927 return \"fintrz%.x %f1,%0\";
1928 return \"fintrz%.s %f1,%0\";
1931 ;; Convert a float whose value is an integer
1932 ;; to an actual integer. Second stage of converting float to integer type.
1933 (define_insn "fixsfqi2"
1934 [(set (match_operand:QI 0 "general_operand" "=dm")
1935 (fix:QI (match_operand:SF 1 "general_operand" "f")))]
1939 (define_insn "fixsfhi2"
1940 [(set (match_operand:HI 0 "general_operand" "=dm")
1941 (fix:HI (match_operand:SF 1 "general_operand" "f")))]
1945 (define_insn "fixsfsi2"
1946 [(set (match_operand:SI 0 "general_operand" "=dm")
1947 (fix:SI (match_operand:SF 1 "general_operand" "f")))]
1951 (define_insn "fixdfqi2"
1952 [(set (match_operand:QI 0 "general_operand" "=dm")
1953 (fix:QI (match_operand:DF 1 "general_operand" "f")))]
1957 (define_insn "fixdfhi2"
1958 [(set (match_operand:HI 0 "general_operand" "=dm")
1959 (fix:HI (match_operand:DF 1 "general_operand" "f")))]
1963 (define_insn "fixdfsi2"
1964 [(set (match_operand:SI 0 "general_operand" "=dm")
1965 (fix:SI (match_operand:DF 1 "general_operand" "f")))]
1969 ;; Convert a float to an integer.
1970 ;; On the Sun FPA, this is done in one step.
1973 [(set (match_operand:SI 0 "general_operand" "=x,y")
1974 (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "xH,rmF"))))]
1979 [(set (match_operand:SI 0 "general_operand" "=x,y")
1980 (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "xH,rmF"))))]
1986 (define_insn "adddi_lshrdi_63"
1987 [(set (match_operand:DI 0 "general_operand" "=d")
1988 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
1991 (clobber (match_scratch:SI 2 "=d"))]
1995 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1996 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
1998 \"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0\";
1999 if (GET_CODE (operands[1]) == REG)
2000 operands[4] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2001 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
2002 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2003 operands[4] = operands[1];
2005 operands[4] = adj_offsettable_operand (operands[1], 4);
2006 if (GET_CODE (operands[1]) == MEM
2007 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2008 output_asm_insn (\"move%.l %4,%3\", operands);
2009 output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
2010 if (TARGET_68020 || TARGET_5200)
2011 output_asm_insn (\"extb%.l %2\", operands);
2013 output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
2014 if (GET_CODE (operands[1]) != MEM
2015 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
2016 output_asm_insn (\"move%.l %4,%3\", operands);
2017 return \"sub%.l %2,%3\;subx%.l %2,%0\";
2020 (define_insn "adddi_sexthishl32"
2021 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2022 (plus:DI (ashift:DI (sign_extend:DI
2023 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
2025 (match_operand:DI 2 "general_operand" "0,0,0,0")))
2026 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2031 if (ADDRESS_REG_P (operands[0]))
2032 return \"add%.w %1,%0\";
2033 else if (ADDRESS_REG_P (operands[3]))
2034 return \"move%.w %1,%3\;add%.l %3,%0\";
2036 return \"move%.w %1,%3\;ext%.l %3\;add%.l %3,%0\";
2039 (define_insn "adddi_dilshr32"
2040 [(set (match_operand:DI 0 "general_operand" "=do")
2041 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2042 ;; (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
2043 ;; (const_int 32))))]
2044 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
2046 (match_operand:DI 2 "general_operand" "0")))]
2051 if (GET_CODE (operands[0]) == REG)
2052 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
2054 operands[2] = adj_offsettable_operand (operands[0], 4);
2055 return \"add%.l %1,%2\;negx%.l %0\;neg%.l %0\";
2058 (define_insn "adddi_dishl32"
2059 [(set (match_operand:DI 0 "general_operand" "=ro")
2060 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2061 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2062 ;; (const_int 32))))]
2063 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2065 (match_operand:DI 2 "general_operand" "0")))]
2070 if (GET_CODE (operands[1]) == REG)
2071 operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2073 operands[1] = adj_offsettable_operand (operands[1], 4);
2074 return \"add%.l %1,%0\";
2077 (define_insn "adddi3"
2078 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2079 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0,0")
2080 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2081 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2085 if (DATA_REG_P (operands[0]))
2087 if (DATA_REG_P (operands[2]))
2088 return \"add%.l %R2,%R0\;addx%.l %2,%0\";
2089 else if (GET_CODE (operands[2]) == MEM
2090 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2092 return \"move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0\";
2096 if (GET_CODE (operands[2]) == REG)
2097 operands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
2098 else if (GET_CODE (operands[2]) == CONST_DOUBLE)
2100 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
2101 operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
2103 else if (GET_CODE (operands[2]) == CONST_INT)
2105 operands[1] = operands[2];
2106 operands[2] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx;
2109 operands[1] = adj_offsettable_operand (operands[2], 4);
2110 /* TODO : for consts, optimize move and add */
2111 return \"move%.l %2,%3\;add%.l %1,%R0\;addx%.l %3,%0\";
2114 else if (GET_CODE (operands[0]) == MEM)
2116 if (GET_CODE (operands[2]) == MEM
2117 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2118 return \"add%.l %2,%0\;addx%.l %2,%0\";
2120 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2122 operands[1] = gen_rtx (MEM, SImode,
2123 gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
2124 gen_rtx (CONST_INT, VOIDmode, -8)));
2125 return \"move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1\";
2127 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2129 operands[1] = XEXP(operands[0], 0);
2130 return \"add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
2134 operands[1] = adj_offsettable_operand (operands[0], 4);
2135 return \"add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
2140 (define_insn "addsi_lshrsi_31"
2141 [(set (match_operand:SI 0 "general_operand" "=dm")
2142 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
2148 operands[2] = operands[0];
2149 operands[3] = gen_label_rtx();
2150 if (GET_CODE (operands[0]) == MEM)
2152 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2153 operands[0] = gen_rtx (MEM, SImode, XEXP (XEXP (operands[0], 0), 0));
2154 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2155 operands[2] = gen_rtx (MEM, SImode, XEXP (XEXP (operands[0], 0), 0));
2157 output_asm_insn (\"move%.l %1,%0\", operands);
2159 output_asm_insn (\"jbpl %l3\", operands);
2161 output_asm_insn (\"jpl %l3\", operands);
2164 output_asm_insn (\"addq%.l %#1,%2\", operands);
2166 output_asm_insn (\"add%.l %#1,%2\", operands);
2168 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
2169 CODE_LABEL_NUMBER (operands[3]));
2173 (define_expand "addsi3"
2174 [(set (match_operand:SI 0 "general_operand" "")
2175 (plus:SI (match_operand:SI 1 "general_operand" "")
2176 (match_operand:SI 2 "general_operand" "")))]
2180 ;; Note that the middle two alternatives are near-duplicates
2181 ;; in order to handle insns generated by reload.
2182 ;; This is needed since they are not themselves reloaded,
2183 ;; so commutativity won't apply to them.
2184 (define_insn "*addsi3_internal"
2185 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
2186 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2187 (match_operand:SI 2 "general_operand" "dIKLs,rJK,a,mrIKLs")))]
2189 "* return output_addsi3 (operands);")
2191 (define_insn "*addsi3_5200"
2192 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
2193 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2194 (match_operand:SI 2 "general_operand" "d,rJK,a,mrIKLs")))]
2196 "* return output_addsi3 (operands);")
2199 [(set (match_operand:SI 0 "general_operand" "=a")
2200 (plus:SI (match_operand:SI 1 "general_operand" "0")
2202 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2206 (define_insn "addhi3"
2207 [(set (match_operand:HI 0 "general_operand" "=m,r")
2208 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2209 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2213 if (GET_CODE (operands[2]) == CONST_INT)
2216 /* If the constant would be a negative number when interpreted as
2217 HImode, make it negative. This is usually, but not always, done
2218 elsewhere in the compiler. First check for constants out of range,
2219 which could confuse us. */
2221 if (INTVAL (operands[2]) >= 32768)
2222 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2223 INTVAL (operands[2]) - 65536);
2225 if (INTVAL (operands[2]) > 0
2226 && INTVAL (operands[2]) <= 8)
2227 return \"addq%.w %2,%0\";
2228 if (INTVAL (operands[2]) < 0
2229 && INTVAL (operands[2]) >= -8)
2231 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2232 - INTVAL (operands[2]));
2233 return \"subq%.w %2,%0\";
2235 /* On the CPU32 it is faster to use two addqw instructions to
2236 add a small integer (8 < N <= 16) to a register.
2237 Likewise for subqw. */
2238 if (TARGET_CPU32 && REG_P (operands[0]))
2240 if (INTVAL (operands[2]) > 8
2241 && INTVAL (operands[2]) <= 16)
2243 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2244 INTVAL (operands[2]) - 8);
2245 return \"addq%.w %#8,%0\;addq%.w %2,%0\";
2247 if (INTVAL (operands[2]) < -8
2248 && INTVAL (operands[2]) >= -16)
2250 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2251 - INTVAL (operands[2]) - 8);
2252 return \"subq%.w %#8,%0\;subq%.w %2,%0\";
2256 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2258 return \"lea (%c2,%0),%0\";
2260 return \"lea %0@(%c2),%0\";
2263 return \"add%.w %2,%0\";
2266 ;; These insns must use MATCH_DUP instead of the more expected
2267 ;; use of a matching constraint because the "output" here is also
2268 ;; an input, so you can't use the matching constraint. That also means
2269 ;; that you can't use the "%", so you need patterns with the matched
2270 ;; operand in both positions.
2273 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2274 (plus:HI (match_dup 0)
2275 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2279 if (GET_CODE (operands[1]) == CONST_INT)
2282 /* If the constant would be a negative number when interpreted as
2283 HImode, make it negative. This is usually, but not always, done
2284 elsewhere in the compiler. First check for constants out of range,
2285 which could confuse us. */
2287 if (INTVAL (operands[1]) >= 32768)
2288 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2289 INTVAL (operands[1]) - 65536);
2291 if (INTVAL (operands[1]) > 0
2292 && INTVAL (operands[1]) <= 8)
2293 return \"addq%.w %1,%0\";
2294 if (INTVAL (operands[1]) < 0
2295 && INTVAL (operands[1]) >= -8)
2297 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2298 - INTVAL (operands[1]));
2299 return \"subq%.w %1,%0\";
2301 /* On the CPU32 it is faster to use two addqw instructions to
2302 add a small integer (8 < N <= 16) to a register.
2303 Likewise for subqw. */
2304 if (TARGET_CPU32 && REG_P (operands[0]))
2306 if (INTVAL (operands[1]) > 8
2307 && INTVAL (operands[1]) <= 16)
2309 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2310 INTVAL (operands[1]) - 8);
2311 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2313 if (INTVAL (operands[1]) < -8
2314 && INTVAL (operands[1]) >= -16)
2316 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2317 - INTVAL (operands[1]) - 8);
2318 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2322 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2324 return \"lea (%c1,%0),%0\";
2326 return \"lea %0@(%c1),%0\";
2329 return \"add%.w %1,%0\";
2333 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2334 (plus:HI (match_operand:HI 1 "general_operand" "dn,rmn")
2339 if (GET_CODE (operands[1]) == CONST_INT)
2342 /* If the constant would be a negative number when interpreted as
2343 HImode, make it negative. This is usually, but not always, done
2344 elsewhere in the compiler. First check for constants out of range,
2345 which could confuse us. */
2347 if (INTVAL (operands[1]) >= 32768)
2348 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2349 INTVAL (operands[1]) - 65536);
2351 if (INTVAL (operands[1]) > 0
2352 && INTVAL (operands[1]) <= 8)
2353 return \"addq%.w %1,%0\";
2354 if (INTVAL (operands[1]) < 0
2355 && INTVAL (operands[1]) >= -8)
2357 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2358 - INTVAL (operands[1]));
2359 return \"subq%.w %1,%0\";
2361 /* On the CPU32 it is faster to use two addqw instructions to
2362 add a small integer (8 < N <= 16) to a register.
2363 Likewise for subqw. */
2364 if (TARGET_CPU32 && REG_P (operands[0]))
2366 if (INTVAL (operands[1]) > 8
2367 && INTVAL (operands[1]) <= 16)
2369 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2370 INTVAL (operands[1]) - 8);
2371 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2373 if (INTVAL (operands[1]) < -8
2374 && INTVAL (operands[1]) >= -16)
2376 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2377 - INTVAL (operands[1]) - 8);
2378 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2382 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2384 return \"lea (%c1,%0),%0\";
2386 return \"lea %0@(%c1),%0\";
2389 return \"add%.w %1,%0\";
2392 (define_insn "addqi3"
2393 [(set (match_operand:QI 0 "general_operand" "=m,d")
2394 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2395 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2400 if (GET_CODE (operands[2]) == CONST_INT)
2402 if (INTVAL (operands[2]) >= 128)
2403 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2404 INTVAL (operands[2]) - 256);
2406 if (INTVAL (operands[2]) > 0
2407 && INTVAL (operands[2]) <= 8)
2408 return \"addq%.b %2,%0\";
2409 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2411 operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2]));
2412 return \"subq%.b %2,%0\";
2416 return \"add%.b %2,%0\";
2420 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2421 (plus:QI (match_dup 0)
2422 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2427 if (GET_CODE (operands[1]) == CONST_INT)
2429 if (INTVAL (operands[1]) >= 128)
2430 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2431 INTVAL (operands[1]) - 256);
2433 if (INTVAL (operands[1]) > 0
2434 && INTVAL (operands[1]) <= 8)
2435 return \"addq%.b %1,%0\";
2436 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2438 operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]));
2439 return \"subq%.b %1,%0\";
2443 return \"add%.b %1,%0\";
2447 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2448 (plus:QI (match_operand:QI 1 "general_operand" "dn,dmn")
2454 if (GET_CODE (operands[1]) == CONST_INT)
2456 if (INTVAL (operands[1]) >= 128)
2457 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2458 INTVAL (operands[1]) - 256);
2460 if (INTVAL (operands[1]) > 0
2461 && INTVAL (operands[1]) <= 8)
2462 return \"addq%.b %1,%0\";
2463 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2465 operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]));
2466 return \"subq%.b %1,%0\";
2470 return \"add%.b %1,%0\";
2473 (define_expand "adddf3"
2474 [(set (match_operand:DF 0 "general_operand" "")
2475 (plus:DF (match_operand:DF 1 "general_operand" "")
2476 (match_operand:DF 2 "general_operand" "")))]
2477 "TARGET_68881 || TARGET_FPA"
2481 [(set (match_operand:DF 0 "general_operand" "=x,y")
2482 (plus:DF (match_operand:DF 1 "general_operand" "%xH,y")
2483 (match_operand:DF 2 "general_operand" "xH,dmF")))]
2487 if (rtx_equal_p (operands[0], operands[1]))
2488 return \"fpadd%.d %y2,%0\";
2489 if (rtx_equal_p (operands[0], operands[2]))
2490 return \"fpadd%.d %y1,%0\";
2491 if (which_alternative == 0)
2492 return \"fpadd3%.d %w2,%w1,%0\";
2493 return \"fpadd3%.d %x2,%x1,%0\";
2497 [(set (match_operand:DF 0 "general_operand" "=f")
2498 (plus:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2499 (match_operand:DF 1 "general_operand" "0")))]
2504 [(set (match_operand:DF 0 "general_operand" "=f")
2505 (plus:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2506 (match_operand:DF 1 "general_operand" "0")))]
2511 [(set (match_operand:DF 0 "general_operand" "=f")
2512 (plus:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2513 (match_operand:DF 1 "general_operand" "0")))]
2518 [(set (match_operand:DF 0 "general_operand" "=f")
2519 (plus:DF (match_operand:DF 1 "general_operand" "%0")
2520 (match_operand:DF 2 "general_operand" "fmG")))]
2524 if (REG_P (operands[2]))
2525 return \"f%&add%.x %2,%0\";
2526 return \"f%&add%.d %f2,%0\";
2529 (define_expand "addsf3"
2530 [(set (match_operand:SF 0 "general_operand" "")
2531 (plus:SF (match_operand:SF 1 "general_operand" "")
2532 (match_operand:SF 2 "general_operand" "")))]
2533 "TARGET_68881 || TARGET_FPA"
2537 [(set (match_operand:SF 0 "general_operand" "=x,y")
2538 (plus:SF (match_operand:SF 1 "general_operand" "%xH,y")
2539 (match_operand:SF 2 "general_operand" "xH,rmF")))]
2543 if (rtx_equal_p (operands[0], operands[1]))
2544 return \"fpadd%.s %w2,%0\";
2545 if (rtx_equal_p (operands[0], operands[2]))
2546 return \"fpadd%.s %w1,%0\";
2547 if (which_alternative == 0)
2548 return \"fpadd3%.s %w2,%w1,%0\";
2549 return \"fpadd3%.s %2,%1,%0\";
2553 [(set (match_operand:SF 0 "general_operand" "=f")
2554 (plus:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2555 (match_operand:SF 1 "general_operand" "0")))]
2560 [(set (match_operand:SF 0 "general_operand" "=f")
2561 (plus:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
2562 (match_operand:SF 1 "general_operand" "0")))]
2567 [(set (match_operand:SF 0 "general_operand" "=f")
2568 (plus:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
2569 (match_operand:SF 1 "general_operand" "0")))]
2574 [(set (match_operand:SF 0 "general_operand" "=f")
2575 (plus:SF (match_operand:SF 1 "general_operand" "%0")
2576 (match_operand:SF 2 "general_operand" "fdmF")))]
2580 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2581 return \"f%$add%.x %2,%0\";
2582 return \"f%$add%.s %f2,%0\";
2585 ;; subtract instructions
2587 (define_insn "subdi_sexthishl32"
2588 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2589 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2590 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2592 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2597 if (ADDRESS_REG_P (operands[0]))
2598 return \"sub%.w %2,%0\";
2599 else if (ADDRESS_REG_P (operands[3]))
2600 return \"move%.w %2,%3\;sub%.l %3,%0\";
2602 return \"move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0\";
2605 (define_insn "subdi_dishl32"
2606 [(set (match_operand:DI 0 "general_operand" "+ro")
2607 (minus:DI (match_dup 0)
2608 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2614 if (GET_CODE (operands[1]) == REG)
2615 operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2617 operands[1] = adj_offsettable_operand (operands[1], 4);
2618 return \"sub%.l %1,%0\";
2621 (define_insn "subdi3"
2622 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2623 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0,0")
2624 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2625 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2629 if (DATA_REG_P (operands[0]))
2631 if (DATA_REG_P (operands[2]))
2632 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
2633 else if (GET_CODE (operands[2]) == MEM
2634 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2636 return \"move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0\";
2640 if (GET_CODE (operands[2]) == REG)
2641 operands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
2642 else if (GET_CODE (operands[2]) == CONST_DOUBLE)
2644 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
2645 operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
2647 else if (GET_CODE (operands[2]) == CONST_INT)
2649 operands[1] = operands[2];
2650 operands[2] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx;
2653 operands[1] = adj_offsettable_operand (operands[2], 4);
2654 /* TODO : for consts, optimize move and sub */
2655 return \"move%.l %2,%3\;sub%.l %1,%R0\;subx%.l %3,%0\";
2658 else if (GET_CODE (operands[0]) == MEM)
2660 if (GET_CODE (operands[2]) == MEM
2661 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2662 return \"sub%.l %2,%0\;subx%.l %2,%0\";
2664 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2666 operands[1] = gen_rtx (MEM, SImode,
2667 gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
2668 gen_rtx (CONST_INT, VOIDmode, -8)));
2669 return \"move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1\";
2671 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2673 operands[1] = XEXP(operands[0], 0);
2674 return \"sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
2678 operands[1] = adj_offsettable_operand (operands[0], 4);
2679 return \"sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
2684 (define_insn "subsi3"
2685 [(set (match_operand:SI 0 "general_operand" "=m,r")
2686 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
2687 (match_operand:SI 2 "general_operand" "ds,mrs")))]
2692 [(set (match_operand:SI 0 "general_operand" "=a")
2693 (minus:SI (match_operand:SI 1 "general_operand" "0")
2695 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2699 (define_insn "subhi3"
2700 [(set (match_operand:HI 0 "general_operand" "=m,r")
2701 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2702 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2707 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2708 (minus:HI (match_dup 0)
2709 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2713 (define_insn "subqi3"
2714 [(set (match_operand:QI 0 "general_operand" "=m,d")
2715 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2716 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2721 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2722 (minus:QI (match_dup 0)
2723 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2727 (define_expand "subdf3"
2728 [(set (match_operand:DF 0 "general_operand" "")
2729 (minus:DF (match_operand:DF 1 "general_operand" "")
2730 (match_operand:DF 2 "general_operand" "")))]
2731 "TARGET_68881 || TARGET_FPA"
2735 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
2736 (minus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF")
2737 (match_operand:DF 2 "general_operand" "xH,dmF,0")))]
2741 if (rtx_equal_p (operands[0], operands[2]))
2742 return \"fprsub%.d %y1,%0\";
2743 if (rtx_equal_p (operands[0], operands[1]))
2744 return \"fpsub%.d %y2,%0\";
2745 if (which_alternative == 0)
2746 return \"fpsub3%.d %w2,%w1,%0\";
2747 return \"fpsub3%.d %x2,%x1,%0\";
2751 [(set (match_operand:DF 0 "general_operand" "=f")
2752 (minus:DF (match_operand:DF 1 "general_operand" "0")
2753 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
2758 [(set (match_operand:DF 0 "general_operand" "=f")
2759 (minus:DF (match_operand:DF 1 "general_operand" "0")
2760 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
2765 [(set (match_operand:DF 0 "general_operand" "=f")
2766 (minus:DF (match_operand:DF 1 "general_operand" "0")
2767 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
2772 [(set (match_operand:DF 0 "general_operand" "=f")
2773 (minus:DF (match_operand:DF 1 "general_operand" "0")
2774 (match_operand:DF 2 "general_operand" "fmG")))]
2778 if (REG_P (operands[2]))
2779 return \"f%&sub%.x %2,%0\";
2780 return \"f%&sub%.d %f2,%0\";
2783 (define_expand "subsf3"
2784 [(set (match_operand:SF 0 "general_operand" "")
2785 (minus:SF (match_operand:SF 1 "general_operand" "")
2786 (match_operand:SF 2 "general_operand" "")))]
2787 "TARGET_68881 || TARGET_FPA"
2791 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
2792 (minus:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
2793 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
2797 if (rtx_equal_p (operands[0], operands[2]))
2798 return \"fprsub%.s %w1,%0\";
2799 if (rtx_equal_p (operands[0], operands[1]))
2800 return \"fpsub%.s %w2,%0\";
2801 if (which_alternative == 0)
2802 return \"fpsub3%.s %w2,%w1,%0\";
2803 return \"fpsub3%.s %2,%1,%0\";
2807 [(set (match_operand:SF 0 "general_operand" "=f")
2808 (minus:SF (match_operand:SF 1 "general_operand" "0")
2809 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
2814 [(set (match_operand:SF 0 "general_operand" "=f")
2815 (minus:SF (match_operand:SF 1 "general_operand" "0")
2816 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
2821 [(set (match_operand:SF 0 "general_operand" "=f")
2822 (minus:SF (match_operand:SF 1 "general_operand" "0")
2823 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
2828 [(set (match_operand:SF 0 "general_operand" "=f")
2829 (minus:SF (match_operand:SF 1 "general_operand" "0")
2830 (match_operand:SF 2 "general_operand" "fdmF")))]
2834 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2835 return \"f%$sub%.x %2,%0\";
2836 return \"f%$sub%.s %f2,%0\";
2839 ;; multiply instructions
2841 (define_insn "mulhi3"
2842 [(set (match_operand:HI 0 "general_operand" "=d")
2843 (mult:HI (match_operand:HI 1 "general_operand" "%0")
2844 (match_operand:HI 2 "general_operand" "dmn")))]
2848 #if defined(MOTOROLA) && !defined(CRDS)
2849 return \"muls%.w %2,%0\";
2851 return \"muls %2,%0\";
2855 (define_insn "mulhisi3"
2856 [(set (match_operand:SI 0 "general_operand" "=d")
2857 (mult:SI (sign_extend:SI
2858 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2860 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
2864 #if defined(MOTOROLA) && !defined(CRDS)
2865 return \"muls%.w %2,%0\";
2867 return \"muls %2,%0\";
2872 [(set (match_operand:SI 0 "general_operand" "=d")
2873 (mult:SI (sign_extend:SI
2874 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2875 (match_operand:SI 2 "const_int_operand" "n")))]
2876 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
2879 #if defined(MOTOROLA) && !defined(CRDS)
2880 return \"muls%.w %2,%0\";
2882 return \"muls %2,%0\";
2886 (define_expand "mulsi3"
2887 [(set (match_operand:SI 0 "general_operand" "")
2888 (mult:SI (match_operand:SI 1 "general_operand" "")
2889 (match_operand:SI 2 "general_operand" "")))]
2890 "TARGET_68020 || TARGET_5200"
2894 [(set (match_operand:SI 0 "general_operand" "=d")
2895 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2896 (match_operand:SI 2 "general_operand" "dmsK")))]
2901 [(set (match_operand:SI 0 "general_operand" "=d")
2902 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2903 (match_operand:SI 2 "general_operand" "d<Q>")))]
2907 (define_insn "umulhisi3"
2908 [(set (match_operand:SI 0 "general_operand" "=d")
2909 (mult:SI (zero_extend:SI
2910 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2912 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
2916 #if defined(MOTOROLA) && !defined(CRDS)
2917 return \"mulu%.w %2,%0\";
2919 return \"mulu %2,%0\";
2924 [(set (match_operand:SI 0 "general_operand" "=d")
2925 (mult:SI (zero_extend:SI
2926 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2927 (match_operand:SI 2 "const_int_operand" "n")))]
2928 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
2931 #if defined(MOTOROLA) && !defined(CRDS)
2932 return \"mulu%.w %2,%0\";
2934 return \"mulu %2,%0\";
2938 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
2939 ;; proper matching constraint. This is because the matching is between
2940 ;; the high-numbered word of the DImode operand[0] and operand[1].
2941 (define_expand "umulsidi3"
2943 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
2944 (mult:SI (match_operand:SI 1 "register_operand" "")
2945 (match_operand:SI 2 "nonimmediate_operand" "")))
2946 (set (subreg:SI (match_dup 0) 0)
2947 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2948 (zero_extend:DI (match_dup 2)))
2949 (const_int 32))))])]
2950 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2954 [(set (match_operand:SI 0 "register_operand" "=d")
2955 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2956 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2957 (set (match_operand:SI 3 "register_operand" "=d")
2958 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2959 (zero_extend:DI (match_dup 2)))
2961 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2964 ; Match immediate case. For 2.4 only match things < 2^31.
2965 ; It's tricky with larger values in these patterns since we need to match
2966 ; values between the two parallel multiplies, between a CONST_DOUBLE and
2969 [(set (match_operand:SI 0 "register_operand" "=d")
2970 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2971 (match_operand:SI 2 "const_int_operand" "n")))
2972 (set (match_operand:SI 3 "register_operand" "=d")
2973 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2976 "TARGET_68020 && !TARGET_68060 && !TARGET_5200
2977 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
2980 (define_expand "mulsidi3"
2982 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
2983 (mult:SI (match_operand:SI 1 "register_operand" "")
2984 (match_operand:SI 2 "nonimmediate_operand" "")))
2985 (set (subreg:SI (match_dup 0) 0)
2986 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2987 (sign_extend:DI (match_dup 2)))
2988 (const_int 32))))])]
2989 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2993 [(set (match_operand:SI 0 "register_operand" "=d")
2994 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2995 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2996 (set (match_operand:SI 3 "register_operand" "=d")
2997 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2998 (sign_extend:DI (match_dup 2)))
3000 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3004 [(set (match_operand:SI 0 "register_operand" "=d")
3005 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3006 (match_operand:SI 2 "const_sint32_operand" "")))
3007 (set (match_operand:SI 3 "register_operand" "=d")
3008 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3011 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3014 (define_expand "umulsi3_highpart"
3016 [(set (match_operand:SI 0 "register_operand" "")
3019 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
3020 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
3022 (clobber (match_dup 3))])]
3023 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3026 operands[3] = gen_reg_rtx (SImode);
3027 if (GET_CODE (operands[2]) == CONST_INT
3028 || GET_CODE (operands[2]) == CONST_DOUBLE)
3030 if (! const_uint32_operand (operands[2], VOIDmode))
3032 /* We have to adjust the operand order for the matching constraints. */
3033 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
3034 operands[1], operands[2]));
3040 [(set (match_operand:SI 0 "register_operand" "=d")
3043 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3044 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3046 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3047 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3050 (define_insn "const_umulsi3_highpart"
3051 [(set (match_operand:SI 0 "register_operand" "=d")
3054 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
3055 (match_operand 3 "const_uint32_operand" ""))
3057 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3058 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3061 (define_expand "smulsi3_highpart"
3063 [(set (match_operand:SI 0 "register_operand" "")
3066 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
3067 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
3069 (clobber (match_dup 3))])]
3070 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3073 operands[3] = gen_reg_rtx (SImode);
3074 if (GET_CODE (operands[2]) == CONST_INT
3075 || GET_CODE (operands[2]) == CONST_DOUBLE)
3077 if (! const_sint32_operand (operands[2], VOIDmode))
3079 /* We have to adjust the operand order for the matching constraints. */
3080 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
3081 operands[1], operands[2]));
3087 [(set (match_operand:SI 0 "register_operand" "=d")
3090 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3091 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3093 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3094 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3097 (define_insn "const_smulsi3_highpart"
3098 [(set (match_operand:SI 0 "register_operand" "=d")
3101 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
3102 (match_operand 3 "const_sint32_operand" ""))
3104 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3105 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3108 (define_expand "muldf3"
3109 [(set (match_operand:DF 0 "general_operand" "")
3110 (mult:DF (match_operand:DF 1 "general_operand" "")
3111 (match_operand:DF 2 "general_operand" "")))]
3112 "TARGET_68881 || TARGET_FPA"
3116 [(set (match_operand:DF 0 "general_operand" "=x,y")
3117 (mult:DF (match_operand:DF 1 "general_operand" "%xH,y")
3118 (match_operand:DF 2 "general_operand" "xH,rmF")))]
3122 if (rtx_equal_p (operands[1], operands[2]))
3123 return \"fpsqr%.d %y1,%0\";
3124 if (rtx_equal_p (operands[0], operands[1]))
3125 return \"fpmul%.d %y2,%0\";
3126 if (rtx_equal_p (operands[0], operands[2]))
3127 return \"fpmul%.d %y1,%0\";
3128 if (which_alternative == 0)
3129 return \"fpmul3%.d %w2,%w1,%0\";
3130 return \"fpmul3%.d %x2,%x1,%0\";
3134 [(set (match_operand:DF 0 "general_operand" "=f")
3135 (mult:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
3136 (match_operand:DF 1 "general_operand" "0")))]
3141 [(set (match_operand:DF 0 "general_operand" "=f")
3142 (mult:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
3143 (match_operand:DF 1 "general_operand" "0")))]
3148 [(set (match_operand:DF 0 "general_operand" "=f")
3149 (mult:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
3150 (match_operand:DF 1 "general_operand" "0")))]
3155 [(set (match_operand:DF 0 "general_operand" "=f")
3156 (mult:DF (match_operand:DF 1 "general_operand" "%0")
3157 (match_operand:DF 2 "general_operand" "fmG")))]
3161 if (GET_CODE (operands[2]) == CONST_DOUBLE
3162 && floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
3164 int i = floating_exact_log2 (operands[2]);
3165 operands[2] = gen_rtx (CONST_INT, VOIDmode, i);
3166 return \"fscale%.l %2,%0\";
3168 if (REG_P (operands[2]))
3169 return \"f%&mul%.x %2,%0\";
3170 return \"f%&mul%.d %f2,%0\";
3173 (define_expand "mulsf3"
3174 [(set (match_operand:SF 0 "general_operand" "")
3175 (mult:SF (match_operand:SF 1 "general_operand" "")
3176 (match_operand:SF 2 "general_operand" "")))]
3177 "TARGET_68881 || TARGET_FPA"
3181 [(set (match_operand:SF 0 "general_operand" "=x,y")
3182 (mult:SF (match_operand:SF 1 "general_operand" "%xH,y")
3183 (match_operand:SF 2 "general_operand" "xH,rmF")))]
3187 if (rtx_equal_p (operands[1], operands[2]))
3188 return \"fpsqr%.s %w1,%0\";
3189 if (rtx_equal_p (operands[0], operands[1]))
3190 return \"fpmul%.s %w2,%0\";
3191 if (rtx_equal_p (operands[0], operands[2]))
3192 return \"fpmul%.s %w1,%0\";
3193 if (which_alternative == 0)
3194 return \"fpmul3%.s %w2,%w1,%0\";
3195 return \"fpmul3%.s %2,%1,%0\";
3199 [(set (match_operand:SF 0 "general_operand" "=f")
3200 (mult:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
3201 (match_operand:SF 1 "general_operand" "0")))]
3205 return (TARGET_68040_ONLY
3206 ? \"fsmul%.l %2,%0\"
3207 : \"fsglmul%.l %2,%0\");
3211 [(set (match_operand:SF 0 "general_operand" "=f")
3212 (mult:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
3213 (match_operand:SF 1 "general_operand" "0")))]
3217 return (TARGET_68040_ONLY
3218 ? \"fsmul%.w %2,%0\"
3219 : \"fsglmul%.w %2,%0\");
3223 [(set (match_operand:SF 0 "general_operand" "=f")
3224 (mult:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
3225 (match_operand:SF 1 "general_operand" "0")))]
3229 return (TARGET_68040_ONLY
3230 ? \"fsmul%.b %2,%0\"
3231 : \"fsglmul%.b %2,%0\");
3235 [(set (match_operand:SF 0 "general_operand" "=f")
3236 (mult:SF (match_operand:SF 1 "general_operand" "%0")
3237 (match_operand:SF 2 "general_operand" "fdmF")))]
3241 #ifdef FSGLMUL_USE_S
3242 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3243 return (TARGET_68040_ONLY
3244 ? \"fsmul%.s %2,%0\"
3245 : \"fsglmul%.s %2,%0\");
3247 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3248 return (TARGET_68040_ONLY
3249 ? \"fsmul%.x %2,%0\"
3250 : \"fsglmul%.x %2,%0\");
3252 return (TARGET_68040_ONLY
3253 ? \"fsmul%.s %f2,%0\"
3254 : \"fsglmul%.s %f2,%0\");
3257 ;; divide instructions
3259 (define_expand "divdf3"
3260 [(set (match_operand:DF 0 "general_operand" "")
3261 (div:DF (match_operand:DF 1 "general_operand" "")
3262 (match_operand:DF 2 "general_operand" "")))]
3263 "TARGET_68881 || TARGET_FPA"
3267 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
3268 (div:DF (match_operand:DF 1 "general_operand" "xH,y,rmF")
3269 (match_operand:DF 2 "general_operand" "xH,rmF,0")))]
3273 if (rtx_equal_p (operands[0], operands[2]))
3274 return \"fprdiv%.d %y1,%0\";
3275 if (rtx_equal_p (operands[0], operands[1]))
3276 return \"fpdiv%.d %y2,%0\";
3277 if (which_alternative == 0)
3278 return \"fpdiv3%.d %w2,%w1,%0\";
3279 return \"fpdiv3%.d %x2,%x1,%x0\";
3283 [(set (match_operand:DF 0 "general_operand" "=f")
3284 (div:DF (match_operand:DF 1 "general_operand" "0")
3285 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
3290 [(set (match_operand:DF 0 "general_operand" "=f")
3291 (div:DF (match_operand:DF 1 "general_operand" "0")
3292 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
3297 [(set (match_operand:DF 0 "general_operand" "=f")
3298 (div:DF (match_operand:DF 1 "general_operand" "0")
3299 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
3304 [(set (match_operand:DF 0 "general_operand" "=f")
3305 (div:DF (match_operand:DF 1 "general_operand" "0")
3306 (match_operand:DF 2 "general_operand" "fmG")))]
3310 if (REG_P (operands[2]))
3311 return \"f%&div%.x %2,%0\";
3312 return \"f%&div%.d %f2,%0\";
3315 (define_expand "divsf3"
3316 [(set (match_operand:SF 0 "general_operand" "")
3317 (div:SF (match_operand:SF 1 "general_operand" "")
3318 (match_operand:SF 2 "general_operand" "")))]
3319 "TARGET_68881 || TARGET_FPA"
3323 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
3324 (div:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
3325 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
3329 if (rtx_equal_p (operands[0], operands[1]))
3330 return \"fpdiv%.s %w2,%0\";
3331 if (rtx_equal_p (operands[0], operands[2]))
3332 return \"fprdiv%.s %w1,%0\";
3333 if (which_alternative == 0)
3334 return \"fpdiv3%.s %w2,%w1,%0\";
3335 return \"fpdiv3%.s %2,%1,%0\";
3339 [(set (match_operand:SF 0 "general_operand" "=f")
3340 (div:SF (match_operand:SF 1 "general_operand" "0")
3341 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
3345 return (TARGET_68040_ONLY
3346 ? \"fsdiv%.l %2,%0\"
3347 : \"fsgldiv%.l %2,%0\");
3351 [(set (match_operand:SF 0 "general_operand" "=f")
3352 (div:SF (match_operand:SF 1 "general_operand" "0")
3353 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
3357 return (TARGET_68040_ONLY
3358 ? \"fsdiv%.w %2,%0\"
3359 : \"fsgldiv%.w %2,%0\");
3363 [(set (match_operand:SF 0 "general_operand" "=f")
3364 (div:SF (match_operand:SF 1 "general_operand" "0")
3365 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
3369 return (TARGET_68040_ONLY
3370 ? \"fsdiv%.b %2,%0\"
3371 : \"fsgldiv%.b %2,%0\");
3375 [(set (match_operand:SF 0 "general_operand" "=f")
3376 (div:SF (match_operand:SF 1 "general_operand" "0")
3377 (match_operand:SF 2 "general_operand" "fdmF")))]
3381 #ifdef FSGLDIV_USE_S
3382 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3383 return (TARGET_68040_ONLY
3384 ? \"fsdiv%.s %2,%0\"
3385 : \"fsgldiv%.s %2,%0\");
3387 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3388 return (TARGET_68040_ONLY
3389 ? \"fsdiv%.x %2,%0\"
3390 : \"fsgldiv%.x %2,%0\");
3392 return (TARGET_68040_ONLY
3393 ? \"fsdiv%.s %f2,%0\"
3394 : \"fsgldiv%.s %f2,%0\");
3397 ;; Remainder instructions.
3399 (define_insn "divmodsi4"
3400 [(set (match_operand:SI 0 "general_operand" "=d")
3401 (div:SI (match_operand:SI 1 "general_operand" "0")
3402 (match_operand:SI 2 "general_operand" "dmsK")))
3403 (set (match_operand:SI 3 "general_operand" "=d")
3404 (mod:SI (match_dup 1) (match_dup 2)))]
3405 "TARGET_68020 && !TARGET_5200"
3408 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3409 return \"divs%.l %2,%0\";
3411 return \"divsl%.l %2,%3:%0\";
3414 (define_insn "udivmodsi4"
3415 [(set (match_operand:SI 0 "general_operand" "=d")
3416 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3417 (match_operand:SI 2 "general_operand" "dmsK")))
3418 (set (match_operand:SI 3 "general_operand" "=d")
3419 (umod:SI (match_dup 1) (match_dup 2)))]
3420 "TARGET_68020 && !TARGET_5200"
3423 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3424 return \"divu%.l %2,%0\";
3426 return \"divul%.l %2,%3:%0\";
3429 (define_insn "divmodhi4"
3430 [(set (match_operand:HI 0 "general_operand" "=d")
3431 (div:HI (match_operand:HI 1 "general_operand" "0")
3432 (match_operand:HI 2 "general_operand" "dmsK")))
3433 (set (match_operand:HI 3 "general_operand" "=d")
3434 (mod:HI (match_dup 1) (match_dup 2)))]
3439 output_asm_insn (\"ext%.l %0\;divs%.w %2,%0\", operands);
3441 output_asm_insn (\"extl %0\;divs %2,%0\", operands);
3443 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3446 return \"move%.l %0,%3\;swap %3\";
3452 (define_insn "udivmodhi4"
3453 [(set (match_operand:HI 0 "general_operand" "=d")
3454 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3455 (match_operand:HI 2 "general_operand" "dmsK")))
3456 (set (match_operand:HI 3 "general_operand" "=d")
3457 (umod:HI (match_dup 1) (match_dup 2)))]
3462 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu%.w %2,%0\", operands);
3464 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu %2,%0\", operands);
3466 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3469 return \"move%.l %0,%3\;swap %3\";
3475 ;; logical-and instructions
3477 ;; "anddi3" is mainly here to help combine().
3478 (define_insn "anddi3"
3479 [(set (match_operand:DI 0 "general_operand" "=o,d")
3480 (and:DI (match_operand:DI 1 "general_operand" "%0,0")
3481 (match_operand:DI 2 "general_operand" "dn,don")))]
3486 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3487 if (GET_CODE (operands[2]) == CONST_DOUBLE
3488 || GET_CODE (operands[2]) == CONST_INT)
3492 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3494 hi = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
3495 lo = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3500 hi = INTVAL (lo) < 0 ? constm1_rtx : const0_rtx;
3502 switch (INTVAL (hi))
3505 output_asm_insn (\"clr%.l %0\", operands);
3513 xoperands[0] = operands[0];
3515 output_asm_insn (output_andsi3 (xoperands), xoperands);
3518 if (GET_CODE (operands[0]) == REG)
3519 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3521 operands[0] = adj_offsettable_operand (operands[0], 4);
3522 switch (INTVAL (lo))
3525 output_asm_insn (\"clr%.l %0\", operands);
3533 xoperands[0] = operands[0];
3535 output_asm_insn (output_andsi3 (xoperands), xoperands);
3540 if (GET_CODE (operands[0]) != REG)
3542 operands[1] = adj_offsettable_operand (operands[0], 4);
3543 return \"and%.l %2,%0\;and%.l %R2,%1\";
3545 if (GET_CODE (operands[2]) != REG)
3547 operands[1] = adj_offsettable_operand (operands[2], 4);
3548 return \"and%.l %2,%0\;and%.l %1,%R0\";
3550 return \"and%.l %2,%0\;and%.l %R2,%R0\";
3553 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3554 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3555 ;; can't allocate pseudos into it.
3557 (define_expand "andsi3"
3558 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3559 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3560 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3564 (define_insn "andsi3_internal"
3565 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3566 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3567 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3571 return output_andsi3 (operands);
3574 (define_insn "andsi3_5200"
3575 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3576 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3577 (match_operand:SI 2 "general_operand" "d,dmsK")))]
3581 (define_insn "andhi3"
3582 [(set (match_operand:HI 0 "general_operand" "=m,d")
3583 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3584 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3589 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3590 (and:HI (match_dup 0)
3591 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3596 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3597 (and:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3602 (define_insn "andqi3"
3603 [(set (match_operand:QI 0 "general_operand" "=m,d")
3604 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3605 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3610 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3611 (and:QI (match_dup 0)
3612 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3617 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3618 (and:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3623 ;; inclusive-or instructions
3625 ;; "iordi3" is mainly here to help combine().
3626 (define_insn "iordi3"
3627 [(set (match_operand:DI 0 "general_operand" "=o,d")
3628 (ior:DI (match_operand:DI 1 "general_operand" "%0,0")
3629 (match_operand:DI 2 "general_operand" "dn,don")))]
3634 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3635 if (GET_CODE (operands[2]) == CONST_DOUBLE
3636 || GET_CODE (operands[2]) == CONST_INT)
3640 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3642 hi = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
3643 lo = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3648 hi = INTVAL (lo) < 0 ? constm1_rtx : const0_rtx;
3650 switch (INTVAL (hi))
3655 /* FIXME : a scratch register would be welcome here if operand[0]
3656 is not a register */
3657 output_asm_insn (\"move%.l %#-1,%0\", operands);
3663 xoperands[0] = operands[0];
3665 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3668 if (GET_CODE (operands[0]) == REG)
3669 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3671 operands[0] = adj_offsettable_operand (operands[0], 4);
3672 switch (INTVAL (lo))
3677 /* FIXME : a scratch register would be welcome here if operand[0]
3678 is not a register */
3679 output_asm_insn (\"move%.l %#-1,%R0\", operands);
3685 xoperands[0] = operands[0];
3687 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3692 if (GET_CODE (operands[0]) != REG)
3694 operands[1] = adj_offsettable_operand (operands[0], 4);
3695 return \"or%.l %2,%0\;or%.l %R2,%1\";
3697 if (GET_CODE (operands[2]) != REG)
3699 operands[1] = adj_offsettable_operand (operands[2], 4);
3700 return \"or%.l %2,%0\;or%.l %1,%R0\";
3702 return \"or%.l %2,%0\;or%.l %R2,%R0\";
3705 (define_expand "iorsi3"
3706 [(set (match_operand:SI 0 "general_operand" "")
3707 (ior:SI (match_operand:SI 1 "general_operand" "")
3708 (match_operand:SI 2 "general_operand" "")))]
3712 (define_insn "iorsi3_internal"
3713 [(set (match_operand:SI 0 "general_operand" "=m,d")
3714 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3715 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3719 return output_iorsi3 (operands);
3722 (define_insn "iorsi3_5200"
3723 [(set (match_operand:SI 0 "general_operand" "=m,d")
3724 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3725 (match_operand:SI 2 "general_operand" "d,dmsK")))]
3729 (define_insn "iorhi3"
3730 [(set (match_operand:HI 0 "general_operand" "=m,d")
3731 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3732 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3737 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3738 (ior:HI (match_dup 0)
3739 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3744 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3745 (ior:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3750 (define_insn "iorqi3"
3751 [(set (match_operand:QI 0 "general_operand" "=m,d")
3752 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3753 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3758 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3759 (ior:QI (match_dup 0)
3760 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3765 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3766 (ior:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3771 ;; On all 68k models, this makes faster code in a special case.
3772 ;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
3774 ;; ??? This pattern can not work as written, because it fails if operand 0
3775 ;; and operand 1 are the same register. This can happen for alternative 1.
3776 ;; This will still fail even if an early clobber is added to the output
3777 ;; for alternative 1. This is because reload may satisfy the matching
3778 ;; constraint by forcing the output to use exactly the same register as
3779 ;; operand 2, without noticing that this then causes a conflict with operand 1.
3780 ;; Possible fix: check for operand 0/1 overlap, and emit correct but slower
3781 ;; code. This should be rare if the early clobber is added.
3783 (define_insn "iorsi_zexthi_ashl16"
3784 [(set (match_operand:SI 0 "general_operand" "=&d,d")
3785 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "dmn,dmn"))
3786 (ashift:SI (match_operand:SI 2 "general_operand" "o,0")
3792 if (GET_CODE (operands[2]) != REG)
3794 operands[2] = adj_offsettable_operand (operands[2], 2);
3795 output_asm_insn (\"move%.w %2,%0\", operands);
3797 return \"swap %0\;mov%.w %1,%0\";
3801 [(set (match_operand:SI 0 "general_operand" "=o,d")
3802 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3803 (match_operand:SI 2 "general_operand" "0,0")))]
3810 byte_mode = (GET_MODE(operands[1]) == QImode);
3811 if (GET_CODE (operands[0]) == MEM)
3812 operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
3814 return \"or%.b %1,%0\";
3816 return \"or%.w %1,%0\";
3821 ;; "xordi3" is mainly here to help combine().
3822 (define_insn "xordi3"
3823 [(set (match_operand:DI 0 "general_operand" "=od")
3824 (xor:DI (match_operand:DI 1 "general_operand" "%0")
3825 (match_operand:DI 2 "general_operand" "dn")))]
3830 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3831 if (GET_CODE (operands[2]) == CONST_DOUBLE
3832 || GET_CODE (operands[2]) == CONST_INT)
3836 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3838 hi = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
3839 lo = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3844 hi = INTVAL (lo) < 0 ? constm1_rtx : const0_rtx;
3846 switch (INTVAL (hi))
3851 output_asm_insn (\"not%.l %0\", operands);
3854 /* FIXME : a scratch register would be welcome here if
3855 -128 <= INTVAL (hi) < -1 */
3859 xoperands[0] = operands[0];
3861 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3864 if (GET_CODE (operands[0]) == REG)
3865 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3867 operands[0] = adj_offsettable_operand (operands[0], 4);
3868 switch (INTVAL (lo))
3873 output_asm_insn (\"not%.l %0\", operands);
3876 /* FIXME : a scratch register would be welcome here if
3877 -128 <= INTVAL (lo) < -1 */
3879 /* FIXME : this should be merged with xorsi3 */
3883 xoperands[0] = operands[0];
3885 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3890 if (GET_CODE (operands[0]) != REG)
3892 operands[1] = adj_offsettable_operand (operands[0], 4);
3893 return \"eor%.l %2,%0\;eor%.l %R2,%1\";
3895 if (GET_CODE (operands[2]) != REG)
3897 operands[1] = adj_offsettable_operand (operands[2], 4);
3898 return \"eor%.l %2,%0\;eor%.l %1,%R0\";
3900 return \"eor%.l %2,%0\;eor%.l %R2,%R0\";
3903 (define_expand "xorsi3"
3904 [(set (match_operand:SI 0 "general_operand" "")
3905 (xor:SI (match_operand:SI 1 "general_operand" "")
3906 (match_operand:SI 2 "general_operand" "")))]
3910 (define_insn "xorsi3_internal"
3911 [(set (match_operand:SI 0 "general_operand" "=do,m")
3912 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3913 (match_operand:SI 2 "general_operand" "di,dKs")))]
3917 return output_xorsi3 (operands);
3920 (define_insn "xorsi3_5200"
3921 [(set (match_operand:SI 0 "general_operand" "=dm,d")
3922 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3923 (match_operand:SI 2 "general_operand" "d,Ks")))]
3927 (define_insn "xorhi3"
3928 [(set (match_operand:HI 0 "general_operand" "=dm")
3929 (xor:HI (match_operand:HI 1 "general_operand" "%0")
3930 (match_operand:HI 2 "general_operand" "dn")))]
3935 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3936 (xor:HI (match_dup 0)
3937 (match_operand:HI 1 "general_operand" "dn")))]
3942 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3943 (xor:HI (match_operand:HI 1 "general_operand" "dn")
3948 (define_insn "xorqi3"
3949 [(set (match_operand:QI 0 "general_operand" "=dm")
3950 (xor:QI (match_operand:QI 1 "general_operand" "%0")
3951 (match_operand:QI 2 "general_operand" "dn")))]
3956 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
3957 (xor:QI (match_dup 0)
3958 (match_operand:QI 1 "general_operand" "dn")))]
3963 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
3964 (xor:QI (match_operand:QI 1 "general_operand" "dn")
3969 ;; negation instructions
3971 (define_expand "negdi2"
3972 [(set (match_operand:DI 0 "general_operand" "")
3973 (neg:DI (match_operand:DI 1 "general_operand" "")))]
3978 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
3980 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
3984 (define_insn "negdi2_internal"
3985 [(set (match_operand:DI 0 "general_operand" "=<,do,!*a")
3986 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
3990 if (which_alternative == 0)
3991 return \"neg%.l %0\;negx%.l %0\";
3992 if (GET_CODE (operands[0]) == REG)
3993 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3995 operands[1] = adj_offsettable_operand (operands[0], 4);
3996 if (ADDRESS_REG_P (operands[0]))
3997 return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
3999 return \"neg%.l %1\;negx%.l %0\";
4002 (define_insn "negdi2_5200"
4003 [(set (match_operand:DI 0 "general_operand" "=d")
4004 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
4008 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4009 return \"neg%.l %1\;negx%.l %0\";
4012 (define_expand "negsi2"
4013 [(set (match_operand:SI 0 "general_operand" "")
4014 (neg:SI (match_operand:SI 1 "general_operand" "")))]
4019 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
4021 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
4025 (define_insn "negsi2_internal"
4026 [(set (match_operand:SI 0 "general_operand" "=dm")
4027 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4031 (define_insn "negsi2_5200"
4032 [(set (match_operand:SI 0 "general_operand" "=d")
4033 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4037 (define_insn "neghi2"
4038 [(set (match_operand:HI 0 "general_operand" "=dm")
4039 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
4044 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4045 (neg:HI (match_dup 0)))]
4049 (define_insn "negqi2"
4050 [(set (match_operand:QI 0 "general_operand" "=dm")
4051 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
4056 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4057 (neg:QI (match_dup 0)))]
4061 ;; If using software floating point, just flip the sign bit.
4063 (define_expand "negsf2"
4064 [(set (match_operand:SF 0 "general_operand" "")
4065 (neg:SF (match_operand:SF 1 "general_operand" "")))]
4069 if (!TARGET_FPA && !TARGET_68881)
4074 target = operand_subword_force (operands[0], 0, SFmode);
4075 result = expand_binop (SImode, xor_optab,
4076 operand_subword_force (operands[1], 0, SFmode),
4077 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
4081 if (result != target)
4082 emit_move_insn (result, target);
4084 /* Make a place for REG_EQUAL. */
4085 emit_move_insn (operands[0], operands[0]);
4091 [(set (match_operand:SF 0 "general_operand" "=x,y")
4092 (neg:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4097 [(set (match_operand:SF 0 "general_operand" "=f,d")
4098 (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))]
4102 if (DATA_REG_P (operands[0]))
4104 operands[1] = gen_rtx (CONST_INT, VOIDmode, 31);
4105 return \"bchg %1,%0\";
4107 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4108 return \"f%$neg%.x %1,%0\";
4109 return \"f%$neg%.s %f1,%0\";
4112 (define_expand "negdf2"
4113 [(set (match_operand:DF 0 "general_operand" "")
4114 (neg:DF (match_operand:DF 1 "general_operand" "")))]
4118 if (!TARGET_FPA && !TARGET_68881)
4125 target = operand_subword (operands[0], 0, 1, DFmode);
4126 result = expand_binop (SImode, xor_optab,
4127 operand_subword_force (operands[1], 0, DFmode),
4128 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
4132 if (result != target)
4133 emit_move_insn (result, target);
4135 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4136 operand_subword_force (operands[1], 1, DFmode));
4138 insns = get_insns ();
4141 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4147 [(set (match_operand:DF 0 "general_operand" "=x,y")
4148 (neg:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4153 [(set (match_operand:DF 0 "general_operand" "=f,d")
4154 (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
4158 if (DATA_REG_P (operands[0]))
4160 operands[1] = gen_rtx (CONST_INT, VOIDmode, 31);
4161 return \"bchg %1,%0\";
4163 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4164 return \"f%&neg%.x %1,%0\";
4165 return \"f%&neg%.d %f1,%0\";
4168 ;; Sqrt instruction for the 68881
4170 (define_insn "sqrtsf2"
4171 [(set (match_operand:SF 0 "general_operand" "=f")
4172 (sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
4176 if (FP_REG_P (operands[1]))
4177 return \"f%$sqrt%.x %1,%0\";
4179 return \"f%$sqrt%.s %1,%0\";
4182 (define_insn "sqrtdf2"
4183 [(set (match_operand:DF 0 "general_operand" "=f")
4184 (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
4188 if (FP_REG_P (operands[1]))
4189 return \"f%&sqrt%.x %1,%0\";
4191 return \"f%&sqrt%.d %1,%0\";
4194 ;; Absolute value instructions
4195 ;; If using software floating point, just zero the sign bit.
4197 (define_expand "abssf2"
4198 [(set (match_operand:SF 0 "general_operand" "")
4199 (abs:SF (match_operand:SF 1 "general_operand" "")))]
4203 if (!TARGET_FPA && !TARGET_68881)
4208 target = operand_subword_force (operands[0], 0, SFmode);
4209 result = expand_binop (SImode, and_optab,
4210 operand_subword_force (operands[1], 0, SFmode),
4211 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
4215 if (result != target)
4216 emit_move_insn (result, target);
4218 /* Make a place for REG_EQUAL. */
4219 emit_move_insn (operands[0], operands[0]);
4225 [(set (match_operand:SF 0 "general_operand" "=x,y")
4226 (abs:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4231 [(set (match_operand:SF 0 "general_operand" "=f")
4232 (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
4236 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4237 return \"f%$abs%.x %1,%0\";
4238 return \"f%$abs%.s %f1,%0\";
4241 (define_expand "absdf2"
4242 [(set (match_operand:DF 0 "general_operand" "")
4243 (abs:DF (match_operand:DF 1 "general_operand" "")))]
4247 if (!TARGET_FPA && !TARGET_68881)
4254 target = operand_subword (operands[0], 0, 1, DFmode);
4255 result = expand_binop (SImode, and_optab,
4256 operand_subword_force (operands[1], 0, DFmode),
4257 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
4261 if (result != target)
4262 emit_move_insn (result, target);
4264 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4265 operand_subword_force (operands[1], 1, DFmode));
4267 insns = get_insns ();
4270 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4276 [(set (match_operand:DF 0 "general_operand" "=x,y")
4277 (abs:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4282 [(set (match_operand:DF 0 "general_operand" "=f")
4283 (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
4287 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4288 return \"f%&abs%.x %1,%0\";
4289 return \"f%&abs%.d %f1,%0\";
4292 ;; one complement instructions
4294 ;; "one_cmpldi2" is mainly here to help combine().
4295 (define_insn "one_cmpldi2"
4296 [(set (match_operand:DI 0 "general_operand" "=dm")
4297 (not:DI (match_operand:DI 1 "general_operand" "0")))]
4302 if (GET_CODE (operands[0]) == REG)
4303 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4304 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
4305 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4306 operands[1] = operands[0];
4308 operands[1] = adj_offsettable_operand (operands[0], 4);
4309 return \"not%.l %1\;not%.l %0\";
4312 (define_expand "one_cmplsi2"
4313 [(set (match_operand:SI 0 "general_operand" "")
4314 (not:SI (match_operand:SI 1 "general_operand" "")))]
4319 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
4321 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
4325 (define_insn "one_cmplsi2_internal"
4326 [(set (match_operand:SI 0 "general_operand" "=dm")
4327 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4331 (define_insn "one_cmplsi2_5200"
4332 [(set (match_operand:SI 0 "general_operand" "=d")
4333 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4337 (define_insn "one_cmplhi2"
4338 [(set (match_operand:HI 0 "general_operand" "=dm")
4339 (not:HI (match_operand:HI 1 "general_operand" "0")))]
4344 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4345 (not:HI (match_dup 0)))]
4349 (define_insn "one_cmplqi2"
4350 [(set (match_operand:QI 0 "general_operand" "=dm")
4351 (not:QI (match_operand:QI 1 "general_operand" "0")))]
4356 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4357 (not:QI (match_dup 0)))]
4361 ;; arithmetic shift instructions
4362 ;; We don't need the shift memory by 1 bit instruction
4364 (define_insn "ashldi_extsi"
4365 [(set (match_operand:DI 0 "general_operand" "=ro")
4367 (match_operator:DI 2 "extend_operator"
4368 [(match_operand:SI 1 "general_operand" "rm")])
4374 if (GET_CODE (operands[0]) == REG)
4375 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4377 operands[2] = adj_offsettable_operand (operands[0], 4);
4378 if (ADDRESS_REG_P (operands[0]))
4379 return \"move%.l %1,%0\;sub%.l %2,%2\";
4381 return \"move%.l %1,%0\;clr%.l %2\";
4384 (define_insn "ashldi_sexthi"
4385 [(set (match_operand:DI 0 "general_operand" "=m,a*d")
4386 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
4388 (clobber (match_scratch:SI 2 "=a,X"))]
4393 if (GET_CODE (operands[0]) == MEM)
4395 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4396 return \"clr%.l %0\;move%.w %1,%2\;move%.l %2,%0\";
4397 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4398 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %0\";
4401 operands[3] = adj_offsettable_operand (operands[0], 4);
4402 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %3\";
4405 else if (DATA_REG_P (operands[0]))
4406 return \"move%.w %1,%0\;ext%.l %0\;clr%.l %R0\";
4408 return \"move%.w %1,%0\;sub%.l %R0,%R0\";
4411 (define_insn "ashldi_const32"
4412 [(set (match_operand:DI 0 "general_operand" "=rm")
4413 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
4419 if (GET_CODE (operands[1]) == REG)
4420 operands[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4422 operands[3] = adj_offsettable_operand (operands[1], 4);
4423 if (GET_CODE (operands[0]) == REG)
4424 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4425 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4426 return \"clr%.l %0\;move%.l %3,%0\";
4427 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4428 return \"move%.l %3,%0\;clr%.l %0\";
4430 operands[2] = adj_offsettable_operand (operands[0], 4);
4431 if (ADDRESS_REG_P (operands[2]))
4432 return \"move%.l %3,%0\;sub%.l %2,%2\";
4434 return \"move%.l %3,%0\;clr%.l %2\";
4437 ;; The predicate below must be general_operand, because ashldi3 allows that
4438 (define_insn "ashldi_const"
4439 [(set (match_operand:DI 0 "general_operand" "=d")
4440 (ashift:DI (match_operand:DI 1 "general_operand" "0")
4441 (match_operand 2 "const_int_operand" "n")))]
4442 "(INTVAL (operands[2]) == 1
4443 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4444 || INTVAL (operands[2]) == 2 || INTVAL (operands[2]) == 3)"
4447 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4448 if (INTVAL (operands[2]) == 1)
4449 return \"add%.l %1,%1\;addx%.l %0,%0\";
4450 else if (INTVAL (operands[2]) == 8)
4451 return \"rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1\";
4452 else if (INTVAL (operands[2]) == 16)
4453 return \"swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1\";
4454 else if (INTVAL (operands[2]) == 2)
4455 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4456 else/* if (INTVAL (operands[2]) == 3)*/
4457 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4460 (define_expand "ashldi3"
4461 [(set (match_operand:DI 0 "general_operand" "")
4462 (ashift:DI (match_operand:DI 1 "general_operand" "")
4463 (match_operand 2 "const_int_operand" "")))]
4467 if (GET_CODE (operands[2]) != CONST_INT
4468 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 32
4469 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4470 && INTVAL (operands[2]) != 2 && INTVAL (operands[2]) != 3))
4474 ;; On most 68k models, this makes faster code in a special case.
4476 (define_insn "ashlsi_16"
4477 [(set (match_operand:SI 0 "register_operand" "=d")
4478 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4484 return \"swap %0\;clr%.w %0\";
4487 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
4488 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
4490 ;; On the 68000, this makes faster code in a special case.
4492 (define_insn "ashlsi_17_24"
4493 [(set (match_operand:SI 0 "register_operand" "=d")
4494 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4495 (match_operand:SI 2 "const_int_operand" "n")))]
4496 "(! TARGET_68020 && !TARGET_5200
4497 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4502 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4503 return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\";
4506 (define_insn "ashlsi3"
4507 [(set (match_operand:SI 0 "register_operand" "=d")
4508 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4509 (match_operand:SI 2 "general_operand" "dI")))]
4513 if (operands[2] == const1_rtx)
4515 cc_status.flags = CC_NO_OVERFLOW;
4516 return \"add%.l %0,%0\";
4518 return \"lsl%.l %2,%0\";
4521 (define_insn "ashlhi3"
4522 [(set (match_operand:HI 0 "register_operand" "=d")
4523 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4524 (match_operand:HI 2 "general_operand" "dI")))]
4529 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4530 (ashift:HI (match_dup 0)
4531 (match_operand:HI 1 "general_operand" "dI")))]
4535 (define_insn "ashlqi3"
4536 [(set (match_operand:QI 0 "register_operand" "=d")
4537 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4538 (match_operand:QI 2 "general_operand" "dI")))]
4543 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4544 (ashift:QI (match_dup 0)
4545 (match_operand:QI 1 "general_operand" "dI")))]
4549 ;; On most 68k models, this makes faster code in a special case.
4551 (define_insn "ashrsi_16"
4552 [(set (match_operand:SI 0 "register_operand" "=d")
4553 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4556 "swap %0\;ext%.l %0")
4558 ;; On the 68000, this makes faster code in a special case.
4561 [(set (match_operand:SI 0 "register_operand" "=d")
4562 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4563 (match_operand:SI 2 "const_int_operand" "n")))]
4564 "(! TARGET_68020 && !TARGET_5200
4565 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4568 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4569 return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
4572 (define_insn "subreghi1ashrdi_const32"
4573 [(set (match_operand:HI 0 "general_operand" "=rm")
4574 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4575 (const_int 32)) 1))]
4579 if (GET_CODE (operands[1]) != REG)
4580 operands[1] = adj_offsettable_operand (operands[1], 2);
4581 return \"move%.w %1,%0\";
4584 (define_insn "subregsi1ashrdi_const32"
4585 [(set (match_operand:SI 0 "general_operand" "=rm")
4586 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4587 (const_int 32)) 1))]
4591 return \"move%.l %1,%0\";
4594 (define_insn "ashrdi_const32"
4595 [(set (match_operand:DI 0 "register_operand" "=d")
4596 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4602 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4604 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
4606 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
4609 (define_insn "ashrdi_const32_mem"
4610 [(set (match_operand:DI 0 "general_operand" "=o,<")
4611 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro")
4613 (clobber (match_scratch:SI 2 "=d,d"))]
4618 if (which_alternative == 1)
4619 operands[3] = operands[0];
4621 operands[3] = adj_offsettable_operand (operands[0], 4);
4623 return \"move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0\";
4625 return \"move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\";
4628 ;; The predicate below must be general_operand, because ashrdi3 allows that
4629 (define_insn "ashrdi_const"
4630 [(set (match_operand:DI 0 "general_operand" "=d")
4631 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
4632 (match_operand 2 "const_int_operand" "n")))]
4634 && ((INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == 2
4635 || INTVAL (operands[2]) == 3 || INTVAL (operands[2]) == 8
4636 || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 31
4637 || INTVAL (operands[2]) == 63))"
4640 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4641 if (INTVAL (operands[2]) == 63)
4642 return \"add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1\";
4644 if (INTVAL (operands[2]) == 1)
4645 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
4646 else if (INTVAL (operands[2]) == 8)
4647 return \"move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1\";
4648 else if (INTVAL (operands[2]) == 16)
4649 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;ext%.l %0\";
4650 else if (INTVAL (operands[2]) == 31)
4651 return \"add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0\";
4652 else if (INTVAL (operands[2]) == 2)
4653 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4654 else/* if (INTVAL (operands[2]) == 3)*/
4655 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4658 (define_expand "ashrdi3"
4659 [(set (match_operand:DI 0 "general_operand" "")
4660 (ashiftrt:DI (match_operand:DI 1 "general_operand" "")
4661 (match_operand 2 "const_int_operand" "")))]
4665 if (GET_CODE (operands[2]) != CONST_INT
4666 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 2
4667 && INTVAL (operands[2]) != 3 && INTVAL (operands[2]) != 8
4668 && INTVAL (operands[2]) != 16 && INTVAL (operands[2]) != 31
4669 && INTVAL (operands[2]) != 32 && INTVAL (operands[2]) != 63))
4673 ;; On all 68k models, this makes faster code in a special case.
4675 (define_insn "ashrsi_31"
4676 [(set (match_operand:SI 0 "register_operand" "=d")
4677 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4682 return \"add%.l %0,%0\;subx%.l %0,%0\";
4685 (define_insn "ashrsi3"
4686 [(set (match_operand:SI 0 "register_operand" "=d")
4687 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4688 (match_operand:SI 2 "general_operand" "dI")))]
4692 (define_insn "ashrhi3"
4693 [(set (match_operand:HI 0 "register_operand" "=d")
4694 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4695 (match_operand:HI 2 "general_operand" "dI")))]
4700 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4701 (ashiftrt:HI (match_dup 0)
4702 (match_operand:HI 1 "general_operand" "dI")))]
4706 (define_insn "ashrqi3"
4707 [(set (match_operand:QI 0 "register_operand" "=d")
4708 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4709 (match_operand:QI 2 "general_operand" "dI")))]
4714 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4715 (ashiftrt:QI (match_dup 0)
4716 (match_operand:QI 1 "general_operand" "dI")))]
4720 ;; logical shift instructions
4722 ;; commented out because of reload problems in 950612-1.c
4725 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4726 ;; (const_int 32)) 1))
4727 ;; (set (match_operand:SI 1 "general_operand" "=dm")
4728 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
4729 ;; (const_int 32)) 1))]
4733 ;; return \"move%.l %0,%1\";
4738 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4739 ;; (const_int 32)) 0))
4740 ;; (set (match_operand:DI 1 "general_operand" "=do")
4741 ;; (lshiftrt:DI (match_dup 0)
4742 ;; (const_int 32)))]
4746 ;; if (GET_CODE (operands[1]) == REG)
4747 ;; operands[2] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4749 ;; operands[2] = adj_offsettable_operand (operands[1], 4);
4750 ;; return \"move%.l %0,%2\;clr%.l %1\";
4753 (define_insn "subreg1lshrdi_const32"
4754 [(set (match_operand:SI 0 "general_operand" "=rm")
4755 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4756 (const_int 32)) 1))]
4760 return \"move%.l %1,%0\";
4763 (define_insn "lshrdi_const32"
4764 [(set (match_operand:DI 0 "general_operand" "=ro,<,>")
4765 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
4771 if (which_alternative == 1)
4772 return \"move%.l %1,%0\;clr%.l %0\";
4773 if (which_alternative == 2)
4774 return \"clr%.l %0\;move%.l %1,%0\";
4775 if (GET_CODE (operands[0]) == REG)
4776 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4778 operands[2] = adj_offsettable_operand (operands[0], 4);
4779 if (GET_CODE (operands[1]) == REG)
4780 operands[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4782 operands[3] = adj_offsettable_operand (operands[1], 4);
4783 if (ADDRESS_REG_P (operands[0]))
4784 return \"move%.l %1,%2\;sub%.l %0,%0\";
4786 return \"move%.l %1,%2\;clr%.l %0\";
4789 ;; The predicate below must be general_operand, because lshrdi3 allows that
4790 (define_insn "lshrdi_const"
4791 [(set (match_operand:DI 0 "general_operand" "=d")
4792 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
4793 (match_operand 2 "const_int_operand" "n")))]
4795 && ((INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == 2
4796 || INTVAL (operands[2]) == 3 || INTVAL (operands[2]) == 8
4797 || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 63))"
4800 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4801 if (INTVAL (operands[2]) == 63)
4802 return \"add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1\";
4804 if (INTVAL (operands[2]) == 1)
4805 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4806 else if (INTVAL (operands[2]) == 8)
4807 return \"move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1\";
4808 else if (INTVAL (operands[2]) == 16)
4809 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0\";
4810 else if (INTVAL (operands[2]) == 2)
4811 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4812 else /*if (INTVAL (operands[2]) == 3)*/
4813 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4816 (define_expand "lshrdi3"
4817 [(set (match_operand:DI 0 "general_operand" "")
4818 (lshiftrt:DI (match_operand:DI 1 "general_operand" "")
4819 (match_operand 2 "const_int_operand" "")))]
4823 if (GET_CODE (operands[2]) != CONST_INT
4824 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 2
4825 && INTVAL (operands[2]) != 3 && INTVAL (operands[2]) != 8
4826 && INTVAL (operands[2]) != 16 && INTVAL (operands[2]) != 32
4827 && INTVAL (operands[2]) != 63))
4831 ;; On all 68k models, this makes faster code in a special case.
4833 (define_insn "lshrsi_31"
4834 [(set (match_operand:SI 0 "register_operand" "=d")
4835 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4840 return \"add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0\";
4843 ;; On most 68k models, this makes faster code in a special case.
4845 (define_insn "lshrsi_16"
4846 [(set (match_operand:SI 0 "register_operand" "=d")
4847 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4853 return \"clr%.w %0\;swap %0\";
4856 ;; On the 68000, this makes faster code in a special case.
4858 (define_insn "lshrsi_17_24"
4859 [(set (match_operand:SI 0 "register_operand" "=d")
4860 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4861 (match_operand:SI 2 "const_int_operand" "n")))]
4862 "(! TARGET_68020 && !TARGET_5200
4863 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4866 /* I think lsr%.w sets the CC properly. */
4867 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4868 return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\";
4871 (define_insn "lshrsi3"
4872 [(set (match_operand:SI 0 "register_operand" "=d")
4873 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4874 (match_operand:SI 2 "general_operand" "dI")))]
4878 (define_insn "lshrhi3"
4879 [(set (match_operand:HI 0 "register_operand" "=d")
4880 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
4881 (match_operand:HI 2 "general_operand" "dI")))]
4886 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4887 (lshiftrt:HI (match_dup 0)
4888 (match_operand:HI 1 "general_operand" "dI")))]
4892 (define_insn "lshrqi3"
4893 [(set (match_operand:QI 0 "register_operand" "=d")
4894 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
4895 (match_operand:QI 2 "general_operand" "dI")))]
4900 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4901 (lshiftrt:QI (match_dup 0)
4902 (match_operand:QI 1 "general_operand" "dI")))]
4906 ;; rotate instructions
4908 (define_insn "rotlsi3"
4909 [(set (match_operand:SI 0 "register_operand" "=d")
4910 (rotate:SI (match_operand:SI 1 "register_operand" "0")
4911 (match_operand:SI 2 "general_operand" "dINO")))]
4915 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
4917 else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
4919 operands[2] = gen_rtx (CONST_INT, VOIDmode, 32 - INTVAL (operands[2]));
4920 return \"ror%.l %2,%0\";
4923 return \"rol%.l %2,%0\";
4926 (define_insn "rotlhi3"
4927 [(set (match_operand:HI 0 "register_operand" "=d")
4928 (rotate:HI (match_operand:HI 1 "register_operand" "0")
4929 (match_operand:HI 2 "general_operand" "dIP")))]
4933 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
4935 operands[2] = gen_rtx (CONST_INT, VOIDmode, 16 - INTVAL (operands[2]));
4936 return \"ror%.w %2,%0\";
4939 return \"rol%.w %2,%0\";
4943 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4944 (rotate:HI (match_dup 0)
4945 (match_operand:HI 1 "general_operand" "dIP")))]
4949 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
4951 operands[2] = gen_rtx (CONST_INT, VOIDmode, 16 - INTVAL (operands[2]));
4952 return \"ror%.w %2,%0\";
4955 return \"rol%.w %2,%0\";
4958 (define_insn "rotlqi3"
4959 [(set (match_operand:QI 0 "register_operand" "=d")
4960 (rotate:QI (match_operand:QI 1 "register_operand" "0")
4961 (match_operand:QI 2 "general_operand" "dI")))]
4965 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
4967 operands[2] = gen_rtx (CONST_INT, VOIDmode, 8 - INTVAL (operands[2]));
4968 return \"ror%.b %2,%0\";
4971 return \"rol%.b %2,%0\";
4975 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4976 (rotate:QI (match_dup 0)
4977 (match_operand:QI 1 "general_operand" "dI")))]
4981 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
4983 operands[2] = gen_rtx (CONST_INT, VOIDmode, 8 - INTVAL (operands[2]));
4984 return \"ror%.b %2,%0\";
4987 return \"rol%.b %2,%0\";
4990 (define_insn "rotrsi3"
4991 [(set (match_operand:SI 0 "register_operand" "=d")
4992 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
4993 (match_operand:SI 2 "general_operand" "dI")))]
4997 (define_insn "rotrhi3"
4998 [(set (match_operand:HI 0 "register_operand" "=d")
4999 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
5000 (match_operand:HI 2 "general_operand" "dI")))]
5005 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5006 (rotatert:HI (match_dup 0)
5007 (match_operand:HI 1 "general_operand" "dI")))]
5011 (define_insn "rotrqi3"
5012 [(set (match_operand:QI 0 "register_operand" "=d")
5013 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
5014 (match_operand:QI 2 "general_operand" "dI")))]
5019 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5020 (rotatert:QI (match_dup 0)
5021 (match_operand:QI 1 "general_operand" "dI")))]
5026 ;; Bit set/clear in memory byte.
5028 ;; set bit, bit number is int
5029 (define_insn "bsetmemqi"
5030 [(set (match_operand:QI 0 "memory_operand" "+m")
5031 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5032 (match_operand:SI 1 "general_operand" "d")) 0)
5038 return \"bset %1,%0\";
5041 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
5043 [(set (match_operand:QI 0 "memory_operand" "+m")
5044 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5045 (match_operator:SI 2 "extend_operator"
5046 [(match_operand 1 "general_operand" "d")])) 0)
5052 return \"bset %1,%0\";
5055 ;; clear bit, bit number is int
5056 (define_insn "bclrmemqi"
5057 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5059 (minus:SI (const_int 7)
5060 (match_operand:SI 1 "general_operand" "d")))
5066 return \"bclr %1,%0\";
5069 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
5071 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5073 (minus:SI (const_int 7)
5074 (match_operator:SI 2 "extend_operator"
5075 [(match_operand 1 "general_operand" "d")])))
5081 return \"bclr %1,%0\";
5084 ;; Special cases of bit-field insns which we should
5085 ;; recognize in preference to the general case.
5086 ;; These handle aligned 8-bit and 16-bit fields,
5087 ;; which can usually be done with move instructions.
5090 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5091 ; alignment of structure members is specified.
5093 ; The move is allowed to be odd byte aligned, because that's still faster
5094 ; than an odd byte aligned bit field instruction.
5097 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5099 (match_operand:SI 2 "const_int_operand" "n"))
5100 (match_operand:SI 3 "general_operand" "rmi"))]
5101 "TARGET_68020 && TARGET_BITFIELD
5102 && (INTVAL (operands[2]) % 8) == 0
5103 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
5107 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
5109 return \"move%.l %3,%0\";
5113 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
5114 (match_operand:SI 1 "const_int_operand" "n")
5115 (match_operand:SI 2 "const_int_operand" "n"))
5116 (match_operand:SI 3 "register_operand" "d"))]
5117 "TARGET_68020 && TARGET_BITFIELD
5118 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
5119 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
5120 && (GET_CODE (operands[0]) == REG
5121 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
5124 if (REG_P (operands[0]))
5126 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
5127 return \"bfins %3,%0{%b2:%b1}\";
5131 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
5133 if (GET_CODE (operands[3]) == MEM)
5134 operands[3] = adj_offsettable_operand (operands[3],
5135 (32 - INTVAL (operands[1])) / 8);
5136 if (INTVAL (operands[1]) == 8)
5137 return \"move%.b %3,%0\";
5138 return \"move%.w %3,%0\";
5143 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5144 ; alignment of structure members is specified.
5146 ; The move is allowed to be odd byte aligned, because that's still faster
5147 ; than an odd byte aligned bit field instruction.
5150 [(set (match_operand:SI 0 "general_operand" "=rm")
5151 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o")
5153 (match_operand:SI 3 "const_int_operand" "n")))]
5154 "TARGET_68020 && TARGET_BITFIELD
5155 && (INTVAL (operands[3]) % 8) == 0
5156 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5160 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5162 return \"move%.l %1,%0\";
5166 [(set (match_operand:SI 0 "general_operand" "=&d")
5167 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
5168 (match_operand:SI 2 "const_int_operand" "n")
5169 (match_operand:SI 3 "const_int_operand" "n")))]
5170 "TARGET_68020 && TARGET_BITFIELD
5171 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5172 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5173 && (GET_CODE (operands[1]) == REG
5174 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5177 cc_status.flags |= CC_NOT_NEGATIVE;
5178 if (REG_P (operands[1]))
5180 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5181 return \"bfextu %1{%b3:%b2},%0\";
5185 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5187 output_asm_insn (\"clr%.l %0\", operands);
5188 if (GET_CODE (operands[0]) == MEM)
5189 operands[0] = adj_offsettable_operand (operands[0],
5190 (32 - INTVAL (operands[1])) / 8);
5191 if (INTVAL (operands[2]) == 8)
5192 return \"move%.b %1,%0\";
5193 return \"move%.w %1,%0\";
5197 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5198 ; alignment of structure members is specified.
5200 ; The move is allowed to be odd byte aligned, because that's still faster
5201 ; than an odd byte aligned bit field instruction.
5204 [(set (match_operand:SI 0 "general_operand" "=rm")
5205 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5207 (match_operand:SI 3 "const_int_operand" "n")))]
5208 "TARGET_68020 && TARGET_BITFIELD
5209 && (INTVAL (operands[3]) % 8) == 0
5210 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5214 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5216 return \"move%.l %1,%0\";
5220 [(set (match_operand:SI 0 "general_operand" "=d")
5221 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
5222 (match_operand:SI 2 "const_int_operand" "n")
5223 (match_operand:SI 3 "const_int_operand" "n")))]
5224 "TARGET_68020 && TARGET_BITFIELD
5225 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5226 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5227 && (GET_CODE (operands[1]) == REG
5228 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5231 if (REG_P (operands[1]))
5233 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5234 return \"bfexts %1{%b3:%b2},%0\";
5238 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5240 if (INTVAL (operands[2]) == 8)
5241 return \"move%.b %1,%0\;extb%.l %0\";
5242 return \"move%.w %1,%0\;ext%.l %0\";
5245 ;; Bit field instructions, general cases.
5246 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
5247 ;; so that its address is reloaded.
5249 (define_expand "extv"
5250 [(set (match_operand:SI 0 "general_operand" "")
5251 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
5252 (match_operand:SI 2 "general_operand" "")
5253 (match_operand:SI 3 "general_operand" "")))]
5254 "TARGET_68020 && TARGET_BITFIELD"
5258 [(set (match_operand:SI 0 "general_operand" "=d")
5259 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5260 (match_operand:SI 2 "general_operand" "di")
5261 (match_operand:SI 3 "general_operand" "di")))]
5262 "TARGET_68020 && TARGET_BITFIELD"
5263 "bfexts %1{%b3:%b2},%0")
5265 (define_expand "extzv"
5266 [(set (match_operand:SI 0 "general_operand" "")
5267 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
5268 (match_operand:SI 2 "general_operand" "")
5269 (match_operand:SI 3 "general_operand" "")))]
5270 "TARGET_68020 && TARGET_BITFIELD"
5274 [(set (match_operand:SI 0 "general_operand" "=d,d")
5275 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
5276 (match_operand:SI 2 "general_operand" "di,di")
5277 (match_operand:SI 3 "general_operand" "di,di")))]
5278 "TARGET_68020 && TARGET_BITFIELD"
5281 if (GET_CODE (operands[2]) == CONST_INT)
5283 if (INTVAL (operands[2]) != 32)
5284 cc_status.flags |= CC_NOT_NEGATIVE;
5290 return \"bfextu %1{%b3:%b2},%0\";
5294 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5295 (match_operand:SI 1 "general_operand" "di")
5296 (match_operand:SI 2 "general_operand" "di"))
5297 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
5298 (match_operand 3 "const_int_operand" "n")))]
5299 "TARGET_68020 && TARGET_BITFIELD
5300 && (INTVAL (operands[3]) == -1
5301 || (GET_CODE (operands[1]) == CONST_INT
5302 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
5306 return \"bfchg %0{%b2:%b1}\";
5310 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5311 (match_operand:SI 1 "general_operand" "di")
5312 (match_operand:SI 2 "general_operand" "di"))
5314 "TARGET_68020 && TARGET_BITFIELD"
5318 return \"bfclr %0{%b2:%b1}\";
5322 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5323 (match_operand:SI 1 "general_operand" "di")
5324 (match_operand:SI 2 "general_operand" "di"))
5326 "TARGET_68020 && TARGET_BITFIELD"
5330 return \"bfset %0{%b2:%b1}\";
5333 (define_expand "insv"
5334 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
5335 (match_operand:SI 1 "general_operand" "")
5336 (match_operand:SI 2 "general_operand" ""))
5337 (match_operand:SI 3 "register_operand" ""))]
5338 "TARGET_68020 && TARGET_BITFIELD"
5342 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5343 (match_operand:SI 1 "general_operand" "di")
5344 (match_operand:SI 2 "general_operand" "di"))
5345 (match_operand:SI 3 "register_operand" "d"))]
5346 "TARGET_68020 && TARGET_BITFIELD"
5347 "bfins %3,%0{%b2:%b1}")
5349 ;; Now recognize bit field insns that operate on registers
5350 ;; (or at least were intended to do so).
5353 [(set (match_operand:SI 0 "general_operand" "=d")
5354 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5355 (match_operand:SI 2 "general_operand" "di")
5356 (match_operand:SI 3 "general_operand" "di")))]
5357 "TARGET_68020 && TARGET_BITFIELD"
5358 "bfexts %1{%b3:%b2},%0")
5361 [(set (match_operand:SI 0 "general_operand" "=d")
5362 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5363 (match_operand:SI 2 "general_operand" "di")
5364 (match_operand:SI 3 "general_operand" "di")))]
5365 "TARGET_68020 && TARGET_BITFIELD"
5368 if (GET_CODE (operands[2]) == CONST_INT)
5370 if (INTVAL (operands[2]) != 32)
5371 cc_status.flags |= CC_NOT_NEGATIVE;
5377 return \"bfextu %1{%b3:%b2},%0\";
5381 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5382 (match_operand:SI 1 "general_operand" "di")
5383 (match_operand:SI 2 "general_operand" "di"))
5385 "TARGET_68020 && TARGET_BITFIELD"
5389 return \"bfclr %0{%b2:%b1}\";
5393 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5394 (match_operand:SI 1 "general_operand" "di")
5395 (match_operand:SI 2 "general_operand" "di"))
5397 "TARGET_68020 && TARGET_BITFIELD"
5401 return \"bfset %0{%b2:%b1}\";
5405 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5406 (match_operand:SI 1 "general_operand" "di")
5407 (match_operand:SI 2 "general_operand" "di"))
5408 (match_operand:SI 3 "register_operand" "d"))]
5409 "TARGET_68020 && TARGET_BITFIELD"
5413 /* These special cases are now recognized by a specific pattern. */
5414 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5415 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5416 return \"move%.w %3,%0\";
5417 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5418 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
5419 return \"move%.b %3,%0\";
5421 return \"bfins %3,%0{%b2:%b1}\";
5424 ;; Special patterns for optimizing bit-field instructions.
5428 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5429 (match_operand:SI 1 "const_int_operand" "n")
5430 (match_operand:SI 2 "general_operand" "di")))]
5431 "TARGET_68020 && TARGET_BITFIELD"
5434 if (operands[1] == const1_rtx
5435 && GET_CODE (operands[2]) == CONST_INT)
5437 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5438 return output_btst (operands,
5439 gen_rtx (CONST_INT, VOIDmode,
5440 width - INTVAL (operands[2])),
5443 /* Pass 1000 as SIGNPOS argument so that btst will
5444 not think we are testing the sign bit for an `and'
5445 and assume that nonzero implies a negative result. */
5447 if (INTVAL (operands[1]) != 32)
5448 cc_status.flags = CC_NOT_NEGATIVE;
5449 return \"bftst %0{%b2:%b1}\";
5453 ;;; now handle the register cases
5456 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5457 (match_operand:SI 1 "const_int_operand" "n")
5458 (match_operand:SI 2 "general_operand" "di")))]
5459 "TARGET_68020 && TARGET_BITFIELD"
5462 if (operands[1] == const1_rtx
5463 && GET_CODE (operands[2]) == CONST_INT)
5465 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5466 return output_btst (operands,
5467 gen_rtx (CONST_INT, VOIDmode,
5468 width - INTVAL (operands[2])),
5471 /* Pass 1000 as SIGNPOS argument so that btst will
5472 not think we are testing the sign bit for an `and'
5473 and assume that nonzero implies a negative result. */
5475 if (INTVAL (operands[1]) != 32)
5476 cc_status.flags = CC_NOT_NEGATIVE;
5477 return \"bftst %0{%b2:%b1}\";
5480 (define_insn "scc0_di"
5481 [(set (match_operand:QI 0 "general_operand" "=dm")
5482 (match_operator 1 "valid_dbcc_comparison_p"
5483 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5487 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5490 (define_insn "scc0_di_5200"
5491 [(set (match_operand:QI 0 "general_operand" "=d")
5492 (match_operator 1 "valid_dbcc_comparison_p"
5493 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5497 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5500 (define_insn "scc_di"
5501 [(set (match_operand:QI 0 "general_operand" "=dm,dm")
5502 (match_operator 1 "valid_dbcc_comparison_p"
5503 [(match_operand:DI 2 "general_operand" "ro,r")
5504 (match_operand:DI 3 "general_operand" "r,ro")]))]
5508 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5511 (define_insn "scc_di_5200"
5512 [(set (match_operand:QI 0 "general_operand" "=d,d")
5513 (match_operator 1 "valid_dbcc_comparison_p"
5514 [(match_operand:DI 2 "general_operand" "ro,r")
5515 (match_operand:DI 3 "general_operand" "r,ro")]))]
5519 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5522 (define_expand "seq"
5523 [(set (match_operand:QI 0 "general_operand" "")
5524 (eq:QI (cc0) (const_int 0)))]
5528 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5530 m68k_last_compare_had_fp_operands = 0;
5536 [(set (match_operand:QI 0 "general_operand" "=dm")
5537 (eq:QI (cc0) (const_int 0)))]
5540 cc_status = cc_prev_status;
5541 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5545 [(set (match_operand:QI 0 "general_operand" "=d")
5546 (eq:QI (cc0) (const_int 0)))]
5549 cc_status = cc_prev_status;
5550 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5553 (define_expand "sne"
5554 [(set (match_operand:QI 0 "general_operand" "")
5555 (ne:QI (cc0) (const_int 0)))]
5559 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5561 m68k_last_compare_had_fp_operands = 0;
5567 [(set (match_operand:QI 0 "general_operand" "=dm")
5568 (ne:QI (cc0) (const_int 0)))]
5571 cc_status = cc_prev_status;
5572 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5576 [(set (match_operand:QI 0 "general_operand" "=d")
5577 (ne:QI (cc0) (const_int 0)))]
5580 cc_status = cc_prev_status;
5581 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5584 (define_expand "sgt"
5585 [(set (match_operand:QI 0 "general_operand" "")
5586 (gt:QI (cc0) (const_int 0)))]
5590 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5592 m68k_last_compare_had_fp_operands = 0;
5598 [(set (match_operand:QI 0 "general_operand" "=dm")
5599 (gt:QI (cc0) (const_int 0)))]
5602 cc_status = cc_prev_status;
5603 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5607 [(set (match_operand:QI 0 "general_operand" "=d")
5608 (gt:QI (cc0) (const_int 0)))]
5611 cc_status = cc_prev_status;
5612 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5615 (define_expand "sgtu"
5616 [(set (match_operand:QI 0 "general_operand" "")
5617 (gtu:QI (cc0) (const_int 0)))]
5622 [(set (match_operand:QI 0 "general_operand" "=dm")
5623 (gtu:QI (cc0) (const_int 0)))]
5625 "* cc_status = cc_prev_status;
5626 return \"shi %0\"; ")
5629 [(set (match_operand:QI 0 "general_operand" "=d")
5630 (gtu:QI (cc0) (const_int 0)))]
5632 "* cc_status = cc_prev_status;
5633 return \"shi %0\"; ")
5635 (define_expand "slt"
5636 [(set (match_operand:QI 0 "general_operand" "")
5637 (lt:QI (cc0) (const_int 0)))]
5641 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5643 m68k_last_compare_had_fp_operands = 0;
5649 [(set (match_operand:QI 0 "general_operand" "=dm")
5650 (lt:QI (cc0) (const_int 0)))]
5652 "* cc_status = cc_prev_status;
5653 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5656 [(set (match_operand:QI 0 "general_operand" "=d")
5657 (lt:QI (cc0) (const_int 0)))]
5659 "* cc_status = cc_prev_status;
5660 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5662 (define_expand "sltu"
5663 [(set (match_operand:QI 0 "general_operand" "")
5664 (ltu:QI (cc0) (const_int 0)))]
5669 [(set (match_operand:QI 0 "general_operand" "=dm")
5670 (ltu:QI (cc0) (const_int 0)))]
5672 "* cc_status = cc_prev_status;
5673 return \"scs %0\"; ")
5676 [(set (match_operand:QI 0 "general_operand" "=d")
5677 (ltu:QI (cc0) (const_int 0)))]
5679 "* cc_status = cc_prev_status;
5680 return \"scs %0\"; ")
5682 (define_expand "sge"
5683 [(set (match_operand:QI 0 "general_operand" "")
5684 (ge:QI (cc0) (const_int 0)))]
5688 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5690 m68k_last_compare_had_fp_operands = 0;
5696 [(set (match_operand:QI 0 "general_operand" "=dm")
5697 (ge:QI (cc0) (const_int 0)))]
5699 "* cc_status = cc_prev_status;
5700 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5703 [(set (match_operand:QI 0 "general_operand" "=d")
5704 (ge:QI (cc0) (const_int 0)))]
5706 "* cc_status = cc_prev_status;
5707 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5709 (define_expand "sgeu"
5710 [(set (match_operand:QI 0 "general_operand" "")
5711 (geu:QI (cc0) (const_int 0)))]
5716 [(set (match_operand:QI 0 "general_operand" "=dm")
5717 (geu:QI (cc0) (const_int 0)))]
5719 "* cc_status = cc_prev_status;
5720 return \"scc %0\"; ")
5723 [(set (match_operand:QI 0 "general_operand" "=d")
5724 (geu:QI (cc0) (const_int 0)))]
5726 "* cc_status = cc_prev_status;
5727 return \"scc %0\"; ")
5729 (define_expand "sle"
5730 [(set (match_operand:QI 0 "general_operand" "")
5731 (le:QI (cc0) (const_int 0)))]
5735 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5737 m68k_last_compare_had_fp_operands = 0;
5743 [(set (match_operand:QI 0 "general_operand" "=dm")
5744 (le:QI (cc0) (const_int 0)))]
5747 cc_status = cc_prev_status;
5748 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5752 [(set (match_operand:QI 0 "general_operand" "=d")
5753 (le:QI (cc0) (const_int 0)))]
5756 cc_status = cc_prev_status;
5757 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5760 (define_expand "sleu"
5761 [(set (match_operand:QI 0 "general_operand" "")
5762 (leu:QI (cc0) (const_int 0)))]
5767 [(set (match_operand:QI 0 "general_operand" "=dm")
5768 (leu:QI (cc0) (const_int 0)))]
5770 "* cc_status = cc_prev_status;
5771 return \"sls %0\"; ")
5774 [(set (match_operand:QI 0 "general_operand" "=d")
5775 (leu:QI (cc0) (const_int 0)))]
5777 "* cc_status = cc_prev_status;
5778 return \"sls %0\"; ")
5780 ;; Basic conditional jump instructions.
5782 (define_insn "beq0_di"
5784 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
5786 (label_ref (match_operand 1 "" ","))
5788 (clobber (match_scratch:SI 2 "=d,d"))]
5793 if (which_alternative == 1)
5795 return \"move%.l %0,%2\;or%.l %0,%2\;jbeq %l1\";
5797 return \"move%.l %0,%2\;or%.l %0,%2\;jeq %l1\";
5799 if ((cc_prev_status.value1
5800 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5801 || (cc_prev_status.value2
5802 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5804 cc_status = cc_prev_status;
5806 return \"jbeq %l1\";
5811 if (GET_CODE (operands[0]) == REG)
5812 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
5814 operands[3] = adj_offsettable_operand (operands[0], 4);
5815 if (! ADDRESS_REG_P (operands[0]))
5818 return \"move%.l %0,%2\;or%.l %3,%2\;jbeq %l1\";
5820 return \"move%.l %0,%2\;or%.l %3,%2\;jeq %l1\";
5823 operands[4] = gen_label_rtx();
5824 if (TARGET_68020 || TARGET_5200)
5827 output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands);
5829 output_asm_insn (\"tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1\", operands);
5835 #ifdef SGS_CMP_ORDER
5836 output_asm_insn (\"cmp%.w %0,%#0\;jbne %l4\;cmp%.w %3,%#0\;jbeq %l1\", operands);
5838 output_asm_insn (\"cmp%.w %#0,%0\;jbne %l4\;cmp%.w %#0,%3\;jbeq %l1\", operands);
5841 output_asm_insn (\"cmp%.w %#0,%0\;jne %l4\;cmp%.w %#0,%3\;jeq %l1\", operands);
5844 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5845 CODE_LABEL_NUMBER (operands[4]));
5849 (define_insn "bne0_di"
5851 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
5853 (label_ref (match_operand 1 "" ","))
5855 (clobber (match_scratch:SI 2 "=d,X"))]
5859 if ((cc_prev_status.value1
5860 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5861 || (cc_prev_status.value2
5862 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5864 cc_status = cc_prev_status;
5866 return \"jbne %l1\";
5872 if (GET_CODE (operands[0]) == REG)
5873 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
5875 operands[3] = adj_offsettable_operand (operands[0], 4);
5876 if (!ADDRESS_REG_P (operands[0]))
5879 return \"move%.l %0,%2\;or%.l %3,%2\;jbne %l1\";
5881 return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\";
5884 if (TARGET_68020 || TARGET_5200)
5887 return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\";
5889 return \"tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1\";
5895 #ifdef SGS_CMP_ORDER
5896 return \"cmp%.w %0,%#0\;jbne %l1\;cmp%.w %3,%#0\;jbne %l1\";
5898 return \"cmp%.w %#0,%0\;jbne %l1\;cmp%.w %#0,%3\;jbne %l1\";
5901 return \"cmp%.w %#0,%0\;jne %l1\;cmp%.w %#0,%3\;jne %l1\";
5906 (define_insn "bge0_di"
5908 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
5910 (label_ref (match_operand 1 "" ""))
5915 if ((cc_prev_status.value1
5916 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5917 || (cc_prev_status.value2
5918 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5920 cc_status = cc_prev_status;
5921 if (cc_status.flags & CC_REVERSED)
5924 return \"jble %l1\";
5932 return \"jbpl %l1\";
5939 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
5940 output_asm_insn(\"tst%.l %0\", operands);
5943 /* On an address reg, cmpw may replace cmpl. */
5944 #ifdef SGS_CMP_ORDER
5945 output_asm_insn(\"cmp%.w %0,%#0\", operands);
5947 output_asm_insn(\"cmp%.w %#0,%0\", operands);
5952 return \"jbpl %l1\";
5958 (define_insn "blt0_di"
5960 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
5962 (label_ref (match_operand 1 "" ""))
5967 if ((cc_prev_status.value1
5968 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5969 || (cc_prev_status.value2
5970 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5972 cc_status = cc_prev_status;
5973 if (cc_status.flags & CC_REVERSED)
5976 return \"jbgt %l1\";
5984 return \"jbmi %l1\";
5991 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
5992 output_asm_insn(\"tst%.l %0\", operands);
5995 /* On an address reg, cmpw may replace cmpl. */
5996 #ifdef SGS_CMP_ORDER
5997 output_asm_insn(\"cmp%.w %0,%#0\", operands);
5999 output_asm_insn(\"cmp%.w %#0,%0\", operands);
6004 return \"jbmi %l1\";
6012 (if_then_else (eq (cc0)
6014 (label_ref (match_operand 0 "" ""))
6020 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6022 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6028 (if_then_else (ne (cc0)
6030 (label_ref (match_operand 0 "" ""))
6036 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6038 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6044 (if_then_else (gt (cc0)
6046 (label_ref (match_operand 0 "" ""))
6051 OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0);
6053 OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0);
6059 (if_then_else (gtu (cc0)
6061 (label_ref (match_operand 0 "" ""))
6066 return \"jbhi %l0\";
6074 (if_then_else (lt (cc0)
6076 (label_ref (match_operand 0 "" ""))
6081 OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\");
6083 OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\");
6089 (if_then_else (ltu (cc0)
6091 (label_ref (match_operand 0 "" ""))
6096 return \"jbcs %l0\";
6104 (if_then_else (ge (cc0)
6106 (label_ref (match_operand 0 "" ""))
6111 OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\");
6113 OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\");
6119 (if_then_else (geu (cc0)
6121 (label_ref (match_operand 0 "" ""))
6126 return \"jbcc %l0\";
6134 (if_then_else (le (cc0)
6136 (label_ref (match_operand 0 "" ""))
6141 OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0);
6143 OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0);
6149 (if_then_else (leu (cc0)
6151 (label_ref (match_operand 0 "" ""))
6156 return \"jbls %l0\";
6162 ;; Negated conditional jump instructions.
6166 (if_then_else (eq (cc0)
6169 (label_ref (match_operand 0 "" ""))))]
6174 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6176 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6182 (if_then_else (ne (cc0)
6185 (label_ref (match_operand 0 "" ""))))]
6190 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6192 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6198 (if_then_else (gt (cc0)
6201 (label_ref (match_operand 0 "" ""))))]
6205 OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0);
6207 OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0);
6213 (if_then_else (gtu (cc0)
6216 (label_ref (match_operand 0 "" ""))))]
6220 return \"jbls %l0\";
6228 (if_then_else (lt (cc0)
6231 (label_ref (match_operand 0 "" ""))))]
6235 OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\");
6237 OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\");
6243 (if_then_else (ltu (cc0)
6246 (label_ref (match_operand 0 "" ""))))]
6250 return \"jbcc %l0\";
6258 (if_then_else (ge (cc0)
6261 (label_ref (match_operand 0 "" ""))))]
6265 OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\");
6267 OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\");
6273 (if_then_else (geu (cc0)
6276 (label_ref (match_operand 0 "" ""))))]
6280 return \"jbcs %l0\";
6288 (if_then_else (le (cc0)
6291 (label_ref (match_operand 0 "" ""))))]
6295 OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0);
6297 OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0);
6303 (if_then_else (leu (cc0)
6306 (label_ref (match_operand 0 "" ""))))]
6310 return \"jbhi %l0\";
6316 ;; Unconditional and other jump instructions
6319 (label_ref (match_operand 0 "" "")))]
6323 return \"jbra %l0\";
6329 ;; We support two different ways of handling dispatch tables.
6330 ;; The NeXT uses absolute tables, and other machines use relative.
6331 ;; This define_expand can generate either kind.
6332 (define_expand "tablejump"
6333 [(parallel [(set (pc) (match_operand 0 "" ""))
6334 (use (label_ref (match_operand 1 "" "")))])]
6338 #ifdef CASE_VECTOR_PC_RELATIVE
6339 operands[0] = gen_rtx (PLUS, SImode, pc_rtx,
6340 gen_rtx (SIGN_EXTEND, SImode, operands[0]));
6344 ;; Jump to variable address from dispatch table of absolute addresses.
6346 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
6347 (use (label_ref (match_operand 1 "" "")))]
6351 return \"jmp (%0)\";
6357 ;; Jump to variable address from dispatch table of relative addresses.
6361 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
6362 (use (label_ref (match_operand 1 "" "")))]
6365 #ifdef ASM_RETURN_CASE_JUMP
6366 ASM_RETURN_CASE_JUMP;
6369 #ifdef ASM_OUTPUT_CASE_LABEL
6371 return \"ext%.l %0\;jmp 6(%%pc,%0.l)\";
6373 return \"jmp 6(%%pc,%0.w)\";
6378 return \"ext%.l %0\;jmp 2(pc,%0.l)\";
6380 return \"extl %0\;jmp 2(%%pc,%0.l)\";
6381 #endif /* end !CRDS */
6386 return \"jmp 2(pc,%0.w)\";
6388 return \"jmp 2(%%pc,%0.w)\";
6389 #endif /* end !CRDS */
6396 return \"ext%.l %0\;jmp (2,pc,%0.l)\";
6398 return \"extl %0\;jmp pc@(2,%0:l)\";
6404 return \"jmp (2,pc,%0.w)\";
6406 return \"jmp pc@(2,%0:w)\";
6413 ;; Decrement-and-branch insns.
6417 (ne (match_operand:HI 0 "general_operand" "+d*g")
6419 (label_ref (match_operand 1 "" ""))
6422 (plus:HI (match_dup 0)
6428 if (DATA_REG_P (operands[0]))
6429 return \"dbra %0,%l1\";
6430 if (GET_CODE (operands[0]) == MEM)
6434 return \"sub%.w %#1,%0\;jbcc %l1\";
6436 return \"subq%.w %#1,%0\;jbcc %l1\";
6438 #else /* not MOTOROLA */
6439 return \"subqw %#1,%0\;jcc %l1\";
6443 #ifdef SGS_CMP_ORDER
6445 return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6447 return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6449 #else /* not SGS_CMP_ORDER */
6450 return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
6452 #else /* not MOTOROLA */
6453 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6460 (ne (match_operand:SI 0 "general_operand" "+d*g")
6462 (label_ref (match_operand 1 "" ""))
6465 (plus:SI (match_dup 0)
6473 if (DATA_REG_P (operands[0]))
6474 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6475 if (GET_CODE (operands[0]) == MEM)
6476 return \"sub%.l %#1,%0\;jbcc %l1\";
6478 if (DATA_REG_P (operands[0]))
6479 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6480 if (GET_CODE (operands[0]) == MEM)
6481 return \"subq%.l %#1,%0\;jbcc %l1\";
6482 #endif /* NO_ADDSUB_Q */
6483 #ifdef SGS_CMP_ORDER
6485 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6487 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6489 #else /* not SGS_CMP_ORDER */
6490 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6491 #endif /* not SGS_CMP_ORDER */
6492 #else /* not MOTOROLA */
6493 if (DATA_REG_P (operands[0]))
6494 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6495 if (GET_CODE (operands[0]) == MEM)
6496 return \"subql %#1,%0\;jcc %l1\";
6497 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6498 #endif /* not MOTOROLA */
6501 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
6506 (ge (plus:HI (match_operand:HI 0 "general_operand" "+d*am")
6509 (label_ref (match_operand 1 "" ""))
6512 (plus:HI (match_dup 0)
6514 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6520 if (DATA_REG_P (operands[0]))
6521 return \"dbra %0,%l1\";
6522 if (GET_CODE (operands[0]) == MEM)
6523 return \"sub%.w %#1,%0\;jbcc %l1\";
6525 if (DATA_REG_P (operands[0]))
6526 return \"dbra %0,%l1\";
6527 if (GET_CODE (operands[0]) == MEM)
6528 return \"subq%.w %#1,%0\;jbcc %l1\";
6530 #ifdef SGS_CMP_ORDER
6532 return \"sub.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6534 return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6536 #else /* not SGS_CMP_ORDER */
6537 return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\";
6538 #endif /* not SGS_CMP_ORDER */
6539 #else /* not MOTOROLA */
6540 if (DATA_REG_P (operands[0]))
6541 return \"dbra %0,%l1\";
6542 if (GET_CODE (operands[0]) == MEM)
6543 return \"subqw %#1,%0\;jcc %l1\";
6544 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6545 #endif /* not MOTOROLA */
6548 (define_expand "decrement_and_branch_until_zero"
6549 [(parallel [(set (pc)
6551 (ge (plus:SI (match_operand:SI 0 "general_operand" "")
6554 (label_ref (match_operand 1 "" ""))
6557 (plus:SI (match_dup 0)
6565 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
6568 (label_ref (match_operand 1 "" ""))
6571 (plus:SI (match_dup 0)
6573 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6579 if (DATA_REG_P (operands[0]))
6580 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6581 if (GET_CODE (operands[0]) == MEM)
6582 return \"sub%.l %#1,%0\;jbcc %l1\";
6584 if (DATA_REG_P (operands[0]))
6585 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6586 if (GET_CODE (operands[0]) == MEM)
6587 return \"subq%.l %#1,%0\;jbcc %l1\";
6589 #ifdef SGS_CMP_ORDER
6591 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6593 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6595 #else /* not SGS_CMP_ORDER */
6596 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6597 #endif /* not SGS_CMP_ORDER */
6598 #else /* not MOTOROLA */
6599 if (DATA_REG_P (operands[0]))
6600 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6601 if (GET_CODE (operands[0]) == MEM)
6602 return \"subql %#1,%0\;jcc %l1\";
6603 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6604 #endif /* not MOTOROLA */
6608 ;; For PIC calls, in order to be able to support
6609 ;; dynamic linker LAZY BINDING, all the procedure calls need to go
6610 ;; through the PLT (Procedure Linkage Table) section in PIC mode.
6612 ;; PIC calls are handled by loading the address of the function into a
6613 ;; register (via movsi), then emitting a register indirect call using
6614 ;; the "jsr" function call syntax.
6616 ;; When outputting MIT syntax (e.g. on Suns), we add a bogus extra
6617 ;; operand to the jbsr statement to indicate that this call should
6618 ;; go through the PLT (why? because this is the way that Sun does it).
6620 ;; We have different patterns for PIC calls and non-PIC calls. The
6621 ;; different patterns are only used to choose the right syntax.
6623 ;; The svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it
6624 ;; will create the correct relocation entry (R_68K_PLT32) for `FUNC',
6625 ;; that tells the linker editor to create an entry for `FUNC' in PLT
6626 ;; section at link time. However, all global objects reference are still
6627 ;; done by using `OBJ@GOT'. So, the goal here is to output the function
6628 ;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'.
6629 ;; We need to have a way to differentiate these two different operands.
6631 ;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate
6632 ;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs
6633 ;; to be changed to recognize function calls symbol_ref operand as a valid
6634 ;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will
6635 ;; avoid the compiler to load this symbol_ref operand into a register.
6636 ;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly
6637 ;; since the value is a PC relative offset, not a real address.
6639 ;; All global objects are treated in the similar way as in SUN3. The only
6640 ;; difference is: on m68k svr4, the reference of such global object needs
6641 ;; to end with a suffix "@GOT" so the assembler and linker know to create
6642 ;; an entry for it in GOT (Global Offset Table) section. This is done in
6645 ;; Call subroutine with no return value.
6646 (define_expand "call"
6647 [(call (match_operand:QI 0 "memory_operand" "")
6648 (match_operand:SI 1 "general_operand" ""))]
6649 ;; Operand 1 not really used on the m68000.
6654 if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6655 SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
6658 ;; This is a normal call sequence.
6660 [(call (match_operand:QI 0 "memory_operand" "o")
6661 (match_operand:SI 1 "general_operand" "g"))]
6662 ;; Operand 1 not really used on the m68000.
6666 #if defined (MOTOROLA) && !defined (USE_GAS)
6668 if (GET_CODE (operands[0]) == MEM
6669 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6678 ;; This is a PIC call sequence.
6680 [(call (match_operand:QI 0 "memory_operand" "o")
6681 (match_operand:SI 1 "general_operand" "g"))]
6682 ;; Operand 1 not really used on the m68000.
6686 if (GET_CODE (operands[0]) == MEM
6687 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6690 return \"bsr.l %0\";
6693 return \"bsr.l %0@PLTPC\";
6695 return \"bsr %0@PLTPC\";
6699 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC,
6700 GAS just plain ignores it. */
6701 return \"jbsr %0,a1\";
6706 ;; Call subroutine, returning value in operand 0
6707 ;; (which must be a hard register).
6708 ;; See comments before "call" regarding PIC calls.
6709 (define_expand "call_value"
6710 [(set (match_operand 0 "" "")
6711 (call (match_operand:QI 1 "memory_operand" "")
6712 (match_operand:SI 2 "general_operand" "")))]
6713 ;; Operand 2 not really used on the m68000.
6717 if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6718 SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
6721 ;; This is a normal call_value
6723 [(set (match_operand 0 "" "=rf")
6724 (call (match_operand:QI 1 "memory_operand" "o")
6725 (match_operand:SI 2 "general_operand" "g")))]
6726 ;; Operand 2 not really used on the m68000.
6729 #if defined (MOTOROLA) && !defined (USE_GAS)
6731 if (GET_CODE (operands[1]) == MEM
6732 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6741 ;; This is a PIC call_value
6743 [(set (match_operand 0 "" "=rf")
6744 (call (match_operand:QI 1 "memory_operand" "o")
6745 (match_operand:SI 2 "general_operand" "g")))]
6746 ;; Operand 2 not really used on the m68000.
6749 if (GET_CODE (operands[1]) == MEM
6750 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6754 return \"bsr.l %1\";
6757 return \"bsr.l %1@PLTPC\";
6759 return \"bsr %1@PLTPC\";
6763 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC
6764 GAS just plain ignores it. */
6765 return \"jbsr %1,a1\";
6771 ;; Call subroutine returning any type.
6773 (define_expand "untyped_call"
6774 [(parallel [(call (match_operand 0 "" "")
6776 (match_operand 1 "" "")
6777 (match_operand 2 "" "")])]
6778 "NEEDS_UNTYPED_CALL"
6783 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
6785 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6787 rtx set = XVECEXP (operands[2], 0, i);
6788 emit_move_insn (SET_DEST (set), SET_SRC (set));
6791 /* The optimizer does not know that the call sets the function value
6792 registers we stored in the result block. We avoid problems by
6793 claiming that all hard registers are used and clobbered at this
6795 emit_insn (gen_blockage ());
6800 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6801 ;; all of memory. This blocks insns from being moved across this point.
6803 (define_insn "blockage"
6804 [(unspec_volatile [(const_int 0)] 0)]
6813 (define_insn "probe"
6818 operands[0] = gen_rtx (PLUS, SImode, stack_pointer_rtx,
6819 gen_rtx (CONST_INT, VOIDmode, NEED_PROBE));
6820 return \"tstl %a0\";
6823 ;; Used for frameless functions which save no regs and allocate no locals.
6824 (define_insn "return"
6829 if (current_function_pops_args == 0)
6831 operands[0] = gen_rtx (CONST_INT, VOIDmode, current_function_pops_args);
6835 (define_insn "indirect_jump"
6836 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
6840 ;; This should not be used unless the add/sub insns can't be.
6843 [(set (match_operand:SI 0 "general_operand" "=a")
6844 (match_operand:QI 1 "address_operand" "p"))]
6849 /* Recognize an insn that refers to a table of offsets. Such an insn will
6850 need to refer to a label on the insn. So output one. Use the
6851 label-number of the table of offsets to generate this label. This code,
6852 and similar code above, assumes that there will be at most one reference
6854 if (GET_CODE (operands[1]) == PLUS
6855 && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
6856 && GET_CODE (XEXP (operands[1], 0)) != PLUS)
6858 rtx labelref = XEXP (operands[1], 1);
6859 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
6861 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
6862 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6864 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
6865 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6866 #endif /* not SGS */
6867 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
6868 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
6869 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6870 #ifdef SGS_SWITCH_TABLES
6871 /* Set flag saying we need to define the symbol
6872 LD%n (with value L%n-LI%n) at the end of the switch table. */
6873 switch_table_difference_label_flag = 1;
6874 #endif /* SGS_SWITCH_TABLES */
6875 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
6877 #endif /* SGS_NO_LI */
6879 return \"lea %a1,%0\";
6882 ;; This is the first machine-dependent peephole optimization.
6883 ;; It is useful when a floating value is returned from a function call
6884 ;; and then is moved into an FP register.
6885 ;; But it is mainly intended to test the support for these optimizations.
6888 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
6889 (set (match_operand:DF 0 "register_operand" "=f")
6890 (match_operand:DF 1 "register_operand" "ad"))]
6891 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
6895 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
6896 output_asm_insn (\"move%.l %1,%@\", xoperands);
6897 output_asm_insn (\"move%.l %1,%-\", operands);
6898 return \"fmove%.d %+,%0\";
6902 ;; Optimize a stack-adjust followed by a push of an argument.
6903 ;; This is said to happen frequently with -msoft-float
6904 ;; when there are consecutive library calls.
6907 [(set (reg:SI 15) (plus:SI (reg:SI 15)
6908 (match_operand:SI 0 "const_int_operand" "n")))
6909 (set (match_operand:SF 1 "push_operand" "=m")
6910 (match_operand:SF 2 "general_operand" "rmfF"))]
6911 "INTVAL (operands[0]) >= 4
6912 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
6915 if (INTVAL (operands[0]) > 4)
6918 xoperands[0] = stack_pointer_rtx;
6919 xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4);
6921 if (INTVAL (xoperands[1]) <= 8)
6924 output_asm_insn (\"addq%.w %1,%0\", xoperands);
6926 output_asm_insn (\"addq%.l %1,%0\", xoperands);
6928 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
6930 xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
6931 INTVAL (xoperands[1]) - 8);
6932 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
6936 if (INTVAL (xoperands[1]) <= 0x7FFF)
6939 output_asm_insn (\"add%.w %1,%0\", xoperands);
6942 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
6944 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
6948 output_asm_insn (\"add%.l %1,%0\", xoperands);
6950 if (FP_REG_P (operands[2]))
6951 return \"fmove%.s %2,%@\";
6952 return \"move%.l %2,%@\";
6955 ;; Speed up stack adjust followed by a fullword fixedpoint push.
6958 [(set (reg:SI 15) (plus:SI (reg:SI 15)
6959 (match_operand:SI 0 "const_int_operand" "n")))
6960 (set (match_operand:SI 1 "push_operand" "=m")
6961 (match_operand:SI 2 "general_operand" "g"))]
6962 "INTVAL (operands[0]) >= 4
6963 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
6966 if (INTVAL (operands[0]) > 4)
6969 xoperands[0] = stack_pointer_rtx;
6970 xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4);
6972 if (INTVAL (xoperands[1]) <= 8)
6975 output_asm_insn (\"addq%.w %1,%0\", xoperands);
6977 output_asm_insn (\"addq%.l %1,%0\", xoperands);
6979 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
6981 xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
6982 INTVAL (xoperands[1]) - 8);
6983 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
6987 if (INTVAL (xoperands[1]) <= 0x7FFF)
6990 output_asm_insn (\"add%.w %1,%0\", xoperands);
6994 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
6996 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
7001 output_asm_insn (\"add%.l %1,%0\", xoperands);
7003 if (operands[2] == const0_rtx)
7004 return \"clr%.l %@\";
7005 return \"move%.l %2,%@\";
7008 ;; Speed up pushing a single byte but leaving four bytes of space.
7011 [(set (mem:QI (pre_dec:SI (reg:SI 15)))
7012 (match_operand:QI 1 "general_operand" "dami"))
7013 (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))]
7014 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
7019 if (GET_CODE (operands[1]) == REG)
7020 return \"move%.l %1,%-\";
7022 xoperands[1] = operands[1];
7024 = gen_rtx (MEM, QImode,
7025 gen_rtx (PLUS, VOIDmode, stack_pointer_rtx,
7026 gen_rtx (CONST_INT, VOIDmode, 3)));
7027 xoperands[3] = stack_pointer_rtx;
7029 output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
7031 output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands);
7036 [(set (match_operand:SI 0 "register_operand" "=d")
7038 (set (strict_low_part (subreg:HI (match_dup 0) 0))
7039 (match_operand:HI 1 "general_operand" "rmn"))]
7040 "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
7043 if (GET_CODE (operands[1]) == CONST_INT)
7045 if (operands[1] == const0_rtx
7046 && (DATA_REG_P (operands[0])
7047 || GET_CODE (operands[0]) == MEM)
7048 /* clr insns on 68000 read before writing.
7049 This isn't so on the 68010, but we have no TARGET_68010. */
7050 && ((TARGET_68020 || TARGET_5200)
7051 || !(GET_CODE (operands[0]) == MEM
7052 && MEM_VOLATILE_P (operands[0]))))
7053 return \"clr%.w %0\";
7055 return \"move%.w %1,%0\";
7063 ;; jCC label ; abnormal loop termination
7064 ;; dbra dN, loop ; normal loop termination
7072 ;; Which moves the jCC condition outside the inner loop for free.
7075 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7076 [(cc0) (const_int 0)])
7077 (label_ref (match_operand 2 "" ""))
7082 (ge (plus:HI (match_operand:HI 0 "register_operand" "+d")
7085 (label_ref (match_operand 1 "" ""))
7088 (plus:HI (match_dup 0)
7090 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7094 output_dbcc_and_branch (operands);
7099 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7100 [(cc0) (const_int 0)])
7101 (label_ref (match_operand 2 "" ""))
7106 (ge (plus:SI (match_operand:SI 0 "register_operand" "+d")
7109 (label_ref (match_operand 1 "" ""))
7112 (plus:SI (match_dup 0)
7114 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7118 output_dbcc_and_branch (operands);
7123 ;; FPA multiply and add.
7125 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7126 (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%x,dmF,y")
7127 (match_operand:DF 2 "general_operand" "xH,y,y"))
7128 (match_operand:DF 3 "general_operand" "xH,y,dmF")))]
7131 fpma%.d %1,%w2,%w3,%0
7132 fpma%.d %x1,%x2,%x3,%0
7133 fpma%.d %x1,%x2,%x3,%0")
7136 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7137 (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%x,ydmF,y")
7138 (match_operand:SF 2 "general_operand" "xH,y,ydmF"))
7139 (match_operand:SF 3 "general_operand" "xH,ydmF,ydmF")))]
7142 fpma%.s %1,%w2,%w3,%0
7144 fpma%.s %1,%2,%3,%0")
7146 ;; FPA Multiply and subtract
7148 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7149 (minus:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
7150 (mult:DF (match_operand:DF 2 "general_operand" "%xH,y,y")
7151 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
7154 fpms%.d %3,%w2,%w1,%0
7155 fpms%.d %x3,%2,%x1,%0
7156 fpms%.d %x3,%2,%x1,%0")
7159 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7160 (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
7161 (mult:SF (match_operand:SF 2 "general_operand" "%xH,rmF,y")
7162 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
7165 fpms%.s %3,%w2,%w1,%0
7167 fpms%.s %3,%2,%1,%0")
7170 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7171 (minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
7172 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7173 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7176 fpmr%.d %2,%w1,%w3,%0
7177 fpmr%.d %x2,%1,%x3,%0
7178 fpmr%.d %x2,%1,%x3,%0")
7181 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7182 (minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
7183 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7184 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7187 fpmr%.s %2,%w1,%w3,%0
7188 fpmr%.s %x2,%1,%x3,%0
7189 fpmr%.s %x2,%1,%x3,%0")
7191 ;; FPA Add and multiply
7193 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7194 (mult:DF (plus:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
7195 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7196 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7199 fpam%.d %2,%w1,%w3,%0
7200 fpam%.d %x2,%1,%x3,%0
7201 fpam%.d %x2,%1,%x3,%0")
7204 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7205 (mult:SF (plus:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
7206 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7207 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7210 fpam%.s %2,%w1,%w3,%0
7211 fpam%.s %x2,%1,%x3,%0
7212 fpam%.s %x2,%1,%x3,%0")
7214 ;;FPA Subtract and multiply
7216 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7217 (mult:DF (minus:DF (match_operand:DF 1 "general_operand" "xH,y,y")
7218 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7219 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7222 fpsm%.d %2,%w1,%w3,%0
7223 fpsm%.d %x2,%1,%x3,%0
7224 fpsm%.d %x2,%1,%x3,%0")
7227 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7228 (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
7229 (minus:DF (match_operand:DF 2 "general_operand" "xH,y,y")
7230 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
7233 fpsm%.d %3,%w2,%w1,%0
7234 fpsm%.d %x3,%2,%x1,%0
7235 fpsm%.d %x3,%2,%x1,%0")
7238 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7239 (mult:SF (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,y")
7240 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7241 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7244 fpsm%.s %2,%w1,%w3,%0
7245 fpsm%.s %x2,%1,%x3,%0
7246 fpsm%.s %x2,%1,%x3,%0")
7249 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7250 (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
7251 (minus:SF (match_operand:SF 2 "general_operand" "xH,rmF,y")
7252 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
7255 fpsm%.s %3,%w2,%w1,%0
7256 fpsm%.s %x3,%2,%x1,%0
7257 fpsm%.s %x3,%2,%x1,%0")
7259 (define_expand "tstxf"
7261 (match_operand:XF 0 "nonimmediate_operand" ""))]
7263 "m68k_last_compare_had_fp_operands = 1;")
7267 (match_operand:XF 0 "nonimmediate_operand" "fm"))]
7271 cc_status.flags = CC_IN_68881;
7272 return \"ftst%.x %0\";
7275 (define_expand "cmpxf"
7277 (compare (match_operand:XF 0 "nonimmediate_operand" "")
7278 (match_operand:XF 1 "nonimmediate_operand" "")))]
7280 "m68k_last_compare_had_fp_operands = 1;")
7284 (compare (match_operand:XF 0 "nonimmediate_operand" "f,m")
7285 (match_operand:XF 1 "nonimmediate_operand" "fm,f")))]
7289 cc_status.flags = CC_IN_68881;
7290 #ifdef SGS_CMP_ORDER
7291 if (REG_P (operands[0]))
7293 if (REG_P (operands[1]))
7294 return \"fcmp%.x %0,%1\";
7296 return \"fcmp%.x %0,%f1\";
7298 cc_status.flags |= CC_REVERSED;
7299 return \"fcmp%.x %1,%f0\";
7301 if (REG_P (operands[0]))
7303 if (REG_P (operands[1]))
7304 return \"fcmp%.x %1,%0\";
7306 return \"fcmp%.x %f1,%0\";
7308 cc_status.flags |= CC_REVERSED;
7309 return \"fcmp%.x %f0,%1\";
7313 (define_insn "extendsfxf2"
7314 [(set (match_operand:XF 0 "general_operand" "=fm,f")
7315 (float_extend:XF (match_operand:SF 1 "general_operand" "f,m")))]
7319 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7321 if (REGNO (operands[0]) == REGNO (operands[1]))
7323 /* Extending float to double in an fp-reg is a no-op.
7324 NOTICE_UPDATE_CC has already assumed that the
7325 cc will be set. So cancel what it did. */
7326 cc_status = cc_prev_status;
7329 return \"f%$move%.x %1,%0\";
7331 if (FP_REG_P (operands[0]))
7332 return \"f%$move%.s %f1,%0\";
7333 return \"fmove%.x %f1,%0\";
7337 (define_insn "extenddfxf2"
7338 [(set (match_operand:XF 0 "general_operand" "=fm,f")
7340 (match_operand:DF 1 "general_operand" "f,m")))]
7344 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7346 if (REGNO (operands[0]) == REGNO (operands[1]))
7348 /* Extending float to double in an fp-reg is a no-op.
7349 NOTICE_UPDATE_CC has already assumed that the
7350 cc will be set. So cancel what it did. */
7351 cc_status = cc_prev_status;
7354 return \"fmove%.x %1,%0\";
7356 if (FP_REG_P (operands[0]))
7357 return \"f%&move%.d %f1,%0\";
7358 return \"fmove%.x %f1,%0\";
7361 (define_insn "truncxfdf2"
7362 [(set (match_operand:DF 0 "general_operand" "=m,!r")
7364 (match_operand:XF 1 "general_operand" "f,f")))]
7368 if (REG_P (operands[0]))
7370 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
7371 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
7372 return \"move%.l %+,%0\";
7374 return \"fmove%.d %f1,%0\";
7377 (define_insn "truncxfsf2"
7378 [(set (match_operand:SF 0 "general_operand" "=dm")
7380 (match_operand:XF 1 "general_operand" "f")))]
7384 (define_insn "floatsixf2"
7385 [(set (match_operand:XF 0 "general_operand" "=f")
7386 (float:XF (match_operand:SI 1 "general_operand" "dmi")))]
7390 (define_insn "floathixf2"
7391 [(set (match_operand:XF 0 "general_operand" "=f")
7392 (float:XF (match_operand:HI 1 "general_operand" "dmn")))]
7396 (define_insn "floatqixf2"
7397 [(set (match_operand:XF 0 "general_operand" "=f")
7398 (float:XF (match_operand:QI 1 "general_operand" "dmn")))]
7402 (define_insn "ftruncxf2"
7403 [(set (match_operand:XF 0 "general_operand" "=f")
7404 (fix:XF (match_operand:XF 1 "general_operand" "fFm")))]
7408 if (FP_REG_P (operands[1]))
7409 return \"fintrz%.x %f1,%0\";
7410 return \"fintrz%.x %f1,%0\";
7413 (define_insn "fixxfqi2"
7414 [(set (match_operand:QI 0 "general_operand" "=dm")
7415 (fix:QI (match_operand:XF 1 "general_operand" "f")))]
7419 (define_insn "fixxfhi2"
7420 [(set (match_operand:HI 0 "general_operand" "=dm")
7421 (fix:HI (match_operand:XF 1 "general_operand" "f")))]
7425 (define_insn "fixxfsi2"
7426 [(set (match_operand:SI 0 "general_operand" "=dm")
7427 (fix:SI (match_operand:XF 1 "general_operand" "f")))]
7432 [(set (match_operand:XF 0 "general_operand" "=f")
7433 (plus:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7434 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7439 [(set (match_operand:XF 0 "general_operand" "=f")
7440 (plus:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7441 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7446 [(set (match_operand:XF 0 "general_operand" "=f")
7447 (plus:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7448 (match_operand:XF 1 "general_operand" "0")))]
7452 (define_insn "addxf3"
7453 [(set (match_operand:XF 0 "general_operand" "=f")
7454 (plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7455 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7459 if (REG_P (operands[2]))
7460 return \"fadd%.x %2,%0\";
7461 return \"fadd%.x %f2,%0\";
7465 [(set (match_operand:XF 0 "general_operand" "=f")
7466 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7467 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7472 [(set (match_operand:XF 0 "general_operand" "=f")
7473 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7474 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7479 [(set (match_operand:XF 0 "general_operand" "=f")
7480 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7481 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7485 (define_insn "subxf3"
7486 [(set (match_operand:XF 0 "general_operand" "=f")
7487 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7488 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7492 if (REG_P (operands[2]))
7493 return \"fsub%.x %2,%0\";
7494 return \"fsub%.x %f2,%0\";
7498 [(set (match_operand:XF 0 "general_operand" "=f")
7499 (mult:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7500 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7505 [(set (match_operand:XF 0 "general_operand" "=f")
7506 (mult:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7507 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7512 [(set (match_operand:XF 0 "general_operand" "=f")
7513 (mult:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7514 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7518 (define_insn "mulxf3"
7519 [(set (match_operand:XF 0 "general_operand" "=f")
7520 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7521 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7525 if (REG_P (operands[2]))
7526 return \"fmul%.x %2,%0\";
7527 return \"fmul%.x %f2,%0\";
7531 [(set (match_operand:XF 0 "general_operand" "=f")
7532 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7533 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7538 [(set (match_operand:XF 0 "general_operand" "=f")
7539 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7540 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7545 [(set (match_operand:XF 0 "general_operand" "=f")
7546 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7547 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7551 (define_insn "divxf3"
7552 [(set (match_operand:XF 0 "general_operand" "=f")
7553 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7554 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7558 if (REG_P (operands[2]))
7559 return \"fdiv%.x %2,%0\";
7560 return \"fdiv%.x %f2,%0\";
7563 (define_expand "negxf2"
7564 [(set (match_operand:XF 0 "general_operand" "")
7565 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7569 /* ??? There isn't an FPA define_insn so we could handle it here too.
7570 For now we don't (paranoia). */
7578 target = operand_subword (operands[0], 0, 1, XFmode);
7579 result = expand_binop (SImode, xor_optab,
7580 operand_subword_force (operands[1], 0, XFmode),
7581 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
7585 if (result != target)
7586 emit_move_insn (result, target);
7588 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7589 operand_subword_force (operands[1], 1, XFmode));
7590 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7591 operand_subword_force (operands[1], 2, XFmode));
7593 insns = get_insns ();
7596 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7601 (define_insn "negxf2_68881"
7602 [(set (match_operand:XF 0 "general_operand" "=f")
7603 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7607 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7608 return \"fneg%.x %1,%0\";
7609 return \"fneg%.x %f1,%0\";
7612 (define_expand "absxf2"
7613 [(set (match_operand:XF 0 "general_operand" "")
7614 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7618 /* ??? There isn't an FPA define_insn so we could handle it here too.
7619 For now we don't (paranoia). */
7627 target = operand_subword (operands[0], 0, 1, XFmode);
7628 result = expand_binop (SImode, and_optab,
7629 operand_subword_force (operands[1], 0, XFmode),
7630 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
7634 if (result != target)
7635 emit_move_insn (result, target);
7637 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7638 operand_subword_force (operands[1], 1, XFmode));
7639 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7640 operand_subword_force (operands[1], 2, XFmode));
7642 insns = get_insns ();
7645 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7650 (define_insn "absxf2_68881"
7651 [(set (match_operand:XF 0 "general_operand" "=f")
7652 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7656 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7657 return \"fabs%.x %1,%0\";
7658 return \"fabs%.x %f1,%0\";
7661 (define_insn "sqrtxf2"
7662 [(set (match_operand:XF 0 "general_operand" "=f")
7663 (sqrt:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7667 (define_insn "sinsf2"
7668 [(set (match_operand:SF 0 "general_operand" "=f")
7669 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 1))]
7670 "TARGET_68881 && flag_fast_math"
7673 if (FP_REG_P (operands[1]))
7674 return \"fsin%.x %1,%0\";
7676 return \"fsin%.s %1,%0\";
7679 (define_insn "sindf2"
7680 [(set (match_operand:DF 0 "general_operand" "=f")
7681 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 1))]
7682 "TARGET_68881 && flag_fast_math"
7685 if (FP_REG_P (operands[1]))
7686 return \"fsin%.x %1,%0\";
7688 return \"fsin%.d %1,%0\";
7691 (define_insn "sinxf2"
7692 [(set (match_operand:XF 0 "general_operand" "=f")
7693 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 1))]
7694 "TARGET_68881 && flag_fast_math"
7697 (define_insn "cossf2"
7698 [(set (match_operand:SF 0 "general_operand" "=f")
7699 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 2))]
7700 "TARGET_68881 && flag_fast_math"
7703 if (FP_REG_P (operands[1]))
7704 return \"fcos%.x %1,%0\";
7706 return \"fcos%.s %1,%0\";
7709 (define_insn "cosdf2"
7710 [(set (match_operand:DF 0 "general_operand" "=f")
7711 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 2))]
7712 "TARGET_68881 && flag_fast_math"
7715 if (FP_REG_P (operands[1]))
7716 return \"fcos%.x %1,%0\";
7718 return \"fcos%.d %1,%0\";
7721 (define_insn "cosxf2"
7722 [(set (match_operand:XF 0 "general_operand" "=f")
7723 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 2))]
7724 "TARGET_68881 && flag_fast_math"