1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 88, 93, 94, 95, 1996 Free Software Foundation, Inc.
4 ;; This file is part of GNU CC.
6 ;; GNU CC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GNU CC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GNU CC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
19 ;; Boston, MA 02111-1307, USA.
21 ;;- Information about MCF5200 port.
23 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
24 ;;- 68k ISA. Differences include reduced support for byte and word
25 ;;- operands and the removal of BCD, bitfield, rotate, and integer
26 ;;- divide instructions. The TARGET_5200 flag turns the use of the
27 ;;- removed opcodes and addressing modes off.
31 ;;- instruction definitions
33 ;;- @@The original PO technology requires these to be ordered by speed,
34 ;;- @@ so that assigner will pick the fastest.
36 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
38 ;;- When naming insn's (operand 0 of define_insn) be careful about using
39 ;;- names from other targets machine descriptions.
41 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
42 ;;- updates for most instructions.
44 ;;- Operand classes for the register allocator:
45 ;;- 'a' one of the address registers can be used.
46 ;;- 'd' one of the data registers can be used.
47 ;;- 'f' one of the m68881 registers can be used
48 ;;- 'r' either a data or an address register can be used.
49 ;;- 'x' if one of the Sun FPA registers
50 ;;- 'y' if one of the Low Sun FPA registers (fpa0-fpa15).
52 ;;- Immediate Floating point operator constraints
53 ;;- 'G' a floating point constant that is *NOT* one of the standard
54 ;; 68881 constant values (to force calling output_move_const_double
55 ;; to get it from rom if it is a 68881 constant).
56 ;;- 'H' one of the standard FPA constant values
58 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
61 ;;- Immediate integer operand constraints:
63 ;;- 'J' -32768 .. 32767
64 ;;- 'K' all integers EXCEPT -128 .. 127
66 ;;- 'M' all integers EXCEPT -256 .. 255
69 ;;- "%." size separator ("." or "") move%.l d0,d1
70 ;;- "%#" immediate separator ("#" or "") move%.l %#0,d0
71 ;;- "%-" push operand "sp@-" move%.l d0,%-
72 ;;- "%+" pop operand "sp@+" move%.l d0,%+
73 ;;- "%@" top of stack "sp@" move%.l d0,%@
74 ;;- "%!" fpcr register
75 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
76 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
79 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
80 ;; operand 1 is the argument for `sin'.
81 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
82 ;; operand 1 is the argument for `cos'.
84 ;;- Information about 68040 port.
86 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
87 ;;- be emulated in software by the OS. It is faster to avoid these
88 ;;- instructions and issue a library call rather than trapping into
89 ;;- the kernel. The affected instructions are fintrz and fscale. The
90 ;;- TARGET_68040 flag turns the use of the opcodes off.
92 ;;- The '040 also implements a set of new floating-point instructions
93 ;;- which specify the rounding precision in the opcode. This finally
94 ;;- permit the 68k series to be truly IEEE compliant, and solves all
95 ;;- issues of excess precision accumulating in the extended registers.
96 ;;- By default, GCC does not use these instructions, since such code will
97 ;;- not run on an '030. To use these instructions, use the -m68040-only
98 ;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY,
99 ;;- you can make these instructions the default.
101 ;;- These new instructions aren't directly in the md. They are brought
102 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
105 ;;- Information about 68060 port.
107 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
108 ;;- be emulated in software by the OS. It is faster to avoid these
109 ;;- instructions and issue a library call rather than trapping into
110 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
111 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
112 ;;- fscale. The TARGET_68060 flag turns the use of the opcodes off.
114 ;;- FPA port explanation:
116 ;;- Usage of the Sun FPA and the 68881 together
118 ;;- The current port of gcc to the sun fpa disallows use of the m68881
119 ;;- instructions completely if code is targeted for the fpa. This is
120 ;;- for the following reasons:
122 ;;- 1) Expressing the preference hierarchy (ie. use the fpa if you
123 ;;- can, the 68881 otherwise, and data registers only if you are
124 ;;- forced to it) is a bitch with the current constraint scheme,
125 ;;- especially since it would have to work for any combination of
128 ;;- 2) There are no instructions to move between the two types of
129 ;;- registers; the stack must be used as an intermediary.
131 ;;- It could indeed be done; I think the best way would be to have
132 ;;- separate patterns for TARGET_FPA (which implies a 68881),
133 ;;- TARGET_68881, and no floating point co-processor. Use
134 ;;- define_expands for all of the named instruction patterns, and
135 ;;- include code in the FPA instruction to deal with the 68881 with
136 ;;- preferences specifically set to favor the fpa. Some of this has
137 ;;- already been done:
139 ;;- 1) Separation of most of the patterns out into a TARGET_FPA
140 ;;- case and a TARGET_68881 case (the exceptions are the patterns
141 ;;- which would need one define_expand and three define_insn's under
142 ;;- it (with a lot of duplicate code between them) to replace the
143 ;;- current single define_insn. These are mov{[ds]f,[ds]i} and the
144 ;;- first two patterns in the md.
146 ;;- Some would still have to be done:
148 ;;- 1) Add code to the fpa patterns which correspond to 68881
149 ;;- patterns to deal with the 68881 case (including preferences!).
150 ;;- What you might actually do here is combine the fpa and 68881 code
151 ;;- back together into one pattern for those instructions where it's
152 ;;- absolutely necessary and save yourself some duplicate code. I'm
153 ;;- not completely sure as to whether you could get away with doing
154 ;;- this only for the mov* insns, or if you'd have to do it for all
156 ;;- 2) Add code to the mov{[ds]f,[ds]i} instructions to handle
157 ;;- moving between fpa regs and 68881 regs.
159 ;;- Since the fpa is more powerful than the 68881 and also has more
160 ;;- registers, and since I think the resultant md would be medium ugly
161 ;;- (lot's of duplicate code, ugly constraint strings), I elected not
162 ;;- to do this change.
164 ;;- Another reason why someone *might* want to do the change is to
165 ;;- control which register classes are accessed in a slightly cleaner
166 ;;- way than I have. See the blurb on CONDITIONAL_REGISTER_USAGE in
167 ;;- the internals manual.
169 ;;- Yet another reason why someone might want to do this change is to
170 ;;- allow use of some of the 68881 insns which have no equivalent on
171 ;;- the fpa. The sqrt instruction comes fairly quickly to mind.
173 ;;- If this is ever done, don't forget to change sun3.h so that
174 ;;- it *will* define __HAVE_68881__ when the FPA is in use.
176 ;;- Condition code hack
178 ;;- When a floating point compare is done in the fpa, the resulting
179 ;;- condition codes are left in the fpastatus register. The values in
180 ;;- this register must be moved into the 68000 cc register before any
181 ;;- jump is executed. Once this has been done, regular jump
182 ;;- instructions are fine (ie. floating point jumps are not necessary.
183 ;;- They are only done if the cc is in the 68881).
185 ;;- The instructions that move the fpastatus register to the 68000
186 ;;- register clobber a data register (the move cannot be done direct).
187 ;;- These instructions might be bundled either with the compare
188 ;;- instruction, or the branch instruction. If we were using both the
189 ;;- fpa and the 68881 together, we would wish to only mark the
190 ;;- register clobbered if we were doing the compare in the fpa, but I
191 ;;- think that that decision (whether to clobber the register or not)
192 ;;- must be done before register allocation (makes sense) and hence we
193 ;;- can't know if the floating point compare will be done in the fpa
194 ;;- or the fp. So whenever we are asked for code that uses the fpa,
195 ;;- we will mark a data register as clobbered. This is reasonable, as
196 ;;- almost all floating point compare operations done with fpa code
197 ;;- enabled will be done in the fpa. It's even more reasonable since
198 ;;- we decided to make the 68881 and the fpa mutually exclusive.
200 ;;- We place to code to move the fpastatus register inside of a
201 ;;- define_expand so that we can do it conditionally based on whether
202 ;;- we are targeting an fpa or not.
204 ;;- This still leaves us with the question of where we wish to put the
205 ;;- code to move the fpastatus reg. If we put it in the compare
206 ;;- instruction, we can restrict the clobbering of the register to
207 ;;- floating point compares, but we can't take advantage of floating
208 ;;- point subtracts & etc. that alter the fpastatus register. If we
209 ;;- put it in the branch instruction, all branches compiled with fpa
210 ;;- code enabled will clobber a data register, but we will be able to
211 ;;- take advantage of fpa subtracts. This balance favors putting the
212 ;;- code in with the compare instruction.
214 ;;- Note that if some enterprising hacker should decide to switch
215 ;;- this, he'll need to modify the code in NOTICE_UPDATE_CC.
217 ;;- Usage of the top 16 fpa registers
219 ;;- The only locations which we may transfer fpa registers 16-31 from
220 ;;- or to are the fpa registers 0-15. (68000 registers and memory
221 ;;- locations are impossible). This causes problems in gcc, which
222 ;;- assumes that mov?? instructions require no additional registers
223 ;;- (see section 11.7) and since floating point moves *must* be
224 ;;- supported into general registers (see section 12.3 under
225 ;;- HARD_REGNO_OK_FOR_MODE_P) from anywhere.
227 ;;- My solution was to reserve fpa0 for moves into or out of these top
228 ;;- 16 registers and to disparage the choice to reload into or out of
229 ;;- these registers as much as I could. That alternative is always
230 ;;- last in the list, so it will not be used unless all else fails. I
231 ;;- will note that according to my current information, sun's compiler
232 ;;- doesn't use these top 16 registers at all.
234 ;;- There is another possible way to do it. I *believe* that if you
235 ;;- make absolutely sure that the code will not be executed in the
236 ;;- reload pass, you can support the mov?? names with define_expands
237 ;;- which require new registers. This may be possible by the
238 ;;- appropriate juggling of constraints. I may come back to this later.
240 ;;- Usage of constant RAM
242 ;;- This has been handled correctly (I believe) but the way I've done
243 ;;- it could use a little explanation. The constant RAM can only be
244 ;;- accessed when the instruction is in "command register" mode.
245 ;;- "command register" mode means that no accessing of memory or the
246 ;;- 68000 registers is being done. This can be expressed easily in
247 ;;- constraints, so generally the mode of the instruction is
248 ;;- determined by a branch off of which_alternative. In outputting
249 ;;- instructions, a 'w' means to output an access to the constant ram
250 ;;- (if the arg is CONST_DOUBLE and is one of the available
251 ;;- constants), and 'x' means to output a register pair (if the arg is
252 ;;- a 68000 register) and a 'y' is the combination of the above two
253 ;;- processes. You use a 'y' in two operand DF instructions where you
254 ;;- *know* the other operand is an fpa register, you use an 'x' in DF
255 ;;- instructions where the arg might be a 68000 register and the
256 ;;- instruction is *not* in "command register" mode, and you use a 'w'
257 ;;- in two situations: 1) The instruction *is* in command register
258 ;;- mode (and hence won't be accessing 68000 registers), or 2) The
259 ;;- instruction is a two operand SF instruction where you know the
260 ;;- other operand is an fpa register.
262 ;;- Optimization issues
264 ;;- I actually think that I've included all of the fpa instructions
265 ;;- that should be included. Note that if someone is interested in
266 ;;- doing serious floating point work on the sun fpa, I would advise
267 ;;- the use of the "asm" instruction in gcc to allow you to use the
268 ;;- sin, cos, and exponential functions on the fpa board.
270 ;;- END FPA Explanation Section.
273 ;;- Some of these insn's are composites of several m68000 op codes.
274 ;;- The assembler (or final @@??) insures that the appropriate one is
278 [(set (match_operand:DF 0 "push_operand" "=m")
279 (match_operand:DF 1 "general_operand" "ro<>fyE"))]
283 if (FP_REG_P (operands[1]))
284 return \"fmove%.d %f1,%0\";
285 if (FPA_REG_P (operands[1]))
286 return \"fpmove%.d %1, %x0\";
287 return output_move_double (operands);
290 (define_insn "pushdi"
291 [(set (match_operand:DI 0 "push_operand" "=m")
292 (match_operand:DI 1 "general_operand" "ro<>Fyi"))]
296 return output_move_double (operands);
299 ;; We don't want to allow a constant operand for test insns because
300 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
301 ;; be folded while optimizing anyway.
305 (match_operand:DI 0 "nonimmediate_operand" "am,d"))
306 (clobber (match_scratch:SI 1 "=X,d"))
307 (clobber (match_scratch:DI 2 "=d,X"))]
311 if (which_alternative == 0)
315 xoperands[0] = operands[2];
316 xoperands[1] = operands[0];
317 output_move_double (xoperands);
318 cc_status.flags |= CC_REVERSED;
319 return \"neg%.l %R2\;negx%.l %2\";
321 if (find_reg_note (insn, REG_DEAD, operands[0]))
323 cc_status.flags |= CC_REVERSED;
324 return \"neg%.l %R0\;negx%.l %0\";
328 ** 'sub' clears %1, and also clears the X cc bit
329 ** 'tst' sets the Z cc bit according to the low part of the DImode operand
330 ** 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part
332 return \"sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0\";
337 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
342 /* ISI's assembler fails to handle tstl a0. */
343 if (! ADDRESS_REG_P (operands[0]))
345 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
347 return \"tst%.l %0\";
348 /* If you think that the 68020 does not support tstl a0,
349 reread page B-167 of the 68020 manual more carefully. */
350 /* On an address reg, cmpw may replace cmpl. */
352 return \"cmp%.w %0,%#0\";
354 return \"cmp%.w %#0,%0\";
358 ;; This can't use an address register, because comparisons
359 ;; with address registers as second operand always test the whole word.
362 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
368 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
372 (define_expand "tstsf"
374 (match_operand:SF 0 "general_operand" ""))]
375 "TARGET_68881 || TARGET_FPA"
380 emit_insn (gen_tstsf_fpa (operands[0]));
385 (define_insn "tstsf_fpa"
387 (match_operand:SF 0 "general_operand" "xmdF"))
388 (clobber (match_scratch:SI 1 "=d"))]
390 "fptst%.s %x0\;fpmove fpastatus,%1\;movw %1,cc")
394 (match_operand:SF 0 "general_operand" "fdm"))]
398 cc_status.flags = CC_IN_68881;
399 if (FP_REG_P (operands[0]))
400 return \"ftst%.x %0\";
401 return \"ftst%.s %0\";
404 (define_expand "tstdf"
406 (match_operand:DF 0 "general_operand" ""))]
407 "TARGET_68881 || TARGET_FPA"
412 emit_insn (gen_tstsf_fpa (operands[0]));
417 (define_insn "tstdf_fpa"
419 (match_operand:DF 0 "general_operand" "xrmF"))
420 (clobber (match_scratch:SI 1 "=d"))]
422 "fptst%.d %x0\;fpmove fpastatus,%1\;movw %1,cc")
426 (match_operand:DF 0 "general_operand" "fm"))]
430 cc_status.flags = CC_IN_68881;
431 if (FP_REG_P (operands[0]))
432 return \"ftst%.x %0\";
433 return \"ftst%.d %0\";
436 ;; compare instructions.
438 (define_expand "cmpdi"
441 (compare (match_operand:DI 0 "nonimmediate_operand" "")
442 (match_operand:DI 1 "general_operand" "")))
443 (clobber (match_dup 2))])]
445 "operands[2] = gen_reg_rtx (DImode);")
449 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
450 (match_operand:DI 2 "general_operand" "d,0")))
451 (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
455 if (rtx_equal_p (operands[0], operands[1]))
456 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
459 cc_status.flags |= CC_REVERSED;
460 return \"sub%.l %R1,%R0\;subx%.l %1,%0\";
464 ;; This is the second "hook" for PIC code (in addition to movsi). See
465 ;; comment of movsi for a description of PIC handling.
466 (define_expand "cmpsi"
468 (compare (match_operand:SI 0 "nonimmediate_operand" "")
469 (match_operand:SI 1 "general_operand" "")))]
473 if (flag_pic && symbolic_operand (operands[1], SImode))
475 /* The source is an address which requires PIC relocation.
476 Call legitimize_pic_address with the source, mode, and a relocation
477 register (a new pseudo, or the final destination if reload_in_progress
478 is set). Then fall through normally */
479 extern rtx legitimize_pic_address();
480 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
481 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
485 ;; A composite of the cmp, cmpa, & cmpi m68000 op codes.
488 (compare (match_operand:SI 0 "nonimmediate_operand" "rKs,mr,>")
489 (match_operand:SI 1 "general_operand" "mr,Ksr,>")))]
493 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
495 return \"cmpm%.l %0,%1\";
497 return \"cmpm%.l %1,%0\";
499 if (REG_P (operands[1])
500 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
501 { cc_status.flags |= CC_REVERSED;
503 return \"cmp%.l %d1,%d0\";
505 return \"cmp%.l %d0,%d1\";
509 return \"cmp%.l %d0,%d1\";
511 return \"cmp%.l %d1,%d0\";
517 (compare (match_operand:HI 0 "nonimmediate_operand" "rnm,d,n,m,>")
518 (match_operand:HI 1 "general_operand" "d,rnm,m,n,>")))]
522 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
524 return \"cmpm%.w %0,%1\";
526 return \"cmpm%.w %1,%0\";
528 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
529 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
530 { cc_status.flags |= CC_REVERSED;
532 return \"cmp%.w %d1,%d0\";
534 return \"cmp%.w %d0,%d1\";
538 return \"cmp%.w %d0,%d1\";
540 return \"cmp%.w %d1,%d0\";
546 (compare (match_operand:QI 0 "nonimmediate_operand" "dn,md,>")
547 (match_operand:QI 1 "general_operand" "dm,nd,>")))]
551 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
553 return \"cmpm%.b %0,%1\";
555 return \"cmpm%.b %1,%0\";
557 if (REG_P (operands[1])
558 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
559 { cc_status.flags |= CC_REVERSED;
561 return \"cmp%.b %d1,%d0\";
563 return \"cmp%.b %d0,%d1\";
567 return \"cmp%.b %d0,%d1\";
569 return \"cmp%.b %d1,%d0\";
573 (define_expand "cmpdf"
575 (compare (match_operand:DF 0 "general_operand" "")
576 (match_operand:DF 1 "general_operand" "")))]
577 "TARGET_68881 || TARGET_FPA"
582 emit_insn (gen_cmpdf_fpa (operands[0], operands[1]));
587 (define_insn "cmpdf_fpa"
589 (compare (match_operand:DF 0 "general_operand" "x,y")
590 (match_operand:DF 1 "general_operand" "xH,rmF")))
591 (clobber (match_scratch:SI 2 "=d,d"))]
593 "fpcmp%.d %y1,%0\;fpmove fpastatus,%2\;movw %2,cc")
597 (compare (match_operand:DF 0 "general_operand" "f,mG")
598 (match_operand:DF 1 "general_operand" "fmG,f")))]
602 cc_status.flags = CC_IN_68881;
604 if (REG_P (operands[0]))
606 if (REG_P (operands[1]))
607 return \"fcmp%.x %0,%1\";
609 return \"fcmp%.d %0,%f1\";
611 cc_status.flags |= CC_REVERSED;
612 return \"fcmp%.d %1,%f0\";
614 if (REG_P (operands[0]))
616 if (REG_P (operands[1]))
617 return \"fcmp%.x %1,%0\";
619 return \"fcmp%.d %f1,%0\";
621 cc_status.flags |= CC_REVERSED;
622 return \"fcmp%.d %f0,%1\";
626 (define_expand "cmpsf"
628 (compare (match_operand:SF 0 "general_operand" "")
629 (match_operand:SF 1 "general_operand" "")))]
630 "TARGET_68881 || TARGET_FPA"
635 emit_insn (gen_cmpsf_fpa (operands[0], operands[1]));
640 (define_insn "cmpsf_fpa"
642 (compare (match_operand:SF 0 "general_operand" "x,y")
643 (match_operand:SF 1 "general_operand" "xH,rmF")))
644 (clobber (match_scratch:SI 2 "=d,d"))]
646 "fpcmp%.s %w1,%x0\;fpmove fpastatus,%2\;movw %2,cc")
650 (compare (match_operand:SF 0 "general_operand" "f,mdG")
651 (match_operand:SF 1 "general_operand" "fmdG,f")))]
655 cc_status.flags = CC_IN_68881;
657 if (FP_REG_P (operands[0]))
659 if (FP_REG_P (operands[1]))
660 return \"fcmp%.x %0,%1\";
662 return \"fcmp%.s %0,%f1\";
664 cc_status.flags |= CC_REVERSED;
665 return \"fcmp%.s %1,%f0\";
667 if (FP_REG_P (operands[0]))
669 if (FP_REG_P (operands[1]))
670 return \"fcmp%.x %1,%0\";
672 return \"fcmp%.s %f1,%0\";
674 cc_status.flags |= CC_REVERSED;
675 return \"fcmp%.s %f0,%1\";
679 ;; Recognizers for btst instructions.
682 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
684 (minus:SI (const_int 7)
685 (match_operand:SI 1 "general_operand" "di"))))]
687 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
690 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
692 (minus:SI (const_int 31)
693 (match_operand:SI 1 "general_operand" "di"))))]
695 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
697 ;; The following two patterns are like the previous two
698 ;; except that they use the fact that bit-number operands
699 ;; are automatically masked to 3 or 5 bits.
702 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
704 (minus:SI (const_int 7)
706 (match_operand:SI 1 "register_operand" "d")
709 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
712 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
714 (minus:SI (const_int 31)
716 (match_operand:SI 1 "register_operand" "d")
719 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
721 ;; Nonoffsettable mem refs are ok in this one pattern
722 ;; since we don't try to adjust them.
724 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
726 (match_operand:SI 1 "const_int_operand" "n")))]
727 "(unsigned) INTVAL (operands[1]) < 8"
730 operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1]));
731 return output_btst (operands, operands[1], operands[0], insn, 7);
735 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
737 (match_operand:SI 1 "const_int_operand" "n")))]
741 if (GET_CODE (operands[0]) == MEM)
743 operands[0] = adj_offsettable_operand (operands[0],
744 INTVAL (operands[1]) / 8);
745 operands[1] = gen_rtx (CONST_INT, VOIDmode,
746 7 - INTVAL (operands[1]) % 8);
747 return output_btst (operands, operands[1], operands[0], insn, 7);
749 operands[1] = gen_rtx (CONST_INT, VOIDmode,
750 31 - INTVAL (operands[1]));
751 return output_btst (operands, operands[1], operands[0], insn, 31);
757 ;; A special case in which it is not desirable
758 ;; to reload the constant into a data register.
759 (define_insn "pushexthisi_const"
760 [(set (match_operand:SI 0 "push_operand" "=m")
761 (match_operand:SI 1 "const_int_operand" "J"))]
762 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
765 if (operands[1] == const0_rtx)
766 return \"clr%.l %0\";
771 ;(define_insn "swapsi"
772 ; [(set (match_operand:SI 0 "general_operand" "+r")
773 ; (match_operand:SI 1 "general_operand" "+r"))
774 ; (set (match_dup 1) (match_dup 0))]
778 ;; Special case of fullword move when source is zero.
779 ;; The reason this is special is to avoid loading a zero
780 ;; into a data reg with moveq in order to store it elsewhere.
782 (define_insn "movsi_const0"
783 [(set (match_operand:SI 0 "general_operand" "=g")
785 ;; clr insns on 68000 read before writing.
786 ;; This isn't so on the 68010, but we have no TARGET_68010.
787 "((TARGET_68020 || TARGET_5200)
788 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
791 if (ADDRESS_REG_P (operands[0]))
792 return \"sub%.l %0,%0\";
793 /* moveq is faster on the 68000. */
794 if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_5200))
795 #if defined(MOTOROLA) && !defined(CRDS)
796 return \"moveq%.l %#0,%0\";
798 return \"moveq %#0,%0\";
800 return \"clr%.l %0\";
803 ;; General case of fullword move.
805 ;; This is the main "hook" for PIC code. When generating
806 ;; PIC, movsi is responsible for determining when the source address
807 ;; needs PIC relocation and appropriately calling legitimize_pic_address
808 ;; to perform the actual relocation.
810 ;; In both the PIC and non-PIC cases the patterns generated will
811 ;; matched by the next define_insn.
812 (define_expand "movsi"
813 [(set (match_operand:SI 0 "general_operand" "")
814 (match_operand:SI 1 "general_operand" ""))]
818 if (flag_pic && symbolic_operand (operands[1], SImode))
820 /* The source is an address which requires PIC relocation.
821 Call legitimize_pic_address with the source, mode, and a relocation
822 register (a new pseudo, or the final destination if reload_in_progress
823 is set). Then fall through normally */
824 extern rtx legitimize_pic_address();
825 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
826 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
830 ;; General case of fullword move. The register constraints
831 ;; force integer constants in range for a moveq to be reloaded
832 ;; if they are headed for memory.
834 ;; Notes: make sure no alternative allows g vs g.
835 ;; We don't allow f-regs since fixed point cannot go in them.
836 ;; We do allow y and x regs since fixed point is allowed in them.
837 [(set (match_operand:SI 0 "general_operand" "=g,da,y,!*x*r*m")
838 (match_operand:SI 1 "general_operand" "daymKs,i,g,*x*r*m"))]
842 if (which_alternative == 3)
843 return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\";
844 if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0]))
845 return \"fpmove%.l %x1,%x0\";
846 if (GET_CODE (operands[1]) == CONST_INT)
847 return output_move_simode_const (operands);
848 else if ((GET_CODE (operands[1]) == SYMBOL_REF
849 || GET_CODE (operands[1]) == CONST)
850 && push_operand (operands[0], SImode))
852 else if ((GET_CODE (operands[1]) == SYMBOL_REF
853 || GET_CODE (operands[1]) == CONST)
854 && ADDRESS_REG_P (operands[0]))
855 return \"lea %a1,%0\";
856 return \"move%.l %1,%0\";
860 [(set (match_operand:HI 0 "general_operand" "=g")
861 (match_operand:HI 1 "general_operand" "g"))]
865 if (GET_CODE (operands[1]) == CONST_INT)
867 if (operands[1] == const0_rtx
868 && (DATA_REG_P (operands[0])
869 || GET_CODE (operands[0]) == MEM)
870 /* clr insns on 68000 read before writing.
871 This isn't so on the 68010, but we have no TARGET_68010. */
872 && ((TARGET_68020 || TARGET_5200)
873 || !(GET_CODE (operands[0]) == MEM
874 && MEM_VOLATILE_P (operands[0]))))
875 return \"clr%.w %0\";
876 else if (DATA_REG_P (operands[0])
877 && INTVAL (operands[1]) < 128
878 && INTVAL (operands[1]) >= -128)
880 #if defined(MOTOROLA) && !defined(CRDS)
881 return \"moveq%.l %1,%0\";
883 return \"moveq %1,%0\";
886 else if (INTVAL (operands[1]) < 0x8000
887 && INTVAL (operands[1]) >= -0x8000)
888 return \"move%.w %1,%0\";
890 else if (CONSTANT_P (operands[1]))
891 return \"move%.l %1,%0\";
893 /* Recognize the insn before a tablejump, one that refers
894 to a table of offsets. Such an insn will need to refer
895 to a label on the insn. So output one. Use the label-number
896 of the table of offsets to generate this label. This code,
897 and similar code below, assumes that there will be at most one
898 reference to each table. */
899 if (GET_CODE (operands[1]) == MEM
900 && GET_CODE (XEXP (operands[1], 0)) == PLUS
901 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF
902 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS)
904 rtx labelref = XEXP (XEXP (operands[1], 0), 1);
905 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
907 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
908 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
910 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
911 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
913 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
914 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
915 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
916 #ifdef SGS_SWITCH_TABLES
917 /* Set flag saying we need to define the symbol
918 LD%n (with value L%n-LI%n) at the end of the switch table. */
919 switch_table_difference_label_flag = 1;
920 #endif /* SGS_SWITCH_TABLES */
921 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
923 #endif /* SGS_NO_LI */
924 return \"move%.w %1,%0\";
927 (define_insn "movstricthi"
928 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
929 (match_operand:HI 1 "general_operand" "rmn"))]
933 if (GET_CODE (operands[1]) == CONST_INT)
935 if (operands[1] == const0_rtx
936 && (DATA_REG_P (operands[0])
937 || GET_CODE (operands[0]) == MEM)
938 /* clr insns on 68000 read before writing.
939 This isn't so on the 68010, but we have no TARGET_68010. */
940 && ((TARGET_68020 || TARGET_5200)
941 || !(GET_CODE (operands[0]) == MEM
942 && MEM_VOLATILE_P (operands[0]))))
943 return \"clr%.w %0\";
945 return \"move%.w %1,%0\";
949 [(set (match_operand:QI 0 "general_operand" "=d,*a,m")
950 (match_operand:QI 1 "general_operand" "dmi*a,di*a,dmi"))]
956 /* This is probably useless, since it loses for pushing a struct
957 of several bytes a byte at a time. */
958 if (GET_CODE (operands[0]) == MEM
959 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
960 && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx
961 && ! ADDRESS_REG_P (operands[1]))
963 xoperands[1] = operands[1];
965 = gen_rtx (MEM, QImode,
966 gen_rtx (PLUS, VOIDmode, stack_pointer_rtx, const1_rtx));
967 /* Just pushing a byte puts it in the high byte of the halfword. */
968 /* We must put it in the low-order, high-numbered byte. */
969 output_asm_insn (\"move%.b %1,%-\;move%.b %@,%2\", xoperands);
973 /* clr and st insns on 68000 read before writing.
974 This isn't so on the 68010, but we have no TARGET_68010. */
975 if (!ADDRESS_REG_P (operands[0])
977 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
979 if (operands[1] == const0_rtx)
980 return \"clr%.b %0\";
981 if (GET_CODE (operands[1]) == CONST_INT
982 && (INTVAL (operands[1]) & 255) == 255)
988 if (GET_CODE (operands[1]) == CONST_INT
989 && DATA_REG_P (operands[0])
990 && INTVAL (operands[1]) < 128
991 && INTVAL (operands[1]) >= -128)
993 #if defined(MOTOROLA) && !defined(CRDS)
994 return \"moveq%.l %1,%0\";
996 return \"moveq %1,%0\";
999 if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
1000 return \"move%.l %1,%0\";
1001 if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
1002 return \"move%.w %1,%0\";
1003 return \"move%.b %1,%0\";
1006 (define_insn "movstrictqi"
1007 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
1008 (match_operand:QI 1 "general_operand" "dmn"))]
1012 if (operands[1] == const0_rtx
1013 /* clr insns on 68000 read before writing.
1014 This isn't so on the 68010, but we have no TARGET_68010. */
1015 && ((TARGET_68020 || TARGET_5200)
1016 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1017 return \"clr%.b %0\";
1018 return \"move%.b %1,%0\";
1021 (define_insn "movsf"
1022 [(set (match_operand:SF 0 "general_operand" "=rmf,x,y,rm,!x,!rm")
1023 (match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))]
1024 ; [(set (match_operand:SF 0 "general_operand" "=rmf")
1025 ; (match_operand:SF 1 "general_operand" "rmfF"))]
1029 if (which_alternative >= 4)
1030 return \"fpmove%.s %1,fpa0\;fpmove%.s fpa0,%0\";
1031 if (FPA_REG_P (operands[0]))
1033 if (FPA_REG_P (operands[1]))
1034 return \"fpmove%.s %x1,%x0\";
1035 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1036 return output_move_const_single (operands);
1037 else if (FP_REG_P (operands[1]))
1038 return \"fmove%.s %1,sp@-\;fpmove%.d sp@+, %0\";
1039 return \"fpmove%.s %x1,%x0\";
1041 if (FPA_REG_P (operands[1]))
1043 if (FP_REG_P (operands[0]))
1044 return \"fpmove%.s %x1,sp@-\;fmove%.s sp@+,%0\";
1046 return \"fpmove%.s %x1,%x0\";
1048 if (FP_REG_P (operands[0]))
1050 if (FP_REG_P (operands[1]))
1051 return \"f%$move%.x %1,%0\";
1052 else if (ADDRESS_REG_P (operands[1]))
1053 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
1054 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1055 return output_move_const_single (operands);
1056 return \"f%$move%.s %f1,%0\";
1058 if (FP_REG_P (operands[1]))
1060 if (ADDRESS_REG_P (operands[0]))
1061 return \"fmove%.s %1,%-\;move%.l %+,%0\";
1062 return \"fmove%.s %f1,%0\";
1064 return \"move%.l %1,%0\";
1067 (define_insn "movdf"
1068 [(set (match_operand:DF 0 "general_operand" "=rm,rf,rf,&rof<>,y,rm,x,!x,!rm")
1069 (match_operand:DF 1 "general_operand" "rf,m,0,rofE<>,rmE,y,xH,rm,x"))]
1070 ; [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>")
1071 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
1075 if (which_alternative == 7)
1076 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1077 if (FPA_REG_P (operands[0]))
1079 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1080 return output_move_const_double (operands);
1081 if (FP_REG_P (operands[1]))
1082 return \"fmove%.d %1,sp@-\;fpmove%.d sp@+,%x0\";
1083 return \"fpmove%.d %x1,%x0\";
1085 else if (FPA_REG_P (operands[1]))
1087 if (FP_REG_P(operands[0]))
1088 return \"fpmove%.d %x1,sp@-\;fmoved sp@+,%0\";
1090 return \"fpmove%.d %x1,%x0\";
1092 if (FP_REG_P (operands[0]))
1094 if (FP_REG_P (operands[1]))
1095 return \"f%&move%.x %1,%0\";
1096 if (REG_P (operands[1]))
1099 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1100 output_asm_insn (\"move%.l %1,%-\", xoperands);
1101 output_asm_insn (\"move%.l %1,%-\", operands);
1102 return \"f%&move%.d %+,%0\";
1104 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1105 return output_move_const_double (operands);
1106 return \"f%&move%.d %f1,%0\";
1108 else if (FP_REG_P (operands[1]))
1110 if (REG_P (operands[0]))
1112 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1113 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1114 return \"move%.l %+,%0\";
1117 return \"fmove%.d %f1,%0\";
1119 return output_move_double (operands);
1123 (define_expand "movxf"
1124 [(set (match_operand:XF 0 "nonimmediate_operand" "")
1125 (match_operand:XF 1 "general_operand" ""))]
1129 if (CONSTANT_P (operands[1]))
1131 operands[1] = force_const_mem (XFmode, operands[1]);
1132 if (! memory_address_p (XFmode, XEXP (operands[1], 0))
1133 && ! reload_in_progress)
1134 operands[1] = change_address (operands[1], XFmode,
1135 XEXP (operands[1], 0));
1140 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f")
1141 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r"))]
1145 if (FP_REG_P (operands[0]))
1147 if (FP_REG_P (operands[1]))
1148 return \"fmove%.x %1,%0\";
1149 if (REG_P (operands[1]))
1152 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
1153 output_asm_insn (\"move%.l %1,%-\", xoperands);
1154 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1155 output_asm_insn (\"move%.l %1,%-\", xoperands);
1156 output_asm_insn (\"move%.l %1,%-\", operands);
1157 return \"fmove%.x %+,%0\";
1159 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1160 return \"fmove%.x %1,%0\";
1161 return \"fmove%.x %f1,%0\";
1163 if (REG_P (operands[0]))
1165 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1166 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1167 output_asm_insn (\"move%.l %+,%0\", operands);
1168 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1169 return \"move%.l %+,%0\";
1171 return \"fmove%.x %f1,%0\";
1176 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1177 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1181 if (FP_REG_P (operands[0]))
1183 if (FP_REG_P (operands[1]))
1184 return \"fmove%.x %1,%0\";
1185 if (REG_P (operands[1]))
1188 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
1189 output_asm_insn (\"move%.l %1,%-\", xoperands);
1190 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1191 output_asm_insn (\"move%.l %1,%-\", xoperands);
1192 output_asm_insn (\"move%.l %1,%-\", operands);
1193 return \"fmove%.x %+,%0\";
1195 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1196 return \"fmove%.x %1,%0\";
1197 return \"fmove%.x %f1,%0\";
1199 if (FP_REG_P (operands[1]))
1201 if (REG_P (operands[0]))
1203 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1204 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1205 output_asm_insn (\"move%.l %+,%0\", operands);
1206 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1207 return \"move%.l %+,%0\";
1210 return \"fmove%.x %f1,%0\";
1212 return output_move_double (operands);
1216 ;; movdi can apply to fp regs in some cases
1217 (define_insn "movdi"
1218 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1219 [(set (match_operand:DI 0 "general_operand" "=rm,r,&ro<>,y,rm,!*x,!rm")
1220 (match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))]
1221 ; [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm")
1222 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))]
1223 ; [(set (match_operand:DI 0 "general_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1224 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1228 if (which_alternative == 8)
1229 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1230 if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
1231 return \"fpmove%.d %x1,%x0\";
1232 if (FP_REG_P (operands[0]))
1234 if (FP_REG_P (operands[1]))
1235 return \"fmove%.x %1,%0\";
1236 if (REG_P (operands[1]))
1239 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1240 output_asm_insn (\"move%.l %1,%-\", xoperands);
1241 output_asm_insn (\"move%.l %1,%-\", operands);
1242 return \"fmove%.d %+,%0\";
1244 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1245 return output_move_const_double (operands);
1246 return \"fmove%.d %f1,%0\";
1248 else if (FP_REG_P (operands[1]))
1250 if (REG_P (operands[0]))
1252 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1253 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1254 return \"move%.l %+,%0\";
1257 return \"fmove%.d %f1,%0\";
1259 return output_move_double (operands);
1263 ;; Thus goes after the move instructions
1264 ;; because the move instructions are better (require no spilling)
1265 ;; when they can apply. It goes before the add/sub insns
1266 ;; so we will prefer it to them.
1268 (define_insn "pushasi"
1269 [(set (match_operand:SI 0 "push_operand" "=m")
1270 (match_operand:SI 1 "address_operand" "p"))]
1274 ;; truncation instructions
1275 (define_insn "truncsiqi2"
1276 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1278 (match_operand:SI 1 "general_operand" "doJ,i")))]
1282 if (GET_CODE (operands[0]) == REG)
1284 /* Must clear condition codes, since the move.l bases them on
1285 the entire 32 bits, not just the desired 8 bits. */
1287 return \"move%.l %1,%0\";
1289 if (GET_CODE (operands[1]) == MEM)
1290 operands[1] = adj_offsettable_operand (operands[1], 3);
1291 return \"move%.b %1,%0\";
1294 (define_insn "trunchiqi2"
1295 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1297 (match_operand:HI 1 "general_operand" "doJ,i")))]
1301 if (GET_CODE (operands[0]) == REG
1302 && (GET_CODE (operands[1]) == MEM
1303 || GET_CODE (operands[1]) == CONST_INT))
1305 /* Must clear condition codes, since the move.w bases them on
1306 the entire 16 bits, not just the desired 8 bits. */
1308 return \"move%.w %1,%0\";
1310 if (GET_CODE (operands[0]) == REG)
1312 /* Must clear condition codes, since the move.l bases them on
1313 the entire 32 bits, not just the desired 8 bits. */
1315 return \"move%.l %1,%0\";
1317 if (GET_CODE (operands[1]) == MEM)
1318 operands[1] = adj_offsettable_operand (operands[1], 1);
1319 return \"move%.b %1,%0\";
1322 (define_insn "truncsihi2"
1323 [(set (match_operand:HI 0 "general_operand" "=dm,d")
1325 (match_operand:SI 1 "general_operand" "roJ,i")))]
1329 if (GET_CODE (operands[0]) == REG)
1331 /* Must clear condition codes, since the move.l bases them on
1332 the entire 32 bits, not just the desired 8 bits. */
1334 return \"move%.l %1,%0\";
1336 if (GET_CODE (operands[1]) == MEM)
1337 operands[1] = adj_offsettable_operand (operands[1], 2);
1338 return \"move%.w %1,%0\";
1341 ;; zero extension instructions
1343 ;; this is the canonical form for (lshiftrt:DI x 32)
1344 (define_insn "zero_extendsidi2"
1345 [(set (match_operand:DI 0 "general_operand" "rm")
1346 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
1351 if (GET_CODE (operands[0]) == REG)
1352 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1353 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1354 return \"move%.l %1,%0\;clr%.l %0\";
1355 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1356 return \"clr%.l %0\;move%.l %1,%0\";
1358 operands[2] = adj_offsettable_operand (operands[0], 4);
1359 if (ADDRESS_REG_P (operands[0]))
1360 return \"move%.l %1,%2\;sub%.l %0,%0\";
1362 return \"move%.l %1,%2\;clr%.l %0\";
1365 (define_expand "zero_extendhisi2"
1366 [(set (match_operand:SI 0 "register_operand" "")
1368 (set (strict_low_part (match_dup 2))
1369 (match_operand:HI 1 "general_operand" ""))]
1373 operands[1] = make_safe_from (operands[1], operands[0]);
1374 if (GET_CODE (operands[0]) == SUBREG)
1375 operands[2] = gen_rtx (SUBREG, HImode, SUBREG_REG (operands[0]),
1376 SUBREG_WORD (operands[0]));
1378 operands[2] = gen_rtx (SUBREG, HImode, operands[0], 0);
1381 (define_expand "zero_extendqihi2"
1382 [(set (match_operand:HI 0 "register_operand" "")
1384 (set (strict_low_part (match_dup 2))
1385 (match_operand:QI 1 "general_operand" ""))]
1389 operands[1] = make_safe_from (operands[1], operands[0]);
1390 if (GET_CODE (operands[0]) == SUBREG)
1391 operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]),
1392 SUBREG_WORD (operands[0]));
1394 operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0);
1397 (define_expand "zero_extendqisi2"
1398 [(set (match_operand:SI 0 "register_operand" "")
1400 (set (strict_low_part (match_dup 2))
1401 (match_operand:QI 1 "general_operand" ""))]
1405 operands[1] = make_safe_from (operands[1], operands[0]);
1406 if (GET_CODE (operands[0]) == SUBREG)
1407 operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]),
1408 SUBREG_WORD (operands[0]));
1410 operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0);
1413 ;; Patterns to recognize zero-extend insns produced by the combiner.
1414 ;; We don't allow both operands in memory, because of aliasing problems.
1415 ;; Explicitly disallow two memory operands via the condition since reloading
1416 ;; of this case will result in worse code than the uncombined patterns.
1419 [(set (match_operand:SI 0 "general_operand" "=do<>,d<")
1420 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1421 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1424 if (DATA_REG_P (operands[0]))
1426 if (GET_CODE (operands[1]) == REG
1427 && REGNO (operands[0]) == REGNO (operands[1]))
1428 return \"and%.l %#0xFFFF,%0\";
1429 if (reg_mentioned_p (operands[0], operands[1]))
1430 return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\";
1431 return \"clr%.l %0\;move%.w %1,%0\";
1433 else if (GET_CODE (operands[0]) == MEM
1434 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1435 return \"move%.w %1,%0\;clr%.w %0\";
1436 else if (GET_CODE (operands[0]) == MEM
1437 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1438 return \"clr%.w %0\;move%.w %1,%0\";
1441 output_asm_insn (\"clr%.w %0\", operands);
1442 operands[0] = adj_offsettable_operand (operands[0], 2);
1443 return \"move%.w %1,%0\";
1448 [(set (match_operand:HI 0 "general_operand" "=do<>,d")
1449 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1450 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1453 if (DATA_REG_P (operands[0]))
1455 if (GET_CODE (operands[1]) == REG
1456 && REGNO (operands[0]) == REGNO (operands[1]))
1457 return \"and%.w %#0xFF,%0\";
1458 if (reg_mentioned_p (operands[0], operands[1]))
1459 return \"move%.b %1,%0\;and%.w %#0xFF,%0\";
1460 return \"clr%.w %0\;move%.b %1,%0\";
1462 else if (GET_CODE (operands[0]) == MEM
1463 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1465 if (REGNO (XEXP (XEXP (operands[0], 0), 0))
1466 == STACK_POINTER_REGNUM)
1468 output_asm_insn (\"clr%.w %-\", operands);
1469 operands[0] = gen_rtx (MEM, GET_MODE (operands[0]),
1470 plus_constant (stack_pointer_rtx, 1));
1471 return \"move%.b %1,%0\";
1474 return \"move%.b %1,%0\;clr%.b %0\";
1476 else if (GET_CODE (operands[0]) == MEM
1477 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1478 return \"clr%.b %0\;move%.b %1,%0\";
1481 output_asm_insn (\"clr%.b %0\", operands);
1482 operands[0] = adj_offsettable_operand (operands[0], 1);
1483 return \"move%.b %1,%0\";
1488 [(set (match_operand:SI 0 "general_operand" "=do<>,d")
1489 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1490 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1493 if (DATA_REG_P (operands[0]))
1495 if (GET_CODE (operands[1]) == REG
1496 && REGNO (operands[0]) == REGNO (operands[1]))
1497 return \"and%.l %#0xFF,%0\";
1498 if (reg_mentioned_p (operands[0], operands[1]))
1499 return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
1500 return \"clr%.l %0\;move%.b %1,%0\";
1502 else if (GET_CODE (operands[0]) == MEM
1503 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1505 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1508 return \"clr%.l -(%0)\;move%.b %1,3(%0)\";
1510 return \"clr%.l -(%0)\;move%.b %1,(3,%0)\";
1513 return \"clrl %0@-\;moveb %1,%0@(3)\";
1516 else if (GET_CODE (operands[0]) == MEM
1517 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1519 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1522 return \"clr%.l (%0)+\;move%.b %1,-1(%0)\";
1524 return \"clr%.l (%0)+\;move%.b %1,(-1,%0)\";
1527 return \"clrl %0@+\;moveb %1,%0@(-1)\";
1532 output_asm_insn (\"clr%.l %0\", operands);
1533 operands[0] = adj_offsettable_operand (operands[0], 3);
1534 return \"move%.b %1,%0\";
1538 ;; sign extension instructions
1540 (define_insn "extendqidi2"
1541 [(set (match_operand:DI 0 "general_operand" "=d")
1543 (match_operand:QI 1 "general_operand" "rm")))]
1548 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1549 if (TARGET_68020 || TARGET_5200)
1550 return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
1552 return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
1555 (define_insn "extendhidi2"
1556 [(set (match_operand:DI 0 "general_operand" "=d")
1558 (match_operand:HI 1 "general_operand" "rm")))]
1563 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1564 if (TARGET_68020 || TARGET_5200)
1565 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
1567 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
1570 (define_insn "extendsidi2"
1571 [(set (match_operand:DI 0 "general_operand" "=d")
1573 (match_operand:SI 1 "general_operand" "rm")))]
1578 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1579 if (TARGET_68020 || TARGET_5200)
1580 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
1582 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
1585 ;; Special case when one can avoid register clobbering, copy and test
1586 ;; Maybe there is a way to make that the general case, by forcing the
1587 ;; result of the SI tree to be in the lower register of the DI target
1589 (define_insn "extendplussidi"
1590 [(set (match_operand:DI 0 "register_operand" "=d")
1591 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1592 (match_operand:SI 2 "general_operand" "rmn"))))]
1597 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1598 if (GET_CODE (operands[1]) == CONST_INT
1599 && (unsigned) INTVAL (operands[1]) > 8)
1601 rtx tmp = operands[1];
1603 operands[1] = operands[2];
1606 if (GET_CODE (operands[1]) == REG
1607 && REGNO (operands[1]) == REGNO (operands[3]))
1608 output_asm_insn (\"add%.l %2,%3\", operands);
1610 output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands);
1611 if (TARGET_68020 || TARGET_5200)
1612 return \"smi %0\;extb%.l %0\";
1614 return \"smi %0\;ext%.w %0\;ext%.l %0\";
1617 (define_insn "extendhisi2"
1618 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1620 (match_operand:HI 1 "nonimmediate_operand" "0,rm")))]
1624 if (ADDRESS_REG_P (operands[0]))
1625 return \"move%.w %1,%0\";
1626 return \"ext%.l %0\";
1629 (define_insn "extendqihi2"
1630 [(set (match_operand:HI 0 "general_operand" "=d")
1631 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1635 (define_insn "extendqisi2"
1636 [(set (match_operand:SI 0 "general_operand" "=d")
1637 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1638 "TARGET_68020 || TARGET_5200"
1641 ;; Conversions between float and double.
1643 (define_expand "extendsfdf2"
1644 [(set (match_operand:DF 0 "general_operand" "")
1646 (match_operand:SF 1 "general_operand" "")))]
1647 "TARGET_68881 || TARGET_FPA"
1651 [(set (match_operand:DF 0 "general_operand" "=x,y")
1653 (match_operand:SF 1 "general_operand" "xH,rmF")))]
1658 [(set (match_operand:DF 0 "general_operand" "=*fdm,f")
1660 (match_operand:SF 1 "general_operand" "f,dmF")))]
1664 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1666 if (REGNO (operands[0]) == REGNO (operands[1]))
1668 /* Extending float to double in an fp-reg is a no-op.
1669 NOTICE_UPDATE_CC has already assumed that the
1670 cc will be set. So cancel what it did. */
1671 cc_status = cc_prev_status;
1674 return \"f%&move%.x %1,%0\";
1676 if (FP_REG_P (operands[0]))
1677 return \"f%&move%.s %f1,%0\";
1678 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1680 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1681 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1682 return \"move%.l %+,%0\";
1684 return \"fmove%.d %f1,%0\";
1687 ;; This cannot output into an f-reg because there is no way to be
1688 ;; sure of truncating in that case.
1689 ;; But on the Sun FPA, we can be sure.
1690 (define_expand "truncdfsf2"
1691 [(set (match_operand:SF 0 "general_operand" "")
1693 (match_operand:DF 1 "general_operand" "")))]
1694 "TARGET_68881 || TARGET_FPA"
1698 [(set (match_operand:SF 0 "general_operand" "=x,y")
1700 (match_operand:DF 1 "general_operand" "xH,rmF")))]
1704 ;; On the '040 we can truncate in a register accurately and easily.
1706 [(set (match_operand:SF 0 "general_operand" "=f")
1708 (match_operand:DF 1 "general_operand" "fmG")))]
1712 if (FP_REG_P (operands[1]))
1713 return \"f%$move%.x %1,%0\";
1714 return \"f%$move%.d %f1,%0\";
1718 [(set (match_operand:SF 0 "general_operand" "=dm")
1720 (match_operand:DF 1 "general_operand" "f")))]
1724 ;; Conversion between fixed point and floating point.
1725 ;; Note that among the fix-to-float insns
1726 ;; the ones that start with SImode come first.
1727 ;; That is so that an operand that is a CONST_INT
1728 ;; (and therefore lacks a specific machine mode).
1729 ;; will be recognized as SImode (which is always valid)
1730 ;; rather than as QImode or HImode.
1732 (define_expand "floatsisf2"
1733 [(set (match_operand:SF 0 "general_operand" "")
1734 (float:SF (match_operand:SI 1 "general_operand" "")))]
1735 "TARGET_68881 || TARGET_FPA"
1739 [(set (match_operand:SF 0 "general_operand" "=y,x")
1740 (float:SF (match_operand:SI 1 "general_operand" "rmi,x")))]
1745 [(set (match_operand:SF 0 "general_operand" "=f")
1746 (float:SF (match_operand:SI 1 "general_operand" "dmi")))]
1750 (define_expand "floatsidf2"
1751 [(set (match_operand:DF 0 "general_operand" "")
1752 (float:DF (match_operand:SI 1 "general_operand" "")))]
1753 "TARGET_68881 || TARGET_FPA"
1757 [(set (match_operand:DF 0 "general_operand" "=y,x")
1758 (float:DF (match_operand:SI 1 "general_operand" "rmi,x")))]
1763 [(set (match_operand:DF 0 "general_operand" "=f")
1764 (float:DF (match_operand:SI 1 "general_operand" "dmi")))]
1768 (define_insn "floathisf2"
1769 [(set (match_operand:SF 0 "general_operand" "=f")
1770 (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
1774 (define_insn "floathidf2"
1775 [(set (match_operand:DF 0 "general_operand" "=f")
1776 (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
1780 (define_insn "floatqisf2"
1781 [(set (match_operand:SF 0 "general_operand" "=f")
1782 (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
1786 (define_insn "floatqidf2"
1787 [(set (match_operand:DF 0 "general_operand" "=f")
1788 (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
1792 ;; New routines to convert floating-point values to integers
1793 ;; to be used on the '040. These should be faster than trapping
1794 ;; into the kernel to emulate fintrz. They should also be faster
1795 ;; than calling the subroutines fixsfsi or fixdfsi.
1797 (define_insn "fix_truncdfsi2"
1798 [(set (match_operand:SI 0 "general_operand" "=dm")
1799 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1800 (clobber (match_scratch:SI 2 "=d"))
1801 (clobber (match_scratch:SI 3 "=d"))]
1802 "TARGET_68881 && TARGET_68040"
1806 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\";
1809 (define_insn "fix_truncdfhi2"
1810 [(set (match_operand:HI 0 "general_operand" "=dm")
1811 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1812 (clobber (match_scratch:SI 2 "=d"))
1813 (clobber (match_scratch:SI 3 "=d"))]
1814 "TARGET_68881 && TARGET_68040"
1818 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\";
1821 (define_insn "fix_truncdfqi2"
1822 [(set (match_operand:QI 0 "general_operand" "=dm")
1823 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1824 (clobber (match_scratch:SI 2 "=d"))
1825 (clobber (match_scratch:SI 3 "=d"))]
1826 "TARGET_68881 && TARGET_68040"
1830 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\";
1833 ;; Convert a float to a float whose value is an integer.
1834 ;; This is the first stage of converting it to an integer type.
1836 (define_insn "ftruncdf2"
1837 [(set (match_operand:DF 0 "general_operand" "=f")
1838 (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
1839 "TARGET_68881 && !TARGET_68040"
1842 if (FP_REG_P (operands[1]))
1843 return \"fintrz%.x %f1,%0\";
1844 return \"fintrz%.d %f1,%0\";
1847 (define_insn "ftruncsf2"
1848 [(set (match_operand:SF 0 "general_operand" "=f")
1849 (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
1850 "TARGET_68881 && !TARGET_68040"
1853 if (FP_REG_P (operands[1]))
1854 return \"fintrz%.x %f1,%0\";
1855 return \"fintrz%.s %f1,%0\";
1858 ;; Convert a float whose value is an integer
1859 ;; to an actual integer. Second stage of converting float to integer type.
1860 (define_insn "fixsfqi2"
1861 [(set (match_operand:QI 0 "general_operand" "=dm")
1862 (fix:QI (match_operand:SF 1 "general_operand" "f")))]
1866 (define_insn "fixsfhi2"
1867 [(set (match_operand:HI 0 "general_operand" "=dm")
1868 (fix:HI (match_operand:SF 1 "general_operand" "f")))]
1872 (define_insn "fixsfsi2"
1873 [(set (match_operand:SI 0 "general_operand" "=dm")
1874 (fix:SI (match_operand:SF 1 "general_operand" "f")))]
1878 (define_insn "fixdfqi2"
1879 [(set (match_operand:QI 0 "general_operand" "=dm")
1880 (fix:QI (match_operand:DF 1 "general_operand" "f")))]
1884 (define_insn "fixdfhi2"
1885 [(set (match_operand:HI 0 "general_operand" "=dm")
1886 (fix:HI (match_operand:DF 1 "general_operand" "f")))]
1890 (define_insn "fixdfsi2"
1891 [(set (match_operand:SI 0 "general_operand" "=dm")
1892 (fix:SI (match_operand:DF 1 "general_operand" "f")))]
1896 ;; Convert a float to an integer.
1897 ;; On the Sun FPA, this is done in one step.
1900 [(set (match_operand:SI 0 "general_operand" "=x,y")
1901 (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "xH,rmF"))))]
1906 [(set (match_operand:SI 0 "general_operand" "=x,y")
1907 (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "xH,rmF"))))]
1913 (define_insn "adddi_lshrdi_63"
1914 [(set (match_operand:DI 0 "general_operand" "=d")
1915 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
1918 (clobber (match_scratch:SI 2 "=d"))]
1922 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1923 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
1925 \"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0\";
1926 if (GET_CODE (operands[1]) == REG)
1927 operands[4] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1928 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
1929 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1930 operands[4] = operands[1];
1932 operands[4] = adj_offsettable_operand (operands[1], 4);
1933 if (GET_CODE (operands[1]) == MEM
1934 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1935 output_asm_insn (\"move%.l %4,%3\", operands);
1936 output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
1937 if (TARGET_68020 || TARGET_5200)
1938 output_asm_insn (\"extb%.l %2\", operands);
1940 output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
1941 if (GET_CODE (operands[1]) != MEM
1942 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
1943 output_asm_insn (\"move%.l %4,%3\", operands);
1944 return \"sub%.l %2,%3\;subx%.l %2,%0\";
1947 (define_insn "adddi_sexthishl32"
1948 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
1949 (plus:DI (ashift:DI (sign_extend:DI
1950 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
1952 (match_operand:DI 2 "general_operand" "0,0,0,0")))
1953 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
1958 if (ADDRESS_REG_P (operands[0]))
1959 return \"add%.w %1,%0\";
1960 else if (ADDRESS_REG_P (operands[3]))
1961 return \"move%.w %1,%3\;add%.l %3,%0\";
1963 return \"move%.w %1,%3\;ext%.l %3\;add%.l %3,%0\";
1966 (define_insn "adddi_dilshr32"
1967 [(set (match_operand:DI 0 "general_operand" "=do")
1968 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
1969 ;; (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
1970 ;; (const_int 32))))]
1971 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
1973 (match_operand:DI 2 "general_operand" "0")))]
1978 if (GET_CODE (operands[0]) == REG)
1979 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1981 operands[2] = adj_offsettable_operand (operands[0], 4);
1982 return \"add%.l %1,%2\;negx%.l %0\;neg%.l %0\";
1985 (define_insn "adddi_dishl32"
1986 [(set (match_operand:DI 0 "general_operand" "=ro")
1987 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
1988 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
1989 ;; (const_int 32))))]
1990 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro")
1992 (match_operand:DI 2 "general_operand" "0")))]
1997 if (GET_CODE (operands[1]) == REG)
1998 operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2000 operands[1] = adj_offsettable_operand (operands[1], 4);
2001 return \"add%.l %1,%0\";
2004 (define_insn "adddi3"
2005 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2006 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0,0")
2007 (match_operand:DI 2 "general_operand" "<,d,o>,d,a")))
2008 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2012 if (DATA_REG_P (operands[0]))
2014 if (DATA_REG_P (operands[2]))
2015 return \"add%.l %R2,%R0\;addx%.l %2,%0\";
2016 else if (GET_CODE (operands[2]) == MEM
2017 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2019 return \"move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0\";
2023 /* TODO : this should work also for CONST operands[2] */
2024 if (GET_CODE (operands[2]) == REG)
2025 operands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
2027 operands[1] = adj_offsettable_operand (operands[2], 4);
2028 return \"move%.l %2,%3\;add%.l %1,%R0\;addx%.l %3,%0\";
2031 else if (GET_CODE (operands[0]) == MEM)
2033 if (GET_CODE (operands[2]) == MEM
2034 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2035 return \"add%.l %2,%0\;addx%.l %2,%0\";
2037 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2039 operands[1] = gen_rtx (MEM, SImode,
2040 gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
2041 gen_rtx (CONST_INT, VOIDmode, -8)));
2042 return \"move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1\";
2044 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2046 operands[1] = XEXP(operands[0], 0);
2047 return \"add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
2051 operands[1] = adj_offsettable_operand (operands[0], 4);
2052 return \"add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
2057 (define_insn "addsi_lshrsi_31"
2058 [(set (match_operand:SI 0 "general_operand" "=dm")
2059 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
2065 operands[2] = operands[0];
2066 operands[3] = gen_label_rtx();
2067 if (GET_CODE (operands[0]) == MEM)
2069 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2070 operands[0] = gen_rtx (MEM, SImode, XEXP (XEXP (operands[0], 0), 0));
2071 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2072 operands[2] = gen_rtx (MEM, SImode, XEXP (XEXP (operands[0], 0), 0));
2074 output_asm_insn (\"move%.l %1,%0\", operands);
2076 output_asm_insn (\"jbpl %l3\", operands);
2078 output_asm_insn (\"jpl %l3\", operands);
2081 output_asm_insn (\"addq%.l %#1,%2\", operands);
2083 output_asm_insn (\"add%.l %#1,%2\", operands);
2085 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
2086 CODE_LABEL_NUMBER (operands[3]));
2090 ;; Note that the middle two alternatives are near-duplicates
2091 ;; in order to handle insns generated by reload.
2092 ;; This is needed since they are not themselves reloaded,
2093 ;; so commutativity won't apply to them.
2094 (define_insn "addsi3"
2095 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
2096 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2097 (match_operand:SI 2 "general_operand" "dIKLs,rJK,a,mrIKLs")))]
2101 if (! operands_match_p (operands[0], operands[1]))
2103 if (!ADDRESS_REG_P (operands[1]))
2105 rtx tmp = operands[1];
2107 operands[1] = operands[2];
2111 /* These insns can result from reloads to access
2112 stack slots over 64k from the frame pointer. */
2113 if (GET_CODE (operands[2]) == CONST_INT
2114 && INTVAL (operands[2]) + 0x8000 >= (unsigned) 0x10000)
2115 return \"move%.l %2,%0\;add%.l %1,%0\";
2117 if (GET_CODE (operands[2]) == REG)
2118 return \"lea 0(%1,%2.l),%0\";
2120 return \"lea %c2(%1),%0\";
2123 if (GET_CODE (operands[2]) == REG)
2124 return \"lea (%1,%2.l),%0\";
2126 return \"lea (%c2,%1),%0\";
2127 #else /* not MOTOROLA (MIT syntax) */
2128 if (GET_CODE (operands[2]) == REG)
2129 return \"lea %1@(0,%2:l),%0\";
2131 return \"lea %1@(%c2),%0\";
2132 #endif /* not MOTOROLA */
2133 #endif /* not SGS */
2135 if (GET_CODE (operands[2]) == CONST_INT)
2138 if (INTVAL (operands[2]) > 0
2139 && INTVAL (operands[2]) <= 8)
2140 return (ADDRESS_REG_P (operands[0]) && !TARGET_5200
2142 : \"addq%.l %2,%0\");
2143 if (INTVAL (operands[2]) < 0
2144 && INTVAL (operands[2]) >= -8)
2146 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2147 - INTVAL (operands[2]));
2148 return (ADDRESS_REG_P (operands[0]) && !TARGET_5200
2150 : \"subq%.l %2,%0\");
2152 /* On the 68020 it is faster to use two addqw instructions to
2153 add a small integer (8 < N <= 16) to an address register.
2154 Likewise for subqw. */
2155 if (TARGET_68020 && !TARGET_68040 && !TARGET_68060
2156 && ADDRESS_REG_P (operands[0]))
2158 if (INTVAL (operands[2]) > 8
2159 && INTVAL (operands[2]) <= 16)
2161 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2162 INTVAL (operands[2]) - 8);
2163 return \"addq%.w %#8,%0\;addq%.w %2,%0\";
2165 if (INTVAL (operands[2]) < -8
2166 && INTVAL (operands[2]) >= -16)
2168 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2169 - INTVAL (operands[2]) - 8);
2170 return \"subq%.w %#8,%0\;subq%.w %2,%0\";
2174 if (ADDRESS_REG_P (operands[0])
2175 && INTVAL (operands[2]) >= -0x8000
2176 && INTVAL (operands[2]) < 0x8000)
2179 return \"add%.w %2,%0\";
2182 return \"lea (%c2,%0),%0\";
2184 return \"lea %0@(%c2),%0\";
2188 return \"add%.l %2,%0\";
2192 [(set (match_operand:SI 0 "general_operand" "=a")
2193 (plus:SI (match_operand:SI 1 "general_operand" "0")
2195 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2199 (define_insn "addhi3"
2200 [(set (match_operand:HI 0 "general_operand" "=m,r")
2201 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2202 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2207 if (GET_CODE (operands[2]) == CONST_INT)
2209 /* If the constant would be a negative number when interpreted as
2210 HImode, make it negative. This is usually, but not always, done
2211 elsewhere in the compiler. First check for constants out of range,
2212 which could confuse us. */
2214 if (INTVAL (operands[2]) >= 32768)
2215 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2216 INTVAL (operands[2]) - 65536);
2218 if (INTVAL (operands[2]) > 0
2219 && INTVAL (operands[2]) <= 8)
2220 return \"addq%.w %2,%0\";
2221 if (INTVAL (operands[2]) < 0
2222 && INTVAL (operands[2]) >= -8)
2224 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2225 - INTVAL (operands[2]));
2226 return \"subq%.w %2,%0\";
2228 /* On the 68020 it is faster to use two addqw instructions to
2229 add a small integer (8 < N <= 16) to an address register.
2230 Likewise for subqw. */
2231 if (TARGET_68020 && !TARGET_68040 && !TARGET_68060
2232 && ADDRESS_REG_P (operands[0]))
2234 if (INTVAL (operands[2]) > 8
2235 && INTVAL (operands[2]) <= 16)
2237 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2238 INTVAL (operands[2]) - 8);
2239 return \"addq%.w %#8,%0\;addq%.w %2,%0\";
2241 if (INTVAL (operands[2]) < -8
2242 && INTVAL (operands[2]) >= -16)
2244 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2245 - INTVAL (operands[2]) - 8);
2246 return \"subq%.w %#8,%0\;subq%.w %2,%0\";
2251 return \"add%.w %2,%0\";
2254 ;; These insns must use MATCH_DUP instead of the more expected
2255 ;; use of a matching constraint because the "output" here is also
2256 ;; an input, so you can't use the matching constraint. That also means
2257 ;; that you can't use the "%", so you need patterns with the matched
2258 ;; operand in both positions.
2261 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2262 (plus:HI (match_dup 0)
2263 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2268 if (GET_CODE (operands[1]) == CONST_INT)
2270 /* If the constant would be a negative number when interpreted as
2271 HImode, make it negative. This is usually, but not always, done
2272 elsewhere in the compiler. First check for constants out of range,
2273 which could confuse us. */
2275 if (INTVAL (operands[1]) >= 32768)
2276 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2277 INTVAL (operands[1]) - 65536);
2279 if (INTVAL (operands[1]) > 0
2280 && INTVAL (operands[1]) <= 8)
2281 return \"addq%.w %1,%0\";
2282 if (INTVAL (operands[1]) < 0
2283 && INTVAL (operands[1]) >= -8)
2285 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2286 - INTVAL (operands[1]));
2287 return \"subq%.w %1,%0\";
2289 /* On the 68020 it is faster to use two addqw instructions to
2290 add a small integer (8 < N <= 16) to an address register.
2291 Likewise for subqw. */
2292 if (TARGET_68020 && !TARGET_68040 && !TARGET_68060
2293 && ADDRESS_REG_P (operands[0]))
2295 if (INTVAL (operands[1]) > 8
2296 && INTVAL (operands[1]) <= 16)
2298 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2299 INTVAL (operands[1]) - 8);
2300 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2302 if (INTVAL (operands[1]) < -8
2303 && INTVAL (operands[1]) >= -16)
2305 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2306 - INTVAL (operands[1]) - 8);
2307 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2312 return \"add%.w %1,%0\";
2316 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2317 (plus:HI (match_operand:HI 1 "general_operand" "dn,rmn")
2323 if (GET_CODE (operands[1]) == CONST_INT)
2325 /* If the constant would be a negative number when interpreted as
2326 HImode, make it negative. This is usually, but not always, done
2327 elsewhere in the compiler. First check for constants out of range,
2328 which could confuse us. */
2330 if (INTVAL (operands[1]) >= 32768)
2331 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2332 INTVAL (operands[1]) - 65536);
2334 if (INTVAL (operands[1]) > 0
2335 && INTVAL (operands[1]) <= 8)
2336 return \"addq%.w %1,%0\";
2337 if (INTVAL (operands[1]) < 0
2338 && INTVAL (operands[1]) >= -8)
2340 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2341 - INTVAL (operands[1]));
2342 return \"subq%.w %1,%0\";
2344 /* On the 68020 it is faster to use two addqw instructions to
2345 add a small integer (8 < N <= 16) to an address register.
2346 Likewise for subqw. */
2347 if (TARGET_68020 && !TARGET_68040 && !TARGET_68060
2348 && ADDRESS_REG_P (operands[0]))
2350 if (INTVAL (operands[1]) > 8
2351 && INTVAL (operands[1]) <= 16)
2353 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2354 INTVAL (operands[1]) - 8);
2355 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2357 if (INTVAL (operands[1]) < -8
2358 && INTVAL (operands[1]) >= -16)
2360 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2361 - INTVAL (operands[1]) - 8);
2362 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2367 return \"add%.w %1,%0\";
2370 (define_insn "addqi3"
2371 [(set (match_operand:QI 0 "general_operand" "=m,d")
2372 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2373 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2378 if (GET_CODE (operands[2]) == CONST_INT)
2380 if (INTVAL (operands[2]) >= 128)
2381 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2382 INTVAL (operands[2]) - 256);
2384 if (INTVAL (operands[2]) > 0
2385 && INTVAL (operands[2]) <= 8)
2386 return \"addq%.b %2,%0\";
2387 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2389 operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2]));
2390 return \"subq%.b %2,%0\";
2394 return \"add%.b %2,%0\";
2398 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2399 (plus:QI (match_dup 0)
2400 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2405 if (GET_CODE (operands[1]) == CONST_INT)
2407 if (INTVAL (operands[1]) >= 128)
2408 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2409 INTVAL (operands[1]) - 256);
2411 if (INTVAL (operands[1]) > 0
2412 && INTVAL (operands[1]) <= 8)
2413 return \"addq%.b %1,%0\";
2414 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2416 operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]));
2417 return \"subq%.b %1,%0\";
2421 return \"add%.b %1,%0\";
2425 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2426 (plus:QI (match_operand:QI 1 "general_operand" "dn,dmn")
2432 if (GET_CODE (operands[1]) == CONST_INT)
2434 if (INTVAL (operands[1]) >= 128)
2435 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2436 INTVAL (operands[1]) - 256);
2438 if (INTVAL (operands[1]) > 0
2439 && INTVAL (operands[1]) <= 8)
2440 return \"addq%.b %1,%0\";
2441 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2443 operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]));
2444 return \"subq%.b %1,%0\";
2448 return \"add%.b %1,%0\";
2451 (define_expand "adddf3"
2452 [(set (match_operand:DF 0 "general_operand" "")
2453 (plus:DF (match_operand:DF 1 "general_operand" "")
2454 (match_operand:DF 2 "general_operand" "")))]
2455 "TARGET_68881 || TARGET_FPA"
2459 [(set (match_operand:DF 0 "general_operand" "=x,y")
2460 (plus:DF (match_operand:DF 1 "general_operand" "%xH,y")
2461 (match_operand:DF 2 "general_operand" "xH,dmF")))]
2465 if (rtx_equal_p (operands[0], operands[1]))
2466 return \"fpadd%.d %y2,%0\";
2467 if (rtx_equal_p (operands[0], operands[2]))
2468 return \"fpadd%.d %y1,%0\";
2469 if (which_alternative == 0)
2470 return \"fpadd3%.d %w2,%w1,%0\";
2471 return \"fpadd3%.d %x2,%x1,%0\";
2475 [(set (match_operand:DF 0 "general_operand" "=f")
2476 (plus:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2477 (match_operand:DF 1 "general_operand" "0")))]
2482 [(set (match_operand:DF 0 "general_operand" "=f")
2483 (plus:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2484 (match_operand:DF 1 "general_operand" "0")))]
2489 [(set (match_operand:DF 0 "general_operand" "=f")
2490 (plus:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2491 (match_operand:DF 1 "general_operand" "0")))]
2496 [(set (match_operand:DF 0 "general_operand" "=f")
2497 (plus:DF (match_operand:DF 1 "general_operand" "%0")
2498 (match_operand:DF 2 "general_operand" "fmG")))]
2502 if (REG_P (operands[2]))
2503 return \"f%&add%.x %2,%0\";
2504 return \"f%&add%.d %f2,%0\";
2507 (define_expand "addsf3"
2508 [(set (match_operand:SF 0 "general_operand" "")
2509 (plus:SF (match_operand:SF 1 "general_operand" "")
2510 (match_operand:SF 2 "general_operand" "")))]
2511 "TARGET_68881 || TARGET_FPA"
2515 [(set (match_operand:SF 0 "general_operand" "=x,y")
2516 (plus:SF (match_operand:SF 1 "general_operand" "%xH,y")
2517 (match_operand:SF 2 "general_operand" "xH,rmF")))]
2521 if (rtx_equal_p (operands[0], operands[1]))
2522 return \"fpadd%.s %w2,%0\";
2523 if (rtx_equal_p (operands[0], operands[2]))
2524 return \"fpadd%.s %w1,%0\";
2525 if (which_alternative == 0)
2526 return \"fpadd3%.s %w2,%w1,%0\";
2527 return \"fpadd3%.s %2,%1,%0\";
2531 [(set (match_operand:SF 0 "general_operand" "=f")
2532 (plus:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2533 (match_operand:SF 1 "general_operand" "0")))]
2538 [(set (match_operand:SF 0 "general_operand" "=f")
2539 (plus:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
2540 (match_operand:SF 1 "general_operand" "0")))]
2545 [(set (match_operand:SF 0 "general_operand" "=f")
2546 (plus:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
2547 (match_operand:SF 1 "general_operand" "0")))]
2552 [(set (match_operand:SF 0 "general_operand" "=f")
2553 (plus:SF (match_operand:SF 1 "general_operand" "%0")
2554 (match_operand:SF 2 "general_operand" "fdmF")))]
2558 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2559 return \"f%$add%.x %2,%0\";
2560 return \"f%$add%.s %f2,%0\";
2563 ;; subtract instructions
2565 (define_insn "subdi_sexthishl32"
2566 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2567 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2568 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2570 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2575 if (ADDRESS_REG_P (operands[0]))
2576 return \"sub%.w %2,%0\";
2577 else if (ADDRESS_REG_P (operands[3]))
2578 return \"move%.w %2,%3\;sub%.l %3,%0\";
2580 return \"move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0\";
2583 (define_insn "subdi_dishl32"
2584 [(set (match_operand:DI 0 "general_operand" "+ro")
2585 (minus:DI (match_dup 0)
2586 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2592 if (GET_CODE (operands[1]) == REG)
2593 operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2595 operands[1] = adj_offsettable_operand (operands[1], 4);
2596 return \"sub%.l %1,%0\";
2599 (define_insn "subdi3"
2600 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2601 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0,0")
2602 (match_operand:DI 2 "general_operand" "<,d,o>,d,a")))
2603 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2607 if (DATA_REG_P (operands[0]))
2609 if (DATA_REG_P (operands[2]))
2610 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
2611 else if (GET_CODE (operands[2]) == MEM
2612 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2614 return \"move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0\";
2618 /* TODO : this should work also for CONST operands[2] */
2619 if (GET_CODE (operands[2]) == REG)
2620 operands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
2622 operands[1] = adj_offsettable_operand (operands[2], 4);
2623 return \"move%.l %2,%3\;sub%.l %1,%R0\;subx%.l %3,%0\";
2626 else if (GET_CODE (operands[0]) == MEM)
2628 if (GET_CODE (operands[2]) == MEM
2629 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2630 return \"sub%.l %2,%0\;subx%.l %2,%0\";
2632 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2634 operands[1] = gen_rtx (MEM, SImode,
2635 gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
2636 gen_rtx (CONST_INT, VOIDmode, -8)));
2637 return \"move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1\";
2639 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2641 operands[1] = XEXP(operands[0], 0);
2642 return \"sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
2646 operands[1] = adj_offsettable_operand (operands[0], 4);
2647 return \"sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
2652 (define_insn "subsi3"
2653 [(set (match_operand:SI 0 "general_operand" "=m,r")
2654 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
2655 (match_operand:SI 2 "general_operand" "ds,mrs")))]
2660 [(set (match_operand:SI 0 "general_operand" "=a")
2661 (minus:SI (match_operand:SI 1 "general_operand" "0")
2663 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2667 (define_insn "subhi3"
2668 [(set (match_operand:HI 0 "general_operand" "=m,r")
2669 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2670 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2675 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2676 (minus:HI (match_dup 0)
2677 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2681 (define_insn "subqi3"
2682 [(set (match_operand:QI 0 "general_operand" "=m,d")
2683 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2684 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2689 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2690 (minus:QI (match_dup 0)
2691 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2695 (define_expand "subdf3"
2696 [(set (match_operand:DF 0 "general_operand" "")
2697 (minus:DF (match_operand:DF 1 "general_operand" "")
2698 (match_operand:DF 2 "general_operand" "")))]
2699 "TARGET_68881 || TARGET_FPA"
2703 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
2704 (minus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF")
2705 (match_operand:DF 2 "general_operand" "xH,dmF,0")))]
2709 if (rtx_equal_p (operands[0], operands[2]))
2710 return \"fprsub%.d %y1,%0\";
2711 if (rtx_equal_p (operands[0], operands[1]))
2712 return \"fpsub%.d %y2,%0\";
2713 if (which_alternative == 0)
2714 return \"fpsub3%.d %w2,%w1,%0\";
2715 return \"fpsub3%.d %x2,%x1,%0\";
2719 [(set (match_operand:DF 0 "general_operand" "=f")
2720 (minus:DF (match_operand:DF 1 "general_operand" "0")
2721 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
2726 [(set (match_operand:DF 0 "general_operand" "=f")
2727 (minus:DF (match_operand:DF 1 "general_operand" "0")
2728 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
2733 [(set (match_operand:DF 0 "general_operand" "=f")
2734 (minus:DF (match_operand:DF 1 "general_operand" "0")
2735 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
2740 [(set (match_operand:DF 0 "general_operand" "=f")
2741 (minus:DF (match_operand:DF 1 "general_operand" "0")
2742 (match_operand:DF 2 "general_operand" "fmG")))]
2746 if (REG_P (operands[2]))
2747 return \"f%&sub%.x %2,%0\";
2748 return \"f%&sub%.d %f2,%0\";
2751 (define_expand "subsf3"
2752 [(set (match_operand:SF 0 "general_operand" "")
2753 (minus:SF (match_operand:SF 1 "general_operand" "")
2754 (match_operand:SF 2 "general_operand" "")))]
2755 "TARGET_68881 || TARGET_FPA"
2759 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
2760 (minus:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
2761 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
2765 if (rtx_equal_p (operands[0], operands[2]))
2766 return \"fprsub%.s %w1,%0\";
2767 if (rtx_equal_p (operands[0], operands[1]))
2768 return \"fpsub%.s %w2,%0\";
2769 if (which_alternative == 0)
2770 return \"fpsub3%.s %w2,%w1,%0\";
2771 return \"fpsub3%.s %2,%1,%0\";
2775 [(set (match_operand:SF 0 "general_operand" "=f")
2776 (minus:SF (match_operand:SF 1 "general_operand" "0")
2777 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
2782 [(set (match_operand:SF 0 "general_operand" "=f")
2783 (minus:SF (match_operand:SF 1 "general_operand" "0")
2784 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
2789 [(set (match_operand:SF 0 "general_operand" "=f")
2790 (minus:SF (match_operand:SF 1 "general_operand" "0")
2791 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
2796 [(set (match_operand:SF 0 "general_operand" "=f")
2797 (minus:SF (match_operand:SF 1 "general_operand" "0")
2798 (match_operand:SF 2 "general_operand" "fdmF")))]
2802 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2803 return \"f%$sub%.x %2,%0\";
2804 return \"f%$sub%.s %f2,%0\";
2807 ;; multiply instructions
2809 (define_insn "mulhi3"
2810 [(set (match_operand:HI 0 "general_operand" "=d")
2811 (mult:HI (match_operand:HI 1 "general_operand" "%0")
2812 (match_operand:HI 2 "general_operand" "dmn")))]
2816 #if defined(MOTOROLA) && !defined(CRDS)
2817 return \"muls%.w %2,%0\";
2819 return \"muls %2,%0\";
2823 (define_insn "mulhisi3"
2824 [(set (match_operand:SI 0 "general_operand" "=d")
2825 (mult:SI (sign_extend:SI
2826 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2828 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
2832 #if defined(MOTOROLA) && !defined(CRDS)
2833 return \"muls%.w %2,%0\";
2835 return \"muls %2,%0\";
2840 [(set (match_operand:SI 0 "general_operand" "=d")
2841 (mult:SI (sign_extend:SI
2842 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2843 (match_operand:SI 2 "const_int_operand" "n")))]
2844 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
2847 #if defined(MOTOROLA) && !defined(CRDS)
2848 return \"muls%.w %2,%0\";
2850 return \"muls %2,%0\";
2854 (define_insn "mulsi3"
2855 [(set (match_operand:SI 0 "general_operand" "=d")
2856 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2857 (match_operand:SI 2 "general_operand" "dmsK")))]
2858 "TARGET_68020 || TARGET_5200"
2861 (define_insn "umulhisi3"
2862 [(set (match_operand:SI 0 "general_operand" "=d")
2863 (mult:SI (zero_extend:SI
2864 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2866 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
2870 #if defined(MOTOROLA) && !defined(CRDS)
2871 return \"mulu%.w %2,%0\";
2873 return \"mulu %2,%0\";
2878 [(set (match_operand:SI 0 "general_operand" "=d")
2879 (mult:SI (zero_extend:SI
2880 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2881 (match_operand:SI 2 "const_int_operand" "n")))]
2882 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
2885 #if defined(MOTOROLA) && !defined(CRDS)
2886 return \"mulu%.w %2,%0\";
2888 return \"mulu %2,%0\";
2892 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
2893 ;; proper matching constraint. This is because the matching is between
2894 ;; the high-numbered word of the DImode operand[0] and operand[1].
2895 (define_expand "umulsidi3"
2897 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
2898 (mult:SI (match_operand:SI 1 "register_operand" "")
2899 (match_operand:SI 2 "nonimmediate_operand" "")))
2900 (set (subreg:SI (match_dup 0) 0)
2901 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2902 (zero_extend:DI (match_dup 2)))
2903 (const_int 32))))])]
2904 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2908 [(set (match_operand:SI 0 "register_operand" "=d")
2909 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2910 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2911 (set (match_operand:SI 3 "register_operand" "=d")
2912 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2913 (zero_extend:DI (match_dup 2)))
2915 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2918 ; Match immediate case. For 2.4 only match things < 2^31.
2919 ; It's tricky with larger values in these patterns since we need to match
2920 ; values between the two parallel multiplies, between a CONST_DOUBLE and
2923 [(set (match_operand:SI 0 "register_operand" "=d")
2924 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2925 (match_operand:SI 2 "const_int_operand" "n")))
2926 (set (match_operand:SI 3 "register_operand" "=d")
2927 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2930 "TARGET_68020 && !TARGET_68060 && !TARGET_5200
2931 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
2934 (define_expand "mulsidi3"
2936 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
2937 (mult:SI (match_operand:SI 1 "register_operand" "")
2938 (match_operand:SI 2 "nonimmediate_operand" "")))
2939 (set (subreg:SI (match_dup 0) 0)
2940 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2941 (sign_extend:DI (match_dup 2)))
2942 (const_int 32))))])]
2943 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2947 [(set (match_operand:SI 0 "register_operand" "=d")
2948 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2949 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2950 (set (match_operand:SI 3 "register_operand" "=d")
2951 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2952 (sign_extend:DI (match_dup 2)))
2954 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2958 [(set (match_operand:SI 0 "register_operand" "=d")
2959 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2960 (match_operand:SI 2 "const_sint32_operand" "")))
2961 (set (match_operand:SI 3 "register_operand" "=d")
2962 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2965 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2968 (define_expand "umulsi3_highpart"
2970 [(set (match_operand:SI 0 "register_operand" "")
2973 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
2974 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
2976 (clobber (match_dup 3))])]
2977 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2980 operands[3] = gen_reg_rtx (SImode);
2981 if (GET_CODE (operands[2]) == CONST_INT
2982 || GET_CODE (operands[2]) == CONST_DOUBLE)
2984 if (! const_uint32_operand (operands[2], VOIDmode))
2986 /* We have to adjust the operand order for the matching constraints. */
2987 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
2988 operands[1], operands[2]));
2994 [(set (match_operand:SI 0 "register_operand" "=d")
2997 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
2998 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3000 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3001 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3004 (define_insn "const_umulsi3_highpart"
3005 [(set (match_operand:SI 0 "register_operand" "=d")
3008 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
3009 (match_operand 3 "const_uint32_operand" ""))
3011 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3012 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3015 (define_expand "smulsi3_highpart"
3017 [(set (match_operand:SI 0 "register_operand" "")
3020 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
3021 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
3023 (clobber (match_dup 3))])]
3024 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3027 operands[3] = gen_reg_rtx (SImode);
3028 if (GET_CODE (operands[2]) == CONST_INT
3029 || GET_CODE (operands[2]) == CONST_DOUBLE)
3031 if (! const_sint32_operand (operands[2], VOIDmode))
3033 /* We have to adjust the operand order for the matching constraints. */
3034 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
3035 operands[1], operands[2]));
3041 [(set (match_operand:SI 0 "register_operand" "=d")
3044 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3045 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3047 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3048 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3051 (define_insn "const_smulsi3_highpart"
3052 [(set (match_operand:SI 0 "register_operand" "=d")
3055 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
3056 (match_operand 3 "const_sint32_operand" ""))
3058 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3059 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3062 (define_expand "muldf3"
3063 [(set (match_operand:DF 0 "general_operand" "")
3064 (mult:DF (match_operand:DF 1 "general_operand" "")
3065 (match_operand:DF 2 "general_operand" "")))]
3066 "TARGET_68881 || TARGET_FPA"
3070 [(set (match_operand:DF 0 "general_operand" "=x,y")
3071 (mult:DF (match_operand:DF 1 "general_operand" "%xH,y")
3072 (match_operand:DF 2 "general_operand" "xH,rmF")))]
3076 if (rtx_equal_p (operands[1], operands[2]))
3077 return \"fpsqr%.d %y1,%0\";
3078 if (rtx_equal_p (operands[0], operands[1]))
3079 return \"fpmul%.d %y2,%0\";
3080 if (rtx_equal_p (operands[0], operands[2]))
3081 return \"fpmul%.d %y1,%0\";
3082 if (which_alternative == 0)
3083 return \"fpmul3%.d %w2,%w1,%0\";
3084 return \"fpmul3%.d %x2,%x1,%0\";
3088 [(set (match_operand:DF 0 "general_operand" "=f")
3089 (mult:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
3090 (match_operand:DF 1 "general_operand" "0")))]
3095 [(set (match_operand:DF 0 "general_operand" "=f")
3096 (mult:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
3097 (match_operand:DF 1 "general_operand" "0")))]
3102 [(set (match_operand:DF 0 "general_operand" "=f")
3103 (mult:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
3104 (match_operand:DF 1 "general_operand" "0")))]
3109 [(set (match_operand:DF 0 "general_operand" "=f")
3110 (mult:DF (match_operand:DF 1 "general_operand" "%0")
3111 (match_operand:DF 2 "general_operand" "fmG")))]
3115 if (GET_CODE (operands[2]) == CONST_DOUBLE
3116 && floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
3118 int i = floating_exact_log2 (operands[2]);
3119 operands[2] = gen_rtx (CONST_INT, VOIDmode, i);
3120 return \"fscale%.l %2,%0\";
3122 if (REG_P (operands[2]))
3123 return \"f%&mul%.x %2,%0\";
3124 return \"f%&mul%.d %f2,%0\";
3127 (define_expand "mulsf3"
3128 [(set (match_operand:SF 0 "general_operand" "")
3129 (mult:SF (match_operand:SF 1 "general_operand" "")
3130 (match_operand:SF 2 "general_operand" "")))]
3131 "TARGET_68881 || TARGET_FPA"
3135 [(set (match_operand:SF 0 "general_operand" "=x,y")
3136 (mult:SF (match_operand:SF 1 "general_operand" "%xH,y")
3137 (match_operand:SF 2 "general_operand" "xH,rmF")))]
3141 if (rtx_equal_p (operands[1], operands[2]))
3142 return \"fpsqr%.s %w1,%0\";
3143 if (rtx_equal_p (operands[0], operands[1]))
3144 return \"fpmul%.s %w2,%0\";
3145 if (rtx_equal_p (operands[0], operands[2]))
3146 return \"fpmul%.s %w1,%0\";
3147 if (which_alternative == 0)
3148 return \"fpmul3%.s %w2,%w1,%0\";
3149 return \"fpmul3%.s %2,%1,%0\";
3153 [(set (match_operand:SF 0 "general_operand" "=f")
3154 (mult:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
3155 (match_operand:SF 1 "general_operand" "0")))]
3159 return (TARGET_68040_ONLY
3160 ? \"fsmul%.l %2,%0\"
3161 : \"fsglmul%.l %2,%0\");
3165 [(set (match_operand:SF 0 "general_operand" "=f")
3166 (mult:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
3167 (match_operand:SF 1 "general_operand" "0")))]
3171 return (TARGET_68040_ONLY
3172 ? \"fsmul%.w %2,%0\"
3173 : \"fsglmul%.w %2,%0\");
3177 [(set (match_operand:SF 0 "general_operand" "=f")
3178 (mult:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
3179 (match_operand:SF 1 "general_operand" "0")))]
3183 return (TARGET_68040_ONLY
3184 ? \"fsmul%.b %2,%0\"
3185 : \"fsglmul%.b %2,%0\");
3189 [(set (match_operand:SF 0 "general_operand" "=f")
3190 (mult:SF (match_operand:SF 1 "general_operand" "%0")
3191 (match_operand:SF 2 "general_operand" "fdmF")))]
3195 #ifdef FSGLMUL_USE_S
3196 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3197 return (TARGET_68040_ONLY
3198 ? \"fsmul%.s %2,%0\"
3199 : \"fsglmul%.s %2,%0\");
3201 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3202 return (TARGET_68040_ONLY
3203 ? \"fsmul%.x %2,%0\"
3204 : \"fsglmul%.x %2,%0\");
3206 return (TARGET_68040_ONLY
3207 ? \"fsmul%.s %f2,%0\"
3208 : \"fsglmul%.s %f2,%0\");
3211 ;; divide instructions
3213 (define_expand "divdf3"
3214 [(set (match_operand:DF 0 "general_operand" "")
3215 (div:DF (match_operand:DF 1 "general_operand" "")
3216 (match_operand:DF 2 "general_operand" "")))]
3217 "TARGET_68881 || TARGET_FPA"
3221 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
3222 (div:DF (match_operand:DF 1 "general_operand" "xH,y,rmF")
3223 (match_operand:DF 2 "general_operand" "xH,rmF,0")))]
3227 if (rtx_equal_p (operands[0], operands[2]))
3228 return \"fprdiv%.d %y1,%0\";
3229 if (rtx_equal_p (operands[0], operands[1]))
3230 return \"fpdiv%.d %y2,%0\";
3231 if (which_alternative == 0)
3232 return \"fpdiv3%.d %w2,%w1,%0\";
3233 return \"fpdiv3%.d %x2,%x1,%x0\";
3237 [(set (match_operand:DF 0 "general_operand" "=f")
3238 (div:DF (match_operand:DF 1 "general_operand" "0")
3239 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
3244 [(set (match_operand:DF 0 "general_operand" "=f")
3245 (div:DF (match_operand:DF 1 "general_operand" "0")
3246 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
3251 [(set (match_operand:DF 0 "general_operand" "=f")
3252 (div:DF (match_operand:DF 1 "general_operand" "0")
3253 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
3258 [(set (match_operand:DF 0 "general_operand" "=f")
3259 (div:DF (match_operand:DF 1 "general_operand" "0")
3260 (match_operand:DF 2 "general_operand" "fmG")))]
3264 if (REG_P (operands[2]))
3265 return \"f%&div%.x %2,%0\";
3266 return \"f%&div%.d %f2,%0\";
3269 (define_expand "divsf3"
3270 [(set (match_operand:SF 0 "general_operand" "")
3271 (div:SF (match_operand:SF 1 "general_operand" "")
3272 (match_operand:SF 2 "general_operand" "")))]
3273 "TARGET_68881 || TARGET_FPA"
3277 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
3278 (div:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
3279 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
3283 if (rtx_equal_p (operands[0], operands[1]))
3284 return \"fpdiv%.s %w2,%0\";
3285 if (rtx_equal_p (operands[0], operands[2]))
3286 return \"fprdiv%.s %w1,%0\";
3287 if (which_alternative == 0)
3288 return \"fpdiv3%.s %w2,%w1,%0\";
3289 return \"fpdiv3%.s %2,%1,%0\";
3293 [(set (match_operand:SF 0 "general_operand" "=f")
3294 (div:SF (match_operand:SF 1 "general_operand" "0")
3295 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
3299 return (TARGET_68040_ONLY
3300 ? \"fsdiv%.l %2,%0\"
3301 : \"fsgldiv%.l %2,%0\");
3305 [(set (match_operand:SF 0 "general_operand" "=f")
3306 (div:SF (match_operand:SF 1 "general_operand" "0")
3307 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
3311 return (TARGET_68040_ONLY
3312 ? \"fsdiv%.w %2,%0\"
3313 : \"fsgldiv%.w %2,%0\");
3317 [(set (match_operand:SF 0 "general_operand" "=f")
3318 (div:SF (match_operand:SF 1 "general_operand" "0")
3319 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
3323 return (TARGET_68040_ONLY
3324 ? \"fsdiv%.b %2,%0\"
3325 : \"fsgldiv%.b %2,%0\");
3329 [(set (match_operand:SF 0 "general_operand" "=f")
3330 (div:SF (match_operand:SF 1 "general_operand" "0")
3331 (match_operand:SF 2 "general_operand" "fdmF")))]
3335 #ifdef FSGLDIV_USE_S
3336 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3337 return (TARGET_68040_ONLY
3338 ? \"fsdiv%.s %2,%0\"
3339 : \"fsgldiv%.s %2,%0\");
3341 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3342 return (TARGET_68040_ONLY
3343 ? \"fsdiv%.x %2,%0\"
3344 : \"fsgldiv%.x %2,%0\");
3346 return (TARGET_68040_ONLY
3347 ? \"fsdiv%.s %f2,%0\"
3348 : \"fsgldiv%.s %f2,%0\");
3351 ;; Remainder instructions.
3353 (define_insn "divmodsi4"
3354 [(set (match_operand:SI 0 "general_operand" "=d")
3355 (div:SI (match_operand:SI 1 "general_operand" "0")
3356 (match_operand:SI 2 "general_operand" "dmsK")))
3357 (set (match_operand:SI 3 "general_operand" "=d")
3358 (mod:SI (match_dup 1) (match_dup 2)))]
3359 "TARGET_68020 && !TARGET_5200"
3362 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3363 return \"divs%.l %2,%0\";
3365 return \"divsl%.l %2,%3:%0\";
3368 (define_insn "udivmodsi4"
3369 [(set (match_operand:SI 0 "general_operand" "=d")
3370 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3371 (match_operand:SI 2 "general_operand" "dmsK")))
3372 (set (match_operand:SI 3 "general_operand" "=d")
3373 (umod:SI (match_dup 1) (match_dup 2)))]
3374 "TARGET_68020 && !TARGET_5200"
3377 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3378 return \"divu%.l %2,%0\";
3380 return \"divul%.l %2,%3:%0\";
3383 (define_insn "divmodhi4"
3384 [(set (match_operand:HI 0 "general_operand" "=d")
3385 (div:HI (match_operand:HI 1 "general_operand" "0")
3386 (match_operand:HI 2 "general_operand" "dmsK")))
3387 (set (match_operand:HI 3 "general_operand" "=d")
3388 (mod:HI (match_dup 1) (match_dup 2)))]
3393 output_asm_insn(\"ext%.l %0\;divs%.w %2,%0\", operands);
3395 output_asm_insn(\"extl %0\;divs %2,%0\", operands);
3397 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3400 return \"move%.l %0,%3\;swap %3\";
3406 (define_insn "udivmodhi4"
3407 [(set (match_operand:HI 0 "general_operand" "=d")
3408 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3409 (match_operand:HI 2 "general_operand" "dmsK")))
3410 (set (match_operand:HI 3 "general_operand" "=d")
3411 (umod:HI (match_dup 1) (match_dup 2)))]
3416 output_asm_insn(\"and%.l %#0xFFFF,%0\;divu%.w %2,%0\", operands);
3418 output_asm_insn(\"and%.l %#0xFFFF,%0\;divu %2,%0\", operands);
3420 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3423 return \"move%.l %0,%3\;swap %3\";
3429 ;; logical-and instructions
3431 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3432 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3433 ;; can't allocate pseudos into it.
3435 (define_expand "andsi3"
3436 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3437 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3438 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3442 (define_insn "andsi3_internal"
3443 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3444 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3445 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3450 if (GET_CODE (operands[2]) == CONST_INT
3451 && (INTVAL (operands[2]) | 0xffff) == 0xffffffff
3452 && (DATA_REG_P (operands[0])
3453 || offsettable_memref_p (operands[0])))
3455 if (GET_CODE (operands[0]) != REG)
3456 operands[0] = adj_offsettable_operand (operands[0], 2);
3457 operands[2] = gen_rtx (CONST_INT, VOIDmode,
3458 INTVAL (operands[2]) & 0xffff);
3459 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3461 if (operands[2] == const0_rtx)
3462 return \"clr%.w %0\";
3463 return \"and%.w %2,%0\";
3465 if (GET_CODE (operands[2]) == CONST_INT
3466 && (logval = exact_log2 (~ INTVAL (operands[2]))) >= 0
3467 && (DATA_REG_P (operands[0])
3468 || offsettable_memref_p (operands[0])))
3470 if (DATA_REG_P (operands[0]))
3472 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval);
3476 operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
3477 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8);
3479 /* This does not set condition codes in a standard way. */
3481 return \"bclr %1,%0\";
3483 return \"and%.l %2,%0\";
3486 (define_insn "andsi3_5200"
3487 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3488 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3489 (match_operand:SI 2 "general_operand" "d,dmsK")))]
3493 (define_insn "andhi3"
3494 [(set (match_operand:HI 0 "general_operand" "=m,d")
3495 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3496 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3501 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3502 (and:HI (match_dup 0)
3503 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3508 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3509 (and:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3514 (define_insn "andqi3"
3515 [(set (match_operand:QI 0 "general_operand" "=m,d")
3516 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3517 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3522 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3523 (and:QI (match_dup 0)
3524 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3529 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3530 (and:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3535 ;; inclusive-or instructions
3537 (define_expand "iorsi3"
3538 [(set (match_operand:SI 0 "general_operand" "")
3539 (ior:SI (match_operand:SI 1 "general_operand" "")
3540 (match_operand:SI 2 "general_operand" "")))]
3544 (define_insn "iorsi3_internal"
3545 [(set (match_operand:SI 0 "general_operand" "=m,d")
3546 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3547 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3551 register int logval;
3552 if (GET_CODE (operands[2]) == CONST_INT
3553 && INTVAL (operands[2]) >> 16 == 0
3554 && (DATA_REG_P (operands[0])
3555 || offsettable_memref_p (operands[0])))
3557 if (GET_CODE (operands[0]) != REG)
3558 operands[0] = adj_offsettable_operand (operands[0], 2);
3559 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3561 return \"or%.w %2,%0\";
3563 if (GET_CODE (operands[2]) == CONST_INT
3564 && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
3565 && (DATA_REG_P (operands[0])
3566 || offsettable_memref_p (operands[0])))
3568 if (DATA_REG_P (operands[0]))
3570 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval);
3574 operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
3575 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8);
3578 return \"bset %1,%0\";
3580 return \"or%.l %2,%0\";
3583 (define_insn "iorsi3_5200"
3584 [(set (match_operand:SI 0 "general_operand" "=m,d")
3585 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3586 (match_operand:SI 2 "general_operand" "d,dmsK")))]
3590 (define_insn "iorhi3"
3591 [(set (match_operand:HI 0 "general_operand" "=m,d")
3592 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3593 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3598 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3599 (ior:HI (match_dup 0)
3600 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3605 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3606 (ior:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3611 (define_insn "iorqi3"
3612 [(set (match_operand:QI 0 "general_operand" "=m,d")
3613 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3614 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3619 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3620 (ior:QI (match_dup 0)
3621 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3626 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3627 (ior:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3632 ;; On all 68k models, this makes faster code in a special case.
3633 ;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
3635 (define_insn "iorsi_zexthi_ashl16"
3636 [(set (match_operand:SI 0 "general_operand" "=d,d")
3637 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "dmn,dmn"))
3638 (ashift:SI (match_operand:SI 2 "general_operand" "o,0")
3644 if (GET_CODE (operands[2]) != REG)
3646 operands[2] = adj_offsettable_operand (operands[2], 2);
3647 output_asm_insn (\"move%.w %2,%0\", operands);
3649 return \"swap %0\;mov%.w %1,%0\";
3653 [(set (match_operand:SI 0 "general_operand" "=o,d")
3654 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3655 (match_operand:SI 2 "general_operand" "0,0")))]
3662 byte_mode = (GET_MODE(operands[1]) == QImode);
3663 if (GET_CODE (operands[0]) == MEM)
3664 operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
3666 return \"or%.b %1,%0\";
3668 return \"or%.w %1,%0\";
3673 (define_expand "xorsi3"
3674 [(set (match_operand:SI 0 "general_operand" "")
3675 (xor:SI (match_operand:SI 1 "general_operand" "")
3676 (match_operand:SI 2 "general_operand" "")))]
3680 (define_insn "xorsi3_internal"
3681 [(set (match_operand:SI 0 "general_operand" "=do,m")
3682 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3683 (match_operand:SI 2 "general_operand" "di,dKs")))]
3687 if (GET_CODE (operands[2]) == CONST_INT
3688 && INTVAL (operands[2]) >> 16 == 0
3689 && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0])))
3691 if (! DATA_REG_P (operands[0]))
3692 operands[0] = adj_offsettable_operand (operands[0], 2);
3693 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3695 return \"eor%.w %2,%0\";
3697 return \"eor%.l %2,%0\";
3700 (define_insn "xorsi3_5200"
3701 [(set (match_operand:SI 0 "general_operand" "=dm")
3702 (xor:SI (match_operand:SI 1 "general_operand" "%0")
3703 (match_operand:SI 2 "general_operand" "dn")))]
3707 (define_insn "xorhi3"
3708 [(set (match_operand:HI 0 "general_operand" "=dm")
3709 (xor:HI (match_operand:HI 1 "general_operand" "%0")
3710 (match_operand:HI 2 "general_operand" "dn")))]
3715 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3716 (xor:HI (match_dup 0)
3717 (match_operand:HI 1 "general_operand" "dn")))]
3722 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3723 (xor:HI (match_operand:HI 1 "general_operand" "dn")
3728 (define_insn "xorqi3"
3729 [(set (match_operand:QI 0 "general_operand" "=dm")
3730 (xor:QI (match_operand:QI 1 "general_operand" "%0")
3731 (match_operand:QI 2 "general_operand" "dn")))]
3736 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
3737 (xor:QI (match_dup 0)
3738 (match_operand:QI 1 "general_operand" "dn")))]
3743 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
3744 (xor:QI (match_operand:QI 1 "general_operand" "dn")
3749 ;; negation instructions
3751 (define_expand "negdi2"
3752 [(set (match_operand:DI 0 "general_operand" "")
3753 (neg:DI (match_operand:DI 1 "general_operand" "")))]
3758 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
3760 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
3764 (define_insn "negdi2_internal"
3765 [(set (match_operand:DI 0 "general_operand" "=<,do,!*a")
3766 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
3770 if (which_alternative == 0)
3771 return \"neg%.l %0\;negx%.l %0\";
3772 if (GET_CODE (operands[0]) == REG)
3773 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3775 operands[1] = adj_offsettable_operand (operands[0], 4);
3776 if (ADDRESS_REG_P (operands[0]))
3777 return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
3779 return \"neg%.l %1\;negx%.l %0\";
3782 (define_insn "negdi2_5200"
3783 [(set (match_operand:DI 0 "general_operand" "=d")
3784 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
3788 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3789 return \"neg%.l %1\;negx%.l %0\";
3792 (define_expand "negsi2"
3793 [(set (match_operand:SI 0 "general_operand" "")
3794 (neg:SI (match_operand:SI 1 "general_operand" "")))]
3799 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
3801 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
3805 (define_insn "negsi2_internal"
3806 [(set (match_operand:SI 0 "general_operand" "=dm")
3807 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3811 (define_insn "negsi2_5200"
3812 [(set (match_operand:SI 0 "general_operand" "=d")
3813 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3817 (define_insn "neghi2"
3818 [(set (match_operand:HI 0 "general_operand" "=dm")
3819 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
3824 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3825 (neg:HI (match_dup 0)))]
3829 (define_insn "negqi2"
3830 [(set (match_operand:QI 0 "general_operand" "=dm")
3831 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
3836 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
3837 (neg:QI (match_dup 0)))]
3841 ;; If using software floating point, just flip the sign bit.
3843 (define_expand "negsf2"
3844 [(set (match_operand:SF 0 "general_operand" "")
3845 (neg:SF (match_operand:SF 1 "general_operand" "")))]
3849 if (!TARGET_FPA && !TARGET_68881)
3854 target = operand_subword_force (operands[0], 0, SFmode);
3855 result = expand_binop (SImode, xor_optab,
3856 operand_subword_force (operands[1], 0, SFmode),
3857 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
3861 if (result != target)
3862 emit_move_insn (result, target);
3864 /* Make a place for REG_EQUAL. */
3865 emit_move_insn (operands[0], operands[0]);
3871 [(set (match_operand:SF 0 "general_operand" "=x,y")
3872 (neg:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
3877 [(set (match_operand:SF 0 "general_operand" "=f,d")
3878 (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))]
3882 if (DATA_REG_P (operands[0]))
3884 operands[1] = gen_rtx (CONST_INT, VOIDmode, 31);
3885 return \"bchg %1,%0\";
3887 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3888 return \"f%$neg%.x %1,%0\";
3889 return \"f%$neg%.s %f1,%0\";
3892 (define_expand "negdf2"
3893 [(set (match_operand:DF 0 "general_operand" "")
3894 (neg:DF (match_operand:DF 1 "general_operand" "")))]
3898 if (!TARGET_FPA && !TARGET_68881)
3905 target = operand_subword (operands[0], 0, 1, DFmode);
3906 result = expand_binop (SImode, xor_optab,
3907 operand_subword_force (operands[1], 0, DFmode),
3908 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
3912 if (result != target)
3913 emit_move_insn (result, target);
3915 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
3916 operand_subword_force (operands[1], 1, DFmode));
3918 insns = get_insns ();
3921 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
3927 [(set (match_operand:DF 0 "general_operand" "=x,y")
3928 (neg:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
3933 [(set (match_operand:DF 0 "general_operand" "=f,d")
3934 (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
3938 if (DATA_REG_P (operands[0]))
3940 operands[1] = gen_rtx (CONST_INT, VOIDmode, 31);
3941 return \"bchg %1,%0\";
3943 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3944 return \"f%&neg%.x %1,%0\";
3945 return \"f%&neg%.d %f1,%0\";
3948 ;; Sqrt instruction for the 68881
3950 (define_insn "sqrtsf2"
3951 [(set (match_operand:SF 0 "general_operand" "=f")
3952 (sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
3956 if (FP_REG_P (operands[1]))
3957 return \"f%$sqrt%.x %1,%0\";
3959 return \"f%$sqrt%.s %1,%0\";
3962 (define_insn "sqrtdf2"
3963 [(set (match_operand:DF 0 "general_operand" "=f")
3964 (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
3968 if (FP_REG_P (operands[1]))
3969 return \"f%&sqrt%.x %1,%0\";
3971 return \"f%&sqrt%.d %1,%0\";
3974 ;; Absolute value instructions
3975 ;; If using software floating point, just zero the sign bit.
3977 (define_expand "abssf2"
3978 [(set (match_operand:SF 0 "general_operand" "")
3979 (abs:SF (match_operand:SF 1 "general_operand" "")))]
3983 if (!TARGET_FPA && !TARGET_68881)
3988 target = operand_subword_force (operands[0], 0, SFmode);
3989 result = expand_binop (SImode, and_optab,
3990 operand_subword_force (operands[1], 0, SFmode),
3991 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
3995 if (result != target)
3996 emit_move_insn (result, target);
3998 /* Make a place for REG_EQUAL. */
3999 emit_move_insn (operands[0], operands[0]);
4005 [(set (match_operand:SF 0 "general_operand" "=x,y")
4006 (abs:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4011 [(set (match_operand:SF 0 "general_operand" "=f")
4012 (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
4016 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4017 return \"f%$abs%.x %1,%0\";
4018 return \"f%$abs%.s %f1,%0\";
4021 (define_expand "absdf2"
4022 [(set (match_operand:DF 0 "general_operand" "")
4023 (abs:DF (match_operand:DF 1 "general_operand" "")))]
4027 if (!TARGET_FPA && !TARGET_68881)
4034 target = operand_subword (operands[0], 0, 1, DFmode);
4035 result = expand_binop (SImode, and_optab,
4036 operand_subword_force (operands[1], 0, DFmode),
4037 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
4041 if (result != target)
4042 emit_move_insn (result, target);
4044 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4045 operand_subword_force (operands[1], 1, DFmode));
4047 insns = get_insns ();
4050 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4056 [(set (match_operand:DF 0 "general_operand" "=x,y")
4057 (abs:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4062 [(set (match_operand:DF 0 "general_operand" "=f")
4063 (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
4067 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4068 return \"f%&abs%.x %1,%0\";
4069 return \"f%&abs%.d %f1,%0\";
4072 ;; one complement instructions
4074 ;; "one_cmpldi2" is only here to help combine().
4075 (define_insn "one_cmpldi2"
4076 [(set (match_operand:DI 0 "general_operand" "=dm")
4077 (not:DI (match_operand:DI 1 "general_operand" "0")))]
4082 if (GET_CODE (operands[0]) == REG)
4083 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4084 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
4085 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4086 operands[1] = operands[0];
4088 operands[1] = adj_offsettable_operand (operands[0], 4);
4089 return \"not%.l %1\;not%.l %0\";
4092 (define_expand "one_cmplsi2"
4093 [(set (match_operand:SI 0 "general_operand" "")
4094 (not:SI (match_operand:SI 1 "general_operand" "")))]
4099 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
4101 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
4105 (define_insn "one_cmplsi2_internal"
4106 [(set (match_operand:SI 0 "general_operand" "=dm")
4107 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4111 (define_insn "one_cmplsi2_5200"
4112 [(set (match_operand:SI 0 "general_operand" "=d")
4113 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4117 (define_insn "one_cmplhi2"
4118 [(set (match_operand:HI 0 "general_operand" "=dm")
4119 (not:HI (match_operand:HI 1 "general_operand" "0")))]
4124 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4125 (not:HI (match_dup 0)))]
4129 (define_insn "one_cmplqi2"
4130 [(set (match_operand:QI 0 "general_operand" "=dm")
4131 (not:QI (match_operand:QI 1 "general_operand" "0")))]
4136 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4137 (not:QI (match_dup 0)))]
4141 ;; arithmetic shift instructions
4142 ;; We don't need the shift memory by 1 bit instruction
4144 (define_insn "ashldi_extsi"
4145 [(set (match_operand:DI 0 "general_operand" "=ro")
4147 (match_operator:DI 2 "extend_operator"
4148 [(match_operand:SI 1 "general_operand" "rm")])
4154 if (GET_CODE (operands[0]) == REG)
4155 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4157 operands[2] = adj_offsettable_operand (operands[0], 4);
4158 if (ADDRESS_REG_P (operands[0]))
4159 return \"move%.l %1,%0\;sub%.l %2,%2\";
4161 return \"move%.l %1,%0\;clr%.l %2\";
4164 (define_insn "ashldi_sexthi"
4165 [(set (match_operand:DI 0 "general_operand" "=m,a*d")
4166 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
4168 (clobber (match_scratch:SI 2 "=a,X"))]
4173 if (GET_CODE (operands[0]) == MEM)
4175 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4176 return \"clr%.l %0\;move%.w %1,%2\;move%.l %2,%0\";
4177 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4178 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %0\";
4181 operands[3] = adj_offsettable_operand (operands[0], 4);
4182 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %3\";
4185 else if (DATA_REG_P (operands[0]))
4186 return \"move%.w %1,%0\;ext%.l %0\;clr%.l %R0\";
4188 return \"move%.w %1,%0\;sub%.l %R0,%R0\";
4191 (define_insn "ashldi_const32"
4192 [(set (match_operand:DI 0 "general_operand" "=rm")
4193 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
4199 if (GET_CODE (operands[1]) == REG)
4200 operands[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4202 operands[3] = adj_offsettable_operand (operands[1], 4);
4203 if (GET_CODE (operands[0]) == REG)
4204 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4205 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4206 return \"clr%.l %0\;move%.l %3,%0\";
4207 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4208 return \"move%.l %3,%0\;clr%.l %0\";
4210 operands[2] = adj_offsettable_operand (operands[0], 4);
4211 if (ADDRESS_REG_P (operands[2]))
4212 return \"move%.l %3,%0\;sub%.l %2,%2\";
4214 return \"move%.l %3,%0\;clr%.l %2\";
4217 ;; The predicate below must be general_operand, because ashldi3 allows that
4218 (define_insn "ashldi_const"
4219 [(set (match_operand:DI 0 "general_operand" "=d")
4220 (ashift:DI (match_operand:DI 1 "general_operand" "0")
4221 (match_operand 2 "const_int_operand" "n")))]
4222 "(INTVAL (operands[2]) == 1
4223 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4224 || INTVAL (operands[2]) == 2 || INTVAL (operands[2]) == 3)"
4227 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4228 if (INTVAL (operands[2]) == 1)
4229 return \"add%.l %1,%1\;addx%.l %0,%0\";
4230 else if (INTVAL (operands[2]) == 8)
4231 return \"rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1\";
4232 else if (INTVAL (operands[2]) == 16)
4233 return \"swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1\";
4234 else if (INTVAL (operands[2]) == 2)
4235 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4236 else/* if (INTVAL (operands[2]) == 3)*/
4237 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4240 (define_expand "ashldi3"
4241 [(set (match_operand:DI 0 "general_operand" "")
4242 (ashift:DI (match_operand:DI 1 "general_operand" "")
4243 (match_operand 2 "const_int_operand" "")))]
4247 if (GET_CODE (operands[2]) != CONST_INT
4248 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 32
4249 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4250 && INTVAL (operands[2]) != 2 && INTVAL (operands[2]) != 3))
4254 ;; On most 68k models, this makes faster code in a special case.
4256 (define_insn "ashlsi_16"
4257 [(set (match_operand:SI 0 "register_operand" "=d")
4258 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4264 return \"swap %0\;clr%.w %0\";
4267 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
4268 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
4270 ;; On the 68000, this makes faster code in a special case.
4272 (define_insn "ashlsi_17_24"
4273 [(set (match_operand:SI 0 "register_operand" "=d")
4274 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4275 (match_operand:SI 2 "const_int_operand" "n")))]
4276 "(! TARGET_68020 && !TARGET_5200
4277 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4282 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4283 return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\";
4286 (define_insn "ashlsi3"
4287 [(set (match_operand:SI 0 "register_operand" "=d")
4288 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4289 (match_operand:SI 2 "general_operand" "dI")))]
4293 if (operands[2] == const1_rtx)
4295 cc_status.flags = CC_NO_OVERFLOW;
4296 return \"add%.l %0,%0\";
4298 return \"lsl%.l %2,%0\";
4301 (define_insn "ashlhi3"
4302 [(set (match_operand:HI 0 "register_operand" "=d")
4303 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4304 (match_operand:HI 2 "general_operand" "dI")))]
4309 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4310 (ashift:HI (match_dup 0)
4311 (match_operand:HI 1 "general_operand" "dI")))]
4315 (define_insn "ashlqi3"
4316 [(set (match_operand:QI 0 "register_operand" "=d")
4317 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4318 (match_operand:QI 2 "general_operand" "dI")))]
4323 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4324 (ashift:QI (match_dup 0)
4325 (match_operand:QI 1 "general_operand" "dI")))]
4329 ;; On all 68k models, this makes faster code in a special case.
4331 (define_insn "ashrsi_16"
4332 [(set (match_operand:SI 0 "register_operand" "=d")
4333 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4336 "swap %0\;ext%.l %0")
4338 ;; On the 68000, this makes faster code in a special case.
4341 [(set (match_operand:SI 0 "register_operand" "=d")
4342 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4343 (match_operand:SI 2 "const_int_operand" "n")))]
4344 "(! TARGET_68020 && !TARGET_5200
4345 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4348 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4349 return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
4352 (define_insn "subreghi1ashrdi_const32"
4353 [(set (match_operand:HI 0 "general_operand" "=rm")
4354 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4355 (const_int 32)) 1))]
4359 if (GET_CODE (operands[1]) != REG)
4360 operands[1] = adj_offsettable_operand (operands[1], 2);
4361 return \"move%.w %1,%0\";
4364 (define_insn "subregsi1ashrdi_const32"
4365 [(set (match_operand:SI 0 "general_operand" "=rm")
4366 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4367 (const_int 32)) 1))]
4371 return \"move%.l %1,%0\";
4374 (define_insn "ashrdi_const32"
4375 [(set (match_operand:DI 0 "register_operand" "=d")
4376 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4382 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4384 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
4386 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
4389 (define_insn "ashrdi_const32_mem"
4390 [(set (match_operand:DI 0 "general_operand" "=o,<")
4391 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro")
4393 (clobber (match_scratch:SI 2 "=d,d"))]
4398 if (which_alternative == 1)
4399 operands[3] = operands[0];
4401 operands[3] = adj_offsettable_operand (operands[0], 4);
4403 return \"move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0\";
4405 return \"move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\";
4408 ;; The predicate below must be general_operand, because ashrdi3 allows that
4409 (define_insn "ashrdi_const"
4410 [(set (match_operand:DI 0 "general_operand" "=d")
4411 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
4412 (match_operand 2 "const_int_operand" "n")))]
4414 && ((INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == 2
4415 || INTVAL (operands[2]) == 3 || INTVAL (operands[2]) == 8
4416 || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 63))"
4419 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4420 if (INTVAL (operands[2]) == 63)
4421 return \"add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1\";
4423 if (INTVAL (operands[2]) == 1)
4424 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
4425 else if (INTVAL (operands[2]) == 8)
4426 return \"move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1\";
4427 else if (INTVAL (operands[2]) == 16)
4428 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;ext%.l %0\";
4429 else if (INTVAL (operands[2]) == 2)
4430 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4431 else/* if (INTVAL (operands[2]) == 3)*/
4432 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4435 (define_expand "ashrdi3"
4436 [(set (match_operand:DI 0 "general_operand" "")
4437 (ashiftrt:DI (match_operand:DI 1 "general_operand" "")
4438 (match_operand 2 "const_int_operand" "")))]
4442 if (GET_CODE (operands[2]) != CONST_INT
4443 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 2
4444 && INTVAL (operands[2]) != 3 && INTVAL (operands[2]) != 8
4445 && INTVAL (operands[2]) != 16 && INTVAL (operands[2]) != 32
4446 && INTVAL (operands[2]) != 63))
4450 ;; On all 68k models, this makes faster code in a special case.
4452 (define_insn "ashrsi_31"
4453 [(set (match_operand:SI 0 "register_operand" "=d")
4454 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4459 return \"add%.l %0,%0\;subx%.l %0,%0\";
4462 (define_insn "ashrsi3"
4463 [(set (match_operand:SI 0 "register_operand" "=d")
4464 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4465 (match_operand:SI 2 "general_operand" "dI")))]
4469 (define_insn "ashrhi3"
4470 [(set (match_operand:HI 0 "register_operand" "=d")
4471 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4472 (match_operand:HI 2 "general_operand" "dI")))]
4477 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4478 (ashiftrt:HI (match_dup 0)
4479 (match_operand:HI 1 "general_operand" "dI")))]
4483 (define_insn "ashrqi3"
4484 [(set (match_operand:QI 0 "register_operand" "=d")
4485 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4486 (match_operand:QI 2 "general_operand" "dI")))]
4491 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4492 (ashiftrt:QI (match_dup 0)
4493 (match_operand:QI 1 "general_operand" "dI")))]
4497 ;; logical shift instructions
4499 ;; commented out because of reload problems in 950612-1.c
4502 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4503 ;; (const_int 32)) 1))
4504 ;; (set (match_operand:SI 1 "general_operand" "=dm")
4505 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
4506 ;; (const_int 32)) 1))]
4510 ;; return \"move%.l %0,%1\";
4515 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4516 ;; (const_int 32)) 0))
4517 ;; (set (match_operand:DI 1 "general_operand" "=do")
4518 ;; (lshiftrt:DI (match_dup 0)
4519 ;; (const_int 32)))]
4523 ;; if (GET_CODE (operands[1]) == REG)
4524 ;; operands[2] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4526 ;; operands[2] = adj_offsettable_operand (operands[1], 4);
4527 ;; return \"move%.l %0,%2\;clr%.l %1\";
4530 (define_insn "subreg1lshrdi_const32"
4531 [(set (match_operand:SI 0 "general_operand" "=rm")
4532 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4533 (const_int 32)) 1))]
4537 return \"move%.l %1,%0\";
4540 (define_insn "lshrdi_const32"
4541 [(set (match_operand:DI 0 "general_operand" "=ro,<,>")
4542 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
4548 if (which_alternative == 1)
4549 return \"move%.l %1,%0\;clr%.l %0\";
4550 if (which_alternative == 2)
4551 return \"clr%.l %0\;move%.l %1,%0\";
4552 if (GET_CODE (operands[0]) == REG)
4553 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4555 operands[2] = adj_offsettable_operand (operands[0], 4);
4556 if (GET_CODE (operands[1]) == REG)
4557 operands[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4559 operands[3] = adj_offsettable_operand (operands[1], 4);
4560 if (ADDRESS_REG_P (operands[0]))
4561 return \"move%.l %1,%2\;sub%.l %0,%0\";
4563 return \"move%.l %1,%2\;clr%.l %0\";
4566 ;; The predicate below must be general_operand, because lshrdi3 allows that
4567 (define_insn "lshrdi_const"
4568 [(set (match_operand:DI 0 "general_operand" "=d")
4569 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
4570 (match_operand 2 "const_int_operand" "n")))]
4572 && ((INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == 2
4573 || INTVAL (operands[2]) == 3 || INTVAL (operands[2]) == 8
4574 || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 63))"
4577 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4578 if (INTVAL (operands[2]) == 63)
4579 return \"add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1\";
4581 if (INTVAL (operands[2]) == 1)
4582 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4583 else if (INTVAL (operands[2]) == 8)
4584 return \"move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1\";
4585 else if (INTVAL (operands[2]) == 16)
4586 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0\";
4587 else if (INTVAL (operands[2]) == 2)
4588 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4589 else /*if (INTVAL (operands[2]) == 3)*/
4590 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4593 (define_expand "lshrdi3"
4594 [(set (match_operand:DI 0 "general_operand" "")
4595 (lshiftrt:DI (match_operand:DI 1 "general_operand" "")
4596 (match_operand 2 "const_int_operand" "")))]
4600 if (GET_CODE (operands[2]) != CONST_INT
4601 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 2
4602 && INTVAL (operands[2]) != 3 && INTVAL (operands[2]) != 8
4603 && INTVAL (operands[2]) != 16 && INTVAL (operands[2]) != 32
4604 && INTVAL (operands[2]) != 63))
4608 ;; On all 68k models, this makes faster code in a special case.
4610 (define_insn "lshrsi_31"
4611 [(set (match_operand:SI 0 "register_operand" "=d")
4612 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4617 return \"add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0\";
4620 ;; On most 68k models, this makes faster code in a special case.
4622 (define_insn "lshrsi_16"
4623 [(set (match_operand:SI 0 "register_operand" "=d")
4624 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4630 return \"clr%.w %0\;swap %0\";
4633 ;; On the 68000, this makes faster code in a special case.
4635 (define_insn "lshrsi_17_24"
4636 [(set (match_operand:SI 0 "register_operand" "=d")
4637 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4638 (match_operand:SI 2 "const_int_operand" "n")))]
4639 "(! TARGET_68020 && !TARGET_5200
4640 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4643 /* I think lsr%.w sets the CC properly. */
4644 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4645 return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\";
4648 (define_insn "lshrsi3"
4649 [(set (match_operand:SI 0 "register_operand" "=d")
4650 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4651 (match_operand:SI 2 "general_operand" "dI")))]
4655 (define_insn "lshrhi3"
4656 [(set (match_operand:HI 0 "register_operand" "=d")
4657 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
4658 (match_operand:HI 2 "general_operand" "dI")))]
4663 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4664 (lshiftrt:HI (match_dup 0)
4665 (match_operand:HI 1 "general_operand" "dI")))]
4669 (define_insn "lshrqi3"
4670 [(set (match_operand:QI 0 "register_operand" "=d")
4671 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
4672 (match_operand:QI 2 "general_operand" "dI")))]
4677 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4678 (lshiftrt:QI (match_dup 0)
4679 (match_operand:QI 1 "general_operand" "dI")))]
4683 ;; rotate instructions
4685 (define_insn "rotlsi3"
4686 [(set (match_operand:SI 0 "register_operand" "=d")
4687 (rotate:SI (match_operand:SI 1 "register_operand" "0")
4688 (match_operand:SI 2 "general_operand" "dI")))]
4692 (define_insn "rotlhi3"
4693 [(set (match_operand:HI 0 "register_operand" "=d")
4694 (rotate:HI (match_operand:HI 1 "register_operand" "0")
4695 (match_operand:HI 2 "general_operand" "dI")))]
4701 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4702 (rotate:HI (match_dup 0)
4703 (match_operand:HI 1 "general_operand" "dI")))]
4707 (define_insn "rotlqi3"
4708 [(set (match_operand:QI 0 "register_operand" "=d")
4709 (rotate:QI (match_operand:QI 1 "register_operand" "0")
4710 (match_operand:QI 2 "general_operand" "dI")))]
4715 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4716 (rotate:QI (match_dup 0)
4717 (match_operand:QI 1 "general_operand" "dI")))]
4721 (define_insn "rotrsi3"
4722 [(set (match_operand:SI 0 "register_operand" "=d")
4723 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
4724 (match_operand:SI 2 "general_operand" "dI")))]
4728 (define_insn "rotrhi3"
4729 [(set (match_operand:HI 0 "register_operand" "=d")
4730 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
4731 (match_operand:HI 2 "general_operand" "dI")))]
4736 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4737 (rotatert:HI (match_dup 0)
4738 (match_operand:HI 1 "general_operand" "dI")))]
4742 (define_insn "rotrqi3"
4743 [(set (match_operand:QI 0 "register_operand" "=d")
4744 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
4745 (match_operand:QI 2 "general_operand" "dI")))]
4750 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4751 (rotatert:QI (match_dup 0)
4752 (match_operand:QI 1 "general_operand" "dI")))]
4757 ;; Bit set/clear in memory byte.
4759 ;; set bit, bit number is int
4760 (define_insn "bsetmemqi"
4761 [(set (match_operand:QI 0 "memory_operand" "+m")
4762 (ior:QI (subreg:QI (ashift:SI (const_int 1)
4763 (match_operand:SI 1 "general_operand" "d")) 0)
4769 return \"bset %1,%0\";
4772 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
4774 [(set (match_operand:QI 0 "memory_operand" "+m")
4775 (ior:QI (subreg:QI (ashift:SI (const_int 1)
4776 (match_operator:SI 2 "extend_operator"
4777 [(match_operand 1 "general_operand" "d")])) 0)
4783 return \"bset %1,%0\";
4786 ;; clear bit, bit number is int
4787 (define_insn "bclrmemqi"
4788 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
4790 (minus:SI (const_int 7)
4791 (match_operand:SI 1 "general_operand" "d")))
4797 return \"bclr %1,%0\";
4800 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
4802 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
4804 (minus:SI (const_int 7)
4805 (match_operator:SI 2 "extend_operator"
4806 [(match_operand 1 "general_operand" "d")])))
4812 return \"bclr %1,%0\";
4815 ;; Special cases of bit-field insns which we should
4816 ;; recognize in preference to the general case.
4817 ;; These handle aligned 8-bit and 16-bit fields,
4818 ;; which can usually be done with move instructions.
4821 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4822 ; alignment of structure members is specified.
4824 ; The move is allowed to be odd byte aligned, because that's still faster
4825 ; than an odd byte aligned bit field instruction.
4828 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
4830 (match_operand:SI 2 "const_int_operand" "n"))
4831 (match_operand:SI 3 "general_operand" "rmi"))]
4832 "TARGET_68020 && TARGET_BITFIELD
4833 && (INTVAL (operands[2]) % 8) == 0
4834 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
4838 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
4840 return \"move%.l %3,%0\";
4844 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
4845 (match_operand:SI 1 "const_int_operand" "n")
4846 (match_operand:SI 2 "const_int_operand" "n"))
4847 (match_operand:SI 3 "register_operand" "d"))]
4848 "TARGET_68020 && TARGET_BITFIELD
4849 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
4850 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
4851 && (GET_CODE (operands[0]) == REG
4852 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
4855 if (REG_P (operands[0]))
4857 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
4858 return \"bfins %3,%0{%b2:%b1}\";
4862 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
4864 if (GET_CODE (operands[3]) == MEM)
4865 operands[3] = adj_offsettable_operand (operands[3],
4866 (32 - INTVAL (operands[1])) / 8);
4867 if (INTVAL (operands[1]) == 8)
4868 return \"move%.b %3,%0\";
4869 return \"move%.w %3,%0\";
4874 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4875 ; alignment of structure members is specified.
4877 ; The move is allowed to be odd byte aligned, because that's still faster
4878 ; than an odd byte aligned bit field instruction.
4881 [(set (match_operand:SI 0 "general_operand" "=rm")
4882 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o")
4884 (match_operand:SI 3 "const_int_operand" "n")))]
4885 "TARGET_68020 && TARGET_BITFIELD
4886 && (INTVAL (operands[3]) % 8) == 0
4887 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
4891 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
4893 return \"move%.l %1,%0\";
4897 [(set (match_operand:SI 0 "general_operand" "=&d")
4898 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
4899 (match_operand:SI 2 "const_int_operand" "n")
4900 (match_operand:SI 3 "const_int_operand" "n")))]
4901 "TARGET_68020 && TARGET_BITFIELD
4902 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
4903 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
4904 && (GET_CODE (operands[1]) == REG
4905 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
4908 cc_status.flags |= CC_NOT_NEGATIVE;
4909 if (REG_P (operands[1]))
4911 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
4912 return \"bfextu %1{%b3:%b2},%0\";
4916 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
4918 output_asm_insn (\"clr%.l %0\", operands);
4919 if (GET_CODE (operands[0]) == MEM)
4920 operands[0] = adj_offsettable_operand (operands[0],
4921 (32 - INTVAL (operands[1])) / 8);
4922 if (INTVAL (operands[2]) == 8)
4923 return \"move%.b %1,%0\";
4924 return \"move%.w %1,%0\";
4928 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4929 ; alignment of structure members is specified.
4931 ; The move is allowed to be odd byte aligned, because that's still faster
4932 ; than an odd byte aligned bit field instruction.
4935 [(set (match_operand:SI 0 "general_operand" "=rm")
4936 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
4938 (match_operand:SI 3 "const_int_operand" "n")))]
4939 "TARGET_68020 && TARGET_BITFIELD
4940 && (INTVAL (operands[3]) % 8) == 0
4941 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
4945 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
4947 return \"move%.l %1,%0\";
4951 [(set (match_operand:SI 0 "general_operand" "=d")
4952 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
4953 (match_operand:SI 2 "const_int_operand" "n")
4954 (match_operand:SI 3 "const_int_operand" "n")))]
4955 "TARGET_68020 && TARGET_BITFIELD
4956 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
4957 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
4958 && (GET_CODE (operands[1]) == REG
4959 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
4962 if (REG_P (operands[1]))
4964 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
4965 return \"bfexts %1{%b3:%b2},%0\";
4969 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
4971 if (INTVAL (operands[2]) == 8)
4972 return \"move%.b %1,%0\;extb%.l %0\";
4973 return \"move%.w %1,%0\;ext%.l %0\";
4976 ;; Bit field instructions, general cases.
4977 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
4978 ;; so that its address is reloaded.
4980 (define_expand "extv"
4981 [(set (match_operand:SI 0 "general_operand" "")
4982 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
4983 (match_operand:SI 2 "general_operand" "")
4984 (match_operand:SI 3 "general_operand" "")))]
4985 "TARGET_68020 && TARGET_BITFIELD"
4989 [(set (match_operand:SI 0 "general_operand" "=d")
4990 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
4991 (match_operand:SI 2 "general_operand" "di")
4992 (match_operand:SI 3 "general_operand" "di")))]
4993 "TARGET_68020 && TARGET_BITFIELD"
4994 "bfexts %1{%b3:%b2},%0")
4996 (define_expand "extzv"
4997 [(set (match_operand:SI 0 "general_operand" "")
4998 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
4999 (match_operand:SI 2 "general_operand" "")
5000 (match_operand:SI 3 "general_operand" "")))]
5001 "TARGET_68020 && TARGET_BITFIELD"
5005 [(set (match_operand:SI 0 "general_operand" "=d,d")
5006 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
5007 (match_operand:SI 2 "general_operand" "di,di")
5008 (match_operand:SI 3 "general_operand" "di,di")))]
5009 "TARGET_68020 && TARGET_BITFIELD"
5012 if (GET_CODE (operands[2]) == CONST_INT)
5014 if (INTVAL (operands[2]) != 32)
5015 cc_status.flags |= CC_NOT_NEGATIVE;
5021 return \"bfextu %1{%b3:%b2},%0\";
5025 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5026 (match_operand:SI 1 "general_operand" "di")
5027 (match_operand:SI 2 "general_operand" "di"))
5028 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
5029 (match_operand 3 "const_int_operand" "n")))]
5030 "TARGET_68020 && TARGET_BITFIELD
5031 && (INTVAL (operands[3]) == -1
5032 || (GET_CODE (operands[1]) == CONST_INT
5033 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
5037 return \"bfchg %0{%b2:%b1}\";
5041 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5042 (match_operand:SI 1 "general_operand" "di")
5043 (match_operand:SI 2 "general_operand" "di"))
5045 "TARGET_68020 && TARGET_BITFIELD"
5049 return \"bfclr %0{%b2:%b1}\";
5053 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5054 (match_operand:SI 1 "general_operand" "di")
5055 (match_operand:SI 2 "general_operand" "di"))
5057 "TARGET_68020 && TARGET_BITFIELD"
5061 return \"bfset %0{%b2:%b1}\";
5064 (define_expand "insv"
5065 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
5066 (match_operand:SI 1 "general_operand" "")
5067 (match_operand:SI 2 "general_operand" ""))
5068 (match_operand:SI 3 "register_operand" ""))]
5069 "TARGET_68020 && TARGET_BITFIELD"
5073 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5074 (match_operand:SI 1 "general_operand" "di")
5075 (match_operand:SI 2 "general_operand" "di"))
5076 (match_operand:SI 3 "register_operand" "d"))]
5077 "TARGET_68020 && TARGET_BITFIELD"
5078 "bfins %3,%0{%b2:%b1}")
5080 ;; Now recognize bit field insns that operate on registers
5081 ;; (or at least were intended to do so).
5084 [(set (match_operand:SI 0 "general_operand" "=d")
5085 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5086 (match_operand:SI 2 "general_operand" "di")
5087 (match_operand:SI 3 "general_operand" "di")))]
5088 "TARGET_68020 && TARGET_BITFIELD"
5089 "bfexts %1{%b3:%b2},%0")
5092 [(set (match_operand:SI 0 "general_operand" "=d")
5093 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5094 (match_operand:SI 2 "general_operand" "di")
5095 (match_operand:SI 3 "general_operand" "di")))]
5096 "TARGET_68020 && TARGET_BITFIELD"
5099 if (GET_CODE (operands[2]) == CONST_INT)
5101 if (INTVAL (operands[2]) != 32)
5102 cc_status.flags |= CC_NOT_NEGATIVE;
5108 return \"bfextu %1{%b3:%b2},%0\";
5112 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5113 (match_operand:SI 1 "general_operand" "di")
5114 (match_operand:SI 2 "general_operand" "di"))
5116 "TARGET_68020 && TARGET_BITFIELD"
5120 return \"bfclr %0{%b2:%b1}\";
5124 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5125 (match_operand:SI 1 "general_operand" "di")
5126 (match_operand:SI 2 "general_operand" "di"))
5128 "TARGET_68020 && TARGET_BITFIELD"
5132 return \"bfset %0{%b2:%b1}\";
5136 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5137 (match_operand:SI 1 "general_operand" "di")
5138 (match_operand:SI 2 "general_operand" "di"))
5139 (match_operand:SI 3 "register_operand" "d"))]
5140 "TARGET_68020 && TARGET_BITFIELD"
5144 /* These special cases are now recognized by a specific pattern. */
5145 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5146 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5147 return \"move%.w %3,%0\";
5148 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5149 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
5150 return \"move%.b %3,%0\";
5152 return \"bfins %3,%0{%b2:%b1}\";
5155 ;; Special patterns for optimizing bit-field instructions.
5159 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5160 (match_operand:SI 1 "const_int_operand" "n")
5161 (match_operand:SI 2 "general_operand" "di")))]
5162 "TARGET_68020 && TARGET_BITFIELD"
5165 if (operands[1] == const1_rtx
5166 && GET_CODE (operands[2]) == CONST_INT)
5168 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5169 return output_btst (operands,
5170 gen_rtx (CONST_INT, VOIDmode,
5171 width - INTVAL (operands[2])),
5174 /* Pass 1000 as SIGNPOS argument so that btst will
5175 not think we are testing the sign bit for an `and'
5176 and assume that nonzero implies a negative result. */
5178 if (INTVAL (operands[1]) != 32)
5179 cc_status.flags = CC_NOT_NEGATIVE;
5180 return \"bftst %0{%b2:%b1}\";
5184 ;;; now handle the register cases
5187 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5188 (match_operand:SI 1 "const_int_operand" "n")
5189 (match_operand:SI 2 "general_operand" "di")))]
5190 "TARGET_68020 && TARGET_BITFIELD"
5193 if (operands[1] == const1_rtx
5194 && GET_CODE (operands[2]) == CONST_INT)
5196 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5197 return output_btst (operands,
5198 gen_rtx (CONST_INT, VOIDmode,
5199 width - INTVAL (operands[2])),
5202 /* Pass 1000 as SIGNPOS argument so that btst will
5203 not think we are testing the sign bit for an `and'
5204 and assume that nonzero implies a negative result. */
5206 if (INTVAL (operands[1]) != 32)
5207 cc_status.flags = CC_NOT_NEGATIVE;
5208 return \"bftst %0{%b2:%b1}\";
5211 (define_insn "scc0_di"
5212 [(set (match_operand:QI 0 "general_operand" "=dm")
5213 (match_operator 1 "valid_dbcc_comparison_p"
5214 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5218 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5221 (define_insn "scc_di"
5222 [(set (match_operand:QI 0 "general_operand" "=dm,dm")
5223 (match_operator 1 "valid_dbcc_comparison_p"
5224 [(match_operand:DI 2 "general_operand" "ro,r")
5225 (match_operand:DI 3 "general_operand" "r,ro")]))]
5229 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5233 [(set (match_operand:QI 0 "general_operand" "=dm")
5234 (eq:QI (cc0) (const_int 0)))]
5237 cc_status = cc_prev_status;
5238 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5242 [(set (match_operand:QI 0 "general_operand" "=dm")
5243 (ne:QI (cc0) (const_int 0)))]
5246 cc_status = cc_prev_status;
5247 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5251 [(set (match_operand:QI 0 "general_operand" "=dm")
5252 (gt:QI (cc0) (const_int 0)))]
5255 cc_status = cc_prev_status;
5256 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5260 [(set (match_operand:QI 0 "general_operand" "=dm")
5261 (gtu:QI (cc0) (const_int 0)))]
5263 "* cc_status = cc_prev_status;
5264 return \"shi %0\"; ")
5267 [(set (match_operand:QI 0 "general_operand" "=dm")
5268 (lt:QI (cc0) (const_int 0)))]
5270 "* cc_status = cc_prev_status;
5271 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5274 [(set (match_operand:QI 0 "general_operand" "=dm")
5275 (ltu:QI (cc0) (const_int 0)))]
5277 "* cc_status = cc_prev_status;
5278 return \"scs %0\"; ")
5281 [(set (match_operand:QI 0 "general_operand" "=dm")
5282 (ge:QI (cc0) (const_int 0)))]
5284 "* cc_status = cc_prev_status;
5285 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5288 [(set (match_operand:QI 0 "general_operand" "=dm")
5289 (geu:QI (cc0) (const_int 0)))]
5291 "* cc_status = cc_prev_status;
5292 return \"scc %0\"; ")
5295 [(set (match_operand:QI 0 "general_operand" "=dm")
5296 (le:QI (cc0) (const_int 0)))]
5299 cc_status = cc_prev_status;
5300 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5304 [(set (match_operand:QI 0 "general_operand" "=dm")
5305 (leu:QI (cc0) (const_int 0)))]
5307 "* cc_status = cc_prev_status;
5308 return \"sls %0\"; ")
5310 ;; Basic conditional jump instructions.
5312 (define_insn "beq0_di"
5314 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
5316 (label_ref (match_operand 1 "" ","))
5318 (clobber (match_scratch:SI 2 "=d,d"))]
5323 if (which_alternative == 1)
5325 return \"move%.l %0,%2\;or%.l %0,%2\;jbeq %l1\";
5327 return \"move%.l %0,%2\;or%.l %0,%2\;jeq %l1\";
5329 if ((cc_prev_status.value1
5330 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5331 || (cc_prev_status.value2
5332 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5334 cc_status = cc_prev_status;
5336 return \"jbeq %l1\";
5341 if (GET_CODE (operands[0]) == REG)
5342 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
5344 operands[3] = adj_offsettable_operand (operands[0], 4);
5345 if (! ADDRESS_REG_P (operands[0]))
5347 return \"move%.l %0,%2\;or%.l %3,%2\;jbeq %l1\";
5349 return \"move%.l %0,%2\;or%.l %3,%2\;jeq %l1\";
5351 operands[4] = gen_label_rtx();
5353 output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands);
5355 output_asm_insn (\"tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1\", operands);
5357 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5358 CODE_LABEL_NUMBER (operands[4]));
5362 (define_insn "bne0_di"
5364 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
5366 (label_ref (match_operand 1 "" ","))
5368 (clobber (match_scratch:SI 2 "=d,X"))]
5372 if ((cc_prev_status.value1
5373 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5374 || (cc_prev_status.value2
5375 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5377 cc_status = cc_prev_status;
5379 return \"jbne %l1\";
5385 if (GET_CODE (operands[0]) == REG)
5386 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
5388 operands[3] = adj_offsettable_operand (operands[0], 4);
5389 if (ADDRESS_REG_P (operands[0]))
5391 return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\";
5393 return \"tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1\";
5397 return \"move%.l %0,%2\;or%.l %3,%2\;jbne %l1\";
5399 return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\";
5403 (define_insn "bge0_di"
5405 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
5407 (label_ref (match_operand 1 "" ""))
5412 if ((cc_prev_status.value1
5413 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5414 || (cc_prev_status.value2
5415 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5417 cc_status = cc_prev_status;
5418 if (cc_status.flags & CC_REVERSED)
5421 return \"jble %l1\";
5429 return \"jbpl %l1\";
5437 return \"tst%.l %0\;jbpl %l1\";
5439 return \"tst%.l %0\;jpl %l1\";
5443 (define_insn "blt0_di"
5445 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
5447 (label_ref (match_operand 1 "" ""))
5452 if ((cc_prev_status.value1
5453 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5454 || (cc_prev_status.value2
5455 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5457 cc_status = cc_prev_status;
5458 if (cc_status.flags & CC_REVERSED)
5461 return \"jbgt %l1\";
5469 return \"jbmi %l1\";
5477 return \"tst%.l %0\;jbmi %l1\";
5479 return \"tst%.l %0\;jmi %l1\";
5485 (if_then_else (eq (cc0)
5487 (label_ref (match_operand 0 "" ""))
5493 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
5495 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
5501 (if_then_else (ne (cc0)
5503 (label_ref (match_operand 0 "" ""))
5509 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
5511 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
5517 (if_then_else (gt (cc0)
5519 (label_ref (match_operand 0 "" ""))
5524 OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0);
5526 OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0);
5532 (if_then_else (gtu (cc0)
5534 (label_ref (match_operand 0 "" ""))
5539 return \"jbhi %l0\";
5547 (if_then_else (lt (cc0)
5549 (label_ref (match_operand 0 "" ""))
5554 OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\");
5556 OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\");
5562 (if_then_else (ltu (cc0)
5564 (label_ref (match_operand 0 "" ""))
5569 return \"jbcs %l0\";
5577 (if_then_else (ge (cc0)
5579 (label_ref (match_operand 0 "" ""))
5584 OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\");
5586 OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\");
5592 (if_then_else (geu (cc0)
5594 (label_ref (match_operand 0 "" ""))
5599 return \"jbcc %l0\";
5607 (if_then_else (le (cc0)
5609 (label_ref (match_operand 0 "" ""))
5614 OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0);
5616 OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0);
5622 (if_then_else (leu (cc0)
5624 (label_ref (match_operand 0 "" ""))
5629 return \"jbls %l0\";
5635 ;; Negated conditional jump instructions.
5639 (if_then_else (eq (cc0)
5642 (label_ref (match_operand 0 "" ""))))]
5647 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
5649 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
5655 (if_then_else (ne (cc0)
5658 (label_ref (match_operand 0 "" ""))))]
5663 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
5665 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
5671 (if_then_else (gt (cc0)
5674 (label_ref (match_operand 0 "" ""))))]
5678 OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0);
5680 OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0);
5686 (if_then_else (gtu (cc0)
5689 (label_ref (match_operand 0 "" ""))))]
5693 return \"jbls %l0\";
5701 (if_then_else (lt (cc0)
5704 (label_ref (match_operand 0 "" ""))))]
5708 OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\");
5710 OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\");
5716 (if_then_else (ltu (cc0)
5719 (label_ref (match_operand 0 "" ""))))]
5723 return \"jbcc %l0\";
5731 (if_then_else (ge (cc0)
5734 (label_ref (match_operand 0 "" ""))))]
5738 OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\");
5740 OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\");
5746 (if_then_else (geu (cc0)
5749 (label_ref (match_operand 0 "" ""))))]
5753 return \"jbcs %l0\";
5761 (if_then_else (le (cc0)
5764 (label_ref (match_operand 0 "" ""))))]
5768 OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0);
5770 OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0);
5776 (if_then_else (leu (cc0)
5779 (label_ref (match_operand 0 "" ""))))]
5783 return \"jbhi %l0\";
5789 ;; Unconditional and other jump instructions
5792 (label_ref (match_operand 0 "" "")))]
5796 return \"jbra %l0\";
5802 ;; We support two different ways of handling dispatch tables.
5803 ;; The NeXT uses absolute tables, and other machines use relative.
5804 ;; This define_expand can generate either kind.
5805 (define_expand "tablejump"
5806 [(parallel [(set (pc) (match_operand 0 "" ""))
5807 (use (label_ref (match_operand 1 "" "")))])]
5811 #ifdef CASE_VECTOR_PC_RELATIVE
5812 operands[0] = gen_rtx (PLUS, SImode, pc_rtx,
5813 gen_rtx (SIGN_EXTEND, SImode, operands[0]));
5817 ;; Jump to variable address from dispatch table of absolute addresses.
5819 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
5820 (use (label_ref (match_operand 1 "" "")))]
5824 return \"jmp (%0)\";
5830 ;; Jump to variable address from dispatch table of relative addresses.
5834 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
5835 (use (label_ref (match_operand 1 "" "")))]
5838 #ifdef ASM_RETURN_CASE_JUMP
5839 ASM_RETURN_CASE_JUMP;
5842 #ifdef ASM_OUTPUT_CASE_LABEL
5843 return \"jmp 6(%%pc,%0.w)\";
5846 return \"jmp 2(pc,%0.w)\";
5848 return \"jmp 2(%%pc,%0.w)\";
5849 #endif /* end !CRDS */
5853 return \"jmp (2,pc,%0.w)\";
5855 return \"jmp pc@(2,%0:w)\";
5861 ;; Decrement-and-branch insns.
5865 (ne (match_operand:HI 0 "general_operand" "+d*g")
5867 (label_ref (match_operand 1 "" ""))
5870 (plus:HI (match_dup 0)
5876 if (DATA_REG_P (operands[0]))
5877 return \"dbra %0,%l1\";
5878 if (GET_CODE (operands[0]) == MEM)
5882 return \"sub%.w %#1,%0\;jbcc %l1\";
5884 return \"subq%.w %#1,%0\;jbcc %l1\";
5886 #else /* not MOTOROLA */
5887 return \"subqw %#1,%0\;jcc %l1\";
5891 #ifdef SGS_CMP_ORDER
5893 return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
5895 return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
5897 #else /* not SGS_CMP_ORDER */
5898 return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
5900 #else /* not MOTOROLA */
5901 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
5908 (ne (match_operand:SI 0 "general_operand" "+d*g")
5910 (label_ref (match_operand 1 "" ""))
5913 (plus:SI (match_dup 0)
5921 if (DATA_REG_P (operands[0]))
5922 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
5923 if (GET_CODE (operands[0]) == MEM)
5924 return \"sub%.l %#1,%0\;jbcc %l1\";
5926 if (DATA_REG_P (operands[0]))
5927 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
5928 if (GET_CODE (operands[0]) == MEM)
5929 return \"subq%.l %#1,%0\;jbcc %l1\";
5930 #endif /* NO_ADDSUB_Q */
5931 #ifdef SGS_CMP_ORDER
5933 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
5935 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
5937 #else /* not SGS_CMP_ORDER */
5938 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
5939 #endif /* not SGS_CMP_ORDER */
5940 #else /* not MOTOROLA */
5941 if (DATA_REG_P (operands[0]))
5942 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
5943 if (GET_CODE (operands[0]) == MEM)
5944 return \"subql %#1,%0\;jcc %l1\";
5945 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
5946 #endif /* not MOTOROLA */
5949 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
5954 (ge (plus:HI (match_operand:HI 0 "general_operand" "+d*am")
5957 (label_ref (match_operand 1 "" ""))
5960 (plus:HI (match_dup 0)
5962 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
5968 if (DATA_REG_P (operands[0]))
5969 return \"dbra %0,%l1\";
5970 if (GET_CODE (operands[0]) == MEM)
5971 return \"sub%.w %#1,%0\;jbcc %l1\";
5973 if (DATA_REG_P (operands[0]))
5974 return \"dbra %0,%l1\";
5975 if (GET_CODE (operands[0]) == MEM)
5976 return \"subq%.w %#1,%0\;jbcc %l1\";
5978 #ifdef SGS_CMP_ORDER
5980 return \"sub.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
5982 return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
5984 #else /* not SGS_CMP_ORDER */
5985 return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\";
5986 #endif /* not SGS_CMP_ORDER */
5987 #else /* not MOTOROLA */
5988 if (DATA_REG_P (operands[0]))
5989 return \"dbra %0,%l1\";
5990 if (GET_CODE (operands[0]) == MEM)
5991 return \"subqw %#1,%0\;jcc %l1\";
5992 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
5993 #endif /* not MOTOROLA */
5996 (define_expand "decrement_and_branch_until_zero"
5997 [(parallel [(set (pc)
5999 (ge (plus:SI (match_operand:SI 0 "general_operand" "")
6002 (label_ref (match_operand 1 "" ""))
6005 (plus:SI (match_dup 0)
6013 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
6016 (label_ref (match_operand 1 "" ""))
6019 (plus:SI (match_dup 0)
6021 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6027 if (DATA_REG_P (operands[0]))
6028 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6029 if (GET_CODE (operands[0]) == MEM)
6030 return \"sub%.l %#1,%0\;jbcc %l1\";
6032 if (DATA_REG_P (operands[0]))
6033 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6034 if (GET_CODE (operands[0]) == MEM)
6035 return \"subq%.l %#1,%0\;jbcc %l1\";
6037 #ifdef SGS_CMP_ORDER
6039 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6041 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6043 #else /* not SGS_CMP_ORDER */
6044 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6045 #endif /* not SGS_CMP_ORDER */
6046 #else /* not MOTOROLA */
6047 if (DATA_REG_P (operands[0]))
6048 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6049 if (GET_CODE (operands[0]) == MEM)
6050 return \"subql %#1,%0\;jcc %l1\";
6051 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6052 #endif /* not MOTOROLA */
6056 ;; For PIC calls, in order to be able to support
6057 ;; dynamic linker LAZY BINDING, all the procedure calls need to go
6058 ;; through the PLT (Procedure Linkage Table) section in PIC mode.
6060 ;; PIC calls are handled by loading the address of the function into a
6061 ;; register (via movsi), then emitting a register indirect call using
6062 ;; the "jsr" function call syntax.
6064 ;; When outputting MIT syntax (e.g. on Suns), we add a bogus extra
6065 ;; operand to the jbsr statement to indicate that this call should
6066 ;; go through the PLT (why? because this is the way that Sun does it).
6068 ;; We have different patterns for PIC calls and non-PIC calls. The
6069 ;; different patterns are only used to choose the right syntax.
6071 ;; The svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it
6072 ;; will create the correct relocation entry (R_68K_PLT32) for `FUNC',
6073 ;; that tells the linker editor to create an entry for `FUNC' in PLT
6074 ;; section at link time. However, all global objects reference are still
6075 ;; done by using `OBJ@GOT'. So, the goal here is to output the function
6076 ;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'.
6077 ;; We need to have a way to differentiate these two different operands.
6079 ;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate
6080 ;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs
6081 ;; to be changed to recognize function calls symbol_ref operand as a valid
6082 ;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will
6083 ;; avoid the compiler to load this symbol_ref operand into a register.
6084 ;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly
6085 ;; since the value is a PC relative offset, not a real address.
6087 ;; All global objects are treated in the similar way as in SUN3. The only
6088 ;; difference is: on m68k svr4, the reference of such global object needs
6089 ;; to end with a suffix "@GOT" so the assembler and linker know to create
6090 ;; an entry for it in GOT (Global Offset Table) section. This is done in
6093 ;; Call subroutine with no return value.
6094 (define_expand "call"
6095 [(call (match_operand:QI 0 "memory_operand" "")
6096 (match_operand:SI 1 "general_operand" ""))]
6097 ;; Operand 1 not really used on the m68000.
6102 if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6103 SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
6106 ;; This is a normal call sequence.
6108 [(call (match_operand:QI 0 "memory_operand" "o")
6109 (match_operand:SI 1 "general_operand" "g"))]
6110 ;; Operand 1 not really used on the m68000.
6114 #if defined (MOTOROLA) && !defined (USE_GAS)
6116 if (GET_CODE (operands[0]) == MEM
6117 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6126 ;; This is a PIC call sequence.
6128 [(call (match_operand:QI 0 "memory_operand" "o")
6129 (match_operand:SI 1 "general_operand" "g"))]
6130 ;; Operand 1 not really used on the m68000.
6134 if (GET_CODE (operands[0]) == MEM
6135 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6138 return \"bsr.l %0\";
6141 return \"bsr.l %0@PLTPC\";
6143 return \"bsr %0@PLTPC\";
6147 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC,
6148 GAS just plain ignores it. */
6149 return \"jbsr %0,a1\";
6154 ;; Call subroutine, returning value in operand 0
6155 ;; (which must be a hard register).
6156 ;; See comments before "call" regarding PIC calls.
6157 (define_expand "call_value"
6158 [(set (match_operand 0 "" "")
6159 (call (match_operand:QI 1 "memory_operand" "")
6160 (match_operand:SI 2 "general_operand" "")))]
6161 ;; Operand 2 not really used on the m68000.
6165 if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6166 SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
6169 ;; This is a normal call_value
6171 [(set (match_operand 0 "" "=rf")
6172 (call (match_operand:QI 1 "memory_operand" "o")
6173 (match_operand:SI 2 "general_operand" "g")))]
6174 ;; Operand 2 not really used on the m68000.
6177 #if defined (MOTOROLA) && !defined (USE_GAS)
6179 if (GET_CODE (operands[1]) == MEM
6180 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6189 ;; This is a PIC call_value
6191 [(set (match_operand 0 "" "=rf")
6192 (call (match_operand:QI 1 "memory_operand" "o")
6193 (match_operand:SI 2 "general_operand" "g")))]
6194 ;; Operand 2 not really used on the m68000.
6197 if (GET_CODE (operands[1]) == MEM
6198 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6201 return \"bsr.l %1\";
6204 return \"bsr.l %1@PLTPC\";
6206 return \"bsr %1@PLTPC\";
6210 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC
6211 GAS just plain ignores it. */
6212 return \"jbsr %1,a1\";
6217 ;; Call subroutine returning any type.
6219 (define_expand "untyped_call"
6220 [(parallel [(call (match_operand 0 "" "")
6222 (match_operand 1 "" "")
6223 (match_operand 2 "" "")])]
6224 "NEEDS_UNTYPED_CALL"
6229 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
6231 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6233 rtx set = XVECEXP (operands[2], 0, i);
6234 emit_move_insn (SET_DEST (set), SET_SRC (set));
6237 /* The optimizer does not know that the call sets the function value
6238 registers we stored in the result block. We avoid problems by
6239 claiming that all hard registers are used and clobbered at this
6241 emit_insn (gen_blockage ());
6246 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6247 ;; all of memory. This blocks insns from being moved across this point.
6249 (define_insn "blockage"
6250 [(unspec_volatile [(const_int 0)] 0)]
6259 (define_insn "probe"
6264 operands[0] = gen_rtx (PLUS, SImode, stack_pointer_rtx,
6265 gen_rtx (CONST_INT, VOIDmode, NEED_PROBE));
6266 return \"tstl %a0\";
6269 ;; Used for frameless functions which save no regs and allocate no locals.
6270 (define_insn "return"
6275 if (current_function_pops_args == 0)
6277 operands[0] = gen_rtx (CONST_INT, VOIDmode, current_function_pops_args);
6281 (define_insn "indirect_jump"
6282 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
6286 ;; This should not be used unless the add/sub insns can't be.
6289 [(set (match_operand:SI 0 "general_operand" "=a")
6290 (match_operand:QI 1 "address_operand" "p"))]
6295 /* Recognize an insn that refers to a table of offsets. Such an insn will
6296 need to refer to a label on the insn. So output one. Use the
6297 label-number of the table of offsets to generate this label. This code,
6298 and similar code above, assumes that there will be at most one reference
6300 if (GET_CODE (operands[1]) == PLUS
6301 && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
6302 && GET_CODE (XEXP (operands[1], 0)) != PLUS)
6304 rtx labelref = XEXP (operands[1], 1);
6305 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
6307 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
6308 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6310 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
6311 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6312 #endif /* not SGS */
6313 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
6314 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
6315 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6316 #ifdef SGS_SWITCH_TABLES
6317 /* Set flag saying we need to define the symbol
6318 LD%n (with value L%n-LI%n) at the end of the switch table. */
6319 switch_table_difference_label_flag = 1;
6320 #endif /* SGS_SWITCH_TABLES */
6321 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
6323 #endif /* SGS_NO_LI */
6325 return \"lea %a1,%0\";
6328 ;; This is the first machine-dependent peephole optimization.
6329 ;; It is useful when a floating value is returned from a function call
6330 ;; and then is moved into an FP register.
6331 ;; But it is mainly intended to test the support for these optimizations.
6334 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
6335 (set (match_operand:DF 0 "register_operand" "=f")
6336 (match_operand:DF 1 "register_operand" "ad"))]
6337 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
6341 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
6342 output_asm_insn (\"move%.l %1,%@\", xoperands);
6343 output_asm_insn (\"move%.l %1,%-\", operands);
6344 return \"fmove%.d %+,%0\";
6348 ;; Optimize a stack-adjust followed by a push of an argument.
6349 ;; This is said to happen frequently with -msoft-float
6350 ;; when there are consecutive library calls.
6353 [(set (reg:SI 15) (plus:SI (reg:SI 15)
6354 (match_operand:SI 0 "const_int_operand" "n")))
6355 (set (match_operand:SF 1 "push_operand" "=m")
6356 (match_operand:SF 2 "general_operand" "rmfF"))]
6357 "INTVAL (operands[0]) >= 4
6358 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
6361 if (INTVAL (operands[0]) > 4)
6364 xoperands[0] = stack_pointer_rtx;
6365 xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4);
6367 if (INTVAL (xoperands[1]) <= 8)
6370 output_asm_insn (\"addq%.w %1,%0\", xoperands);
6372 output_asm_insn (\"addq%.l %1,%0\", xoperands);
6374 else if (INTVAL (xoperands[1]) <= 16
6375 && TARGET_68020 && !TARGET_68040 && !TARGET_68060)
6377 xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
6378 INTVAL (xoperands[1]) - 8);
6379 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
6383 if (INTVAL (xoperands[1]) <= 0x7FFF && !TARGET_5200)
6384 output_asm_insn (\"add%.w %1,%0\", xoperands);
6386 output_asm_insn (\"add%.l %1,%0\", xoperands);
6388 if (FP_REG_P (operands[2]))
6389 return \"fmove%.s %2,%@\";
6390 return \"move%.l %2,%@\";
6393 ;; Speed up stack adjust followed by a fullword fixedpoint push.
6396 [(set (reg:SI 15) (plus:SI (reg:SI 15)
6397 (match_operand:SI 0 "const_int_operand" "n")))
6398 (set (match_operand:SI 1 "push_operand" "=m")
6399 (match_operand:SI 2 "general_operand" "g"))]
6400 "INTVAL (operands[0]) >= 4
6401 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
6404 if (INTVAL (operands[0]) > 4)
6407 xoperands[0] = stack_pointer_rtx;
6408 xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4);
6410 if (INTVAL (xoperands[1]) <= 8)
6413 output_asm_insn (\"addq%.w %1,%0\", xoperands);
6415 output_asm_insn (\"addq%.l %1,%0\", xoperands);
6417 else if (INTVAL (xoperands[1]) <= 16
6418 && TARGET_68020 && !TARGET_68040 && !TARGET_68060)
6420 xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
6421 INTVAL (xoperands[1]) - 8);
6422 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
6426 if (INTVAL (xoperands[1]) <= 0x7FFF && !TARGET_5200)
6427 output_asm_insn (\"add%.w %1,%0\", xoperands);
6429 output_asm_insn (\"add%.l %1,%0\", xoperands);
6431 if (operands[2] == const0_rtx)
6432 return \"clr%.l %@\";
6433 return \"move%.l %2,%@\";
6436 ;; Speed up pushing a single byte but leaving four bytes of space.
6439 [(set (mem:QI (pre_dec:SI (reg:SI 15)))
6440 (match_operand:QI 1 "general_operand" "dami"))
6441 (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))]
6442 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
6447 if (GET_CODE (operands[1]) == REG)
6448 return \"move%.l %1,%-\";
6450 xoperands[1] = operands[1];
6452 = gen_rtx (MEM, QImode,
6453 gen_rtx (PLUS, VOIDmode, stack_pointer_rtx,
6454 gen_rtx (CONST_INT, VOIDmode, 3)));
6455 xoperands[3] = stack_pointer_rtx;
6457 output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
6459 output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands);
6464 [(set (match_operand:SI 0 "register_operand" "=d")
6466 (set (strict_low_part (subreg:HI (match_dup 0) 0))
6467 (match_operand:HI 1 "general_operand" "rmn"))]
6468 "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
6471 if (GET_CODE (operands[1]) == CONST_INT)
6473 if (operands[1] == const0_rtx
6474 && (DATA_REG_P (operands[0])
6475 || GET_CODE (operands[0]) == MEM)
6476 /* clr insns on 68000 read before writing.
6477 This isn't so on the 68010, but we have no TARGET_68010. */
6478 && ((TARGET_68020 || TARGET_5200)
6479 || !(GET_CODE (operands[0]) == MEM
6480 && MEM_VOLATILE_P (operands[0]))))
6481 return \"clr%.w %0\";
6483 return \"move%.w %1,%0\";
6491 ;; jCC label ; abnormal loop termination
6492 ;; dbra dN, loop ; normal loop termination
6500 ;; Which moves the jCC condition outside the inner loop for free.
6503 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
6504 [(cc0) (const_int 0)])
6505 (label_ref (match_operand 2 "" ""))
6510 (ge (plus:HI (match_operand:HI 0 "register_operand" "+d")
6513 (label_ref (match_operand 1 "" ""))
6516 (plus:HI (match_dup 0)
6518 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
6522 output_dbcc_and_branch (operands);
6527 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
6528 [(cc0) (const_int 0)])
6529 (label_ref (match_operand 2 "" ""))
6534 (ge (plus:SI (match_operand:SI 0 "register_operand" "+d")
6537 (label_ref (match_operand 1 "" ""))
6540 (plus:SI (match_dup 0)
6542 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
6546 output_dbcc_and_branch (operands);
6551 ;; FPA multiply and add.
6553 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6554 (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%x,dmF,y")
6555 (match_operand:DF 2 "general_operand" "xH,y,y"))
6556 (match_operand:DF 3 "general_operand" "xH,y,dmF")))]
6559 fpma%.d %1,%w2,%w3,%0
6560 fpma%.d %x1,%x2,%x3,%0
6561 fpma%.d %x1,%x2,%x3,%0")
6564 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6565 (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%x,ydmF,y")
6566 (match_operand:SF 2 "general_operand" "xH,y,ydmF"))
6567 (match_operand:SF 3 "general_operand" "xH,ydmF,ydmF")))]
6570 fpma%.s %1,%w2,%w3,%0
6572 fpma%.s %1,%2,%3,%0")
6574 ;; FPA Multiply and subtract
6576 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6577 (minus:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
6578 (mult:DF (match_operand:DF 2 "general_operand" "%xH,y,y")
6579 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
6582 fpms%.d %3,%w2,%w1,%0
6583 fpms%.d %x3,%2,%x1,%0
6584 fpms%.d %x3,%2,%x1,%0")
6587 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6588 (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
6589 (mult:SF (match_operand:SF 2 "general_operand" "%xH,rmF,y")
6590 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
6593 fpms%.s %3,%w2,%w1,%0
6595 fpms%.s %3,%2,%1,%0")
6598 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6599 (minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
6600 (match_operand:DF 2 "general_operand" "x,y,rmF"))
6601 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
6604 fpmr%.d %2,%w1,%w3,%0
6605 fpmr%.d %x2,%1,%x3,%0
6606 fpmr%.d %x2,%1,%x3,%0")
6609 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6610 (minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
6611 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
6612 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
6615 fpmr%.s %2,%w1,%w3,%0
6616 fpmr%.s %x2,%1,%x3,%0
6617 fpmr%.s %x2,%1,%x3,%0")
6619 ;; FPA Add and multiply
6621 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6622 (mult:DF (plus:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
6623 (match_operand:DF 2 "general_operand" "x,y,rmF"))
6624 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
6627 fpam%.d %2,%w1,%w3,%0
6628 fpam%.d %x2,%1,%x3,%0
6629 fpam%.d %x2,%1,%x3,%0")
6632 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6633 (mult:SF (plus:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
6634 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
6635 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
6638 fpam%.s %2,%w1,%w3,%0
6639 fpam%.s %x2,%1,%x3,%0
6640 fpam%.s %x2,%1,%x3,%0")
6642 ;;FPA Subtract and multiply
6644 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6645 (mult:DF (minus:DF (match_operand:DF 1 "general_operand" "xH,y,y")
6646 (match_operand:DF 2 "general_operand" "x,y,rmF"))
6647 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
6650 fpsm%.d %2,%w1,%w3,%0
6651 fpsm%.d %x2,%1,%x3,%0
6652 fpsm%.d %x2,%1,%x3,%0")
6655 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6656 (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
6657 (minus:DF (match_operand:DF 2 "general_operand" "xH,y,y")
6658 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
6661 fpsm%.d %3,%w2,%w1,%0
6662 fpsm%.d %x3,%2,%x1,%0
6663 fpsm%.d %x3,%2,%x1,%0")
6666 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6667 (mult:SF (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,y")
6668 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
6669 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
6672 fpsm%.s %2,%w1,%w3,%0
6673 fpsm%.s %x2,%1,%x3,%0
6674 fpsm%.s %x2,%1,%x3,%0")
6677 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6678 (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
6679 (minus:SF (match_operand:SF 2 "general_operand" "xH,rmF,y")
6680 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
6683 fpsm%.s %3,%w2,%w1,%0
6684 fpsm%.s %x3,%2,%x1,%0
6685 fpsm%.s %x3,%2,%x1,%0")
6687 (define_insn "tstxf"
6689 (match_operand:XF 0 "nonimmediate_operand" "fm"))]
6693 cc_status.flags = CC_IN_68881;
6694 return \"ftst%.x %0\";
6697 (define_insn "cmpxf"
6699 (compare (match_operand:XF 0 "nonimmediate_operand" "f,m")
6700 (match_operand:XF 1 "nonimmediate_operand" "fm,f")))]
6704 cc_status.flags = CC_IN_68881;
6705 #ifdef SGS_CMP_ORDER
6706 if (REG_P (operands[0]))
6708 if (REG_P (operands[1]))
6709 return \"fcmp%.x %0,%1\";
6711 return \"fcmp%.x %0,%f1\";
6713 cc_status.flags |= CC_REVERSED;
6714 return \"fcmp%.x %1,%f0\";
6716 if (REG_P (operands[0]))
6718 if (REG_P (operands[1]))
6719 return \"fcmp%.x %1,%0\";
6721 return \"fcmp%.x %f1,%0\";
6723 cc_status.flags |= CC_REVERSED;
6724 return \"fcmp%.x %f0,%1\";
6728 (define_insn "extendsfxf2"
6729 [(set (match_operand:XF 0 "general_operand" "=fm,f")
6730 (float_extend:XF (match_operand:SF 1 "general_operand" "f,m")))]
6734 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
6736 if (REGNO (operands[0]) == REGNO (operands[1]))
6738 /* Extending float to double in an fp-reg is a no-op.
6739 NOTICE_UPDATE_CC has already assumed that the
6740 cc will be set. So cancel what it did. */
6741 cc_status = cc_prev_status;
6744 return \"f%$move%.x %1,%0\";
6746 if (FP_REG_P (operands[0]))
6747 return \"f%$move%.s %f1,%0\";
6748 return \"fmove%.x %f1,%0\";
6752 (define_insn "extenddfxf2"
6753 [(set (match_operand:XF 0 "general_operand" "=fm,f")
6755 (match_operand:DF 1 "general_operand" "f,m")))]
6759 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
6761 if (REGNO (operands[0]) == REGNO (operands[1]))
6763 /* Extending float to double in an fp-reg is a no-op.
6764 NOTICE_UPDATE_CC has already assumed that the
6765 cc will be set. So cancel what it did. */
6766 cc_status = cc_prev_status;
6769 return \"fmove%.x %1,%0\";
6771 if (FP_REG_P (operands[0]))
6772 return \"f%&move%.d %f1,%0\";
6773 return \"fmove%.x %f1,%0\";
6776 (define_insn "truncxfdf2"
6777 [(set (match_operand:DF 0 "general_operand" "=m,!r")
6779 (match_operand:XF 1 "general_operand" "f,f")))]
6783 if (REG_P (operands[0]))
6785 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
6786 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
6787 return \"move%.l %+,%0\";
6789 return \"fmove%.d %f1,%0\";
6792 (define_insn "truncxfsf2"
6793 [(set (match_operand:SF 0 "general_operand" "=dm")
6795 (match_operand:XF 1 "general_operand" "f")))]
6799 (define_insn "floatsixf2"
6800 [(set (match_operand:XF 0 "general_operand" "=f")
6801 (float:XF (match_operand:SI 1 "general_operand" "dmi")))]
6805 (define_insn "floathixf2"
6806 [(set (match_operand:XF 0 "general_operand" "=f")
6807 (float:XF (match_operand:HI 1 "general_operand" "dmn")))]
6811 (define_insn "floatqixf2"
6812 [(set (match_operand:XF 0 "general_operand" "=f")
6813 (float:XF (match_operand:QI 1 "general_operand" "dmn")))]
6817 (define_insn "ftruncxf2"
6818 [(set (match_operand:XF 0 "general_operand" "=f")
6819 (fix:XF (match_operand:XF 1 "general_operand" "fFm")))]
6823 if (FP_REG_P (operands[1]))
6824 return \"fintrz%.x %f1,%0\";
6825 return \"fintrz%.x %f1,%0\";
6828 (define_insn "fixxfqi2"
6829 [(set (match_operand:QI 0 "general_operand" "=dm")
6830 (fix:QI (match_operand:XF 1 "general_operand" "f")))]
6834 (define_insn "fixxfhi2"
6835 [(set (match_operand:HI 0 "general_operand" "=dm")
6836 (fix:HI (match_operand:XF 1 "general_operand" "f")))]
6840 (define_insn "fixxfsi2"
6841 [(set (match_operand:SI 0 "general_operand" "=dm")
6842 (fix:SI (match_operand:XF 1 "general_operand" "f")))]
6847 [(set (match_operand:XF 0 "general_operand" "=f")
6848 (plus:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
6849 (match_operand:XF 1 "nonimmediate_operand" "0")))]
6854 [(set (match_operand:XF 0 "general_operand" "=f")
6855 (plus:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
6856 (match_operand:XF 1 "nonimmediate_operand" "0")))]
6861 [(set (match_operand:XF 0 "general_operand" "=f")
6862 (plus:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
6863 (match_operand:XF 1 "general_operand" "0")))]
6867 (define_insn "addxf3"
6868 [(set (match_operand:XF 0 "general_operand" "=f")
6869 (plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
6870 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
6874 if (REG_P (operands[2]))
6875 return \"fadd%.x %2,%0\";
6876 return \"fadd%.x %f2,%0\";
6880 [(set (match_operand:XF 0 "general_operand" "=f")
6881 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
6882 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
6887 [(set (match_operand:XF 0 "general_operand" "=f")
6888 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
6889 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
6894 [(set (match_operand:XF 0 "general_operand" "=f")
6895 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
6896 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
6900 (define_insn "subxf3"
6901 [(set (match_operand:XF 0 "general_operand" "=f")
6902 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
6903 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
6907 if (REG_P (operands[2]))
6908 return \"fsub%.x %2,%0\";
6909 return \"fsub%.x %f2,%0\";
6913 [(set (match_operand:XF 0 "general_operand" "=f")
6914 (mult:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
6915 (match_operand:XF 1 "nonimmediate_operand" "0")))]
6920 [(set (match_operand:XF 0 "general_operand" "=f")
6921 (mult:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
6922 (match_operand:XF 1 "nonimmediate_operand" "0")))]
6927 [(set (match_operand:XF 0 "general_operand" "=f")
6928 (mult:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
6929 (match_operand:XF 1 "nonimmediate_operand" "0")))]
6933 (define_insn "mulxf3"
6934 [(set (match_operand:XF 0 "general_operand" "=f")
6935 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
6936 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
6940 if (REG_P (operands[2]))
6941 return \"fmul%.x %2,%0\";
6942 return \"fmul%.x %f2,%0\";
6946 [(set (match_operand:XF 0 "general_operand" "=f")
6947 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
6948 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
6953 [(set (match_operand:XF 0 "general_operand" "=f")
6954 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
6955 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
6960 [(set (match_operand:XF 0 "general_operand" "=f")
6961 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
6962 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
6966 (define_insn "divxf3"
6967 [(set (match_operand:XF 0 "general_operand" "=f")
6968 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
6969 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
6973 if (REG_P (operands[2]))
6974 return \"fdiv%.x %2,%0\";
6975 return \"fdiv%.x %f2,%0\";
6978 (define_expand "negxf2"
6979 [(set (match_operand:XF 0 "general_operand" "")
6980 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
6984 /* ??? There isn't an FPA define_insn so we could handle it here too.
6985 For now we don't (paranoia). */
6993 target = operand_subword (operands[0], 0, 1, XFmode);
6994 result = expand_binop (SImode, xor_optab,
6995 operand_subword_force (operands[1], 0, XFmode),
6996 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
7000 if (result != target)
7001 emit_move_insn (result, target);
7003 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7004 operand_subword_force (operands[1], 1, XFmode));
7005 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7006 operand_subword_force (operands[1], 2, XFmode));
7008 insns = get_insns ();
7011 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7016 (define_insn "negxf2_68881"
7017 [(set (match_operand:XF 0 "general_operand" "=f")
7018 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7022 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7023 return \"fneg%.x %1,%0\";
7024 return \"fneg%.x %f1,%0\";
7027 (define_expand "absxf2"
7028 [(set (match_operand:XF 0 "general_operand" "")
7029 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7033 /* ??? There isn't an FPA define_insn so we could handle it here too.
7034 For now we don't (paranoia). */
7042 target = operand_subword (operands[0], 0, 1, XFmode);
7043 result = expand_binop (SImode, and_optab,
7044 operand_subword_force (operands[1], 0, XFmode),
7045 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
7049 if (result != target)
7050 emit_move_insn (result, target);
7052 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7053 operand_subword_force (operands[1], 1, XFmode));
7054 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7055 operand_subword_force (operands[1], 2, XFmode));
7057 insns = get_insns ();
7060 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7065 (define_insn "absxf2_68881"
7066 [(set (match_operand:XF 0 "general_operand" "=f")
7067 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7071 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7072 return \"fabs%.x %1,%0\";
7073 return \"fabs%.x %f1,%0\";
7076 (define_insn "sqrtxf2"
7077 [(set (match_operand:XF 0 "general_operand" "=f")
7078 (sqrt:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7082 (define_insn "sinsf2"
7083 [(set (match_operand:SF 0 "general_operand" "=f")
7084 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 1))]
7085 "TARGET_68881 && flag_fast_math"
7088 if (FP_REG_P (operands[1]))
7089 return \"fsin%.x %1,%0\";
7091 return \"fsin%.s %1,%0\";
7094 (define_insn "sindf2"
7095 [(set (match_operand:DF 0 "general_operand" "=f")
7096 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 1))]
7097 "TARGET_68881 && flag_fast_math"
7100 if (FP_REG_P (operands[1]))
7101 return \"fsin%.x %1,%0\";
7103 return \"fsin%.d %1,%0\";
7106 (define_insn "sinxf2"
7107 [(set (match_operand:XF 0 "general_operand" "=f")
7108 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 1))]
7109 "TARGET_68881 && flag_fast_math"
7112 (define_insn "cossf2"
7113 [(set (match_operand:SF 0 "general_operand" "=f")
7114 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 2))]
7115 "TARGET_68881 && flag_fast_math"
7118 if (FP_REG_P (operands[1]))
7119 return \"fcos%.x %1,%0\";
7121 return \"fcos%.s %1,%0\";
7124 (define_insn "cosdf2"
7125 [(set (match_operand:DF 0 "general_operand" "=f")
7126 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 2))]
7127 "TARGET_68881 && flag_fast_math"
7130 if (FP_REG_P (operands[1]))
7131 return \"fcos%.x %1,%0\";
7133 return \"fcos%.d %1,%0\";
7136 (define_insn "cosxf2"
7137 [(set (match_operand:XF 0 "general_operand" "=f")
7138 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 2))]
7139 "TARGET_68881 && flag_fast_math"