1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 88, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
4 ;; This file is part of GNU CC.
6 ;; GNU CC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GNU CC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GNU CC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
19 ;; Boston, MA 02111-1307, USA.
21 ;;- Information about MCF5200 port.
23 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
24 ;;- 68k ISA. Differences include reduced support for byte and word
25 ;;- operands and the removal of BCD, bitfield, rotate, and integer
26 ;;- divide instructions. The TARGET_5200 flag turns the use of the
27 ;;- removed opcodes and addressing modes off.
31 ;;- instruction definitions
33 ;;- @@The original PO technology requires these to be ordered by speed,
34 ;;- @@ so that assigner will pick the fastest.
36 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
38 ;;- When naming insn's (operand 0 of define_insn) be careful about using
39 ;;- names from other targets machine descriptions.
41 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
42 ;;- updates for most instructions.
44 ;;- Operand classes for the register allocator:
45 ;;- 'a' one of the address registers can be used.
46 ;;- 'd' one of the data registers can be used.
47 ;;- 'f' one of the m68881 registers can be used
48 ;;- 'r' either a data or an address register can be used.
49 ;;- 'x' if one of the Sun FPA registers
50 ;;- 'y' if one of the Low Sun FPA registers (fpa0-fpa15).
52 ;;- Immediate Floating point operator constraints
53 ;;- 'G' a floating point constant that is *NOT* one of the standard
54 ;; 68881 constant values (to force calling output_move_const_double
55 ;; to get it from rom if it is a 68881 constant).
56 ;;- 'H' one of the standard FPA constant values
58 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
61 ;;- Immediate integer operand constraints:
63 ;;- 'J' -32768 .. 32767
64 ;;- 'K' all integers EXCEPT -128 .. 127
66 ;;- 'M' all integers EXCEPT -256 .. 255
72 ;;- "%." size separator ("." or "") move%.l d0,d1
73 ;;- "%#" immediate separator ("#" or "") move%.l %#0,d0
74 ;;- "%-" push operand "sp@-" move%.l d0,%-
75 ;;- "%+" pop operand "sp@+" move%.l d0,%+
76 ;;- "%@" top of stack "sp@" move%.l d0,%@
77 ;;- "%!" fpcr register
78 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
79 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
82 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
83 ;; operand 1 is the argument for `sin'.
84 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
85 ;; operand 1 is the argument for `cos'.
87 ;;- Information about 68040 port.
89 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
90 ;;- be emulated in software by the OS. It is faster to avoid these
91 ;;- instructions and issue a library call rather than trapping into
92 ;;- the kernel. The affected instructions are fintrz and fscale. The
93 ;;- TARGET_68040 flag turns the use of the opcodes off.
95 ;;- The '040 also implements a set of new floating-point instructions
96 ;;- which specify the rounding precision in the opcode. This finally
97 ;;- permit the 68k series to be truly IEEE compliant, and solves all
98 ;;- issues of excess precision accumulating in the extended registers.
99 ;;- By default, GCC does not use these instructions, since such code will
100 ;;- not run on an '030. To use these instructions, use the -m68040-only
101 ;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY,
102 ;;- you can make these instructions the default.
104 ;;- These new instructions aren't directly in the md. They are brought
105 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
108 ;;- Information about 68060 port.
110 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
111 ;;- be emulated in software by the OS. It is faster to avoid these
112 ;;- instructions and issue a library call rather than trapping into
113 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
114 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
115 ;;- fscale. The TARGET_68060 flag turns the use of the opcodes off.
117 ;;- FPA port explanation:
119 ;;- Usage of the Sun FPA and the 68881 together
121 ;;- The current port of gcc to the sun fpa disallows use of the m68881
122 ;;- instructions completely if code is targeted for the fpa. This is
123 ;;- for the following reasons:
125 ;;- 1) Expressing the preference hierarchy (ie. use the fpa if you
126 ;;- can, the 68881 otherwise, and data registers only if you are
127 ;;- forced to it) is a bitch with the current constraint scheme,
128 ;;- especially since it would have to work for any combination of
131 ;;- 2) There are no instructions to move between the two types of
132 ;;- registers; the stack must be used as an intermediary.
134 ;;- It could indeed be done; I think the best way would be to have
135 ;;- separate patterns for TARGET_FPA (which implies a 68881),
136 ;;- TARGET_68881, and no floating point co-processor. Use
137 ;;- define_expands for all of the named instruction patterns, and
138 ;;- include code in the FPA instruction to deal with the 68881 with
139 ;;- preferences specifically set to favor the fpa. Some of this has
140 ;;- already been done:
142 ;;- 1) Separation of most of the patterns out into a TARGET_FPA
143 ;;- case and a TARGET_68881 case (the exceptions are the patterns
144 ;;- which would need one define_expand and three define_insn's under
145 ;;- it (with a lot of duplicate code between them) to replace the
146 ;;- current single define_insn. These are mov{[ds]f,[ds]i} and the
147 ;;- first two patterns in the md.
149 ;;- Some would still have to be done:
151 ;;- 1) Add code to the fpa patterns which correspond to 68881
152 ;;- patterns to deal with the 68881 case (including preferences!).
153 ;;- What you might actually do here is combine the fpa and 68881 code
154 ;;- back together into one pattern for those instructions where it's
155 ;;- absolutely necessary and save yourself some duplicate code. I'm
156 ;;- not completely sure as to whether you could get away with doing
157 ;;- this only for the mov* insns, or if you'd have to do it for all
159 ;;- 2) Add code to the mov{[ds]f,[ds]i} instructions to handle
160 ;;- moving between fpa regs and 68881 regs.
162 ;;- Since the fpa is more powerful than the 68881 and also has more
163 ;;- registers, and since I think the resultant md would be medium ugly
164 ;;- (lot's of duplicate code, ugly constraint strings), I elected not
165 ;;- to do this change.
167 ;;- Another reason why someone *might* want to do the change is to
168 ;;- control which register classes are accessed in a slightly cleaner
169 ;;- way than I have. See the blurb on CONDITIONAL_REGISTER_USAGE in
170 ;;- the internals manual.
172 ;;- Yet another reason why someone might want to do this change is to
173 ;;- allow use of some of the 68881 insns which have no equivalent on
174 ;;- the fpa. The sqrt instruction comes fairly quickly to mind.
176 ;;- If this is ever done, don't forget to change sun3.h so that
177 ;;- it *will* define __HAVE_68881__ when the FPA is in use.
179 ;;- Condition code hack
181 ;;- When a floating point compare is done in the fpa, the resulting
182 ;;- condition codes are left in the fpastatus register. The values in
183 ;;- this register must be moved into the 68000 cc register before any
184 ;;- jump is executed. Once this has been done, regular jump
185 ;;- instructions are fine (ie. floating point jumps are not necessary.
186 ;;- They are only done if the cc is in the 68881).
188 ;;- The instructions that move the fpastatus register to the 68000
189 ;;- register clobber a data register (the move cannot be done direct).
190 ;;- These instructions might be bundled either with the compare
191 ;;- instruction, or the branch instruction. If we were using both the
192 ;;- fpa and the 68881 together, we would wish to only mark the
193 ;;- register clobbered if we were doing the compare in the fpa, but I
194 ;;- think that that decision (whether to clobber the register or not)
195 ;;- must be done before register allocation (makes sense) and hence we
196 ;;- can't know if the floating point compare will be done in the fpa
197 ;;- or the fp. So whenever we are asked for code that uses the fpa,
198 ;;- we will mark a data register as clobbered. This is reasonable, as
199 ;;- almost all floating point compare operations done with fpa code
200 ;;- enabled will be done in the fpa. It's even more reasonable since
201 ;;- we decided to make the 68881 and the fpa mutually exclusive.
203 ;;- We place to code to move the fpastatus register inside of a
204 ;;- define_expand so that we can do it conditionally based on whether
205 ;;- we are targeting an fpa or not.
207 ;;- This still leaves us with the question of where we wish to put the
208 ;;- code to move the fpastatus reg. If we put it in the compare
209 ;;- instruction, we can restrict the clobbering of the register to
210 ;;- floating point compares, but we can't take advantage of floating
211 ;;- point subtracts & etc. that alter the fpastatus register. If we
212 ;;- put it in the branch instruction, all branches compiled with fpa
213 ;;- code enabled will clobber a data register, but we will be able to
214 ;;- take advantage of fpa subtracts. This balance favors putting the
215 ;;- code in with the compare instruction.
217 ;;- Note that if some enterprising hacker should decide to switch
218 ;;- this, he'll need to modify the code in NOTICE_UPDATE_CC.
220 ;;- Usage of the top 16 fpa registers
222 ;;- The only locations which we may transfer fpa registers 16-31 from
223 ;;- or to are the fpa registers 0-15. (68000 registers and memory
224 ;;- locations are impossible). This causes problems in gcc, which
225 ;;- assumes that mov?? instructions require no additional registers
226 ;;- (see section 11.7) and since floating point moves *must* be
227 ;;- supported into general registers (see section 12.3 under
228 ;;- HARD_REGNO_OK_FOR_MODE_P) from anywhere.
230 ;;- My solution was to reserve fpa0 for moves into or out of these top
231 ;;- 16 registers and to disparage the choice to reload into or out of
232 ;;- these registers as much as I could. That alternative is always
233 ;;- last in the list, so it will not be used unless all else fails. I
234 ;;- will note that according to my current information, sun's compiler
235 ;;- doesn't use these top 16 registers at all.
237 ;;- There is another possible way to do it. I *believe* that if you
238 ;;- make absolutely sure that the code will not be executed in the
239 ;;- reload pass, you can support the mov?? names with define_expands
240 ;;- which require new registers. This may be possible by the
241 ;;- appropriate juggling of constraints. I may come back to this later.
243 ;;- Usage of constant RAM
245 ;;- This has been handled correctly (I believe) but the way I've done
246 ;;- it could use a little explanation. The constant RAM can only be
247 ;;- accessed when the instruction is in "command register" mode.
248 ;;- "command register" mode means that no accessing of memory or the
249 ;;- 68000 registers is being done. This can be expressed easily in
250 ;;- constraints, so generally the mode of the instruction is
251 ;;- determined by a branch off of which_alternative. In outputting
252 ;;- instructions, a 'w' means to output an access to the constant ram
253 ;;- (if the arg is CONST_DOUBLE and is one of the available
254 ;;- constants), and 'x' means to output a register pair (if the arg is
255 ;;- a 68000 register) and a 'y' is the combination of the above two
256 ;;- processes. You use a 'y' in two operand DF instructions where you
257 ;;- *know* the other operand is an fpa register, you use an 'x' in DF
258 ;;- instructions where the arg might be a 68000 register and the
259 ;;- instruction is *not* in "command register" mode, and you use a 'w'
260 ;;- in two situations: 1) The instruction *is* in command register
261 ;;- mode (and hence won't be accessing 68000 registers), or 2) The
262 ;;- instruction is a two operand SF instruction where you know the
263 ;;- other operand is an fpa register.
265 ;;- Optimization issues
267 ;;- I actually think that I've included all of the fpa instructions
268 ;;- that should be included. Note that if someone is interested in
269 ;;- doing serious floating point work on the sun fpa, I would advise
270 ;;- the use of the "asm" instruction in gcc to allow you to use the
271 ;;- sin, cos, and exponential functions on the fpa board.
273 ;;- END FPA Explanation Section.
276 ;;- Some of these insn's are composites of several m68000 op codes.
277 ;;- The assembler (or final @@??) insures that the appropriate one is
281 [(set (match_operand:DF 0 "push_operand" "=m")
282 (match_operand:DF 1 "general_operand" "ro<>fyE"))]
286 if (FP_REG_P (operands[1]))
287 return \"fmove%.d %f1,%0\";
288 if (FPA_REG_P (operands[1]))
289 return \"fpmove%.d %1, %x0\";
290 return output_move_double (operands);
293 (define_insn "pushdi"
294 [(set (match_operand:DI 0 "push_operand" "=m")
295 (match_operand:DI 1 "general_operand" "ro<>Fyi"))]
299 return output_move_double (operands);
302 ;; We don't want to allow a constant operand for test insns because
303 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
304 ;; be folded while optimizing anyway.
306 (define_expand "tstdi"
308 (match_operand:DI 0 "nonimmediate_operand" ""))
309 (clobber (match_scratch:SI 1 ""))
310 (clobber (match_scratch:DI 2 ""))]
312 "m68k_last_compare_had_fp_operands = 0;")
316 (match_operand:DI 0 "nonimmediate_operand" "am,d"))
317 (clobber (match_scratch:SI 1 "=X,d"))
318 (clobber (match_scratch:DI 2 "=d,X"))]
322 if (which_alternative == 0)
326 xoperands[0] = operands[2];
327 xoperands[1] = operands[0];
328 output_move_double (xoperands);
329 cc_status.flags |= CC_REVERSED;
330 return \"neg%.l %R2\;negx%.l %2\";
332 if (find_reg_note (insn, REG_DEAD, operands[0]))
334 cc_status.flags |= CC_REVERSED;
335 return \"neg%.l %R0\;negx%.l %0\";
339 ** 'sub' clears %1, and also clears the X cc bit
340 ** 'tst' sets the Z cc bit according to the low part of the DImode operand
341 ** 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part
343 return \"sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0\";
346 (define_expand "tstsi"
348 (match_operand:SI 0 "nonimmediate_operand" ""))]
350 "m68k_last_compare_had_fp_operands = 0;")
354 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
359 /* ISI's assembler fails to handle tstl a0. */
360 if (! ADDRESS_REG_P (operands[0]))
362 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
364 return \"tst%.l %0\";
365 /* If you think that the 68020 does not support tstl a0,
366 reread page B-167 of the 68020 manual more carefully. */
367 /* On an address reg, cmpw may replace cmpl. */
369 return \"cmp%.w %0,%#0\";
371 return \"cmp%.w %#0,%0\";
375 ;; This can't use an address register, because comparisons
376 ;; with address registers as second operand always test the whole word.
377 (define_expand "tsthi"
379 (match_operand:HI 0 "nonimmediate_operand" ""))]
381 "m68k_last_compare_had_fp_operands = 0;")
385 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
389 (define_expand "tstqi"
391 (match_operand:QI 0 "nonimmediate_operand" ""))]
393 "m68k_last_compare_had_fp_operands = 0;")
397 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
401 (define_expand "tstsf"
403 (match_operand:SF 0 "general_operand" ""))]
404 "TARGET_68881 || TARGET_FPA"
407 m68k_last_compare_had_fp_operands = 1;
410 emit_insn (gen_tstsf_fpa (operands[0]));
415 (define_insn "tstsf_fpa"
417 (match_operand:SF 0 "general_operand" "xmdF"))
418 (clobber (match_scratch:SI 1 "=d"))]
420 "fptst%.s %x0\;fpmove fpastatus,%1\;movw %1,cc")
424 (match_operand:SF 0 "general_operand" "fdm"))]
428 cc_status.flags = CC_IN_68881;
429 if (FP_REG_P (operands[0]))
430 return \"ftst%.x %0\";
431 return \"ftst%.s %0\";
434 (define_expand "tstdf"
436 (match_operand:DF 0 "general_operand" ""))]
437 "TARGET_68881 || TARGET_FPA"
440 m68k_last_compare_had_fp_operands = 1;
443 emit_insn (gen_tstsf_fpa (operands[0]));
448 (define_insn "tstdf_fpa"
450 (match_operand:DF 0 "general_operand" "xrmF"))
451 (clobber (match_scratch:SI 1 "=d"))]
453 "fptst%.d %x0\;fpmove fpastatus,%1\;movw %1,cc")
457 (match_operand:DF 0 "general_operand" "fm"))]
461 cc_status.flags = CC_IN_68881;
462 if (FP_REG_P (operands[0]))
463 return \"ftst%.x %0\";
464 return \"ftst%.d %0\";
467 ;; compare instructions.
469 (define_expand "cmpdi"
472 (compare (match_operand:DI 0 "nonimmediate_operand" "")
473 (match_operand:DI 1 "general_operand" "")))
474 (clobber (match_dup 2))])]
476 "m68k_last_compare_had_fp_operands = 0; operands[2] = gen_reg_rtx (DImode);")
480 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
481 (match_operand:DI 2 "general_operand" "d,0")))
482 (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
486 if (rtx_equal_p (operands[0], operands[1]))
487 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
490 cc_status.flags |= CC_REVERSED;
491 return \"sub%.l %R1,%R0\;subx%.l %1,%0\";
495 ;; This is the second "hook" for PIC code (in addition to movsi). See
496 ;; comment of movsi for a description of PIC handling.
497 (define_expand "cmpsi"
499 (compare (match_operand:SI 0 "nonimmediate_operand" "")
500 (match_operand:SI 1 "general_operand" "")))]
504 m68k_last_compare_had_fp_operands = 0;
505 if (flag_pic && symbolic_operand (operands[1], SImode))
507 /* The source is an address which requires PIC relocation.
508 Call legitimize_pic_address with the source, mode, and a relocation
509 register (a new pseudo, or the final destination if reload_in_progress
510 is set). Then fall through normally */
511 extern rtx legitimize_pic_address();
512 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
513 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
517 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
520 (compare (match_operand:SI 0 "nonimmediate_operand" "rKs,mr,>")
521 (match_operand:SI 1 "general_operand" "mr,rKs,>")))]
525 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
527 return \"cmpm%.l %0,%1\";
529 return \"cmpm%.l %1,%0\";
531 if (REG_P (operands[1])
532 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
533 { cc_status.flags |= CC_REVERSED;
535 return \"cmp%.l %d1,%d0\";
537 return \"cmp%.l %d0,%d1\";
541 return \"cmp%.l %d0,%d1\";
543 return \"cmp%.l %d1,%d0\";
549 (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
550 (match_operand:SI 1 "general_operand" "r,mrKs")))]
554 if (REG_P (operands[1])
555 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
556 { cc_status.flags |= CC_REVERSED;
558 return \"cmp%.l %d1,%d0\";
560 return \"cmp%.l %d0,%d1\";
564 return \"cmp%.l %d0,%d1\";
566 return \"cmp%.l %d1,%d0\";
570 (define_expand "cmphi"
572 (compare (match_operand:HI 0 "nonimmediate_operand" "")
573 (match_operand:HI 1 "general_operand" "")))]
575 "m68k_last_compare_had_fp_operands = 0;")
579 (compare (match_operand:HI 0 "nonimmediate_operand" "rnm,d,n,m,>")
580 (match_operand:HI 1 "general_operand" "d,rnm,m,n,>")))]
584 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
586 return \"cmpm%.w %0,%1\";
588 return \"cmpm%.w %1,%0\";
590 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
591 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
592 { cc_status.flags |= CC_REVERSED;
594 return \"cmp%.w %d1,%d0\";
596 return \"cmp%.w %d0,%d1\";
600 return \"cmp%.w %d0,%d1\";
602 return \"cmp%.w %d1,%d0\";
606 (define_expand "cmpqi"
608 (compare (match_operand:QI 0 "nonimmediate_operand" "")
609 (match_operand:QI 1 "general_operand" "")))]
611 "m68k_last_compare_had_fp_operands = 0;")
615 (compare (match_operand:QI 0 "nonimmediate_operand" "dn,md,>")
616 (match_operand:QI 1 "general_operand" "dm,nd,>")))]
620 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
622 return \"cmpm%.b %0,%1\";
624 return \"cmpm%.b %1,%0\";
626 if (REG_P (operands[1])
627 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
628 { cc_status.flags |= CC_REVERSED;
630 return \"cmp%.b %d1,%d0\";
632 return \"cmp%.b %d0,%d1\";
636 return \"cmp%.b %d0,%d1\";
638 return \"cmp%.b %d1,%d0\";
642 (define_expand "cmpdf"
644 (compare (match_operand:DF 0 "general_operand" "")
645 (match_operand:DF 1 "general_operand" "")))]
646 "TARGET_68881 || TARGET_FPA"
649 m68k_last_compare_had_fp_operands = 1;
652 emit_insn (gen_cmpdf_fpa (operands[0], operands[1]));
657 (define_insn "cmpdf_fpa"
659 (compare (match_operand:DF 0 "general_operand" "x,y")
660 (match_operand:DF 1 "general_operand" "xH,rmF")))
661 (clobber (match_scratch:SI 2 "=d,d"))]
663 "fpcmp%.d %y1,%0\;fpmove fpastatus,%2\;movw %2,cc")
667 (compare (match_operand:DF 0 "general_operand" "f,mG")
668 (match_operand:DF 1 "general_operand" "fmG,f")))]
672 cc_status.flags = CC_IN_68881;
674 if (REG_P (operands[0]))
676 if (REG_P (operands[1]))
677 return \"fcmp%.x %0,%1\";
679 return \"fcmp%.d %0,%f1\";
681 cc_status.flags |= CC_REVERSED;
682 return \"fcmp%.d %1,%f0\";
684 if (REG_P (operands[0]))
686 if (REG_P (operands[1]))
687 return \"fcmp%.x %1,%0\";
689 return \"fcmp%.d %f1,%0\";
691 cc_status.flags |= CC_REVERSED;
692 return \"fcmp%.d %f0,%1\";
696 (define_expand "cmpsf"
698 (compare (match_operand:SF 0 "general_operand" "")
699 (match_operand:SF 1 "general_operand" "")))]
700 "TARGET_68881 || TARGET_FPA"
703 m68k_last_compare_had_fp_operands = 1;
706 emit_insn (gen_cmpsf_fpa (operands[0], operands[1]));
711 (define_insn "cmpsf_fpa"
713 (compare (match_operand:SF 0 "general_operand" "x,y")
714 (match_operand:SF 1 "general_operand" "xH,rmF")))
715 (clobber (match_scratch:SI 2 "=d,d"))]
717 "fpcmp%.s %w1,%x0\;fpmove fpastatus,%2\;movw %2,cc")
721 (compare (match_operand:SF 0 "general_operand" "f,mdG")
722 (match_operand:SF 1 "general_operand" "fmdG,f")))]
726 cc_status.flags = CC_IN_68881;
728 if (FP_REG_P (operands[0]))
730 if (FP_REG_P (operands[1]))
731 return \"fcmp%.x %0,%1\";
733 return \"fcmp%.s %0,%f1\";
735 cc_status.flags |= CC_REVERSED;
736 return \"fcmp%.s %1,%f0\";
738 if (FP_REG_P (operands[0]))
740 if (FP_REG_P (operands[1]))
741 return \"fcmp%.x %1,%0\";
743 return \"fcmp%.s %f1,%0\";
745 cc_status.flags |= CC_REVERSED;
746 return \"fcmp%.s %f0,%1\";
750 ;; Recognizers for btst instructions.
753 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
755 (minus:SI (const_int 7)
756 (match_operand:SI 1 "general_operand" "di"))))]
758 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
761 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
763 (minus:SI (const_int 31)
764 (match_operand:SI 1 "general_operand" "di"))))]
766 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
768 ;; The following two patterns are like the previous two
769 ;; except that they use the fact that bit-number operands
770 ;; are automatically masked to 3 or 5 bits.
773 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
775 (minus:SI (const_int 7)
777 (match_operand:SI 1 "register_operand" "d")
780 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
783 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
785 (minus:SI (const_int 31)
787 (match_operand:SI 1 "register_operand" "d")
790 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
792 ;; Nonoffsettable mem refs are ok in this one pattern
793 ;; since we don't try to adjust them.
795 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
797 (match_operand:SI 1 "const_int_operand" "n")))]
798 "(unsigned) INTVAL (operands[1]) < 8"
801 operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1]));
802 return output_btst (operands, operands[1], operands[0], insn, 7);
806 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
808 (match_operand:SI 1 "const_int_operand" "n")))]
812 if (GET_CODE (operands[0]) == MEM)
814 operands[0] = adj_offsettable_operand (operands[0],
815 INTVAL (operands[1]) / 8);
816 operands[1] = gen_rtx (CONST_INT, VOIDmode,
817 7 - INTVAL (operands[1]) % 8);
818 return output_btst (operands, operands[1], operands[0], insn, 7);
820 operands[1] = gen_rtx (CONST_INT, VOIDmode,
821 31 - INTVAL (operands[1]));
822 return output_btst (operands, operands[1], operands[0], insn, 31);
828 ;; A special case in which it is not desirable
829 ;; to reload the constant into a data register.
830 (define_insn "pushexthisi_const"
831 [(set (match_operand:SI 0 "push_operand" "=m")
832 (match_operand:SI 1 "const_int_operand" "J"))]
833 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
836 if (operands[1] == const0_rtx)
837 return \"clr%.l %0\";
842 ;(define_insn "swapsi"
843 ; [(set (match_operand:SI 0 "general_operand" "+r")
844 ; (match_operand:SI 1 "general_operand" "+r"))
845 ; (set (match_dup 1) (match_dup 0))]
849 ;; Special case of fullword move when source is zero.
850 ;; The reason this is special is to avoid loading a zero
851 ;; into a data reg with moveq in order to store it elsewhere.
853 (define_insn "movsi_const0"
854 [(set (match_operand:SI 0 "general_operand" "=g")
856 ;; clr insns on 68000 read before writing.
857 ;; This isn't so on the 68010, but we have no TARGET_68010.
858 "((TARGET_68020 || TARGET_5200)
859 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
862 if (ADDRESS_REG_P (operands[0]))
864 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
865 if (!TARGET_68040 && !TARGET_68060)
866 return \"sub%.l %0,%0\";
871 /* Many SGS assemblers croak on size specifiers for constants. */
874 return \"lea 0.w,%0\";
877 return \"lea 0:w,%0\";
881 /* moveq is faster on the 68000. */
882 if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_5200))
883 #if defined(MOTOROLA) && !defined(CRDS)
884 return \"moveq%.l %#0,%0\";
886 return \"moveq %#0,%0\";
888 return \"clr%.l %0\";
891 ;; General case of fullword move.
893 ;; This is the main "hook" for PIC code. When generating
894 ;; PIC, movsi is responsible for determining when the source address
895 ;; needs PIC relocation and appropriately calling legitimize_pic_address
896 ;; to perform the actual relocation.
898 ;; In both the PIC and non-PIC cases the patterns generated will
899 ;; matched by the next define_insn.
900 (define_expand "movsi"
901 [(set (match_operand:SI 0 "general_operand" "")
902 (match_operand:SI 1 "general_operand" ""))]
906 if (flag_pic && symbolic_operand (operands[1], SImode))
908 /* The source is an address which requires PIC relocation.
909 Call legitimize_pic_address with the source, mode, and a relocation
910 register (a new pseudo, or the final destination if reload_in_progress
911 is set). Then fall through normally */
912 extern rtx legitimize_pic_address();
913 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
914 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
918 ;; General case of fullword move. The register constraints
919 ;; force integer constants in range for a moveq to be reloaded
920 ;; if they are headed for memory.
922 ;; Notes: make sure no alternative allows g vs g.
923 ;; We don't allow f-regs since fixed point cannot go in them.
924 ;; We do allow y and x regs since fixed point is allowed in them.
925 [(set (match_operand:SI 0 "general_operand" "=g,da,y,!*x*r*m")
926 (match_operand:SI 1 "general_operand" "daymKs,i,g,*x*r*m"))]
930 if (which_alternative == 3)
931 return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\";
932 if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0]))
933 return \"fpmove%.l %x1,%x0\";
934 return output_move_simode (operands);
938 [(set (match_operand:SI 0 "general_operand" "=r<>,g")
939 (match_operand:SI 1 "general_operand" "g,r<>"))]
941 "* return output_move_simode (operands);")
943 (define_expand "movhi"
944 [(set (match_operand:HI 0 "general_operand" "")
945 (match_operand:HI 1 "general_operand" ""))]
950 [(set (match_operand:HI 0 "general_operand" "=g")
951 (match_operand:HI 1 "general_operand" "g"))]
953 "* return output_move_himode (operands);")
956 [(set (match_operand:HI 0 "general_operand" "=r<>,g")
957 (match_operand:HI 1 "general_operand" "g,r<>"))]
959 "* return output_move_himode (operands);")
961 (define_insn "movstricthi"
962 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
963 (match_operand:HI 1 "general_operand" "rmn"))]
967 if (GET_CODE (operands[1]) == CONST_INT)
969 if (operands[1] == const0_rtx
970 && (DATA_REG_P (operands[0])
971 || GET_CODE (operands[0]) == MEM)
972 /* clr insns on 68000 read before writing.
973 This isn't so on the 68010, but we have no TARGET_68010. */
974 && ((TARGET_68020 || TARGET_5200)
975 || !(GET_CODE (operands[0]) == MEM
976 && MEM_VOLATILE_P (operands[0]))))
977 return \"clr%.w %0\";
979 return \"move%.w %1,%0\";
982 (define_expand "movqi"
983 [(set (match_operand:QI 0 "general_operand" "")
984 (match_operand:QI 1 "general_operand" ""))]
989 [(set (match_operand:QI 0 "general_operand" "=d,*a,m")
990 (match_operand:QI 1 "general_operand" "dmi*a,di*a,dmi"))]
992 "* return output_move_qimode (operands);")
995 [(set (match_operand:QI 0 "general_operand" "=r<>,g")
996 (match_operand:QI 1 "general_operand" "g,r<>"))]
998 "* return output_move_qimode (operands);")
1000 (define_insn "movstrictqi"
1001 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
1002 (match_operand:QI 1 "general_operand" "dmn"))]
1006 if (operands[1] == const0_rtx
1007 /* clr insns on 68000 read before writing.
1008 This isn't so on the 68010, but we have no TARGET_68010. */
1009 && ((TARGET_68020 || TARGET_5200)
1010 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1011 return \"clr%.b %0\";
1012 return \"move%.b %1,%0\";
1015 (define_expand "movsf"
1016 [(set (match_operand:SF 0 "general_operand" "")
1017 (match_operand:SF 1 "general_operand" ""))]
1022 [(set (match_operand:SF 0 "general_operand" "=rmf,x,y,rm,!x,!rm")
1023 (match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))]
1024 ; [(set (match_operand:SF 0 "general_operand" "=rmf")
1025 ; (match_operand:SF 1 "general_operand" "rmfF"))]
1029 if (which_alternative >= 4)
1030 return \"fpmove%.s %1,fpa0\;fpmove%.s fpa0,%0\";
1031 if (FPA_REG_P (operands[0]))
1033 if (FPA_REG_P (operands[1]))
1034 return \"fpmove%.s %x1,%x0\";
1035 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1036 return output_move_const_single (operands);
1037 else if (FP_REG_P (operands[1]))
1038 return \"fmove%.s %1,sp@-\;fpmove%.d sp@+, %0\";
1039 return \"fpmove%.s %x1,%x0\";
1041 if (FPA_REG_P (operands[1]))
1043 if (FP_REG_P (operands[0]))
1044 return \"fpmove%.s %x1,sp@-\;fmove%.s sp@+,%0\";
1046 return \"fpmove%.s %x1,%x0\";
1048 if (FP_REG_P (operands[0]))
1050 if (FP_REG_P (operands[1]))
1051 return \"f%$move%.x %1,%0\";
1052 else if (ADDRESS_REG_P (operands[1]))
1053 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
1054 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1055 return output_move_const_single (operands);
1056 return \"f%$move%.s %f1,%0\";
1058 if (FP_REG_P (operands[1]))
1060 if (ADDRESS_REG_P (operands[0]))
1061 return \"fmove%.s %1,%-\;move%.l %+,%0\";
1062 return \"fmove%.s %f1,%0\";
1064 return \"move%.l %1,%0\";
1068 [(set (match_operand:SF 0 "general_operand" "=r,g")
1069 (match_operand:SF 1 "general_operand" "g,r"))]
1071 "* return \"move%.l %1,%0\";")
1073 (define_expand "movdf"
1074 [(set (match_operand:DF 0 "general_operand" "")
1075 (match_operand:DF 1 "general_operand" ""))]
1080 [(set (match_operand:DF 0 "general_operand" "=rm,rf,rf,&rof<>,y,rm,x,!x,!rm")
1081 (match_operand:DF 1 "general_operand" "rf,m,0,rofE<>,rmE,y,xH,rm,x"))]
1082 ; [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>")
1083 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
1087 if (which_alternative == 7)
1088 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1089 if (FPA_REG_P (operands[0]))
1091 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1092 return output_move_const_double (operands);
1093 if (FP_REG_P (operands[1]))
1094 return \"fmove%.d %1,sp@-\;fpmove%.d sp@+,%x0\";
1095 return \"fpmove%.d %x1,%x0\";
1097 else if (FPA_REG_P (operands[1]))
1099 if (FP_REG_P(operands[0]))
1100 return \"fpmove%.d %x1,sp@-\;fmoved sp@+,%0\";
1102 return \"fpmove%.d %x1,%x0\";
1104 if (FP_REG_P (operands[0]))
1106 if (FP_REG_P (operands[1]))
1107 return \"f%&move%.x %1,%0\";
1108 if (REG_P (operands[1]))
1111 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1112 output_asm_insn (\"move%.l %1,%-\", xoperands);
1113 output_asm_insn (\"move%.l %1,%-\", operands);
1114 return \"f%&move%.d %+,%0\";
1116 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1117 return output_move_const_double (operands);
1118 return \"f%&move%.d %f1,%0\";
1120 else if (FP_REG_P (operands[1]))
1122 if (REG_P (operands[0]))
1124 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1125 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1126 return \"move%.l %+,%0\";
1129 return \"fmove%.d %f1,%0\";
1131 return output_move_double (operands);
1135 [(set (match_operand:DF 0 "general_operand" "=r,g")
1136 (match_operand:DF 1 "general_operand" "g,r"))]
1138 "* return output_move_double (operands);")
1140 (define_expand "movxf"
1141 [(set (match_operand:XF 0 "nonimmediate_operand" "")
1142 (match_operand:XF 1 "general_operand" ""))]
1146 if (CONSTANT_P (operands[1]))
1148 operands[1] = force_const_mem (XFmode, operands[1]);
1149 if (! memory_address_p (XFmode, XEXP (operands[1], 0))
1150 && ! reload_in_progress)
1151 operands[1] = change_address (operands[1], XFmode,
1152 XEXP (operands[1], 0));
1157 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f")
1158 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r"))]
1162 if (FP_REG_P (operands[0]))
1164 if (FP_REG_P (operands[1]))
1165 return \"fmove%.x %1,%0\";
1166 if (REG_P (operands[1]))
1169 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
1170 output_asm_insn (\"move%.l %1,%-\", xoperands);
1171 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1172 output_asm_insn (\"move%.l %1,%-\", xoperands);
1173 output_asm_insn (\"move%.l %1,%-\", operands);
1174 return \"fmove%.x %+,%0\";
1176 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1177 return \"fmove%.x %1,%0\";
1178 return \"fmove%.x %f1,%0\";
1180 if (REG_P (operands[0]))
1182 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1183 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1184 output_asm_insn (\"move%.l %+,%0\", operands);
1185 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1186 return \"move%.l %+,%0\";
1188 return \"fmove%.x %f1,%0\";
1193 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1194 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1198 if (FP_REG_P (operands[0]))
1200 if (FP_REG_P (operands[1]))
1201 return \"fmove%.x %1,%0\";
1202 if (REG_P (operands[1]))
1205 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
1206 output_asm_insn (\"move%.l %1,%-\", xoperands);
1207 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1208 output_asm_insn (\"move%.l %1,%-\", xoperands);
1209 output_asm_insn (\"move%.l %1,%-\", operands);
1210 return \"fmove%.x %+,%0\";
1212 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1213 return \"fmove%.x %1,%0\";
1214 return \"fmove%.x %f1,%0\";
1216 if (FP_REG_P (operands[1]))
1218 if (REG_P (operands[0]))
1220 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1221 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1222 output_asm_insn (\"move%.l %+,%0\", operands);
1223 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1224 return \"move%.l %+,%0\";
1227 return \"fmove%.x %f1,%0\";
1229 return output_move_double (operands);
1233 (define_expand "movdi"
1234 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1235 [(set (match_operand:DI 0 "general_operand" "")
1236 (match_operand:DI 1 "general_operand" ""))]
1240 ;; movdi can apply to fp regs in some cases
1242 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1243 [(set (match_operand:DI 0 "general_operand" "=rm,r,&ro<>,y,rm,!*x,!rm")
1244 (match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))]
1245 ; [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm")
1246 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))]
1247 ; [(set (match_operand:DI 0 "general_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1248 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1252 if (which_alternative == 8)
1253 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1254 if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
1255 return \"fpmove%.d %x1,%x0\";
1256 if (FP_REG_P (operands[0]))
1258 if (FP_REG_P (operands[1]))
1259 return \"fmove%.x %1,%0\";
1260 if (REG_P (operands[1]))
1263 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1264 output_asm_insn (\"move%.l %1,%-\", xoperands);
1265 output_asm_insn (\"move%.l %1,%-\", operands);
1266 return \"fmove%.d %+,%0\";
1268 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1269 return output_move_const_double (operands);
1270 return \"fmove%.d %f1,%0\";
1272 else if (FP_REG_P (operands[1]))
1274 if (REG_P (operands[0]))
1276 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1277 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1278 return \"move%.l %+,%0\";
1281 return \"fmove%.d %f1,%0\";
1283 return output_move_double (operands);
1287 [(set (match_operand:DI 0 "general_operand" "=r,g")
1288 (match_operand:DI 1 "general_operand" "g,r"))]
1290 "* return output_move_double (operands);")
1292 ;; Thus goes after the move instructions
1293 ;; because the move instructions are better (require no spilling)
1294 ;; when they can apply. It goes before the add/sub insns
1295 ;; so we will prefer it to them.
1297 (define_insn "pushasi"
1298 [(set (match_operand:SI 0 "push_operand" "=m")
1299 (match_operand:SI 1 "address_operand" "p"))]
1303 ;; truncation instructions
1304 (define_insn "truncsiqi2"
1305 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1307 (match_operand:SI 1 "general_operand" "doJ,i")))]
1311 if (GET_CODE (operands[0]) == REG)
1313 /* Must clear condition codes, since the move.l bases them on
1314 the entire 32 bits, not just the desired 8 bits. */
1316 return \"move%.l %1,%0\";
1318 if (GET_CODE (operands[1]) == MEM)
1319 operands[1] = adj_offsettable_operand (operands[1], 3);
1320 return \"move%.b %1,%0\";
1323 (define_insn "trunchiqi2"
1324 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1326 (match_operand:HI 1 "general_operand" "doJ,i")))]
1330 if (GET_CODE (operands[0]) == REG
1331 && (GET_CODE (operands[1]) == MEM
1332 || GET_CODE (operands[1]) == CONST_INT))
1334 /* Must clear condition codes, since the move.w bases them on
1335 the entire 16 bits, not just the desired 8 bits. */
1337 return \"move%.w %1,%0\";
1339 if (GET_CODE (operands[0]) == REG)
1341 /* Must clear condition codes, since the move.l bases them on
1342 the entire 32 bits, not just the desired 8 bits. */
1344 return \"move%.l %1,%0\";
1346 if (GET_CODE (operands[1]) == MEM)
1347 operands[1] = adj_offsettable_operand (operands[1], 1);
1348 return \"move%.b %1,%0\";
1351 (define_insn "truncsihi2"
1352 [(set (match_operand:HI 0 "general_operand" "=dm,d")
1354 (match_operand:SI 1 "general_operand" "roJ,i")))]
1358 if (GET_CODE (operands[0]) == REG)
1360 /* Must clear condition codes, since the move.l bases them on
1361 the entire 32 bits, not just the desired 8 bits. */
1363 return \"move%.l %1,%0\";
1365 if (GET_CODE (operands[1]) == MEM)
1366 operands[1] = adj_offsettable_operand (operands[1], 2);
1367 return \"move%.w %1,%0\";
1370 ;; zero extension instructions
1372 ;; this is the canonical form for (lshiftrt:DI x 32)
1373 (define_insn "zero_extendsidi2"
1374 [(set (match_operand:DI 0 "general_operand" "rm")
1375 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
1380 if (GET_CODE (operands[0]) == REG)
1381 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1382 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1383 return \"move%.l %1,%0\;clr%.l %0\";
1384 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1385 return \"clr%.l %0\;move%.l %1,%0\";
1387 operands[2] = adj_offsettable_operand (operands[0], 4);
1388 if (ADDRESS_REG_P (operands[0]))
1389 return \"move%.l %1,%2\;sub%.l %0,%0\";
1391 return \"move%.l %1,%2\;clr%.l %0\";
1394 (define_expand "zero_extendhisi2"
1395 [(set (match_operand:SI 0 "register_operand" "")
1397 (set (strict_low_part (match_dup 2))
1398 (match_operand:HI 1 "general_operand" ""))]
1402 operands[1] = make_safe_from (operands[1], operands[0]);
1403 if (GET_CODE (operands[0]) == SUBREG)
1404 operands[2] = gen_rtx (SUBREG, HImode, SUBREG_REG (operands[0]),
1405 SUBREG_WORD (operands[0]));
1407 operands[2] = gen_rtx (SUBREG, HImode, operands[0], 0);
1410 (define_expand "zero_extendqihi2"
1411 [(set (match_operand:HI 0 "register_operand" "")
1413 (set (strict_low_part (match_dup 2))
1414 (match_operand:QI 1 "general_operand" ""))]
1418 operands[1] = make_safe_from (operands[1], operands[0]);
1419 if (GET_CODE (operands[0]) == SUBREG)
1420 operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]),
1421 SUBREG_WORD (operands[0]));
1423 operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0);
1426 (define_expand "zero_extendqisi2"
1427 [(set (match_operand:SI 0 "register_operand" "")
1429 (set (strict_low_part (match_dup 2))
1430 (match_operand:QI 1 "general_operand" ""))]
1434 operands[1] = make_safe_from (operands[1], operands[0]);
1435 if (GET_CODE (operands[0]) == SUBREG)
1436 operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]),
1437 SUBREG_WORD (operands[0]));
1439 operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0);
1442 ;; Patterns to recognize zero-extend insns produced by the combiner.
1443 ;; We don't allow both operands in memory, because of aliasing problems.
1444 ;; Explicitly disallow two memory operands via the condition since reloading
1445 ;; of this case will result in worse code than the uncombined patterns.
1448 [(set (match_operand:SI 0 "general_operand" "=do<>,d<")
1449 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1450 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1453 if (DATA_REG_P (operands[0]))
1455 if (GET_CODE (operands[1]) == REG
1456 && REGNO (operands[0]) == REGNO (operands[1]))
1457 return \"and%.l %#0xFFFF,%0\";
1458 if (reg_mentioned_p (operands[0], operands[1]))
1459 return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\";
1460 return \"clr%.l %0\;move%.w %1,%0\";
1462 else if (GET_CODE (operands[0]) == MEM
1463 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1464 return \"move%.w %1,%0\;clr%.w %0\";
1465 else if (GET_CODE (operands[0]) == MEM
1466 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1467 return \"clr%.w %0\;move%.w %1,%0\";
1470 output_asm_insn (\"clr%.w %0\", operands);
1471 operands[0] = adj_offsettable_operand (operands[0], 2);
1472 return \"move%.w %1,%0\";
1477 [(set (match_operand:HI 0 "general_operand" "=do<>,d")
1478 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1479 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1482 if (DATA_REG_P (operands[0]))
1484 if (GET_CODE (operands[1]) == REG
1485 && REGNO (operands[0]) == REGNO (operands[1]))
1486 return \"and%.w %#0xFF,%0\";
1487 if (reg_mentioned_p (operands[0], operands[1]))
1488 return \"move%.b %1,%0\;and%.w %#0xFF,%0\";
1489 return \"clr%.w %0\;move%.b %1,%0\";
1491 else if (GET_CODE (operands[0]) == MEM
1492 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1494 if (REGNO (XEXP (XEXP (operands[0], 0), 0))
1495 == STACK_POINTER_REGNUM)
1497 output_asm_insn (\"clr%.w %-\", operands);
1498 operands[0] = gen_rtx (MEM, GET_MODE (operands[0]),
1499 plus_constant (stack_pointer_rtx, 1));
1500 return \"move%.b %1,%0\";
1503 return \"move%.b %1,%0\;clr%.b %0\";
1505 else if (GET_CODE (operands[0]) == MEM
1506 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1507 return \"clr%.b %0\;move%.b %1,%0\";
1510 output_asm_insn (\"clr%.b %0\", operands);
1511 operands[0] = adj_offsettable_operand (operands[0], 1);
1512 return \"move%.b %1,%0\";
1517 [(set (match_operand:SI 0 "general_operand" "=do<>,d")
1518 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1519 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1522 if (DATA_REG_P (operands[0]))
1524 if (GET_CODE (operands[1]) == REG
1525 && REGNO (operands[0]) == REGNO (operands[1]))
1526 return \"and%.l %#0xFF,%0\";
1527 if (reg_mentioned_p (operands[0], operands[1]))
1528 return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
1529 return \"clr%.l %0\;move%.b %1,%0\";
1531 else if (GET_CODE (operands[0]) == MEM
1532 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1534 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1537 return \"clr%.l -(%0)\;move%.b %1,3(%0)\";
1539 return \"clr%.l -(%0)\;move%.b %1,(3,%0)\";
1542 return \"clrl %0@-\;moveb %1,%0@(3)\";
1545 else if (GET_CODE (operands[0]) == MEM
1546 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1548 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1551 return \"clr%.l (%0)+\;move%.b %1,-1(%0)\";
1553 return \"clr%.l (%0)+\;move%.b %1,(-1,%0)\";
1556 return \"clrl %0@+\;moveb %1,%0@(-1)\";
1561 output_asm_insn (\"clr%.l %0\", operands);
1562 operands[0] = adj_offsettable_operand (operands[0], 3);
1563 return \"move%.b %1,%0\";
1567 ;; sign extension instructions
1569 (define_insn "extendqidi2"
1570 [(set (match_operand:DI 0 "general_operand" "=d")
1572 (match_operand:QI 1 "general_operand" "rm")))]
1577 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1578 if (TARGET_68020 || TARGET_5200)
1579 return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
1581 return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
1584 (define_insn "extendhidi2"
1585 [(set (match_operand:DI 0 "general_operand" "=d")
1587 (match_operand:HI 1 "general_operand" "rm")))]
1592 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1593 if (TARGET_68020 || TARGET_5200)
1594 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
1596 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
1599 (define_insn "extendsidi2"
1600 [(set (match_operand:DI 0 "general_operand" "=d")
1602 (match_operand:SI 1 "general_operand" "rm")))]
1607 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1608 if (TARGET_68020 || TARGET_5200)
1609 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
1611 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
1614 ;; Special case when one can avoid register clobbering, copy and test
1615 ;; Maybe there is a way to make that the general case, by forcing the
1616 ;; result of the SI tree to be in the lower register of the DI target
1618 (define_insn "extendplussidi"
1619 [(set (match_operand:DI 0 "register_operand" "=d")
1620 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1621 (match_operand:SI 2 "general_operand" "rmn"))))]
1626 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1627 if (GET_CODE (operands[1]) == CONST_INT
1628 && (unsigned) INTVAL (operands[1]) > 8)
1630 rtx tmp = operands[1];
1632 operands[1] = operands[2];
1635 if (GET_CODE (operands[1]) == REG
1636 && REGNO (operands[1]) == REGNO (operands[3]))
1637 output_asm_insn (\"add%.l %2,%3\", operands);
1639 output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands);
1640 if (TARGET_68020 || TARGET_5200)
1641 return \"smi %0\;extb%.l %0\";
1643 return \"smi %0\;ext%.w %0\;ext%.l %0\";
1646 (define_insn "extendhisi2"
1647 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1649 (match_operand:HI 1 "nonimmediate_operand" "0,rm")))]
1653 if (ADDRESS_REG_P (operands[0]))
1654 return \"move%.w %1,%0\";
1655 return \"ext%.l %0\";
1658 (define_insn "extendqihi2"
1659 [(set (match_operand:HI 0 "general_operand" "=d")
1660 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1664 (define_insn "extendqisi2"
1665 [(set (match_operand:SI 0 "general_operand" "=d")
1666 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1667 "TARGET_68020 || TARGET_5200"
1670 ;; Conversions between float and double.
1672 (define_expand "extendsfdf2"
1673 [(set (match_operand:DF 0 "general_operand" "")
1675 (match_operand:SF 1 "general_operand" "")))]
1676 "TARGET_68881 || TARGET_FPA"
1680 [(set (match_operand:DF 0 "general_operand" "=x,y")
1682 (match_operand:SF 1 "general_operand" "xH,rmF")))]
1687 [(set (match_operand:DF 0 "general_operand" "=*fdm,f")
1689 (match_operand:SF 1 "general_operand" "f,dmF")))]
1693 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1695 if (REGNO (operands[0]) == REGNO (operands[1]))
1697 /* Extending float to double in an fp-reg is a no-op.
1698 NOTICE_UPDATE_CC has already assumed that the
1699 cc will be set. So cancel what it did. */
1700 cc_status = cc_prev_status;
1703 return \"f%&move%.x %1,%0\";
1705 if (FP_REG_P (operands[0]))
1706 return \"f%&move%.s %f1,%0\";
1707 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1709 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1710 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1711 return \"move%.l %+,%0\";
1713 return \"fmove%.d %f1,%0\";
1716 ;; This cannot output into an f-reg because there is no way to be
1717 ;; sure of truncating in that case.
1718 ;; But on the Sun FPA, we can be sure.
1719 (define_expand "truncdfsf2"
1720 [(set (match_operand:SF 0 "general_operand" "")
1722 (match_operand:DF 1 "general_operand" "")))]
1723 "TARGET_68881 || TARGET_FPA"
1727 [(set (match_operand:SF 0 "general_operand" "=x,y")
1729 (match_operand:DF 1 "general_operand" "xH,rmF")))]
1733 ;; On the '040 we can truncate in a register accurately and easily.
1735 [(set (match_operand:SF 0 "general_operand" "=f")
1737 (match_operand:DF 1 "general_operand" "fmG")))]
1741 if (FP_REG_P (operands[1]))
1742 return \"f%$move%.x %1,%0\";
1743 return \"f%$move%.d %f1,%0\";
1747 [(set (match_operand:SF 0 "general_operand" "=dm")
1749 (match_operand:DF 1 "general_operand" "f")))]
1753 ;; Conversion between fixed point and floating point.
1754 ;; Note that among the fix-to-float insns
1755 ;; the ones that start with SImode come first.
1756 ;; That is so that an operand that is a CONST_INT
1757 ;; (and therefore lacks a specific machine mode).
1758 ;; will be recognized as SImode (which is always valid)
1759 ;; rather than as QImode or HImode.
1761 (define_expand "floatsisf2"
1762 [(set (match_operand:SF 0 "general_operand" "")
1763 (float:SF (match_operand:SI 1 "general_operand" "")))]
1764 "TARGET_68881 || TARGET_FPA"
1768 [(set (match_operand:SF 0 "general_operand" "=y,x")
1769 (float:SF (match_operand:SI 1 "general_operand" "rmi,x")))]
1774 [(set (match_operand:SF 0 "general_operand" "=f")
1775 (float:SF (match_operand:SI 1 "general_operand" "dmi")))]
1779 (define_expand "floatsidf2"
1780 [(set (match_operand:DF 0 "general_operand" "")
1781 (float:DF (match_operand:SI 1 "general_operand" "")))]
1782 "TARGET_68881 || TARGET_FPA"
1786 [(set (match_operand:DF 0 "general_operand" "=y,x")
1787 (float:DF (match_operand:SI 1 "general_operand" "rmi,x")))]
1792 [(set (match_operand:DF 0 "general_operand" "=f")
1793 (float:DF (match_operand:SI 1 "general_operand" "dmi")))]
1797 (define_insn "floathisf2"
1798 [(set (match_operand:SF 0 "general_operand" "=f")
1799 (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
1803 (define_insn "floathidf2"
1804 [(set (match_operand:DF 0 "general_operand" "=f")
1805 (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
1809 (define_insn "floatqisf2"
1810 [(set (match_operand:SF 0 "general_operand" "=f")
1811 (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
1815 (define_insn "floatqidf2"
1816 [(set (match_operand:DF 0 "general_operand" "=f")
1817 (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
1821 ;; New routines to convert floating-point values to integers
1822 ;; to be used on the '040. These should be faster than trapping
1823 ;; into the kernel to emulate fintrz. They should also be faster
1824 ;; than calling the subroutines fixsfsi or fixdfsi.
1826 (define_insn "fix_truncdfsi2"
1827 [(set (match_operand:SI 0 "general_operand" "=dm")
1828 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1829 (clobber (match_scratch:SI 2 "=d"))
1830 (clobber (match_scratch:SI 3 "=d"))]
1831 "TARGET_68881 && TARGET_68040"
1835 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\";
1838 (define_insn "fix_truncdfhi2"
1839 [(set (match_operand:HI 0 "general_operand" "=dm")
1840 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1841 (clobber (match_scratch:SI 2 "=d"))
1842 (clobber (match_scratch:SI 3 "=d"))]
1843 "TARGET_68881 && TARGET_68040"
1847 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\";
1850 (define_insn "fix_truncdfqi2"
1851 [(set (match_operand:QI 0 "general_operand" "=dm")
1852 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1853 (clobber (match_scratch:SI 2 "=d"))
1854 (clobber (match_scratch:SI 3 "=d"))]
1855 "TARGET_68881 && TARGET_68040"
1859 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\";
1862 ;; Convert a float to a float whose value is an integer.
1863 ;; This is the first stage of converting it to an integer type.
1865 (define_insn "ftruncdf2"
1866 [(set (match_operand:DF 0 "general_operand" "=f")
1867 (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
1868 "TARGET_68881 && !TARGET_68040"
1871 if (FP_REG_P (operands[1]))
1872 return \"fintrz%.x %f1,%0\";
1873 return \"fintrz%.d %f1,%0\";
1876 (define_insn "ftruncsf2"
1877 [(set (match_operand:SF 0 "general_operand" "=f")
1878 (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
1879 "TARGET_68881 && !TARGET_68040"
1882 if (FP_REG_P (operands[1]))
1883 return \"fintrz%.x %f1,%0\";
1884 return \"fintrz%.s %f1,%0\";
1887 ;; Convert a float whose value is an integer
1888 ;; to an actual integer. Second stage of converting float to integer type.
1889 (define_insn "fixsfqi2"
1890 [(set (match_operand:QI 0 "general_operand" "=dm")
1891 (fix:QI (match_operand:SF 1 "general_operand" "f")))]
1895 (define_insn "fixsfhi2"
1896 [(set (match_operand:HI 0 "general_operand" "=dm")
1897 (fix:HI (match_operand:SF 1 "general_operand" "f")))]
1901 (define_insn "fixsfsi2"
1902 [(set (match_operand:SI 0 "general_operand" "=dm")
1903 (fix:SI (match_operand:SF 1 "general_operand" "f")))]
1907 (define_insn "fixdfqi2"
1908 [(set (match_operand:QI 0 "general_operand" "=dm")
1909 (fix:QI (match_operand:DF 1 "general_operand" "f")))]
1913 (define_insn "fixdfhi2"
1914 [(set (match_operand:HI 0 "general_operand" "=dm")
1915 (fix:HI (match_operand:DF 1 "general_operand" "f")))]
1919 (define_insn "fixdfsi2"
1920 [(set (match_operand:SI 0 "general_operand" "=dm")
1921 (fix:SI (match_operand:DF 1 "general_operand" "f")))]
1925 ;; Convert a float to an integer.
1926 ;; On the Sun FPA, this is done in one step.
1929 [(set (match_operand:SI 0 "general_operand" "=x,y")
1930 (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "xH,rmF"))))]
1935 [(set (match_operand:SI 0 "general_operand" "=x,y")
1936 (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "xH,rmF"))))]
1942 (define_insn "adddi_lshrdi_63"
1943 [(set (match_operand:DI 0 "general_operand" "=d")
1944 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
1947 (clobber (match_scratch:SI 2 "=d"))]
1951 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1952 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
1954 \"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0\";
1955 if (GET_CODE (operands[1]) == REG)
1956 operands[4] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1957 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
1958 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1959 operands[4] = operands[1];
1961 operands[4] = adj_offsettable_operand (operands[1], 4);
1962 if (GET_CODE (operands[1]) == MEM
1963 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1964 output_asm_insn (\"move%.l %4,%3\", operands);
1965 output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
1966 if (TARGET_68020 || TARGET_5200)
1967 output_asm_insn (\"extb%.l %2\", operands);
1969 output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
1970 if (GET_CODE (operands[1]) != MEM
1971 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
1972 output_asm_insn (\"move%.l %4,%3\", operands);
1973 return \"sub%.l %2,%3\;subx%.l %2,%0\";
1976 (define_insn "adddi_sexthishl32"
1977 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
1978 (plus:DI (ashift:DI (sign_extend:DI
1979 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
1981 (match_operand:DI 2 "general_operand" "0,0,0,0")))
1982 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
1987 if (ADDRESS_REG_P (operands[0]))
1988 return \"add%.w %1,%0\";
1989 else if (ADDRESS_REG_P (operands[3]))
1990 return \"move%.w %1,%3\;add%.l %3,%0\";
1992 return \"move%.w %1,%3\;ext%.l %3\;add%.l %3,%0\";
1995 (define_insn "adddi_dilshr32"
1996 [(set (match_operand:DI 0 "general_operand" "=do")
1997 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
1998 ;; (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
1999 ;; (const_int 32))))]
2000 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
2002 (match_operand:DI 2 "general_operand" "0")))]
2007 if (GET_CODE (operands[0]) == REG)
2008 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
2010 operands[2] = adj_offsettable_operand (operands[0], 4);
2011 return \"add%.l %1,%2\;negx%.l %0\;neg%.l %0\";
2014 (define_insn "adddi_dishl32"
2015 [(set (match_operand:DI 0 "general_operand" "=ro")
2016 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2017 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2018 ;; (const_int 32))))]
2019 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2021 (match_operand:DI 2 "general_operand" "0")))]
2026 if (GET_CODE (operands[1]) == REG)
2027 operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2029 operands[1] = adj_offsettable_operand (operands[1], 4);
2030 return \"add%.l %1,%0\";
2033 (define_insn "adddi3"
2034 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2035 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0,0")
2036 (match_operand:DI 2 "general_operand" "<,d,o>,d,a")))
2037 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2041 if (DATA_REG_P (operands[0]))
2043 if (DATA_REG_P (operands[2]))
2044 return \"add%.l %R2,%R0\;addx%.l %2,%0\";
2045 else if (GET_CODE (operands[2]) == MEM
2046 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2048 return \"move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0\";
2052 /* TODO : this should work also for CONST operands[2] */
2053 if (GET_CODE (operands[2]) == REG)
2054 operands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
2056 operands[1] = adj_offsettable_operand (operands[2], 4);
2057 return \"move%.l %2,%3\;add%.l %1,%R0\;addx%.l %3,%0\";
2060 else if (GET_CODE (operands[0]) == MEM)
2062 if (GET_CODE (operands[2]) == MEM
2063 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2064 return \"add%.l %2,%0\;addx%.l %2,%0\";
2066 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2068 operands[1] = gen_rtx (MEM, SImode,
2069 gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
2070 gen_rtx (CONST_INT, VOIDmode, -8)));
2071 return \"move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1\";
2073 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2075 operands[1] = XEXP(operands[0], 0);
2076 return \"add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
2080 operands[1] = adj_offsettable_operand (operands[0], 4);
2081 return \"add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
2086 (define_insn "addsi_lshrsi_31"
2087 [(set (match_operand:SI 0 "general_operand" "=dm")
2088 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
2094 operands[2] = operands[0];
2095 operands[3] = gen_label_rtx();
2096 if (GET_CODE (operands[0]) == MEM)
2098 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2099 operands[0] = gen_rtx (MEM, SImode, XEXP (XEXP (operands[0], 0), 0));
2100 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2101 operands[2] = gen_rtx (MEM, SImode, XEXP (XEXP (operands[0], 0), 0));
2103 output_asm_insn (\"move%.l %1,%0\", operands);
2105 output_asm_insn (\"jbpl %l3\", operands);
2107 output_asm_insn (\"jpl %l3\", operands);
2110 output_asm_insn (\"addq%.l %#1,%2\", operands);
2112 output_asm_insn (\"add%.l %#1,%2\", operands);
2114 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
2115 CODE_LABEL_NUMBER (operands[3]));
2119 ;; Note that the middle two alternatives are near-duplicates
2120 ;; in order to handle insns generated by reload.
2121 ;; This is needed since they are not themselves reloaded,
2122 ;; so commutativity won't apply to them.
2123 (define_insn "addsi3"
2124 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
2125 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2126 (match_operand:SI 2 "general_operand" "dIKLs,rJK,a,mrIKLs")))]
2130 if (! operands_match_p (operands[0], operands[1]))
2132 if (!ADDRESS_REG_P (operands[1]))
2134 rtx tmp = operands[1];
2136 operands[1] = operands[2];
2140 /* These insns can result from reloads to access
2141 stack slots over 64k from the frame pointer. */
2142 if (GET_CODE (operands[2]) == CONST_INT
2143 && INTVAL (operands[2]) + 0x8000 >= (unsigned) 0x10000)
2144 return \"move%.l %2,%0\;add%.l %1,%0\";
2146 if (GET_CODE (operands[2]) == REG)
2147 return \"lea 0(%1,%2.l),%0\";
2149 return \"lea %c2(%1),%0\";
2152 if (GET_CODE (operands[2]) == REG)
2153 return \"lea (%1,%2.l),%0\";
2155 return \"lea (%c2,%1),%0\";
2156 #else /* not MOTOROLA (MIT syntax) */
2157 if (GET_CODE (operands[2]) == REG)
2158 return \"lea %1@(0,%2:l),%0\";
2160 return \"lea %1@(%c2),%0\";
2161 #endif /* not MOTOROLA */
2162 #endif /* not SGS */
2164 if (GET_CODE (operands[2]) == CONST_INT)
2167 if (INTVAL (operands[2]) > 0
2168 && INTVAL (operands[2]) <= 8)
2169 return \"addq%.l %2,%0\";
2170 if (INTVAL (operands[2]) < 0
2171 && INTVAL (operands[2]) >= -8)
2173 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2174 - INTVAL (operands[2]));
2175 return \"subq%.l %2,%0\";
2177 /* On the CPU32 it is faster to use two addql instructions to
2178 add a small integer (8 < N <= 16) to a register.
2179 Likewise for subql. */
2180 if (TARGET_CPU32 && REG_P (operands[0]))
2182 if (INTVAL (operands[2]) > 8
2183 && INTVAL (operands[2]) <= 16)
2185 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2186 INTVAL (operands[2]) - 8);
2187 return \"addq%.l %#8,%0\;addq%.l %2,%0\";
2189 if (INTVAL (operands[2]) < -8
2190 && INTVAL (operands[2]) >= -16)
2192 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2193 - INTVAL (operands[2]) - 8);
2194 return \"subq%.l %#8,%0\;subq%.l %2,%0\";
2198 if (ADDRESS_REG_P (operands[0])
2199 && INTVAL (operands[2]) >= -0x8000
2200 && INTVAL (operands[2]) < 0x8000)
2203 return \"add%.w %2,%0\";
2206 return \"lea (%c2,%0),%0\";
2208 return \"lea %0@(%c2),%0\";
2212 return \"add%.l %2,%0\";
2216 [(set (match_operand:SI 0 "general_operand" "=a")
2217 (plus:SI (match_operand:SI 1 "general_operand" "0")
2219 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2223 (define_insn "addhi3"
2224 [(set (match_operand:HI 0 "general_operand" "=m,r")
2225 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2226 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2230 if (GET_CODE (operands[2]) == CONST_INT)
2233 /* If the constant would be a negative number when interpreted as
2234 HImode, make it negative. This is usually, but not always, done
2235 elsewhere in the compiler. First check for constants out of range,
2236 which could confuse us. */
2238 if (INTVAL (operands[2]) >= 32768)
2239 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2240 INTVAL (operands[2]) - 65536);
2242 if (INTVAL (operands[2]) > 0
2243 && INTVAL (operands[2]) <= 8)
2244 return \"addq%.w %2,%0\";
2245 if (INTVAL (operands[2]) < 0
2246 && INTVAL (operands[2]) >= -8)
2248 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2249 - INTVAL (operands[2]));
2250 return \"subq%.w %2,%0\";
2252 /* On the CPU32 it is faster to use two addqw instructions to
2253 add a small integer (8 < N <= 16) to a register.
2254 Likewise for subqw. */
2255 if (TARGET_CPU32 && REG_P (operands[0]))
2257 if (INTVAL (operands[2]) > 8
2258 && INTVAL (operands[2]) <= 16)
2260 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2261 INTVAL (operands[2]) - 8);
2262 return \"addq%.w %#8,%0\;addq%.w %2,%0\";
2264 if (INTVAL (operands[2]) < -8
2265 && INTVAL (operands[2]) >= -16)
2267 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2268 - INTVAL (operands[2]) - 8);
2269 return \"subq%.w %#8,%0\;subq%.w %2,%0\";
2273 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2275 return \"lea (%c2,%0),%0\";
2277 return \"lea %0@(%c2),%0\";
2280 return \"add%.w %2,%0\";
2283 ;; These insns must use MATCH_DUP instead of the more expected
2284 ;; use of a matching constraint because the "output" here is also
2285 ;; an input, so you can't use the matching constraint. That also means
2286 ;; that you can't use the "%", so you need patterns with the matched
2287 ;; operand in both positions.
2290 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2291 (plus:HI (match_dup 0)
2292 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2296 if (GET_CODE (operands[1]) == CONST_INT)
2299 /* If the constant would be a negative number when interpreted as
2300 HImode, make it negative. This is usually, but not always, done
2301 elsewhere in the compiler. First check for constants out of range,
2302 which could confuse us. */
2304 if (INTVAL (operands[1]) >= 32768)
2305 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2306 INTVAL (operands[1]) - 65536);
2308 if (INTVAL (operands[1]) > 0
2309 && INTVAL (operands[1]) <= 8)
2310 return \"addq%.w %1,%0\";
2311 if (INTVAL (operands[1]) < 0
2312 && INTVAL (operands[1]) >= -8)
2314 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2315 - INTVAL (operands[1]));
2316 return \"subq%.w %1,%0\";
2318 /* On the CPU32 it is faster to use two addqw instructions to
2319 add a small integer (8 < N <= 16) to a register.
2320 Likewise for subqw. */
2321 if (TARGET_CPU32 && REG_P (operands[0]))
2323 if (INTVAL (operands[1]) > 8
2324 && INTVAL (operands[1]) <= 16)
2326 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2327 INTVAL (operands[1]) - 8);
2328 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2330 if (INTVAL (operands[1]) < -8
2331 && INTVAL (operands[1]) >= -16)
2333 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2334 - INTVAL (operands[1]) - 8);
2335 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2339 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2341 return \"lea (%c1,%0),%0\";
2343 return \"lea %0@(%c1),%0\";
2346 return \"add%.w %1,%0\";
2350 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2351 (plus:HI (match_operand:HI 1 "general_operand" "dn,rmn")
2356 if (GET_CODE (operands[1]) == CONST_INT)
2359 /* If the constant would be a negative number when interpreted as
2360 HImode, make it negative. This is usually, but not always, done
2361 elsewhere in the compiler. First check for constants out of range,
2362 which could confuse us. */
2364 if (INTVAL (operands[1]) >= 32768)
2365 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2366 INTVAL (operands[1]) - 65536);
2368 if (INTVAL (operands[1]) > 0
2369 && INTVAL (operands[1]) <= 8)
2370 return \"addq%.w %1,%0\";
2371 if (INTVAL (operands[1]) < 0
2372 && INTVAL (operands[1]) >= -8)
2374 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2375 - INTVAL (operands[1]));
2376 return \"subq%.w %1,%0\";
2378 /* On the CPU32 it is faster to use two addqw instructions to
2379 add a small integer (8 < N <= 16) to a register.
2380 Likewise for subqw. */
2381 if (TARGET_CPU32 && REG_P (operands[0]))
2383 if (INTVAL (operands[1]) > 8
2384 && INTVAL (operands[1]) <= 16)
2386 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2387 INTVAL (operands[1]) - 8);
2388 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2390 if (INTVAL (operands[1]) < -8
2391 && INTVAL (operands[1]) >= -16)
2393 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2394 - INTVAL (operands[1]) - 8);
2395 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2399 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2401 return \"lea (%c1,%0),%0\";
2403 return \"lea %0@(%c1),%0\";
2406 return \"add%.w %1,%0\";
2409 (define_insn "addqi3"
2410 [(set (match_operand:QI 0 "general_operand" "=m,d")
2411 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2412 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2417 if (GET_CODE (operands[2]) == CONST_INT)
2419 if (INTVAL (operands[2]) >= 128)
2420 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2421 INTVAL (operands[2]) - 256);
2423 if (INTVAL (operands[2]) > 0
2424 && INTVAL (operands[2]) <= 8)
2425 return \"addq%.b %2,%0\";
2426 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2428 operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2]));
2429 return \"subq%.b %2,%0\";
2433 return \"add%.b %2,%0\";
2437 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2438 (plus:QI (match_dup 0)
2439 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2444 if (GET_CODE (operands[1]) == CONST_INT)
2446 if (INTVAL (operands[1]) >= 128)
2447 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2448 INTVAL (operands[1]) - 256);
2450 if (INTVAL (operands[1]) > 0
2451 && INTVAL (operands[1]) <= 8)
2452 return \"addq%.b %1,%0\";
2453 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2455 operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]));
2456 return \"subq%.b %1,%0\";
2460 return \"add%.b %1,%0\";
2464 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2465 (plus:QI (match_operand:QI 1 "general_operand" "dn,dmn")
2471 if (GET_CODE (operands[1]) == CONST_INT)
2473 if (INTVAL (operands[1]) >= 128)
2474 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2475 INTVAL (operands[1]) - 256);
2477 if (INTVAL (operands[1]) > 0
2478 && INTVAL (operands[1]) <= 8)
2479 return \"addq%.b %1,%0\";
2480 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2482 operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]));
2483 return \"subq%.b %1,%0\";
2487 return \"add%.b %1,%0\";
2490 (define_expand "adddf3"
2491 [(set (match_operand:DF 0 "general_operand" "")
2492 (plus:DF (match_operand:DF 1 "general_operand" "")
2493 (match_operand:DF 2 "general_operand" "")))]
2494 "TARGET_68881 || TARGET_FPA"
2498 [(set (match_operand:DF 0 "general_operand" "=x,y")
2499 (plus:DF (match_operand:DF 1 "general_operand" "%xH,y")
2500 (match_operand:DF 2 "general_operand" "xH,dmF")))]
2504 if (rtx_equal_p (operands[0], operands[1]))
2505 return \"fpadd%.d %y2,%0\";
2506 if (rtx_equal_p (operands[0], operands[2]))
2507 return \"fpadd%.d %y1,%0\";
2508 if (which_alternative == 0)
2509 return \"fpadd3%.d %w2,%w1,%0\";
2510 return \"fpadd3%.d %x2,%x1,%0\";
2514 [(set (match_operand:DF 0 "general_operand" "=f")
2515 (plus:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2516 (match_operand:DF 1 "general_operand" "0")))]
2521 [(set (match_operand:DF 0 "general_operand" "=f")
2522 (plus:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2523 (match_operand:DF 1 "general_operand" "0")))]
2528 [(set (match_operand:DF 0 "general_operand" "=f")
2529 (plus:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2530 (match_operand:DF 1 "general_operand" "0")))]
2535 [(set (match_operand:DF 0 "general_operand" "=f")
2536 (plus:DF (match_operand:DF 1 "general_operand" "%0")
2537 (match_operand:DF 2 "general_operand" "fmG")))]
2541 if (REG_P (operands[2]))
2542 return \"f%&add%.x %2,%0\";
2543 return \"f%&add%.d %f2,%0\";
2546 (define_expand "addsf3"
2547 [(set (match_operand:SF 0 "general_operand" "")
2548 (plus:SF (match_operand:SF 1 "general_operand" "")
2549 (match_operand:SF 2 "general_operand" "")))]
2550 "TARGET_68881 || TARGET_FPA"
2554 [(set (match_operand:SF 0 "general_operand" "=x,y")
2555 (plus:SF (match_operand:SF 1 "general_operand" "%xH,y")
2556 (match_operand:SF 2 "general_operand" "xH,rmF")))]
2560 if (rtx_equal_p (operands[0], operands[1]))
2561 return \"fpadd%.s %w2,%0\";
2562 if (rtx_equal_p (operands[0], operands[2]))
2563 return \"fpadd%.s %w1,%0\";
2564 if (which_alternative == 0)
2565 return \"fpadd3%.s %w2,%w1,%0\";
2566 return \"fpadd3%.s %2,%1,%0\";
2570 [(set (match_operand:SF 0 "general_operand" "=f")
2571 (plus:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2572 (match_operand:SF 1 "general_operand" "0")))]
2577 [(set (match_operand:SF 0 "general_operand" "=f")
2578 (plus:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
2579 (match_operand:SF 1 "general_operand" "0")))]
2584 [(set (match_operand:SF 0 "general_operand" "=f")
2585 (plus:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
2586 (match_operand:SF 1 "general_operand" "0")))]
2591 [(set (match_operand:SF 0 "general_operand" "=f")
2592 (plus:SF (match_operand:SF 1 "general_operand" "%0")
2593 (match_operand:SF 2 "general_operand" "fdmF")))]
2597 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2598 return \"f%$add%.x %2,%0\";
2599 return \"f%$add%.s %f2,%0\";
2602 ;; subtract instructions
2604 (define_insn "subdi_sexthishl32"
2605 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2606 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2607 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2609 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2614 if (ADDRESS_REG_P (operands[0]))
2615 return \"sub%.w %2,%0\";
2616 else if (ADDRESS_REG_P (operands[3]))
2617 return \"move%.w %2,%3\;sub%.l %3,%0\";
2619 return \"move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0\";
2622 (define_insn "subdi_dishl32"
2623 [(set (match_operand:DI 0 "general_operand" "+ro")
2624 (minus:DI (match_dup 0)
2625 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2631 if (GET_CODE (operands[1]) == REG)
2632 operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2634 operands[1] = adj_offsettable_operand (operands[1], 4);
2635 return \"sub%.l %1,%0\";
2638 (define_insn "subdi3"
2639 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2640 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0,0")
2641 (match_operand:DI 2 "general_operand" "<,d,o>,d,a")))
2642 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2646 if (DATA_REG_P (operands[0]))
2648 if (DATA_REG_P (operands[2]))
2649 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
2650 else if (GET_CODE (operands[2]) == MEM
2651 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2653 return \"move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0\";
2657 /* TODO : this should work also for CONST operands[2] */
2658 if (GET_CODE (operands[2]) == REG)
2659 operands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
2661 operands[1] = adj_offsettable_operand (operands[2], 4);
2662 return \"move%.l %2,%3\;sub%.l %1,%R0\;subx%.l %3,%0\";
2665 else if (GET_CODE (operands[0]) == MEM)
2667 if (GET_CODE (operands[2]) == MEM
2668 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2669 return \"sub%.l %2,%0\;subx%.l %2,%0\";
2671 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2673 operands[1] = gen_rtx (MEM, SImode,
2674 gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
2675 gen_rtx (CONST_INT, VOIDmode, -8)));
2676 return \"move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1\";
2678 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2680 operands[1] = XEXP(operands[0], 0);
2681 return \"sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
2685 operands[1] = adj_offsettable_operand (operands[0], 4);
2686 return \"sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
2691 (define_insn "subsi3"
2692 [(set (match_operand:SI 0 "general_operand" "=m,r")
2693 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
2694 (match_operand:SI 2 "general_operand" "ds,mrs")))]
2699 [(set (match_operand:SI 0 "general_operand" "=a")
2700 (minus:SI (match_operand:SI 1 "general_operand" "0")
2702 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2706 (define_insn "subhi3"
2707 [(set (match_operand:HI 0 "general_operand" "=m,r")
2708 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2709 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2714 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2715 (minus:HI (match_dup 0)
2716 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2720 (define_insn "subqi3"
2721 [(set (match_operand:QI 0 "general_operand" "=m,d")
2722 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2723 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2728 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2729 (minus:QI (match_dup 0)
2730 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2734 (define_expand "subdf3"
2735 [(set (match_operand:DF 0 "general_operand" "")
2736 (minus:DF (match_operand:DF 1 "general_operand" "")
2737 (match_operand:DF 2 "general_operand" "")))]
2738 "TARGET_68881 || TARGET_FPA"
2742 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
2743 (minus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF")
2744 (match_operand:DF 2 "general_operand" "xH,dmF,0")))]
2748 if (rtx_equal_p (operands[0], operands[2]))
2749 return \"fprsub%.d %y1,%0\";
2750 if (rtx_equal_p (operands[0], operands[1]))
2751 return \"fpsub%.d %y2,%0\";
2752 if (which_alternative == 0)
2753 return \"fpsub3%.d %w2,%w1,%0\";
2754 return \"fpsub3%.d %x2,%x1,%0\";
2758 [(set (match_operand:DF 0 "general_operand" "=f")
2759 (minus:DF (match_operand:DF 1 "general_operand" "0")
2760 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
2765 [(set (match_operand:DF 0 "general_operand" "=f")
2766 (minus:DF (match_operand:DF 1 "general_operand" "0")
2767 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
2772 [(set (match_operand:DF 0 "general_operand" "=f")
2773 (minus:DF (match_operand:DF 1 "general_operand" "0")
2774 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
2779 [(set (match_operand:DF 0 "general_operand" "=f")
2780 (minus:DF (match_operand:DF 1 "general_operand" "0")
2781 (match_operand:DF 2 "general_operand" "fmG")))]
2785 if (REG_P (operands[2]))
2786 return \"f%&sub%.x %2,%0\";
2787 return \"f%&sub%.d %f2,%0\";
2790 (define_expand "subsf3"
2791 [(set (match_operand:SF 0 "general_operand" "")
2792 (minus:SF (match_operand:SF 1 "general_operand" "")
2793 (match_operand:SF 2 "general_operand" "")))]
2794 "TARGET_68881 || TARGET_FPA"
2798 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
2799 (minus:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
2800 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
2804 if (rtx_equal_p (operands[0], operands[2]))
2805 return \"fprsub%.s %w1,%0\";
2806 if (rtx_equal_p (operands[0], operands[1]))
2807 return \"fpsub%.s %w2,%0\";
2808 if (which_alternative == 0)
2809 return \"fpsub3%.s %w2,%w1,%0\";
2810 return \"fpsub3%.s %2,%1,%0\";
2814 [(set (match_operand:SF 0 "general_operand" "=f")
2815 (minus:SF (match_operand:SF 1 "general_operand" "0")
2816 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
2821 [(set (match_operand:SF 0 "general_operand" "=f")
2822 (minus:SF (match_operand:SF 1 "general_operand" "0")
2823 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
2828 [(set (match_operand:SF 0 "general_operand" "=f")
2829 (minus:SF (match_operand:SF 1 "general_operand" "0")
2830 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
2835 [(set (match_operand:SF 0 "general_operand" "=f")
2836 (minus:SF (match_operand:SF 1 "general_operand" "0")
2837 (match_operand:SF 2 "general_operand" "fdmF")))]
2841 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2842 return \"f%$sub%.x %2,%0\";
2843 return \"f%$sub%.s %f2,%0\";
2846 ;; multiply instructions
2848 (define_insn "mulhi3"
2849 [(set (match_operand:HI 0 "general_operand" "=d")
2850 (mult:HI (match_operand:HI 1 "general_operand" "%0")
2851 (match_operand:HI 2 "general_operand" "dmn")))]
2855 #if defined(MOTOROLA) && !defined(CRDS)
2856 return \"muls%.w %2,%0\";
2858 return \"muls %2,%0\";
2862 (define_insn "mulhisi3"
2863 [(set (match_operand:SI 0 "general_operand" "=d")
2864 (mult:SI (sign_extend:SI
2865 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2867 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
2871 #if defined(MOTOROLA) && !defined(CRDS)
2872 return \"muls%.w %2,%0\";
2874 return \"muls %2,%0\";
2879 [(set (match_operand:SI 0 "general_operand" "=d")
2880 (mult:SI (sign_extend:SI
2881 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2882 (match_operand:SI 2 "const_int_operand" "n")))]
2883 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
2886 #if defined(MOTOROLA) && !defined(CRDS)
2887 return \"muls%.w %2,%0\";
2889 return \"muls %2,%0\";
2893 (define_insn "mulsi3"
2894 [(set (match_operand:SI 0 "general_operand" "=d")
2895 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2896 (match_operand:SI 2 "general_operand" "dmsK")))]
2897 "TARGET_68020 || TARGET_5200"
2900 (define_insn "umulhisi3"
2901 [(set (match_operand:SI 0 "general_operand" "=d")
2902 (mult:SI (zero_extend:SI
2903 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2905 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
2909 #if defined(MOTOROLA) && !defined(CRDS)
2910 return \"mulu%.w %2,%0\";
2912 return \"mulu %2,%0\";
2917 [(set (match_operand:SI 0 "general_operand" "=d")
2918 (mult:SI (zero_extend:SI
2919 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2920 (match_operand:SI 2 "const_int_operand" "n")))]
2921 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
2924 #if defined(MOTOROLA) && !defined(CRDS)
2925 return \"mulu%.w %2,%0\";
2927 return \"mulu %2,%0\";
2931 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
2932 ;; proper matching constraint. This is because the matching is between
2933 ;; the high-numbered word of the DImode operand[0] and operand[1].
2934 (define_expand "umulsidi3"
2936 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
2937 (mult:SI (match_operand:SI 1 "register_operand" "")
2938 (match_operand:SI 2 "nonimmediate_operand" "")))
2939 (set (subreg:SI (match_dup 0) 0)
2940 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2941 (zero_extend:DI (match_dup 2)))
2942 (const_int 32))))])]
2943 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2947 [(set (match_operand:SI 0 "register_operand" "=d")
2948 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2949 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2950 (set (match_operand:SI 3 "register_operand" "=d")
2951 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2952 (zero_extend:DI (match_dup 2)))
2954 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2957 ; Match immediate case. For 2.4 only match things < 2^31.
2958 ; It's tricky with larger values in these patterns since we need to match
2959 ; values between the two parallel multiplies, between a CONST_DOUBLE and
2962 [(set (match_operand:SI 0 "register_operand" "=d")
2963 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2964 (match_operand:SI 2 "const_int_operand" "n")))
2965 (set (match_operand:SI 3 "register_operand" "=d")
2966 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2969 "TARGET_68020 && !TARGET_68060 && !TARGET_5200
2970 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
2973 (define_expand "mulsidi3"
2975 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
2976 (mult:SI (match_operand:SI 1 "register_operand" "")
2977 (match_operand:SI 2 "nonimmediate_operand" "")))
2978 (set (subreg:SI (match_dup 0) 0)
2979 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2980 (sign_extend:DI (match_dup 2)))
2981 (const_int 32))))])]
2982 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2986 [(set (match_operand:SI 0 "register_operand" "=d")
2987 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2988 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2989 (set (match_operand:SI 3 "register_operand" "=d")
2990 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2991 (sign_extend:DI (match_dup 2)))
2993 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2997 [(set (match_operand:SI 0 "register_operand" "=d")
2998 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2999 (match_operand:SI 2 "const_sint32_operand" "")))
3000 (set (match_operand:SI 3 "register_operand" "=d")
3001 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3004 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3007 (define_expand "umulsi3_highpart"
3009 [(set (match_operand:SI 0 "register_operand" "")
3012 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
3013 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
3015 (clobber (match_dup 3))])]
3016 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3019 operands[3] = gen_reg_rtx (SImode);
3020 if (GET_CODE (operands[2]) == CONST_INT
3021 || GET_CODE (operands[2]) == CONST_DOUBLE)
3023 if (! const_uint32_operand (operands[2], VOIDmode))
3025 /* We have to adjust the operand order for the matching constraints. */
3026 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
3027 operands[1], operands[2]));
3033 [(set (match_operand:SI 0 "register_operand" "=d")
3036 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3037 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3039 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3040 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3043 (define_insn "const_umulsi3_highpart"
3044 [(set (match_operand:SI 0 "register_operand" "=d")
3047 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
3048 (match_operand 3 "const_uint32_operand" ""))
3050 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3051 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3054 (define_expand "smulsi3_highpart"
3056 [(set (match_operand:SI 0 "register_operand" "")
3059 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
3060 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
3062 (clobber (match_dup 3))])]
3063 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3066 operands[3] = gen_reg_rtx (SImode);
3067 if (GET_CODE (operands[2]) == CONST_INT
3068 || GET_CODE (operands[2]) == CONST_DOUBLE)
3070 if (! const_sint32_operand (operands[2], VOIDmode))
3072 /* We have to adjust the operand order for the matching constraints. */
3073 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
3074 operands[1], operands[2]));
3080 [(set (match_operand:SI 0 "register_operand" "=d")
3083 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3084 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3086 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3087 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3090 (define_insn "const_smulsi3_highpart"
3091 [(set (match_operand:SI 0 "register_operand" "=d")
3094 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
3095 (match_operand 3 "const_sint32_operand" ""))
3097 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3098 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3101 (define_expand "muldf3"
3102 [(set (match_operand:DF 0 "general_operand" "")
3103 (mult:DF (match_operand:DF 1 "general_operand" "")
3104 (match_operand:DF 2 "general_operand" "")))]
3105 "TARGET_68881 || TARGET_FPA"
3109 [(set (match_operand:DF 0 "general_operand" "=x,y")
3110 (mult:DF (match_operand:DF 1 "general_operand" "%xH,y")
3111 (match_operand:DF 2 "general_operand" "xH,rmF")))]
3115 if (rtx_equal_p (operands[1], operands[2]))
3116 return \"fpsqr%.d %y1,%0\";
3117 if (rtx_equal_p (operands[0], operands[1]))
3118 return \"fpmul%.d %y2,%0\";
3119 if (rtx_equal_p (operands[0], operands[2]))
3120 return \"fpmul%.d %y1,%0\";
3121 if (which_alternative == 0)
3122 return \"fpmul3%.d %w2,%w1,%0\";
3123 return \"fpmul3%.d %x2,%x1,%0\";
3127 [(set (match_operand:DF 0 "general_operand" "=f")
3128 (mult:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
3129 (match_operand:DF 1 "general_operand" "0")))]
3134 [(set (match_operand:DF 0 "general_operand" "=f")
3135 (mult:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
3136 (match_operand:DF 1 "general_operand" "0")))]
3141 [(set (match_operand:DF 0 "general_operand" "=f")
3142 (mult:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
3143 (match_operand:DF 1 "general_operand" "0")))]
3148 [(set (match_operand:DF 0 "general_operand" "=f")
3149 (mult:DF (match_operand:DF 1 "general_operand" "%0")
3150 (match_operand:DF 2 "general_operand" "fmG")))]
3154 if (GET_CODE (operands[2]) == CONST_DOUBLE
3155 && floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
3157 int i = floating_exact_log2 (operands[2]);
3158 operands[2] = gen_rtx (CONST_INT, VOIDmode, i);
3159 return \"fscale%.l %2,%0\";
3161 if (REG_P (operands[2]))
3162 return \"f%&mul%.x %2,%0\";
3163 return \"f%&mul%.d %f2,%0\";
3166 (define_expand "mulsf3"
3167 [(set (match_operand:SF 0 "general_operand" "")
3168 (mult:SF (match_operand:SF 1 "general_operand" "")
3169 (match_operand:SF 2 "general_operand" "")))]
3170 "TARGET_68881 || TARGET_FPA"
3174 [(set (match_operand:SF 0 "general_operand" "=x,y")
3175 (mult:SF (match_operand:SF 1 "general_operand" "%xH,y")
3176 (match_operand:SF 2 "general_operand" "xH,rmF")))]
3180 if (rtx_equal_p (operands[1], operands[2]))
3181 return \"fpsqr%.s %w1,%0\";
3182 if (rtx_equal_p (operands[0], operands[1]))
3183 return \"fpmul%.s %w2,%0\";
3184 if (rtx_equal_p (operands[0], operands[2]))
3185 return \"fpmul%.s %w1,%0\";
3186 if (which_alternative == 0)
3187 return \"fpmul3%.s %w2,%w1,%0\";
3188 return \"fpmul3%.s %2,%1,%0\";
3192 [(set (match_operand:SF 0 "general_operand" "=f")
3193 (mult:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
3194 (match_operand:SF 1 "general_operand" "0")))]
3198 return (TARGET_68040_ONLY
3199 ? \"fsmul%.l %2,%0\"
3200 : \"fsglmul%.l %2,%0\");
3204 [(set (match_operand:SF 0 "general_operand" "=f")
3205 (mult:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
3206 (match_operand:SF 1 "general_operand" "0")))]
3210 return (TARGET_68040_ONLY
3211 ? \"fsmul%.w %2,%0\"
3212 : \"fsglmul%.w %2,%0\");
3216 [(set (match_operand:SF 0 "general_operand" "=f")
3217 (mult:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
3218 (match_operand:SF 1 "general_operand" "0")))]
3222 return (TARGET_68040_ONLY
3223 ? \"fsmul%.b %2,%0\"
3224 : \"fsglmul%.b %2,%0\");
3228 [(set (match_operand:SF 0 "general_operand" "=f")
3229 (mult:SF (match_operand:SF 1 "general_operand" "%0")
3230 (match_operand:SF 2 "general_operand" "fdmF")))]
3234 #ifdef FSGLMUL_USE_S
3235 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3236 return (TARGET_68040_ONLY
3237 ? \"fsmul%.s %2,%0\"
3238 : \"fsglmul%.s %2,%0\");
3240 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3241 return (TARGET_68040_ONLY
3242 ? \"fsmul%.x %2,%0\"
3243 : \"fsglmul%.x %2,%0\");
3245 return (TARGET_68040_ONLY
3246 ? \"fsmul%.s %f2,%0\"
3247 : \"fsglmul%.s %f2,%0\");
3250 ;; divide instructions
3252 (define_expand "divdf3"
3253 [(set (match_operand:DF 0 "general_operand" "")
3254 (div:DF (match_operand:DF 1 "general_operand" "")
3255 (match_operand:DF 2 "general_operand" "")))]
3256 "TARGET_68881 || TARGET_FPA"
3260 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
3261 (div:DF (match_operand:DF 1 "general_operand" "xH,y,rmF")
3262 (match_operand:DF 2 "general_operand" "xH,rmF,0")))]
3266 if (rtx_equal_p (operands[0], operands[2]))
3267 return \"fprdiv%.d %y1,%0\";
3268 if (rtx_equal_p (operands[0], operands[1]))
3269 return \"fpdiv%.d %y2,%0\";
3270 if (which_alternative == 0)
3271 return \"fpdiv3%.d %w2,%w1,%0\";
3272 return \"fpdiv3%.d %x2,%x1,%x0\";
3276 [(set (match_operand:DF 0 "general_operand" "=f")
3277 (div:DF (match_operand:DF 1 "general_operand" "0")
3278 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
3283 [(set (match_operand:DF 0 "general_operand" "=f")
3284 (div:DF (match_operand:DF 1 "general_operand" "0")
3285 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
3290 [(set (match_operand:DF 0 "general_operand" "=f")
3291 (div:DF (match_operand:DF 1 "general_operand" "0")
3292 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
3297 [(set (match_operand:DF 0 "general_operand" "=f")
3298 (div:DF (match_operand:DF 1 "general_operand" "0")
3299 (match_operand:DF 2 "general_operand" "fmG")))]
3303 if (REG_P (operands[2]))
3304 return \"f%&div%.x %2,%0\";
3305 return \"f%&div%.d %f2,%0\";
3308 (define_expand "divsf3"
3309 [(set (match_operand:SF 0 "general_operand" "")
3310 (div:SF (match_operand:SF 1 "general_operand" "")
3311 (match_operand:SF 2 "general_operand" "")))]
3312 "TARGET_68881 || TARGET_FPA"
3316 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
3317 (div:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
3318 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
3322 if (rtx_equal_p (operands[0], operands[1]))
3323 return \"fpdiv%.s %w2,%0\";
3324 if (rtx_equal_p (operands[0], operands[2]))
3325 return \"fprdiv%.s %w1,%0\";
3326 if (which_alternative == 0)
3327 return \"fpdiv3%.s %w2,%w1,%0\";
3328 return \"fpdiv3%.s %2,%1,%0\";
3332 [(set (match_operand:SF 0 "general_operand" "=f")
3333 (div:SF (match_operand:SF 1 "general_operand" "0")
3334 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
3338 return (TARGET_68040_ONLY
3339 ? \"fsdiv%.l %2,%0\"
3340 : \"fsgldiv%.l %2,%0\");
3344 [(set (match_operand:SF 0 "general_operand" "=f")
3345 (div:SF (match_operand:SF 1 "general_operand" "0")
3346 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
3350 return (TARGET_68040_ONLY
3351 ? \"fsdiv%.w %2,%0\"
3352 : \"fsgldiv%.w %2,%0\");
3356 [(set (match_operand:SF 0 "general_operand" "=f")
3357 (div:SF (match_operand:SF 1 "general_operand" "0")
3358 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
3362 return (TARGET_68040_ONLY
3363 ? \"fsdiv%.b %2,%0\"
3364 : \"fsgldiv%.b %2,%0\");
3368 [(set (match_operand:SF 0 "general_operand" "=f")
3369 (div:SF (match_operand:SF 1 "general_operand" "0")
3370 (match_operand:SF 2 "general_operand" "fdmF")))]
3374 #ifdef FSGLDIV_USE_S
3375 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3376 return (TARGET_68040_ONLY
3377 ? \"fsdiv%.s %2,%0\"
3378 : \"fsgldiv%.s %2,%0\");
3380 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3381 return (TARGET_68040_ONLY
3382 ? \"fsdiv%.x %2,%0\"
3383 : \"fsgldiv%.x %2,%0\");
3385 return (TARGET_68040_ONLY
3386 ? \"fsdiv%.s %f2,%0\"
3387 : \"fsgldiv%.s %f2,%0\");
3390 ;; Remainder instructions.
3392 (define_insn "divmodsi4"
3393 [(set (match_operand:SI 0 "general_operand" "=d")
3394 (div:SI (match_operand:SI 1 "general_operand" "0")
3395 (match_operand:SI 2 "general_operand" "dmsK")))
3396 (set (match_operand:SI 3 "general_operand" "=d")
3397 (mod:SI (match_dup 1) (match_dup 2)))]
3398 "TARGET_68020 && !TARGET_5200"
3401 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3402 return \"divs%.l %2,%0\";
3404 return \"divsl%.l %2,%3:%0\";
3407 (define_insn "udivmodsi4"
3408 [(set (match_operand:SI 0 "general_operand" "=d")
3409 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3410 (match_operand:SI 2 "general_operand" "dmsK")))
3411 (set (match_operand:SI 3 "general_operand" "=d")
3412 (umod:SI (match_dup 1) (match_dup 2)))]
3413 "TARGET_68020 && !TARGET_5200"
3416 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3417 return \"divu%.l %2,%0\";
3419 return \"divul%.l %2,%3:%0\";
3422 (define_insn "divmodhi4"
3423 [(set (match_operand:HI 0 "general_operand" "=d")
3424 (div:HI (match_operand:HI 1 "general_operand" "0")
3425 (match_operand:HI 2 "general_operand" "dmsK")))
3426 (set (match_operand:HI 3 "general_operand" "=d")
3427 (mod:HI (match_dup 1) (match_dup 2)))]
3432 output_asm_insn(\"ext%.l %0\;divs%.w %2,%0\", operands);
3434 output_asm_insn(\"extl %0\;divs %2,%0\", operands);
3436 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3439 return \"move%.l %0,%3\;swap %3\";
3445 (define_insn "udivmodhi4"
3446 [(set (match_operand:HI 0 "general_operand" "=d")
3447 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3448 (match_operand:HI 2 "general_operand" "dmsK")))
3449 (set (match_operand:HI 3 "general_operand" "=d")
3450 (umod:HI (match_dup 1) (match_dup 2)))]
3455 output_asm_insn(\"and%.l %#0xFFFF,%0\;divu%.w %2,%0\", operands);
3457 output_asm_insn(\"and%.l %#0xFFFF,%0\;divu %2,%0\", operands);
3459 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3462 return \"move%.l %0,%3\;swap %3\";
3468 ;; logical-and instructions
3470 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3471 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3472 ;; can't allocate pseudos into it.
3474 (define_expand "andsi3"
3475 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3476 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3477 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3481 (define_insn "andsi3_internal"
3482 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3483 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3484 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3489 if (GET_CODE (operands[2]) == CONST_INT
3490 && (INTVAL (operands[2]) | 0xffff) == 0xffffffff
3491 && (DATA_REG_P (operands[0])
3492 || offsettable_memref_p (operands[0])))
3494 if (GET_CODE (operands[0]) != REG)
3495 operands[0] = adj_offsettable_operand (operands[0], 2);
3496 operands[2] = gen_rtx (CONST_INT, VOIDmode,
3497 INTVAL (operands[2]) & 0xffff);
3498 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3500 if (operands[2] == const0_rtx)
3501 return \"clr%.w %0\";
3502 return \"and%.w %2,%0\";
3504 if (GET_CODE (operands[2]) == CONST_INT
3505 && (logval = exact_log2 (~ INTVAL (operands[2]))) >= 0
3506 && (DATA_REG_P (operands[0])
3507 || offsettable_memref_p (operands[0])))
3509 if (DATA_REG_P (operands[0]))
3511 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval);
3515 operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
3516 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8);
3518 /* This does not set condition codes in a standard way. */
3520 return \"bclr %1,%0\";
3522 return \"and%.l %2,%0\";
3525 (define_insn "andsi3_5200"
3526 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3527 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3528 (match_operand:SI 2 "general_operand" "d,dmsK")))]
3532 (define_insn "andhi3"
3533 [(set (match_operand:HI 0 "general_operand" "=m,d")
3534 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3535 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3540 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3541 (and:HI (match_dup 0)
3542 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3547 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3548 (and:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3553 (define_insn "andqi3"
3554 [(set (match_operand:QI 0 "general_operand" "=m,d")
3555 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3556 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3561 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3562 (and:QI (match_dup 0)
3563 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3568 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3569 (and:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3574 ;; inclusive-or instructions
3576 (define_expand "iorsi3"
3577 [(set (match_operand:SI 0 "general_operand" "")
3578 (ior:SI (match_operand:SI 1 "general_operand" "")
3579 (match_operand:SI 2 "general_operand" "")))]
3583 (define_insn "iorsi3_internal"
3584 [(set (match_operand:SI 0 "general_operand" "=m,d")
3585 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3586 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3590 register int logval;
3591 if (GET_CODE (operands[2]) == CONST_INT
3592 && INTVAL (operands[2]) >> 16 == 0
3593 && (DATA_REG_P (operands[0])
3594 || offsettable_memref_p (operands[0])))
3596 if (GET_CODE (operands[0]) != REG)
3597 operands[0] = adj_offsettable_operand (operands[0], 2);
3598 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3600 return \"or%.w %2,%0\";
3602 if (GET_CODE (operands[2]) == CONST_INT
3603 && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
3604 && (DATA_REG_P (operands[0])
3605 || offsettable_memref_p (operands[0])))
3607 if (DATA_REG_P (operands[0]))
3609 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval);
3613 operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
3614 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8);
3617 return \"bset %1,%0\";
3619 return \"or%.l %2,%0\";
3622 (define_insn "iorsi3_5200"
3623 [(set (match_operand:SI 0 "general_operand" "=m,d")
3624 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3625 (match_operand:SI 2 "general_operand" "d,dmsK")))]
3629 (define_insn "iorhi3"
3630 [(set (match_operand:HI 0 "general_operand" "=m,d")
3631 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3632 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3637 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3638 (ior:HI (match_dup 0)
3639 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3644 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3645 (ior:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3650 (define_insn "iorqi3"
3651 [(set (match_operand:QI 0 "general_operand" "=m,d")
3652 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3653 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3658 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3659 (ior:QI (match_dup 0)
3660 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3665 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3666 (ior:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3671 ;; On all 68k models, this makes faster code in a special case.
3672 ;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
3674 (define_insn "iorsi_zexthi_ashl16"
3675 [(set (match_operand:SI 0 "general_operand" "=d,d")
3676 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "dmn,dmn"))
3677 (ashift:SI (match_operand:SI 2 "general_operand" "o,0")
3683 if (GET_CODE (operands[2]) != REG)
3685 operands[2] = adj_offsettable_operand (operands[2], 2);
3686 output_asm_insn (\"move%.w %2,%0\", operands);
3688 return \"swap %0\;mov%.w %1,%0\";
3692 [(set (match_operand:SI 0 "general_operand" "=o,d")
3693 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3694 (match_operand:SI 2 "general_operand" "0,0")))]
3701 byte_mode = (GET_MODE(operands[1]) == QImode);
3702 if (GET_CODE (operands[0]) == MEM)
3703 operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
3705 return \"or%.b %1,%0\";
3707 return \"or%.w %1,%0\";
3712 (define_expand "xorsi3"
3713 [(set (match_operand:SI 0 "general_operand" "")
3714 (xor:SI (match_operand:SI 1 "general_operand" "")
3715 (match_operand:SI 2 "general_operand" "")))]
3719 (define_insn "xorsi3_internal"
3720 [(set (match_operand:SI 0 "general_operand" "=do,m")
3721 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3722 (match_operand:SI 2 "general_operand" "di,dKs")))]
3726 if (GET_CODE (operands[2]) == CONST_INT
3727 && INTVAL (operands[2]) >> 16 == 0
3728 && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0])))
3730 if (! DATA_REG_P (operands[0]))
3731 operands[0] = adj_offsettable_operand (operands[0], 2);
3732 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3734 return \"eor%.w %2,%0\";
3736 return \"eor%.l %2,%0\";
3739 (define_insn "xorsi3_5200"
3740 [(set (match_operand:SI 0 "general_operand" "=dm,d")
3741 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3742 (match_operand:SI 2 "general_operand" "d,Ks")))]
3746 (define_insn "xorhi3"
3747 [(set (match_operand:HI 0 "general_operand" "=dm")
3748 (xor:HI (match_operand:HI 1 "general_operand" "%0")
3749 (match_operand:HI 2 "general_operand" "dn")))]
3754 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3755 (xor:HI (match_dup 0)
3756 (match_operand:HI 1 "general_operand" "dn")))]
3761 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3762 (xor:HI (match_operand:HI 1 "general_operand" "dn")
3767 (define_insn "xorqi3"
3768 [(set (match_operand:QI 0 "general_operand" "=dm")
3769 (xor:QI (match_operand:QI 1 "general_operand" "%0")
3770 (match_operand:QI 2 "general_operand" "dn")))]
3775 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
3776 (xor:QI (match_dup 0)
3777 (match_operand:QI 1 "general_operand" "dn")))]
3782 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
3783 (xor:QI (match_operand:QI 1 "general_operand" "dn")
3788 ;; negation instructions
3790 (define_expand "negdi2"
3791 [(set (match_operand:DI 0 "general_operand" "")
3792 (neg:DI (match_operand:DI 1 "general_operand" "")))]
3797 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
3799 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
3803 (define_insn "negdi2_internal"
3804 [(set (match_operand:DI 0 "general_operand" "=<,do,!*a")
3805 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
3809 if (which_alternative == 0)
3810 return \"neg%.l %0\;negx%.l %0\";
3811 if (GET_CODE (operands[0]) == REG)
3812 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3814 operands[1] = adj_offsettable_operand (operands[0], 4);
3815 if (ADDRESS_REG_P (operands[0]))
3816 return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
3818 return \"neg%.l %1\;negx%.l %0\";
3821 (define_insn "negdi2_5200"
3822 [(set (match_operand:DI 0 "general_operand" "=d")
3823 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
3827 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3828 return \"neg%.l %1\;negx%.l %0\";
3831 (define_expand "negsi2"
3832 [(set (match_operand:SI 0 "general_operand" "")
3833 (neg:SI (match_operand:SI 1 "general_operand" "")))]
3838 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
3840 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
3844 (define_insn "negsi2_internal"
3845 [(set (match_operand:SI 0 "general_operand" "=dm")
3846 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3850 (define_insn "negsi2_5200"
3851 [(set (match_operand:SI 0 "general_operand" "=d")
3852 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3856 (define_insn "neghi2"
3857 [(set (match_operand:HI 0 "general_operand" "=dm")
3858 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
3863 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3864 (neg:HI (match_dup 0)))]
3868 (define_insn "negqi2"
3869 [(set (match_operand:QI 0 "general_operand" "=dm")
3870 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
3875 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
3876 (neg:QI (match_dup 0)))]
3880 ;; If using software floating point, just flip the sign bit.
3882 (define_expand "negsf2"
3883 [(set (match_operand:SF 0 "general_operand" "")
3884 (neg:SF (match_operand:SF 1 "general_operand" "")))]
3888 if (!TARGET_FPA && !TARGET_68881)
3893 target = operand_subword_force (operands[0], 0, SFmode);
3894 result = expand_binop (SImode, xor_optab,
3895 operand_subword_force (operands[1], 0, SFmode),
3896 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
3900 if (result != target)
3901 emit_move_insn (result, target);
3903 /* Make a place for REG_EQUAL. */
3904 emit_move_insn (operands[0], operands[0]);
3910 [(set (match_operand:SF 0 "general_operand" "=x,y")
3911 (neg:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
3916 [(set (match_operand:SF 0 "general_operand" "=f,d")
3917 (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))]
3921 if (DATA_REG_P (operands[0]))
3923 operands[1] = gen_rtx (CONST_INT, VOIDmode, 31);
3924 return \"bchg %1,%0\";
3926 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3927 return \"f%$neg%.x %1,%0\";
3928 return \"f%$neg%.s %f1,%0\";
3931 (define_expand "negdf2"
3932 [(set (match_operand:DF 0 "general_operand" "")
3933 (neg:DF (match_operand:DF 1 "general_operand" "")))]
3937 if (!TARGET_FPA && !TARGET_68881)
3944 target = operand_subword (operands[0], 0, 1, DFmode);
3945 result = expand_binop (SImode, xor_optab,
3946 operand_subword_force (operands[1], 0, DFmode),
3947 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
3951 if (result != target)
3952 emit_move_insn (result, target);
3954 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
3955 operand_subword_force (operands[1], 1, DFmode));
3957 insns = get_insns ();
3960 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
3966 [(set (match_operand:DF 0 "general_operand" "=x,y")
3967 (neg:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
3972 [(set (match_operand:DF 0 "general_operand" "=f,d")
3973 (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
3977 if (DATA_REG_P (operands[0]))
3979 operands[1] = gen_rtx (CONST_INT, VOIDmode, 31);
3980 return \"bchg %1,%0\";
3982 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3983 return \"f%&neg%.x %1,%0\";
3984 return \"f%&neg%.d %f1,%0\";
3987 ;; Sqrt instruction for the 68881
3989 (define_insn "sqrtsf2"
3990 [(set (match_operand:SF 0 "general_operand" "=f")
3991 (sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
3995 if (FP_REG_P (operands[1]))
3996 return \"f%$sqrt%.x %1,%0\";
3998 return \"f%$sqrt%.s %1,%0\";
4001 (define_insn "sqrtdf2"
4002 [(set (match_operand:DF 0 "general_operand" "=f")
4003 (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
4007 if (FP_REG_P (operands[1]))
4008 return \"f%&sqrt%.x %1,%0\";
4010 return \"f%&sqrt%.d %1,%0\";
4013 ;; Absolute value instructions
4014 ;; If using software floating point, just zero the sign bit.
4016 (define_expand "abssf2"
4017 [(set (match_operand:SF 0 "general_operand" "")
4018 (abs:SF (match_operand:SF 1 "general_operand" "")))]
4022 if (!TARGET_FPA && !TARGET_68881)
4027 target = operand_subword_force (operands[0], 0, SFmode);
4028 result = expand_binop (SImode, and_optab,
4029 operand_subword_force (operands[1], 0, SFmode),
4030 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
4034 if (result != target)
4035 emit_move_insn (result, target);
4037 /* Make a place for REG_EQUAL. */
4038 emit_move_insn (operands[0], operands[0]);
4044 [(set (match_operand:SF 0 "general_operand" "=x,y")
4045 (abs:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4050 [(set (match_operand:SF 0 "general_operand" "=f")
4051 (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
4055 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4056 return \"f%$abs%.x %1,%0\";
4057 return \"f%$abs%.s %f1,%0\";
4060 (define_expand "absdf2"
4061 [(set (match_operand:DF 0 "general_operand" "")
4062 (abs:DF (match_operand:DF 1 "general_operand" "")))]
4066 if (!TARGET_FPA && !TARGET_68881)
4073 target = operand_subword (operands[0], 0, 1, DFmode);
4074 result = expand_binop (SImode, and_optab,
4075 operand_subword_force (operands[1], 0, DFmode),
4076 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
4080 if (result != target)
4081 emit_move_insn (result, target);
4083 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4084 operand_subword_force (operands[1], 1, DFmode));
4086 insns = get_insns ();
4089 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4095 [(set (match_operand:DF 0 "general_operand" "=x,y")
4096 (abs:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4101 [(set (match_operand:DF 0 "general_operand" "=f")
4102 (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
4106 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4107 return \"f%&abs%.x %1,%0\";
4108 return \"f%&abs%.d %f1,%0\";
4111 ;; one complement instructions
4113 ;; "one_cmpldi2" is only here to help combine().
4114 (define_insn "one_cmpldi2"
4115 [(set (match_operand:DI 0 "general_operand" "=dm")
4116 (not:DI (match_operand:DI 1 "general_operand" "0")))]
4121 if (GET_CODE (operands[0]) == REG)
4122 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4123 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
4124 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4125 operands[1] = operands[0];
4127 operands[1] = adj_offsettable_operand (operands[0], 4);
4128 return \"not%.l %1\;not%.l %0\";
4131 (define_expand "one_cmplsi2"
4132 [(set (match_operand:SI 0 "general_operand" "")
4133 (not:SI (match_operand:SI 1 "general_operand" "")))]
4138 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
4140 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
4144 (define_insn "one_cmplsi2_internal"
4145 [(set (match_operand:SI 0 "general_operand" "=dm")
4146 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4150 (define_insn "one_cmplsi2_5200"
4151 [(set (match_operand:SI 0 "general_operand" "=d")
4152 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4156 (define_insn "one_cmplhi2"
4157 [(set (match_operand:HI 0 "general_operand" "=dm")
4158 (not:HI (match_operand:HI 1 "general_operand" "0")))]
4163 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4164 (not:HI (match_dup 0)))]
4168 (define_insn "one_cmplqi2"
4169 [(set (match_operand:QI 0 "general_operand" "=dm")
4170 (not:QI (match_operand:QI 1 "general_operand" "0")))]
4175 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4176 (not:QI (match_dup 0)))]
4180 ;; arithmetic shift instructions
4181 ;; We don't need the shift memory by 1 bit instruction
4183 (define_insn "ashldi_extsi"
4184 [(set (match_operand:DI 0 "general_operand" "=ro")
4186 (match_operator:DI 2 "extend_operator"
4187 [(match_operand:SI 1 "general_operand" "rm")])
4193 if (GET_CODE (operands[0]) == REG)
4194 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4196 operands[2] = adj_offsettable_operand (operands[0], 4);
4197 if (ADDRESS_REG_P (operands[0]))
4198 return \"move%.l %1,%0\;sub%.l %2,%2\";
4200 return \"move%.l %1,%0\;clr%.l %2\";
4203 (define_insn "ashldi_sexthi"
4204 [(set (match_operand:DI 0 "general_operand" "=m,a*d")
4205 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
4207 (clobber (match_scratch:SI 2 "=a,X"))]
4212 if (GET_CODE (operands[0]) == MEM)
4214 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4215 return \"clr%.l %0\;move%.w %1,%2\;move%.l %2,%0\";
4216 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4217 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %0\";
4220 operands[3] = adj_offsettable_operand (operands[0], 4);
4221 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %3\";
4224 else if (DATA_REG_P (operands[0]))
4225 return \"move%.w %1,%0\;ext%.l %0\;clr%.l %R0\";
4227 return \"move%.w %1,%0\;sub%.l %R0,%R0\";
4230 (define_insn "ashldi_const32"
4231 [(set (match_operand:DI 0 "general_operand" "=rm")
4232 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
4238 if (GET_CODE (operands[1]) == REG)
4239 operands[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4241 operands[3] = adj_offsettable_operand (operands[1], 4);
4242 if (GET_CODE (operands[0]) == REG)
4243 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4244 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4245 return \"clr%.l %0\;move%.l %3,%0\";
4246 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4247 return \"move%.l %3,%0\;clr%.l %0\";
4249 operands[2] = adj_offsettable_operand (operands[0], 4);
4250 if (ADDRESS_REG_P (operands[2]))
4251 return \"move%.l %3,%0\;sub%.l %2,%2\";
4253 return \"move%.l %3,%0\;clr%.l %2\";
4256 ;; The predicate below must be general_operand, because ashldi3 allows that
4257 (define_insn "ashldi_const"
4258 [(set (match_operand:DI 0 "general_operand" "=d")
4259 (ashift:DI (match_operand:DI 1 "general_operand" "0")
4260 (match_operand 2 "const_int_operand" "n")))]
4261 "(INTVAL (operands[2]) == 1
4262 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4263 || INTVAL (operands[2]) == 2 || INTVAL (operands[2]) == 3)"
4266 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4267 if (INTVAL (operands[2]) == 1)
4268 return \"add%.l %1,%1\;addx%.l %0,%0\";
4269 else if (INTVAL (operands[2]) == 8)
4270 return \"rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1\";
4271 else if (INTVAL (operands[2]) == 16)
4272 return \"swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1\";
4273 else if (INTVAL (operands[2]) == 2)
4274 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4275 else/* if (INTVAL (operands[2]) == 3)*/
4276 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4279 (define_expand "ashldi3"
4280 [(set (match_operand:DI 0 "general_operand" "")
4281 (ashift:DI (match_operand:DI 1 "general_operand" "")
4282 (match_operand 2 "const_int_operand" "")))]
4286 if (GET_CODE (operands[2]) != CONST_INT
4287 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 32
4288 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4289 && INTVAL (operands[2]) != 2 && INTVAL (operands[2]) != 3))
4293 ;; On most 68k models, this makes faster code in a special case.
4295 (define_insn "ashlsi_16"
4296 [(set (match_operand:SI 0 "register_operand" "=d")
4297 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4303 return \"swap %0\;clr%.w %0\";
4306 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
4307 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
4309 ;; On the 68000, this makes faster code in a special case.
4311 (define_insn "ashlsi_17_24"
4312 [(set (match_operand:SI 0 "register_operand" "=d")
4313 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4314 (match_operand:SI 2 "const_int_operand" "n")))]
4315 "(! TARGET_68020 && !TARGET_5200
4316 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4321 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4322 return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\";
4325 (define_insn "ashlsi3"
4326 [(set (match_operand:SI 0 "register_operand" "=d")
4327 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4328 (match_operand:SI 2 "general_operand" "dI")))]
4332 if (operands[2] == const1_rtx)
4334 cc_status.flags = CC_NO_OVERFLOW;
4335 return \"add%.l %0,%0\";
4337 return \"lsl%.l %2,%0\";
4340 (define_insn "ashlhi3"
4341 [(set (match_operand:HI 0 "register_operand" "=d")
4342 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4343 (match_operand:HI 2 "general_operand" "dI")))]
4348 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4349 (ashift:HI (match_dup 0)
4350 (match_operand:HI 1 "general_operand" "dI")))]
4354 (define_insn "ashlqi3"
4355 [(set (match_operand:QI 0 "register_operand" "=d")
4356 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4357 (match_operand:QI 2 "general_operand" "dI")))]
4362 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4363 (ashift:QI (match_dup 0)
4364 (match_operand:QI 1 "general_operand" "dI")))]
4368 ;; On most 68k models, this makes faster code in a special case.
4370 (define_insn "ashrsi_16"
4371 [(set (match_operand:SI 0 "register_operand" "=d")
4372 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4375 "swap %0\;ext%.l %0")
4377 ;; On the 68000, this makes faster code in a special case.
4380 [(set (match_operand:SI 0 "register_operand" "=d")
4381 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4382 (match_operand:SI 2 "const_int_operand" "n")))]
4383 "(! TARGET_68020 && !TARGET_5200
4384 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4387 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4388 return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
4391 (define_insn "subreghi1ashrdi_const32"
4392 [(set (match_operand:HI 0 "general_operand" "=rm")
4393 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4394 (const_int 32)) 1))]
4398 if (GET_CODE (operands[1]) != REG)
4399 operands[1] = adj_offsettable_operand (operands[1], 2);
4400 return \"move%.w %1,%0\";
4403 (define_insn "subregsi1ashrdi_const32"
4404 [(set (match_operand:SI 0 "general_operand" "=rm")
4405 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4406 (const_int 32)) 1))]
4410 return \"move%.l %1,%0\";
4413 (define_insn "ashrdi_const32"
4414 [(set (match_operand:DI 0 "register_operand" "=d")
4415 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4421 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4423 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
4425 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
4428 (define_insn "ashrdi_const32_mem"
4429 [(set (match_operand:DI 0 "general_operand" "=o,<")
4430 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro")
4432 (clobber (match_scratch:SI 2 "=d,d"))]
4437 if (which_alternative == 1)
4438 operands[3] = operands[0];
4440 operands[3] = adj_offsettable_operand (operands[0], 4);
4442 return \"move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0\";
4444 return \"move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\";
4447 ;; The predicate below must be general_operand, because ashrdi3 allows that
4448 (define_insn "ashrdi_const"
4449 [(set (match_operand:DI 0 "general_operand" "=d")
4450 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
4451 (match_operand 2 "const_int_operand" "n")))]
4453 && ((INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == 2
4454 || INTVAL (operands[2]) == 3 || INTVAL (operands[2]) == 8
4455 || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 31
4456 || INTVAL (operands[2]) == 63))"
4459 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4460 if (INTVAL (operands[2]) == 63)
4461 return \"add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1\";
4463 if (INTVAL (operands[2]) == 1)
4464 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
4465 else if (INTVAL (operands[2]) == 8)
4466 return \"move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1\";
4467 else if (INTVAL (operands[2]) == 16)
4468 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;ext%.l %0\";
4469 else if (INTVAL (operands[2]) == 31)
4470 return \"add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0\";
4471 else if (INTVAL (operands[2]) == 2)
4472 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4473 else/* if (INTVAL (operands[2]) == 3)*/
4474 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4477 (define_expand "ashrdi3"
4478 [(set (match_operand:DI 0 "general_operand" "")
4479 (ashiftrt:DI (match_operand:DI 1 "general_operand" "")
4480 (match_operand 2 "const_int_operand" "")))]
4484 if (GET_CODE (operands[2]) != CONST_INT
4485 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 2
4486 && INTVAL (operands[2]) != 3 && INTVAL (operands[2]) != 8
4487 && INTVAL (operands[2]) != 16 && INTVAL (operands[2]) != 31
4488 && INTVAL (operands[2]) != 32 && INTVAL (operands[2]) != 63))
4492 ;; On all 68k models, this makes faster code in a special case.
4494 (define_insn "ashrsi_31"
4495 [(set (match_operand:SI 0 "register_operand" "=d")
4496 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4501 return \"add%.l %0,%0\;subx%.l %0,%0\";
4504 (define_insn "ashrsi3"
4505 [(set (match_operand:SI 0 "register_operand" "=d")
4506 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4507 (match_operand:SI 2 "general_operand" "dI")))]
4511 (define_insn "ashrhi3"
4512 [(set (match_operand:HI 0 "register_operand" "=d")
4513 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4514 (match_operand:HI 2 "general_operand" "dI")))]
4519 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4520 (ashiftrt:HI (match_dup 0)
4521 (match_operand:HI 1 "general_operand" "dI")))]
4525 (define_insn "ashrqi3"
4526 [(set (match_operand:QI 0 "register_operand" "=d")
4527 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4528 (match_operand:QI 2 "general_operand" "dI")))]
4533 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4534 (ashiftrt:QI (match_dup 0)
4535 (match_operand:QI 1 "general_operand" "dI")))]
4539 ;; logical shift instructions
4541 ;; commented out because of reload problems in 950612-1.c
4544 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4545 ;; (const_int 32)) 1))
4546 ;; (set (match_operand:SI 1 "general_operand" "=dm")
4547 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
4548 ;; (const_int 32)) 1))]
4552 ;; return \"move%.l %0,%1\";
4557 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4558 ;; (const_int 32)) 0))
4559 ;; (set (match_operand:DI 1 "general_operand" "=do")
4560 ;; (lshiftrt:DI (match_dup 0)
4561 ;; (const_int 32)))]
4565 ;; if (GET_CODE (operands[1]) == REG)
4566 ;; operands[2] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4568 ;; operands[2] = adj_offsettable_operand (operands[1], 4);
4569 ;; return \"move%.l %0,%2\;clr%.l %1\";
4572 (define_insn "subreg1lshrdi_const32"
4573 [(set (match_operand:SI 0 "general_operand" "=rm")
4574 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4575 (const_int 32)) 1))]
4579 return \"move%.l %1,%0\";
4582 (define_insn "lshrdi_const32"
4583 [(set (match_operand:DI 0 "general_operand" "=ro,<,>")
4584 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
4590 if (which_alternative == 1)
4591 return \"move%.l %1,%0\;clr%.l %0\";
4592 if (which_alternative == 2)
4593 return \"clr%.l %0\;move%.l %1,%0\";
4594 if (GET_CODE (operands[0]) == REG)
4595 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4597 operands[2] = adj_offsettable_operand (operands[0], 4);
4598 if (GET_CODE (operands[1]) == REG)
4599 operands[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4601 operands[3] = adj_offsettable_operand (operands[1], 4);
4602 if (ADDRESS_REG_P (operands[0]))
4603 return \"move%.l %1,%2\;sub%.l %0,%0\";
4605 return \"move%.l %1,%2\;clr%.l %0\";
4608 ;; The predicate below must be general_operand, because lshrdi3 allows that
4609 (define_insn "lshrdi_const"
4610 [(set (match_operand:DI 0 "general_operand" "=d")
4611 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
4612 (match_operand 2 "const_int_operand" "n")))]
4614 && ((INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == 2
4615 || INTVAL (operands[2]) == 3 || INTVAL (operands[2]) == 8
4616 || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 63))"
4619 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4620 if (INTVAL (operands[2]) == 63)
4621 return \"add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1\";
4623 if (INTVAL (operands[2]) == 1)
4624 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4625 else if (INTVAL (operands[2]) == 8)
4626 return \"move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1\";
4627 else if (INTVAL (operands[2]) == 16)
4628 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0\";
4629 else if (INTVAL (operands[2]) == 2)
4630 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4631 else /*if (INTVAL (operands[2]) == 3)*/
4632 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4635 (define_expand "lshrdi3"
4636 [(set (match_operand:DI 0 "general_operand" "")
4637 (lshiftrt:DI (match_operand:DI 1 "general_operand" "")
4638 (match_operand 2 "const_int_operand" "")))]
4642 if (GET_CODE (operands[2]) != CONST_INT
4643 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 2
4644 && INTVAL (operands[2]) != 3 && INTVAL (operands[2]) != 8
4645 && INTVAL (operands[2]) != 16 && INTVAL (operands[2]) != 32
4646 && INTVAL (operands[2]) != 63))
4650 ;; On all 68k models, this makes faster code in a special case.
4652 (define_insn "lshrsi_31"
4653 [(set (match_operand:SI 0 "register_operand" "=d")
4654 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4659 return \"add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0\";
4662 ;; On most 68k models, this makes faster code in a special case.
4664 (define_insn "lshrsi_16"
4665 [(set (match_operand:SI 0 "register_operand" "=d")
4666 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4672 return \"clr%.w %0\;swap %0\";
4675 ;; On the 68000, this makes faster code in a special case.
4677 (define_insn "lshrsi_17_24"
4678 [(set (match_operand:SI 0 "register_operand" "=d")
4679 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4680 (match_operand:SI 2 "const_int_operand" "n")))]
4681 "(! TARGET_68020 && !TARGET_5200
4682 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4685 /* I think lsr%.w sets the CC properly. */
4686 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4687 return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\";
4690 (define_insn "lshrsi3"
4691 [(set (match_operand:SI 0 "register_operand" "=d")
4692 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4693 (match_operand:SI 2 "general_operand" "dI")))]
4697 (define_insn "lshrhi3"
4698 [(set (match_operand:HI 0 "register_operand" "=d")
4699 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
4700 (match_operand:HI 2 "general_operand" "dI")))]
4705 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4706 (lshiftrt:HI (match_dup 0)
4707 (match_operand:HI 1 "general_operand" "dI")))]
4711 (define_insn "lshrqi3"
4712 [(set (match_operand:QI 0 "register_operand" "=d")
4713 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
4714 (match_operand:QI 2 "general_operand" "dI")))]
4719 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4720 (lshiftrt:QI (match_dup 0)
4721 (match_operand:QI 1 "general_operand" "dI")))]
4725 ;; rotate instructions
4727 (define_insn "rotlsi3"
4728 [(set (match_operand:SI 0 "register_operand" "=d")
4729 (rotate:SI (match_operand:SI 1 "register_operand" "0")
4730 (match_operand:SI 2 "general_operand" "dINO")))]
4734 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
4736 else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
4738 INTVAL (operands[2]) = 32 - INTVAL (operands[2]);
4739 return \"ror%.l %2,%0\";
4742 return \"rol%.l %2,%0\";
4745 (define_insn "rotlhi3"
4746 [(set (match_operand:HI 0 "register_operand" "=d")
4747 (rotate:HI (match_operand:HI 1 "register_operand" "0")
4748 (match_operand:HI 2 "general_operand" "dIP")))]
4752 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
4754 INTVAL (operands[2]) = 16 - INTVAL (operands[2]);
4755 return \"ror%.w %2,%0\";
4758 return \"rol%.w %2,%0\";
4762 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4763 (rotate:HI (match_dup 0)
4764 (match_operand:HI 1 "general_operand" "dIP")))]
4768 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
4770 INTVAL (operands[2]) = 16 - INTVAL (operands[2]);
4771 return \"ror%.w %2,%0\";
4774 return \"rol%.w %2,%0\";
4777 (define_insn "rotlqi3"
4778 [(set (match_operand:QI 0 "register_operand" "=d")
4779 (rotate:QI (match_operand:QI 1 "register_operand" "0")
4780 (match_operand:QI 2 "general_operand" "dI")))]
4784 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
4786 INTVAL (operands[2]) = 8 - INTVAL (operands[2]);
4787 return \"ror%.b %2,%0\";
4790 return \"rol%.b %2,%0\";
4794 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4795 (rotate:QI (match_dup 0)
4796 (match_operand:QI 1 "general_operand" "dI")))]
4800 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
4802 INTVAL (operands[2]) = 8 - INTVAL (operands[2]);
4803 return \"ror%.b %2,%0\";
4806 return \"rol%.b %2,%0\";
4809 (define_insn "rotrsi3"
4810 [(set (match_operand:SI 0 "register_operand" "=d")
4811 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
4812 (match_operand:SI 2 "general_operand" "dI")))]
4816 (define_insn "rotrhi3"
4817 [(set (match_operand:HI 0 "register_operand" "=d")
4818 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
4819 (match_operand:HI 2 "general_operand" "dI")))]
4824 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4825 (rotatert:HI (match_dup 0)
4826 (match_operand:HI 1 "general_operand" "dI")))]
4830 (define_insn "rotrqi3"
4831 [(set (match_operand:QI 0 "register_operand" "=d")
4832 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
4833 (match_operand:QI 2 "general_operand" "dI")))]
4838 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4839 (rotatert:QI (match_dup 0)
4840 (match_operand:QI 1 "general_operand" "dI")))]
4845 ;; Bit set/clear in memory byte.
4847 ;; set bit, bit number is int
4848 (define_insn "bsetmemqi"
4849 [(set (match_operand:QI 0 "memory_operand" "+m")
4850 (ior:QI (subreg:QI (ashift:SI (const_int 1)
4851 (match_operand:SI 1 "general_operand" "d")) 0)
4857 return \"bset %1,%0\";
4860 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
4862 [(set (match_operand:QI 0 "memory_operand" "+m")
4863 (ior:QI (subreg:QI (ashift:SI (const_int 1)
4864 (match_operator:SI 2 "extend_operator"
4865 [(match_operand 1 "general_operand" "d")])) 0)
4871 return \"bset %1,%0\";
4874 ;; clear bit, bit number is int
4875 (define_insn "bclrmemqi"
4876 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
4878 (minus:SI (const_int 7)
4879 (match_operand:SI 1 "general_operand" "d")))
4885 return \"bclr %1,%0\";
4888 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
4890 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
4892 (minus:SI (const_int 7)
4893 (match_operator:SI 2 "extend_operator"
4894 [(match_operand 1 "general_operand" "d")])))
4900 return \"bclr %1,%0\";
4903 ;; Special cases of bit-field insns which we should
4904 ;; recognize in preference to the general case.
4905 ;; These handle aligned 8-bit and 16-bit fields,
4906 ;; which can usually be done with move instructions.
4909 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4910 ; alignment of structure members is specified.
4912 ; The move is allowed to be odd byte aligned, because that's still faster
4913 ; than an odd byte aligned bit field instruction.
4916 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
4918 (match_operand:SI 2 "const_int_operand" "n"))
4919 (match_operand:SI 3 "general_operand" "rmi"))]
4920 "TARGET_68020 && TARGET_BITFIELD
4921 && (INTVAL (operands[2]) % 8) == 0
4922 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
4926 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
4928 return \"move%.l %3,%0\";
4932 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
4933 (match_operand:SI 1 "const_int_operand" "n")
4934 (match_operand:SI 2 "const_int_operand" "n"))
4935 (match_operand:SI 3 "register_operand" "d"))]
4936 "TARGET_68020 && TARGET_BITFIELD
4937 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
4938 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
4939 && (GET_CODE (operands[0]) == REG
4940 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
4943 if (REG_P (operands[0]))
4945 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
4946 return \"bfins %3,%0{%b2:%b1}\";
4950 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
4952 if (GET_CODE (operands[3]) == MEM)
4953 operands[3] = adj_offsettable_operand (operands[3],
4954 (32 - INTVAL (operands[1])) / 8);
4955 if (INTVAL (operands[1]) == 8)
4956 return \"move%.b %3,%0\";
4957 return \"move%.w %3,%0\";
4962 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4963 ; alignment of structure members is specified.
4965 ; The move is allowed to be odd byte aligned, because that's still faster
4966 ; than an odd byte aligned bit field instruction.
4969 [(set (match_operand:SI 0 "general_operand" "=rm")
4970 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o")
4972 (match_operand:SI 3 "const_int_operand" "n")))]
4973 "TARGET_68020 && TARGET_BITFIELD
4974 && (INTVAL (operands[3]) % 8) == 0
4975 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
4979 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
4981 return \"move%.l %1,%0\";
4985 [(set (match_operand:SI 0 "general_operand" "=&d")
4986 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
4987 (match_operand:SI 2 "const_int_operand" "n")
4988 (match_operand:SI 3 "const_int_operand" "n")))]
4989 "TARGET_68020 && TARGET_BITFIELD
4990 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
4991 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
4992 && (GET_CODE (operands[1]) == REG
4993 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
4996 cc_status.flags |= CC_NOT_NEGATIVE;
4997 if (REG_P (operands[1]))
4999 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5000 return \"bfextu %1{%b3:%b2},%0\";
5004 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5006 output_asm_insn (\"clr%.l %0\", operands);
5007 if (GET_CODE (operands[0]) == MEM)
5008 operands[0] = adj_offsettable_operand (operands[0],
5009 (32 - INTVAL (operands[1])) / 8);
5010 if (INTVAL (operands[2]) == 8)
5011 return \"move%.b %1,%0\";
5012 return \"move%.w %1,%0\";
5016 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5017 ; alignment of structure members is specified.
5019 ; The move is allowed to be odd byte aligned, because that's still faster
5020 ; than an odd byte aligned bit field instruction.
5023 [(set (match_operand:SI 0 "general_operand" "=rm")
5024 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5026 (match_operand:SI 3 "const_int_operand" "n")))]
5027 "TARGET_68020 && TARGET_BITFIELD
5028 && (INTVAL (operands[3]) % 8) == 0
5029 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5033 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5035 return \"move%.l %1,%0\";
5039 [(set (match_operand:SI 0 "general_operand" "=d")
5040 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
5041 (match_operand:SI 2 "const_int_operand" "n")
5042 (match_operand:SI 3 "const_int_operand" "n")))]
5043 "TARGET_68020 && TARGET_BITFIELD
5044 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5045 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5046 && (GET_CODE (operands[1]) == REG
5047 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5050 if (REG_P (operands[1]))
5052 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5053 return \"bfexts %1{%b3:%b2},%0\";
5057 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5059 if (INTVAL (operands[2]) == 8)
5060 return \"move%.b %1,%0\;extb%.l %0\";
5061 return \"move%.w %1,%0\;ext%.l %0\";
5064 ;; Bit field instructions, general cases.
5065 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
5066 ;; so that its address is reloaded.
5068 (define_expand "extv"
5069 [(set (match_operand:SI 0 "general_operand" "")
5070 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
5071 (match_operand:SI 2 "general_operand" "")
5072 (match_operand:SI 3 "general_operand" "")))]
5073 "TARGET_68020 && TARGET_BITFIELD"
5077 [(set (match_operand:SI 0 "general_operand" "=d")
5078 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5079 (match_operand:SI 2 "general_operand" "di")
5080 (match_operand:SI 3 "general_operand" "di")))]
5081 "TARGET_68020 && TARGET_BITFIELD"
5082 "bfexts %1{%b3:%b2},%0")
5084 (define_expand "extzv"
5085 [(set (match_operand:SI 0 "general_operand" "")
5086 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
5087 (match_operand:SI 2 "general_operand" "")
5088 (match_operand:SI 3 "general_operand" "")))]
5089 "TARGET_68020 && TARGET_BITFIELD"
5093 [(set (match_operand:SI 0 "general_operand" "=d,d")
5094 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
5095 (match_operand:SI 2 "general_operand" "di,di")
5096 (match_operand:SI 3 "general_operand" "di,di")))]
5097 "TARGET_68020 && TARGET_BITFIELD"
5100 if (GET_CODE (operands[2]) == CONST_INT)
5102 if (INTVAL (operands[2]) != 32)
5103 cc_status.flags |= CC_NOT_NEGATIVE;
5109 return \"bfextu %1{%b3:%b2},%0\";
5113 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5114 (match_operand:SI 1 "general_operand" "di")
5115 (match_operand:SI 2 "general_operand" "di"))
5116 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
5117 (match_operand 3 "const_int_operand" "n")))]
5118 "TARGET_68020 && TARGET_BITFIELD
5119 && (INTVAL (operands[3]) == -1
5120 || (GET_CODE (operands[1]) == CONST_INT
5121 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
5125 return \"bfchg %0{%b2:%b1}\";
5129 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5130 (match_operand:SI 1 "general_operand" "di")
5131 (match_operand:SI 2 "general_operand" "di"))
5133 "TARGET_68020 && TARGET_BITFIELD"
5137 return \"bfclr %0{%b2:%b1}\";
5141 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5142 (match_operand:SI 1 "general_operand" "di")
5143 (match_operand:SI 2 "general_operand" "di"))
5145 "TARGET_68020 && TARGET_BITFIELD"
5149 return \"bfset %0{%b2:%b1}\";
5152 (define_expand "insv"
5153 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
5154 (match_operand:SI 1 "general_operand" "")
5155 (match_operand:SI 2 "general_operand" ""))
5156 (match_operand:SI 3 "register_operand" ""))]
5157 "TARGET_68020 && TARGET_BITFIELD"
5161 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5162 (match_operand:SI 1 "general_operand" "di")
5163 (match_operand:SI 2 "general_operand" "di"))
5164 (match_operand:SI 3 "register_operand" "d"))]
5165 "TARGET_68020 && TARGET_BITFIELD"
5166 "bfins %3,%0{%b2:%b1}")
5168 ;; Now recognize bit field insns that operate on registers
5169 ;; (or at least were intended to do so).
5172 [(set (match_operand:SI 0 "general_operand" "=d")
5173 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5174 (match_operand:SI 2 "general_operand" "di")
5175 (match_operand:SI 3 "general_operand" "di")))]
5176 "TARGET_68020 && TARGET_BITFIELD"
5177 "bfexts %1{%b3:%b2},%0")
5180 [(set (match_operand:SI 0 "general_operand" "=d")
5181 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5182 (match_operand:SI 2 "general_operand" "di")
5183 (match_operand:SI 3 "general_operand" "di")))]
5184 "TARGET_68020 && TARGET_BITFIELD"
5187 if (GET_CODE (operands[2]) == CONST_INT)
5189 if (INTVAL (operands[2]) != 32)
5190 cc_status.flags |= CC_NOT_NEGATIVE;
5196 return \"bfextu %1{%b3:%b2},%0\";
5200 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5201 (match_operand:SI 1 "general_operand" "di")
5202 (match_operand:SI 2 "general_operand" "di"))
5204 "TARGET_68020 && TARGET_BITFIELD"
5208 return \"bfclr %0{%b2:%b1}\";
5212 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5213 (match_operand:SI 1 "general_operand" "di")
5214 (match_operand:SI 2 "general_operand" "di"))
5216 "TARGET_68020 && TARGET_BITFIELD"
5220 return \"bfset %0{%b2:%b1}\";
5224 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5225 (match_operand:SI 1 "general_operand" "di")
5226 (match_operand:SI 2 "general_operand" "di"))
5227 (match_operand:SI 3 "register_operand" "d"))]
5228 "TARGET_68020 && TARGET_BITFIELD"
5232 /* These special cases are now recognized by a specific pattern. */
5233 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5234 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5235 return \"move%.w %3,%0\";
5236 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5237 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
5238 return \"move%.b %3,%0\";
5240 return \"bfins %3,%0{%b2:%b1}\";
5243 ;; Special patterns for optimizing bit-field instructions.
5247 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5248 (match_operand:SI 1 "const_int_operand" "n")
5249 (match_operand:SI 2 "general_operand" "di")))]
5250 "TARGET_68020 && TARGET_BITFIELD"
5253 if (operands[1] == const1_rtx
5254 && GET_CODE (operands[2]) == CONST_INT)
5256 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5257 return output_btst (operands,
5258 gen_rtx (CONST_INT, VOIDmode,
5259 width - INTVAL (operands[2])),
5262 /* Pass 1000 as SIGNPOS argument so that btst will
5263 not think we are testing the sign bit for an `and'
5264 and assume that nonzero implies a negative result. */
5266 if (INTVAL (operands[1]) != 32)
5267 cc_status.flags = CC_NOT_NEGATIVE;
5268 return \"bftst %0{%b2:%b1}\";
5272 ;;; now handle the register cases
5275 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5276 (match_operand:SI 1 "const_int_operand" "n")
5277 (match_operand:SI 2 "general_operand" "di")))]
5278 "TARGET_68020 && TARGET_BITFIELD"
5281 if (operands[1] == const1_rtx
5282 && GET_CODE (operands[2]) == CONST_INT)
5284 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5285 return output_btst (operands,
5286 gen_rtx (CONST_INT, VOIDmode,
5287 width - INTVAL (operands[2])),
5290 /* Pass 1000 as SIGNPOS argument so that btst will
5291 not think we are testing the sign bit for an `and'
5292 and assume that nonzero implies a negative result. */
5294 if (INTVAL (operands[1]) != 32)
5295 cc_status.flags = CC_NOT_NEGATIVE;
5296 return \"bftst %0{%b2:%b1}\";
5299 (define_insn "scc0_di"
5300 [(set (match_operand:QI 0 "general_operand" "=dm")
5301 (match_operator 1 "valid_dbcc_comparison_p"
5302 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5306 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5309 (define_insn "scc_di"
5310 [(set (match_operand:QI 0 "general_operand" "=dm,dm")
5311 (match_operator 1 "valid_dbcc_comparison_p"
5312 [(match_operand:DI 2 "general_operand" "ro,r")
5313 (match_operand:DI 3 "general_operand" "r,ro")]))]
5317 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5320 (define_expand "seq"
5321 [(set (match_operand:QI 0 "general_operand" "")
5322 (eq:QI (cc0) (const_int 0)))]
5326 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5328 m68k_last_compare_had_fp_operands = 0;
5334 [(set (match_operand:QI 0 "general_operand" "=dm")
5335 (eq:QI (cc0) (const_int 0)))]
5338 cc_status = cc_prev_status;
5339 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5342 (define_expand "sne"
5343 [(set (match_operand:QI 0 "general_operand" "")
5344 (ne:QI (cc0) (const_int 0)))]
5348 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5350 m68k_last_compare_had_fp_operands = 0;
5356 [(set (match_operand:QI 0 "general_operand" "=dm")
5357 (ne:QI (cc0) (const_int 0)))]
5360 cc_status = cc_prev_status;
5361 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5364 (define_expand "sgt"
5365 [(set (match_operand:QI 0 "general_operand" "")
5366 (gt:QI (cc0) (const_int 0)))]
5370 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5372 m68k_last_compare_had_fp_operands = 0;
5378 [(set (match_operand:QI 0 "general_operand" "=dm")
5379 (gt:QI (cc0) (const_int 0)))]
5382 cc_status = cc_prev_status;
5383 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5387 [(set (match_operand:QI 0 "general_operand" "=dm")
5388 (gtu:QI (cc0) (const_int 0)))]
5390 "* cc_status = cc_prev_status;
5391 return \"shi %0\"; ")
5393 (define_expand "slt"
5394 [(set (match_operand:QI 0 "general_operand" "")
5395 (lt:QI (cc0) (const_int 0)))]
5399 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5401 m68k_last_compare_had_fp_operands = 0;
5407 [(set (match_operand:QI 0 "general_operand" "=dm")
5408 (lt:QI (cc0) (const_int 0)))]
5410 "* cc_status = cc_prev_status;
5411 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5414 [(set (match_operand:QI 0 "general_operand" "=dm")
5415 (ltu:QI (cc0) (const_int 0)))]
5417 "* cc_status = cc_prev_status;
5418 return \"scs %0\"; ")
5420 (define_expand "sge"
5421 [(set (match_operand:QI 0 "general_operand" "")
5422 (ge:QI (cc0) (const_int 0)))]
5426 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5428 m68k_last_compare_had_fp_operands = 0;
5434 [(set (match_operand:QI 0 "general_operand" "=dm")
5435 (ge:QI (cc0) (const_int 0)))]
5437 "* cc_status = cc_prev_status;
5438 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5441 [(set (match_operand:QI 0 "general_operand" "=dm")
5442 (geu:QI (cc0) (const_int 0)))]
5444 "* cc_status = cc_prev_status;
5445 return \"scc %0\"; ")
5447 (define_expand "sle"
5448 [(set (match_operand:QI 0 "general_operand" "")
5449 (le:QI (cc0) (const_int 0)))]
5453 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5455 m68k_last_compare_had_fp_operands = 0;
5461 [(set (match_operand:QI 0 "general_operand" "=dm")
5462 (le:QI (cc0) (const_int 0)))]
5465 cc_status = cc_prev_status;
5466 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5470 [(set (match_operand:QI 0 "general_operand" "=dm")
5471 (leu:QI (cc0) (const_int 0)))]
5473 "* cc_status = cc_prev_status;
5474 return \"sls %0\"; ")
5476 ;; Basic conditional jump instructions.
5478 (define_insn "beq0_di"
5480 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
5482 (label_ref (match_operand 1 "" ","))
5484 (clobber (match_scratch:SI 2 "=d,d"))]
5489 if (which_alternative == 1)
5491 return \"move%.l %0,%2\;or%.l %0,%2\;jbeq %l1\";
5493 return \"move%.l %0,%2\;or%.l %0,%2\;jeq %l1\";
5495 if ((cc_prev_status.value1
5496 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5497 || (cc_prev_status.value2
5498 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5500 cc_status = cc_prev_status;
5502 return \"jbeq %l1\";
5507 if (GET_CODE (operands[0]) == REG)
5508 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
5510 operands[3] = adj_offsettable_operand (operands[0], 4);
5511 if (! ADDRESS_REG_P (operands[0]))
5513 return \"move%.l %0,%2\;or%.l %3,%2\;jbeq %l1\";
5515 return \"move%.l %0,%2\;or%.l %3,%2\;jeq %l1\";
5517 operands[4] = gen_label_rtx();
5518 if (TARGET_68020 || TARGET_5200)
5520 output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands);
5522 output_asm_insn (\"tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1\", operands);
5526 #ifdef SGS_CMP_ORDER
5527 output_asm_insn (\"cmp%.w %0,%#0\;jbne %l4\;cmp%.w %3,%#0\;jbeq %l1\", operands);
5529 output_asm_insn (\"cmp%.w %#0,%0\;jbne %l4\;cmp%.w %#0,%3\;jbeq %l1\", operands);
5532 output_asm_insn (\"cmp%.w %#0,%0\;jne %l4\;cmp%.w %#0,%3\;jeq %l1\", operands);
5534 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5535 CODE_LABEL_NUMBER (operands[4]));
5539 (define_insn "bne0_di"
5541 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
5543 (label_ref (match_operand 1 "" ","))
5545 (clobber (match_scratch:SI 2 "=d,X"))]
5549 if ((cc_prev_status.value1
5550 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5551 || (cc_prev_status.value2
5552 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5554 cc_status = cc_prev_status;
5556 return \"jbne %l1\";
5562 if (GET_CODE (operands[0]) == REG)
5563 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
5565 operands[3] = adj_offsettable_operand (operands[0], 4);
5566 if (!ADDRESS_REG_P (operands[0]))
5568 return \"move%.l %0,%2\;or%.l %3,%2\;jbne %l1\";
5570 return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\";
5572 if (TARGET_68020 || TARGET_5200)
5574 return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\";
5576 return \"tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1\";
5580 #ifdef SGS_CMP_ORDER
5581 return \"cmp%.w %#0,%0\;jbne %l1\;cmp%.w %#0,%3\;jbne %l1\";
5583 return \"cmp%.w %0,%#0\;jbne %l1\;cmp%.w %3,%#0\;jbne %l1\";
5586 return \"cmp%.w %#0,%0\;jne %l1\;cmp%.w %#0,%3\;jne %l1\";
5590 (define_insn "bge0_di"
5592 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
5594 (label_ref (match_operand 1 "" ""))
5599 if ((cc_prev_status.value1
5600 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5601 || (cc_prev_status.value2
5602 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5604 cc_status = cc_prev_status;
5605 if (cc_status.flags & CC_REVERSED)
5608 return \"jble %l1\";
5616 return \"jbpl %l1\";
5623 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
5624 output_asm_insn(\"tst%.l %0\", operands);
5626 /* On an address reg, cmpw may replace cmpl. */
5627 #ifdef SGS_CMP_ORDER
5628 output_asm_insn(\"cmp%.w %0,%#0\", operands);
5630 output_asm_insn(\"cmp%.w %#0,%0\", operands);
5634 return \"jbpl %l1\";
5640 (define_insn "blt0_di"
5642 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
5644 (label_ref (match_operand 1 "" ""))
5649 if ((cc_prev_status.value1
5650 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5651 || (cc_prev_status.value2
5652 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5654 cc_status = cc_prev_status;
5655 if (cc_status.flags & CC_REVERSED)
5658 return \"jbgt %l1\";
5666 return \"jbmi %l1\";
5673 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
5674 output_asm_insn(\"tst%.l %0\", operands);
5676 /* On an address reg, cmpw may replace cmpl. */
5677 #ifdef SGS_CMP_ORDER
5678 output_asm_insn(\"cmp%.w %0,%#0\", operands);
5680 output_asm_insn(\"cmp%.w %#0,%0\", operands);
5684 return \"jbmi %l1\";
5692 (if_then_else (eq (cc0)
5694 (label_ref (match_operand 0 "" ""))
5700 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
5702 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
5708 (if_then_else (ne (cc0)
5710 (label_ref (match_operand 0 "" ""))
5716 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
5718 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
5724 (if_then_else (gt (cc0)
5726 (label_ref (match_operand 0 "" ""))
5731 OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0);
5733 OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0);
5739 (if_then_else (gtu (cc0)
5741 (label_ref (match_operand 0 "" ""))
5746 return \"jbhi %l0\";
5754 (if_then_else (lt (cc0)
5756 (label_ref (match_operand 0 "" ""))
5761 OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\");
5763 OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\");
5769 (if_then_else (ltu (cc0)
5771 (label_ref (match_operand 0 "" ""))
5776 return \"jbcs %l0\";
5784 (if_then_else (ge (cc0)
5786 (label_ref (match_operand 0 "" ""))
5791 OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\");
5793 OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\");
5799 (if_then_else (geu (cc0)
5801 (label_ref (match_operand 0 "" ""))
5806 return \"jbcc %l0\";
5814 (if_then_else (le (cc0)
5816 (label_ref (match_operand 0 "" ""))
5821 OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0);
5823 OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0);
5829 (if_then_else (leu (cc0)
5831 (label_ref (match_operand 0 "" ""))
5836 return \"jbls %l0\";
5842 ;; Negated conditional jump instructions.
5846 (if_then_else (eq (cc0)
5849 (label_ref (match_operand 0 "" ""))))]
5854 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
5856 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
5862 (if_then_else (ne (cc0)
5865 (label_ref (match_operand 0 "" ""))))]
5870 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
5872 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
5878 (if_then_else (gt (cc0)
5881 (label_ref (match_operand 0 "" ""))))]
5885 OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0);
5887 OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0);
5893 (if_then_else (gtu (cc0)
5896 (label_ref (match_operand 0 "" ""))))]
5900 return \"jbls %l0\";
5908 (if_then_else (lt (cc0)
5911 (label_ref (match_operand 0 "" ""))))]
5915 OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\");
5917 OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\");
5923 (if_then_else (ltu (cc0)
5926 (label_ref (match_operand 0 "" ""))))]
5930 return \"jbcc %l0\";
5938 (if_then_else (ge (cc0)
5941 (label_ref (match_operand 0 "" ""))))]
5945 OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\");
5947 OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\");
5953 (if_then_else (geu (cc0)
5956 (label_ref (match_operand 0 "" ""))))]
5960 return \"jbcs %l0\";
5968 (if_then_else (le (cc0)
5971 (label_ref (match_operand 0 "" ""))))]
5975 OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0);
5977 OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0);
5983 (if_then_else (leu (cc0)
5986 (label_ref (match_operand 0 "" ""))))]
5990 return \"jbhi %l0\";
5996 ;; Unconditional and other jump instructions
5999 (label_ref (match_operand 0 "" "")))]
6003 return \"jbra %l0\";
6009 ;; We support two different ways of handling dispatch tables.
6010 ;; The NeXT uses absolute tables, and other machines use relative.
6011 ;; This define_expand can generate either kind.
6012 (define_expand "tablejump"
6013 [(parallel [(set (pc) (match_operand 0 "" ""))
6014 (use (label_ref (match_operand 1 "" "")))])]
6018 #ifdef CASE_VECTOR_PC_RELATIVE
6019 operands[0] = gen_rtx (PLUS, SImode, pc_rtx,
6020 gen_rtx (SIGN_EXTEND, SImode, operands[0]));
6024 ;; Jump to variable address from dispatch table of absolute addresses.
6026 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
6027 (use (label_ref (match_operand 1 "" "")))]
6031 return \"jmp (%0)\";
6037 ;; Jump to variable address from dispatch table of relative addresses.
6041 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
6042 (use (label_ref (match_operand 1 "" "")))]
6045 #ifdef ASM_RETURN_CASE_JUMP
6046 ASM_RETURN_CASE_JUMP;
6049 #ifdef ASM_OUTPUT_CASE_LABEL
6050 return \"jmp 6(%%pc,%0.w)\";
6053 return \"jmp 2(pc,%0.w)\";
6055 return \"jmp 2(%%pc,%0.w)\";
6056 #endif /* end !CRDS */
6060 return \"jmp (2,pc,%0.w)\";
6062 return \"jmp pc@(2,%0:w)\";
6068 ;; Decrement-and-branch insns.
6072 (ne (match_operand:HI 0 "general_operand" "+d*g")
6074 (label_ref (match_operand 1 "" ""))
6077 (plus:HI (match_dup 0)
6083 if (DATA_REG_P (operands[0]))
6084 return \"dbra %0,%l1\";
6085 if (GET_CODE (operands[0]) == MEM)
6089 return \"sub%.w %#1,%0\;jbcc %l1\";
6091 return \"subq%.w %#1,%0\;jbcc %l1\";
6093 #else /* not MOTOROLA */
6094 return \"subqw %#1,%0\;jcc %l1\";
6098 #ifdef SGS_CMP_ORDER
6100 return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6102 return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6104 #else /* not SGS_CMP_ORDER */
6105 return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
6107 #else /* not MOTOROLA */
6108 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6115 (ne (match_operand:SI 0 "general_operand" "+d*g")
6117 (label_ref (match_operand 1 "" ""))
6120 (plus:SI (match_dup 0)
6128 if (DATA_REG_P (operands[0]))
6129 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6130 if (GET_CODE (operands[0]) == MEM)
6131 return \"sub%.l %#1,%0\;jbcc %l1\";
6133 if (DATA_REG_P (operands[0]))
6134 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6135 if (GET_CODE (operands[0]) == MEM)
6136 return \"subq%.l %#1,%0\;jbcc %l1\";
6137 #endif /* NO_ADDSUB_Q */
6138 #ifdef SGS_CMP_ORDER
6140 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6142 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6144 #else /* not SGS_CMP_ORDER */
6145 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6146 #endif /* not SGS_CMP_ORDER */
6147 #else /* not MOTOROLA */
6148 if (DATA_REG_P (operands[0]))
6149 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6150 if (GET_CODE (operands[0]) == MEM)
6151 return \"subql %#1,%0\;jcc %l1\";
6152 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6153 #endif /* not MOTOROLA */
6156 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
6161 (ge (plus:HI (match_operand:HI 0 "general_operand" "+d*am")
6164 (label_ref (match_operand 1 "" ""))
6167 (plus:HI (match_dup 0)
6169 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6175 if (DATA_REG_P (operands[0]))
6176 return \"dbra %0,%l1\";
6177 if (GET_CODE (operands[0]) == MEM)
6178 return \"sub%.w %#1,%0\;jbcc %l1\";
6180 if (DATA_REG_P (operands[0]))
6181 return \"dbra %0,%l1\";
6182 if (GET_CODE (operands[0]) == MEM)
6183 return \"subq%.w %#1,%0\;jbcc %l1\";
6185 #ifdef SGS_CMP_ORDER
6187 return \"sub.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6189 return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6191 #else /* not SGS_CMP_ORDER */
6192 return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\";
6193 #endif /* not SGS_CMP_ORDER */
6194 #else /* not MOTOROLA */
6195 if (DATA_REG_P (operands[0]))
6196 return \"dbra %0,%l1\";
6197 if (GET_CODE (operands[0]) == MEM)
6198 return \"subqw %#1,%0\;jcc %l1\";
6199 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6200 #endif /* not MOTOROLA */
6203 (define_expand "decrement_and_branch_until_zero"
6204 [(parallel [(set (pc)
6206 (ge (plus:SI (match_operand:SI 0 "general_operand" "")
6209 (label_ref (match_operand 1 "" ""))
6212 (plus:SI (match_dup 0)
6220 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
6223 (label_ref (match_operand 1 "" ""))
6226 (plus:SI (match_dup 0)
6228 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6234 if (DATA_REG_P (operands[0]))
6235 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6236 if (GET_CODE (operands[0]) == MEM)
6237 return \"sub%.l %#1,%0\;jbcc %l1\";
6239 if (DATA_REG_P (operands[0]))
6240 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6241 if (GET_CODE (operands[0]) == MEM)
6242 return \"subq%.l %#1,%0\;jbcc %l1\";
6244 #ifdef SGS_CMP_ORDER
6246 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6248 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6250 #else /* not SGS_CMP_ORDER */
6251 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6252 #endif /* not SGS_CMP_ORDER */
6253 #else /* not MOTOROLA */
6254 if (DATA_REG_P (operands[0]))
6255 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6256 if (GET_CODE (operands[0]) == MEM)
6257 return \"subql %#1,%0\;jcc %l1\";
6258 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6259 #endif /* not MOTOROLA */
6263 ;; For PIC calls, in order to be able to support
6264 ;; dynamic linker LAZY BINDING, all the procedure calls need to go
6265 ;; through the PLT (Procedure Linkage Table) section in PIC mode.
6267 ;; PIC calls are handled by loading the address of the function into a
6268 ;; register (via movsi), then emitting a register indirect call using
6269 ;; the "jsr" function call syntax.
6271 ;; When outputting MIT syntax (e.g. on Suns), we add a bogus extra
6272 ;; operand to the jbsr statement to indicate that this call should
6273 ;; go through the PLT (why? because this is the way that Sun does it).
6275 ;; We have different patterns for PIC calls and non-PIC calls. The
6276 ;; different patterns are only used to choose the right syntax.
6278 ;; The svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it
6279 ;; will create the correct relocation entry (R_68K_PLT32) for `FUNC',
6280 ;; that tells the linker editor to create an entry for `FUNC' in PLT
6281 ;; section at link time. However, all global objects reference are still
6282 ;; done by using `OBJ@GOT'. So, the goal here is to output the function
6283 ;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'.
6284 ;; We need to have a way to differentiate these two different operands.
6286 ;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate
6287 ;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs
6288 ;; to be changed to recognize function calls symbol_ref operand as a valid
6289 ;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will
6290 ;; avoid the compiler to load this symbol_ref operand into a register.
6291 ;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly
6292 ;; since the value is a PC relative offset, not a real address.
6294 ;; All global objects are treated in the similar way as in SUN3. The only
6295 ;; difference is: on m68k svr4, the reference of such global object needs
6296 ;; to end with a suffix "@GOT" so the assembler and linker know to create
6297 ;; an entry for it in GOT (Global Offset Table) section. This is done in
6300 ;; Call subroutine with no return value.
6301 (define_expand "call"
6302 [(call (match_operand:QI 0 "memory_operand" "")
6303 (match_operand:SI 1 "general_operand" ""))]
6304 ;; Operand 1 not really used on the m68000.
6309 if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6310 SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
6313 ;; This is a normal call sequence.
6315 [(call (match_operand:QI 0 "memory_operand" "o")
6316 (match_operand:SI 1 "general_operand" "g"))]
6317 ;; Operand 1 not really used on the m68000.
6321 #if defined (MOTOROLA) && !defined (USE_GAS)
6323 if (GET_CODE (operands[0]) == MEM
6324 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6333 ;; This is a PIC call sequence.
6335 [(call (match_operand:QI 0 "memory_operand" "o")
6336 (match_operand:SI 1 "general_operand" "g"))]
6337 ;; Operand 1 not really used on the m68000.
6341 if (GET_CODE (operands[0]) == MEM
6342 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6345 return \"bsr.l %0\";
6348 return \"bsr.l %0@PLTPC\";
6350 return \"bsr %0@PLTPC\";
6354 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC,
6355 GAS just plain ignores it. */
6356 return \"jbsr %0,a1\";
6361 ;; Call subroutine, returning value in operand 0
6362 ;; (which must be a hard register).
6363 ;; See comments before "call" regarding PIC calls.
6364 (define_expand "call_value"
6365 [(set (match_operand 0 "" "")
6366 (call (match_operand:QI 1 "memory_operand" "")
6367 (match_operand:SI 2 "general_operand" "")))]
6368 ;; Operand 2 not really used on the m68000.
6372 if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6373 SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
6376 ;; This is a normal call_value
6378 [(set (match_operand 0 "" "=rf")
6379 (call (match_operand:QI 1 "memory_operand" "o")
6380 (match_operand:SI 2 "general_operand" "g")))]
6381 ;; Operand 2 not really used on the m68000.
6384 #if defined (MOTOROLA) && !defined (USE_GAS)
6386 if (GET_CODE (operands[1]) == MEM
6387 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6396 ;; This is a PIC call_value
6398 [(set (match_operand 0 "" "=rf")
6399 (call (match_operand:QI 1 "memory_operand" "o")
6400 (match_operand:SI 2 "general_operand" "g")))]
6401 ;; Operand 2 not really used on the m68000.
6404 if (GET_CODE (operands[1]) == MEM
6405 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6408 return \"bsr.l %1\";
6411 return \"bsr.l %1@PLTPC\";
6413 return \"bsr %1@PLTPC\";
6417 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC
6418 GAS just plain ignores it. */
6419 return \"jbsr %1,a1\";
6424 ;; Call subroutine returning any type.
6426 (define_expand "untyped_call"
6427 [(parallel [(call (match_operand 0 "" "")
6429 (match_operand 1 "" "")
6430 (match_operand 2 "" "")])]
6431 "NEEDS_UNTYPED_CALL"
6436 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
6438 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6440 rtx set = XVECEXP (operands[2], 0, i);
6441 emit_move_insn (SET_DEST (set), SET_SRC (set));
6444 /* The optimizer does not know that the call sets the function value
6445 registers we stored in the result block. We avoid problems by
6446 claiming that all hard registers are used and clobbered at this
6448 emit_insn (gen_blockage ());
6453 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6454 ;; all of memory. This blocks insns from being moved across this point.
6456 (define_insn "blockage"
6457 [(unspec_volatile [(const_int 0)] 0)]
6466 (define_insn "probe"
6471 operands[0] = gen_rtx (PLUS, SImode, stack_pointer_rtx,
6472 gen_rtx (CONST_INT, VOIDmode, NEED_PROBE));
6473 return \"tstl %a0\";
6476 ;; Used for frameless functions which save no regs and allocate no locals.
6477 (define_insn "return"
6482 if (current_function_pops_args == 0)
6484 operands[0] = gen_rtx (CONST_INT, VOIDmode, current_function_pops_args);
6488 (define_insn "indirect_jump"
6489 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
6493 ;; This should not be used unless the add/sub insns can't be.
6496 [(set (match_operand:SI 0 "general_operand" "=a")
6497 (match_operand:QI 1 "address_operand" "p"))]
6502 /* Recognize an insn that refers to a table of offsets. Such an insn will
6503 need to refer to a label on the insn. So output one. Use the
6504 label-number of the table of offsets to generate this label. This code,
6505 and similar code above, assumes that there will be at most one reference
6507 if (GET_CODE (operands[1]) == PLUS
6508 && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
6509 && GET_CODE (XEXP (operands[1], 0)) != PLUS)
6511 rtx labelref = XEXP (operands[1], 1);
6512 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
6514 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
6515 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6517 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
6518 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6519 #endif /* not SGS */
6520 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
6521 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
6522 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6523 #ifdef SGS_SWITCH_TABLES
6524 /* Set flag saying we need to define the symbol
6525 LD%n (with value L%n-LI%n) at the end of the switch table. */
6526 switch_table_difference_label_flag = 1;
6527 #endif /* SGS_SWITCH_TABLES */
6528 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
6530 #endif /* SGS_NO_LI */
6532 return \"lea %a1,%0\";
6535 ;; This is the first machine-dependent peephole optimization.
6536 ;; It is useful when a floating value is returned from a function call
6537 ;; and then is moved into an FP register.
6538 ;; But it is mainly intended to test the support for these optimizations.
6541 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
6542 (set (match_operand:DF 0 "register_operand" "=f")
6543 (match_operand:DF 1 "register_operand" "ad"))]
6544 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
6548 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
6549 output_asm_insn (\"move%.l %1,%@\", xoperands);
6550 output_asm_insn (\"move%.l %1,%-\", operands);
6551 return \"fmove%.d %+,%0\";
6555 ;; Optimize a stack-adjust followed by a push of an argument.
6556 ;; This is said to happen frequently with -msoft-float
6557 ;; when there are consecutive library calls.
6560 [(set (reg:SI 15) (plus:SI (reg:SI 15)
6561 (match_operand:SI 0 "const_int_operand" "n")))
6562 (set (match_operand:SF 1 "push_operand" "=m")
6563 (match_operand:SF 2 "general_operand" "rmfF"))]
6564 "INTVAL (operands[0]) >= 4
6565 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
6568 if (INTVAL (operands[0]) > 4)
6571 xoperands[0] = stack_pointer_rtx;
6572 xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4);
6574 if (INTVAL (xoperands[1]) <= 8)
6577 output_asm_insn (\"addq%.w %1,%0\", xoperands);
6579 output_asm_insn (\"addq%.l %1,%0\", xoperands);
6581 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
6583 xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
6584 INTVAL (xoperands[1]) - 8);
6585 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
6589 if (INTVAL (xoperands[1]) <= 0x7FFF)
6592 output_asm_insn (\"add%.w %1,%0\", xoperands);
6595 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
6597 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
6601 output_asm_insn (\"add%.l %1,%0\", xoperands);
6603 if (FP_REG_P (operands[2]))
6604 return \"fmove%.s %2,%@\";
6605 return \"move%.l %2,%@\";
6608 ;; Speed up stack adjust followed by a fullword fixedpoint push.
6611 [(set (reg:SI 15) (plus:SI (reg:SI 15)
6612 (match_operand:SI 0 "const_int_operand" "n")))
6613 (set (match_operand:SI 1 "push_operand" "=m")
6614 (match_operand:SI 2 "general_operand" "g"))]
6615 "INTVAL (operands[0]) >= 4
6616 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
6619 if (INTVAL (operands[0]) > 4)
6622 xoperands[0] = stack_pointer_rtx;
6623 xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4);
6625 if (INTVAL (xoperands[1]) <= 8)
6628 output_asm_insn (\"addq%.w %1,%0\", xoperands);
6630 output_asm_insn (\"addq%.l %1,%0\", xoperands);
6632 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
6634 xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
6635 INTVAL (xoperands[1]) - 8);
6636 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
6640 if (INTVAL (xoperands[1]) <= 0x7FFF)
6643 output_asm_insn (\"add%.w %1,%0\", xoperands);
6646 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
6648 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
6652 output_asm_insn (\"add%.l %1,%0\", xoperands);
6654 if (operands[2] == const0_rtx)
6655 return \"clr%.l %@\";
6656 return \"move%.l %2,%@\";
6659 ;; Speed up pushing a single byte but leaving four bytes of space.
6662 [(set (mem:QI (pre_dec:SI (reg:SI 15)))
6663 (match_operand:QI 1 "general_operand" "dami"))
6664 (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))]
6665 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
6670 if (GET_CODE (operands[1]) == REG)
6671 return \"move%.l %1,%-\";
6673 xoperands[1] = operands[1];
6675 = gen_rtx (MEM, QImode,
6676 gen_rtx (PLUS, VOIDmode, stack_pointer_rtx,
6677 gen_rtx (CONST_INT, VOIDmode, 3)));
6678 xoperands[3] = stack_pointer_rtx;
6680 output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
6682 output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands);
6687 [(set (match_operand:SI 0 "register_operand" "=d")
6689 (set (strict_low_part (subreg:HI (match_dup 0) 0))
6690 (match_operand:HI 1 "general_operand" "rmn"))]
6691 "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
6694 if (GET_CODE (operands[1]) == CONST_INT)
6696 if (operands[1] == const0_rtx
6697 && (DATA_REG_P (operands[0])
6698 || GET_CODE (operands[0]) == MEM)
6699 /* clr insns on 68000 read before writing.
6700 This isn't so on the 68010, but we have no TARGET_68010. */
6701 && ((TARGET_68020 || TARGET_5200)
6702 || !(GET_CODE (operands[0]) == MEM
6703 && MEM_VOLATILE_P (operands[0]))))
6704 return \"clr%.w %0\";
6706 return \"move%.w %1,%0\";
6714 ;; jCC label ; abnormal loop termination
6715 ;; dbra dN, loop ; normal loop termination
6723 ;; Which moves the jCC condition outside the inner loop for free.
6726 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
6727 [(cc0) (const_int 0)])
6728 (label_ref (match_operand 2 "" ""))
6733 (ge (plus:HI (match_operand:HI 0 "register_operand" "+d")
6736 (label_ref (match_operand 1 "" ""))
6739 (plus:HI (match_dup 0)
6741 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
6745 output_dbcc_and_branch (operands);
6750 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
6751 [(cc0) (const_int 0)])
6752 (label_ref (match_operand 2 "" ""))
6757 (ge (plus:SI (match_operand:SI 0 "register_operand" "+d")
6760 (label_ref (match_operand 1 "" ""))
6763 (plus:SI (match_dup 0)
6765 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
6769 output_dbcc_and_branch (operands);
6774 ;; FPA multiply and add.
6776 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6777 (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%x,dmF,y")
6778 (match_operand:DF 2 "general_operand" "xH,y,y"))
6779 (match_operand:DF 3 "general_operand" "xH,y,dmF")))]
6782 fpma%.d %1,%w2,%w3,%0
6783 fpma%.d %x1,%x2,%x3,%0
6784 fpma%.d %x1,%x2,%x3,%0")
6787 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6788 (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%x,ydmF,y")
6789 (match_operand:SF 2 "general_operand" "xH,y,ydmF"))
6790 (match_operand:SF 3 "general_operand" "xH,ydmF,ydmF")))]
6793 fpma%.s %1,%w2,%w3,%0
6795 fpma%.s %1,%2,%3,%0")
6797 ;; FPA Multiply and subtract
6799 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6800 (minus:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
6801 (mult:DF (match_operand:DF 2 "general_operand" "%xH,y,y")
6802 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
6805 fpms%.d %3,%w2,%w1,%0
6806 fpms%.d %x3,%2,%x1,%0
6807 fpms%.d %x3,%2,%x1,%0")
6810 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6811 (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
6812 (mult:SF (match_operand:SF 2 "general_operand" "%xH,rmF,y")
6813 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
6816 fpms%.s %3,%w2,%w1,%0
6818 fpms%.s %3,%2,%1,%0")
6821 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6822 (minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
6823 (match_operand:DF 2 "general_operand" "x,y,rmF"))
6824 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
6827 fpmr%.d %2,%w1,%w3,%0
6828 fpmr%.d %x2,%1,%x3,%0
6829 fpmr%.d %x2,%1,%x3,%0")
6832 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6833 (minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
6834 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
6835 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
6838 fpmr%.s %2,%w1,%w3,%0
6839 fpmr%.s %x2,%1,%x3,%0
6840 fpmr%.s %x2,%1,%x3,%0")
6842 ;; FPA Add and multiply
6844 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6845 (mult:DF (plus:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
6846 (match_operand:DF 2 "general_operand" "x,y,rmF"))
6847 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
6850 fpam%.d %2,%w1,%w3,%0
6851 fpam%.d %x2,%1,%x3,%0
6852 fpam%.d %x2,%1,%x3,%0")
6855 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6856 (mult:SF (plus:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
6857 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
6858 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
6861 fpam%.s %2,%w1,%w3,%0
6862 fpam%.s %x2,%1,%x3,%0
6863 fpam%.s %x2,%1,%x3,%0")
6865 ;;FPA Subtract and multiply
6867 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6868 (mult:DF (minus:DF (match_operand:DF 1 "general_operand" "xH,y,y")
6869 (match_operand:DF 2 "general_operand" "x,y,rmF"))
6870 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
6873 fpsm%.d %2,%w1,%w3,%0
6874 fpsm%.d %x2,%1,%x3,%0
6875 fpsm%.d %x2,%1,%x3,%0")
6878 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6879 (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
6880 (minus:DF (match_operand:DF 2 "general_operand" "xH,y,y")
6881 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
6884 fpsm%.d %3,%w2,%w1,%0
6885 fpsm%.d %x3,%2,%x1,%0
6886 fpsm%.d %x3,%2,%x1,%0")
6889 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6890 (mult:SF (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,y")
6891 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
6892 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
6895 fpsm%.s %2,%w1,%w3,%0
6896 fpsm%.s %x2,%1,%x3,%0
6897 fpsm%.s %x2,%1,%x3,%0")
6900 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6901 (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
6902 (minus:SF (match_operand:SF 2 "general_operand" "xH,rmF,y")
6903 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
6906 fpsm%.s %3,%w2,%w1,%0
6907 fpsm%.s %x3,%2,%x1,%0
6908 fpsm%.s %x3,%2,%x1,%0")
6910 (define_expand "tstxf"
6912 (match_operand:XF 0 "nonimmediate_operand" ""))]
6914 "m68k_last_compare_had_fp_operands = 1;")
6918 (match_operand:XF 0 "nonimmediate_operand" "fm"))]
6922 cc_status.flags = CC_IN_68881;
6923 return \"ftst%.x %0\";
6926 (define_expand "cmpxf"
6928 (compare (match_operand:XF 0 "nonimmediate_operand" "")
6929 (match_operand:XF 1 "nonimmediate_operand" "")))]
6931 "m68k_last_compare_had_fp_operands = 1;")
6935 (compare (match_operand:XF 0 "nonimmediate_operand" "f,m")
6936 (match_operand:XF 1 "nonimmediate_operand" "fm,f")))]
6940 cc_status.flags = CC_IN_68881;
6941 #ifdef SGS_CMP_ORDER
6942 if (REG_P (operands[0]))
6944 if (REG_P (operands[1]))
6945 return \"fcmp%.x %0,%1\";
6947 return \"fcmp%.x %0,%f1\";
6949 cc_status.flags |= CC_REVERSED;
6950 return \"fcmp%.x %1,%f0\";
6952 if (REG_P (operands[0]))
6954 if (REG_P (operands[1]))
6955 return \"fcmp%.x %1,%0\";
6957 return \"fcmp%.x %f1,%0\";
6959 cc_status.flags |= CC_REVERSED;
6960 return \"fcmp%.x %f0,%1\";
6964 (define_insn "extendsfxf2"
6965 [(set (match_operand:XF 0 "general_operand" "=fm,f")
6966 (float_extend:XF (match_operand:SF 1 "general_operand" "f,m")))]
6970 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
6972 if (REGNO (operands[0]) == REGNO (operands[1]))
6974 /* Extending float to double in an fp-reg is a no-op.
6975 NOTICE_UPDATE_CC has already assumed that the
6976 cc will be set. So cancel what it did. */
6977 cc_status = cc_prev_status;
6980 return \"f%$move%.x %1,%0\";
6982 if (FP_REG_P (operands[0]))
6983 return \"f%$move%.s %f1,%0\";
6984 return \"fmove%.x %f1,%0\";
6988 (define_insn "extenddfxf2"
6989 [(set (match_operand:XF 0 "general_operand" "=fm,f")
6991 (match_operand:DF 1 "general_operand" "f,m")))]
6995 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
6997 if (REGNO (operands[0]) == REGNO (operands[1]))
6999 /* Extending float to double in an fp-reg is a no-op.
7000 NOTICE_UPDATE_CC has already assumed that the
7001 cc will be set. So cancel what it did. */
7002 cc_status = cc_prev_status;
7005 return \"fmove%.x %1,%0\";
7007 if (FP_REG_P (operands[0]))
7008 return \"f%&move%.d %f1,%0\";
7009 return \"fmove%.x %f1,%0\";
7012 (define_insn "truncxfdf2"
7013 [(set (match_operand:DF 0 "general_operand" "=m,!r")
7015 (match_operand:XF 1 "general_operand" "f,f")))]
7019 if (REG_P (operands[0]))
7021 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
7022 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
7023 return \"move%.l %+,%0\";
7025 return \"fmove%.d %f1,%0\";
7028 (define_insn "truncxfsf2"
7029 [(set (match_operand:SF 0 "general_operand" "=dm")
7031 (match_operand:XF 1 "general_operand" "f")))]
7035 (define_insn "floatsixf2"
7036 [(set (match_operand:XF 0 "general_operand" "=f")
7037 (float:XF (match_operand:SI 1 "general_operand" "dmi")))]
7041 (define_insn "floathixf2"
7042 [(set (match_operand:XF 0 "general_operand" "=f")
7043 (float:XF (match_operand:HI 1 "general_operand" "dmn")))]
7047 (define_insn "floatqixf2"
7048 [(set (match_operand:XF 0 "general_operand" "=f")
7049 (float:XF (match_operand:QI 1 "general_operand" "dmn")))]
7053 (define_insn "ftruncxf2"
7054 [(set (match_operand:XF 0 "general_operand" "=f")
7055 (fix:XF (match_operand:XF 1 "general_operand" "fFm")))]
7059 if (FP_REG_P (operands[1]))
7060 return \"fintrz%.x %f1,%0\";
7061 return \"fintrz%.x %f1,%0\";
7064 (define_insn "fixxfqi2"
7065 [(set (match_operand:QI 0 "general_operand" "=dm")
7066 (fix:QI (match_operand:XF 1 "general_operand" "f")))]
7070 (define_insn "fixxfhi2"
7071 [(set (match_operand:HI 0 "general_operand" "=dm")
7072 (fix:HI (match_operand:XF 1 "general_operand" "f")))]
7076 (define_insn "fixxfsi2"
7077 [(set (match_operand:SI 0 "general_operand" "=dm")
7078 (fix:SI (match_operand:XF 1 "general_operand" "f")))]
7083 [(set (match_operand:XF 0 "general_operand" "=f")
7084 (plus:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7085 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7090 [(set (match_operand:XF 0 "general_operand" "=f")
7091 (plus:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7092 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7097 [(set (match_operand:XF 0 "general_operand" "=f")
7098 (plus:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7099 (match_operand:XF 1 "general_operand" "0")))]
7103 (define_insn "addxf3"
7104 [(set (match_operand:XF 0 "general_operand" "=f")
7105 (plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7106 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7110 if (REG_P (operands[2]))
7111 return \"fadd%.x %2,%0\";
7112 return \"fadd%.x %f2,%0\";
7116 [(set (match_operand:XF 0 "general_operand" "=f")
7117 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7118 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7123 [(set (match_operand:XF 0 "general_operand" "=f")
7124 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7125 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7130 [(set (match_operand:XF 0 "general_operand" "=f")
7131 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7132 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7136 (define_insn "subxf3"
7137 [(set (match_operand:XF 0 "general_operand" "=f")
7138 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7139 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7143 if (REG_P (operands[2]))
7144 return \"fsub%.x %2,%0\";
7145 return \"fsub%.x %f2,%0\";
7149 [(set (match_operand:XF 0 "general_operand" "=f")
7150 (mult:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7151 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7156 [(set (match_operand:XF 0 "general_operand" "=f")
7157 (mult:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7158 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7163 [(set (match_operand:XF 0 "general_operand" "=f")
7164 (mult:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7165 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7169 (define_insn "mulxf3"
7170 [(set (match_operand:XF 0 "general_operand" "=f")
7171 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7172 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7176 if (REG_P (operands[2]))
7177 return \"fmul%.x %2,%0\";
7178 return \"fmul%.x %f2,%0\";
7182 [(set (match_operand:XF 0 "general_operand" "=f")
7183 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7184 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7189 [(set (match_operand:XF 0 "general_operand" "=f")
7190 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7191 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7196 [(set (match_operand:XF 0 "general_operand" "=f")
7197 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7198 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7202 (define_insn "divxf3"
7203 [(set (match_operand:XF 0 "general_operand" "=f")
7204 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7205 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7209 if (REG_P (operands[2]))
7210 return \"fdiv%.x %2,%0\";
7211 return \"fdiv%.x %f2,%0\";
7214 (define_expand "negxf2"
7215 [(set (match_operand:XF 0 "general_operand" "")
7216 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7220 /* ??? There isn't an FPA define_insn so we could handle it here too.
7221 For now we don't (paranoia). */
7229 target = operand_subword (operands[0], 0, 1, XFmode);
7230 result = expand_binop (SImode, xor_optab,
7231 operand_subword_force (operands[1], 0, XFmode),
7232 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
7236 if (result != target)
7237 emit_move_insn (result, target);
7239 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7240 operand_subword_force (operands[1], 1, XFmode));
7241 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7242 operand_subword_force (operands[1], 2, XFmode));
7244 insns = get_insns ();
7247 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7252 (define_insn "negxf2_68881"
7253 [(set (match_operand:XF 0 "general_operand" "=f")
7254 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7258 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7259 return \"fneg%.x %1,%0\";
7260 return \"fneg%.x %f1,%0\";
7263 (define_expand "absxf2"
7264 [(set (match_operand:XF 0 "general_operand" "")
7265 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7269 /* ??? There isn't an FPA define_insn so we could handle it here too.
7270 For now we don't (paranoia). */
7278 target = operand_subword (operands[0], 0, 1, XFmode);
7279 result = expand_binop (SImode, and_optab,
7280 operand_subword_force (operands[1], 0, XFmode),
7281 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
7285 if (result != target)
7286 emit_move_insn (result, target);
7288 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7289 operand_subword_force (operands[1], 1, XFmode));
7290 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7291 operand_subword_force (operands[1], 2, XFmode));
7293 insns = get_insns ();
7296 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7301 (define_insn "absxf2_68881"
7302 [(set (match_operand:XF 0 "general_operand" "=f")
7303 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7307 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7308 return \"fabs%.x %1,%0\";
7309 return \"fabs%.x %f1,%0\";
7312 (define_insn "sqrtxf2"
7313 [(set (match_operand:XF 0 "general_operand" "=f")
7314 (sqrt:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7318 (define_insn "sinsf2"
7319 [(set (match_operand:SF 0 "general_operand" "=f")
7320 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 1))]
7321 "TARGET_68881 && flag_fast_math"
7324 if (FP_REG_P (operands[1]))
7325 return \"fsin%.x %1,%0\";
7327 return \"fsin%.s %1,%0\";
7330 (define_insn "sindf2"
7331 [(set (match_operand:DF 0 "general_operand" "=f")
7332 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 1))]
7333 "TARGET_68881 && flag_fast_math"
7336 if (FP_REG_P (operands[1]))
7337 return \"fsin%.x %1,%0\";
7339 return \"fsin%.d %1,%0\";
7342 (define_insn "sinxf2"
7343 [(set (match_operand:XF 0 "general_operand" "=f")
7344 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 1))]
7345 "TARGET_68881 && flag_fast_math"
7348 (define_insn "cossf2"
7349 [(set (match_operand:SF 0 "general_operand" "=f")
7350 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 2))]
7351 "TARGET_68881 && flag_fast_math"
7354 if (FP_REG_P (operands[1]))
7355 return \"fcos%.x %1,%0\";
7357 return \"fcos%.s %1,%0\";
7360 (define_insn "cosdf2"
7361 [(set (match_operand:DF 0 "general_operand" "=f")
7362 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 2))]
7363 "TARGET_68881 && flag_fast_math"
7366 if (FP_REG_P (operands[1]))
7367 return \"fcos%.x %1,%0\";
7369 return \"fcos%.d %1,%0\";
7372 (define_insn "cosxf2"
7373 [(set (match_operand:XF 0 "general_operand" "=f")
7374 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 2))]
7375 "TARGET_68881 && flag_fast_math"