1 /* Definitions of target machine for GNU compiler.
2 Sun 68000/68020 version.
3 Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 2000, 2001, 2002 Free Software Foundation, Inc.
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 /* Note that some other tm.h files include this one and then override
25 many of the definitions that relate to assembler syntax. */
28 /* Classify the groups of pseudo-ops used to assemble QI, HI and SI
30 #define INT_OP_STANDARD 0 /* .byte, .short, .long */
31 #define INT_OP_DOT_WORD 1 /* .byte, .word, .long */
32 #define INT_OP_NO_DOT 2 /* byte, short, long */
33 #define INT_OP_DC 3 /* dc.b, dc.w, dc.l */
36 #define INT_OP_GROUP INT_OP_DOT_WORD
38 /* Names to predefine in the preprocessor for this target machine. */
40 /* See sun3.h, sun2.h, isi.h for different CPP_PREDEFINES. */
42 /* Print subsidiary information on the compiler version in use. */
44 #define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)");
46 #define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)");
49 /* Define SUPPORT_SUN_FPA to include support for generating code for
50 the Sun Floating Point Accelerator, an optional product for Sun 3
51 machines. By default, it is not defined. Avoid defining it unless
52 you need to output code for the Sun3+FPA architecture, as it has the
53 effect of slowing down the register set operations in hard-reg-set.h
54 (total number of registers will exceed number of bits in a long,
55 if defined, causing the set operations to expand to loops).
56 SUPPORT_SUN_FPA is typically defined in sun3.h. */
58 /* Run-time compilation parameters selecting different hardware subsets. */
60 extern int target_flags;
62 /* Macros used in the machine description to test the flags. */
64 /* Compile for a 68020 (not a 68000 or 68010). */
66 #define TARGET_68020 (target_flags & MASK_68020)
68 /* Compile 68881 insns for floating point (not library calls). */
70 #define TARGET_68881 (target_flags & MASK_68881)
72 /* Compile using 68020 bitfield insns. */
73 #define MASK_BITFIELD 4
74 #define TARGET_BITFIELD (target_flags & MASK_BITFIELD)
76 /* Compile using rtd insn calling sequence.
77 This will not work unless you use prototypes at least
78 for all functions that can take varying numbers of args. */
80 #define TARGET_RTD (target_flags & MASK_RTD)
82 /* Compile passing first two args in regs 0 and 1.
83 This exists only to test compiler features that will
84 be needed for RISC chips. It is not usable
85 and is not intended to be usable on this cpu. */
86 #define MASK_REGPARM 16
87 #define TARGET_REGPARM (target_flags & MASK_REGPARM)
89 /* Compile with 16-bit `int'. */
91 #define TARGET_SHORT (target_flags & MASK_SHORT)
93 /* Compile with special insns for Sun FPA. */
95 #define TARGET_FPA (target_flags & MASK_FPA)
97 /* Compile (actually, link) for Sun SKY board. */
99 #define TARGET_SKY (target_flags & MASK_SKY)
101 /* Optimize for 68040, but still allow execution on 68020
102 (-m68020-40 or -m68040).
103 The 68040 will execute all 68030 and 68881/2 instructions, but some
104 of them must be emulated in software by the OS. When TARGET_68040 is
105 turned on, these instructions won't be used. This code will still
106 run on a 68030 and 68881/2. */
107 #define MASK_68040 256
108 #define TARGET_68040 (target_flags & MASK_68040)
110 /* Use the 68040-only fp instructions (-m68040 or -m68060). */
111 #define MASK_68040_ONLY 512
112 #define TARGET_68040_ONLY (target_flags & MASK_68040_ONLY)
114 /* Optimize for 68060, but still allow execution on 68020
115 (-m68020-60 or -m68060).
116 The 68060 will execute all 68030 and 68881/2 instructions, but some
117 of them must be emulated in software by the OS. When TARGET_68060 is
118 turned on, these instructions won't be used. This code will still
119 run on a 68030 and 68881/2. */
120 #define MASK_68060 1024
121 #define TARGET_68060 (target_flags & MASK_68060)
123 /* Compile for mcf5200 */
124 #define MASK_5200 2048
125 #define TARGET_5200 (target_flags & MASK_5200)
127 /* Align ints to a word boundary. This breaks compatibility with the
128 published ABI's for structures containing ints, but produces faster
129 code on cpus with 32 bit busses (020, 030, 040, 060, CPU32+, coldfire).
130 It's required for coldfire cpus without a misalignment module. */
131 #define MASK_ALIGN_INT 4096
132 #define TARGET_ALIGN_INT (target_flags & MASK_ALIGN_INT)
134 /* Compile for a CPU32 */
135 /* A 68020 without bitfields is a good heuristic for a CPU32 */
136 #define TARGET_CPU32 (TARGET_68020 && !TARGET_BITFIELD)
138 /* Use PC-relative addressing modes (without using a global offset table).
139 The m68000 supports 16-bit PC-relative addressing.
140 The m68020 supports 32-bit PC-relative addressing
141 (using outer displacements).
143 Under this model, all SYMBOL_REFs (and CONSTs) and LABEL_REFs are
144 treated as all containing an implicit PC-relative component, and hence
145 cannot be used directly as addresses for memory writes. See the comments
146 in m68k.c for more information. */
147 #define MASK_PCREL 8192
148 #define TARGET_PCREL (target_flags & MASK_PCREL)
150 /* Relax strict alignment. */
151 #define MASK_NO_STRICT_ALIGNMENT 16384
152 #define TARGET_STRICT_ALIGNMENT (~target_flags & MASK_NO_STRICT_ALIGNMENT)
154 /* Macro to define tables used to set the flags.
155 This is a list in braces of pairs in braces,
156 each pair being { "NAME", VALUE }
157 where VALUE is the bits to set or minus the bits to clear.
158 An empty string NAME is used to identify the default VALUE. */
160 #define TARGET_SWITCHES \
161 { { "68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \
162 N_("Generate code for a 68020") }, \
163 { "c68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \
164 N_("Generate code for a 68020") }, \
165 { "68020", (MASK_68020|MASK_BITFIELD), "" }, \
166 { "c68020", (MASK_68020|MASK_BITFIELD), "" }, \
167 { "68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
168 |MASK_68020|MASK_BITFIELD|MASK_68881), \
169 N_("Generate code for a 68000") }, \
170 { "c68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
171 |MASK_68020|MASK_BITFIELD|MASK_68881), \
172 N_("Generate code for a 68000") }, \
173 { "bitfield", MASK_BITFIELD, \
174 N_("Use the bit-field instructions") }, \
175 { "nobitfield", - MASK_BITFIELD, \
176 N_("Do not use the bit-field instructions") }, \
178 N_("Use different calling convention using 'rtd'") }, \
179 { "nortd", - MASK_RTD, \
180 N_("Use normal calling convention") }, \
181 { "short", MASK_SHORT, \
182 N_("Consider type `int' to be 16 bits wide") }, \
183 { "noshort", - MASK_SHORT, \
184 N_("Consider type `int' to be 32 bits wide") }, \
185 { "fpa", -(MASK_SKY|MASK_68040_ONLY|MASK_68881), \
186 N_("Generate code for a Sun FPA") }, \
187 { "fpa", MASK_FPA, "" }, \
188 { "nofpa", - MASK_FPA, \
189 N_("Do not generate code for a Sun FPA") }, \
190 { "sky", -(MASK_FPA|MASK_68040_ONLY|MASK_68881), \
191 N_("Generate code for a Sun Sky board") }, \
193 N_("Generate code for a Sun Sky board") }, \
194 { "nosky", - MASK_SKY, \
195 N_("Do not use Sky linkage convention") }, \
196 { "68881", - (MASK_FPA|MASK_SKY), \
197 N_("Generate code for a 68881") }, \
198 { "68881", MASK_68881, "" }, \
199 { "soft-float", - (MASK_FPA|MASK_SKY|MASK_68040_ONLY|MASK_68881), \
200 N_("Generate code with library calls for floating point") }, \
201 { "68020-40", -(MASK_5200|MASK_68060|MASK_68040_ONLY), \
202 N_("Generate code for a 68040, without any new instructions") }, \
203 { "68020-40", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040), ""},\
204 { "68020-60", -(MASK_5200|MASK_68040_ONLY), \
205 N_("Generate code for a 68060, without any new instructions") }, \
206 { "68020-60", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040 \
207 |MASK_68060), "" }, \
208 { "68030", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \
209 N_("Generate code for a 68030") }, \
210 { "68030", (MASK_68020|MASK_BITFIELD), "" }, \
211 { "68040", - (MASK_5200|MASK_68060), \
212 N_("Generate code for a 68040") }, \
213 { "68040", (MASK_68020|MASK_68881|MASK_BITFIELD \
214 |MASK_68040_ONLY|MASK_68040), "" }, \
215 { "68060", - (MASK_5200|MASK_68040), \
216 N_("Generate code for a 68060") }, \
217 { "68060", (MASK_68020|MASK_68881|MASK_BITFIELD \
218 |MASK_68040_ONLY|MASK_68060), "" }, \
219 { "5200", - (MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
220 |MASK_BITFIELD|MASK_68881), \
221 N_("Generate code for a 520X") }, \
222 { "5200", (MASK_5200), "" }, \
224 N_("Generate code for a 68851") }, \
226 N_("Do no generate code for a 68851") }, \
227 { "68302", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
228 |MASK_68020|MASK_BITFIELD|MASK_68881), \
229 N_("Generate code for a 68302") }, \
230 { "68332", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
231 |MASK_BITFIELD|MASK_68881), \
232 N_("Generate code for a 68332") }, \
233 { "68332", MASK_68020, "" }, \
234 { "cpu32", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
235 |MASK_BITFIELD|MASK_68881), \
236 N_("Generate code for a cpu32") }, \
237 { "cpu32", MASK_68020, "" }, \
238 { "align-int", MASK_ALIGN_INT, \
239 N_("Align variables on a 32-bit boundary") }, \
240 { "no-align-int", -MASK_ALIGN_INT, \
241 N_("Align variables on a 16-bit boundary") }, \
242 { "pcrel", MASK_PCREL, \
243 N_("Generate pc-relative code") }, \
244 { "strict-align", -MASK_NO_STRICT_ALIGNMENT, \
245 N_("Do not use unaligned memory references") }, \
246 { "no-strict-align", MASK_NO_STRICT_ALIGNMENT, \
247 N_("Use unaligned memory references") }, \
249 { "", TARGET_DEFAULT, "" }}
250 /* TARGET_DEFAULT is defined in sun*.h and isi.h, etc. */
252 /* This macro is similar to `TARGET_SWITCHES' but defines names of
253 command options that have values. Its definition is an
254 initializer with a subgrouping for each command option.
256 Each subgrouping contains a string constant, that defines the
257 fixed part of the option name, and the address of a variable. The
258 variable, type `char *', is set to the variable part of the given
259 option if the fixed part matches. The actual option name is made
260 by appending `-m' to the specified name. */
261 #define TARGET_OPTIONS \
262 { { "align-loops=", &m68k_align_loops_string, \
263 N_("Loop code aligned to this power of 2") }, \
264 { "align-jumps=", &m68k_align_jumps_string, \
265 N_("Jump targets are aligned to this power of 2") }, \
266 { "align-functions=", &m68k_align_funcs_string, \
267 N_("Function starts are aligned to this power of 2") }, \
271 /* Sometimes certain combinations of command options do not make
272 sense on a particular target machine. You can define a macro
273 `OVERRIDE_OPTIONS' to take account of this. This macro, if
274 defined, is executed once just after all the command options have
277 Don't use this macro to turn on various extra optimizations for
278 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
280 #define OVERRIDE_OPTIONS \
282 override_options(); \
283 if (! TARGET_68020 && flag_pic == 2) \
284 error("-fPIC is not currently supported on the 68000 or 68010\n"); \
285 if (TARGET_PCREL && flag_pic == 0) \
287 SUBTARGET_OVERRIDE_OPTIONS; \
290 /* These are meant to be redefined in the host dependent files */
291 #define SUBTARGET_SWITCHES
292 #define SUBTARGET_OPTIONS
293 #define SUBTARGET_OVERRIDE_OPTIONS
295 /* target machine storage layout */
297 /* Define for XFmode extended real floating point support.
298 This will automatically cause REAL_ARITHMETIC to be defined. */
299 #define LONG_DOUBLE_TYPE_SIZE 96
301 /* Define if you don't want extended real, but do want to use the
302 software floating point emulator for REAL_ARITHMETIC and
303 decimal <-> binary conversion. */
304 /* #define REAL_ARITHMETIC */
306 /* Define this if most significant bit is lowest numbered
307 in instructions that operate on numbered bit-fields.
308 This is true for 68020 insns such as bfins and bfexts.
309 We make it true always by avoiding using the single-bit insns
310 except in special cases with constant bit numbers. */
311 #define BITS_BIG_ENDIAN 1
313 /* Define this if most significant byte of a word is the lowest numbered. */
314 /* That is true on the 68000. */
315 #define BYTES_BIG_ENDIAN 1
317 /* Define this if most significant word of a multiword number is the lowest
319 /* For 68000 we can decide arbitrarily
320 since there are no machine instructions for them.
321 So let's be consistent. */
322 #define WORDS_BIG_ENDIAN 1
324 /* number of bits in an addressable storage unit */
325 #define BITS_PER_UNIT 8
327 /* Width in bits of a "word", which is the contents of a machine register.
328 Note that this is not necessarily the width of data type `int';
329 if using 16-bit ints on a 68000, this would still be 32.
330 But on a machine with 16-bit registers, this would be 16. */
331 #define BITS_PER_WORD 32
333 /* Width of a word, in units (bytes). */
334 #define UNITS_PER_WORD 4
336 /* Width in bits of a pointer.
337 See also the macro `Pmode' defined below. */
338 #define POINTER_SIZE 32
340 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
341 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
343 /* Boundary (in *bits*) on which stack pointer should be aligned. */
344 #define STACK_BOUNDARY 16
346 /* Allocation boundary (in *bits*) for the code of a function. */
347 #define FUNCTION_BOUNDARY (1 << (m68k_align_funcs + 3))
349 /* Alignment of field after `int : 0' in a structure. */
350 #define EMPTY_FIELD_BOUNDARY 16
352 /* No data type wants to be aligned rounder than this.
353 Most published ABIs say that ints should be aligned on 16 bit
354 boundaries, but cpus with 32 bit busses get better performance
355 aligned on 32 bit boundaries. Coldfires without a misalignment
356 module require 32 bit alignment. */
357 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
359 /* Set this nonzero if move instructions will actually fail to work
360 when given unaligned data. */
361 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT)
363 /* Maximum power of 2 that code can be aligned to. */
364 #define MAX_CODE_ALIGN 2 /* 4 byte alignment */
366 /* Align loop starts for optimal branching. */
367 #define LOOP_ALIGN(LABEL) (m68k_align_loops)
369 /* This is how to align an instruction for optimal branching. */
370 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) (m68k_align_jumps)
372 #define SELECT_RTX_SECTION(MODE, X, ALIGN) \
375 readonly_data_section(); \
376 else if (LEGITIMATE_PIC_OPERAND_P (X)) \
377 readonly_data_section(); \
382 /* Define number of bits in most basic integer type.
383 (If undefined, default is BITS_PER_WORD). */
385 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
387 /* Define these to avoid dependence on meaning of `int'. */
389 #define WCHAR_TYPE "long int"
390 #define WCHAR_TYPE_SIZE 32
392 /* Standard register usage. */
394 /* Number of actual hardware registers.
395 The hardware registers are assigned numbers for the compiler
396 from 0 to just below FIRST_PSEUDO_REGISTER.
397 All registers that the compiler knows about must be given numbers,
398 even those that are not normally considered general registers.
399 For the 68000, we give the data registers numbers 0-7,
400 the address registers numbers 010-017,
401 and the 68881 floating point registers numbers 020-027. */
402 #ifndef SUPPORT_SUN_FPA
403 #define FIRST_PSEUDO_REGISTER 24
405 #define FIRST_PSEUDO_REGISTER 56
408 /* This defines the register which is used to hold the offset table for PIC. */
409 #define PIC_OFFSET_TABLE_REGNUM 13
411 #ifndef SUPPORT_SUN_FPA
413 /* 1 for registers that have pervasive standard uses
414 and are not available for the register allocator.
415 On the 68000, only the stack pointer is such. */
417 #define FIXED_REGISTERS \
418 {/* Data registers. */ \
419 0, 0, 0, 0, 0, 0, 0, 0, \
421 /* Address registers. */ \
422 0, 0, 0, 0, 0, 0, 0, 1, \
424 /* Floating point registers \
426 0, 0, 0, 0, 0, 0, 0, 0 }
428 /* 1 for registers not available across function calls.
429 These must include the FIXED_REGISTERS and also any
430 registers that can be used without being saved.
431 The latter must include the registers where values are returned
432 and the register where structure-value addresses are passed.
433 Aside from that, you can include as many other registers as you like. */
434 #define CALL_USED_REGISTERS \
435 {1, 1, 0, 0, 0, 0, 0, 0, \
436 1, 1, 0, 0, 0, 0, 0, 1, \
437 1, 1, 0, 0, 0, 0, 0, 0 }
439 #else /* SUPPORT_SUN_FPA */
441 /* 1 for registers that have pervasive standard uses
442 and are not available for the register allocator.
443 On the 68000, only the stack pointer is such. */
445 /* fpa0 is also reserved so that it can be used to move data back and
446 forth between high fpa regs and everything else. */
448 #define FIXED_REGISTERS \
449 {/* Data registers. */ \
450 0, 0, 0, 0, 0, 0, 0, 0, \
452 /* Address registers. */ \
453 0, 0, 0, 0, 0, 0, 0, 1, \
455 /* Floating point registers \
457 0, 0, 0, 0, 0, 0, 0, 0, \
459 /* Sun3 FPA registers. */ \
460 1, 0, 0, 0, 0, 0, 0, 0, \
461 0, 0, 0, 0, 0, 0, 0, 0, \
462 0, 0, 0, 0, 0, 0, 0, 0, \
463 0, 0, 0, 0, 0, 0, 0, 0 }
465 /* 1 for registers not available across function calls.
466 These must include the FIXED_REGISTERS and also any
467 registers that can be used without being saved.
468 The latter must include the registers where values are returned
469 and the register where structure-value addresses are passed.
470 Aside from that, you can include as many other registers as you like. */
471 #define CALL_USED_REGISTERS \
472 {1, 1, 0, 0, 0, 0, 0, 0, \
473 1, 1, 0, 0, 0, 0, 0, 1, \
474 1, 1, 0, 0, 0, 0, 0, 0, \
475 /* FPA registers. */ \
476 1, 1, 1, 1, 0, 0, 0, 0, \
477 0, 0, 0, 0, 0, 0, 0, 0, \
478 0, 0, 0, 0, 0, 0, 0, 0, \
479 0, 0, 0, 0, 0, 0, 0, 0 }
481 #endif /* defined SUPPORT_SUN_FPA */
484 /* Make sure everything's fine if we *don't* have a given processor.
485 This assumes that putting a register in fixed_regs will keep the
486 compiler's mitts completely off it. We don't bother to zero it out
487 of register classes. */
489 #ifdef SUPPORT_SUN_FPA
491 #define CONDITIONAL_REGISTER_USAGE \
497 COPY_HARD_REG_SET (x, reg_class_contents[(int)FPA_REGS]); \
498 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
499 if (TEST_HARD_REG_BIT (x, i)) \
500 fixed_regs[i] = call_used_regs[i] = 1; \
502 if (! TARGET_68881) \
504 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
505 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
506 if (TEST_HARD_REG_BIT (x, i)) \
507 fixed_regs[i] = call_used_regs[i] = 1; \
510 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
511 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;\
514 #define CONDITIONAL_REGISTER_USAGE \
518 if (! TARGET_68881) \
520 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
521 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
522 if (TEST_HARD_REG_BIT (x, i)) \
523 fixed_regs[i] = call_used_regs[i] = 1; \
526 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
527 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;\
530 #endif /* defined SUPPORT_SUN_FPA */
532 /* Return number of consecutive hard regs needed starting at reg REGNO
533 to hold something of mode MODE.
534 This is ordinarily the length in words of a value of mode MODE
535 but can be less for certain modes in special long registers.
537 On the 68000, ordinary registers hold 32 bits worth;
538 for the 68881 registers, a single register is always enough for
539 anything that can be stored in them at all. */
540 #define HARD_REGNO_NREGS(REGNO, MODE) \
541 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
542 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
544 #ifndef SUPPORT_SUN_FPA
546 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
547 On the 68000, the cpu registers can hold any mode but the 68881 registers
548 can hold only SFmode or DFmode. */
550 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
552 && !((REGNO) < 8 && (REGNO) + GET_MODE_SIZE (MODE) / 4 > 8)) \
553 || ((REGNO) >= 16 && (REGNO) < 24 \
554 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
555 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
556 && GET_MODE_UNIT_SIZE (MODE) <= 12))
558 #else /* defined SUPPORT_SUN_FPA */
560 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
561 On the 68000, the cpu registers can hold any mode but the 68881 registers
562 can hold only SFmode or DFmode. However, the Sun FPA register can
563 (apparently) hold whatever you feel like putting in them.
564 If using the fpa, don't put a double in d7/a0. */
566 /* ??? This is confused. The check to prohibit d7/a0 overlaps should always
567 be enabled regardless of whether TARGET_FPA is specified. It isn't clear
568 what the other d/a register checks are for. Every check using REGNO
569 actually needs to use a range, e.g. 24>=X<56 not <56. There is probably
570 no one using this code anymore.
571 This code used to be used to suppress register usage for the 68881 by
572 saying that the 68881 registers couldn't hold values of any mode if there
573 was no 68881. This was wrong, because reload (etc.) will still try
574 to save and restore call-saved registers during, for instance, non-local
576 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
579 && GET_MODE_CLASS ((MODE)) != MODE_INT \
580 && GET_MODE_UNIT_SIZE ((MODE)) > 4 \
581 && (REGNO) < 8 && (REGNO) + GET_MODE_SIZE ((MODE)) / 4 > 8 \
582 && (REGNO) % (GET_MODE_UNIT_SIZE ((MODE)) / 4) != 0)) \
583 || ((REGNO) >= 16 && (REGNO) < 24 \
584 ? ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
585 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
586 && GET_MODE_UNIT_SIZE (MODE) <= 12) \
587 : ((REGNO) < 56 ? TARGET_FPA && GET_MODE_UNIT_SIZE (MODE) <= 8 : 0)))
589 #endif /* defined SUPPORT_SUN_FPA */
591 /* Value is 1 if it is a good idea to tie two pseudo registers
592 when one has mode MODE1 and one has mode MODE2.
593 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
594 for any hard reg, then this must be 0 for correct output. */
595 #define MODES_TIEABLE_P(MODE1, MODE2) \
597 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
598 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
599 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
600 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
602 /* Specify the registers used for certain standard purposes.
603 The values of these macros are register numbers. */
605 /* m68000 pc isn't overloaded on a register. */
606 /* #define PC_REGNUM */
608 /* Register to use for pushing function arguments. */
609 #define STACK_POINTER_REGNUM 15
611 /* Base register for access to local variables of the function. */
612 #define FRAME_POINTER_REGNUM 14
614 /* Value should be nonzero if functions must have frame pointers.
615 Zero means the frame pointer need not be set up (and parms
616 may be accessed via the stack pointer) in functions that seem suitable.
617 This is computed in `reload', in reload1.c. */
618 #define FRAME_POINTER_REQUIRED 0
620 /* Base register for access to arguments of the function. */
621 #define ARG_POINTER_REGNUM 14
623 /* Register in which static-chain is passed to a function. */
624 #define STATIC_CHAIN_REGNUM 8
626 /* Register in which address to store a structure value
627 is passed to a function. */
628 #define STRUCT_VALUE_REGNUM 9
630 /* Define the classes of registers for register constraints in the
631 machine description. Also define ranges of constants.
633 One of the classes must always be named ALL_REGS and include all hard regs.
634 If there is more than one class, another class must be named NO_REGS
635 and contain no registers.
637 The name GENERAL_REGS must be the name of a class (or an alias for
638 another name such as ALL_REGS). This is the class of registers
639 that is allowed by "g" or "r" in a register constraint.
640 Also, registers outside this class are allocated only when
641 instructions express preferences for them.
643 The classes must be numbered in nondecreasing order; that is,
644 a larger-numbered class must never be contained completely
645 in a smaller-numbered class.
647 For any two classes, it is very desirable that there be another
648 class that represents their union. */
650 /* The 68000 has three kinds of registers, so eight classes would be
651 a complete set. One of them is not needed. */
653 #ifndef SUPPORT_SUN_FPA
658 GENERAL_REGS, DATA_OR_FP_REGS,
659 ADDR_OR_FP_REGS, ALL_REGS,
662 #define N_REG_CLASSES (int) LIM_REG_CLASSES
664 /* Give names of register classes as strings for dump file. */
666 #define REG_CLASS_NAMES \
667 { "NO_REGS", "DATA_REGS", \
668 "ADDR_REGS", "FP_REGS", \
669 "GENERAL_REGS", "DATA_OR_FP_REGS", \
670 "ADDR_OR_FP_REGS", "ALL_REGS" }
672 /* Define which registers fit in which classes.
673 This is an initializer for a vector of HARD_REG_SET
674 of length N_REG_CLASSES. */
676 #define REG_CLASS_CONTENTS \
678 {0x00000000}, /* NO_REGS */ \
679 {0x000000ff}, /* DATA_REGS */ \
680 {0x0000ff00}, /* ADDR_REGS */ \
681 {0x00ff0000}, /* FP_REGS */ \
682 {0x0000ffff}, /* GENERAL_REGS */ \
683 {0x00ff00ff}, /* DATA_OR_FP_REGS */ \
684 {0x00ffff00}, /* ADDR_OR_FP_REGS */ \
685 {0x00ffffff}, /* ALL_REGS */ \
688 /* The same information, inverted:
689 Return the class number of the smallest class containing
690 reg number REGNO. This could be a conditional expression
691 or could index an array. */
693 #define REGNO_REG_CLASS(REGNO) (((REGNO)>>3)+1)
695 #else /* defined SUPPORT_SUN_FPA */
698 * Notes on final choices:
700 * 1) Didn't feel any need to union-ize LOW_FPA_REGS with anything
702 * 2) Removed all unions that involve address registers with
703 * floating point registers (left in unions of address and data with
705 * 3) Defined GENERAL_REGS as ADDR_OR_DATA_REGS.
706 * 4) Defined ALL_REGS as FPA_OR_FP_OR_GENERAL_REGS.
707 * 4) Left in everything else.
709 enum reg_class { NO_REGS, LO_FPA_REGS, FPA_REGS, FP_REGS,
710 FP_OR_FPA_REGS, DATA_REGS, DATA_OR_FPA_REGS, DATA_OR_FP_REGS,
711 DATA_OR_FP_OR_FPA_REGS, ADDR_REGS, GENERAL_REGS,
712 GENERAL_OR_FPA_REGS, GENERAL_OR_FP_REGS, ALL_REGS,
715 #define N_REG_CLASSES (int) LIM_REG_CLASSES
717 /* Give names of register classes as strings for dump file. */
719 #define REG_CLASS_NAMES \
720 { "NO_REGS", "LO_FPA_REGS", "FPA_REGS", "FP_REGS", \
721 "FP_OR_FPA_REGS", "DATA_REGS", "DATA_OR_FPA_REGS", "DATA_OR_FP_REGS", \
722 "DATA_OR_FP_OR_FPA_REGS", "ADDR_REGS", "GENERAL_REGS", \
723 "GENERAL_OR_FPA_REGS", "GENERAL_OR_FP_REGS", "ALL_REGS" }
725 /* Define which registers fit in which classes.
726 This is an initializer for a vector of HARD_REG_SET
727 of length N_REG_CLASSES. */
729 #define REG_CLASS_CONTENTS \
731 {0, 0}, /* NO_REGS */ \
732 {0xff000000, 0x000000ff}, /* LO_FPA_REGS */ \
733 {0xff000000, 0x00ffffff}, /* FPA_REGS */ \
734 {0x00ff0000, 0x00000000}, /* FP_REGS */ \
735 {0xffff0000, 0x00ffffff}, /* FP_OR_FPA_REGS */ \
736 {0x000000ff, 0x00000000}, /* DATA_REGS */ \
737 {0xff0000ff, 0x00ffffff}, /* DATA_OR_FPA_REGS */ \
738 {0x00ff00ff, 0x00000000}, /* DATA_OR_FP_REGS */ \
739 {0xffff00ff, 0x00ffffff}, /* DATA_OR_FP_OR_FPA_REGS */\
740 {0x0000ff00, 0x00000000}, /* ADDR_REGS */ \
741 {0x0000ffff, 0x00000000}, /* GENERAL_REGS */ \
742 {0xff00ffff, 0x00ffffff}, /* GENERAL_OR_FPA_REGS */\
743 {0x00ffffff, 0x00000000}, /* GENERAL_OR_FP_REGS */\
744 {0xffffffff, 0x00ffffff}, /* ALL_REGS */ \
747 /* The same information, inverted:
748 Return the class number of the smallest class containing
749 reg number REGNO. This could be a conditional expression
750 or could index an array. */
752 extern const enum reg_class regno_reg_class[];
753 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)>>3])
755 #endif /* SUPPORT_SUN_FPA */
757 /* The class value for index registers, and the one for base regs. */
759 #define INDEX_REG_CLASS GENERAL_REGS
760 #define BASE_REG_CLASS ADDR_REGS
762 /* Get reg_class from a letter such as appears in the machine description.
763 We do a trick here to modify the effective constraints on the
764 machine description; we zorch the constraint letters that aren't
765 appropriate for a specific target. This allows us to guarantee
766 that a specific kind of register will not be used for a given target
767 without fiddling with the register classes above. */
769 #ifndef SUPPORT_SUN_FPA
771 #define REG_CLASS_FROM_LETTER(C) \
772 ((C) == 'a' ? ADDR_REGS : \
773 ((C) == 'd' ? DATA_REGS : \
774 ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \
778 #else /* defined SUPPORT_SUN_FPA */
780 #define REG_CLASS_FROM_LETTER(C) \
781 ((C) == 'a' ? ADDR_REGS : \
782 ((C) == 'd' ? DATA_REGS : \
783 ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \
785 ((C) == 'x' ? (TARGET_FPA ? FPA_REGS : \
787 ((C) == 'y' ? (TARGET_FPA ? LO_FPA_REGS : \
791 #endif /* defined SUPPORT_SUN_FPA */
793 /* The letters I, J, K, L and M in a register constraint string
794 can be used to stand for particular ranges of immediate operands.
795 This macro defines what the ranges are.
796 C is the letter, and VALUE is a constant value.
797 Return 1 if VALUE is in the range specified by C.
799 For the 68000, `I' is used for the range 1 to 8
800 allowed as immediate shift counts and in addq.
801 `J' is used for the range of signed numbers that fit in 16 bits.
802 `K' is for numbers that moveq can't handle.
803 `L' is for range -8 to -1, range of values that can be added with subq.
804 `M' is for numbers that moveq+notb can't handle.
805 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate.
806 'O' is for 16 (for rotate using swap).
807 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */
809 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
810 ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \
811 (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
812 (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
813 (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \
814 (C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \
815 (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \
816 (C) == 'O' ? (VALUE) == 16 : \
817 (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0)
820 * A small bit of explanation:
821 * "G" defines all of the floating constants that are *NOT* 68881
822 * constants. this is so 68881 constants get reloaded and the
823 * fpmovecr is used. "H" defines *only* the class of constants that
824 * the fpa can use, because these can be gotten at in any fpa
825 * instruction and there is no need to force reloads.
827 #ifndef SUPPORT_SUN_FPA
828 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
829 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 )
830 #else /* defined SUPPORT_SUN_FPA */
831 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
832 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : \
833 (C) == 'H' ? (TARGET_FPA && standard_sun_fpa_constant_p (VALUE)) : 0)
834 #endif /* defined SUPPORT_SUN_FPA */
836 /* A C expression that defines the optional machine-dependent constraint
837 letters that can be used to segregate specific types of operands,
838 usually memory references, for the target machine. It should return 1 if
839 VALUE corresponds to the operand type represented by the constraint letter
840 C. If C is not defined as an extra constraint, the value returned should
841 be 0 regardless of VALUE. */
843 /* Letters in the range `Q' through `U' may be defined in a
844 machine-dependent fashion to stand for arbitrary operand types.
845 The machine description macro `EXTRA_CONSTRAINT' is passed the
846 operand as its first argument and the constraint letter as its
849 `Q' means address register indirect addressing mode.
850 `S' is for operands that satisfy 'm' when -mpcrel is in effect.
851 `T' is for operands that satisfy 's' when -mpcrel is not in effect. */
853 #define EXTRA_CONSTRAINT(OP,CODE) \
856 && GET_CODE (OP) == MEM \
857 && (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
858 || GET_CODE (XEXP (OP, 0)) == LABEL_REF \
859 || GET_CODE (XEXP (OP, 0)) == CONST)) \
863 && (GET_CODE (OP) == SYMBOL_REF \
864 || GET_CODE (OP) == LABEL_REF \
865 || GET_CODE (OP) == CONST)) \
868 ? (GET_CODE (OP) == MEM \
869 && GET_CODE (XEXP (OP, 0)) == REG) \
873 /* Given an rtx X being reloaded into a reg required to be
874 in class CLASS, return the class of reg to actually use.
875 In general this is just CLASS; but on some machines
876 in some cases it is preferable to use a more restrictive class.
877 On the 68000 series, use a data reg if possible when the
878 value is a constant in the range where moveq could be used
879 and we ensure that QImodes are reloaded into data regs. */
881 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
882 ((GET_CODE (X) == CONST_INT \
883 && (unsigned) (INTVAL (X) + 0x80) < 0x100 \
884 && (CLASS) != ADDR_REGS) \
886 : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \
888 : (GET_CODE (X) == CONST_DOUBLE \
889 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
890 ? (TARGET_68881 && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \
891 ? FP_REGS : NO_REGS) \
893 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
894 || GET_CODE (X) == LABEL_REF)) \
898 /* Force QImode output reloads from subregs to be allocated to data regs,
899 since QImode stores from address regs are not supported. We make the
900 assumption that if the class is not ADDR_REGS, then it must be a superset
903 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
904 (((MODE) == QImode && (CLASS) != ADDR_REGS) \
908 /* Return the maximum number of consecutive registers
909 needed to represent mode MODE in a register of class CLASS. */
910 /* On the 68000, this is the size of MODE in words,
911 except in the FP regs, where a single reg is always enough. */
912 #ifndef SUPPORT_SUN_FPA
914 #define CLASS_MAX_NREGS(CLASS, MODE) \
915 ((CLASS) == FP_REGS ? 1 \
916 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
918 /* Moves between fp regs and other regs are two insns. */
919 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
920 (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
921 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
924 #else /* defined SUPPORT_SUN_FPA */
926 #define CLASS_MAX_NREGS(CLASS, MODE) \
927 ((CLASS) == FP_REGS || (CLASS) == FPA_REGS || (CLASS) == LO_FPA_REGS ? 1 \
928 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
930 /* Moves between fp regs and other regs are two insns. */
931 /* Likewise for high fpa regs and other regs. */
932 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
933 ((((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
934 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
935 || ((CLASS1) == FPA_REGS && (CLASS2) != FPA_REGS) \
936 || ((CLASS2) == FPA_REGS && (CLASS1) != FPA_REGS)) \
939 #endif /* define SUPPORT_SUN_FPA */
941 /* Stack layout; function entry, exit and calling. */
943 /* Define this if pushing a word on the stack
944 makes the stack pointer a smaller address. */
945 #define STACK_GROWS_DOWNWARD
947 /* Nonzero if we need to generate stack-probe insns.
948 On most systems they are not needed.
949 When they are needed, define this as the stack offset to probe at. */
952 /* Define this if the nominal address of the stack frame
953 is at the high-address end of the local variables;
954 that is, each additional local variable allocated
955 goes at a more negative offset in the frame. */
956 #define FRAME_GROWS_DOWNWARD
958 /* Offset within stack frame to start allocating local variables at.
959 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
960 first local allocated. Otherwise, it is the offset to the BEGINNING
961 of the first local allocated. */
962 #define STARTING_FRAME_OFFSET 0
964 /* If we generate an insn to push BYTES bytes,
965 this says how many the stack pointer really advances by.
966 On the 68000, sp@- in a byte insn really pushes a word.
967 On the 5200 (coldfire), sp@- in a byte insn pushes just a byte. */
968 #define PUSH_ROUNDING(BYTES) (TARGET_5200 ? BYTES : ((BYTES) + 1) & ~1)
970 /* We want to avoid trying to push bytes. */
971 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
972 (move_by_pieces_ninsns (SIZE, ALIGN) < MOVE_RATIO \
973 && (((SIZE) >=16 && (ALIGN) >= 16) || (TARGET_5200)))
975 /* Offset of first parameter from the argument pointer register value. */
976 #define FIRST_PARM_OFFSET(FNDECL) 8
978 /* Value is the number of byte of arguments automatically
979 popped when returning from a subroutine call.
980 FUNDECL is the declaration node of the function (as a tree),
981 FUNTYPE is the data type of the function (as a tree),
982 or for a library call it is an identifier node for the subroutine name.
983 SIZE is the number of bytes of arguments passed on the stack.
985 On the 68000, the RTS insn cannot pop anything.
986 On the 68010, the RTD insn may be used to pop them if the number
987 of args is fixed, but if the number is variable then the caller
988 must pop them all. RTD can't be used for library calls now
989 because the library is compiled with the Unix compiler.
990 Use of RTD is a selectable option, since it is incompatible with
991 standard Unix calling sequences. If the option is not selected,
992 the caller must always pop the args. */
994 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
995 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \
996 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
997 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
998 == void_type_node))) \
1001 /* Define how to find the value returned by a function.
1002 VALTYPE is the data type of the value (as a tree).
1003 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1004 otherwise, FUNC is 0. */
1006 /* On the 68000 the return value is in D0 regardless. */
1008 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1009 gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
1011 /* Define how to find the value returned by a library function
1012 assuming the value has mode MODE. */
1014 /* On the 68000 the return value is in D0 regardless. */
1016 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
1018 /* 1 if N is a possible register number for a function value.
1019 On the 68000, d0 is the only register thus used. */
1021 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
1023 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
1024 more than one register. */
1026 #define NEEDS_UNTYPED_CALL 0
1028 /* Define this if PCC uses the nonreentrant convention for returning
1029 structure and union values. */
1031 #define PCC_STATIC_STRUCT_RETURN
1033 /* 1 if N is a possible register number for function argument passing.
1034 On the 68000, no registers are used in this way. */
1036 #define FUNCTION_ARG_REGNO_P(N) 0
1038 /* Define a data type for recording info about an argument list
1039 during the scan of that argument list. This data type should
1040 hold all necessary information about the function itself
1041 and about the args processed so far, enough to enable macros
1042 such as FUNCTION_ARG to determine where the next arg should go.
1044 On the m68k, this is a single integer, which is a number of bytes
1045 of arguments scanned so far. */
1047 #define CUMULATIVE_ARGS int
1049 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1050 for a call to a function whose data type is FNTYPE.
1051 For a library call, FNTYPE is 0.
1053 On the m68k, the offset starts at 0. */
1055 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1058 /* Update the data in CUM to advance over an argument
1059 of mode MODE and data type TYPE.
1060 (TYPE is null for libcalls where that information may not be available.) */
1062 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1063 ((CUM) += ((MODE) != BLKmode \
1064 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
1065 : (int_size_in_bytes (TYPE) + 3) & ~3))
1067 /* Define where to put the arguments to a function.
1068 Value is zero to push the argument on the stack,
1069 or a hard register in which to store the argument.
1071 MODE is the argument's machine mode.
1072 TYPE is the data type of the argument (as a tree).
1073 This is null for libcalls where that information may
1075 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1076 the preceding args and about the function being called.
1077 NAMED is nonzero if this argument is a named parameter
1078 (otherwise it is an extra parameter matching an ellipsis). */
1080 /* On the 68000 all args are pushed, except if -mregparm is specified
1081 then the first two words of arguments are passed in d0, d1.
1082 *NOTE* -mregparm does not work.
1083 It exists only to test register calling conventions. */
1085 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1086 ((TARGET_REGPARM && (CUM) < 8) ? gen_rtx_REG ((MODE), (CUM) / 4) : 0)
1088 /* For an arg passed partly in registers and partly in memory,
1089 this is the number of registers used.
1090 For args passed entirely in registers or entirely in memory, zero. */
1092 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1093 ((TARGET_REGPARM && (CUM) < 8 \
1094 && 8 < ((CUM) + ((MODE) == BLKmode \
1095 ? int_size_in_bytes (TYPE) \
1096 : GET_MODE_SIZE (MODE)))) \
1097 ? 2 - (CUM) / 4 : 0)
1099 /* Output assembler code to FILE to increment profiler label # LABELNO
1100 for profiling a function entry. */
1102 #define FUNCTION_PROFILER(FILE, LABELNO) \
1103 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO))
1105 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1106 the stack pointer does not matter. The value is tested only in
1107 functions that have frame pointers.
1108 No definition is equivalent to always zero. */
1110 #define EXIT_IGNORE_STACK 1
1112 /* This is a hook for other tm files to change. */
1113 /* #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) */
1115 /* Determine if the epilogue should be output as RTL.
1116 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1117 #define USE_RETURN_INSN use_return_insn ()
1119 /* Store in the variable DEPTH the initial difference between the
1120 frame pointer reg contents and the stack pointer reg contents,
1121 as of the start of the function body. This depends on the layout
1122 of the fixed parts of the stack frame and on how registers are saved.
1124 On the 68k, if we have a frame, we must add one word to its length
1125 to allow for the place that a6 is stored when we do have a frame pointer.
1126 Otherwise, we would need to compute the offset from the frame pointer
1127 of a local variable as a function of frame_pointer_needed, which
1130 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
1133 for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \
1134 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1136 for (regno = 0; regno < 16; regno++) \
1137 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1139 if (flag_pic && current_function_uses_pic_offset_table) \
1141 (DEPTH) = (offset + ((get_frame_size () + 3) & -4) \
1142 + (get_frame_size () == 0 ? 0 : 4)); \
1145 /* Output assembler code for a block containing the constant parts
1146 of a trampoline, leaving space for the variable parts. */
1148 /* On the 68k, the trampoline looks like this:
1152 WARNING: Targets that may run on 68040+ cpus must arrange for
1153 the instruction cache to be flushed. Previous incarnations of
1154 the m68k trampoline code attempted to get around this by either
1155 using an out-of-line transfer function or pc-relative data, but
1156 the fact remains that the code to jump to the transfer function
1157 or the code to load the pc-relative data needs to be flushed
1158 just as much as the "variable" portion of the trampoline.
1159 Recognizing that a cache flush is going to be required anyway,
1160 dispense with such notions and build a smaller trampoline. */
1162 /* Since more instructions are required to move a template into
1163 place than to create it on the spot, don't use a template. */
1165 /* Length in units of the trampoline for entering a nested function. */
1167 #define TRAMPOLINE_SIZE 12
1169 /* Alignment required for a trampoline in bits. */
1171 #define TRAMPOLINE_ALIGNMENT 16
1173 /* Targets redefine this to invoke code to either flush the cache,
1174 or enable stack execution (or both). */
1176 #ifndef FINALIZE_TRAMPOLINE
1177 #define FINALIZE_TRAMPOLINE(TRAMP)
1180 /* Emit RTL insns to initialize the variable parts of a trampoline.
1181 FNADDR is an RTX for the address of the function's pure code.
1182 CXT is an RTX for the static chain value for the function.
1184 We generate a two-instructions program at address TRAMP :
1188 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1190 emit_move_insn (gen_rtx_MEM (HImode, TRAMP), GEN_INT(0x207C)); \
1191 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \
1192 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \
1194 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \
1195 FINALIZE_TRAMPOLINE(TRAMP); \
1198 /* This is the library routine that is used
1199 to transfer control from the trampoline
1200 to the actual nested function.
1201 It is defined for backward compatibility,
1202 for linking with object code that used the old
1203 trampoline definition. */
1205 /* A colon is used with no explicit operands
1206 to cause the template string to be scanned for %-constructs. */
1207 /* The function name __transfer_from_trampoline is not actually used.
1208 The function definition just permits use of "asm with operands"
1209 (though the operand list is empty). */
1210 #define TRANSFER_FROM_TRAMPOLINE \
1212 __transfer_from_trampoline () \
1214 register char *a0 asm ("%a0"); \
1215 asm (GLOBAL_ASM_OP "___trampoline"); \
1216 asm ("___trampoline:"); \
1217 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \
1218 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \
1222 /* Addressing modes, and classification of registers for them. */
1224 #define HAVE_POST_INCREMENT 1
1225 /* #define HAVE_POST_DECREMENT 0 */
1227 #define HAVE_PRE_DECREMENT 1
1228 /* #define HAVE_PRE_INCREMENT 0 */
1230 /* Macros to check register numbers against specific register classes. */
1232 /* These assume that REGNO is a hard or pseudo reg number.
1233 They give nonzero only if REGNO is a hard reg of the suitable class
1234 or a pseudo reg currently allocated to a suitable hard reg.
1235 Since they use reg_renumber, they are safe only once reg_renumber
1236 has been allocated, which happens in local-alloc.c. */
1238 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1239 ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
1240 #define REGNO_OK_FOR_BASE_P(REGNO) \
1241 (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
1242 #define REGNO_OK_FOR_DATA_P(REGNO) \
1243 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
1244 #define REGNO_OK_FOR_FP_P(REGNO) \
1245 (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
1246 #ifdef SUPPORT_SUN_FPA
1247 #define REGNO_OK_FOR_FPA_P(REGNO) \
1248 (((REGNO) >= 24 && (REGNO) < 56) || (reg_renumber[REGNO] >= 24 && reg_renumber[REGNO] < 56))
1251 /* Now macros that check whether X is a register and also,
1252 strictly, whether it is in a specified class.
1254 These macros are specific to the 68000, and may be used only
1255 in code for printing assembler insns and in conditions for
1256 define_optimization. */
1258 /* 1 if X is a data register. */
1260 #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
1262 /* 1 if X is an fp register. */
1264 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1266 /* 1 if X is an address register */
1268 #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
1270 #ifdef SUPPORT_SUN_FPA
1271 /* 1 if X is a register in the Sun FPA. */
1272 #define FPA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FPA_P (REGNO (X)))
1274 /* Answer must be no if we don't have an FPA. */
1275 #define FPA_REG_P(X) 0
1278 /* Maximum number of registers that can appear in a valid memory address. */
1280 #define MAX_REGS_PER_ADDRESS 2
1282 /* Recognize any constant value that is a valid address. */
1284 #define CONSTANT_ADDRESS_P(X) \
1285 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1286 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1287 || GET_CODE (X) == HIGH)
1289 /* Nonzero if the constant value X is a legitimate general operand.
1290 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1292 #define LEGITIMATE_CONSTANT_P(X) 1
1294 /* Nonzero if the constant value X is a legitimate general operand
1295 when generating PIC code. It is given that flag_pic is on and
1296 that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1298 PCREL_GENERAL_OPERAND_OK makes reload accept addresses that are
1299 accepted by insn predicates, but which would otherwise fail the
1300 `general_operand' test. */
1302 #ifndef REG_OK_STRICT
1303 #define PCREL_GENERAL_OPERAND_OK 0
1305 #define PCREL_GENERAL_OPERAND_OK (TARGET_PCREL)
1308 #define LEGITIMATE_PIC_OPERAND_P(X) \
1309 ((! symbolic_operand (X, VOIDmode) \
1310 && ! (GET_CODE (X) == CONST_DOUBLE && mem_for_const_double (X) != 0 \
1311 && GET_CODE (mem_for_const_double (X)) == MEM \
1312 && symbolic_operand (XEXP (mem_for_const_double (X), 0), \
1314 || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \
1315 || PCREL_GENERAL_OPERAND_OK)
1317 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1318 and check its validity for a certain class.
1319 We have two alternate definitions for each of them.
1320 The usual definition accepts all pseudo regs; the other rejects
1321 them unless they have been allocated suitable hard regs.
1322 The symbol REG_OK_STRICT causes the latter definition to be used.
1324 Most source files want to accept pseudo regs in the hope that
1325 they will get allocated to the class that the insn wants them to be in.
1326 Source files for reload pass need to be strict.
1327 After reload, it makes no difference, since pseudo regs have
1328 been eliminated by then. */
1330 #ifndef REG_OK_STRICT
1332 /* Nonzero if X is a hard reg that can be used as an index
1333 or if it is a pseudo reg. */
1334 #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
1335 /* Nonzero if X is a hard reg that can be used as a base reg
1336 or if it is a pseudo reg. */
1337 #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
1341 /* Nonzero if X is a hard reg that can be used as an index. */
1342 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1343 /* Nonzero if X is a hard reg that can be used as a base reg. */
1344 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1348 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1349 that is a valid memory address for an instruction.
1350 The MODE argument is the machine mode for the MEM expression
1351 that wants to use this address.
1353 When generating PIC, an address involving a SYMBOL_REF is legitimate
1354 if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF.
1355 We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses,
1356 and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF.
1358 Likewise for a LABEL_REF when generating PIC.
1360 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1362 /* Allow SUBREG everywhere we allow REG. This results in better code. It
1363 also makes function inlining work when inline functions are called with
1364 arguments that are SUBREGs. */
1366 #define LEGITIMATE_BASE_REG_P(X) \
1367 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1368 || (GET_CODE (X) == SUBREG \
1369 && GET_CODE (SUBREG_REG (X)) == REG \
1370 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1372 #define INDIRECTABLE_1_ADDRESS_P(X) \
1373 ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \
1374 || LEGITIMATE_BASE_REG_P (X) \
1375 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
1376 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
1377 || (GET_CODE (X) == PLUS \
1378 && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
1379 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1381 || ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) \
1382 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1383 && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \
1384 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1385 && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF))
1387 #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
1388 { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
1390 /* Only labels on dispatch tables are valid for indexing from. */
1391 #define GO_IF_INDEXABLE_BASE(X, ADDR) \
1393 if (GET_CODE (X) == LABEL_REF \
1394 && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \
1395 && GET_CODE (temp) == JUMP_INSN \
1396 && (GET_CODE (PATTERN (temp)) == ADDR_VEC \
1397 || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \
1399 if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; }
1401 #define GO_IF_INDEXING(X, ADDR) \
1402 { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
1403 { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
1404 if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
1405 { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
1407 #define GO_IF_INDEXED_ADDRESS(X, ADDR) \
1408 { GO_IF_INDEXING (X, ADDR); \
1409 if (GET_CODE (X) == PLUS) \
1410 { if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1411 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)) \
1412 { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \
1413 if (GET_CODE (XEXP (X, 0)) == CONST_INT \
1414 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)) \
1415 { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
1417 /* coldfire/5200 does not allow HImode index registers. */
1418 #define LEGITIMATE_INDEX_REG_P(X) \
1419 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1421 && GET_CODE (X) == SIGN_EXTEND \
1422 && GET_CODE (XEXP (X, 0)) == REG \
1423 && GET_MODE (XEXP (X, 0)) == HImode \
1424 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
1425 || (GET_CODE (X) == SUBREG \
1426 && GET_CODE (SUBREG_REG (X)) == REG \
1427 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1429 #define LEGITIMATE_INDEX_P(X) \
1430 (LEGITIMATE_INDEX_REG_P (X) \
1431 || ((TARGET_68020 || TARGET_5200) && GET_CODE (X) == MULT \
1432 && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
1433 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1434 && (INTVAL (XEXP (X, 1)) == 2 \
1435 || INTVAL (XEXP (X, 1)) == 4 \
1436 || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_5200))))
1438 /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */
1439 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1440 { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
1441 GO_IF_INDEXED_ADDRESS (X, ADDR); \
1442 if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \
1443 && LEGITIMATE_INDEX_P (XEXP (X, 0)) \
1444 && GET_CODE (XEXP (X, 1)) == LABEL_REF) \
1447 /* Don't call memory_address_noforce for the address to fetch
1448 the switch offset. This address is ok as it stands (see above),
1449 but memory_address_noforce would alter it. */
1450 #define PIC_CASE_VECTOR_ADDRESS(index) index
1452 /* Try machine-dependent ways of modifying an illegitimate address
1453 to be legitimate. If we find one, return the new, valid address.
1454 This macro is used in only one place: `memory_address' in explow.c.
1456 OLDX is the address as it was before break_out_memory_refs was called.
1457 In some cases it is useful to look at this to decide what needs to be done.
1459 MODE and WIN are passed so that this macro can use
1460 GO_IF_LEGITIMATE_ADDRESS.
1462 It is always safe for this macro to do nothing. It exists to recognize
1463 opportunities to optimize the output.
1465 For the 68000, we handle X+REG by loading X into a register R and
1466 using R+REG. R will go in an address reg and indexing will be used.
1467 However, if REG is a broken-out memory address or multiplication,
1468 nothing needs to be done because REG can certainly go in an address reg. */
1470 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1471 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1472 { register int ch = (X) != (OLDX); \
1473 if (GET_CODE (X) == PLUS) \
1475 if (GET_CODE (XEXP (X, 0)) == MULT) \
1476 { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \
1477 if (GET_CODE (XEXP (X, 1)) == MULT) \
1478 { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \
1479 if (ch && GET_CODE (XEXP (X, 1)) == REG \
1480 && GET_CODE (XEXP (X, 0)) == REG) \
1482 if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
1483 if (GET_CODE (XEXP (X, 0)) == REG \
1484 || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
1485 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1486 && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
1487 { register rtx temp = gen_reg_rtx (Pmode); \
1488 register rtx val = force_operand (XEXP (X, 1), 0); \
1489 emit_move_insn (temp, val); \
1491 XEXP (X, 1) = temp; \
1493 else if (GET_CODE (XEXP (X, 1)) == REG \
1494 || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
1495 && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
1496 && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
1497 { register rtx temp = gen_reg_rtx (Pmode); \
1498 register rtx val = force_operand (XEXP (X, 0), 0); \
1499 emit_move_insn (temp, val); \
1501 XEXP (X, 0) = temp; \
1504 /* Go to LABEL if ADDR (a legitimate address expression)
1505 has an effect that depends on the machine mode it is used for.
1506 On the 68000, only predecrement and postincrement address depend thus
1507 (the amount of decrement or increment being the length of the operand). */
1509 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1510 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL
1512 /* Specify the machine mode that this machine uses
1513 for the index in the tablejump instruction. */
1514 #define CASE_VECTOR_MODE HImode
1516 /* Define as C expression which evaluates to nonzero if the tablejump
1517 instruction expects the table to contain offsets from the address of the
1519 Do not define this if the table should contain absolute addresses. */
1520 #define CASE_VECTOR_PC_RELATIVE 1
1522 /* Define this as 1 if `char' should by default be signed; else as 0. */
1523 #define DEFAULT_SIGNED_CHAR 1
1525 /* Don't cse the address of the function being compiled. */
1526 #define NO_RECURSIVE_FUNCTION_CSE
1528 /* Max number of bytes we can move from memory to memory
1529 in one reasonably fast instruction. */
1532 /* Nonzero if access to memory by bytes is slow and undesirable. */
1533 #define SLOW_BYTE_ACCESS 0
1535 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1536 is done just by pretending it is already truncated. */
1537 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1539 /* We assume that the store-condition-codes instructions store 0 for false
1540 and some other value for true. This is the value stored for true. */
1542 #define STORE_FLAG_VALUE (-1)
1544 /* When a prototype says `char' or `short', really pass an `int'. */
1545 #define PROMOTE_PROTOTYPES 1
1547 /* Specify the machine mode that pointers have.
1548 After generation of rtl, the compiler makes no further distinction
1549 between pointers and any other objects of this machine mode. */
1550 #define Pmode SImode
1552 /* A function address in a call instruction
1553 is a byte address (for indexing purposes)
1554 so give the MEM rtx a byte's mode. */
1555 #define FUNCTION_MODE QImode
1557 /* Compute the cost of computing a constant rtl expression RTX
1558 whose rtx-code is CODE. The body of this macro is a portion
1559 of a switch statement. If the code is computed here,
1560 return it with a return statement. Otherwise, break from the switch. */
1562 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1564 /* Constant zero is super cheap due to clr instruction. */ \
1565 if (RTX == const0_rtx) return 0; \
1566 /* if ((OUTER_CODE) == SET) */ \
1567 return const_int_cost(RTX); \
1572 case CONST_DOUBLE: \
1575 /* Compute the cost of various arithmetic operations.
1576 These are vaguely right for a 68020. */
1577 /* The costs for long multiply have been adjusted to
1578 work properly in synth_mult on the 68020,
1579 relative to an average of the time for add and the time for shift,
1580 taking away a little more because sometimes move insns are needed. */
1581 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */
1582 #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : 13)
1583 #define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : 5)
1584 #define DIVW_COST (TARGET_68020 ? 27 : 12)
1586 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1588 /* An lea costs about three times as much as a simple add. */ \
1589 if (GET_MODE (X) == SImode \
1590 && GET_CODE (XEXP (X, 1)) == REG \
1591 && GET_CODE (XEXP (X, 0)) == MULT \
1592 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1593 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1594 && (INTVAL (XEXP (XEXP (X, 0), 1)) == 2 \
1595 || INTVAL (XEXP (XEXP (X, 0), 1)) == 4 \
1596 || INTVAL (XEXP (XEXP (X, 0), 1)) == 8)) \
1597 return COSTS_N_INSNS (3); /* lea an@(dx:l:i),am */ \
1603 return COSTS_N_INSNS(1); \
1604 if (! TARGET_68020) \
1606 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
1608 if (INTVAL (XEXP (X, 1)) < 16) \
1609 return COSTS_N_INSNS (2) + INTVAL (XEXP (X, 1)) / 2; \
1611 /* We're using clrw + swap for these cases. */ \
1612 return COSTS_N_INSNS (4) + (INTVAL (XEXP (X, 1)) - 16) / 2; \
1614 return COSTS_N_INSNS (10); /* worst case */ \
1616 /* A shift by a big integer takes an extra instruction. */ \
1617 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1618 && (INTVAL (XEXP (X, 1)) == 16)) \
1619 return COSTS_N_INSNS (2); /* clrw;swap */ \
1620 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1621 && !(INTVAL (XEXP (X, 1)) > 0 \
1622 && INTVAL (XEXP (X, 1)) <= 8)) \
1623 return COSTS_N_INSNS (3); /* lsr #i,dn */ \
1626 if ((GET_CODE (XEXP (X, 0)) == ZERO_EXTEND \
1627 || GET_CODE (XEXP (X, 0)) == SIGN_EXTEND) \
1628 && GET_MODE (X) == SImode) \
1629 return COSTS_N_INSNS (MULW_COST); \
1630 if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \
1631 return COSTS_N_INSNS (MULW_COST); \
1633 return COSTS_N_INSNS (MULL_COST); \
1638 if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \
1639 return COSTS_N_INSNS (DIVW_COST); /* div.w */ \
1640 return COSTS_N_INSNS (43); /* div.l */
1642 /* Tell final.c how to eliminate redundant test instructions. */
1644 /* Here we define machine-dependent flags and fields in cc_status
1645 (see `conditions.h'). */
1647 /* Set if the cc value is actually in the 68881, so a floating point
1648 conditional branch must be output. */
1649 #define CC_IN_68881 04000
1651 /* Store in cc_status the expressions that the condition codes will
1652 describe after execution of an instruction whose pattern is EXP.
1653 Do not alter them if the instruction would not alter the cc's. */
1655 /* On the 68000, all the insns to store in an address register fail to
1656 set the cc's. However, in some cases these instructions can make it
1657 possibly invalid to use the saved cc's. In those cases we clear out
1658 some or all of the saved cc's so they won't be used. */
1660 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
1662 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
1663 { if (cc_prev_status.flags & CC_IN_68881) \
1665 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
1669 /* Control the assembler format that we output. */
1671 /* Output at beginning of assembler file. */
1673 #define ASM_FILE_START(FILE) \
1674 fprintf (FILE, "#NO_APP\n");
1676 /* Output to assembler file text saying following lines
1677 may contain character constants, extra white space, comments, etc. */
1679 #define ASM_APP_ON "#APP\n"
1681 /* Output to assembler file text saying following lines
1682 no longer contain unusual constructs. */
1684 #define ASM_APP_OFF "#NO_APP\n"
1686 /* Output before read-only data. */
1688 #define TEXT_SECTION_ASM_OP "\t.text"
1690 /* Output before writable data. */
1692 #define DATA_SECTION_ASM_OP "\t.data"
1694 /* Here are four prefixes that are used by asm_fprintf to
1695 facilitate customization for alternate assembler syntaxes.
1696 Machines with no likelihood of an alternate syntax need not
1697 define these and need not use asm_fprintf. */
1699 /* The prefix for register names. Note that REGISTER_NAMES
1700 is supposed to include this prefix. */
1702 #define REGISTER_PREFIX ""
1704 /* The prefix for local labels. You should be able to define this as
1705 an empty string, or any arbitrary string (such as ".", ".L%", etc)
1706 without having to make any other changes to account for the specific
1707 definition. Note it is a string literal, not interpreted by printf
1710 #define LOCAL_LABEL_PREFIX ""
1712 /* The prefix to add to user-visible assembler symbols. */
1714 #define USER_LABEL_PREFIX "_"
1716 /* The prefix for immediate operands. */
1718 #define IMMEDIATE_PREFIX "#"
1720 /* How to refer to registers in assembler output.
1721 This sequence is indexed by compiler's hard-register-number (see above). */
1723 #ifndef SUPPORT_SUN_FPA
1725 #define REGISTER_NAMES \
1726 {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \
1727 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \
1728 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7" }
1730 #else /* SUPPORTED_SUN_FPA */
1732 #define REGISTER_NAMES \
1733 {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \
1734 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \
1735 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", \
1736 "fpa0", "fpa1", "fpa2", "fpa3", "fpa4", "fpa5", "fpa6", "fpa7", \
1737 "fpa8", "fpa9", "fpa10", "fpa11", "fpa12", "fpa13", "fpa14", "fpa15", \
1738 "fpa16", "fpa17", "fpa18", "fpa19", "fpa20", "fpa21", "fpa22", "fpa23", \
1739 "fpa24", "fpa25", "fpa26", "fpa27", "fpa28", "fpa29", "fpa30", "fpa31" }
1741 #endif /* defined SUPPORT_SUN_FPA */
1743 /* How to renumber registers for dbx and gdb.
1744 On the Sun-3, the floating point registers have numbers
1745 18 to 25, not 16 to 23 as they do in the compiler. */
1747 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
1749 /* Before the prologue, RA is at 0(%sp). */
1750 #define INCOMING_RETURN_ADDR_RTX \
1751 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
1753 /* We must not use the DBX register numbers for the DWARF 2 CFA column
1754 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
1755 Instead use the identity mapping. */
1756 #define DWARF_FRAME_REGNUM(REG) REG
1758 /* Before the prologue, the top of the frame is at 4(%sp). */
1759 #define INCOMING_FRAME_SP_OFFSET 4
1761 /* This is how to output the definition of a user-level label named NAME,
1762 such as the label on a static function or variable NAME. */
1764 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1765 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1767 /* This is how to output a command to make the user-level label named NAME
1768 defined for reference from other files. */
1770 #define GLOBAL_ASM_OP "\t.globl\t"
1771 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1772 do { fprintf (FILE, "%s", GLOBAL_ASM_OP); \
1773 assemble_name (FILE, NAME); \
1774 fputs ("\n", FILE);} while (0)
1776 /* This is how to output a reference to a user-level label named NAME.
1777 `assemble_name' uses this. */
1779 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1780 asm_fprintf (FILE, "%0U%s", NAME)
1782 /* This is how to output an internal numbered label where
1783 PREFIX is the class of label and NUM is the number within the class. */
1785 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1786 asm_fprintf (FILE, "%0L%s%d:\n", PREFIX, NUM)
1788 /* This is how to store into the string LABEL
1789 the symbol_ref name of an internal numbered label where
1790 PREFIX is the class of label and NUM is the number within the class.
1791 This is suitable for output with `assemble_name'. */
1793 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1794 sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM))
1796 /* This is how to output an insn to push a register on the stack.
1797 It need not be very fast code. */
1799 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1800 asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO])
1802 /* This is how to output an insn to pop a register from the stack.
1803 It need not be very fast code. */
1805 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1806 asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO])
1808 /* This is how to output an element of a case-vector that is absolute.
1809 (The 68000 does not use such vectors,
1810 but we must define this macro anyway.) */
1812 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1813 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE)
1815 /* This is how to output an element of a case-vector that is relative. */
1817 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1818 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL)
1820 /* This is how to output an assembler line
1821 that says to advance the location counter
1822 to a multiple of 2**LOG bytes. */
1824 /* We don't have a way to align to more than a two-byte boundary, so do the
1825 best we can and don't complain. */
1826 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1828 fprintf (FILE, "\t.even\n");
1830 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1831 fprintf (FILE, "\t.skip %u\n", (SIZE))
1833 /* This says how to output an assembler line
1834 to define a global common symbol. */
1836 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1837 ( fputs (".comm ", (FILE)), \
1838 assemble_name ((FILE), (NAME)), \
1839 fprintf ((FILE), ",%u\n", (ROUNDED)))
1841 /* This says how to output an assembler line
1842 to define a local common symbol. */
1844 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1845 ( fputs (".lcomm ", (FILE)), \
1846 assemble_name ((FILE), (NAME)), \
1847 fprintf ((FILE), ",%u\n", (ROUNDED)))
1849 /* Store in OUTPUT a string (made with alloca) containing
1850 an assembler-name for a local static variable named NAME.
1851 LABELNO is an integer which is different for each call. */
1853 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1854 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1855 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1857 /* Output a float value (represented as a C double) as an immediate operand.
1858 This macro is a 68k-specific macro. */
1860 #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
1865 REAL_VALUE_TO_DECIMAL (VALUE, "%.9g", dstr); \
1866 asm_fprintf ((FILE), "%I0r%s", dstr); \
1871 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1872 asm_fprintf ((FILE), "%I0x%lx", l); \
1876 /* Output a double value (represented as a C double) as an immediate operand.
1877 This macro is a 68k-specific macro. */
1878 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
1879 do { char dstr[30]; \
1880 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
1881 asm_fprintf (FILE, "%I0r%s", dstr); \
1884 /* Note, long double immediate operands are not actually
1885 generated by m68k.md. */
1886 #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \
1887 do { char dstr[30]; \
1888 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
1889 asm_fprintf (FILE, "%I0r%s", dstr); \
1892 /* Print operand X (an rtx) in assembler syntax to file FILE.
1893 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1894 For `%' followed by punctuation, CODE is the punctuation and X is null.
1896 On the 68000, we use several CODE characters:
1897 '.' for dot needed in Motorola-style opcode names.
1898 '-' for an operand pushing on the stack:
1899 sp@-, -(sp) or -(%sp) depending on the style of syntax.
1900 '+' for an operand pushing on the stack:
1901 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
1902 '@' for a reference to the top word on the stack:
1903 sp@, (sp) or (%sp) depending on the style of syntax.
1904 '#' for an immediate operand prefix (# in MIT and Motorola syntax
1905 but & in SGS syntax).
1906 '!' for the fpcr register (used in some float-to-fixed conversions).
1907 '$' for the letter `s' in an op code, but only on the 68040.
1908 '&' for the letter `d' in an op code, but only on the 68040.
1909 '/' for register prefix needed by longlong.h.
1911 'b' for byte insn (no effect, on the Sun; this is for the ISI).
1912 'd' to force memory addressing to be absolute, not relative.
1913 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1914 'o' for operands to go directly to output_operand_address (bypassing
1915 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
1916 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
1917 than directly). Second part of 'y' below.
1918 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
1919 or print pair of registers as rx:ry.
1920 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
1921 CONST_DOUBLE's as SunFPA constant RAM registers if
1922 possible, so it should not be used except for the SunFPA. */
1924 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1925 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
1926 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \
1927 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/')
1929 /* A C compound statement to output to stdio stream STREAM the
1930 assembler syntax for an instruction operand X. X is an RTL
1933 CODE is a value that can be used to specify one of several ways
1934 of printing the operand. It is used when identical operands
1935 must be printed differently depending on the context. CODE
1936 comes from the `%' specification that was used to request
1937 printing of the operand. If the specification was just `%DIGIT'
1938 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
1939 is the ASCII code for LTR.
1941 If X is a register, this macro should print the register's name.
1942 The names can be found in an array `reg_names' whose type is
1943 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
1945 When the machine description has a specification `%PUNCT' (a `%'
1946 followed by a punctuation character), this macro is called with
1947 a null pointer for X and the punctuation character for CODE.
1949 See m68k.c for the m68k specific codes. */
1951 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1953 /* A C compound statement to output to stdio stream STREAM the
1954 assembler syntax for an instruction operand that is a memory
1955 reference whose address is ADDR. ADDR is an RTL expression.
1957 On some machines, the syntax for a symbolic address depends on
1958 the section that the address refers to. On these machines,
1959 define the macro `ENCODE_SECTION_INFO' to store the information
1960 into the `symbol_ref', and then check for it here. */
1962 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1964 /* Variables in m68k.c */
1965 extern const char *m68k_align_loops_string;
1966 extern const char *m68k_align_jumps_string;
1967 extern const char *m68k_align_funcs_string;
1968 extern int m68k_align_loops;
1969 extern int m68k_align_jumps;
1970 extern int m68k_align_funcs;
1971 extern int m68k_last_compare_had_fp_operands;
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