1 /* Definitions of target machine for GNU compiler. Sun 68000/68020 version.
2 Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000
3 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* Note that some other tm.h files include this one and then override
24 many of the definitions that relate to assembler syntax. */
27 /* Names to predefine in the preprocessor for this target machine. */
29 /* See sun3.h, sun2.h, isi.h for different CPP_PREDEFINES. */
31 /* Print subsidiary information on the compiler version in use. */
33 #define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)");
35 #define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)");
38 /* Define SUPPORT_SUN_FPA to include support for generating code for
39 the Sun Floating Point Accelerator, an optional product for Sun 3
40 machines. By default, it is not defined. Avoid defining it unless
41 you need to output code for the Sun3+FPA architecture, as it has the
42 effect of slowing down the register set operations in hard-reg-set.h
43 (total number of registers will exceed number of bits in a long,
44 if defined, causing the set operations to expand to loops).
45 SUPPORT_SUN_FPA is typically defined in sun3.h. */
47 /* Run-time compilation parameters selecting different hardware subsets. */
49 extern int target_flags;
51 /* Macros used in the machine description to test the flags. */
53 /* Compile for a 68020 (not a 68000 or 68010). */
55 #define TARGET_68020 (target_flags & MASK_68020)
57 /* Compile 68881 insns for floating point (not library calls). */
59 #define TARGET_68881 (target_flags & MASK_68881)
61 /* Compile using 68020 bitfield insns. */
62 #define MASK_BITFIELD 4
63 #define TARGET_BITFIELD (target_flags & MASK_BITFIELD)
65 /* Compile using rtd insn calling sequence.
66 This will not work unless you use prototypes at least
67 for all functions that can take varying numbers of args. */
69 #define TARGET_RTD (target_flags & MASK_RTD)
71 /* Compile passing first two args in regs 0 and 1.
72 This exists only to test compiler features that will
73 be needed for RISC chips. It is not usable
74 and is not intended to be usable on this cpu. */
75 #define MASK_REGPARM 16
76 #define TARGET_REGPARM (target_flags & MASK_REGPARM)
78 /* Compile with 16-bit `int'. */
80 #define TARGET_SHORT (target_flags & MASK_SHORT)
82 /* Compile with special insns for Sun FPA. */
84 #define TARGET_FPA (target_flags & MASK_FPA)
86 /* Compile (actually, link) for Sun SKY board. */
88 #define TARGET_SKY (target_flags & MASK_SKY)
90 /* Optimize for 68040, but still allow execution on 68020
91 (-m68020-40 or -m68040).
92 The 68040 will execute all 68030 and 68881/2 instructions, but some
93 of them must be emulated in software by the OS. When TARGET_68040 is
94 turned on, these instructions won't be used. This code will still
95 run on a 68030 and 68881/2. */
96 #define MASK_68040 256
97 #define TARGET_68040 (target_flags & MASK_68040)
99 /* Use the 68040-only fp instructions (-m68040 or -m68060). */
100 #define MASK_68040_ONLY 512
101 #define TARGET_68040_ONLY (target_flags & MASK_68040_ONLY)
103 /* Optimize for 68060, but still allow execution on 68020
104 (-m68020-60 or -m68060).
105 The 68060 will execute all 68030 and 68881/2 instructions, but some
106 of them must be emulated in software by the OS. When TARGET_68060 is
107 turned on, these instructions won't be used. This code will still
108 run on a 68030 and 68881/2. */
109 #define MASK_68060 1024
110 #define TARGET_68060 (target_flags & MASK_68060)
112 /* Compile for mcf5200 */
113 #define MASK_5200 2048
114 #define TARGET_5200 (target_flags & MASK_5200)
116 /* Align ints to a word boundary. This breaks compatibility with the
117 published ABI's for structures containing ints, but produces faster
118 code on cpus with 32 bit busses (020, 030, 040, 060, CPU32+, coldfire).
119 It's required for coldfire cpus without a misalignment module. */
120 #define MASK_ALIGN_INT 4096
121 #define TARGET_ALIGN_INT (target_flags & MASK_ALIGN_INT)
123 /* Compile for a CPU32 */
124 /* A 68020 without bitfields is a good heuristic for a CPU32 */
125 #define TARGET_CPU32 (TARGET_68020 && !TARGET_BITFIELD)
127 /* Use PC-relative addressing modes (without using a global offset table).
128 The m68000 supports 16-bit PC-relative addressing.
129 The m68020 supports 32-bit PC-relative addressing
130 (using outer displacements).
132 Under this model, all SYMBOL_REFs (and CONSTs) and LABEL_REFs are
133 treated as all containing an implicit PC-relative component, and hence
134 cannot be used directly as addresses for memory writes. See the comments
135 in m68k.c for more information. */
136 #define MASK_PCREL 8192
137 #define TARGET_PCREL (target_flags & MASK_PCREL)
139 /* Relax strict alignment. */
140 #define MASK_NO_STRICT_ALIGNMENT 16384
141 #define TARGET_STRICT_ALIGNMENT (~target_flags & MASK_NO_STRICT_ALIGNMENT)
143 /* Macro to define tables used to set the flags.
144 This is a list in braces of pairs in braces,
145 each pair being { "NAME", VALUE }
146 where VALUE is the bits to set or minus the bits to clear.
147 An empty string NAME is used to identify the default VALUE. */
149 #define TARGET_SWITCHES \
150 { { "68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY)}, \
151 { "c68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY)}, \
152 { "68020", (MASK_68020|MASK_BITFIELD)}, \
153 { "c68020", (MASK_68020|MASK_BITFIELD)}, \
154 { "68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
155 |MASK_68020|MASK_BITFIELD|MASK_68881)}, \
156 { "c68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
157 |MASK_68020|MASK_BITFIELD|MASK_68881)}, \
158 { "bitfield", MASK_BITFIELD}, \
159 { "nobitfield", - MASK_BITFIELD}, \
160 { "rtd", MASK_RTD}, \
161 { "nortd", - MASK_RTD}, \
162 { "short", MASK_SHORT}, \
163 { "noshort", - MASK_SHORT}, \
164 { "fpa", -(MASK_SKY|MASK_68040_ONLY|MASK_68881)}, \
165 { "fpa", MASK_FPA}, \
166 { "nofpa", - MASK_FPA}, \
167 { "sky", -(MASK_FPA|MASK_68040_ONLY|MASK_68881)}, \
168 { "sky", MASK_SKY}, \
169 { "nosky", - MASK_SKY}, \
170 { "68881", - (MASK_FPA|MASK_SKY)}, \
171 { "68881", MASK_68881}, \
172 { "soft-float", - (MASK_FPA|MASK_SKY|MASK_68040_ONLY|MASK_68881)}, \
173 { "68020-40", -(MASK_5200|MASK_68060|MASK_68040_ONLY)}, \
174 { "68020-40", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040)}, \
175 { "68020-60", -(MASK_5200|MASK_68040_ONLY)}, \
176 { "68020-60", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040 \
178 { "68030", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY)}, \
179 { "68030", (MASK_68020|MASK_BITFIELD)}, \
180 { "68040", - (MASK_5200|MASK_68060)}, \
181 { "68040", (MASK_68020|MASK_68881|MASK_BITFIELD \
182 |MASK_68040_ONLY|MASK_68040)}, \
183 { "68060", - (MASK_5200|MASK_68040)}, \
184 { "68060", (MASK_68020|MASK_68881|MASK_BITFIELD \
185 |MASK_68040_ONLY|MASK_68060)}, \
186 { "5200", - (MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
187 |MASK_BITFIELD|MASK_68881)}, \
188 { "5200", (MASK_5200)}, \
191 { "68302", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
192 |MASK_68020|MASK_BITFIELD|MASK_68881)}, \
193 { "68332", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
194 |MASK_BITFIELD|MASK_68881)}, \
195 { "68332", MASK_68020}, \
196 { "cpu32", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
197 |MASK_BITFIELD|MASK_68881)}, \
198 { "cpu32", MASK_68020}, \
199 { "align-int", MASK_ALIGN_INT }, \
200 { "no-align-int", -MASK_ALIGN_INT }, \
201 { "pcrel", MASK_PCREL}, \
202 { "strict-align", -MASK_NO_STRICT_ALIGNMENT}, \
203 { "no-strict-align", MASK_NO_STRICT_ALIGNMENT}, \
205 { "", TARGET_DEFAULT}}
206 /* TARGET_DEFAULT is defined in sun*.h and isi.h, etc. */
208 /* This macro is similar to `TARGET_SWITCHES' but defines names of
209 command options that have values. Its definition is an
210 initializer with a subgrouping for each command option.
212 Each subgrouping contains a string constant, that defines the
213 fixed part of the option name, and the address of a variable. The
214 variable, type `char *', is set to the variable part of the given
215 option if the fixed part matches. The actual option name is made
216 by appending `-m' to the specified name. */
217 #define TARGET_OPTIONS \
218 { { "align-loops=", &m68k_align_loops_string }, \
219 { "align-jumps=", &m68k_align_jumps_string }, \
220 { "align-functions=", &m68k_align_funcs_string }, \
224 /* Sometimes certain combinations of command options do not make
225 sense on a particular target machine. You can define a macro
226 `OVERRIDE_OPTIONS' to take account of this. This macro, if
227 defined, is executed once just after all the command options have
230 Don't use this macro to turn on various extra optimizations for
231 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
233 #define OVERRIDE_OPTIONS \
235 override_options(); \
236 if (! TARGET_68020 && flag_pic == 2) \
237 error("-fPIC is not currently supported on the 68000 or 68010\n"); \
238 if (TARGET_PCREL && flag_pic == 0) \
240 SUBTARGET_OVERRIDE_OPTIONS; \
243 /* These are meant to be redefined in the host dependent files */
244 #define SUBTARGET_SWITCHES
245 #define SUBTARGET_OPTIONS
246 #define SUBTARGET_OVERRIDE_OPTIONS
248 /* target machine storage layout */
250 /* Define for XFmode extended real floating point support.
251 This will automatically cause REAL_ARITHMETIC to be defined. */
252 #define LONG_DOUBLE_TYPE_SIZE 96
254 /* Define if you don't want extended real, but do want to use the
255 software floating point emulator for REAL_ARITHMETIC and
256 decimal <-> binary conversion. */
257 /* #define REAL_ARITHMETIC */
259 /* Define this if most significant bit is lowest numbered
260 in instructions that operate on numbered bit-fields.
261 This is true for 68020 insns such as bfins and bfexts.
262 We make it true always by avoiding using the single-bit insns
263 except in special cases with constant bit numbers. */
264 #define BITS_BIG_ENDIAN 1
266 /* Define this if most significant byte of a word is the lowest numbered. */
267 /* That is true on the 68000. */
268 #define BYTES_BIG_ENDIAN 1
270 /* Define this if most significant word of a multiword number is the lowest
272 /* For 68000 we can decide arbitrarily
273 since there are no machine instructions for them.
274 So let's be consistent. */
275 #define WORDS_BIG_ENDIAN 1
277 /* number of bits in an addressable storage unit */
278 #define BITS_PER_UNIT 8
280 /* Width in bits of a "word", which is the contents of a machine register.
281 Note that this is not necessarily the width of data type `int';
282 if using 16-bit ints on a 68000, this would still be 32.
283 But on a machine with 16-bit registers, this would be 16. */
284 #define BITS_PER_WORD 32
286 /* Width of a word, in units (bytes). */
287 #define UNITS_PER_WORD 4
289 /* Width in bits of a pointer.
290 See also the macro `Pmode' defined below. */
291 #define POINTER_SIZE 32
293 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
294 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
296 /* Boundary (in *bits*) on which stack pointer should be aligned. */
297 #define STACK_BOUNDARY 16
299 /* Allocation boundary (in *bits*) for the code of a function. */
300 #define FUNCTION_BOUNDARY (1 << (m68k_align_funcs + 3))
302 /* Alignment of field after `int : 0' in a structure. */
303 #define EMPTY_FIELD_BOUNDARY 16
305 /* No data type wants to be aligned rounder than this.
306 Most published ABIs say that ints should be aligned on 16 bit
307 boundaries, but cpus with 32 bit busses get better performance
308 aligned on 32 bit boundaries. Coldfires without a misalignment
309 module require 32 bit alignment. */
310 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
312 /* Set this nonzero if move instructions will actually fail to work
313 when given unaligned data. */
314 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT)
316 /* Maximum power of 2 that code can be aligned to. */
317 #define MAX_CODE_ALIGN 2 /* 4 byte alignment */
319 /* Align loop starts for optimal branching. */
320 #define LOOP_ALIGN(LABEL) (m68k_align_loops)
322 /* This is how to align an instruction for optimal branching. */
323 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) (m68k_align_jumps)
325 #define SELECT_RTX_SECTION(MODE, X) \
328 readonly_data_section(); \
329 else if (LEGITIMATE_PIC_OPERAND_P (X)) \
330 readonly_data_section(); \
335 /* Define number of bits in most basic integer type.
336 (If undefined, default is BITS_PER_WORD). */
338 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
340 /* Define these to avoid dependence on meaning of `int'. */
342 #define WCHAR_TYPE "long int"
343 #define WCHAR_TYPE_SIZE 32
345 /* Standard register usage. */
347 /* Number of actual hardware registers.
348 The hardware registers are assigned numbers for the compiler
349 from 0 to just below FIRST_PSEUDO_REGISTER.
350 All registers that the compiler knows about must be given numbers,
351 even those that are not normally considered general registers.
352 For the 68000, we give the data registers numbers 0-7,
353 the address registers numbers 010-017,
354 and the 68881 floating point registers numbers 020-027. */
355 #ifndef SUPPORT_SUN_FPA
356 #define FIRST_PSEUDO_REGISTER 24
358 #define FIRST_PSEUDO_REGISTER 56
361 /* This defines the register which is used to hold the offset table for PIC. */
362 #define PIC_OFFSET_TABLE_REGNUM 13
364 #ifndef SUPPORT_SUN_FPA
366 /* 1 for registers that have pervasive standard uses
367 and are not available for the register allocator.
368 On the 68000, only the stack pointer is such. */
370 #define FIXED_REGISTERS \
371 {/* Data registers. */ \
372 0, 0, 0, 0, 0, 0, 0, 0, \
374 /* Address registers. */ \
375 0, 0, 0, 0, 0, 0, 0, 1, \
377 /* Floating point registers \
379 0, 0, 0, 0, 0, 0, 0, 0 }
381 /* 1 for registers not available across function calls.
382 These must include the FIXED_REGISTERS and also any
383 registers that can be used without being saved.
384 The latter must include the registers where values are returned
385 and the register where structure-value addresses are passed.
386 Aside from that, you can include as many other registers as you like. */
387 #define CALL_USED_REGISTERS \
388 {1, 1, 0, 0, 0, 0, 0, 0, \
389 1, 1, 0, 0, 0, 0, 0, 1, \
390 1, 1, 0, 0, 0, 0, 0, 0 }
392 #else /* SUPPORT_SUN_FPA */
394 /* 1 for registers that have pervasive standard uses
395 and are not available for the register allocator.
396 On the 68000, only the stack pointer is such. */
398 /* fpa0 is also reserved so that it can be used to move data back and
399 forth between high fpa regs and everything else. */
401 #define FIXED_REGISTERS \
402 {/* Data registers. */ \
403 0, 0, 0, 0, 0, 0, 0, 0, \
405 /* Address registers. */ \
406 0, 0, 0, 0, 0, 0, 0, 1, \
408 /* Floating point registers \
410 0, 0, 0, 0, 0, 0, 0, 0, \
412 /* Sun3 FPA registers. */ \
413 1, 0, 0, 0, 0, 0, 0, 0, \
414 0, 0, 0, 0, 0, 0, 0, 0, \
415 0, 0, 0, 0, 0, 0, 0, 0, \
416 0, 0, 0, 0, 0, 0, 0, 0 }
418 /* 1 for registers not available across function calls.
419 These must include the FIXED_REGISTERS and also any
420 registers that can be used without being saved.
421 The latter must include the registers where values are returned
422 and the register where structure-value addresses are passed.
423 Aside from that, you can include as many other registers as you like. */
424 #define CALL_USED_REGISTERS \
425 {1, 1, 0, 0, 0, 0, 0, 0, \
426 1, 1, 0, 0, 0, 0, 0, 1, \
427 1, 1, 0, 0, 0, 0, 0, 0, \
428 /* FPA registers. */ \
429 1, 1, 1, 1, 0, 0, 0, 0, \
430 0, 0, 0, 0, 0, 0, 0, 0, \
431 0, 0, 0, 0, 0, 0, 0, 0, \
432 0, 0, 0, 0, 0, 0, 0, 0 }
434 #endif /* defined SUPPORT_SUN_FPA */
437 /* Make sure everything's fine if we *don't* have a given processor.
438 This assumes that putting a register in fixed_regs will keep the
439 compiler's mitts completely off it. We don't bother to zero it out
440 of register classes. */
442 #ifdef SUPPORT_SUN_FPA
444 #define CONDITIONAL_REGISTER_USAGE \
450 COPY_HARD_REG_SET (x, reg_class_contents[(int)FPA_REGS]); \
451 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
452 if (TEST_HARD_REG_BIT (x, i)) \
453 fixed_regs[i] = call_used_regs[i] = 1; \
455 if (! TARGET_68881) \
457 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
458 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
459 if (TEST_HARD_REG_BIT (x, i)) \
460 fixed_regs[i] = call_used_regs[i] = 1; \
463 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
464 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;\
467 #define CONDITIONAL_REGISTER_USAGE \
471 if (! TARGET_68881) \
473 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
474 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
475 if (TEST_HARD_REG_BIT (x, i)) \
476 fixed_regs[i] = call_used_regs[i] = 1; \
479 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
480 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;\
483 #endif /* defined SUPPORT_SUN_FPA */
485 /* Return number of consecutive hard regs needed starting at reg REGNO
486 to hold something of mode MODE.
487 This is ordinarily the length in words of a value of mode MODE
488 but can be less for certain modes in special long registers.
490 On the 68000, ordinary registers hold 32 bits worth;
491 for the 68881 registers, a single register is always enough for
492 anything that can be stored in them at all. */
493 #define HARD_REGNO_NREGS(REGNO, MODE) \
494 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
495 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
497 #ifndef SUPPORT_SUN_FPA
499 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
500 On the 68000, the cpu registers can hold any mode but the 68881 registers
501 can hold only SFmode or DFmode. */
503 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
505 && !((REGNO) < 8 && (REGNO) + GET_MODE_SIZE (MODE) / 4 > 8)) \
506 || ((REGNO) >= 16 && (REGNO) < 24 \
507 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
508 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
509 && GET_MODE_UNIT_SIZE (MODE) <= 12))
511 #else /* defined SUPPORT_SUN_FPA */
513 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
514 On the 68000, the cpu registers can hold any mode but the 68881 registers
515 can hold only SFmode or DFmode. However, the Sun FPA register can
516 (apparently) hold whatever you feel like putting in them.
517 If using the fpa, don't put a double in d7/a0. */
519 /* ??? This is confused. The check to prohibit d7/a0 overlaps should always
520 be enabled regardless of whether TARGET_FPA is specified. It isn't clear
521 what the other d/a register checks are for. Every check using REGNO
522 actually needs to use a range, e.g. 24>=X<56 not <56. There is probably
523 no one using this code anymore.
524 This code used to be used to suppress register usage for the 68881 by
525 saying that the 68881 registers couldn't hold values of any mode if there
526 was no 68881. This was wrong, because reload (etc.) will still try
527 to save and restore call-saved registers during, for instance, non-local
529 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
532 && GET_MODE_CLASS ((MODE)) != MODE_INT \
533 && GET_MODE_UNIT_SIZE ((MODE)) > 4 \
534 && (REGNO) < 8 && (REGNO) + GET_MODE_SIZE ((MODE)) / 4 > 8 \
535 && (REGNO) % (GET_MODE_UNIT_SIZE ((MODE)) / 4) != 0)) \
536 || ((REGNO) >= 16 && (REGNO) < 24 \
537 ? ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
538 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
539 && GET_MODE_UNIT_SIZE (MODE) <= 12) \
540 : ((REGNO) < 56 ? TARGET_FPA && GET_MODE_UNIT_SIZE (MODE) <= 8 : 0)))
542 #endif /* defined SUPPORT_SUN_FPA */
544 /* Value is 1 if it is a good idea to tie two pseudo registers
545 when one has mode MODE1 and one has mode MODE2.
546 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
547 for any hard reg, then this must be 0 for correct output. */
548 #define MODES_TIEABLE_P(MODE1, MODE2) \
550 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
551 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
552 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
553 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
555 /* Specify the registers used for certain standard purposes.
556 The values of these macros are register numbers. */
558 /* m68000 pc isn't overloaded on a register. */
559 /* #define PC_REGNUM */
561 /* Register to use for pushing function arguments. */
562 #define STACK_POINTER_REGNUM 15
564 /* Base register for access to local variables of the function. */
565 #define FRAME_POINTER_REGNUM 14
567 /* Value should be nonzero if functions must have frame pointers.
568 Zero means the frame pointer need not be set up (and parms
569 may be accessed via the stack pointer) in functions that seem suitable.
570 This is computed in `reload', in reload1.c. */
571 #define FRAME_POINTER_REQUIRED 0
573 /* Base register for access to arguments of the function. */
574 #define ARG_POINTER_REGNUM 14
576 /* Register in which static-chain is passed to a function. */
577 #define STATIC_CHAIN_REGNUM 8
579 /* Register in which address to store a structure value
580 is passed to a function. */
581 #define STRUCT_VALUE_REGNUM 9
583 /* Define the classes of registers for register constraints in the
584 machine description. Also define ranges of constants.
586 One of the classes must always be named ALL_REGS and include all hard regs.
587 If there is more than one class, another class must be named NO_REGS
588 and contain no registers.
590 The name GENERAL_REGS must be the name of a class (or an alias for
591 another name such as ALL_REGS). This is the class of registers
592 that is allowed by "g" or "r" in a register constraint.
593 Also, registers outside this class are allocated only when
594 instructions express preferences for them.
596 The classes must be numbered in nondecreasing order; that is,
597 a larger-numbered class must never be contained completely
598 in a smaller-numbered class.
600 For any two classes, it is very desirable that there be another
601 class that represents their union. */
603 /* The 68000 has three kinds of registers, so eight classes would be
604 a complete set. One of them is not needed. */
606 #ifndef SUPPORT_SUN_FPA
611 GENERAL_REGS, DATA_OR_FP_REGS,
612 ADDR_OR_FP_REGS, ALL_REGS,
615 #define N_REG_CLASSES (int) LIM_REG_CLASSES
617 /* Give names of register classes as strings for dump file. */
619 #define REG_CLASS_NAMES \
620 { "NO_REGS", "DATA_REGS", \
621 "ADDR_REGS", "FP_REGS", \
622 "GENERAL_REGS", "DATA_OR_FP_REGS", \
623 "ADDR_OR_FP_REGS", "ALL_REGS" }
625 /* Define which registers fit in which classes.
626 This is an initializer for a vector of HARD_REG_SET
627 of length N_REG_CLASSES. */
629 #define REG_CLASS_CONTENTS \
631 {0x00000000}, /* NO_REGS */ \
632 {0x000000ff}, /* DATA_REGS */ \
633 {0x0000ff00}, /* ADDR_REGS */ \
634 {0x00ff0000}, /* FP_REGS */ \
635 {0x0000ffff}, /* GENERAL_REGS */ \
636 {0x00ff00ff}, /* DATA_OR_FP_REGS */ \
637 {0x00ffff00}, /* ADDR_OR_FP_REGS */ \
638 {0x00ffffff}, /* ALL_REGS */ \
641 /* The same information, inverted:
642 Return the class number of the smallest class containing
643 reg number REGNO. This could be a conditional expression
644 or could index an array. */
646 #define REGNO_REG_CLASS(REGNO) (((REGNO)>>3)+1)
648 #else /* defined SUPPORT_SUN_FPA */
651 * Notes on final choices:
653 * 1) Didn't feel any need to union-ize LOW_FPA_REGS with anything
655 * 2) Removed all unions that involve address registers with
656 * floating point registers (left in unions of address and data with
658 * 3) Defined GENERAL_REGS as ADDR_OR_DATA_REGS.
659 * 4) Defined ALL_REGS as FPA_OR_FP_OR_GENERAL_REGS.
660 * 4) Left in everything else.
662 enum reg_class { NO_REGS, LO_FPA_REGS, FPA_REGS, FP_REGS,
663 FP_OR_FPA_REGS, DATA_REGS, DATA_OR_FPA_REGS, DATA_OR_FP_REGS,
664 DATA_OR_FP_OR_FPA_REGS, ADDR_REGS, GENERAL_REGS,
665 GENERAL_OR_FPA_REGS, GENERAL_OR_FP_REGS, ALL_REGS,
668 #define N_REG_CLASSES (int) LIM_REG_CLASSES
670 /* Give names of register classes as strings for dump file. */
672 #define REG_CLASS_NAMES \
673 { "NO_REGS", "LO_FPA_REGS", "FPA_REGS", "FP_REGS", \
674 "FP_OR_FPA_REGS", "DATA_REGS", "DATA_OR_FPA_REGS", "DATA_OR_FP_REGS", \
675 "DATA_OR_FP_OR_FPA_REGS", "ADDR_REGS", "GENERAL_REGS", \
676 "GENERAL_OR_FPA_REGS", "GENERAL_OR_FP_REGS", "ALL_REGS" }
678 /* Define which registers fit in which classes.
679 This is an initializer for a vector of HARD_REG_SET
680 of length N_REG_CLASSES. */
682 #define REG_CLASS_CONTENTS \
684 {0, 0}, /* NO_REGS */ \
685 {0xff000000, 0x000000ff}, /* LO_FPA_REGS */ \
686 {0xff000000, 0x00ffffff}, /* FPA_REGS */ \
687 {0x00ff0000, 0x00000000}, /* FP_REGS */ \
688 {0xffff0000, 0x00ffffff}, /* FP_OR_FPA_REGS */ \
689 {0x000000ff, 0x00000000}, /* DATA_REGS */ \
690 {0xff0000ff, 0x00ffffff}, /* DATA_OR_FPA_REGS */ \
691 {0x00ff00ff, 0x00000000}, /* DATA_OR_FP_REGS */ \
692 {0xffff00ff, 0x00ffffff}, /* DATA_OR_FP_OR_FPA_REGS */\
693 {0x0000ff00, 0x00000000}, /* ADDR_REGS */ \
694 {0x0000ffff, 0x00000000}, /* GENERAL_REGS */ \
695 {0xff00ffff, 0x00ffffff}, /* GENERAL_OR_FPA_REGS */\
696 {0x00ffffff, 0x00000000}, /* GENERAL_OR_FP_REGS */\
697 {0xffffffff, 0x00ffffff}, /* ALL_REGS */ \
700 /* The same information, inverted:
701 Return the class number of the smallest class containing
702 reg number REGNO. This could be a conditional expression
703 or could index an array. */
705 extern enum reg_class regno_reg_class[];
706 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)>>3])
708 #endif /* SUPPORT_SUN_FPA */
710 /* The class value for index registers, and the one for base regs. */
712 #define INDEX_REG_CLASS GENERAL_REGS
713 #define BASE_REG_CLASS ADDR_REGS
715 /* Get reg_class from a letter such as appears in the machine description.
716 We do a trick here to modify the effective constraints on the
717 machine description; we zorch the constraint letters that aren't
718 appropriate for a specific target. This allows us to guarantee
719 that a specific kind of register will not be used for a given target
720 without fiddling with the register classes above. */
722 #ifndef SUPPORT_SUN_FPA
724 #define REG_CLASS_FROM_LETTER(C) \
725 ((C) == 'a' ? ADDR_REGS : \
726 ((C) == 'd' ? DATA_REGS : \
727 ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \
731 #else /* defined SUPPORT_SUN_FPA */
733 #define REG_CLASS_FROM_LETTER(C) \
734 ((C) == 'a' ? ADDR_REGS : \
735 ((C) == 'd' ? DATA_REGS : \
736 ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \
738 ((C) == 'x' ? (TARGET_FPA ? FPA_REGS : \
740 ((C) == 'y' ? (TARGET_FPA ? LO_FPA_REGS : \
744 #endif /* defined SUPPORT_SUN_FPA */
746 /* The letters I, J, K, L and M in a register constraint string
747 can be used to stand for particular ranges of immediate operands.
748 This macro defines what the ranges are.
749 C is the letter, and VALUE is a constant value.
750 Return 1 if VALUE is in the range specified by C.
752 For the 68000, `I' is used for the range 1 to 8
753 allowed as immediate shift counts and in addq.
754 `J' is used for the range of signed numbers that fit in 16 bits.
755 `K' is for numbers that moveq can't handle.
756 `L' is for range -8 to -1, range of values that can be added with subq.
757 `M' is for numbers that moveq+notb can't handle.
758 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate.
759 'O' is for 16 (for rotate using swap).
760 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */
762 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
763 ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \
764 (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
765 (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
766 (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \
767 (C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \
768 (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \
769 (C) == 'O' ? (VALUE) == 16 : \
770 (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0)
773 * A small bit of explanation:
774 * "G" defines all of the floating constants that are *NOT* 68881
775 * constants. this is so 68881 constants get reloaded and the
776 * fpmovecr is used. "H" defines *only* the class of constants that
777 * the fpa can use, because these can be gotten at in any fpa
778 * instruction and there is no need to force reloads.
780 #ifndef SUPPORT_SUN_FPA
781 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
782 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 )
783 #else /* defined SUPPORT_SUN_FPA */
784 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
785 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : \
786 (C) == 'H' ? (TARGET_FPA && standard_sun_fpa_constant_p (VALUE)) : 0)
787 #endif /* defined SUPPORT_SUN_FPA */
789 /* A C expression that defines the optional machine-dependent constraint
790 letters that can be used to segregate specific types of operands,
791 usually memory references, for the target machine. It should return 1 if
792 VALUE corresponds to the operand type represented by the constraint letter
793 C. If C is not defined as an extra constraint, the value returned should
794 be 0 regardless of VALUE. */
796 /* Letters in the range `Q' through `U' may be defined in a
797 machine-dependent fashion to stand for arbitrary operand types.
798 The machine description macro `EXTRA_CONSTRAINT' is passed the
799 operand as its first argument and the constraint letter as its
802 `Q' means address register indirect addressing mode.
803 `S' is for operands that satisfy 'm' when -mpcrel is in effect.
804 `T' is for operands that satisfy 's' when -mpcrel is not in effect. */
806 #define EXTRA_CONSTRAINT(OP,CODE) \
809 && GET_CODE (OP) == MEM \
810 && (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
811 || GET_CODE (XEXP (OP, 0)) == LABEL_REF \
812 || GET_CODE (XEXP (OP, 0)) == CONST)) \
816 && (GET_CODE (OP) == SYMBOL_REF \
817 || GET_CODE (OP) == LABEL_REF \
818 || GET_CODE (OP) == CONST)) \
821 ? (GET_CODE (OP) == MEM \
822 && GET_CODE (XEXP (OP, 0)) == REG) \
826 /* Given an rtx X being reloaded into a reg required to be
827 in class CLASS, return the class of reg to actually use.
828 In general this is just CLASS; but on some machines
829 in some cases it is preferable to use a more restrictive class.
830 On the 68000 series, use a data reg if possible when the
831 value is a constant in the range where moveq could be used
832 and we ensure that QImodes are reloaded into data regs. */
834 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
835 ((GET_CODE (X) == CONST_INT \
836 && (unsigned) (INTVAL (X) + 0x80) < 0x100 \
837 && (CLASS) != ADDR_REGS) \
839 : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \
841 : (GET_CODE (X) == CONST_DOUBLE \
842 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
843 ? (TARGET_68881 && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \
844 ? FP_REGS : NO_REGS) \
846 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
847 || GET_CODE (X) == LABEL_REF)) \
851 /* Force QImode output reloads from subregs to be allocated to data regs,
852 since QImode stores from address regs are not supported. We make the
853 assumption that if the class is not ADDR_REGS, then it must be a superset
856 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
857 (((MODE) == QImode && (CLASS) != ADDR_REGS) \
861 /* Return the maximum number of consecutive registers
862 needed to represent mode MODE in a register of class CLASS. */
863 /* On the 68000, this is the size of MODE in words,
864 except in the FP regs, where a single reg is always enough. */
865 #ifndef SUPPORT_SUN_FPA
867 #define CLASS_MAX_NREGS(CLASS, MODE) \
868 ((CLASS) == FP_REGS ? 1 \
869 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
871 /* Moves between fp regs and other regs are two insns. */
872 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
873 (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
874 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
877 #else /* defined SUPPORT_SUN_FPA */
879 #define CLASS_MAX_NREGS(CLASS, MODE) \
880 ((CLASS) == FP_REGS || (CLASS) == FPA_REGS || (CLASS) == LO_FPA_REGS ? 1 \
881 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
883 /* Moves between fp regs and other regs are two insns. */
884 /* Likewise for high fpa regs and other regs. */
885 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
886 ((((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
887 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
888 || ((CLASS1) == FPA_REGS && (CLASS2) != FPA_REGS) \
889 || ((CLASS2) == FPA_REGS && (CLASS1) != FPA_REGS)) \
892 #endif /* define SUPPORT_SUN_FPA */
894 /* Stack layout; function entry, exit and calling. */
896 /* Define this if pushing a word on the stack
897 makes the stack pointer a smaller address. */
898 #define STACK_GROWS_DOWNWARD
900 /* Nonzero if we need to generate stack-probe insns.
901 On most systems they are not needed.
902 When they are needed, define this as the stack offset to probe at. */
905 /* Define this if the nominal address of the stack frame
906 is at the high-address end of the local variables;
907 that is, each additional local variable allocated
908 goes at a more negative offset in the frame. */
909 #define FRAME_GROWS_DOWNWARD
911 /* Offset within stack frame to start allocating local variables at.
912 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
913 first local allocated. Otherwise, it is the offset to the BEGINNING
914 of the first local allocated. */
915 #define STARTING_FRAME_OFFSET 0
917 /* If we generate an insn to push BYTES bytes,
918 this says how many the stack pointer really advances by.
919 On the 68000, sp@- in a byte insn really pushes a word.
920 On the 5200 (coldfire), sp@- in a byte insn pushes just a byte. */
921 #define PUSH_ROUNDING(BYTES) (TARGET_5200 ? BYTES : ((BYTES) + 1) & ~1)
923 /* Offset of first parameter from the argument pointer register value. */
924 #define FIRST_PARM_OFFSET(FNDECL) 8
926 /* Value is the number of byte of arguments automatically
927 popped when returning from a subroutine call.
928 FUNDECL is the declaration node of the function (as a tree),
929 FUNTYPE is the data type of the function (as a tree),
930 or for a library call it is an identifier node for the subroutine name.
931 SIZE is the number of bytes of arguments passed on the stack.
933 On the 68000, the RTS insn cannot pop anything.
934 On the 68010, the RTD insn may be used to pop them if the number
935 of args is fixed, but if the number is variable then the caller
936 must pop them all. RTD can't be used for library calls now
937 because the library is compiled with the Unix compiler.
938 Use of RTD is a selectable option, since it is incompatible with
939 standard Unix calling sequences. If the option is not selected,
940 the caller must always pop the args. */
942 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
943 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \
944 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
945 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
946 == void_type_node))) \
949 /* Define how to find the value returned by a function.
950 VALTYPE is the data type of the value (as a tree).
951 If the precise function being called is known, FUNC is its FUNCTION_DECL;
952 otherwise, FUNC is 0. */
954 /* On the 68000 the return value is in D0 regardless. */
956 #define FUNCTION_VALUE(VALTYPE, FUNC) \
957 gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
959 /* Define how to find the value returned by a library function
960 assuming the value has mode MODE. */
962 /* On the 68000 the return value is in D0 regardless. */
964 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
966 /* 1 if N is a possible register number for a function value.
967 On the 68000, d0 is the only register thus used. */
969 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
971 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
972 more than one register. */
974 #define NEEDS_UNTYPED_CALL 0
976 /* Define this if PCC uses the nonreentrant convention for returning
977 structure and union values. */
979 #define PCC_STATIC_STRUCT_RETURN
981 /* 1 if N is a possible register number for function argument passing.
982 On the 68000, no registers are used in this way. */
984 #define FUNCTION_ARG_REGNO_P(N) 0
986 /* Define a data type for recording info about an argument list
987 during the scan of that argument list. This data type should
988 hold all necessary information about the function itself
989 and about the args processed so far, enough to enable macros
990 such as FUNCTION_ARG to determine where the next arg should go.
992 On the m68k, this is a single integer, which is a number of bytes
993 of arguments scanned so far. */
995 #define CUMULATIVE_ARGS int
997 /* Initialize a variable CUM of type CUMULATIVE_ARGS
998 for a call to a function whose data type is FNTYPE.
999 For a library call, FNTYPE is 0.
1001 On the m68k, the offset starts at 0. */
1003 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1006 /* Update the data in CUM to advance over an argument
1007 of mode MODE and data type TYPE.
1008 (TYPE is null for libcalls where that information may not be available.) */
1010 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1011 ((CUM) += ((MODE) != BLKmode \
1012 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
1013 : (int_size_in_bytes (TYPE) + 3) & ~3))
1015 /* Define where to put the arguments to a function.
1016 Value is zero to push the argument on the stack,
1017 or a hard register in which to store the argument.
1019 MODE is the argument's machine mode.
1020 TYPE is the data type of the argument (as a tree).
1021 This is null for libcalls where that information may
1023 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1024 the preceding args and about the function being called.
1025 NAMED is nonzero if this argument is a named parameter
1026 (otherwise it is an extra parameter matching an ellipsis). */
1028 /* On the 68000 all args are pushed, except if -mregparm is specified
1029 then the first two words of arguments are passed in d0, d1.
1030 *NOTE* -mregparm does not work.
1031 It exists only to test register calling conventions. */
1033 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1034 ((TARGET_REGPARM && (CUM) < 8) ? gen_rtx_REG ((MODE), (CUM) / 4) : 0)
1036 /* For an arg passed partly in registers and partly in memory,
1037 this is the number of registers used.
1038 For args passed entirely in registers or entirely in memory, zero. */
1040 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1041 ((TARGET_REGPARM && (CUM) < 8 \
1042 && 8 < ((CUM) + ((MODE) == BLKmode \
1043 ? int_size_in_bytes (TYPE) \
1044 : GET_MODE_SIZE (MODE)))) \
1045 ? 2 - (CUM) / 4 : 0)
1047 /* Generate the assembly code for function entry. */
1048 #define FUNCTION_PROLOGUE(FILE, SIZE) output_function_prologue(FILE, SIZE)
1050 /* Output assembler code to FILE to increment profiler label # LABELNO
1051 for profiling a function entry. */
1053 #define FUNCTION_PROFILER(FILE, LABELNO) \
1054 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO))
1056 /* Output assembler code to FILE to initialize this source file's
1057 basic block profiling info, if that has not already been done. */
1059 #define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL) \
1062 switch (profile_block_flag) \
1065 asm_fprintf (FILE, "\tpea %d\n\tpea %LLPBX0\n\tjsr %U__bb_init_trace_func\n\taddql %I8,%Rsp\n", \
1066 (BLOCK_OR_LABEL)); \
1070 asm_fprintf (FILE, "\ttstl %LLPBX0\n\tbne %LLPI%d\n\tpea %LLPBX0\n\tjsr %U__bb_init_func\n\taddql %I4,%Rsp\n%LLPI%d:\n", \
1071 (BLOCK_OR_LABEL), (BLOCK_OR_LABEL)); \
1077 /* Output assembler code to FILE to increment the counter for
1078 the BLOCKNO'th basic block in this source file. */
1080 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1083 switch (profile_block_flag) \
1086 asm_fprintf (FILE, "\tmovel %Ra1,%Rsp@-\n\tlea ___bb,%Ra1\n\tmovel %I%d,%Ra1@(0)\n\tmovel %I%LLPBX0,%Ra1@(4)\n\tmovel %Rsp@+,%Ra1\n\tjsr %U__bb_trace_func\n", \
1091 asm_fprintf (FILE, "\taddql %I1,%LLPBX2+%d\n", 4 * BLOCKNO); \
1097 /* Output assembler code to FILE to indicate return from
1098 a function during basic block profiling. */
1100 #define FUNCTION_BLOCK_PROFILER_EXIT(FILE) \
1101 asm_fprintf (FILE, "\tjsr %U__bb_trace_ret\n");
1103 /* Save all registers which may be clobbered by a function call.
1104 MACHINE_STATE_SAVE and MACHINE_STATE_RESTORE are target-code macros,
1105 used in libgcc2.c. They may not refer to TARGET_* macros !!! */
1106 #if defined (__mc68010__) || defined(mc68010) \
1107 || defined(__mc68020__) || defined(mc68020) \
1108 || defined(__mc68030__) || defined(mc68030) \
1109 || defined(__mc68040__) || defined(mc68040) \
1110 || defined(__mcpu32__) || defined(mcpu32)
1111 #define MACHINE_STATE_m68010_up
1115 #if defined(__mcf5200__)
1116 #define MACHINE_STATE_SAVE(id) \
1118 asm ("sub.l 20,%sp"); \
1119 asm ("movm.l &0x0303,4(%sp)"); \
1120 asm ("move.w %ccr,%d0"); \
1121 asm ("movm.l &0x0001,(%sp)"); \
1123 #else /* !__mcf5200__ */
1124 #if defined(MACHINE_STATE_m68010_up)
1126 /* HPUX assembler does not accept %ccr. */
1127 #define MACHINE_STATE_SAVE(id) \
1129 asm ("move.w %cc,-(%sp)"); \
1130 asm ("movm.l &0xc0c0,-(%sp)"); \
1132 #else /* ! __HPUX_ASM__ */
1133 #define MACHINE_STATE_SAVE(id) \
1135 asm ("move.w %ccr,-(%sp)"); \
1136 asm ("movm.l &0xc0c0,-(%sp)"); \
1138 #endif /* __HPUX_ASM__ */
1139 #else /* !MACHINE_STATE_m68010_up */
1140 #define MACHINE_STATE_SAVE(id) \
1142 asm ("move.w %sr,-(%sp)"); \
1143 asm ("movm.l &0xc0c0,-(%sp)"); \
1145 #endif /* MACHINE_STATE_m68010_up */
1146 #endif /* __mcf5200__ */
1147 #else /* !MOTOROLA */
1148 #if defined(__mcf5200__)
1149 #define MACHINE_STATE_SAVE(id) \
1151 asm ("subl %#20,%/sp" : ); \
1152 asm ("movml %/d0/%/d1/%/a0/%/a1,%/sp@(4)" : ); \
1153 asm ("movew %/cc,%/d0" : ); \
1154 asm ("movml %/d0,%/sp@" : ); \
1156 #else /* !__mcf5200__ */
1157 #if defined(MACHINE_STATE_m68010_up)
1158 #define MACHINE_STATE_SAVE(id) \
1160 asm ("movew %/cc,%/sp@-" : ); \
1161 asm ("moveml %/d0/%/d1/%/a0/%/a1,%/sp@-" : ); \
1163 #else /* !MACHINE_STATE_m68010_up */
1164 #define MACHINE_STATE_SAVE(id) \
1166 asm ("movew %/sr,%/sp@-" : ); \
1167 asm ("moveml %/d0/%/d1/%/a0/%/a1,%/sp@-" : ); \
1169 #endif /* MACHINE_STATE_m68010_up */
1170 #endif /* __mcf5200__ */
1171 #endif /* MOTOROLA */
1173 /* Restore all registers saved by MACHINE_STATE_SAVE. */
1176 #if defined(__mcf5200__)
1177 #define MACHINE_STATE_RESTORE(id) \
1179 asm ("movm.l (%sp),&0x0001"); \
1180 asm ("move.w %d0,%ccr"); \
1181 asm ("movm.l 4(%sp),&0x0303"); \
1182 asm ("add.l 20,%sp"); \
1184 #else /* !__mcf5200__ */
1186 /* HPUX assembler does not accept %ccr. */
1187 #define MACHINE_STATE_RESTORE(id) \
1189 asm ("movm.l (%sp)+,&0x0303"); \
1190 asm ("move.w (%sp)+,%cc"); \
1192 #else /* ! __HPUX_ASM__ */
1193 #define MACHINE_STATE_RESTORE(id) \
1195 asm ("movm.l (%sp)+,&0x0303"); \
1196 asm ("move.w (%sp)+,%ccr"); \
1198 #endif /* __HPUX_ASM__ */
1199 #endif /* __mcf5200__ */
1200 #else /* !MOTOROLA */
1201 #if defined(__mcf5200__)
1202 #define MACHINE_STATE_RESTORE(id) \
1204 asm ("movml %/sp@,%/d0" : ); \
1205 asm ("movew %/d0,%/cc" : ); \
1206 asm ("movml %/sp@(4),%/d0/%/d1/%/a0/%/a1" : ); \
1207 asm ("addl %#20,%/sp" : ); \
1209 #else /* !__mcf5200__ */
1210 #define MACHINE_STATE_RESTORE(id) \
1212 asm ("moveml %/sp@+,%/d0/%/d1/%/a0/%/a1" : ); \
1213 asm ("movew %/sp@+,%/cc" : ); \
1215 #endif /* __mcf5200__ */
1216 #endif /* MOTOROLA */
1218 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1219 the stack pointer does not matter. The value is tested only in
1220 functions that have frame pointers.
1221 No definition is equivalent to always zero. */
1223 #define EXIT_IGNORE_STACK 1
1225 /* Generate the assembly code for function exit. */
1226 #define FUNCTION_EPILOGUE(FILE, SIZE) output_function_epilogue (FILE, SIZE)
1228 /* This is a hook for other tm files to change. */
1229 /* #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) */
1231 /* Determine if the epilogue should be output as RTL.
1232 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1233 #define USE_RETURN_INSN use_return_insn ()
1235 /* Store in the variable DEPTH the initial difference between the
1236 frame pointer reg contents and the stack pointer reg contents,
1237 as of the start of the function body. This depends on the layout
1238 of the fixed parts of the stack frame and on how registers are saved.
1240 On the 68k, if we have a frame, we must add one word to its length
1241 to allow for the place that a6 is stored when we do have a frame pointer.
1242 Otherwise, we would need to compute the offset from the frame pointer
1243 of a local variable as a function of frame_pointer_needed, which
1246 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
1249 for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \
1250 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1252 for (regno = 0; regno < 16; regno++) \
1253 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1255 if (flag_pic && current_function_uses_pic_offset_table) \
1257 (DEPTH) = (offset + ((get_frame_size () + 3) & -4) \
1258 + (get_frame_size () == 0 ? 0 : 4)); \
1261 /* Output assembler code for a block containing the constant parts
1262 of a trampoline, leaving space for the variable parts. */
1264 /* On the 68k, the trampoline looks like this:
1268 WARNING: Targets that may run on 68040+ cpus must arrange for
1269 the instruction cache to be flushed. Previous incarnations of
1270 the m68k trampoline code attempted to get around this by either
1271 using an out-of-line transfer function or pc-relative data, but
1272 the fact remains that the code to jump to the transfer function
1273 or the code to load the pc-relative data needs to be flushed
1274 just as much as the "variable" portion of the trampoline.
1275 Recognizing that a cache flush is going to be required anyway,
1276 dispense with such notions and build a smaller trampoline. */
1278 /* Since more instructions are required to move a template into
1279 place than to create it on the spot, don't use a template. */
1281 /* Length in units of the trampoline for entering a nested function. */
1283 #define TRAMPOLINE_SIZE 12
1285 /* Alignment required for a trampoline in bits. */
1287 #define TRAMPOLINE_ALIGNMENT 16
1289 /* Targets redefine this to invoke code to either flush the cache,
1290 or enable stack execution (or both). */
1292 #ifndef FINALIZE_TRAMPOLINE
1293 #define FINALIZE_TRAMPOLINE(TRAMP)
1296 /* Emit RTL insns to initialize the variable parts of a trampoline.
1297 FNADDR is an RTX for the address of the function's pure code.
1298 CXT is an RTX for the static chain value for the function.
1300 We generate a two-instructions program at address TRAMP :
1304 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1306 emit_move_insn (gen_rtx_MEM (HImode, TRAMP), GEN_INT(0x207C)); \
1307 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \
1308 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \
1310 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \
1311 FINALIZE_TRAMPOLINE(TRAMP); \
1314 /* This is the library routine that is used
1315 to transfer control from the trampoline
1316 to the actual nested function.
1317 It is defined for backward compatibility,
1318 for linking with object code that used the old
1319 trampoline definition. */
1321 /* A colon is used with no explicit operands
1322 to cause the template string to be scanned for %-constructs. */
1323 /* The function name __transfer_from_trampoline is not actually used.
1324 The function definition just permits use of "asm with operands"
1325 (though the operand list is empty). */
1326 #define TRANSFER_FROM_TRAMPOLINE \
1328 __transfer_from_trampoline () \
1330 register char *a0 asm ("%a0"); \
1331 asm (GLOBAL_ASM_OP " ___trampoline"); \
1332 asm ("___trampoline:"); \
1333 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \
1334 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \
1338 /* Addressing modes, and classification of registers for them. */
1340 #define HAVE_POST_INCREMENT 1
1341 /* #define HAVE_POST_DECREMENT 0 */
1343 #define HAVE_PRE_DECREMENT 1
1344 /* #define HAVE_PRE_INCREMENT 0 */
1346 /* Macros to check register numbers against specific register classes. */
1348 /* These assume that REGNO is a hard or pseudo reg number.
1349 They give nonzero only if REGNO is a hard reg of the suitable class
1350 or a pseudo reg currently allocated to a suitable hard reg.
1351 Since they use reg_renumber, they are safe only once reg_renumber
1352 has been allocated, which happens in local-alloc.c. */
1354 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1355 ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
1356 #define REGNO_OK_FOR_BASE_P(REGNO) \
1357 (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
1358 #define REGNO_OK_FOR_DATA_P(REGNO) \
1359 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
1360 #define REGNO_OK_FOR_FP_P(REGNO) \
1361 (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
1362 #ifdef SUPPORT_SUN_FPA
1363 #define REGNO_OK_FOR_FPA_P(REGNO) \
1364 (((REGNO) >= 24 && (REGNO) < 56) || (reg_renumber[REGNO] >= 24 && reg_renumber[REGNO] < 56))
1367 /* Now macros that check whether X is a register and also,
1368 strictly, whether it is in a specified class.
1370 These macros are specific to the 68000, and may be used only
1371 in code for printing assembler insns and in conditions for
1372 define_optimization. */
1374 /* 1 if X is a data register. */
1376 #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
1378 /* 1 if X is an fp register. */
1380 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1382 /* 1 if X is an address register */
1384 #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
1386 #ifdef SUPPORT_SUN_FPA
1387 /* 1 if X is a register in the Sun FPA. */
1388 #define FPA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FPA_P (REGNO (X)))
1390 /* Answer must be no if we don't have an FPA. */
1391 #define FPA_REG_P(X) 0
1394 /* Maximum number of registers that can appear in a valid memory address. */
1396 #define MAX_REGS_PER_ADDRESS 2
1398 /* Recognize any constant value that is a valid address. */
1400 #define CONSTANT_ADDRESS_P(X) \
1401 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1402 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1403 || GET_CODE (X) == HIGH)
1405 /* Nonzero if the constant value X is a legitimate general operand.
1406 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1408 #define LEGITIMATE_CONSTANT_P(X) 1
1410 /* Nonzero if the constant value X is a legitimate general operand
1411 when generating PIC code. It is given that flag_pic is on and
1412 that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1414 PCREL_GENERAL_OPERAND_OK makes reload accept addresses that are
1415 accepted by insn predicates, but which would otherwise fail the
1416 `general_operand' test. */
1418 #ifndef REG_OK_STRICT
1419 #define PCREL_GENERAL_OPERAND_OK 0
1421 #define PCREL_GENERAL_OPERAND_OK (TARGET_PCREL)
1424 #define LEGITIMATE_PIC_OPERAND_P(X) \
1425 ((! symbolic_operand (X, VOIDmode) \
1426 && ! (GET_CODE (X) == CONST_DOUBLE && CONST_DOUBLE_MEM (X) \
1427 && GET_CODE (CONST_DOUBLE_MEM (X)) == MEM \
1428 && symbolic_operand (XEXP (CONST_DOUBLE_MEM (X), 0), \
1430 || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \
1431 || PCREL_GENERAL_OPERAND_OK)
1433 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1434 and check its validity for a certain class.
1435 We have two alternate definitions for each of them.
1436 The usual definition accepts all pseudo regs; the other rejects
1437 them unless they have been allocated suitable hard regs.
1438 The symbol REG_OK_STRICT causes the latter definition to be used.
1440 Most source files want to accept pseudo regs in the hope that
1441 they will get allocated to the class that the insn wants them to be in.
1442 Source files for reload pass need to be strict.
1443 After reload, it makes no difference, since pseudo regs have
1444 been eliminated by then. */
1446 #ifndef REG_OK_STRICT
1448 /* Nonzero if X is a hard reg that can be used as an index
1449 or if it is a pseudo reg. */
1450 #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
1451 /* Nonzero if X is a hard reg that can be used as a base reg
1452 or if it is a pseudo reg. */
1453 #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
1457 /* Nonzero if X is a hard reg that can be used as an index. */
1458 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1459 /* Nonzero if X is a hard reg that can be used as a base reg. */
1460 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1464 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1465 that is a valid memory address for an instruction.
1466 The MODE argument is the machine mode for the MEM expression
1467 that wants to use this address.
1469 When generating PIC, an address involving a SYMBOL_REF is legitimate
1470 if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF.
1471 We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses,
1472 and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF.
1474 Likewise for a LABEL_REF when generating PIC.
1476 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1478 /* Allow SUBREG everywhere we allow REG. This results in better code. It
1479 also makes function inlining work when inline functions are called with
1480 arguments that are SUBREGs. */
1482 #define LEGITIMATE_BASE_REG_P(X) \
1483 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1484 || (GET_CODE (X) == SUBREG \
1485 && GET_CODE (SUBREG_REG (X)) == REG \
1486 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1488 #define INDIRECTABLE_1_ADDRESS_P(X) \
1489 ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \
1490 || LEGITIMATE_BASE_REG_P (X) \
1491 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
1492 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
1493 || (GET_CODE (X) == PLUS \
1494 && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
1495 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1497 || ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) \
1498 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1499 && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \
1500 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1501 && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF))
1503 #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
1504 { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
1506 /* Only labels on dispatch tables are valid for indexing from. */
1507 #define GO_IF_INDEXABLE_BASE(X, ADDR) \
1509 if (GET_CODE (X) == LABEL_REF \
1510 && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \
1511 && GET_CODE (temp) == JUMP_INSN \
1512 && (GET_CODE (PATTERN (temp)) == ADDR_VEC \
1513 || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \
1515 if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; }
1517 #define GO_IF_INDEXING(X, ADDR) \
1518 { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
1519 { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
1520 if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
1521 { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
1523 #define GO_IF_INDEXED_ADDRESS(X, ADDR) \
1524 { GO_IF_INDEXING (X, ADDR); \
1525 if (GET_CODE (X) == PLUS) \
1526 { if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1527 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)) \
1528 { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \
1529 if (GET_CODE (XEXP (X, 0)) == CONST_INT \
1530 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)) \
1531 { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
1533 /* coldfire/5200 does not allow HImode index registers. */
1534 #define LEGITIMATE_INDEX_REG_P(X) \
1535 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1537 && GET_CODE (X) == SIGN_EXTEND \
1538 && GET_CODE (XEXP (X, 0)) == REG \
1539 && GET_MODE (XEXP (X, 0)) == HImode \
1540 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
1541 || (GET_CODE (X) == SUBREG \
1542 && GET_CODE (SUBREG_REG (X)) == REG \
1543 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1545 #define LEGITIMATE_INDEX_P(X) \
1546 (LEGITIMATE_INDEX_REG_P (X) \
1547 || ((TARGET_68020 || TARGET_5200) && GET_CODE (X) == MULT \
1548 && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
1549 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1550 && (INTVAL (XEXP (X, 1)) == 2 \
1551 || INTVAL (XEXP (X, 1)) == 4 \
1552 || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_5200))))
1554 /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */
1555 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1556 { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
1557 GO_IF_INDEXED_ADDRESS (X, ADDR); \
1558 if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \
1559 && LEGITIMATE_INDEX_P (XEXP (X, 0)) \
1560 && GET_CODE (XEXP (X, 1)) == LABEL_REF) \
1563 /* Don't call memory_address_noforce for the address to fetch
1564 the switch offset. This address is ok as it stands (see above),
1565 but memory_address_noforce would alter it. */
1566 #define PIC_CASE_VECTOR_ADDRESS(index) index
1568 /* Try machine-dependent ways of modifying an illegitimate address
1569 to be legitimate. If we find one, return the new, valid address.
1570 This macro is used in only one place: `memory_address' in explow.c.
1572 OLDX is the address as it was before break_out_memory_refs was called.
1573 In some cases it is useful to look at this to decide what needs to be done.
1575 MODE and WIN are passed so that this macro can use
1576 GO_IF_LEGITIMATE_ADDRESS.
1578 It is always safe for this macro to do nothing. It exists to recognize
1579 opportunities to optimize the output.
1581 For the 68000, we handle X+REG by loading X into a register R and
1582 using R+REG. R will go in an address reg and indexing will be used.
1583 However, if REG is a broken-out memory address or multiplication,
1584 nothing needs to be done because REG can certainly go in an address reg. */
1586 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1587 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1588 { register int ch = (X) != (OLDX); \
1589 if (GET_CODE (X) == PLUS) \
1591 if (GET_CODE (XEXP (X, 0)) == MULT) \
1592 { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \
1593 if (GET_CODE (XEXP (X, 1)) == MULT) \
1594 { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \
1595 if (ch && GET_CODE (XEXP (X, 1)) == REG \
1596 && GET_CODE (XEXP (X, 0)) == REG) \
1598 if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
1599 if (GET_CODE (XEXP (X, 0)) == REG \
1600 || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
1601 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1602 && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
1603 { register rtx temp = gen_reg_rtx (Pmode); \
1604 register rtx val = force_operand (XEXP (X, 1), 0); \
1605 emit_move_insn (temp, val); \
1607 XEXP (X, 1) = temp; \
1609 else if (GET_CODE (XEXP (X, 1)) == REG \
1610 || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
1611 && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
1612 && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
1613 { register rtx temp = gen_reg_rtx (Pmode); \
1614 register rtx val = force_operand (XEXP (X, 0), 0); \
1615 emit_move_insn (temp, val); \
1617 XEXP (X, 0) = temp; \
1620 /* Go to LABEL if ADDR (a legitimate address expression)
1621 has an effect that depends on the machine mode it is used for.
1622 On the 68000, only predecrement and postincrement address depend thus
1623 (the amount of decrement or increment being the length of the operand). */
1625 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1626 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL
1628 /* Specify the machine mode that this machine uses
1629 for the index in the tablejump instruction. */
1630 #define CASE_VECTOR_MODE HImode
1632 /* Define as C expression which evaluates to nonzero if the tablejump
1633 instruction expects the table to contain offsets from the address of the
1635 Do not define this if the table should contain absolute addresses. */
1636 #define CASE_VECTOR_PC_RELATIVE 1
1638 /* Specify the tree operation to be used to convert reals to integers. */
1639 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1641 /* This is the kind of divide that is easiest to do in the general case. */
1642 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1644 /* Define this as 1 if `char' should by default be signed; else as 0. */
1645 #define DEFAULT_SIGNED_CHAR 1
1647 /* Don't cse the address of the function being compiled. */
1648 #define NO_RECURSIVE_FUNCTION_CSE
1650 /* Max number of bytes we can move from memory to memory
1651 in one reasonably fast instruction. */
1654 /* Define this if zero-extension is slow (more than one real instruction). */
1655 #define SLOW_ZERO_EXTEND
1657 /* Nonzero if access to memory by bytes is slow and undesirable. */
1658 #define SLOW_BYTE_ACCESS 0
1660 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1661 is done just by pretending it is already truncated. */
1662 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1664 /* We assume that the store-condition-codes instructions store 0 for false
1665 and some other value for true. This is the value stored for true. */
1667 #define STORE_FLAG_VALUE -1
1669 /* When a prototype says `char' or `short', really pass an `int'. */
1670 #define PROMOTE_PROTOTYPES 1
1672 /* Specify the machine mode that pointers have.
1673 After generation of rtl, the compiler makes no further distinction
1674 between pointers and any other objects of this machine mode. */
1675 #define Pmode SImode
1677 /* A function address in a call instruction
1678 is a byte address (for indexing purposes)
1679 so give the MEM rtx a byte's mode. */
1680 #define FUNCTION_MODE QImode
1682 /* Compute the cost of computing a constant rtl expression RTX
1683 whose rtx-code is CODE. The body of this macro is a portion
1684 of a switch statement. If the code is computed here,
1685 return it with a return statement. Otherwise, break from the switch. */
1687 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1689 /* Constant zero is super cheap due to clr instruction. */ \
1690 if (RTX == const0_rtx) return 0; \
1691 /* if ((OUTER_CODE) == SET) */ \
1692 return const_int_cost(RTX); \
1697 case CONST_DOUBLE: \
1700 /* Compute the cost of various arithmetic operations.
1701 These are vaguely right for a 68020. */
1702 /* The costs for long multiply have been adjusted to
1703 work properly in synth_mult on the 68020,
1704 relative to an average of the time for add and the time for shift,
1705 taking away a little more because sometimes move insns are needed. */
1706 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */
1707 #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : 13)
1708 #define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : 5)
1709 #define DIVW_COST (TARGET_68020 ? 27 : 12)
1711 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1713 /* An lea costs about three times as much as a simple add. */ \
1714 if (GET_MODE (X) == SImode \
1715 && GET_CODE (XEXP (X, 1)) == REG \
1716 && GET_CODE (XEXP (X, 0)) == MULT \
1717 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1718 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1719 && (INTVAL (XEXP (XEXP (X, 0), 1)) == 2 \
1720 || INTVAL (XEXP (XEXP (X, 0), 1)) == 4 \
1721 || INTVAL (XEXP (XEXP (X, 0), 1)) == 8)) \
1722 return COSTS_N_INSNS (3); /* lea an@(dx:l:i),am */ \
1728 return COSTS_N_INSNS(1); \
1729 if (! TARGET_68020) \
1731 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
1733 if (INTVAL (XEXP (X, 1)) < 16) \
1734 return COSTS_N_INSNS (2) + INTVAL (XEXP (X, 1)) / 2; \
1736 /* We're using clrw + swap for these cases. */ \
1737 return COSTS_N_INSNS (4) + (INTVAL (XEXP (X, 1)) - 16) / 2; \
1739 return COSTS_N_INSNS (10); /* worst case */ \
1741 /* A shift by a big integer takes an extra instruction. */ \
1742 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1743 && (INTVAL (XEXP (X, 1)) == 16)) \
1744 return COSTS_N_INSNS (2); /* clrw;swap */ \
1745 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1746 && !(INTVAL (XEXP (X, 1)) > 0 \
1747 && INTVAL (XEXP (X, 1)) <= 8)) \
1748 return COSTS_N_INSNS (3); /* lsr #i,dn */ \
1751 if ((GET_CODE (XEXP (X, 0)) == ZERO_EXTEND \
1752 || GET_CODE (XEXP (X, 0)) == SIGN_EXTEND) \
1753 && GET_MODE (X) == SImode) \
1754 return COSTS_N_INSNS (MULW_COST); \
1755 if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \
1756 return COSTS_N_INSNS (MULW_COST); \
1758 return COSTS_N_INSNS (MULL_COST); \
1763 if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \
1764 return COSTS_N_INSNS (DIVW_COST); /* div.w */ \
1765 return COSTS_N_INSNS (43); /* div.l */
1767 /* Tell final.c how to eliminate redundant test instructions. */
1769 /* Here we define machine-dependent flags and fields in cc_status
1770 (see `conditions.h'). */
1772 /* Set if the cc value is actually in the 68881, so a floating point
1773 conditional branch must be output. */
1774 #define CC_IN_68881 04000
1776 /* Store in cc_status the expressions that the condition codes will
1777 describe after execution of an instruction whose pattern is EXP.
1778 Do not alter them if the instruction would not alter the cc's. */
1780 /* On the 68000, all the insns to store in an address register fail to
1781 set the cc's. However, in some cases these instructions can make it
1782 possibly invalid to use the saved cc's. In those cases we clear out
1783 some or all of the saved cc's so they won't be used. */
1785 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
1787 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
1788 { if (cc_prev_status.flags & CC_IN_68881) \
1790 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
1794 /* Control the assembler format that we output. */
1796 /* Output at beginning of assembler file. */
1798 #define ASM_FILE_START(FILE) \
1799 fprintf (FILE, "#NO_APP\n");
1801 /* Output to assembler file text saying following lines
1802 may contain character constants, extra white space, comments, etc. */
1804 #define ASM_APP_ON "#APP\n"
1806 /* Output to assembler file text saying following lines
1807 no longer contain unusual constructs. */
1809 #define ASM_APP_OFF "#NO_APP\n"
1811 /* Output before read-only data. */
1813 #define TEXT_SECTION_ASM_OP ".text"
1815 /* Output before writable data. */
1817 #define DATA_SECTION_ASM_OP ".data"
1819 /* Here are four prefixes that are used by asm_fprintf to
1820 facilitate customization for alternate assembler syntaxes.
1821 Machines with no likelihood of an alternate syntax need not
1822 define these and need not use asm_fprintf. */
1824 /* The prefix for register names. Note that REGISTER_NAMES
1825 is supposed to include this prefix. */
1827 #define REGISTER_PREFIX ""
1829 /* The prefix for local labels. You should be able to define this as
1830 an empty string, or any arbitrary string (such as ".", ".L%", etc)
1831 without having to make any other changes to account for the specific
1832 definition. Note it is a string literal, not interpreted by printf
1835 #define LOCAL_LABEL_PREFIX ""
1837 /* The prefix to add to user-visible assembler symbols. */
1839 #define USER_LABEL_PREFIX "_"
1841 /* The prefix for immediate operands. */
1843 #define IMMEDIATE_PREFIX "#"
1845 /* How to refer to registers in assembler output.
1846 This sequence is indexed by compiler's hard-register-number (see above). */
1848 #ifndef SUPPORT_SUN_FPA
1850 #define REGISTER_NAMES \
1851 {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \
1852 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \
1853 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7" }
1855 #else /* SUPPORTED_SUN_FPA */
1857 #define REGISTER_NAMES \
1858 {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \
1859 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \
1860 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", \
1861 "fpa0", "fpa1", "fpa2", "fpa3", "fpa4", "fpa5", "fpa6", "fpa7", \
1862 "fpa8", "fpa9", "fpa10", "fpa11", "fpa12", "fpa13", "fpa14", "fpa15", \
1863 "fpa16", "fpa17", "fpa18", "fpa19", "fpa20", "fpa21", "fpa22", "fpa23", \
1864 "fpa24", "fpa25", "fpa26", "fpa27", "fpa28", "fpa29", "fpa30", "fpa31" }
1866 #endif /* defined SUPPORT_SUN_FPA */
1868 /* How to renumber registers for dbx and gdb.
1869 On the Sun-3, the floating point registers have numbers
1870 18 to 25, not 16 to 23 as they do in the compiler. */
1872 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
1874 /* Before the prologue, RA is at 0(%sp). */
1875 #define INCOMING_RETURN_ADDR_RTX \
1876 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
1878 /* We must not use the DBX register numbers for the DWARF 2 CFA column
1879 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
1880 Instead use the identity mapping. */
1881 #define DWARF_FRAME_REGNUM(REG) REG
1883 /* Before the prologue, the top of the frame is at 4(%sp). */
1884 #define INCOMING_FRAME_SP_OFFSET 4
1886 /* This is how to output the definition of a user-level label named NAME,
1887 such as the label on a static function or variable NAME. */
1889 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1890 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1892 /* This is how to output a command to make the user-level label named NAME
1893 defined for reference from other files. */
1895 #define GLOBAL_ASM_OP ".globl"
1896 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1897 do { fprintf (FILE, "%s ", GLOBAL_ASM_OP); \
1898 assemble_name (FILE, NAME); \
1899 fputs ("\n", FILE);} while (0)
1901 /* This is how to output a reference to a user-level label named NAME.
1902 `assemble_name' uses this. */
1904 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1905 asm_fprintf (FILE, "%0U%s", NAME)
1907 /* This is how to output an internal numbered label where
1908 PREFIX is the class of label and NUM is the number within the class. */
1910 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1911 asm_fprintf (FILE, "%0L%s%d:\n", PREFIX, NUM)
1913 /* This is how to store into the string LABEL
1914 the symbol_ref name of an internal numbered label where
1915 PREFIX is the class of label and NUM is the number within the class.
1916 This is suitable for output with `assemble_name'. */
1918 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1919 sprintf (LABEL, "*%s%s%d", LOCAL_LABEL_PREFIX, PREFIX, NUM)
1921 /* This is how to output a `long double' extended real constant. */
1923 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
1925 REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \
1926 fprintf (FILE, "\t.long 0x%lx,0x%lx,0x%lx\n", l[0], l[1], l[2]); \
1929 /* This is how to output an assembler line defining a `double' constant. */
1931 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1932 do { char dstr[30]; \
1933 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
1934 fprintf (FILE, "\t.double 0r%s\n", dstr); \
1937 /* This is how to output an assembler line defining a `float' constant. */
1939 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1941 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1942 fprintf (FILE, "\t.long 0x%lx\n", l); \
1945 /* This is how to output an assembler line defining an `int' constant. */
1947 #define ASM_OUTPUT_INT(FILE,VALUE) \
1948 ( fprintf (FILE, "\t.long "), \
1949 output_addr_const (FILE, (VALUE)), \
1950 fprintf (FILE, "\n"))
1952 /* Likewise for `char' and `short' constants. */
1954 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1955 ( fprintf (FILE, "\t.word "), \
1956 output_addr_const (FILE, (VALUE)), \
1957 fprintf (FILE, "\n"))
1959 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1960 ( fprintf (FILE, "\t.byte "), \
1961 output_addr_const (FILE, (VALUE)), \
1962 fprintf (FILE, "\n"))
1964 /* This is how to output an assembler line for a numeric constant byte. */
1966 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1967 fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
1969 /* This is how to output an insn to push a register on the stack.
1970 It need not be very fast code. */
1972 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1973 asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO])
1975 /* This is how to output an insn to pop a register from the stack.
1976 It need not be very fast code. */
1978 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1979 asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO])
1981 /* This is how to output an element of a case-vector that is absolute.
1982 (The 68000 does not use such vectors,
1983 but we must define this macro anyway.) */
1985 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1986 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE)
1988 /* This is how to output an element of a case-vector that is relative. */
1990 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1991 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL)
1993 /* This is how to output an assembler line
1994 that says to advance the location counter
1995 to a multiple of 2**LOG bytes. */
1997 /* We don't have a way to align to more than a two-byte boundary, so do the
1998 best we can and don't complain. */
1999 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2001 fprintf (FILE, "\t.even\n");
2003 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2004 fprintf (FILE, "\t.skip %u\n", (SIZE))
2006 /* This says how to output an assembler line
2007 to define a global common symbol. */
2009 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2010 ( fputs (".comm ", (FILE)), \
2011 assemble_name ((FILE), (NAME)), \
2012 fprintf ((FILE), ",%u\n", (ROUNDED)))
2014 /* This says how to output an assembler line
2015 to define a local common symbol. */
2017 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
2018 ( fputs (".lcomm ", (FILE)), \
2019 assemble_name ((FILE), (NAME)), \
2020 fprintf ((FILE), ",%u\n", (ROUNDED)))
2022 /* Store in OUTPUT a string (made with alloca) containing
2023 an assembler-name for a local static variable named NAME.
2024 LABELNO is an integer which is different for each call. */
2026 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2027 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2028 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2030 /* Define the parentheses used to group arithmetic operations
2031 in assembler code. */
2033 #define ASM_OPEN_PAREN "("
2034 #define ASM_CLOSE_PAREN ")"
2036 /* Define results of standard character escape sequences. */
2037 #define TARGET_BELL 007
2038 #define TARGET_BS 010
2039 #define TARGET_TAB 011
2040 #define TARGET_NEWLINE 012
2041 #define TARGET_VT 013
2042 #define TARGET_FF 014
2043 #define TARGET_CR 015
2045 /* Output a float value (represented as a C double) as an immediate operand.
2046 This macro is a 68k-specific macro. */
2048 #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
2053 REAL_VALUE_TO_DECIMAL (VALUE, "%.9g", dstr); \
2054 asm_fprintf ((FILE), "%I0r%s", dstr); \
2059 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
2060 asm_fprintf ((FILE), "%I0x%lx", l); \
2064 /* Output a double value (represented as a C double) as an immediate operand.
2065 This macro is a 68k-specific macro. */
2066 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
2067 do { char dstr[30]; \
2068 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
2069 asm_fprintf (FILE, "%I0r%s", dstr); \
2072 /* Note, long double immediate operands are not actually
2073 generated by m68k.md. */
2074 #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \
2075 do { char dstr[30]; \
2076 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
2077 asm_fprintf (FILE, "%I0r%s", dstr); \
2080 /* Print operand X (an rtx) in assembler syntax to file FILE.
2081 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2082 For `%' followed by punctuation, CODE is the punctuation and X is null.
2084 On the 68000, we use several CODE characters:
2085 '.' for dot needed in Motorola-style opcode names.
2086 '-' for an operand pushing on the stack:
2087 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2088 '+' for an operand pushing on the stack:
2089 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2090 '@' for a reference to the top word on the stack:
2091 sp@, (sp) or (%sp) depending on the style of syntax.
2092 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2093 but & in SGS syntax).
2094 '!' for the fpcr register (used in some float-to-fixed conversions).
2095 '$' for the letter `s' in an op code, but only on the 68040.
2096 '&' for the letter `d' in an op code, but only on the 68040.
2097 '/' for register prefix needed by longlong.h.
2099 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2100 'd' to force memory addressing to be absolute, not relative.
2101 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2102 'o' for operands to go directly to output_operand_address (bypassing
2103 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
2104 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
2105 than directly). Second part of 'y' below.
2106 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2107 or print pair of registers as rx:ry.
2108 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
2109 CONST_DOUBLE's as SunFPA constant RAM registers if
2110 possible, so it should not be used except for the SunFPA. */
2112 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2113 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
2114 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \
2115 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/')
2117 /* A C compound statement to output to stdio stream STREAM the
2118 assembler syntax for an instruction operand X. X is an RTL
2121 CODE is a value that can be used to specify one of several ways
2122 of printing the operand. It is used when identical operands
2123 must be printed differently depending on the context. CODE
2124 comes from the `%' specification that was used to request
2125 printing of the operand. If the specification was just `%DIGIT'
2126 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2127 is the ASCII code for LTR.
2129 If X is a register, this macro should print the register's name.
2130 The names can be found in an array `reg_names' whose type is
2131 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2133 When the machine description has a specification `%PUNCT' (a `%'
2134 followed by a punctuation character), this macro is called with
2135 a null pointer for X and the punctuation character for CODE.
2137 See m68k.c for the m68k specific codes. */
2139 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2141 /* A C compound statement to output to stdio stream STREAM the
2142 assembler syntax for an instruction operand that is a memory
2143 reference whose address is ADDR. ADDR is an RTL expression.
2145 On some machines, the syntax for a symbolic address depends on
2146 the section that the address refers to. On these machines,
2147 define the macro `ENCODE_SECTION_INFO' to store the information
2148 into the `symbol_ref', and then check for it here. */
2150 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2152 /* Variables in m68k.c */
2153 extern const char *m68k_align_loops_string;
2154 extern const char *m68k_align_jumps_string;
2155 extern const char *m68k_align_funcs_string;
2156 extern int m68k_align_loops;
2157 extern int m68k_align_jumps;
2158 extern int m68k_align_funcs;
2159 extern int m68k_last_compare_had_fp_operands;
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