1 /* Definitions of target machine for GNU compiler.
2 Sun 68000/68020 version.
3 Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 2000, 2001 Free Software Foundation, Inc.
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 /* Note that some other tm.h files include this one and then override
25 many of the definitions that relate to assembler syntax. */
28 /* Names to predefine in the preprocessor for this target machine. */
30 /* See sun3.h, sun2.h, isi.h for different CPP_PREDEFINES. */
32 /* Print subsidiary information on the compiler version in use. */
34 #define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)");
36 #define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)");
39 /* Define SUPPORT_SUN_FPA to include support for generating code for
40 the Sun Floating Point Accelerator, an optional product for Sun 3
41 machines. By default, it is not defined. Avoid defining it unless
42 you need to output code for the Sun3+FPA architecture, as it has the
43 effect of slowing down the register set operations in hard-reg-set.h
44 (total number of registers will exceed number of bits in a long,
45 if defined, causing the set operations to expand to loops).
46 SUPPORT_SUN_FPA is typically defined in sun3.h. */
48 /* Run-time compilation parameters selecting different hardware subsets. */
50 extern int target_flags;
52 /* Macros used in the machine description to test the flags. */
54 /* Compile for a 68020 (not a 68000 or 68010). */
56 #define TARGET_68020 (target_flags & MASK_68020)
58 /* Compile 68881 insns for floating point (not library calls). */
60 #define TARGET_68881 (target_flags & MASK_68881)
62 /* Compile using 68020 bitfield insns. */
63 #define MASK_BITFIELD 4
64 #define TARGET_BITFIELD (target_flags & MASK_BITFIELD)
66 /* Compile using rtd insn calling sequence.
67 This will not work unless you use prototypes at least
68 for all functions that can take varying numbers of args. */
70 #define TARGET_RTD (target_flags & MASK_RTD)
72 /* Compile passing first two args in regs 0 and 1.
73 This exists only to test compiler features that will
74 be needed for RISC chips. It is not usable
75 and is not intended to be usable on this cpu. */
76 #define MASK_REGPARM 16
77 #define TARGET_REGPARM (target_flags & MASK_REGPARM)
79 /* Compile with 16-bit `int'. */
81 #define TARGET_SHORT (target_flags & MASK_SHORT)
83 /* Compile with special insns for Sun FPA. */
85 #define TARGET_FPA (target_flags & MASK_FPA)
87 /* Compile (actually, link) for Sun SKY board. */
89 #define TARGET_SKY (target_flags & MASK_SKY)
91 /* Optimize for 68040, but still allow execution on 68020
92 (-m68020-40 or -m68040).
93 The 68040 will execute all 68030 and 68881/2 instructions, but some
94 of them must be emulated in software by the OS. When TARGET_68040 is
95 turned on, these instructions won't be used. This code will still
96 run on a 68030 and 68881/2. */
97 #define MASK_68040 256
98 #define TARGET_68040 (target_flags & MASK_68040)
100 /* Use the 68040-only fp instructions (-m68040 or -m68060). */
101 #define MASK_68040_ONLY 512
102 #define TARGET_68040_ONLY (target_flags & MASK_68040_ONLY)
104 /* Optimize for 68060, but still allow execution on 68020
105 (-m68020-60 or -m68060).
106 The 68060 will execute all 68030 and 68881/2 instructions, but some
107 of them must be emulated in software by the OS. When TARGET_68060 is
108 turned on, these instructions won't be used. This code will still
109 run on a 68030 and 68881/2. */
110 #define MASK_68060 1024
111 #define TARGET_68060 (target_flags & MASK_68060)
113 /* Compile for mcf5200 */
114 #define MASK_5200 2048
115 #define TARGET_5200 (target_flags & MASK_5200)
117 /* Align ints to a word boundary. This breaks compatibility with the
118 published ABI's for structures containing ints, but produces faster
119 code on cpus with 32 bit busses (020, 030, 040, 060, CPU32+, coldfire).
120 It's required for coldfire cpus without a misalignment module. */
121 #define MASK_ALIGN_INT 4096
122 #define TARGET_ALIGN_INT (target_flags & MASK_ALIGN_INT)
124 /* Compile for a CPU32 */
125 /* A 68020 without bitfields is a good heuristic for a CPU32 */
126 #define TARGET_CPU32 (TARGET_68020 && !TARGET_BITFIELD)
128 /* Use PC-relative addressing modes (without using a global offset table).
129 The m68000 supports 16-bit PC-relative addressing.
130 The m68020 supports 32-bit PC-relative addressing
131 (using outer displacements).
133 Under this model, all SYMBOL_REFs (and CONSTs) and LABEL_REFs are
134 treated as all containing an implicit PC-relative component, and hence
135 cannot be used directly as addresses for memory writes. See the comments
136 in m68k.c for more information. */
137 #define MASK_PCREL 8192
138 #define TARGET_PCREL (target_flags & MASK_PCREL)
140 /* Relax strict alignment. */
141 #define MASK_NO_STRICT_ALIGNMENT 16384
142 #define TARGET_STRICT_ALIGNMENT (~target_flags & MASK_NO_STRICT_ALIGNMENT)
144 /* Macro to define tables used to set the flags.
145 This is a list in braces of pairs in braces,
146 each pair being { "NAME", VALUE }
147 where VALUE is the bits to set or minus the bits to clear.
148 An empty string NAME is used to identify the default VALUE. */
150 #define TARGET_SWITCHES \
151 { { "68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \
152 N_("Generate code for a 68020") }, \
153 { "c68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \
154 N_("Generate code for a 68020") }, \
155 { "68020", (MASK_68020|MASK_BITFIELD), "" }, \
156 { "c68020", (MASK_68020|MASK_BITFIELD), "" }, \
157 { "68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
158 |MASK_68020|MASK_BITFIELD|MASK_68881), \
159 N_("Generate code for a 68000") }, \
160 { "c68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
161 |MASK_68020|MASK_BITFIELD|MASK_68881), \
162 N_("Generate code for a 68000") }, \
163 { "bitfield", MASK_BITFIELD, \
164 N_("Use the bit-field instructions") }, \
165 { "nobitfield", - MASK_BITFIELD, \
166 N_("Do not use the bit-field instructions") }, \
168 N_("Use different calling convention using 'rtd'") }, \
169 { "nortd", - MASK_RTD, \
170 N_("Use normal calling convention") }, \
171 { "short", MASK_SHORT, \
172 N_("Consider type `int' to be 16 bits wide") }, \
173 { "noshort", - MASK_SHORT, \
174 N_("Consider type `int' to be 32 bits wide") }, \
175 { "fpa", -(MASK_SKY|MASK_68040_ONLY|MASK_68881), \
176 N_("Generate code for a Sun FPA") }, \
177 { "fpa", MASK_FPA, "" }, \
178 { "nofpa", - MASK_FPA, \
179 N_("Do not generate code for a Sun FPA") }, \
180 { "sky", -(MASK_FPA|MASK_68040_ONLY|MASK_68881), \
181 N_("Generate code for a Sun Sky board") }, \
183 N_("Generate code for a Sun Sky board") }, \
184 { "nosky", - MASK_SKY, \
185 N_("Do not use Sky linkage convention") }, \
186 { "68881", - (MASK_FPA|MASK_SKY), \
187 N_("Generate code for a 68881") }, \
188 { "68881", MASK_68881, "" }, \
189 { "soft-float", - (MASK_FPA|MASK_SKY|MASK_68040_ONLY|MASK_68881), \
190 N_("Generate code with library calls for floating point") }, \
191 { "68020-40", -(MASK_5200|MASK_68060|MASK_68040_ONLY), \
192 N_("Generate code for a 68040, without any new instructions") }, \
193 { "68020-40", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040), ""},\
194 { "68020-60", -(MASK_5200|MASK_68040_ONLY), \
195 N_("Generate code for a 68060, without any new instructions") }, \
196 { "68020-60", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040 \
197 |MASK_68060), "" }, \
198 { "68030", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \
199 N_("Generate code for a 68030") }, \
200 { "68030", (MASK_68020|MASK_BITFIELD), "" }, \
201 { "68040", - (MASK_5200|MASK_68060), \
202 N_("Generate code for a 68040") }, \
203 { "68040", (MASK_68020|MASK_68881|MASK_BITFIELD \
204 |MASK_68040_ONLY|MASK_68040), "" }, \
205 { "68060", - (MASK_5200|MASK_68040), \
206 N_("Generate code for a 68060") }, \
207 { "68060", (MASK_68020|MASK_68881|MASK_BITFIELD \
208 |MASK_68040_ONLY|MASK_68060), "" }, \
209 { "5200", - (MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
210 |MASK_BITFIELD|MASK_68881), \
211 N_("Generate code for a 520X") }, \
212 { "5200", (MASK_5200), "" }, \
214 N_("Generate code for a 68851") }, \
216 N_("Do no generate code for a 68851") }, \
217 { "68302", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
218 |MASK_68020|MASK_BITFIELD|MASK_68881), \
219 N_("Generate code for a 68302") }, \
220 { "68332", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
221 |MASK_BITFIELD|MASK_68881), \
222 N_("Generate code for a 68332") }, \
223 { "68332", MASK_68020, "" }, \
224 { "cpu32", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
225 |MASK_BITFIELD|MASK_68881), \
226 N_("Generate code for a cpu32") }, \
227 { "cpu32", MASK_68020, "" }, \
228 { "align-int", MASK_ALIGN_INT, \
229 N_("Align variables on a 32-bit boundary") }, \
230 { "no-align-int", -MASK_ALIGN_INT, \
231 N_("Align variables on a 16-bit boundary") }, \
232 { "pcrel", MASK_PCREL, \
233 N_("Generate pc-relative code") }, \
234 { "strict-align", -MASK_NO_STRICT_ALIGNMENT, \
235 N_("Do not use unaligned memory references") }, \
236 { "no-strict-align", MASK_NO_STRICT_ALIGNMENT, \
237 N_("Use unaligned memory references") }, \
239 { "", TARGET_DEFAULT, "" }}
240 /* TARGET_DEFAULT is defined in sun*.h and isi.h, etc. */
242 /* This macro is similar to `TARGET_SWITCHES' but defines names of
243 command options that have values. Its definition is an
244 initializer with a subgrouping for each command option.
246 Each subgrouping contains a string constant, that defines the
247 fixed part of the option name, and the address of a variable. The
248 variable, type `char *', is set to the variable part of the given
249 option if the fixed part matches. The actual option name is made
250 by appending `-m' to the specified name. */
251 #define TARGET_OPTIONS \
252 { { "align-loops=", &m68k_align_loops_string, \
253 N_("Loop code aligned to this power of 2") }, \
254 { "align-jumps=", &m68k_align_jumps_string, \
255 N_("Jump targets are aligned to this power of 2") }, \
256 { "align-functions=", &m68k_align_funcs_string, \
257 N_("Function starts are aligned to this power of 2") }, \
261 /* Sometimes certain combinations of command options do not make
262 sense on a particular target machine. You can define a macro
263 `OVERRIDE_OPTIONS' to take account of this. This macro, if
264 defined, is executed once just after all the command options have
267 Don't use this macro to turn on various extra optimizations for
268 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
270 #define OVERRIDE_OPTIONS \
272 override_options(); \
273 if (! TARGET_68020 && flag_pic == 2) \
274 error("-fPIC is not currently supported on the 68000 or 68010\n"); \
275 if (TARGET_PCREL && flag_pic == 0) \
277 SUBTARGET_OVERRIDE_OPTIONS; \
280 /* These are meant to be redefined in the host dependent files */
281 #define SUBTARGET_SWITCHES
282 #define SUBTARGET_OPTIONS
283 #define SUBTARGET_OVERRIDE_OPTIONS
285 /* target machine storage layout */
287 /* Define for XFmode extended real floating point support.
288 This will automatically cause REAL_ARITHMETIC to be defined. */
289 #define LONG_DOUBLE_TYPE_SIZE 96
291 /* Define if you don't want extended real, but do want to use the
292 software floating point emulator for REAL_ARITHMETIC and
293 decimal <-> binary conversion. */
294 /* #define REAL_ARITHMETIC */
296 /* Define this if most significant bit is lowest numbered
297 in instructions that operate on numbered bit-fields.
298 This is true for 68020 insns such as bfins and bfexts.
299 We make it true always by avoiding using the single-bit insns
300 except in special cases with constant bit numbers. */
301 #define BITS_BIG_ENDIAN 1
303 /* Define this if most significant byte of a word is the lowest numbered. */
304 /* That is true on the 68000. */
305 #define BYTES_BIG_ENDIAN 1
307 /* Define this if most significant word of a multiword number is the lowest
309 /* For 68000 we can decide arbitrarily
310 since there are no machine instructions for them.
311 So let's be consistent. */
312 #define WORDS_BIG_ENDIAN 1
314 /* number of bits in an addressable storage unit */
315 #define BITS_PER_UNIT 8
317 /* Width in bits of a "word", which is the contents of a machine register.
318 Note that this is not necessarily the width of data type `int';
319 if using 16-bit ints on a 68000, this would still be 32.
320 But on a machine with 16-bit registers, this would be 16. */
321 #define BITS_PER_WORD 32
323 /* Width of a word, in units (bytes). */
324 #define UNITS_PER_WORD 4
326 /* Width in bits of a pointer.
327 See also the macro `Pmode' defined below. */
328 #define POINTER_SIZE 32
330 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
331 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
333 /* Boundary (in *bits*) on which stack pointer should be aligned. */
334 #define STACK_BOUNDARY 16
336 /* Allocation boundary (in *bits*) for the code of a function. */
337 #define FUNCTION_BOUNDARY (1 << (m68k_align_funcs + 3))
339 /* Alignment of field after `int : 0' in a structure. */
340 #define EMPTY_FIELD_BOUNDARY 16
342 /* No data type wants to be aligned rounder than this.
343 Most published ABIs say that ints should be aligned on 16 bit
344 boundaries, but cpus with 32 bit busses get better performance
345 aligned on 32 bit boundaries. Coldfires without a misalignment
346 module require 32 bit alignment. */
347 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
349 /* Set this nonzero if move instructions will actually fail to work
350 when given unaligned data. */
351 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT)
353 /* Maximum power of 2 that code can be aligned to. */
354 #define MAX_CODE_ALIGN 2 /* 4 byte alignment */
356 /* Align loop starts for optimal branching. */
357 #define LOOP_ALIGN(LABEL) (m68k_align_loops)
359 /* This is how to align an instruction for optimal branching. */
360 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) (m68k_align_jumps)
362 #define SELECT_RTX_SECTION(MODE, X, ALIGN) \
365 readonly_data_section(); \
366 else if (LEGITIMATE_PIC_OPERAND_P (X)) \
367 readonly_data_section(); \
372 /* Define number of bits in most basic integer type.
373 (If undefined, default is BITS_PER_WORD). */
375 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
377 /* Define these to avoid dependence on meaning of `int'. */
379 #define WCHAR_TYPE "long int"
380 #define WCHAR_TYPE_SIZE 32
382 /* Standard register usage. */
384 /* Number of actual hardware registers.
385 The hardware registers are assigned numbers for the compiler
386 from 0 to just below FIRST_PSEUDO_REGISTER.
387 All registers that the compiler knows about must be given numbers,
388 even those that are not normally considered general registers.
389 For the 68000, we give the data registers numbers 0-7,
390 the address registers numbers 010-017,
391 and the 68881 floating point registers numbers 020-027. */
392 #ifndef SUPPORT_SUN_FPA
393 #define FIRST_PSEUDO_REGISTER 24
395 #define FIRST_PSEUDO_REGISTER 56
398 /* This defines the register which is used to hold the offset table for PIC. */
399 #define PIC_OFFSET_TABLE_REGNUM 13
401 #ifndef SUPPORT_SUN_FPA
403 /* 1 for registers that have pervasive standard uses
404 and are not available for the register allocator.
405 On the 68000, only the stack pointer is such. */
407 #define FIXED_REGISTERS \
408 {/* Data registers. */ \
409 0, 0, 0, 0, 0, 0, 0, 0, \
411 /* Address registers. */ \
412 0, 0, 0, 0, 0, 0, 0, 1, \
414 /* Floating point registers \
416 0, 0, 0, 0, 0, 0, 0, 0 }
418 /* 1 for registers not available across function calls.
419 These must include the FIXED_REGISTERS and also any
420 registers that can be used without being saved.
421 The latter must include the registers where values are returned
422 and the register where structure-value addresses are passed.
423 Aside from that, you can include as many other registers as you like. */
424 #define CALL_USED_REGISTERS \
425 {1, 1, 0, 0, 0, 0, 0, 0, \
426 1, 1, 0, 0, 0, 0, 0, 1, \
427 1, 1, 0, 0, 0, 0, 0, 0 }
429 #else /* SUPPORT_SUN_FPA */
431 /* 1 for registers that have pervasive standard uses
432 and are not available for the register allocator.
433 On the 68000, only the stack pointer is such. */
435 /* fpa0 is also reserved so that it can be used to move data back and
436 forth between high fpa regs and everything else. */
438 #define FIXED_REGISTERS \
439 {/* Data registers. */ \
440 0, 0, 0, 0, 0, 0, 0, 0, \
442 /* Address registers. */ \
443 0, 0, 0, 0, 0, 0, 0, 1, \
445 /* Floating point registers \
447 0, 0, 0, 0, 0, 0, 0, 0, \
449 /* Sun3 FPA registers. */ \
450 1, 0, 0, 0, 0, 0, 0, 0, \
451 0, 0, 0, 0, 0, 0, 0, 0, \
452 0, 0, 0, 0, 0, 0, 0, 0, \
453 0, 0, 0, 0, 0, 0, 0, 0 }
455 /* 1 for registers not available across function calls.
456 These must include the FIXED_REGISTERS and also any
457 registers that can be used without being saved.
458 The latter must include the registers where values are returned
459 and the register where structure-value addresses are passed.
460 Aside from that, you can include as many other registers as you like. */
461 #define CALL_USED_REGISTERS \
462 {1, 1, 0, 0, 0, 0, 0, 0, \
463 1, 1, 0, 0, 0, 0, 0, 1, \
464 1, 1, 0, 0, 0, 0, 0, 0, \
465 /* FPA registers. */ \
466 1, 1, 1, 1, 0, 0, 0, 0, \
467 0, 0, 0, 0, 0, 0, 0, 0, \
468 0, 0, 0, 0, 0, 0, 0, 0, \
469 0, 0, 0, 0, 0, 0, 0, 0 }
471 #endif /* defined SUPPORT_SUN_FPA */
474 /* Make sure everything's fine if we *don't* have a given processor.
475 This assumes that putting a register in fixed_regs will keep the
476 compiler's mitts completely off it. We don't bother to zero it out
477 of register classes. */
479 #ifdef SUPPORT_SUN_FPA
481 #define CONDITIONAL_REGISTER_USAGE \
487 COPY_HARD_REG_SET (x, reg_class_contents[(int)FPA_REGS]); \
488 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
489 if (TEST_HARD_REG_BIT (x, i)) \
490 fixed_regs[i] = call_used_regs[i] = 1; \
492 if (! TARGET_68881) \
494 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
495 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
496 if (TEST_HARD_REG_BIT (x, i)) \
497 fixed_regs[i] = call_used_regs[i] = 1; \
500 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
501 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;\
504 #define CONDITIONAL_REGISTER_USAGE \
508 if (! TARGET_68881) \
510 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
511 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
512 if (TEST_HARD_REG_BIT (x, i)) \
513 fixed_regs[i] = call_used_regs[i] = 1; \
516 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
517 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;\
520 #endif /* defined SUPPORT_SUN_FPA */
522 /* Return number of consecutive hard regs needed starting at reg REGNO
523 to hold something of mode MODE.
524 This is ordinarily the length in words of a value of mode MODE
525 but can be less for certain modes in special long registers.
527 On the 68000, ordinary registers hold 32 bits worth;
528 for the 68881 registers, a single register is always enough for
529 anything that can be stored in them at all. */
530 #define HARD_REGNO_NREGS(REGNO, MODE) \
531 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
532 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
534 #ifndef SUPPORT_SUN_FPA
536 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
537 On the 68000, the cpu registers can hold any mode but the 68881 registers
538 can hold only SFmode or DFmode. */
540 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
542 && !((REGNO) < 8 && (REGNO) + GET_MODE_SIZE (MODE) / 4 > 8)) \
543 || ((REGNO) >= 16 && (REGNO) < 24 \
544 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
545 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
546 && GET_MODE_UNIT_SIZE (MODE) <= 12))
548 #else /* defined SUPPORT_SUN_FPA */
550 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
551 On the 68000, the cpu registers can hold any mode but the 68881 registers
552 can hold only SFmode or DFmode. However, the Sun FPA register can
553 (apparently) hold whatever you feel like putting in them.
554 If using the fpa, don't put a double in d7/a0. */
556 /* ??? This is confused. The check to prohibit d7/a0 overlaps should always
557 be enabled regardless of whether TARGET_FPA is specified. It isn't clear
558 what the other d/a register checks are for. Every check using REGNO
559 actually needs to use a range, e.g. 24>=X<56 not <56. There is probably
560 no one using this code anymore.
561 This code used to be used to suppress register usage for the 68881 by
562 saying that the 68881 registers couldn't hold values of any mode if there
563 was no 68881. This was wrong, because reload (etc.) will still try
564 to save and restore call-saved registers during, for instance, non-local
566 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
569 && GET_MODE_CLASS ((MODE)) != MODE_INT \
570 && GET_MODE_UNIT_SIZE ((MODE)) > 4 \
571 && (REGNO) < 8 && (REGNO) + GET_MODE_SIZE ((MODE)) / 4 > 8 \
572 && (REGNO) % (GET_MODE_UNIT_SIZE ((MODE)) / 4) != 0)) \
573 || ((REGNO) >= 16 && (REGNO) < 24 \
574 ? ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
575 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
576 && GET_MODE_UNIT_SIZE (MODE) <= 12) \
577 : ((REGNO) < 56 ? TARGET_FPA && GET_MODE_UNIT_SIZE (MODE) <= 8 : 0)))
579 #endif /* defined SUPPORT_SUN_FPA */
581 /* Value is 1 if it is a good idea to tie two pseudo registers
582 when one has mode MODE1 and one has mode MODE2.
583 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
584 for any hard reg, then this must be 0 for correct output. */
585 #define MODES_TIEABLE_P(MODE1, MODE2) \
587 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
588 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
589 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
590 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
592 /* Specify the registers used for certain standard purposes.
593 The values of these macros are register numbers. */
595 /* m68000 pc isn't overloaded on a register. */
596 /* #define PC_REGNUM */
598 /* Register to use for pushing function arguments. */
599 #define STACK_POINTER_REGNUM 15
601 /* Base register for access to local variables of the function. */
602 #define FRAME_POINTER_REGNUM 14
604 /* Value should be nonzero if functions must have frame pointers.
605 Zero means the frame pointer need not be set up (and parms
606 may be accessed via the stack pointer) in functions that seem suitable.
607 This is computed in `reload', in reload1.c. */
608 #define FRAME_POINTER_REQUIRED 0
610 /* Base register for access to arguments of the function. */
611 #define ARG_POINTER_REGNUM 14
613 /* Register in which static-chain is passed to a function. */
614 #define STATIC_CHAIN_REGNUM 8
616 /* Register in which address to store a structure value
617 is passed to a function. */
618 #define STRUCT_VALUE_REGNUM 9
620 /* Define the classes of registers for register constraints in the
621 machine description. Also define ranges of constants.
623 One of the classes must always be named ALL_REGS and include all hard regs.
624 If there is more than one class, another class must be named NO_REGS
625 and contain no registers.
627 The name GENERAL_REGS must be the name of a class (or an alias for
628 another name such as ALL_REGS). This is the class of registers
629 that is allowed by "g" or "r" in a register constraint.
630 Also, registers outside this class are allocated only when
631 instructions express preferences for them.
633 The classes must be numbered in nondecreasing order; that is,
634 a larger-numbered class must never be contained completely
635 in a smaller-numbered class.
637 For any two classes, it is very desirable that there be another
638 class that represents their union. */
640 /* The 68000 has three kinds of registers, so eight classes would be
641 a complete set. One of them is not needed. */
643 #ifndef SUPPORT_SUN_FPA
648 GENERAL_REGS, DATA_OR_FP_REGS,
649 ADDR_OR_FP_REGS, ALL_REGS,
652 #define N_REG_CLASSES (int) LIM_REG_CLASSES
654 /* Give names of register classes as strings for dump file. */
656 #define REG_CLASS_NAMES \
657 { "NO_REGS", "DATA_REGS", \
658 "ADDR_REGS", "FP_REGS", \
659 "GENERAL_REGS", "DATA_OR_FP_REGS", \
660 "ADDR_OR_FP_REGS", "ALL_REGS" }
662 /* Define which registers fit in which classes.
663 This is an initializer for a vector of HARD_REG_SET
664 of length N_REG_CLASSES. */
666 #define REG_CLASS_CONTENTS \
668 {0x00000000}, /* NO_REGS */ \
669 {0x000000ff}, /* DATA_REGS */ \
670 {0x0000ff00}, /* ADDR_REGS */ \
671 {0x00ff0000}, /* FP_REGS */ \
672 {0x0000ffff}, /* GENERAL_REGS */ \
673 {0x00ff00ff}, /* DATA_OR_FP_REGS */ \
674 {0x00ffff00}, /* ADDR_OR_FP_REGS */ \
675 {0x00ffffff}, /* ALL_REGS */ \
678 /* The same information, inverted:
679 Return the class number of the smallest class containing
680 reg number REGNO. This could be a conditional expression
681 or could index an array. */
683 #define REGNO_REG_CLASS(REGNO) (((REGNO)>>3)+1)
685 #else /* defined SUPPORT_SUN_FPA */
688 * Notes on final choices:
690 * 1) Didn't feel any need to union-ize LOW_FPA_REGS with anything
692 * 2) Removed all unions that involve address registers with
693 * floating point registers (left in unions of address and data with
695 * 3) Defined GENERAL_REGS as ADDR_OR_DATA_REGS.
696 * 4) Defined ALL_REGS as FPA_OR_FP_OR_GENERAL_REGS.
697 * 4) Left in everything else.
699 enum reg_class { NO_REGS, LO_FPA_REGS, FPA_REGS, FP_REGS,
700 FP_OR_FPA_REGS, DATA_REGS, DATA_OR_FPA_REGS, DATA_OR_FP_REGS,
701 DATA_OR_FP_OR_FPA_REGS, ADDR_REGS, GENERAL_REGS,
702 GENERAL_OR_FPA_REGS, GENERAL_OR_FP_REGS, ALL_REGS,
705 #define N_REG_CLASSES (int) LIM_REG_CLASSES
707 /* Give names of register classes as strings for dump file. */
709 #define REG_CLASS_NAMES \
710 { "NO_REGS", "LO_FPA_REGS", "FPA_REGS", "FP_REGS", \
711 "FP_OR_FPA_REGS", "DATA_REGS", "DATA_OR_FPA_REGS", "DATA_OR_FP_REGS", \
712 "DATA_OR_FP_OR_FPA_REGS", "ADDR_REGS", "GENERAL_REGS", \
713 "GENERAL_OR_FPA_REGS", "GENERAL_OR_FP_REGS", "ALL_REGS" }
715 /* Define which registers fit in which classes.
716 This is an initializer for a vector of HARD_REG_SET
717 of length N_REG_CLASSES. */
719 #define REG_CLASS_CONTENTS \
721 {0, 0}, /* NO_REGS */ \
722 {0xff000000, 0x000000ff}, /* LO_FPA_REGS */ \
723 {0xff000000, 0x00ffffff}, /* FPA_REGS */ \
724 {0x00ff0000, 0x00000000}, /* FP_REGS */ \
725 {0xffff0000, 0x00ffffff}, /* FP_OR_FPA_REGS */ \
726 {0x000000ff, 0x00000000}, /* DATA_REGS */ \
727 {0xff0000ff, 0x00ffffff}, /* DATA_OR_FPA_REGS */ \
728 {0x00ff00ff, 0x00000000}, /* DATA_OR_FP_REGS */ \
729 {0xffff00ff, 0x00ffffff}, /* DATA_OR_FP_OR_FPA_REGS */\
730 {0x0000ff00, 0x00000000}, /* ADDR_REGS */ \
731 {0x0000ffff, 0x00000000}, /* GENERAL_REGS */ \
732 {0xff00ffff, 0x00ffffff}, /* GENERAL_OR_FPA_REGS */\
733 {0x00ffffff, 0x00000000}, /* GENERAL_OR_FP_REGS */\
734 {0xffffffff, 0x00ffffff}, /* ALL_REGS */ \
737 /* The same information, inverted:
738 Return the class number of the smallest class containing
739 reg number REGNO. This could be a conditional expression
740 or could index an array. */
742 extern enum reg_class regno_reg_class[];
743 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)>>3])
745 #endif /* SUPPORT_SUN_FPA */
747 /* The class value for index registers, and the one for base regs. */
749 #define INDEX_REG_CLASS GENERAL_REGS
750 #define BASE_REG_CLASS ADDR_REGS
752 /* Get reg_class from a letter such as appears in the machine description.
753 We do a trick here to modify the effective constraints on the
754 machine description; we zorch the constraint letters that aren't
755 appropriate for a specific target. This allows us to guarantee
756 that a specific kind of register will not be used for a given target
757 without fiddling with the register classes above. */
759 #ifndef SUPPORT_SUN_FPA
761 #define REG_CLASS_FROM_LETTER(C) \
762 ((C) == 'a' ? ADDR_REGS : \
763 ((C) == 'd' ? DATA_REGS : \
764 ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \
768 #else /* defined SUPPORT_SUN_FPA */
770 #define REG_CLASS_FROM_LETTER(C) \
771 ((C) == 'a' ? ADDR_REGS : \
772 ((C) == 'd' ? DATA_REGS : \
773 ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \
775 ((C) == 'x' ? (TARGET_FPA ? FPA_REGS : \
777 ((C) == 'y' ? (TARGET_FPA ? LO_FPA_REGS : \
781 #endif /* defined SUPPORT_SUN_FPA */
783 /* The letters I, J, K, L and M in a register constraint string
784 can be used to stand for particular ranges of immediate operands.
785 This macro defines what the ranges are.
786 C is the letter, and VALUE is a constant value.
787 Return 1 if VALUE is in the range specified by C.
789 For the 68000, `I' is used for the range 1 to 8
790 allowed as immediate shift counts and in addq.
791 `J' is used for the range of signed numbers that fit in 16 bits.
792 `K' is for numbers that moveq can't handle.
793 `L' is for range -8 to -1, range of values that can be added with subq.
794 `M' is for numbers that moveq+notb can't handle.
795 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate.
796 'O' is for 16 (for rotate using swap).
797 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */
799 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
800 ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \
801 (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
802 (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
803 (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \
804 (C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \
805 (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \
806 (C) == 'O' ? (VALUE) == 16 : \
807 (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0)
810 * A small bit of explanation:
811 * "G" defines all of the floating constants that are *NOT* 68881
812 * constants. this is so 68881 constants get reloaded and the
813 * fpmovecr is used. "H" defines *only* the class of constants that
814 * the fpa can use, because these can be gotten at in any fpa
815 * instruction and there is no need to force reloads.
817 #ifndef SUPPORT_SUN_FPA
818 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
819 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 )
820 #else /* defined SUPPORT_SUN_FPA */
821 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
822 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : \
823 (C) == 'H' ? (TARGET_FPA && standard_sun_fpa_constant_p (VALUE)) : 0)
824 #endif /* defined SUPPORT_SUN_FPA */
826 /* A C expression that defines the optional machine-dependent constraint
827 letters that can be used to segregate specific types of operands,
828 usually memory references, for the target machine. It should return 1 if
829 VALUE corresponds to the operand type represented by the constraint letter
830 C. If C is not defined as an extra constraint, the value returned should
831 be 0 regardless of VALUE. */
833 /* Letters in the range `Q' through `U' may be defined in a
834 machine-dependent fashion to stand for arbitrary operand types.
835 The machine description macro `EXTRA_CONSTRAINT' is passed the
836 operand as its first argument and the constraint letter as its
839 `Q' means address register indirect addressing mode.
840 `S' is for operands that satisfy 'm' when -mpcrel is in effect.
841 `T' is for operands that satisfy 's' when -mpcrel is not in effect. */
843 #define EXTRA_CONSTRAINT(OP,CODE) \
846 && GET_CODE (OP) == MEM \
847 && (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
848 || GET_CODE (XEXP (OP, 0)) == LABEL_REF \
849 || GET_CODE (XEXP (OP, 0)) == CONST)) \
853 && (GET_CODE (OP) == SYMBOL_REF \
854 || GET_CODE (OP) == LABEL_REF \
855 || GET_CODE (OP) == CONST)) \
858 ? (GET_CODE (OP) == MEM \
859 && GET_CODE (XEXP (OP, 0)) == REG) \
863 /* Given an rtx X being reloaded into a reg required to be
864 in class CLASS, return the class of reg to actually use.
865 In general this is just CLASS; but on some machines
866 in some cases it is preferable to use a more restrictive class.
867 On the 68000 series, use a data reg if possible when the
868 value is a constant in the range where moveq could be used
869 and we ensure that QImodes are reloaded into data regs. */
871 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
872 ((GET_CODE (X) == CONST_INT \
873 && (unsigned) (INTVAL (X) + 0x80) < 0x100 \
874 && (CLASS) != ADDR_REGS) \
876 : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \
878 : (GET_CODE (X) == CONST_DOUBLE \
879 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
880 ? (TARGET_68881 && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \
881 ? FP_REGS : NO_REGS) \
883 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
884 || GET_CODE (X) == LABEL_REF)) \
888 /* Force QImode output reloads from subregs to be allocated to data regs,
889 since QImode stores from address regs are not supported. We make the
890 assumption that if the class is not ADDR_REGS, then it must be a superset
893 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
894 (((MODE) == QImode && (CLASS) != ADDR_REGS) \
898 /* Return the maximum number of consecutive registers
899 needed to represent mode MODE in a register of class CLASS. */
900 /* On the 68000, this is the size of MODE in words,
901 except in the FP regs, where a single reg is always enough. */
902 #ifndef SUPPORT_SUN_FPA
904 #define CLASS_MAX_NREGS(CLASS, MODE) \
905 ((CLASS) == FP_REGS ? 1 \
906 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
908 /* Moves between fp regs and other regs are two insns. */
909 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
910 (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
911 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
914 #else /* defined SUPPORT_SUN_FPA */
916 #define CLASS_MAX_NREGS(CLASS, MODE) \
917 ((CLASS) == FP_REGS || (CLASS) == FPA_REGS || (CLASS) == LO_FPA_REGS ? 1 \
918 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
920 /* Moves between fp regs and other regs are two insns. */
921 /* Likewise for high fpa regs and other regs. */
922 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
923 ((((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
924 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
925 || ((CLASS1) == FPA_REGS && (CLASS2) != FPA_REGS) \
926 || ((CLASS2) == FPA_REGS && (CLASS1) != FPA_REGS)) \
929 #endif /* define SUPPORT_SUN_FPA */
931 /* Stack layout; function entry, exit and calling. */
933 /* Define this if pushing a word on the stack
934 makes the stack pointer a smaller address. */
935 #define STACK_GROWS_DOWNWARD
937 /* Nonzero if we need to generate stack-probe insns.
938 On most systems they are not needed.
939 When they are needed, define this as the stack offset to probe at. */
942 /* Define this if the nominal address of the stack frame
943 is at the high-address end of the local variables;
944 that is, each additional local variable allocated
945 goes at a more negative offset in the frame. */
946 #define FRAME_GROWS_DOWNWARD
948 /* Offset within stack frame to start allocating local variables at.
949 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
950 first local allocated. Otherwise, it is the offset to the BEGINNING
951 of the first local allocated. */
952 #define STARTING_FRAME_OFFSET 0
954 /* If we generate an insn to push BYTES bytes,
955 this says how many the stack pointer really advances by.
956 On the 68000, sp@- in a byte insn really pushes a word.
957 On the 5200 (coldfire), sp@- in a byte insn pushes just a byte. */
958 #define PUSH_ROUNDING(BYTES) (TARGET_5200 ? BYTES : ((BYTES) + 1) & ~1)
960 /* We want to avoid trying to push bytes. */
961 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
962 (move_by_pieces_ninsns (SIZE, ALIGN) < MOVE_RATIO \
963 && (((SIZE) >=16 && (ALIGN) >= 16) || (TARGET_5200)))
965 /* Offset of first parameter from the argument pointer register value. */
966 #define FIRST_PARM_OFFSET(FNDECL) 8
968 /* Value is the number of byte of arguments automatically
969 popped when returning from a subroutine call.
970 FUNDECL is the declaration node of the function (as a tree),
971 FUNTYPE is the data type of the function (as a tree),
972 or for a library call it is an identifier node for the subroutine name.
973 SIZE is the number of bytes of arguments passed on the stack.
975 On the 68000, the RTS insn cannot pop anything.
976 On the 68010, the RTD insn may be used to pop them if the number
977 of args is fixed, but if the number is variable then the caller
978 must pop them all. RTD can't be used for library calls now
979 because the library is compiled with the Unix compiler.
980 Use of RTD is a selectable option, since it is incompatible with
981 standard Unix calling sequences. If the option is not selected,
982 the caller must always pop the args. */
984 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
985 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \
986 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
987 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
988 == void_type_node))) \
991 /* Define how to find the value returned by a function.
992 VALTYPE is the data type of the value (as a tree).
993 If the precise function being called is known, FUNC is its FUNCTION_DECL;
994 otherwise, FUNC is 0. */
996 /* On the 68000 the return value is in D0 regardless. */
998 #define FUNCTION_VALUE(VALTYPE, FUNC) \
999 gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
1001 /* Define how to find the value returned by a library function
1002 assuming the value has mode MODE. */
1004 /* On the 68000 the return value is in D0 regardless. */
1006 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
1008 /* 1 if N is a possible register number for a function value.
1009 On the 68000, d0 is the only register thus used. */
1011 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
1013 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
1014 more than one register. */
1016 #define NEEDS_UNTYPED_CALL 0
1018 /* Define this if PCC uses the nonreentrant convention for returning
1019 structure and union values. */
1021 #define PCC_STATIC_STRUCT_RETURN
1023 /* 1 if N is a possible register number for function argument passing.
1024 On the 68000, no registers are used in this way. */
1026 #define FUNCTION_ARG_REGNO_P(N) 0
1028 /* Define a data type for recording info about an argument list
1029 during the scan of that argument list. This data type should
1030 hold all necessary information about the function itself
1031 and about the args processed so far, enough to enable macros
1032 such as FUNCTION_ARG to determine where the next arg should go.
1034 On the m68k, this is a single integer, which is a number of bytes
1035 of arguments scanned so far. */
1037 #define CUMULATIVE_ARGS int
1039 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1040 for a call to a function whose data type is FNTYPE.
1041 For a library call, FNTYPE is 0.
1043 On the m68k, the offset starts at 0. */
1045 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1048 /* Update the data in CUM to advance over an argument
1049 of mode MODE and data type TYPE.
1050 (TYPE is null for libcalls where that information may not be available.) */
1052 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1053 ((CUM) += ((MODE) != BLKmode \
1054 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
1055 : (int_size_in_bytes (TYPE) + 3) & ~3))
1057 /* Define where to put the arguments to a function.
1058 Value is zero to push the argument on the stack,
1059 or a hard register in which to store the argument.
1061 MODE is the argument's machine mode.
1062 TYPE is the data type of the argument (as a tree).
1063 This is null for libcalls where that information may
1065 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1066 the preceding args and about the function being called.
1067 NAMED is nonzero if this argument is a named parameter
1068 (otherwise it is an extra parameter matching an ellipsis). */
1070 /* On the 68000 all args are pushed, except if -mregparm is specified
1071 then the first two words of arguments are passed in d0, d1.
1072 *NOTE* -mregparm does not work.
1073 It exists only to test register calling conventions. */
1075 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1076 ((TARGET_REGPARM && (CUM) < 8) ? gen_rtx_REG ((MODE), (CUM) / 4) : 0)
1078 /* For an arg passed partly in registers and partly in memory,
1079 this is the number of registers used.
1080 For args passed entirely in registers or entirely in memory, zero. */
1082 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1083 ((TARGET_REGPARM && (CUM) < 8 \
1084 && 8 < ((CUM) + ((MODE) == BLKmode \
1085 ? int_size_in_bytes (TYPE) \
1086 : GET_MODE_SIZE (MODE)))) \
1087 ? 2 - (CUM) / 4 : 0)
1089 /* Output assembler code to FILE to increment profiler label # LABELNO
1090 for profiling a function entry. */
1092 #define FUNCTION_PROFILER(FILE, LABELNO) \
1093 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO))
1095 /* Output assembler code to FILE to initialize this source file's
1096 basic block profiling info, if that has not already been done. */
1098 #define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL) \
1101 switch (profile_block_flag) \
1104 asm_fprintf (FILE, "\tpea %d\n\tpea %LLPBX0\n\tjsr %U__bb_init_trace_func\n\taddql %I8,%Rsp\n", \
1105 (BLOCK_OR_LABEL)); \
1109 asm_fprintf (FILE, "\ttstl %LLPBX0\n\tbne %LLPI%d\n\tpea %LLPBX0\n\tjsr %U__bb_init_func\n\taddql %I4,%Rsp\n%LLPI%d:\n", \
1110 (BLOCK_OR_LABEL), (BLOCK_OR_LABEL)); \
1116 /* Output assembler code to FILE to increment the counter for
1117 the BLOCKNO'th basic block in this source file. */
1119 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1122 switch (profile_block_flag) \
1125 asm_fprintf (FILE, "\tmovel %Ra1,%Rsp@-\n\tlea ___bb,%Ra1\n\tmovel %I%d,%Ra1@(0)\n\tmovel %I%LLPBX0,%Ra1@(4)\n\tmovel %Rsp@+,%Ra1\n\tjsr %U__bb_trace_func\n", \
1130 asm_fprintf (FILE, "\taddql %I1,%LLPBX2+%d\n", 4 * BLOCKNO); \
1136 /* Output assembler code to FILE to indicate return from
1137 a function during basic block profiling. */
1139 #define FUNCTION_BLOCK_PROFILER_EXIT(FILE) \
1140 asm_fprintf (FILE, "\tjsr %U__bb_trace_ret\n");
1142 /* Save all registers which may be clobbered by a function call.
1143 MACHINE_STATE_SAVE and MACHINE_STATE_RESTORE are target-code macros,
1144 used in libgcc2.c. They may not refer to TARGET_* macros !!! */
1145 #if defined (__mc68010__) || defined(mc68010) \
1146 || defined(__mc68020__) || defined(mc68020) \
1147 || defined(__mc68030__) || defined(mc68030) \
1148 || defined(__mc68040__) || defined(mc68040) \
1149 || defined(__mcpu32__) || defined(mcpu32)
1150 #define MACHINE_STATE_m68010_up
1154 #if defined(__mcf5200__)
1155 #define MACHINE_STATE_SAVE(id) \
1157 asm ("sub.l 20,%sp"); \
1158 asm ("movm.l &0x0303,4(%sp)"); \
1159 asm ("move.w %ccr,%d0"); \
1160 asm ("movm.l &0x0001,(%sp)"); \
1162 #else /* !__mcf5200__ */
1163 #if defined(MACHINE_STATE_m68010_up)
1165 /* HPUX assembler does not accept %ccr. */
1166 #define MACHINE_STATE_SAVE(id) \
1168 asm ("move.w %cc,-(%sp)"); \
1169 asm ("movm.l &0xc0c0,-(%sp)"); \
1171 #else /* ! __HPUX_ASM__ */
1172 #define MACHINE_STATE_SAVE(id) \
1174 asm ("move.w %ccr,-(%sp)"); \
1175 asm ("movm.l &0xc0c0,-(%sp)"); \
1177 #endif /* __HPUX_ASM__ */
1178 #else /* !MACHINE_STATE_m68010_up */
1179 #define MACHINE_STATE_SAVE(id) \
1181 asm ("move.w %sr,-(%sp)"); \
1182 asm ("movm.l &0xc0c0,-(%sp)"); \
1184 #endif /* MACHINE_STATE_m68010_up */
1185 #endif /* __mcf5200__ */
1186 #else /* !MOTOROLA */
1187 #if defined(__mcf5200__)
1188 #define MACHINE_STATE_SAVE(id) \
1190 asm ("subl %#20,%/sp" : ); \
1191 asm ("movml %/d0/%/d1/%/a0/%/a1,%/sp@(4)" : ); \
1192 asm ("movew %/cc,%/d0" : ); \
1193 asm ("movml %/d0,%/sp@" : ); \
1195 #else /* !__mcf5200__ */
1196 #if defined(MACHINE_STATE_m68010_up)
1197 #define MACHINE_STATE_SAVE(id) \
1199 asm ("movew %/cc,%/sp@-" : ); \
1200 asm ("moveml %/d0/%/d1/%/a0/%/a1,%/sp@-" : ); \
1202 #else /* !MACHINE_STATE_m68010_up */
1203 #define MACHINE_STATE_SAVE(id) \
1205 asm ("movew %/sr,%/sp@-" : ); \
1206 asm ("moveml %/d0/%/d1/%/a0/%/a1,%/sp@-" : ); \
1208 #endif /* MACHINE_STATE_m68010_up */
1209 #endif /* __mcf5200__ */
1210 #endif /* MOTOROLA */
1212 /* Restore all registers saved by MACHINE_STATE_SAVE. */
1215 #if defined(__mcf5200__)
1216 #define MACHINE_STATE_RESTORE(id) \
1218 asm ("movm.l (%sp),&0x0001"); \
1219 asm ("move.w %d0,%ccr"); \
1220 asm ("movm.l 4(%sp),&0x0303"); \
1221 asm ("add.l 20,%sp"); \
1223 #else /* !__mcf5200__ */
1225 /* HPUX assembler does not accept %ccr. */
1226 #define MACHINE_STATE_RESTORE(id) \
1228 asm ("movm.l (%sp)+,&0x0303"); \
1229 asm ("move.w (%sp)+,%cc"); \
1231 #else /* ! __HPUX_ASM__ */
1232 #define MACHINE_STATE_RESTORE(id) \
1234 asm ("movm.l (%sp)+,&0x0303"); \
1235 asm ("move.w (%sp)+,%ccr"); \
1237 #endif /* __HPUX_ASM__ */
1238 #endif /* __mcf5200__ */
1239 #else /* !MOTOROLA */
1240 #if defined(__mcf5200__)
1241 #define MACHINE_STATE_RESTORE(id) \
1243 asm ("movml %/sp@,%/d0" : ); \
1244 asm ("movew %/d0,%/cc" : ); \
1245 asm ("movml %/sp@(4),%/d0/%/d1/%/a0/%/a1" : ); \
1246 asm ("addl %#20,%/sp" : ); \
1248 #else /* !__mcf5200__ */
1249 #define MACHINE_STATE_RESTORE(id) \
1251 asm ("moveml %/sp@+,%/d0/%/d1/%/a0/%/a1" : ); \
1252 asm ("movew %/sp@+,%/cc" : ); \
1254 #endif /* __mcf5200__ */
1255 #endif /* MOTOROLA */
1257 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1258 the stack pointer does not matter. The value is tested only in
1259 functions that have frame pointers.
1260 No definition is equivalent to always zero. */
1262 #define EXIT_IGNORE_STACK 1
1264 /* This is a hook for other tm files to change. */
1265 /* #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) */
1267 /* Determine if the epilogue should be output as RTL.
1268 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1269 #define USE_RETURN_INSN use_return_insn ()
1271 /* Store in the variable DEPTH the initial difference between the
1272 frame pointer reg contents and the stack pointer reg contents,
1273 as of the start of the function body. This depends on the layout
1274 of the fixed parts of the stack frame and on how registers are saved.
1276 On the 68k, if we have a frame, we must add one word to its length
1277 to allow for the place that a6 is stored when we do have a frame pointer.
1278 Otherwise, we would need to compute the offset from the frame pointer
1279 of a local variable as a function of frame_pointer_needed, which
1282 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
1285 for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \
1286 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1288 for (regno = 0; regno < 16; regno++) \
1289 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1291 if (flag_pic && current_function_uses_pic_offset_table) \
1293 (DEPTH) = (offset + ((get_frame_size () + 3) & -4) \
1294 + (get_frame_size () == 0 ? 0 : 4)); \
1297 /* Output assembler code for a block containing the constant parts
1298 of a trampoline, leaving space for the variable parts. */
1300 /* On the 68k, the trampoline looks like this:
1304 WARNING: Targets that may run on 68040+ cpus must arrange for
1305 the instruction cache to be flushed. Previous incarnations of
1306 the m68k trampoline code attempted to get around this by either
1307 using an out-of-line transfer function or pc-relative data, but
1308 the fact remains that the code to jump to the transfer function
1309 or the code to load the pc-relative data needs to be flushed
1310 just as much as the "variable" portion of the trampoline.
1311 Recognizing that a cache flush is going to be required anyway,
1312 dispense with such notions and build a smaller trampoline. */
1314 /* Since more instructions are required to move a template into
1315 place than to create it on the spot, don't use a template. */
1317 /* Length in units of the trampoline for entering a nested function. */
1319 #define TRAMPOLINE_SIZE 12
1321 /* Alignment required for a trampoline in bits. */
1323 #define TRAMPOLINE_ALIGNMENT 16
1325 /* Targets redefine this to invoke code to either flush the cache,
1326 or enable stack execution (or both). */
1328 #ifndef FINALIZE_TRAMPOLINE
1329 #define FINALIZE_TRAMPOLINE(TRAMP)
1332 /* Emit RTL insns to initialize the variable parts of a trampoline.
1333 FNADDR is an RTX for the address of the function's pure code.
1334 CXT is an RTX for the static chain value for the function.
1336 We generate a two-instructions program at address TRAMP :
1340 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1342 emit_move_insn (gen_rtx_MEM (HImode, TRAMP), GEN_INT(0x207C)); \
1343 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \
1344 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \
1346 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \
1347 FINALIZE_TRAMPOLINE(TRAMP); \
1350 /* This is the library routine that is used
1351 to transfer control from the trampoline
1352 to the actual nested function.
1353 It is defined for backward compatibility,
1354 for linking with object code that used the old
1355 trampoline definition. */
1357 /* A colon is used with no explicit operands
1358 to cause the template string to be scanned for %-constructs. */
1359 /* The function name __transfer_from_trampoline is not actually used.
1360 The function definition just permits use of "asm with operands"
1361 (though the operand list is empty). */
1362 #define TRANSFER_FROM_TRAMPOLINE \
1364 __transfer_from_trampoline () \
1366 register char *a0 asm ("%a0"); \
1367 asm (GLOBAL_ASM_OP "___trampoline"); \
1368 asm ("___trampoline:"); \
1369 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \
1370 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \
1374 /* Addressing modes, and classification of registers for them. */
1376 #define HAVE_POST_INCREMENT 1
1377 /* #define HAVE_POST_DECREMENT 0 */
1379 #define HAVE_PRE_DECREMENT 1
1380 /* #define HAVE_PRE_INCREMENT 0 */
1382 /* Macros to check register numbers against specific register classes. */
1384 /* These assume that REGNO is a hard or pseudo reg number.
1385 They give nonzero only if REGNO is a hard reg of the suitable class
1386 or a pseudo reg currently allocated to a suitable hard reg.
1387 Since they use reg_renumber, they are safe only once reg_renumber
1388 has been allocated, which happens in local-alloc.c. */
1390 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1391 ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
1392 #define REGNO_OK_FOR_BASE_P(REGNO) \
1393 (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
1394 #define REGNO_OK_FOR_DATA_P(REGNO) \
1395 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
1396 #define REGNO_OK_FOR_FP_P(REGNO) \
1397 (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
1398 #ifdef SUPPORT_SUN_FPA
1399 #define REGNO_OK_FOR_FPA_P(REGNO) \
1400 (((REGNO) >= 24 && (REGNO) < 56) || (reg_renumber[REGNO] >= 24 && reg_renumber[REGNO] < 56))
1403 /* Now macros that check whether X is a register and also,
1404 strictly, whether it is in a specified class.
1406 These macros are specific to the 68000, and may be used only
1407 in code for printing assembler insns and in conditions for
1408 define_optimization. */
1410 /* 1 if X is a data register. */
1412 #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
1414 /* 1 if X is an fp register. */
1416 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1418 /* 1 if X is an address register */
1420 #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
1422 #ifdef SUPPORT_SUN_FPA
1423 /* 1 if X is a register in the Sun FPA. */
1424 #define FPA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FPA_P (REGNO (X)))
1426 /* Answer must be no if we don't have an FPA. */
1427 #define FPA_REG_P(X) 0
1430 /* Maximum number of registers that can appear in a valid memory address. */
1432 #define MAX_REGS_PER_ADDRESS 2
1434 /* Recognize any constant value that is a valid address. */
1436 #define CONSTANT_ADDRESS_P(X) \
1437 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1438 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1439 || GET_CODE (X) == HIGH)
1441 /* Nonzero if the constant value X is a legitimate general operand.
1442 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1444 #define LEGITIMATE_CONSTANT_P(X) 1
1446 /* Nonzero if the constant value X is a legitimate general operand
1447 when generating PIC code. It is given that flag_pic is on and
1448 that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1450 PCREL_GENERAL_OPERAND_OK makes reload accept addresses that are
1451 accepted by insn predicates, but which would otherwise fail the
1452 `general_operand' test. */
1454 #ifndef REG_OK_STRICT
1455 #define PCREL_GENERAL_OPERAND_OK 0
1457 #define PCREL_GENERAL_OPERAND_OK (TARGET_PCREL)
1460 #define LEGITIMATE_PIC_OPERAND_P(X) \
1461 ((! symbolic_operand (X, VOIDmode) \
1462 && ! (GET_CODE (X) == CONST_DOUBLE && mem_for_const_double (X) != 0 \
1463 && GET_CODE (mem_for_const_double (X)) == MEM \
1464 && symbolic_operand (XEXP (mem_for_const_double (X), 0), \
1466 || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \
1467 || PCREL_GENERAL_OPERAND_OK)
1469 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1470 and check its validity for a certain class.
1471 We have two alternate definitions for each of them.
1472 The usual definition accepts all pseudo regs; the other rejects
1473 them unless they have been allocated suitable hard regs.
1474 The symbol REG_OK_STRICT causes the latter definition to be used.
1476 Most source files want to accept pseudo regs in the hope that
1477 they will get allocated to the class that the insn wants them to be in.
1478 Source files for reload pass need to be strict.
1479 After reload, it makes no difference, since pseudo regs have
1480 been eliminated by then. */
1482 #ifndef REG_OK_STRICT
1484 /* Nonzero if X is a hard reg that can be used as an index
1485 or if it is a pseudo reg. */
1486 #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
1487 /* Nonzero if X is a hard reg that can be used as a base reg
1488 or if it is a pseudo reg. */
1489 #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
1493 /* Nonzero if X is a hard reg that can be used as an index. */
1494 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1495 /* Nonzero if X is a hard reg that can be used as a base reg. */
1496 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1500 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1501 that is a valid memory address for an instruction.
1502 The MODE argument is the machine mode for the MEM expression
1503 that wants to use this address.
1505 When generating PIC, an address involving a SYMBOL_REF is legitimate
1506 if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF.
1507 We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses,
1508 and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF.
1510 Likewise for a LABEL_REF when generating PIC.
1512 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1514 /* Allow SUBREG everywhere we allow REG. This results in better code. It
1515 also makes function inlining work when inline functions are called with
1516 arguments that are SUBREGs. */
1518 #define LEGITIMATE_BASE_REG_P(X) \
1519 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1520 || (GET_CODE (X) == SUBREG \
1521 && GET_CODE (SUBREG_REG (X)) == REG \
1522 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1524 #define INDIRECTABLE_1_ADDRESS_P(X) \
1525 ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \
1526 || LEGITIMATE_BASE_REG_P (X) \
1527 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
1528 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
1529 || (GET_CODE (X) == PLUS \
1530 && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
1531 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1533 || ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) \
1534 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1535 && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \
1536 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1537 && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF))
1539 #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
1540 { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
1542 /* Only labels on dispatch tables are valid for indexing from. */
1543 #define GO_IF_INDEXABLE_BASE(X, ADDR) \
1545 if (GET_CODE (X) == LABEL_REF \
1546 && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \
1547 && GET_CODE (temp) == JUMP_INSN \
1548 && (GET_CODE (PATTERN (temp)) == ADDR_VEC \
1549 || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \
1551 if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; }
1553 #define GO_IF_INDEXING(X, ADDR) \
1554 { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
1555 { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
1556 if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
1557 { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
1559 #define GO_IF_INDEXED_ADDRESS(X, ADDR) \
1560 { GO_IF_INDEXING (X, ADDR); \
1561 if (GET_CODE (X) == PLUS) \
1562 { if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1563 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)) \
1564 { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \
1565 if (GET_CODE (XEXP (X, 0)) == CONST_INT \
1566 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)) \
1567 { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
1569 /* coldfire/5200 does not allow HImode index registers. */
1570 #define LEGITIMATE_INDEX_REG_P(X) \
1571 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1573 && GET_CODE (X) == SIGN_EXTEND \
1574 && GET_CODE (XEXP (X, 0)) == REG \
1575 && GET_MODE (XEXP (X, 0)) == HImode \
1576 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
1577 || (GET_CODE (X) == SUBREG \
1578 && GET_CODE (SUBREG_REG (X)) == REG \
1579 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1581 #define LEGITIMATE_INDEX_P(X) \
1582 (LEGITIMATE_INDEX_REG_P (X) \
1583 || ((TARGET_68020 || TARGET_5200) && GET_CODE (X) == MULT \
1584 && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
1585 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1586 && (INTVAL (XEXP (X, 1)) == 2 \
1587 || INTVAL (XEXP (X, 1)) == 4 \
1588 || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_5200))))
1590 /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */
1591 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1592 { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
1593 GO_IF_INDEXED_ADDRESS (X, ADDR); \
1594 if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \
1595 && LEGITIMATE_INDEX_P (XEXP (X, 0)) \
1596 && GET_CODE (XEXP (X, 1)) == LABEL_REF) \
1599 /* Don't call memory_address_noforce for the address to fetch
1600 the switch offset. This address is ok as it stands (see above),
1601 but memory_address_noforce would alter it. */
1602 #define PIC_CASE_VECTOR_ADDRESS(index) index
1604 /* Try machine-dependent ways of modifying an illegitimate address
1605 to be legitimate. If we find one, return the new, valid address.
1606 This macro is used in only one place: `memory_address' in explow.c.
1608 OLDX is the address as it was before break_out_memory_refs was called.
1609 In some cases it is useful to look at this to decide what needs to be done.
1611 MODE and WIN are passed so that this macro can use
1612 GO_IF_LEGITIMATE_ADDRESS.
1614 It is always safe for this macro to do nothing. It exists to recognize
1615 opportunities to optimize the output.
1617 For the 68000, we handle X+REG by loading X into a register R and
1618 using R+REG. R will go in an address reg and indexing will be used.
1619 However, if REG is a broken-out memory address or multiplication,
1620 nothing needs to be done because REG can certainly go in an address reg. */
1622 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1623 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1624 { register int ch = (X) != (OLDX); \
1625 if (GET_CODE (X) == PLUS) \
1627 if (GET_CODE (XEXP (X, 0)) == MULT) \
1628 { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \
1629 if (GET_CODE (XEXP (X, 1)) == MULT) \
1630 { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \
1631 if (ch && GET_CODE (XEXP (X, 1)) == REG \
1632 && GET_CODE (XEXP (X, 0)) == REG) \
1634 if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
1635 if (GET_CODE (XEXP (X, 0)) == REG \
1636 || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
1637 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1638 && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
1639 { register rtx temp = gen_reg_rtx (Pmode); \
1640 register rtx val = force_operand (XEXP (X, 1), 0); \
1641 emit_move_insn (temp, val); \
1643 XEXP (X, 1) = temp; \
1645 else if (GET_CODE (XEXP (X, 1)) == REG \
1646 || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
1647 && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
1648 && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
1649 { register rtx temp = gen_reg_rtx (Pmode); \
1650 register rtx val = force_operand (XEXP (X, 0), 0); \
1651 emit_move_insn (temp, val); \
1653 XEXP (X, 0) = temp; \
1656 /* Go to LABEL if ADDR (a legitimate address expression)
1657 has an effect that depends on the machine mode it is used for.
1658 On the 68000, only predecrement and postincrement address depend thus
1659 (the amount of decrement or increment being the length of the operand). */
1661 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1662 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL
1664 /* Specify the machine mode that this machine uses
1665 for the index in the tablejump instruction. */
1666 #define CASE_VECTOR_MODE HImode
1668 /* Define as C expression which evaluates to nonzero if the tablejump
1669 instruction expects the table to contain offsets from the address of the
1671 Do not define this if the table should contain absolute addresses. */
1672 #define CASE_VECTOR_PC_RELATIVE 1
1674 /* Specify the tree operation to be used to convert reals to integers. */
1675 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1677 /* This is the kind of divide that is easiest to do in the general case. */
1678 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1680 /* Define this as 1 if `char' should by default be signed; else as 0. */
1681 #define DEFAULT_SIGNED_CHAR 1
1683 /* Don't cse the address of the function being compiled. */
1684 #define NO_RECURSIVE_FUNCTION_CSE
1686 /* Max number of bytes we can move from memory to memory
1687 in one reasonably fast instruction. */
1690 /* Define this if zero-extension is slow (more than one real instruction). */
1691 #define SLOW_ZERO_EXTEND
1693 /* Nonzero if access to memory by bytes is slow and undesirable. */
1694 #define SLOW_BYTE_ACCESS 0
1696 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1697 is done just by pretending it is already truncated. */
1698 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1700 /* We assume that the store-condition-codes instructions store 0 for false
1701 and some other value for true. This is the value stored for true. */
1703 #define STORE_FLAG_VALUE (-1)
1705 /* When a prototype says `char' or `short', really pass an `int'. */
1706 #define PROMOTE_PROTOTYPES 1
1708 /* Specify the machine mode that pointers have.
1709 After generation of rtl, the compiler makes no further distinction
1710 between pointers and any other objects of this machine mode. */
1711 #define Pmode SImode
1713 /* A function address in a call instruction
1714 is a byte address (for indexing purposes)
1715 so give the MEM rtx a byte's mode. */
1716 #define FUNCTION_MODE QImode
1718 /* Compute the cost of computing a constant rtl expression RTX
1719 whose rtx-code is CODE. The body of this macro is a portion
1720 of a switch statement. If the code is computed here,
1721 return it with a return statement. Otherwise, break from the switch. */
1723 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1725 /* Constant zero is super cheap due to clr instruction. */ \
1726 if (RTX == const0_rtx) return 0; \
1727 /* if ((OUTER_CODE) == SET) */ \
1728 return const_int_cost(RTX); \
1733 case CONST_DOUBLE: \
1736 /* Compute the cost of various arithmetic operations.
1737 These are vaguely right for a 68020. */
1738 /* The costs for long multiply have been adjusted to
1739 work properly in synth_mult on the 68020,
1740 relative to an average of the time for add and the time for shift,
1741 taking away a little more because sometimes move insns are needed. */
1742 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */
1743 #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : 13)
1744 #define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : 5)
1745 #define DIVW_COST (TARGET_68020 ? 27 : 12)
1747 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1749 /* An lea costs about three times as much as a simple add. */ \
1750 if (GET_MODE (X) == SImode \
1751 && GET_CODE (XEXP (X, 1)) == REG \
1752 && GET_CODE (XEXP (X, 0)) == MULT \
1753 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1754 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1755 && (INTVAL (XEXP (XEXP (X, 0), 1)) == 2 \
1756 || INTVAL (XEXP (XEXP (X, 0), 1)) == 4 \
1757 || INTVAL (XEXP (XEXP (X, 0), 1)) == 8)) \
1758 return COSTS_N_INSNS (3); /* lea an@(dx:l:i),am */ \
1764 return COSTS_N_INSNS(1); \
1765 if (! TARGET_68020) \
1767 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
1769 if (INTVAL (XEXP (X, 1)) < 16) \
1770 return COSTS_N_INSNS (2) + INTVAL (XEXP (X, 1)) / 2; \
1772 /* We're using clrw + swap for these cases. */ \
1773 return COSTS_N_INSNS (4) + (INTVAL (XEXP (X, 1)) - 16) / 2; \
1775 return COSTS_N_INSNS (10); /* worst case */ \
1777 /* A shift by a big integer takes an extra instruction. */ \
1778 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1779 && (INTVAL (XEXP (X, 1)) == 16)) \
1780 return COSTS_N_INSNS (2); /* clrw;swap */ \
1781 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1782 && !(INTVAL (XEXP (X, 1)) > 0 \
1783 && INTVAL (XEXP (X, 1)) <= 8)) \
1784 return COSTS_N_INSNS (3); /* lsr #i,dn */ \
1787 if ((GET_CODE (XEXP (X, 0)) == ZERO_EXTEND \
1788 || GET_CODE (XEXP (X, 0)) == SIGN_EXTEND) \
1789 && GET_MODE (X) == SImode) \
1790 return COSTS_N_INSNS (MULW_COST); \
1791 if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \
1792 return COSTS_N_INSNS (MULW_COST); \
1794 return COSTS_N_INSNS (MULL_COST); \
1799 if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \
1800 return COSTS_N_INSNS (DIVW_COST); /* div.w */ \
1801 return COSTS_N_INSNS (43); /* div.l */
1803 /* Tell final.c how to eliminate redundant test instructions. */
1805 /* Here we define machine-dependent flags and fields in cc_status
1806 (see `conditions.h'). */
1808 /* Set if the cc value is actually in the 68881, so a floating point
1809 conditional branch must be output. */
1810 #define CC_IN_68881 04000
1812 /* Store in cc_status the expressions that the condition codes will
1813 describe after execution of an instruction whose pattern is EXP.
1814 Do not alter them if the instruction would not alter the cc's. */
1816 /* On the 68000, all the insns to store in an address register fail to
1817 set the cc's. However, in some cases these instructions can make it
1818 possibly invalid to use the saved cc's. In those cases we clear out
1819 some or all of the saved cc's so they won't be used. */
1821 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
1823 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
1824 { if (cc_prev_status.flags & CC_IN_68881) \
1826 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
1830 /* Control the assembler format that we output. */
1832 /* Output at beginning of assembler file. */
1834 #define ASM_FILE_START(FILE) \
1835 fprintf (FILE, "#NO_APP\n");
1837 /* Output to assembler file text saying following lines
1838 may contain character constants, extra white space, comments, etc. */
1840 #define ASM_APP_ON "#APP\n"
1842 /* Output to assembler file text saying following lines
1843 no longer contain unusual constructs. */
1845 #define ASM_APP_OFF "#NO_APP\n"
1847 /* Output before read-only data. */
1849 #define TEXT_SECTION_ASM_OP "\t.text"
1851 /* Output before writable data. */
1853 #define DATA_SECTION_ASM_OP "\t.data"
1855 /* Here are four prefixes that are used by asm_fprintf to
1856 facilitate customization for alternate assembler syntaxes.
1857 Machines with no likelihood of an alternate syntax need not
1858 define these and need not use asm_fprintf. */
1860 /* The prefix for register names. Note that REGISTER_NAMES
1861 is supposed to include this prefix. */
1863 #define REGISTER_PREFIX ""
1865 /* The prefix for local labels. You should be able to define this as
1866 an empty string, or any arbitrary string (such as ".", ".L%", etc)
1867 without having to make any other changes to account for the specific
1868 definition. Note it is a string literal, not interpreted by printf
1871 #define LOCAL_LABEL_PREFIX ""
1873 /* The prefix to add to user-visible assembler symbols. */
1875 #define USER_LABEL_PREFIX "_"
1877 /* The prefix for immediate operands. */
1879 #define IMMEDIATE_PREFIX "#"
1881 /* How to refer to registers in assembler output.
1882 This sequence is indexed by compiler's hard-register-number (see above). */
1884 #ifndef SUPPORT_SUN_FPA
1886 #define REGISTER_NAMES \
1887 {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \
1888 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \
1889 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7" }
1891 #else /* SUPPORTED_SUN_FPA */
1893 #define REGISTER_NAMES \
1894 {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \
1895 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \
1896 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", \
1897 "fpa0", "fpa1", "fpa2", "fpa3", "fpa4", "fpa5", "fpa6", "fpa7", \
1898 "fpa8", "fpa9", "fpa10", "fpa11", "fpa12", "fpa13", "fpa14", "fpa15", \
1899 "fpa16", "fpa17", "fpa18", "fpa19", "fpa20", "fpa21", "fpa22", "fpa23", \
1900 "fpa24", "fpa25", "fpa26", "fpa27", "fpa28", "fpa29", "fpa30", "fpa31" }
1902 #endif /* defined SUPPORT_SUN_FPA */
1904 /* How to renumber registers for dbx and gdb.
1905 On the Sun-3, the floating point registers have numbers
1906 18 to 25, not 16 to 23 as they do in the compiler. */
1908 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
1910 /* Before the prologue, RA is at 0(%sp). */
1911 #define INCOMING_RETURN_ADDR_RTX \
1912 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
1914 /* We must not use the DBX register numbers for the DWARF 2 CFA column
1915 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
1916 Instead use the identity mapping. */
1917 #define DWARF_FRAME_REGNUM(REG) REG
1919 /* Before the prologue, the top of the frame is at 4(%sp). */
1920 #define INCOMING_FRAME_SP_OFFSET 4
1922 /* This is how to output the definition of a user-level label named NAME,
1923 such as the label on a static function or variable NAME. */
1925 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1926 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1928 /* This is how to output a command to make the user-level label named NAME
1929 defined for reference from other files. */
1931 #define GLOBAL_ASM_OP "\t.globl\t"
1932 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1933 do { fprintf (FILE, "%s", GLOBAL_ASM_OP); \
1934 assemble_name (FILE, NAME); \
1935 fputs ("\n", FILE);} while (0)
1937 /* This is how to output a reference to a user-level label named NAME.
1938 `assemble_name' uses this. */
1940 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1941 asm_fprintf (FILE, "%0U%s", NAME)
1943 /* This is how to output an internal numbered label where
1944 PREFIX is the class of label and NUM is the number within the class. */
1946 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1947 asm_fprintf (FILE, "%0L%s%d:\n", PREFIX, NUM)
1949 /* This is how to store into the string LABEL
1950 the symbol_ref name of an internal numbered label where
1951 PREFIX is the class of label and NUM is the number within the class.
1952 This is suitable for output with `assemble_name'. */
1954 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1955 sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM))
1957 /* This is how to output a `long double' extended real constant. */
1959 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
1961 REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \
1962 fprintf (FILE, "\t.long 0x%lx,0x%lx,0x%lx\n", l[0], l[1], l[2]); \
1965 /* This is how to output an assembler line defining a `double' constant. */
1967 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1968 do { char dstr[30]; \
1969 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
1970 fprintf (FILE, "\t.double 0r%s\n", dstr); \
1973 /* This is how to output an assembler line defining a `float' constant. */
1975 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1977 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1978 fprintf (FILE, "\t.long 0x%lx\n", l); \
1981 /* This is how to output an assembler line defining an `int' constant. */
1983 #define ASM_OUTPUT_INT(FILE,VALUE) \
1984 ( fprintf (FILE, "\t.long "), \
1985 output_addr_const (FILE, (VALUE)), \
1986 fprintf (FILE, "\n"))
1988 /* Likewise for `char' and `short' constants. */
1990 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1991 ( fprintf (FILE, "\t.word "), \
1992 output_addr_const (FILE, (VALUE)), \
1993 fprintf (FILE, "\n"))
1995 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1996 ( fprintf (FILE, "\t.byte "), \
1997 output_addr_const (FILE, (VALUE)), \
1998 fprintf (FILE, "\n"))
2000 /* This is how to output an assembler line for a numeric constant byte. */
2002 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
2003 fprintf (FILE, "\t.byte 0x%x\n", (int)(VALUE))
2005 /* This is how to output an insn to push a register on the stack.
2006 It need not be very fast code. */
2008 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
2009 asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO])
2011 /* This is how to output an insn to pop a register from the stack.
2012 It need not be very fast code. */
2014 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
2015 asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO])
2017 /* This is how to output an element of a case-vector that is absolute.
2018 (The 68000 does not use such vectors,
2019 but we must define this macro anyway.) */
2021 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2022 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE)
2024 /* This is how to output an element of a case-vector that is relative. */
2026 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2027 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL)
2029 /* This is how to output an assembler line
2030 that says to advance the location counter
2031 to a multiple of 2**LOG bytes. */
2033 /* We don't have a way to align to more than a two-byte boundary, so do the
2034 best we can and don't complain. */
2035 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2037 fprintf (FILE, "\t.even\n");
2039 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2040 fprintf (FILE, "\t.skip %u\n", (SIZE))
2042 /* This says how to output an assembler line
2043 to define a global common symbol. */
2045 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2046 ( fputs (".comm ", (FILE)), \
2047 assemble_name ((FILE), (NAME)), \
2048 fprintf ((FILE), ",%u\n", (ROUNDED)))
2050 /* This says how to output an assembler line
2051 to define a local common symbol. */
2053 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
2054 ( fputs (".lcomm ", (FILE)), \
2055 assemble_name ((FILE), (NAME)), \
2056 fprintf ((FILE), ",%u\n", (ROUNDED)))
2058 /* Store in OUTPUT a string (made with alloca) containing
2059 an assembler-name for a local static variable named NAME.
2060 LABELNO is an integer which is different for each call. */
2062 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2063 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2064 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2066 /* Output a float value (represented as a C double) as an immediate operand.
2067 This macro is a 68k-specific macro. */
2069 #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
2074 REAL_VALUE_TO_DECIMAL (VALUE, "%.9g", dstr); \
2075 asm_fprintf ((FILE), "%I0r%s", dstr); \
2080 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
2081 asm_fprintf ((FILE), "%I0x%lx", l); \
2085 /* Output a double value (represented as a C double) as an immediate operand.
2086 This macro is a 68k-specific macro. */
2087 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
2088 do { char dstr[30]; \
2089 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
2090 asm_fprintf (FILE, "%I0r%s", dstr); \
2093 /* Note, long double immediate operands are not actually
2094 generated by m68k.md. */
2095 #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \
2096 do { char dstr[30]; \
2097 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
2098 asm_fprintf (FILE, "%I0r%s", dstr); \
2101 /* Print operand X (an rtx) in assembler syntax to file FILE.
2102 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2103 For `%' followed by punctuation, CODE is the punctuation and X is null.
2105 On the 68000, we use several CODE characters:
2106 '.' for dot needed in Motorola-style opcode names.
2107 '-' for an operand pushing on the stack:
2108 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2109 '+' for an operand pushing on the stack:
2110 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2111 '@' for a reference to the top word on the stack:
2112 sp@, (sp) or (%sp) depending on the style of syntax.
2113 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2114 but & in SGS syntax).
2115 '!' for the fpcr register (used in some float-to-fixed conversions).
2116 '$' for the letter `s' in an op code, but only on the 68040.
2117 '&' for the letter `d' in an op code, but only on the 68040.
2118 '/' for register prefix needed by longlong.h.
2120 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2121 'd' to force memory addressing to be absolute, not relative.
2122 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2123 'o' for operands to go directly to output_operand_address (bypassing
2124 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
2125 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
2126 than directly). Second part of 'y' below.
2127 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2128 or print pair of registers as rx:ry.
2129 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
2130 CONST_DOUBLE's as SunFPA constant RAM registers if
2131 possible, so it should not be used except for the SunFPA. */
2133 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2134 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
2135 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \
2136 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/')
2138 /* A C compound statement to output to stdio stream STREAM the
2139 assembler syntax for an instruction operand X. X is an RTL
2142 CODE is a value that can be used to specify one of several ways
2143 of printing the operand. It is used when identical operands
2144 must be printed differently depending on the context. CODE
2145 comes from the `%' specification that was used to request
2146 printing of the operand. If the specification was just `%DIGIT'
2147 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2148 is the ASCII code for LTR.
2150 If X is a register, this macro should print the register's name.
2151 The names can be found in an array `reg_names' whose type is
2152 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2154 When the machine description has a specification `%PUNCT' (a `%'
2155 followed by a punctuation character), this macro is called with
2156 a null pointer for X and the punctuation character for CODE.
2158 See m68k.c for the m68k specific codes. */
2160 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2162 /* A C compound statement to output to stdio stream STREAM the
2163 assembler syntax for an instruction operand that is a memory
2164 reference whose address is ADDR. ADDR is an RTL expression.
2166 On some machines, the syntax for a symbolic address depends on
2167 the section that the address refers to. On these machines,
2168 define the macro `ENCODE_SECTION_INFO' to store the information
2169 into the `symbol_ref', and then check for it here. */
2171 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2173 /* Variables in m68k.c */
2174 extern const char *m68k_align_loops_string;
2175 extern const char *m68k_align_jumps_string;
2176 extern const char *m68k_align_funcs_string;
2177 extern int m68k_align_loops;
2178 extern int m68k_align_jumps;
2179 extern int m68k_align_funcs;
2180 extern int m68k_last_compare_had_fp_operands;
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