1 /* Definitions of target machine for GNU compiler.
2 Sun 68000/68020 version.
3 Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 /* Note that some other tm.h files include this one and then override
25 many of the definitions that relate to assembler syntax. */
27 /* Target CPU builtins. */
28 #define TARGET_CPU_CPP_BUILTINS() \
31 builtin_define ("__m68k__"); \
32 builtin_define_std ("mc68000"); \
33 if (TARGET_68040_ONLY) \
36 builtin_define_std ("mc68060"); \
38 builtin_define_std ("mc68040"); \
40 else if (TARGET_68060) /* -m68020-60 */ \
42 builtin_define_std ("mc68060"); \
43 builtin_define_std ("mc68040"); \
44 builtin_define_std ("mc68030"); \
45 builtin_define_std ("mc68020"); \
47 else if (TARGET_68040) /* -m68020-40 */ \
49 builtin_define_std ("mc68040"); \
50 builtin_define_std ("mc68030"); \
51 builtin_define_std ("mc68020"); \
53 else if (TARGET_68030) \
54 builtin_define_std ("mc68030"); \
55 else if (TARGET_68020) \
56 builtin_define_std ("mc68020"); \
58 builtin_define ("__HAVE_68881__"); \
61 builtin_define_std ("mc68332"); \
62 builtin_define_std ("mcpu32"); \
64 if (TARGET_COLDFIRE) \
65 builtin_define ("__mcoldfire__"); \
67 builtin_define ("__mcf5200__"); \
70 builtin_define ("__mcf528x__"); \
71 builtin_define ("__mcf5200__"); \
75 builtin_define ("__mcf5300__"); \
76 builtin_define ("__mcf5307__"); \
80 builtin_define ("__mcf5400__"); \
81 builtin_define ("__mcf5407__"); \
83 if (TARGET_CF_HWDIV) \
84 builtin_define ("__mcfhwdiv__"); \
86 builtin_define ("__pic__"); \
88 builtin_define ("__PIC__"); \
89 builtin_assert ("cpu=m68k"); \
90 builtin_assert ("machine=m68k"); \
95 /* Classify the groups of pseudo-ops used to assemble QI, HI and SI
97 #define INT_OP_STANDARD 0 /* .byte, .short, .long */
98 #define INT_OP_DOT_WORD 1 /* .byte, .word, .long */
99 #define INT_OP_NO_DOT 2 /* byte, short, long */
100 #define INT_OP_DC 3 /* dc.b, dc.w, dc.l */
102 /* Set the default */
103 #define INT_OP_GROUP INT_OP_DOT_WORD
105 /* Print subsidiary information on the compiler version in use. */
107 #define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)");
109 #define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)");
112 /* Run-time compilation parameters selecting different hardware subsets. */
114 extern int target_flags;
116 /* Macros used in the machine description to test the flags. */
118 /* Compile for a 68020 (not a 68000 or 68010). */
119 #define MASK_68020 (1<<0)
120 #define TARGET_68020 (target_flags & MASK_68020)
122 /* Compile for a 68030. This does not really make a difference in GCC,
123 it just enables the __mc68030__ predefine. */
124 #define MASK_68030 (1<<1)
125 #define TARGET_68030 (target_flags & MASK_68030)
127 /* Optimize for 68040, but still allow execution on 68020
128 (-m68020-40 or -m68040).
129 The 68040 will execute all 68030 and 68881/2 instructions, but some
130 of them must be emulated in software by the OS. When TARGET_68040 is
131 turned on, these instructions won't be used. This code will still
132 run on a 68030 and 68881/2. */
133 #define MASK_68040 (1<<2)
134 #define TARGET_68040 (target_flags & MASK_68040)
136 /* Use the 68040-only fp instructions (-m68040 or -m68060). */
137 #define MASK_68040_ONLY (1<<3)
138 #define TARGET_68040_ONLY (target_flags & MASK_68040_ONLY)
140 /* Optimize for 68060, but still allow execution on 68020
141 (-m68020-60 or -m68060).
142 The 68060 will execute all 68030 and 68881/2 instructions, but some
143 of them must be emulated in software by the OS. When TARGET_68060 is
144 turned on, these instructions won't be used. This code will still
145 run on a 68030 and 68881/2. */
146 #define MASK_68060 (1<<4)
147 #define TARGET_68060 (target_flags & MASK_68060)
149 /* Compile for mcf5200 */
150 #define MASK_5200 (1<<5)
151 #define TARGET_5200 (target_flags & MASK_5200)
153 /* Build for ColdFire v3 */
154 #define MASK_CFV3 (1<<6)
155 #define TARGET_CFV3 (target_flags & MASK_CFV3)
157 /* Build for ColdFire v4 */
158 #define MASK_CFV4 (1<<7)
159 #define TARGET_CFV4 (target_flags & MASK_CFV4)
161 /* Compile for ColdFire 528x */
162 #define MASK_528x (1<<8)
163 #define TARGET_528x (target_flags & MASK_528x)
165 /* Divide support for ColdFire */
166 #define MASK_CF_HWDIV (1<<9)
167 #define TARGET_CF_HWDIV (target_flags & MASK_CF_HWDIV)
169 /* Compile 68881 insns for floating point (not library calls). */
170 #define MASK_68881 (1<<10)
171 #define TARGET_68881 (target_flags & MASK_68881)
173 /* Compile using 68020 bit-field insns. */
174 #define MASK_BITFIELD (1<<11)
175 #define TARGET_BITFIELD (target_flags & MASK_BITFIELD)
177 /* Compile with 16-bit `int'. */
178 #define MASK_SHORT (1<<12)
179 #define TARGET_SHORT (target_flags & MASK_SHORT)
181 /* Align ints to a word boundary. This breaks compatibility with the
182 published ABI's for structures containing ints, but produces faster
183 code on cpus with 32 bit busses (020, 030, 040, 060, CPU32+, coldfire).
184 It's required for coldfire cpus without a misalignment module. */
185 #define MASK_ALIGN_INT (1<<13)
186 #define TARGET_ALIGN_INT (target_flags & MASK_ALIGN_INT)
188 /* Use PC-relative addressing modes (without using a global offset table).
189 The m68000 supports 16-bit PC-relative addressing.
190 The m68020 supports 32-bit PC-relative addressing
191 (using outer displacements).
193 Under this model, all SYMBOL_REFs (and CONSTs) and LABEL_REFs are
194 treated as all containing an implicit PC-relative component, and hence
195 cannot be used directly as addresses for memory writes. See the comments
196 in m68k.c for more information. */
197 #define MASK_PCREL (1<<14)
198 #define TARGET_PCREL (target_flags & MASK_PCREL)
200 /* Relax strict alignment. */
201 #define MASK_NO_STRICT_ALIGNMENT (1<<15)
202 #define TARGET_STRICT_ALIGNMENT (~target_flags & MASK_NO_STRICT_ALIGNMENT)
205 /* Compile for a CPU32. A 68020 without bitfields is a good
206 heuristic for a CPU32. */
207 #define TARGET_CPU32 (TARGET_68020 && !TARGET_BITFIELD)
209 /* Is the target a ColdFire? */
210 #define MASK_COLDFIRE (MASK_5200|MASK_528x|MASK_CFV3|MASK_CFV4)
211 #define TARGET_COLDFIRE (target_flags & MASK_COLDFIRE)
213 /* Which bits can be set by specifying a coldfire */
214 #define MASK_ALL_CF_BITS (MASK_COLDFIRE|MASK_CF_HWDIV)
216 /* Macro to define tables used to set the flags.
217 This is a list in braces of pairs in braces,
218 each pair being { "NAME", VALUE }
219 where VALUE is the bits to set or minus the bits to clear.
220 An empty string NAME is used to identify the default VALUE. */
222 #define TARGET_SWITCHES \
223 { { "68020", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \
224 N_("Generate code for a 68020") }, \
225 { "c68020", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \
226 N_("Generate code for a 68020") }, \
227 { "68020", (MASK_68020|MASK_BITFIELD), "" }, \
228 { "c68020", (MASK_68020|MASK_BITFIELD), "" }, \
229 { "68000", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
230 |MASK_68020|MASK_BITFIELD|MASK_68881), \
231 N_("Generate code for a 68000") }, \
232 { "c68000", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
233 |MASK_68020|MASK_BITFIELD|MASK_68881), \
234 N_("Generate code for a 68000") }, \
235 { "bitfield", MASK_BITFIELD, \
236 N_("Use the bit-field instructions") }, \
237 { "nobitfield", - MASK_BITFIELD, \
238 N_("Do not use the bit-field instructions") }, \
239 { "short", MASK_SHORT, \
240 N_("Consider type `int' to be 16 bits wide") }, \
241 { "noshort", - MASK_SHORT, \
242 N_("Consider type `int' to be 32 bits wide") }, \
243 { "68881", MASK_68881, "" }, \
244 { "soft-float", - (MASK_68040_ONLY|MASK_68881), \
245 N_("Generate code with library calls for floating point") }, \
246 { "68020-40", -(MASK_ALL_CF_BITS|MASK_68060|MASK_68040_ONLY), \
247 N_("Generate code for a 68040, without any new instructions") }, \
248 { "68020-40", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040), ""},\
249 { "68020-60", -(MASK_ALL_CF_BITS|MASK_68040_ONLY), \
250 N_("Generate code for a 68060, without any new instructions") }, \
251 { "68020-60", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040 \
252 |MASK_68060), "" }, \
253 { "68030", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \
254 N_("Generate code for a 68030") }, \
255 { "68030", (MASK_68020|MASK_68030|MASK_BITFIELD), "" }, \
256 { "68040", - (MASK_ALL_CF_BITS|MASK_68060), \
257 N_("Generate code for a 68040") }, \
258 { "68040", (MASK_68020|MASK_68881|MASK_BITFIELD \
259 |MASK_68040_ONLY|MASK_68040), "" }, \
260 { "68060", - (MASK_ALL_CF_BITS|MASK_68040), \
261 N_("Generate code for a 68060") }, \
262 { "68060", (MASK_68020|MASK_68881|MASK_BITFIELD \
263 |MASK_68040_ONLY|MASK_68060), "" }, \
264 { "5200", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
265 |MASK_BITFIELD|MASK_68881), \
266 N_("Generate code for a 520X") }, \
267 { "5200", (MASK_5200), "" }, \
268 { "5206e", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
269 |MASK_BITFIELD|MASK_68881), \
270 N_("Generate code for a 5206e") }, \
271 { "5206e", (MASK_5200|MASK_CF_HWDIV), "" }, \
272 { "528x", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
273 |MASK_BITFIELD|MASK_68881), \
274 N_("Generate code for a 528x") }, \
275 { "528x", (MASK_528x|MASK_CF_HWDIV), "" }, \
276 { "5307", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
277 |MASK_BITFIELD|MASK_68881), \
278 N_("Generate code for a 5307") }, \
279 { "5307", (MASK_CFV3|MASK_CF_HWDIV), "" }, \
280 { "5407", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
281 |MASK_BITFIELD|MASK_68881), \
282 N_("Generate code for a 5407") }, \
283 { "5407", (MASK_CFV4|MASK_CF_HWDIV), "" }, \
285 N_("Generate code for a 68851") }, \
287 N_("Do no generate code for a 68851") }, \
288 { "68302", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
289 |MASK_68020|MASK_BITFIELD|MASK_68881), \
290 N_("Generate code for a 68302") }, \
291 { "68332", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
292 |MASK_BITFIELD|MASK_68881), \
293 N_("Generate code for a 68332") }, \
294 { "68332", MASK_68020, "" }, \
295 { "cpu32", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
296 |MASK_BITFIELD|MASK_68881), \
297 N_("Generate code for a cpu32") }, \
298 { "cpu32", MASK_68020, "" }, \
299 { "align-int", MASK_ALIGN_INT, \
300 N_("Align variables on a 32-bit boundary") }, \
301 { "no-align-int", -MASK_ALIGN_INT, \
302 N_("Align variables on a 16-bit boundary") }, \
303 { "pcrel", MASK_PCREL, \
304 N_("Generate pc-relative code") }, \
305 { "strict-align", -MASK_NO_STRICT_ALIGNMENT, \
306 N_("Do not use unaligned memory references") }, \
307 { "no-strict-align", MASK_NO_STRICT_ALIGNMENT, \
308 N_("Use unaligned memory references") }, \
310 { "", TARGET_DEFAULT, "" }}
311 /* TARGET_DEFAULT is defined in m68k-none.h, netbsd.h, etc. */
313 /* This macro is similar to `TARGET_SWITCHES' but defines names of
314 command options that have values. Its definition is an
315 initializer with a subgrouping for each command option.
317 Each subgrouping contains a string constant, that defines the
318 fixed part of the option name, and the address of a variable. The
319 variable, type `char *', is set to the variable part of the given
320 option if the fixed part matches. The actual option name is made
321 by appending `-m' to the specified name. */
322 #define TARGET_OPTIONS \
323 { { "align-loops=", &m68k_align_loops_string, \
324 N_("Loop code aligned to this power of 2"), 0}, \
325 { "align-jumps=", &m68k_align_jumps_string, \
326 N_("Jump targets are aligned to this power of 2"), 0}, \
327 { "align-functions=", &m68k_align_funcs_string, \
328 N_("Function starts are aligned to this power of 2"), 0}, \
332 /* Sometimes certain combinations of command options do not make
333 sense on a particular target machine. You can define a macro
334 `OVERRIDE_OPTIONS' to take account of this. This macro, if
335 defined, is executed once just after all the command options have
338 Don't use this macro to turn on various extra optimizations for
339 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
341 #define OVERRIDE_OPTIONS override_options()
343 /* These are meant to be redefined in the host dependent files */
344 #define SUBTARGET_SWITCHES
345 #define SUBTARGET_OPTIONS
346 #define SUBTARGET_OVERRIDE_OPTIONS
348 /* target machine storage layout */
350 /* Define for XFmode extended real floating point support. */
351 #define LONG_DOUBLE_TYPE_SIZE 96
353 /* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
354 instructions, we get proper intermediate rounding, otherwise we
355 get extended precision results. */
356 #define TARGET_FLT_EVAL_METHOD (TARGET_68040_ONLY ? 0 : 2)
358 /* Define this if most significant bit is lowest numbered
359 in instructions that operate on numbered bit-fields.
360 This is true for 68020 insns such as bfins and bfexts.
361 We make it true always by avoiding using the single-bit insns
362 except in special cases with constant bit numbers. */
363 #define BITS_BIG_ENDIAN 1
365 /* Define this if most significant byte of a word is the lowest numbered. */
366 /* That is true on the 68000. */
367 #define BYTES_BIG_ENDIAN 1
369 /* Define this if most significant word of a multiword number is the lowest
371 /* For 68000 we can decide arbitrarily
372 since there are no machine instructions for them.
373 So let's be consistent. */
374 #define WORDS_BIG_ENDIAN 1
376 /* Width of a word, in units (bytes). */
377 #define UNITS_PER_WORD 4
379 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
380 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
382 /* Boundary (in *bits*) on which stack pointer should be aligned. */
383 #define STACK_BOUNDARY 16
385 /* Allocation boundary (in *bits*) for the code of a function. */
386 #define FUNCTION_BOUNDARY (1 << (m68k_align_funcs + 3))
388 /* Alignment of field after `int : 0' in a structure. */
389 #define EMPTY_FIELD_BOUNDARY 16
391 /* No data type wants to be aligned rounder than this.
392 Most published ABIs say that ints should be aligned on 16 bit
393 boundaries, but cpus with 32 bit busses get better performance
394 aligned on 32 bit boundaries. Coldfires without a misalignment
395 module require 32 bit alignment. */
396 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
398 /* Set this nonzero if move instructions will actually fail to work
399 when given unaligned data. */
400 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT)
402 /* Maximum power of 2 that code can be aligned to. */
403 #define MAX_CODE_ALIGN 2 /* 4 byte alignment */
405 /* Align loop starts for optimal branching. */
406 #define LOOP_ALIGN(LABEL) (m68k_align_loops)
408 /* This is how to align an instruction for optimal branching. */
409 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) (m68k_align_jumps)
411 /* Define number of bits in most basic integer type.
412 (If undefined, default is BITS_PER_WORD). */
414 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
416 /* Define these to avoid dependence on meaning of `int'. */
418 #define WCHAR_TYPE "long int"
419 #define WCHAR_TYPE_SIZE 32
421 /* Standard register usage. */
423 /* Number of actual hardware registers.
424 The hardware registers are assigned numbers for the compiler
425 from 0 to just below FIRST_PSEUDO_REGISTER.
426 All registers that the compiler knows about must be given numbers,
427 even those that are not normally considered general registers.
428 For the 68000, we give the data registers numbers 0-7,
429 the address registers numbers 010-017,
430 and the 68881 floating point registers numbers 020-027. */
431 #define FIRST_PSEUDO_REGISTER 25
433 /* This defines the register which is used to hold the offset table for PIC. */
434 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 13 : INVALID_REGNUM)
436 /* 1 for registers that have pervasive standard uses
437 and are not available for the register allocator.
438 On the 68000, only the stack pointer is such. */
440 #define FIXED_REGISTERS \
441 {/* Data registers. */ \
442 0, 0, 0, 0, 0, 0, 0, 0, \
444 /* Address registers. */ \
445 0, 0, 0, 0, 0, 0, 0, 1, \
447 /* Floating point registers \
449 0, 0, 0, 0, 0, 0, 0, 0 }
451 /* 1 for registers not available across function calls.
452 These must include the FIXED_REGISTERS and also any
453 registers that can be used without being saved.
454 The latter must include the registers where values are returned
455 and the register where structure-value addresses are passed.
456 Aside from that, you can include as many other registers as you like. */
457 #define CALL_USED_REGISTERS \
458 {1, 1, 0, 0, 0, 0, 0, 0, \
459 1, 1, 0, 0, 0, 0, 0, 1, \
460 1, 1, 0, 0, 0, 0, 0, 0 }
463 /* Make sure everything's fine if we *don't* have a given processor.
464 This assumes that putting a register in fixed_regs will keep the
465 compiler's mitts completely off it. We don't bother to zero it out
466 of register classes. */
468 #define CONDITIONAL_REGISTER_USAGE \
472 if (! TARGET_68881) \
474 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
475 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
476 if (TEST_HARD_REG_BIT (x, i)) \
477 fixed_regs[i] = call_used_regs[i] = 1; \
479 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
480 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
481 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
484 /* Return number of consecutive hard regs needed starting at reg REGNO
485 to hold something of mode MODE.
486 This is ordinarily the length in words of a value of mode MODE
487 but can be less for certain modes in special long registers.
489 On the 68000, ordinary registers hold 32 bits worth;
490 for the 68881 registers, a single register is always enough for
491 anything that can be stored in them at all. */
492 #define HARD_REGNO_NREGS(REGNO, MODE) \
493 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
494 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
496 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
497 On the 68000, the cpu registers can hold any mode but the 68881 registers
498 can hold only SFmode or DFmode. */
500 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
502 && !((REGNO) < 8 && (REGNO) + GET_MODE_SIZE (MODE) / 4 > 8)) \
503 || ((REGNO) >= 16 && (REGNO) < 24 \
504 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
505 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
506 && GET_MODE_UNIT_SIZE (MODE) <= 12))
509 /* Value is 1 if it is a good idea to tie two pseudo registers
510 when one has mode MODE1 and one has mode MODE2.
511 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
512 for any hard reg, then this must be 0 for correct output. */
513 #define MODES_TIEABLE_P(MODE1, MODE2) \
515 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
516 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
517 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
518 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
520 /* Specify the registers used for certain standard purposes.
521 The values of these macros are register numbers. */
523 /* m68000 pc isn't overloaded on a register. */
524 /* #define PC_REGNUM */
526 /* Register to use for pushing function arguments. */
527 #define STACK_POINTER_REGNUM 15
529 /* Base register for access to local variables of the function. */
530 #define FRAME_POINTER_REGNUM 14
532 /* Value should be nonzero if functions must have frame pointers.
533 Zero means the frame pointer need not be set up (and parms
534 may be accessed via the stack pointer) in functions that seem suitable.
535 This is computed in `reload', in reload1.c. */
536 #define FRAME_POINTER_REQUIRED 0
538 /* Base register for access to arguments of the function.
539 * This isn't a hardware register. It will be eliminated to the
540 * stack pointer or frame pointer.
542 #define ARG_POINTER_REGNUM 24
544 /* Register in which static-chain is passed to a function. */
545 #define STATIC_CHAIN_REGNUM 8
547 /* Register in which address to store a structure value
548 is passed to a function. */
549 #define STRUCT_VALUE_REGNUM 9
551 /* Define the classes of registers for register constraints in the
552 machine description. Also define ranges of constants.
554 One of the classes must always be named ALL_REGS and include all hard regs.
555 If there is more than one class, another class must be named NO_REGS
556 and contain no registers.
558 The name GENERAL_REGS must be the name of a class (or an alias for
559 another name such as ALL_REGS). This is the class of registers
560 that is allowed by "g" or "r" in a register constraint.
561 Also, registers outside this class are allocated only when
562 instructions express preferences for them.
564 The classes must be numbered in nondecreasing order; that is,
565 a larger-numbered class must never be contained completely
566 in a smaller-numbered class.
568 For any two classes, it is very desirable that there be another
569 class that represents their union. */
571 /* The 68000 has three kinds of registers, so eight classes would be
572 a complete set. One of them is not needed. */
577 GENERAL_REGS, DATA_OR_FP_REGS,
578 ADDR_OR_FP_REGS, ALL_REGS,
581 #define N_REG_CLASSES (int) LIM_REG_CLASSES
583 /* Give names of register classes as strings for dump file. */
585 #define REG_CLASS_NAMES \
586 { "NO_REGS", "DATA_REGS", \
587 "ADDR_REGS", "FP_REGS", \
588 "GENERAL_REGS", "DATA_OR_FP_REGS", \
589 "ADDR_OR_FP_REGS", "ALL_REGS" }
591 /* Define which registers fit in which classes.
592 This is an initializer for a vector of HARD_REG_SET
593 of length N_REG_CLASSES. */
595 #define REG_CLASS_CONTENTS \
597 {0x00000000}, /* NO_REGS */ \
598 {0x000000ff}, /* DATA_REGS */ \
599 {0x0000ff00}, /* ADDR_REGS */ \
600 {0x00ff0000}, /* FP_REGS */ \
601 {0x0000ffff}, /* GENERAL_REGS */ \
602 {0x00ff00ff}, /* DATA_OR_FP_REGS */ \
603 {0x00ffff00}, /* ADDR_OR_FP_REGS */ \
604 {0x00ffffff}, /* ALL_REGS */ \
607 /* The same information, inverted:
608 Return the class number of the smallest class containing
609 reg number REGNO. This could be a conditional expression
610 or could index an array. */
612 #define REGNO_REG_CLASS(REGNO) (((REGNO)>>3)+1)
614 /* The class value for index registers, and the one for base regs. */
616 #define INDEX_REG_CLASS GENERAL_REGS
617 #define BASE_REG_CLASS ADDR_REGS
619 /* Get reg_class from a letter such as appears in the machine description.
620 We do a trick here to modify the effective constraints on the
621 machine description; we zorch the constraint letters that aren't
622 appropriate for a specific target. This allows us to guarantee
623 that a specific kind of register will not be used for a given target
624 without fiddling with the register classes above. */
626 #define REG_CLASS_FROM_LETTER(C) \
627 ((C) == 'a' ? ADDR_REGS : \
628 ((C) == 'd' ? DATA_REGS : \
629 ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \
633 /* The letters I, J, K, L and M in a register constraint string
634 can be used to stand for particular ranges of immediate operands.
635 This macro defines what the ranges are.
636 C is the letter, and VALUE is a constant value.
637 Return 1 if VALUE is in the range specified by C.
639 For the 68000, `I' is used for the range 1 to 8
640 allowed as immediate shift counts and in addq.
641 `J' is used for the range of signed numbers that fit in 16 bits.
642 `K' is for numbers that moveq can't handle.
643 `L' is for range -8 to -1, range of values that can be added with subq.
644 `M' is for numbers that moveq+notb can't handle.
645 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate.
646 'O' is for 16 (for rotate using swap).
647 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */
649 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
650 ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \
651 (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
652 (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
653 (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \
654 (C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \
655 (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \
656 (C) == 'O' ? (VALUE) == 16 : \
657 (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0)
660 * A small bit of explanation:
661 * "G" defines all of the floating constants that are *NOT* 68881
662 * constants. this is so 68881 constants get reloaded and the
665 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
666 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 )
668 /* A C expression that defines the optional machine-dependent constraint
669 letters that can be used to segregate specific types of operands,
670 usually memory references, for the target machine. It should return 1 if
671 VALUE corresponds to the operand type represented by the constraint letter
672 C. If C is not defined as an extra constraint, the value returned should
673 be 0 regardless of VALUE. */
675 /* Letters in the range `Q' through `U' may be defined in a
676 machine-dependent fashion to stand for arbitrary operand types.
677 The machine description macro `EXTRA_CONSTRAINT' is passed the
678 operand as its first argument and the constraint letter as its
681 `Q' means address register indirect addressing mode.
682 `S' is for operands that satisfy 'm' when -mpcrel is in effect.
683 `T' is for operands that satisfy 's' when -mpcrel is not in effect. */
685 #define EXTRA_CONSTRAINT(OP,CODE) \
688 && GET_CODE (OP) == MEM \
689 && (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
690 || GET_CODE (XEXP (OP, 0)) == LABEL_REF \
691 || GET_CODE (XEXP (OP, 0)) == CONST)) \
695 && (GET_CODE (OP) == SYMBOL_REF \
696 || GET_CODE (OP) == LABEL_REF \
697 || GET_CODE (OP) == CONST)) \
700 ? (GET_CODE (OP) == MEM \
701 && GET_CODE (XEXP (OP, 0)) == REG) \
705 /* Given an rtx X being reloaded into a reg required to be
706 in class CLASS, return the class of reg to actually use.
707 In general this is just CLASS; but on some machines
708 in some cases it is preferable to use a more restrictive class.
709 On the 68000 series, use a data reg if possible when the
710 value is a constant in the range where moveq could be used
711 and we ensure that QImodes are reloaded into data regs. */
713 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
714 ((GET_CODE (X) == CONST_INT \
715 && (unsigned) (INTVAL (X) + 0x80) < 0x100 \
716 && (CLASS) != ADDR_REGS) \
718 : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \
720 : (GET_CODE (X) == CONST_DOUBLE \
721 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
722 ? (TARGET_68881 && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \
723 ? FP_REGS : NO_REGS) \
725 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
726 || GET_CODE (X) == LABEL_REF)) \
730 /* Force QImode output reloads from subregs to be allocated to data regs,
731 since QImode stores from address regs are not supported. We make the
732 assumption that if the class is not ADDR_REGS, then it must be a superset
735 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
736 (((MODE) == QImode && (CLASS) != ADDR_REGS) \
740 /* Return the maximum number of consecutive registers
741 needed to represent mode MODE in a register of class CLASS. */
742 /* On the 68000, this is the size of MODE in words,
743 except in the FP regs, where a single reg is always enough. */
744 #define CLASS_MAX_NREGS(CLASS, MODE) \
745 ((CLASS) == FP_REGS ? 1 \
746 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
748 /* Moves between fp regs and other regs are two insns. */
749 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
750 (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
751 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
754 /* Stack layout; function entry, exit and calling. */
756 /* Define this if pushing a word on the stack
757 makes the stack pointer a smaller address. */
758 #define STACK_GROWS_DOWNWARD
760 /* Define this if the nominal address of the stack frame
761 is at the high-address end of the local variables;
762 that is, each additional local variable allocated
763 goes at a more negative offset in the frame. */
764 #define FRAME_GROWS_DOWNWARD
766 /* Offset within stack frame to start allocating local variables at.
767 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
768 first local allocated. Otherwise, it is the offset to the BEGINNING
769 of the first local allocated. */
770 #define STARTING_FRAME_OFFSET 0
772 /* If we generate an insn to push BYTES bytes,
773 this says how many the stack pointer really advances by.
774 On the 68000, sp@- in a byte insn really pushes a word.
775 On the 5200 (coldfire), sp@- in a byte insn pushes just a byte. */
776 #define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1)
778 /* We want to avoid trying to push bytes. */
779 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
780 (move_by_pieces_ninsns (SIZE, ALIGN) < MOVE_RATIO \
781 && (((SIZE) >=16 && (ALIGN) >= 16) || (TARGET_COLDFIRE)))
783 /* Offset of first parameter from the argument pointer register value. */
784 #define FIRST_PARM_OFFSET(FNDECL) 8
786 /* Value is the number of byte of arguments automatically
787 popped when returning from a subroutine call.
788 FUNDECL is the declaration node of the function (as a tree),
789 FUNTYPE is the data type of the function (as a tree),
790 or for a library call it is an identifier node for the subroutine name.
791 SIZE is the number of bytes of arguments passed on the stack.
793 On the m68k, the caller must always pop the args. */
795 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
797 /* Define how to find the value returned by a function.
798 VALTYPE is the data type of the value (as a tree).
799 If the precise function being called is known, FUNC is its FUNCTION_DECL;
800 otherwise, FUNC is 0. */
802 /* On the 68000 the return value is in D0 regardless. */
804 #define FUNCTION_VALUE(VALTYPE, FUNC) \
805 gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
807 /* Define how to find the value returned by a library function
808 assuming the value has mode MODE. */
810 /* On the 68000 the return value is in D0 regardless. */
812 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
814 /* 1 if N is a possible register number for a function value.
815 On the 68000, d0 is the only register thus used. */
817 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
819 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
820 more than one register. */
822 #define NEEDS_UNTYPED_CALL 0
824 /* Define this if PCC uses the nonreentrant convention for returning
825 structure and union values. */
827 #define PCC_STATIC_STRUCT_RETURN
829 /* 1 if N is a possible register number for function argument passing.
830 On the 68000, no registers are used in this way. */
832 #define FUNCTION_ARG_REGNO_P(N) 0
834 /* Define a data type for recording info about an argument list
835 during the scan of that argument list. This data type should
836 hold all necessary information about the function itself
837 and about the args processed so far, enough to enable macros
838 such as FUNCTION_ARG to determine where the next arg should go.
840 On the m68k, this is a single integer, which is a number of bytes
841 of arguments scanned so far. */
843 #define CUMULATIVE_ARGS int
845 /* Initialize a variable CUM of type CUMULATIVE_ARGS
846 for a call to a function whose data type is FNTYPE.
847 For a library call, FNTYPE is 0.
849 On the m68k, the offset starts at 0. */
851 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
854 /* Update the data in CUM to advance over an argument
855 of mode MODE and data type TYPE.
856 (TYPE is null for libcalls where that information may not be available.) */
858 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
859 ((CUM) += ((MODE) != BLKmode \
860 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
861 : (int_size_in_bytes (TYPE) + 3) & ~3))
863 /* Define where to put the arguments to a function.
864 Value is zero to push the argument on the stack,
865 or a hard register in which to store the argument.
867 MODE is the argument's machine mode.
868 TYPE is the data type of the argument (as a tree).
869 This is null for libcalls where that information may
871 CUM is a variable of type CUMULATIVE_ARGS which gives info about
872 the preceding args and about the function being called.
873 NAMED is nonzero if this argument is a named parameter
874 (otherwise it is an extra parameter matching an ellipsis).
876 On the m68k all args are always pushed. */
878 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
880 /* For an arg passed partly in registers and partly in memory,
881 this is the number of registers used.
882 For args passed entirely in registers or entirely in memory, zero. */
884 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
886 /* Output assembler code to FILE to increment profiler label # LABELNO
887 for profiling a function entry. */
889 #define FUNCTION_PROFILER(FILE, LABELNO) \
890 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO))
892 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
893 the stack pointer does not matter. The value is tested only in
894 functions that have frame pointers.
895 No definition is equivalent to always zero. */
897 #define EXIT_IGNORE_STACK 1
899 /* This is a hook for other tm files to change. */
900 /* #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) */
902 /* Determine if the epilogue should be output as RTL.
903 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
904 #define USE_RETURN_INSN use_return_insn ()
906 /* Output assembler code for a block containing the constant parts
907 of a trampoline, leaving space for the variable parts. */
909 /* On the 68k, the trampoline looks like this:
913 WARNING: Targets that may run on 68040+ cpus must arrange for
914 the instruction cache to be flushed. Previous incarnations of
915 the m68k trampoline code attempted to get around this by either
916 using an out-of-line transfer function or pc-relative data, but
917 the fact remains that the code to jump to the transfer function
918 or the code to load the pc-relative data needs to be flushed
919 just as much as the "variable" portion of the trampoline.
920 Recognizing that a cache flush is going to be required anyway,
921 dispense with such notions and build a smaller trampoline. */
923 /* Since more instructions are required to move a template into
924 place than to create it on the spot, don't use a template. */
926 /* Length in units of the trampoline for entering a nested function. */
928 #define TRAMPOLINE_SIZE 12
930 /* Alignment required for a trampoline in bits. */
932 #define TRAMPOLINE_ALIGNMENT 16
934 /* Targets redefine this to invoke code to either flush the cache,
935 or enable stack execution (or both). */
937 #ifndef FINALIZE_TRAMPOLINE
938 #define FINALIZE_TRAMPOLINE(TRAMP)
941 /* Emit RTL insns to initialize the variable parts of a trampoline.
942 FNADDR is an RTX for the address of the function's pure code.
943 CXT is an RTX for the static chain value for the function.
945 We generate a two-instructions program at address TRAMP :
949 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
951 emit_move_insn (gen_rtx_MEM (HImode, TRAMP), GEN_INT(0x207C)); \
952 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \
953 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \
955 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \
956 FINALIZE_TRAMPOLINE(TRAMP); \
959 /* This is the library routine that is used
960 to transfer control from the trampoline
961 to the actual nested function.
962 It is defined for backward compatibility,
963 for linking with object code that used the old
964 trampoline definition. */
966 /* A colon is used with no explicit operands
967 to cause the template string to be scanned for %-constructs. */
968 /* The function name __transfer_from_trampoline is not actually used.
969 The function definition just permits use of "asm with operands"
970 (though the operand list is empty). */
971 #define TRANSFER_FROM_TRAMPOLINE \
973 __transfer_from_trampoline () \
975 register char *a0 asm ("%a0"); \
976 asm (GLOBAL_ASM_OP "___trampoline"); \
977 asm ("___trampoline:"); \
978 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \
979 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \
983 /* Definitions for register eliminations.
985 This is an array of structures. Each structure initializes one pair
986 of eliminable registers. The "from" register number is given first,
987 followed by "to". Eliminations of the same "from" register are listed
988 in order of preference.
990 There are two registers that can always be eliminated on the m68k.
991 The frame pointer and the arg pointer can be replaced by either the
992 hard frame pointer or to the stack pointer, depending upon the
993 circumstances. The hard frame pointer is not used before reload and
994 so it is not eligible for elimination. */
996 #define ELIMINABLE_REGS \
997 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
998 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
999 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
1001 /* Given FROM and TO register numbers, say whether this elimination is
1002 allowed. Frame pointer elimination is automatically handled.
1004 All other eliminations are valid. */
1006 #define CAN_ELIMINATE(FROM, TO) \
1007 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1009 /* Define the offset between two registers, one to be eliminated, and the other
1010 its replacement, at the start of a routine. */
1012 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1013 (OFFSET) = m68k_initial_elimination_offset(FROM, TO)
1015 /* Addressing modes, and classification of registers for them. */
1017 #define HAVE_POST_INCREMENT 1
1019 #define HAVE_PRE_DECREMENT 1
1021 /* Macros to check register numbers against specific register classes. */
1023 /* These assume that REGNO is a hard or pseudo reg number.
1024 They give nonzero only if REGNO is a hard reg of the suitable class
1025 or a pseudo reg currently allocated to a suitable hard reg.
1026 Since they use reg_renumber, they are safe only once reg_renumber
1027 has been allocated, which happens in local-alloc.c. */
1029 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1030 ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
1031 #define REGNO_OK_FOR_BASE_P(REGNO) \
1032 (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
1033 #define REGNO_OK_FOR_DATA_P(REGNO) \
1034 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
1035 #define REGNO_OK_FOR_FP_P(REGNO) \
1036 (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
1038 /* Now macros that check whether X is a register and also,
1039 strictly, whether it is in a specified class.
1041 These macros are specific to the 68000, and may be used only
1042 in code for printing assembler insns and in conditions for
1043 define_optimization. */
1045 /* 1 if X is a data register. */
1047 #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
1049 /* 1 if X is an fp register. */
1051 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1053 /* 1 if X is an address register */
1055 #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
1057 /* Maximum number of registers that can appear in a valid memory address. */
1059 #define MAX_REGS_PER_ADDRESS 2
1061 /* Recognize any constant value that is a valid address. */
1063 #define CONSTANT_ADDRESS_P(X) \
1064 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1065 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1066 || GET_CODE (X) == HIGH)
1068 /* Nonzero if the constant value X is a legitimate general operand.
1069 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1071 #define LEGITIMATE_CONSTANT_P(X) (GET_MODE (X) != XFmode)
1073 /* Nonzero if the constant value X is a legitimate general operand
1074 when generating PIC code. It is given that flag_pic is on and
1075 that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1077 PCREL_GENERAL_OPERAND_OK makes reload accept addresses that are
1078 accepted by insn predicates, but which would otherwise fail the
1079 `general_operand' test. */
1081 #ifndef REG_OK_STRICT
1082 #define PCREL_GENERAL_OPERAND_OK 0
1084 #define PCREL_GENERAL_OPERAND_OK (TARGET_PCREL)
1087 #define LEGITIMATE_PIC_OPERAND_P(X) \
1088 (! symbolic_operand (X, VOIDmode) \
1089 || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \
1090 || PCREL_GENERAL_OPERAND_OK)
1092 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1093 and check its validity for a certain class.
1094 We have two alternate definitions for each of them.
1095 The usual definition accepts all pseudo regs; the other rejects
1096 them unless they have been allocated suitable hard regs.
1097 The symbol REG_OK_STRICT causes the latter definition to be used.
1099 Most source files want to accept pseudo regs in the hope that
1100 they will get allocated to the class that the insn wants them to be in.
1101 Source files for reload pass need to be strict.
1102 After reload, it makes no difference, since pseudo regs have
1103 been eliminated by then. */
1105 #ifndef REG_OK_STRICT
1107 /* Nonzero if X is a hard reg that can be used as an index
1108 or if it is a pseudo reg. */
1109 #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
1110 /* Nonzero if X is a hard reg that can be used as a base reg
1111 or if it is a pseudo reg. */
1112 #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
1116 /* Nonzero if X is a hard reg that can be used as an index. */
1117 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1118 /* Nonzero if X is a hard reg that can be used as a base reg. */
1119 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1123 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1124 that is a valid memory address for an instruction.
1125 The MODE argument is the machine mode for the MEM expression
1126 that wants to use this address.
1128 When generating PIC, an address involving a SYMBOL_REF is legitimate
1129 if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF.
1130 We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses,
1131 and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF.
1133 Likewise for a LABEL_REF when generating PIC.
1135 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1137 /* Allow SUBREG everywhere we allow REG. This results in better code. It
1138 also makes function inlining work when inline functions are called with
1139 arguments that are SUBREGs. */
1141 #define LEGITIMATE_BASE_REG_P(X) \
1142 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1143 || (GET_CODE (X) == SUBREG \
1144 && GET_CODE (SUBREG_REG (X)) == REG \
1145 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1147 #define INDIRECTABLE_1_ADDRESS_P(X) \
1148 ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \
1149 || LEGITIMATE_BASE_REG_P (X) \
1150 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
1151 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
1152 || (GET_CODE (X) == PLUS \
1153 && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
1154 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1156 || ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) \
1157 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1158 && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \
1159 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1160 && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF))
1162 #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
1163 { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
1165 /* Only labels on dispatch tables are valid for indexing from. */
1166 #define GO_IF_INDEXABLE_BASE(X, ADDR) \
1168 if (GET_CODE (X) == LABEL_REF \
1169 && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \
1170 && GET_CODE (temp) == JUMP_INSN \
1171 && (GET_CODE (PATTERN (temp)) == ADDR_VEC \
1172 || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \
1174 if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; }
1176 #define GO_IF_INDEXING(X, ADDR) \
1177 { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
1178 { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
1179 if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
1180 { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
1182 #define GO_IF_INDEXED_ADDRESS(X, ADDR) \
1183 { GO_IF_INDEXING (X, ADDR); \
1184 if (GET_CODE (X) == PLUS) \
1185 { if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1186 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)) \
1187 { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \
1188 if (GET_CODE (XEXP (X, 0)) == CONST_INT \
1189 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)) \
1190 { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
1192 /* coldfire/5200 does not allow HImode index registers. */
1193 #define LEGITIMATE_INDEX_REG_P(X) \
1194 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1195 || (! TARGET_COLDFIRE \
1196 && GET_CODE (X) == SIGN_EXTEND \
1197 && GET_CODE (XEXP (X, 0)) == REG \
1198 && GET_MODE (XEXP (X, 0)) == HImode \
1199 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
1200 || (GET_CODE (X) == SUBREG \
1201 && GET_CODE (SUBREG_REG (X)) == REG \
1202 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1204 #define LEGITIMATE_INDEX_P(X) \
1205 (LEGITIMATE_INDEX_REG_P (X) \
1206 || ((TARGET_68020 || TARGET_COLDFIRE) && GET_CODE (X) == MULT \
1207 && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
1208 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1209 && (INTVAL (XEXP (X, 1)) == 2 \
1210 || INTVAL (XEXP (X, 1)) == 4 \
1211 || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_COLDFIRE))))
1213 /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */
1214 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1215 { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
1216 GO_IF_INDEXED_ADDRESS (X, ADDR); \
1217 if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \
1218 && LEGITIMATE_INDEX_P (XEXP (X, 0)) \
1219 && GET_CODE (XEXP (X, 1)) == LABEL_REF) \
1222 /* Don't call memory_address_noforce for the address to fetch
1223 the switch offset. This address is ok as it stands (see above),
1224 but memory_address_noforce would alter it. */
1225 #define PIC_CASE_VECTOR_ADDRESS(index) index
1227 /* Try machine-dependent ways of modifying an illegitimate address
1228 to be legitimate. If we find one, return the new, valid address.
1229 This macro is used in only one place: `memory_address' in explow.c.
1231 OLDX is the address as it was before break_out_memory_refs was called.
1232 In some cases it is useful to look at this to decide what needs to be done.
1234 MODE and WIN are passed so that this macro can use
1235 GO_IF_LEGITIMATE_ADDRESS.
1237 It is always safe for this macro to do nothing. It exists to recognize
1238 opportunities to optimize the output.
1240 For the 68000, we handle X+REG by loading X into a register R and
1241 using R+REG. R will go in an address reg and indexing will be used.
1242 However, if REG is a broken-out memory address or multiplication,
1243 nothing needs to be done because REG can certainly go in an address reg. */
1245 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1246 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1247 { register int ch = (X) != (OLDX); \
1248 if (GET_CODE (X) == PLUS) \
1250 if (GET_CODE (XEXP (X, 0)) == MULT) \
1251 { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \
1252 if (GET_CODE (XEXP (X, 1)) == MULT) \
1253 { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \
1254 if (ch && GET_CODE (XEXP (X, 1)) == REG \
1255 && GET_CODE (XEXP (X, 0)) == REG) \
1257 if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
1258 if (GET_CODE (XEXP (X, 0)) == REG \
1259 || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
1260 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1261 && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
1262 { register rtx temp = gen_reg_rtx (Pmode); \
1263 register rtx val = force_operand (XEXP (X, 1), 0); \
1264 emit_move_insn (temp, val); \
1266 XEXP (X, 1) = temp; \
1268 else if (GET_CODE (XEXP (X, 1)) == REG \
1269 || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
1270 && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
1271 && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
1272 { register rtx temp = gen_reg_rtx (Pmode); \
1273 register rtx val = force_operand (XEXP (X, 0), 0); \
1274 emit_move_insn (temp, val); \
1276 XEXP (X, 0) = temp; \
1279 /* Go to LABEL if ADDR (a legitimate address expression)
1280 has an effect that depends on the machine mode it is used for.
1281 On the 68000, only predecrement and postincrement address depend thus
1282 (the amount of decrement or increment being the length of the operand). */
1284 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1285 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL
1287 /* Specify the machine mode that this machine uses
1288 for the index in the tablejump instruction. */
1289 #define CASE_VECTOR_MODE HImode
1291 /* Define as C expression which evaluates to nonzero if the tablejump
1292 instruction expects the table to contain offsets from the address of the
1294 Do not define this if the table should contain absolute addresses. */
1295 #define CASE_VECTOR_PC_RELATIVE 1
1297 /* Define this as 1 if `char' should by default be signed; else as 0. */
1298 #define DEFAULT_SIGNED_CHAR 1
1300 /* Don't cse the address of the function being compiled. */
1301 #define NO_RECURSIVE_FUNCTION_CSE
1303 /* Max number of bytes we can move from memory to memory
1304 in one reasonably fast instruction. */
1307 /* Nonzero if access to memory by bytes is slow and undesirable. */
1308 #define SLOW_BYTE_ACCESS 0
1310 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1311 is done just by pretending it is already truncated. */
1312 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1314 /* We assume that the store-condition-codes instructions store 0 for false
1315 and some other value for true. This is the value stored for true. */
1317 #define STORE_FLAG_VALUE (-1)
1319 /* When a prototype says `char' or `short', really pass an `int'. */
1320 #define PROMOTE_PROTOTYPES 1
1322 /* Specify the machine mode that pointers have.
1323 After generation of rtl, the compiler makes no further distinction
1324 between pointers and any other objects of this machine mode. */
1325 #define Pmode SImode
1327 /* A function address in a call instruction
1328 is a byte address (for indexing purposes)
1329 so give the MEM rtx a byte's mode. */
1330 #define FUNCTION_MODE QImode
1333 /* Tell final.c how to eliminate redundant test instructions. */
1335 /* Here we define machine-dependent flags and fields in cc_status
1336 (see `conditions.h'). */
1338 /* Set if the cc value is actually in the 68881, so a floating point
1339 conditional branch must be output. */
1340 #define CC_IN_68881 04000
1342 /* Store in cc_status the expressions that the condition codes will
1343 describe after execution of an instruction whose pattern is EXP.
1344 Do not alter them if the instruction would not alter the cc's. */
1346 /* On the 68000, all the insns to store in an address register fail to
1347 set the cc's. However, in some cases these instructions can make it
1348 possibly invalid to use the saved cc's. In those cases we clear out
1349 some or all of the saved cc's so they won't be used. */
1351 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
1353 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
1354 { if (cc_prev_status.flags & CC_IN_68881) \
1356 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
1360 /* Control the assembler format that we output. */
1362 /* Output to assembler file text saying following lines
1363 may contain character constants, extra white space, comments, etc. */
1365 #define ASM_APP_ON "#APP\n"
1367 /* Output to assembler file text saying following lines
1368 no longer contain unusual constructs. */
1370 #define ASM_APP_OFF "#NO_APP\n"
1372 /* Output before read-only data. */
1374 #define TEXT_SECTION_ASM_OP "\t.text"
1376 /* Output before writable data. */
1378 #define DATA_SECTION_ASM_OP "\t.data"
1380 #define GLOBAL_ASM_OP "\t.globl\t"
1382 /* Here are four prefixes that are used by asm_fprintf to
1383 facilitate customization for alternate assembler syntaxes.
1384 Machines with no likelihood of an alternate syntax need not
1385 define these and need not use asm_fprintf. */
1387 /* The prefix for register names. Note that REGISTER_NAMES
1388 is supposed to include this prefix. */
1390 #define REGISTER_PREFIX ""
1392 /* The prefix for local labels. You should be able to define this as
1393 an empty string, or any arbitrary string (such as ".", ".L%", etc)
1394 without having to make any other changes to account for the specific
1395 definition. Note it is a string literal, not interpreted by printf
1398 #define LOCAL_LABEL_PREFIX ""
1400 /* The prefix to add to user-visible assembler symbols. */
1402 #define USER_LABEL_PREFIX "_"
1404 /* The prefix for immediate operands. */
1406 #define IMMEDIATE_PREFIX "#"
1408 /* How to refer to registers in assembler output.
1409 This sequence is indexed by compiler's hard-register-number (see above). */
1411 #define REGISTER_NAMES \
1412 {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \
1413 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \
1414 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", "argptr" }
1416 /* How to renumber registers for dbx and gdb.
1417 On the Sun-3, the floating point registers have numbers
1418 18 to 25, not 16 to 23 as they do in the compiler. */
1420 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
1422 /* Before the prologue, RA is at 0(%sp). */
1423 #define INCOMING_RETURN_ADDR_RTX \
1424 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
1426 /* We must not use the DBX register numbers for the DWARF 2 CFA column
1427 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
1428 Instead use the identity mapping. */
1429 #define DWARF_FRAME_REGNUM(REG) REG
1431 /* Before the prologue, the top of the frame is at 4(%sp). */
1432 #define INCOMING_FRAME_SP_OFFSET 4
1434 /* Describe how we implement __builtin_eh_return. */
1435 #define EH_RETURN_DATA_REGNO(N) \
1436 ((N) < 2 ? (N) : INVALID_REGNUM)
1437 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 8)
1438 #define EH_RETURN_HANDLER_RTX \
1439 gen_rtx_MEM (Pmode, \
1440 gen_rtx_PLUS (Pmode, arg_pointer_rtx, \
1441 plus_constant (EH_RETURN_STACKADJ_RTX, \
1444 /* Select a format to encode pointers in exception handling data. CODE
1445 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1446 true if the symbol may be affected by dynamic relocations. */
1447 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
1449 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
1452 /* This is how to output a reference to a user-level label named NAME.
1453 `assemble_name' uses this. */
1455 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1456 asm_fprintf (FILE, "%U%s", NAME)
1458 /* This is how to store into the string LABEL
1459 the symbol_ref name of an internal numbered label where
1460 PREFIX is the class of label and NUM is the number within the class.
1461 This is suitable for output with `assemble_name'. */
1463 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1464 sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM))
1466 /* This is how to output an insn to push a register on the stack.
1467 It need not be very fast code. */
1469 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1470 asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO])
1472 /* This is how to output an insn to pop a register from the stack.
1473 It need not be very fast code. */
1475 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1476 asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO])
1478 /* This is how to output an element of a case-vector that is absolute.
1479 (The 68000 does not use such vectors,
1480 but we must define this macro anyway.) */
1482 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1483 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE)
1485 /* This is how to output an element of a case-vector that is relative. */
1487 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1488 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL)
1490 /* This is how to output an assembler line
1491 that says to advance the location counter
1492 to a multiple of 2**LOG bytes. */
1494 /* We don't have a way to align to more than a two-byte boundary, so do the
1495 best we can and don't complain. */
1496 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1498 fprintf (FILE, "\t.even\n");
1500 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1501 fprintf (FILE, "\t.skip %u\n", (int)(SIZE))
1503 /* This says how to output an assembler line
1504 to define a global common symbol. */
1506 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1507 ( fputs (".comm ", (FILE)), \
1508 assemble_name ((FILE), (NAME)), \
1509 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
1511 /* This says how to output an assembler line
1512 to define a local common symbol. */
1514 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1515 ( fputs (".lcomm ", (FILE)), \
1516 assemble_name ((FILE), (NAME)), \
1517 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
1519 /* Output a float value (represented as a C double) as an immediate operand.
1520 This macro is a 68k-specific macro. */
1522 #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
1527 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 9, 0); \
1528 asm_fprintf ((FILE), "%I0r%s", dstr); \
1533 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1534 asm_fprintf ((FILE), "%I0x%lx", l); \
1538 /* Output a double value (represented as a C double) as an immediate operand.
1539 This macro is a 68k-specific macro. */
1540 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
1541 do { char dstr[30]; \
1542 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1543 asm_fprintf (FILE, "%I0r%s", dstr); \
1546 /* Note, long double immediate operands are not actually
1547 generated by m68k.md. */
1548 #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \
1549 do { char dstr[30]; \
1550 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1551 asm_fprintf (FILE, "%I0r%s", dstr); \
1554 /* Print operand X (an rtx) in assembler syntax to file FILE.
1555 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1556 For `%' followed by punctuation, CODE is the punctuation and X is null.
1558 On the 68000, we use several CODE characters:
1559 '.' for dot needed in Motorola-style opcode names.
1560 '-' for an operand pushing on the stack:
1561 sp@-, -(sp) or -(%sp) depending on the style of syntax.
1562 '+' for an operand pushing on the stack:
1563 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
1564 '@' for a reference to the top word on the stack:
1565 sp@, (sp) or (%sp) depending on the style of syntax.
1566 '#' for an immediate operand prefix (# in MIT and Motorola syntax
1567 but & in SGS syntax).
1568 '!' for the fpcr register (used in some float-to-fixed conversions).
1569 '$' for the letter `s' in an op code, but only on the 68040.
1570 '&' for the letter `d' in an op code, but only on the 68040.
1571 '/' for register prefix needed by longlong.h.
1573 'b' for byte insn (no effect, on the Sun; this is for the ISI).
1574 'd' to force memory addressing to be absolute, not relative.
1575 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1576 'o' for operands to go directly to output_operand_address (bypassing
1577 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
1578 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
1579 or print pair of registers as rx:ry. */
1581 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1582 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
1583 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \
1584 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/')
1586 /* A C compound statement to output to stdio stream STREAM the
1587 assembler syntax for an instruction operand X. X is an RTL
1590 CODE is a value that can be used to specify one of several ways
1591 of printing the operand. It is used when identical operands
1592 must be printed differently depending on the context. CODE
1593 comes from the `%' specification that was used to request
1594 printing of the operand. If the specification was just `%DIGIT'
1595 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
1596 is the ASCII code for LTR.
1598 If X is a register, this macro should print the register's name.
1599 The names can be found in an array `reg_names' whose type is
1600 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
1602 When the machine description has a specification `%PUNCT' (a `%'
1603 followed by a punctuation character), this macro is called with
1604 a null pointer for X and the punctuation character for CODE.
1606 See m68k.c for the m68k specific codes. */
1608 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1610 /* A C compound statement to output to stdio stream STREAM the
1611 assembler syntax for an instruction operand that is a memory
1612 reference whose address is ADDR. ADDR is an RTL expression. */
1614 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1616 /* Variables in m68k.c */
1617 extern const char *m68k_align_loops_string;
1618 extern const char *m68k_align_jumps_string;
1619 extern const char *m68k_align_funcs_string;
1620 extern int m68k_align_loops;
1621 extern int m68k_align_jumps;
1622 extern int m68k_align_funcs;
1623 extern int m68k_last_compare_had_fp_operands;
1626 /* Define the codes that are matched by predicates in m68k.c. */
1628 #define PREDICATE_CODES \
1629 {"general_src_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
1630 LABEL_REF, SUBREG, REG, MEM}}, \
1631 {"nonimmediate_src_operand", {SUBREG, REG, MEM}}, \
1632 {"memory_src_operand", {SUBREG, MEM}}, \
1633 {"not_sp_operand", {SUBREG, REG, MEM}}, \
1634 {"pcrel_address", {SYMBOL_REF, LABEL_REF, CONST}}, \
1635 {"const_uint32_operand", {CONST_INT, CONST_DOUBLE}}, \
1636 {"const_sint32_operand", {CONST_INT}}, \
1637 {"valid_dbcc_comparison_p", {EQ, NE, GTU, LTU, GEU, LEU, \
1639 {"extend_operator", {SIGN_EXTEND, ZERO_EXTEND}},