1 /* Definitions of target machine for GCC for Motorola 680x0/ColdFire.
2 Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
22 /* We need to have MOTOROLA always defined (either 0 or 1) because we use
23 if-statements and ?: on it. This way we have compile-time error checking
24 for both the MOTOROLA and MIT code paths. We do rely on the host compiler
25 to optimize away all constant tests. */
28 # define MOTOROLA 1 /* Use the Motorola assembly syntax. */
29 # define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)")
31 # define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)")
32 # define MOTOROLA 0 /* Use the MIT assembly syntax. */
35 /* Note that some other tm.h files include this one and then override
36 many of the definitions that relate to assembler syntax. */
38 #define TARGET_CPU_CPP_BUILTINS() \
41 builtin_define ("__m68k__"); \
42 builtin_define_std ("mc68000"); \
43 if (TARGET_68040_ONLY) \
46 builtin_define_std ("mc68060"); \
48 builtin_define_std ("mc68040"); \
50 else if (TUNE_68060) /* -m68020-60 */ \
52 builtin_define_std ("mc68060"); \
53 builtin_define_std ("mc68040"); \
54 builtin_define_std ("mc68030"); \
55 builtin_define_std ("mc68020"); \
57 else if (TUNE_68040) /* -m68020-40 */ \
59 builtin_define_std ("mc68040"); \
60 builtin_define_std ("mc68030"); \
61 builtin_define_std ("mc68020"); \
63 else if (TUNE_68030) \
64 builtin_define_std ("mc68030"); \
65 else if (TARGET_68020) \
66 builtin_define_std ("mc68020"); \
68 builtin_define ("__HAVE_68881__"); \
71 builtin_define_std ("mc68332"); \
72 builtin_define_std ("mcpu32"); \
74 if (TARGET_COLDFIRE) \
75 builtin_define ("__mcoldfire__"); \
77 builtin_define ("__mcf5200__"); \
80 builtin_define ("__mcf528x__"); \
81 builtin_define ("__mcf5200__"); \
85 builtin_define ("__mcf5300__"); \
86 builtin_define ("__mcf5307__"); \
90 builtin_define ("__mcf5400__"); \
91 builtin_define ("__mcf5407__"); \
95 builtin_define ("__mcfv4e__"); \
97 if (TARGET_CF_HWDIV) \
98 builtin_define ("__mcfhwdiv__"); \
99 builtin_assert ("cpu=m68k"); \
100 builtin_assert ("machine=m68k"); \
104 /* Classify the groups of pseudo-ops used to assemble QI, HI and SI
106 #define INT_OP_STANDARD 0 /* .byte, .short, .long */
107 #define INT_OP_DOT_WORD 1 /* .byte, .word, .long */
108 #define INT_OP_NO_DOT 2 /* byte, short, long */
109 #define INT_OP_DC 3 /* dc.b, dc.w, dc.l */
111 /* Set the default. */
112 #define INT_OP_GROUP INT_OP_DOT_WORD
114 /* Compile for a CPU32. A 68020 without bitfields is a good
115 heuristic for a CPU32. */
116 #define TUNE_CPU32 (TARGET_68020 && !TARGET_BITFIELD)
118 /* Is the target a ColdFire? */
119 #define MASK_COLDFIRE \
120 (MASK_5200 | MASK_528x | MASK_CFV3 | MASK_CFV4 | MASK_CFV4E)
121 #define TARGET_COLDFIRE ((target_flags & MASK_COLDFIRE) != 0)
123 #define TARGET_COLDFIRE_FPU TARGET_CFV4E
125 #define TARGET_HARD_FLOAT (TARGET_68881 || TARGET_COLDFIRE_FPU)
126 /* Size (in bytes) of FPU registers. */
127 #define TARGET_FP_REG_SIZE (TARGET_COLDFIRE ? 8 : 12)
129 #define TUNE_68000_10 (!TARGET_68020 && !TARGET_COLDFIRE)
130 #define TUNE_68030 TARGET_68030
131 #define TUNE_68040 TARGET_68040
132 #define TUNE_68060 TARGET_68060
133 #define TUNE_68040_60 (TUNE_68040 || TUNE_68060)
134 #define TUNE_CFV2 TARGET_5200
136 #define OVERRIDE_OPTIONS override_options()
138 /* These are meant to be redefined in the host dependent files */
139 #define SUBTARGET_OVERRIDE_OPTIONS
141 /* target machine storage layout */
143 #define LONG_DOUBLE_TYPE_SIZE 80
145 /* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
146 instructions, we get proper intermediate rounding, otherwise we
147 get extended precision results. */
148 #define TARGET_FLT_EVAL_METHOD ((TARGET_68040_ONLY || ! TARGET_68881) ? 0 : 2)
150 #define BITS_BIG_ENDIAN 1
151 #define BYTES_BIG_ENDIAN 1
152 #define WORDS_BIG_ENDIAN 1
154 #define UNITS_PER_WORD 4
156 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
157 #define STACK_BOUNDARY 16
158 #define FUNCTION_BOUNDARY 16
159 #define EMPTY_FIELD_BOUNDARY 16
161 /* No data type wants to be aligned rounder than this.
162 Most published ABIs say that ints should be aligned on 16 bit
163 boundaries, but CPUs with 32-bit busses get better performance
164 aligned on 32-bit boundaries. ColdFires without a misalignment
165 module require 32-bit alignment. */
166 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
168 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT)
170 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
172 /* Define these to avoid dependence on meaning of `int'. */
173 #define WCHAR_TYPE "long int"
174 #define WCHAR_TYPE_SIZE 32
176 /* Maximum number of library IDs we permit with -mid-shared-library. */
177 #define MAX_LIBRARY_ID 255
180 /* Standard register usage. */
182 /* For the m68k, we give the data registers numbers 0-7,
183 the address registers numbers 010-017 (8-15),
184 and the 68881 floating point registers numbers 020-027 (16-24).
185 We also have a fake `arg-pointer' register 030 (25) used for
186 register elimination. */
187 #define FIRST_PSEUDO_REGISTER 25
189 /* All m68k targets (except AmigaOS) use %a5 as the PIC register */
190 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 13 : INVALID_REGNUM)
192 /* 1 for registers that have pervasive standard uses
193 and are not available for the register allocator.
194 On the m68k, only the stack pointer is such.
195 Our fake arg-pointer is obviously fixed as well. */
196 #define FIXED_REGISTERS \
197 {/* Data registers. */ \
198 0, 0, 0, 0, 0, 0, 0, 0, \
200 /* Address registers. */ \
201 0, 0, 0, 0, 0, 0, 0, 1, \
203 /* Floating point registers \
205 0, 0, 0, 0, 0, 0, 0, 0, \
210 /* 1 for registers not available across function calls.
211 These must include the FIXED_REGISTERS and also any
212 registers that can be used without being saved.
213 The latter must include the registers where values are returned
214 and the register where structure-value addresses are passed.
215 Aside from that, you can include as many other registers as you like. */
216 #define CALL_USED_REGISTERS \
217 {/* Data registers. */ \
218 1, 1, 0, 0, 0, 0, 0, 0, \
220 /* Address registers. */ \
221 1, 1, 0, 0, 0, 0, 0, 1, \
223 /* Floating point registers \
225 1, 1, 0, 0, 0, 0, 0, 0, \
230 #define REG_ALLOC_ORDER \
231 { /* d0/d1/a0/a1 */ \
236 10, 11, 12, 13, 14, 15, 24, \
238 16, 17, 18, 19, 20, 21, 22, 23\
242 /* Make sure everything's fine if we *don't* have a given processor.
243 This assumes that putting a register in fixed_regs will keep the
244 compiler's mitts completely off it. We don't bother to zero it out
245 of register classes. */
246 #define CONDITIONAL_REGISTER_USAGE \
250 if (!TARGET_HARD_FLOAT) \
252 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
253 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
254 if (TEST_HARD_REG_BIT (x, i)) \
255 fixed_regs[i] = call_used_regs[i] = 1; \
257 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
258 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
259 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
262 /* On the m68k, ordinary registers hold 32 bits worth;
263 for the 68881 registers, a single register is always enough for
264 anything that can be stored in them at all. */
265 #define HARD_REGNO_NREGS(REGNO, MODE) \
266 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
267 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
269 /* A C expression that is nonzero if hard register NEW_REG can be
270 considered for use as a rename register for OLD_REG register. */
272 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
273 m68k_hard_regno_rename_ok (OLD_REG, NEW_REG)
275 /* Value is true if hard register REGNO can hold a value of machine-mode MODE.
276 On the 68000, the cpu registers can hold any mode except bytes in
277 address registers, the 68881 registers can hold only SFmode or DFmode. */
279 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
280 m68k_regno_mode_ok ((REGNO), (MODE))
282 #define MODES_TIEABLE_P(MODE1, MODE2) \
283 (! TARGET_HARD_FLOAT \
284 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
285 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
286 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
287 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
289 /* Specify the registers used for certain standard purposes.
290 The values of these macros are register numbers. */
292 #define STACK_POINTER_REGNUM 15
294 /* Most m68k targets use %a6 as a frame pointer. The AmigaOS
295 ABI uses %a6 for shared library calls, therefore the frame
296 pointer is shifted to %a5 on this target. */
297 #define FRAME_POINTER_REGNUM 14
299 #define FRAME_POINTER_REQUIRED 0
301 /* Base register for access to arguments of the function.
302 * This isn't a hardware register. It will be eliminated to the
303 * stack pointer or frame pointer.
305 #define ARG_POINTER_REGNUM 24
307 #define STATIC_CHAIN_REGNUM 8
309 /* Register in which address to store a structure value
310 is passed to a function. */
311 #define M68K_STRUCT_VALUE_REGNUM 9
315 /* The m68k has three kinds of registers, so eight classes would be
316 a complete set. One of them is not needed. */
320 GENERAL_REGS, DATA_OR_FP_REGS,
321 ADDR_OR_FP_REGS, ALL_REGS,
324 #define N_REG_CLASSES (int) LIM_REG_CLASSES
326 #define REG_CLASS_NAMES \
327 { "NO_REGS", "DATA_REGS", \
328 "ADDR_REGS", "FP_REGS", \
329 "GENERAL_REGS", "DATA_OR_FP_REGS", \
330 "ADDR_OR_FP_REGS", "ALL_REGS" }
332 #define REG_CLASS_CONTENTS \
334 {0x00000000}, /* NO_REGS */ \
335 {0x000000ff}, /* DATA_REGS */ \
336 {0x0100ff00}, /* ADDR_REGS */ \
337 {0x00ff0000}, /* FP_REGS */ \
338 {0x0100ffff}, /* GENERAL_REGS */ \
339 {0x00ff00ff}, /* DATA_OR_FP_REGS */ \
340 {0x01ffff00}, /* ADDR_OR_FP_REGS */ \
341 {0x01ffffff}, /* ALL_REGS */ \
344 extern enum reg_class regno_reg_class[];
345 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)])
346 #define INDEX_REG_CLASS GENERAL_REGS
347 #define BASE_REG_CLASS ADDR_REGS
349 /* We do a trick here to modify the effective constraints on the
350 machine description; we zorch the constraint letters that aren't
351 appropriate for a specific target. This allows us to guarantee
352 that a specific kind of register will not be used for a given target
353 without fiddling with the register classes above. */
354 #define REG_CLASS_FROM_LETTER(C) \
355 ((C) == 'a' ? ADDR_REGS : \
356 ((C) == 'd' ? DATA_REGS : \
357 ((C) == 'f' ? (TARGET_HARD_FLOAT ? \
358 FP_REGS : NO_REGS) : \
361 /* For the m68k, `I' is used for the range 1 to 8
362 allowed as immediate shift counts and in addq.
363 `J' is used for the range of signed numbers that fit in 16 bits.
364 `K' is for numbers that moveq can't handle.
365 `L' is for range -8 to -1, range of values that can be added with subq.
366 `M' is for numbers that moveq+notb can't handle.
367 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate.
368 'O' is for 16 (for rotate using swap).
369 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */
370 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
371 ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \
372 (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
373 (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
374 (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \
375 (C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \
376 (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \
377 (C) == 'O' ? (VALUE) == 16 : \
378 (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0)
380 /* "G" defines all of the floating constants that are *NOT* 68881
381 constants. This is so 68881 constants get reloaded and the
383 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
384 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 )
386 /* `Q' means address register indirect addressing mode.
387 `S' is for operands that satisfy 'm' when -mpcrel is in effect.
388 `T' is for operands that satisfy 's' when -mpcrel is not in effect.
389 `U' is for register offset addressing. */
390 #define EXTRA_CONSTRAINT(OP,CODE) \
393 && GET_CODE (OP) == MEM \
394 && (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
395 || GET_CODE (XEXP (OP, 0)) == LABEL_REF \
396 || GET_CODE (XEXP (OP, 0)) == CONST)) \
400 && (GET_CODE (OP) == SYMBOL_REF \
401 || GET_CODE (OP) == LABEL_REF \
402 || GET_CODE (OP) == CONST)) \
405 ? (GET_CODE (OP) == MEM \
406 && GET_CODE (XEXP (OP, 0)) == REG) \
409 ? (GET_CODE (OP) == MEM \
410 && GET_CODE (XEXP (OP, 0)) == PLUS \
411 && GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG \
412 && GET_CODE (XEXP (XEXP (OP, 0), 1)) == CONST_INT) \
416 /* On the m68k, use a data reg if possible when the
417 value is a constant in the range where moveq could be used
418 and we ensure that QImodes are reloaded into data regs. */
419 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
420 ((GET_CODE (X) == CONST_INT \
421 && (unsigned) (INTVAL (X) + 0x80) < 0x100 \
422 && (CLASS) != ADDR_REGS) \
424 : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \
426 : (GET_CODE (X) == CONST_DOUBLE \
427 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
428 ? (TARGET_HARD_FLOAT && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \
429 ? FP_REGS : NO_REGS) \
431 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
432 || GET_CODE (X) == LABEL_REF)) \
436 /* Force QImode output reloads from subregs to be allocated to data regs,
437 since QImode stores from address regs are not supported. We make the
438 assumption that if the class is not ADDR_REGS, then it must be a superset
440 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
441 (((MODE) == QImode && (CLASS) != ADDR_REGS) \
445 /* On the m68k, this is the size of MODE in words,
446 except in the FP regs, where a single reg is always enough. */
447 #define CLASS_MAX_NREGS(CLASS, MODE) \
448 ((CLASS) == FP_REGS ? 1 \
449 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
451 /* Moves between fp regs and other regs are two insns. */
452 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
453 (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
454 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
457 /* Stack layout; function entry, exit and calling. */
459 #define STACK_GROWS_DOWNWARD
460 #define FRAME_GROWS_DOWNWARD 1
461 #define STARTING_FRAME_OFFSET 0
463 /* On the 680x0, sp@- in a byte insn really pushes a word.
464 On the ColdFire, sp@- in a byte insn pushes just a byte. */
465 #define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1)
467 #define FIRST_PARM_OFFSET(FNDECL) 8
469 /* On the 68000, the RTS insn cannot pop anything.
470 On the 68010, the RTD insn may be used to pop them if the number
471 of args is fixed, but if the number is variable then the caller
472 must pop them all. RTD can't be used for library calls now
473 because the library is compiled with the Unix compiler.
474 Use of RTD is a selectable option, since it is incompatible with
475 standard Unix calling sequences. If the option is not selected,
476 the caller must always pop the args. */
477 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
478 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \
479 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
480 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
481 == void_type_node))) \
484 /* On the m68k the return value is always in D0. */
485 #define FUNCTION_VALUE(VALTYPE, FUNC) \
486 gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
488 /* On the m68k the return value is always in D0. */
489 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
491 /* On the m68k, D0 is the only register used. */
492 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
494 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
495 more than one register.
496 XXX This macro is m68k specific and used only for m68kemb.h. */
497 #define NEEDS_UNTYPED_CALL 0
499 #define PCC_STATIC_STRUCT_RETURN
501 /* On the m68k, all arguments are usually pushed on the stack. */
502 #define FUNCTION_ARG_REGNO_P(N) 0
504 /* On the m68k, this is a single integer, which is a number of bytes
505 of arguments scanned so far. */
506 #define CUMULATIVE_ARGS int
508 /* On the m68k, the offset starts at 0. */
509 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
512 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
513 ((CUM) += ((MODE) != BLKmode \
514 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
515 : (int_size_in_bytes (TYPE) + 3) & ~3))
517 /* On the m68k all args are always pushed. */
518 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
520 #define FUNCTION_PROFILER(FILE, LABELNO) \
521 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO))
523 #define EXIT_IGNORE_STACK 1
525 /* Determine if the epilogue should be output as RTL.
526 You should override this if you define FUNCTION_EXTRA_EPILOGUE.
528 XXX This macro is m68k-specific and only used in m68k.md. */
529 #define USE_RETURN_INSN use_return_insn ()
531 /* Output assembler code for a block containing the constant parts
532 of a trampoline, leaving space for the variable parts.
534 On the m68k, the trampoline looks like this:
538 WARNING: Targets that may run on 68040+ cpus must arrange for
539 the instruction cache to be flushed. Previous incarnations of
540 the m68k trampoline code attempted to get around this by either
541 using an out-of-line transfer function or pc-relative data, but
542 the fact remains that the code to jump to the transfer function
543 or the code to load the pc-relative data needs to be flushed
544 just as much as the "variable" portion of the trampoline.
545 Recognizing that a cache flush is going to be required anyway,
546 dispense with such notions and build a smaller trampoline.
548 Since more instructions are required to move a template into
549 place than to create it on the spot, don't use a template. */
551 #define TRAMPOLINE_SIZE 12
552 #define TRAMPOLINE_ALIGNMENT 16
554 /* Targets redefine this to invoke code to either flush the cache,
555 or enable stack execution (or both). */
556 #ifndef FINALIZE_TRAMPOLINE
557 #define FINALIZE_TRAMPOLINE(TRAMP)
560 /* We generate a two-instructions program at address TRAMP :
563 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
565 emit_move_insn (gen_rtx_MEM (HImode, TRAMP), GEN_INT(0x207C)); \
566 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \
567 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \
569 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \
570 FINALIZE_TRAMPOLINE(TRAMP); \
573 /* This is the library routine that is used to transfer control from the
574 trampoline to the actual nested function. It is defined for backward
575 compatibility, for linking with object code that used the old trampoline
578 A colon is used with no explicit operands to cause the template string
579 to be scanned for %-constructs.
581 The function name __transfer_from_trampoline is not actually used.
582 The function definition just permits use of "asm with operands"
583 (though the operand list is empty). */
584 #define TRANSFER_FROM_TRAMPOLINE \
586 __transfer_from_trampoline () \
588 register char *a0 asm ("%a0"); \
589 asm (GLOBAL_ASM_OP "___trampoline"); \
590 asm ("___trampoline:"); \
591 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \
592 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \
596 /* There are two registers that can always be eliminated on the m68k.
597 The frame pointer and the arg pointer can be replaced by either the
598 hard frame pointer or to the stack pointer, depending upon the
599 circumstances. The hard frame pointer is not used before reload and
600 so it is not eligible for elimination. */
601 #define ELIMINABLE_REGS \
602 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
603 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
604 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
606 #define CAN_ELIMINATE(FROM, TO) \
607 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
609 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
610 (OFFSET) = m68k_initial_elimination_offset(FROM, TO)
612 /* Addressing modes, and classification of registers for them. */
614 #define HAVE_POST_INCREMENT 1
615 #define HAVE_PRE_DECREMENT 1
617 /* Macros to check register numbers against specific register classes. */
619 #define REGNO_OK_FOR_INDEX_P(REGNO) \
620 ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
621 #define REGNO_OK_FOR_BASE_P(REGNO) \
622 (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
623 #define REGNO_OK_FOR_DATA_P(REGNO) \
624 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
625 #define REGNO_OK_FOR_FP_P(REGNO) \
626 (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
628 /* Now macros that check whether X is a register and also,
629 strictly, whether it is in a specified class.
631 These macros are specific to the m68k, and may be used only
632 in code for printing assembler insns and in conditions for
633 define_optimization. */
635 /* 1 if X is a data register. */
636 #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
638 /* 1 if X is an fp register. */
639 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
641 /* 1 if X is an address register */
642 #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
645 #define MAX_REGS_PER_ADDRESS 2
647 #define CONSTANT_ADDRESS_P(X) \
648 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
649 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
650 || GET_CODE (X) == HIGH)
652 /* Nonzero if the constant value X is a legitimate general operand.
653 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
654 #define LEGITIMATE_CONSTANT_P(X) (GET_MODE (X) != XFmode)
656 #ifndef REG_OK_STRICT
657 #define PCREL_GENERAL_OPERAND_OK 0
659 #define PCREL_GENERAL_OPERAND_OK (TARGET_PCREL)
662 #define LEGITIMATE_PIC_OPERAND_P(X) \
663 (! symbolic_operand (X, VOIDmode) \
664 || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \
665 || PCREL_GENERAL_OPERAND_OK)
667 #ifndef REG_OK_STRICT
669 /* Nonzero if X is a hard reg that can be used as an index
670 or if it is a pseudo reg. */
671 #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
672 /* Nonzero if X is a hard reg that can be used as a base reg
673 or if it is a pseudo reg. */
674 #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
678 /* Nonzero if X is a hard reg that can be used as an index. */
679 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
680 /* Nonzero if X is a hard reg that can be used as a base reg. */
681 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
685 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
686 that is a valid memory address for an instruction.
687 The MODE argument is the machine mode for the MEM expression
688 that wants to use this address.
690 When generating PIC, an address involving a SYMBOL_REF is legitimate
691 if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF.
692 We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses,
693 and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF.
695 Likewise for a LABEL_REF when generating PIC.
697 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
699 /* Allow SUBREG everywhere we allow REG. This results in better code. It
700 also makes function inlining work when inline functions are called with
701 arguments that are SUBREGs. */
703 #define LEGITIMATE_BASE_REG_P(X) \
704 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
705 || (GET_CODE (X) == SUBREG \
706 && GET_CODE (SUBREG_REG (X)) == REG \
707 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
709 #define INDIRECTABLE_1_ADDRESS_P(X) \
710 ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \
711 || LEGITIMATE_BASE_REG_P (X) \
712 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
713 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
714 || (GET_CODE (X) == PLUS \
715 && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
716 && GET_CODE (XEXP (X, 1)) == CONST_INT \
718 || ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) \
719 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
720 && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \
721 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
722 && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF))
724 #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
725 { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
727 /* Only labels on dispatch tables are valid for indexing from. */
728 #define GO_IF_INDEXABLE_BASE(X, ADDR) \
730 if (GET_CODE (X) == LABEL_REF \
731 && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \
732 && GET_CODE (temp) == JUMP_INSN \
733 && (GET_CODE (PATTERN (temp)) == ADDR_VEC \
734 || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \
736 if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; }
738 #define GO_IF_INDEXING(X, ADDR) \
739 { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
740 { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
741 if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
742 { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
744 #define GO_IF_INDEXED_ADDRESS(X, ADDR) \
745 { GO_IF_INDEXING (X, ADDR); \
746 if (GET_CODE (X) == PLUS) \
747 { if (GET_CODE (XEXP (X, 1)) == CONST_INT \
748 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)) \
749 { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \
750 if (GET_CODE (XEXP (X, 0)) == CONST_INT \
751 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)) \
752 { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
754 /* ColdFire/5200 does not allow HImode index registers. */
755 #define LEGITIMATE_INDEX_REG_P(X) \
756 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
757 || (! TARGET_COLDFIRE \
758 && GET_CODE (X) == SIGN_EXTEND \
759 && GET_CODE (XEXP (X, 0)) == REG \
760 && GET_MODE (XEXP (X, 0)) == HImode \
761 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
762 || (GET_CODE (X) == SUBREG \
763 && GET_CODE (SUBREG_REG (X)) == REG \
764 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
766 #define LEGITIMATE_INDEX_P(X) \
767 (LEGITIMATE_INDEX_REG_P (X) \
768 || ((TARGET_68020 || TARGET_COLDFIRE) && GET_CODE (X) == MULT \
769 && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
770 && GET_CODE (XEXP (X, 1)) == CONST_INT \
771 && (INTVAL (XEXP (X, 1)) == 2 \
772 || INTVAL (XEXP (X, 1)) == 4 \
773 || (INTVAL (XEXP (X, 1)) == 8 \
774 && (TARGET_CFV4E || !TARGET_COLDFIRE)))))
776 /* Coldfire FPU only accepts addressing modes 2-5 */
777 #define GO_IF_COLDFIRE_FPU_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
778 { if (LEGITIMATE_BASE_REG_P (X) \
779 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
780 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
781 || ((GET_CODE (X) == PLUS) && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
782 && (GET_CODE (XEXP (X, 1)) == CONST_INT) \
783 && ((((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)))) \
786 /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */
787 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
788 { if (TARGET_COLDFIRE_FPU && (GET_MODE_CLASS (MODE) == MODE_FLOAT)) \
790 GO_IF_COLDFIRE_FPU_LEGITIMATE_ADDRESS (MODE, X, ADDR); \
794 GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
795 GO_IF_INDEXED_ADDRESS (X, ADDR); \
796 if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \
797 && LEGITIMATE_INDEX_P (XEXP (X, 0)) \
798 && GET_CODE (XEXP (X, 1)) == LABEL_REF) \
802 /* Don't call memory_address_noforce for the address to fetch
803 the switch offset. This address is ok as it stands (see above),
804 but memory_address_noforce would alter it. */
805 #define PIC_CASE_VECTOR_ADDRESS(index) index
807 /* For the 68000, we handle X+REG by loading X into a register R and
808 using R+REG. R will go in an address reg and indexing will be used.
809 However, if REG is a broken-out memory address or multiplication,
810 nothing needs to be done because REG can certainly go in an address reg. */
811 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
812 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
813 { register int ch = (X) != (OLDX); \
814 if (GET_CODE (X) == PLUS) \
816 if (GET_CODE (XEXP (X, 0)) == MULT) \
817 { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \
818 if (GET_CODE (XEXP (X, 1)) == MULT) \
819 { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \
820 if (ch && GET_CODE (XEXP (X, 1)) == REG \
821 && GET_CODE (XEXP (X, 0)) == REG) \
822 { if (TARGET_CFV4E && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
823 { COPY_ONCE (X); X = force_operand (X, 0);} \
825 if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
826 if (GET_CODE (XEXP (X, 0)) == REG \
827 || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
828 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
829 && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
830 { register rtx temp = gen_reg_rtx (Pmode); \
831 register rtx val = force_operand (XEXP (X, 1), 0); \
832 emit_move_insn (temp, val); \
834 XEXP (X, 1) = temp; \
835 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT \
836 && GET_CODE (XEXP (X, 0)) == REG) \
837 X = force_operand (X, 0); \
839 else if (GET_CODE (XEXP (X, 1)) == REG \
840 || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
841 && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
842 && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
843 { register rtx temp = gen_reg_rtx (Pmode); \
844 register rtx val = force_operand (XEXP (X, 0), 0); \
845 emit_move_insn (temp, val); \
847 XEXP (X, 0) = temp; \
848 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT \
849 && GET_CODE (XEXP (X, 1)) == REG) \
850 X = force_operand (X, 0); \
853 /* On the 68000, only predecrement and postincrement address depend thus
854 (the amount of decrement or increment being the length of the operand).
855 These are now treated generically in recog.c. */
856 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
858 #define CASE_VECTOR_MODE HImode
859 #define CASE_VECTOR_PC_RELATIVE 1
861 #define DEFAULT_SIGNED_CHAR 1
863 #define SLOW_BYTE_ACCESS 0
865 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
867 #define STORE_FLAG_VALUE (-1)
870 #define FUNCTION_MODE QImode
873 /* Tell final.c how to eliminate redundant test instructions. */
875 /* Here we define machine-dependent flags and fields in cc_status
876 (see `conditions.h'). */
878 /* Set if the cc value is actually in the 68881, so a floating point
879 conditional branch must be output. */
880 #define CC_IN_68881 04000
882 /* On the 68000, all the insns to store in an address register fail to
883 set the cc's. However, in some cases these instructions can make it
884 possibly invalid to use the saved cc's. In those cases we clear out
885 some or all of the saved cc's so they won't be used. */
886 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
888 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
889 do { if (cc_prev_status.flags & CC_IN_68881) \
891 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
893 return NORMAL; } while (0)
895 /* Control the assembler format that we output. */
897 #define ASM_APP_ON "#APP\n"
898 #define ASM_APP_OFF "#NO_APP\n"
899 #define TEXT_SECTION_ASM_OP "\t.text"
900 #define DATA_SECTION_ASM_OP "\t.data"
901 #define GLOBAL_ASM_OP "\t.globl\t"
902 #define REGISTER_PREFIX ""
903 #define LOCAL_LABEL_PREFIX ""
904 #define USER_LABEL_PREFIX "_"
905 #define IMMEDIATE_PREFIX "#"
907 #define REGISTER_NAMES \
908 {REGISTER_PREFIX"d0", REGISTER_PREFIX"d1", REGISTER_PREFIX"d2", \
909 REGISTER_PREFIX"d3", REGISTER_PREFIX"d4", REGISTER_PREFIX"d5", \
910 REGISTER_PREFIX"d6", REGISTER_PREFIX"d7", \
911 REGISTER_PREFIX"a0", REGISTER_PREFIX"a1", REGISTER_PREFIX"a2", \
912 REGISTER_PREFIX"a3", REGISTER_PREFIX"a4", REGISTER_PREFIX"a5", \
913 REGISTER_PREFIX"a6", REGISTER_PREFIX"sp", \
914 REGISTER_PREFIX"fp0", REGISTER_PREFIX"fp1", REGISTER_PREFIX"fp2", \
915 REGISTER_PREFIX"fp3", REGISTER_PREFIX"fp4", REGISTER_PREFIX"fp5", \
916 REGISTER_PREFIX"fp6", REGISTER_PREFIX"fp7", REGISTER_PREFIX"argptr" }
918 #define M68K_FP_REG_NAME REGISTER_PREFIX"fp"
920 /* Return a register name by index, handling %fp nicely.
921 We don't replace %fp for targets that don't map it to %a6
922 since it may confuse GAS. */
923 #define M68K_REGNAME(r) ( \
924 ((FRAME_POINTER_REGNUM == 14) \
925 && ((r) == FRAME_POINTER_REGNUM) \
926 && frame_pointer_needed) ? \
927 M68K_FP_REG_NAME : reg_names[(r)])
929 /* On the Sun-3, the floating point registers have numbers
930 18 to 25, not 16 to 23 as they do in the compiler. */
931 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
933 /* Before the prologue, RA is at 0(%sp). */
934 #define INCOMING_RETURN_ADDR_RTX \
935 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
937 /* After the prologue, RA is at 4(AP) in the current frame. */
938 #define RETURN_ADDR_RTX(COUNT, FRAME) \
940 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, UNITS_PER_WORD)) \
941 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
943 /* We must not use the DBX register numbers for the DWARF 2 CFA column
944 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
945 Instead use the identity mapping. */
946 #define DWARF_FRAME_REGNUM(REG) REG
948 /* Before the prologue, the top of the frame is at 4(%sp). */
949 #define INCOMING_FRAME_SP_OFFSET 4
951 /* Describe how we implement __builtin_eh_return. */
952 #define EH_RETURN_DATA_REGNO(N) \
953 ((N) < 2 ? (N) : INVALID_REGNUM)
954 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 8)
955 #define EH_RETURN_HANDLER_RTX \
956 gen_rtx_MEM (Pmode, \
957 gen_rtx_PLUS (Pmode, arg_pointer_rtx, \
958 plus_constant (EH_RETURN_STACKADJ_RTX, \
961 /* Select a format to encode pointers in exception handling data. CODE
962 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
963 true if the symbol may be affected by dynamic relocations. */
964 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
966 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
969 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
970 asm_fprintf (FILE, "%U%s", NAME)
972 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
973 sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM))
975 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
976 asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO])
977 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
978 asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO])
980 /* The m68k does not use absolute case-vectors, but we must define this macro
982 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
983 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE)
985 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
986 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL)
988 /* We don't have a way to align to more than a two-byte boundary, so do the
989 best we can and don't complain. */
990 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
992 fprintf (FILE, "\t.even\n");
994 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
995 fprintf (FILE, "\t.skip %u\n", (int)(SIZE))
997 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
998 ( fputs (".comm ", (FILE)), \
999 assemble_name ((FILE), (NAME)), \
1000 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
1002 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1003 ( fputs (".lcomm ", (FILE)), \
1004 assemble_name ((FILE), (NAME)), \
1005 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
1007 /* Output a float value (represented as a C double) as an immediate operand.
1008 This macro is m68k-specific. */
1009 #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
1014 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 9, 0); \
1015 asm_fprintf ((FILE), "%I0r%s", dstr); \
1020 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1021 asm_fprintf ((FILE), "%I0x%lx", l); \
1025 /* Output a double value (represented as a C double) as an immediate operand.
1026 This macro is m68k-specific. */
1027 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
1028 do { char dstr[30]; \
1029 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1030 asm_fprintf (FILE, "%I0r%s", dstr); \
1033 /* Note, long double immediate operands are not actually
1034 generated by m68k.md. */
1035 #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \
1036 do { char dstr[30]; \
1037 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1038 asm_fprintf (FILE, "%I0r%s", dstr); \
1041 /* On the 68000, we use several CODE characters:
1042 '.' for dot needed in Motorola-style opcode names.
1043 '-' for an operand pushing on the stack:
1044 sp@-, -(sp) or -(%sp) depending on the style of syntax.
1045 '+' for an operand pushing on the stack:
1046 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
1047 '@' for a reference to the top word on the stack:
1048 sp@, (sp) or (%sp) depending on the style of syntax.
1049 '#' for an immediate operand prefix (# in MIT and Motorola syntax
1050 but & in SGS syntax).
1051 '!' for the fpcr register (used in some float-to-fixed conversions).
1052 '$' for the letter `s' in an op code, but only on the 68040.
1053 '&' for the letter `d' in an op code, but only on the 68040.
1054 '/' for register prefix needed by longlong.h.
1056 'b' for byte insn (no effect, on the Sun; this is for the ISI).
1057 'd' to force memory addressing to be absolute, not relative.
1058 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1059 'o' for operands to go directly to output_operand_address (bypassing
1060 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
1061 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
1062 or print pair of registers as rx:ry. */
1064 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1065 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
1066 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \
1067 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/')
1070 /* See m68k.c for the m68k specific codes. */
1071 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1073 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1075 /* Variables in m68k.c */
1076 extern const char *m68k_library_id_string;
1077 extern int m68k_last_compare_had_fp_operands;