1 /* Definitions of target machine for GNU compiler.
2 Sun 68000/68020 version.
3 Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 2000, 2001, 2002 Free Software Foundation, Inc.
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 /* Note that some other tm.h files include this one and then override
25 many of the definitions that relate to assembler syntax. */
28 /* Classify the groups of pseudo-ops used to assemble QI, HI and SI
30 #define INT_OP_STANDARD 0 /* .byte, .short, .long */
31 #define INT_OP_DOT_WORD 1 /* .byte, .word, .long */
32 #define INT_OP_NO_DOT 2 /* byte, short, long */
33 #define INT_OP_DC 3 /* dc.b, dc.w, dc.l */
36 #define INT_OP_GROUP INT_OP_DOT_WORD
38 /* Names to predefine in the preprocessor for this target machine. */
40 /* See sun3.h, sun2.h, isi.h for different CPP_PREDEFINES. */
42 /* Print subsidiary information on the compiler version in use. */
44 #define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)");
46 #define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)");
49 /* Define SUPPORT_SUN_FPA to include support for generating code for
50 the Sun Floating Point Accelerator, an optional product for Sun 3
51 machines. By default, it is not defined. Avoid defining it unless
52 you need to output code for the Sun3+FPA architecture, as it has the
53 effect of slowing down the register set operations in hard-reg-set.h
54 (total number of registers will exceed number of bits in a long,
55 if defined, causing the set operations to expand to loops).
56 SUPPORT_SUN_FPA is typically defined in sun3.h. */
58 /* Run-time compilation parameters selecting different hardware subsets. */
60 extern int target_flags;
62 /* Macros used in the machine description to test the flags. */
64 /* Compile for a 68020 (not a 68000 or 68010). */
66 #define TARGET_68020 (target_flags & MASK_68020)
68 /* Compile 68881 insns for floating point (not library calls). */
70 #define TARGET_68881 (target_flags & MASK_68881)
72 /* Compile using 68020 bit-field insns. */
73 #define MASK_BITFIELD 4
74 #define TARGET_BITFIELD (target_flags & MASK_BITFIELD)
76 /* Compile using rtd insn calling sequence.
77 This will not work unless you use prototypes at least
78 for all functions that can take varying numbers of args. */
80 #define TARGET_RTD (target_flags & MASK_RTD)
82 /* Compile passing first two args in regs 0 and 1.
83 This exists only to test compiler features that will
84 be needed for RISC chips. It is not usable
85 and is not intended to be usable on this cpu. */
86 #define MASK_REGPARM 16
87 #define TARGET_REGPARM (target_flags & MASK_REGPARM)
89 /* Compile with 16-bit `int'. */
91 #define TARGET_SHORT (target_flags & MASK_SHORT)
93 /* Compile with special insns for Sun FPA. */
95 #define TARGET_FPA (target_flags & MASK_FPA)
97 /* Compile (actually, link) for Sun SKY board. */
99 #define TARGET_SKY (target_flags & MASK_SKY)
101 /* Optimize for 68040, but still allow execution on 68020
102 (-m68020-40 or -m68040).
103 The 68040 will execute all 68030 and 68881/2 instructions, but some
104 of them must be emulated in software by the OS. When TARGET_68040 is
105 turned on, these instructions won't be used. This code will still
106 run on a 68030 and 68881/2. */
107 #define MASK_68040 256
108 #define TARGET_68040 (target_flags & MASK_68040)
110 /* Use the 68040-only fp instructions (-m68040 or -m68060). */
111 #define MASK_68040_ONLY 512
112 #define TARGET_68040_ONLY (target_flags & MASK_68040_ONLY)
114 /* Optimize for 68060, but still allow execution on 68020
115 (-m68020-60 or -m68060).
116 The 68060 will execute all 68030 and 68881/2 instructions, but some
117 of them must be emulated in software by the OS. When TARGET_68060 is
118 turned on, these instructions won't be used. This code will still
119 run on a 68030 and 68881/2. */
120 #define MASK_68060 1024
121 #define TARGET_68060 (target_flags & MASK_68060)
123 /* Compile for mcf5200 */
124 #define MASK_5200 2048
125 #define TARGET_5200 (target_flags & MASK_5200)
127 /* Align ints to a word boundary. This breaks compatibility with the
128 published ABI's for structures containing ints, but produces faster
129 code on cpus with 32 bit busses (020, 030, 040, 060, CPU32+, coldfire).
130 It's required for coldfire cpus without a misalignment module. */
131 #define MASK_ALIGN_INT 4096
132 #define TARGET_ALIGN_INT (target_flags & MASK_ALIGN_INT)
134 /* Compile for a CPU32 */
135 /* A 68020 without bitfields is a good heuristic for a CPU32 */
136 #define TARGET_CPU32 (TARGET_68020 && !TARGET_BITFIELD)
138 /* Use PC-relative addressing modes (without using a global offset table).
139 The m68000 supports 16-bit PC-relative addressing.
140 The m68020 supports 32-bit PC-relative addressing
141 (using outer displacements).
143 Under this model, all SYMBOL_REFs (and CONSTs) and LABEL_REFs are
144 treated as all containing an implicit PC-relative component, and hence
145 cannot be used directly as addresses for memory writes. See the comments
146 in m68k.c for more information. */
147 #define MASK_PCREL 8192
148 #define TARGET_PCREL (target_flags & MASK_PCREL)
150 /* Relax strict alignment. */
151 #define MASK_NO_STRICT_ALIGNMENT 16384
152 #define TARGET_STRICT_ALIGNMENT (~target_flags & MASK_NO_STRICT_ALIGNMENT)
154 /* Macro to define tables used to set the flags.
155 This is a list in braces of pairs in braces,
156 each pair being { "NAME", VALUE }
157 where VALUE is the bits to set or minus the bits to clear.
158 An empty string NAME is used to identify the default VALUE. */
160 #define TARGET_SWITCHES \
161 { { "68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \
162 N_("Generate code for a 68020") }, \
163 { "c68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \
164 N_("Generate code for a 68020") }, \
165 { "68020", (MASK_68020|MASK_BITFIELD), "" }, \
166 { "c68020", (MASK_68020|MASK_BITFIELD), "" }, \
167 { "68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
168 |MASK_68020|MASK_BITFIELD|MASK_68881), \
169 N_("Generate code for a 68000") }, \
170 { "c68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
171 |MASK_68020|MASK_BITFIELD|MASK_68881), \
172 N_("Generate code for a 68000") }, \
173 { "bitfield", MASK_BITFIELD, \
174 N_("Use the bit-field instructions") }, \
175 { "nobitfield", - MASK_BITFIELD, \
176 N_("Do not use the bit-field instructions") }, \
178 N_("Use different calling convention using 'rtd'") }, \
179 { "nortd", - MASK_RTD, \
180 N_("Use normal calling convention") }, \
181 { "short", MASK_SHORT, \
182 N_("Consider type `int' to be 16 bits wide") }, \
183 { "noshort", - MASK_SHORT, \
184 N_("Consider type `int' to be 32 bits wide") }, \
185 { "fpa", -(MASK_SKY|MASK_68040_ONLY|MASK_68881), \
186 N_("Generate code for a Sun FPA") }, \
187 { "fpa", MASK_FPA, "" }, \
188 { "nofpa", - MASK_FPA, \
189 N_("Do not generate code for a Sun FPA") }, \
190 { "sky", -(MASK_FPA|MASK_68040_ONLY|MASK_68881), \
191 N_("Generate code for a Sun Sky board") }, \
193 N_("Generate code for a Sun Sky board") }, \
194 { "nosky", - MASK_SKY, \
195 N_("Do not use Sky linkage convention") }, \
196 { "68881", - (MASK_FPA|MASK_SKY), \
197 N_("Generate code for a 68881") }, \
198 { "68881", MASK_68881, "" }, \
199 { "soft-float", - (MASK_FPA|MASK_SKY|MASK_68040_ONLY|MASK_68881), \
200 N_("Generate code with library calls for floating point") }, \
201 { "68020-40", -(MASK_5200|MASK_68060|MASK_68040_ONLY), \
202 N_("Generate code for a 68040, without any new instructions") }, \
203 { "68020-40", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040), ""},\
204 { "68020-60", -(MASK_5200|MASK_68040_ONLY), \
205 N_("Generate code for a 68060, without any new instructions") }, \
206 { "68020-60", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040 \
207 |MASK_68060), "" }, \
208 { "68030", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \
209 N_("Generate code for a 68030") }, \
210 { "68030", (MASK_68020|MASK_BITFIELD), "" }, \
211 { "68040", - (MASK_5200|MASK_68060), \
212 N_("Generate code for a 68040") }, \
213 { "68040", (MASK_68020|MASK_68881|MASK_BITFIELD \
214 |MASK_68040_ONLY|MASK_68040), "" }, \
215 { "68060", - (MASK_5200|MASK_68040), \
216 N_("Generate code for a 68060") }, \
217 { "68060", (MASK_68020|MASK_68881|MASK_BITFIELD \
218 |MASK_68040_ONLY|MASK_68060), "" }, \
219 { "5200", - (MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
220 |MASK_BITFIELD|MASK_68881), \
221 N_("Generate code for a 520X") }, \
222 { "5200", (MASK_5200), "" }, \
224 N_("Generate code for a 68851") }, \
226 N_("Do no generate code for a 68851") }, \
227 { "68302", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
228 |MASK_68020|MASK_BITFIELD|MASK_68881), \
229 N_("Generate code for a 68302") }, \
230 { "68332", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
231 |MASK_BITFIELD|MASK_68881), \
232 N_("Generate code for a 68332") }, \
233 { "68332", MASK_68020, "" }, \
234 { "cpu32", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
235 |MASK_BITFIELD|MASK_68881), \
236 N_("Generate code for a cpu32") }, \
237 { "cpu32", MASK_68020, "" }, \
238 { "align-int", MASK_ALIGN_INT, \
239 N_("Align variables on a 32-bit boundary") }, \
240 { "no-align-int", -MASK_ALIGN_INT, \
241 N_("Align variables on a 16-bit boundary") }, \
242 { "pcrel", MASK_PCREL, \
243 N_("Generate pc-relative code") }, \
244 { "strict-align", -MASK_NO_STRICT_ALIGNMENT, \
245 N_("Do not use unaligned memory references") }, \
246 { "no-strict-align", MASK_NO_STRICT_ALIGNMENT, \
247 N_("Use unaligned memory references") }, \
249 { "", TARGET_DEFAULT, "" }}
250 /* TARGET_DEFAULT is defined in sun*.h and isi.h, etc. */
252 /* This macro is similar to `TARGET_SWITCHES' but defines names of
253 command options that have values. Its definition is an
254 initializer with a subgrouping for each command option.
256 Each subgrouping contains a string constant, that defines the
257 fixed part of the option name, and the address of a variable. The
258 variable, type `char *', is set to the variable part of the given
259 option if the fixed part matches. The actual option name is made
260 by appending `-m' to the specified name. */
261 #define TARGET_OPTIONS \
262 { { "align-loops=", &m68k_align_loops_string, \
263 N_("Loop code aligned to this power of 2"), 0}, \
264 { "align-jumps=", &m68k_align_jumps_string, \
265 N_("Jump targets are aligned to this power of 2"), 0}, \
266 { "align-functions=", &m68k_align_funcs_string, \
267 N_("Function starts are aligned to this power of 2"), 0}, \
271 /* Sometimes certain combinations of command options do not make
272 sense on a particular target machine. You can define a macro
273 `OVERRIDE_OPTIONS' to take account of this. This macro, if
274 defined, is executed once just after all the command options have
277 Don't use this macro to turn on various extra optimizations for
278 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
280 #define OVERRIDE_OPTIONS override_options()
282 /* These are meant to be redefined in the host dependent files */
283 #define SUBTARGET_SWITCHES
284 #define SUBTARGET_OPTIONS
285 #define SUBTARGET_OVERRIDE_OPTIONS
287 /* target machine storage layout */
289 /* Define for XFmode extended real floating point support. */
290 #define LONG_DOUBLE_TYPE_SIZE 96
292 /* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
293 instructions, we get proper intermediate rounding, otherwise we
294 get extended precision results. */
295 #define TARGET_FLT_EVAL_METHOD (TARGET_68040_ONLY ? 0 : 2)
297 /* Define this if most significant bit is lowest numbered
298 in instructions that operate on numbered bit-fields.
299 This is true for 68020 insns such as bfins and bfexts.
300 We make it true always by avoiding using the single-bit insns
301 except in special cases with constant bit numbers. */
302 #define BITS_BIG_ENDIAN 1
304 /* Define this if most significant byte of a word is the lowest numbered. */
305 /* That is true on the 68000. */
306 #define BYTES_BIG_ENDIAN 1
308 /* Define this if most significant word of a multiword number is the lowest
310 /* For 68000 we can decide arbitrarily
311 since there are no machine instructions for them.
312 So let's be consistent. */
313 #define WORDS_BIG_ENDIAN 1
315 /* Width of a word, in units (bytes). */
316 #define UNITS_PER_WORD 4
318 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
319 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
321 /* Boundary (in *bits*) on which stack pointer should be aligned. */
322 #define STACK_BOUNDARY 16
324 /* Allocation boundary (in *bits*) for the code of a function. */
325 #define FUNCTION_BOUNDARY (1 << (m68k_align_funcs + 3))
327 /* Alignment of field after `int : 0' in a structure. */
328 #define EMPTY_FIELD_BOUNDARY 16
330 /* No data type wants to be aligned rounder than this.
331 Most published ABIs say that ints should be aligned on 16 bit
332 boundaries, but cpus with 32 bit busses get better performance
333 aligned on 32 bit boundaries. Coldfires without a misalignment
334 module require 32 bit alignment. */
335 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
337 /* Set this nonzero if move instructions will actually fail to work
338 when given unaligned data. */
339 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT)
341 /* Maximum power of 2 that code can be aligned to. */
342 #define MAX_CODE_ALIGN 2 /* 4 byte alignment */
344 /* Align loop starts for optimal branching. */
345 #define LOOP_ALIGN(LABEL) (m68k_align_loops)
347 /* This is how to align an instruction for optimal branching. */
348 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) (m68k_align_jumps)
350 /* Define number of bits in most basic integer type.
351 (If undefined, default is BITS_PER_WORD). */
353 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
355 /* Define these to avoid dependence on meaning of `int'. */
357 #define WCHAR_TYPE "long int"
358 #define WCHAR_TYPE_SIZE 32
360 /* Standard register usage. */
362 /* Number of actual hardware registers.
363 The hardware registers are assigned numbers for the compiler
364 from 0 to just below FIRST_PSEUDO_REGISTER.
365 All registers that the compiler knows about must be given numbers,
366 even those that are not normally considered general registers.
367 For the 68000, we give the data registers numbers 0-7,
368 the address registers numbers 010-017,
369 and the 68881 floating point registers numbers 020-027. */
370 #ifndef SUPPORT_SUN_FPA
371 #define FIRST_PSEUDO_REGISTER 24
373 #define FIRST_PSEUDO_REGISTER 56
376 /* This defines the register which is used to hold the offset table for PIC. */
377 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 13 : INVALID_REGNUM)
379 #ifndef SUPPORT_SUN_FPA
381 /* 1 for registers that have pervasive standard uses
382 and are not available for the register allocator.
383 On the 68000, only the stack pointer is such. */
385 #define FIXED_REGISTERS \
386 {/* Data registers. */ \
387 0, 0, 0, 0, 0, 0, 0, 0, \
389 /* Address registers. */ \
390 0, 0, 0, 0, 0, 0, 0, 1, \
392 /* Floating point registers \
394 0, 0, 0, 0, 0, 0, 0, 0 }
396 /* 1 for registers not available across function calls.
397 These must include the FIXED_REGISTERS and also any
398 registers that can be used without being saved.
399 The latter must include the registers where values are returned
400 and the register where structure-value addresses are passed.
401 Aside from that, you can include as many other registers as you like. */
402 #define CALL_USED_REGISTERS \
403 {1, 1, 0, 0, 0, 0, 0, 0, \
404 1, 1, 0, 0, 0, 0, 0, 1, \
405 1, 1, 0, 0, 0, 0, 0, 0 }
407 #else /* SUPPORT_SUN_FPA */
409 /* 1 for registers that have pervasive standard uses
410 and are not available for the register allocator.
411 On the 68000, only the stack pointer is such. */
413 /* fpa0 is also reserved so that it can be used to move data back and
414 forth between high fpa regs and everything else. */
416 #define FIXED_REGISTERS \
417 {/* Data registers. */ \
418 0, 0, 0, 0, 0, 0, 0, 0, \
420 /* Address registers. */ \
421 0, 0, 0, 0, 0, 0, 0, 1, \
423 /* Floating point registers \
425 0, 0, 0, 0, 0, 0, 0, 0, \
427 /* Sun3 FPA registers. */ \
428 1, 0, 0, 0, 0, 0, 0, 0, \
429 0, 0, 0, 0, 0, 0, 0, 0, \
430 0, 0, 0, 0, 0, 0, 0, 0, \
431 0, 0, 0, 0, 0, 0, 0, 0 }
433 /* 1 for registers not available across function calls.
434 These must include the FIXED_REGISTERS and also any
435 registers that can be used without being saved.
436 The latter must include the registers where values are returned
437 and the register where structure-value addresses are passed.
438 Aside from that, you can include as many other registers as you like. */
439 #define CALL_USED_REGISTERS \
440 {1, 1, 0, 0, 0, 0, 0, 0, \
441 1, 1, 0, 0, 0, 0, 0, 1, \
442 1, 1, 0, 0, 0, 0, 0, 0, \
443 /* FPA registers. */ \
444 1, 1, 1, 1, 0, 0, 0, 0, \
445 0, 0, 0, 0, 0, 0, 0, 0, \
446 0, 0, 0, 0, 0, 0, 0, 0, \
447 0, 0, 0, 0, 0, 0, 0, 0 }
449 #endif /* defined SUPPORT_SUN_FPA */
452 /* Make sure everything's fine if we *don't* have a given processor.
453 This assumes that putting a register in fixed_regs will keep the
454 compiler's mitts completely off it. We don't bother to zero it out
455 of register classes. */
457 #ifdef SUPPORT_SUN_FPA
459 #define CONDITIONAL_REGISTER_USAGE \
465 COPY_HARD_REG_SET (x, reg_class_contents[(int)FPA_REGS]); \
466 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
467 if (TEST_HARD_REG_BIT (x, i)) \
468 fixed_regs[i] = call_used_regs[i] = 1; \
470 if (! TARGET_68881) \
472 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
473 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
474 if (TEST_HARD_REG_BIT (x, i)) \
475 fixed_regs[i] = call_used_regs[i] = 1; \
477 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
478 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
479 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
482 #define CONDITIONAL_REGISTER_USAGE \
486 if (! TARGET_68881) \
488 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
489 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
490 if (TEST_HARD_REG_BIT (x, i)) \
491 fixed_regs[i] = call_used_regs[i] = 1; \
493 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
494 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
495 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
498 #endif /* defined SUPPORT_SUN_FPA */
500 /* Return number of consecutive hard regs needed starting at reg REGNO
501 to hold something of mode MODE.
502 This is ordinarily the length in words of a value of mode MODE
503 but can be less for certain modes in special long registers.
505 On the 68000, ordinary registers hold 32 bits worth;
506 for the 68881 registers, a single register is always enough for
507 anything that can be stored in them at all. */
508 #define HARD_REGNO_NREGS(REGNO, MODE) \
509 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
510 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
512 #ifndef SUPPORT_SUN_FPA
514 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
515 On the 68000, the cpu registers can hold any mode but the 68881 registers
516 can hold only SFmode or DFmode. */
518 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
520 && !((REGNO) < 8 && (REGNO) + GET_MODE_SIZE (MODE) / 4 > 8)) \
521 || ((REGNO) >= 16 && (REGNO) < 24 \
522 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
523 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
524 && GET_MODE_UNIT_SIZE (MODE) <= 12))
526 #else /* defined SUPPORT_SUN_FPA */
528 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
529 On the 68000, the cpu registers can hold any mode but the 68881 registers
530 can hold only SFmode or DFmode. However, the Sun FPA register can
531 (apparently) hold whatever you feel like putting in them.
532 If using the fpa, don't put a double in d7/a0. */
534 /* ??? This is confused. The check to prohibit d7/a0 overlaps should always
535 be enabled regardless of whether TARGET_FPA is specified. It isn't clear
536 what the other d/a register checks are for. Every check using REGNO
537 actually needs to use a range, e.g. 24>=X<56 not <56. There is probably
538 no one using this code anymore.
539 This code used to be used to suppress register usage for the 68881 by
540 saying that the 68881 registers couldn't hold values of any mode if there
541 was no 68881. This was wrong, because reload (etc.) will still try
542 to save and restore call-saved registers during, for instance, non-local
544 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
547 && GET_MODE_CLASS ((MODE)) != MODE_INT \
548 && GET_MODE_UNIT_SIZE ((MODE)) > 4 \
549 && (REGNO) < 8 && (REGNO) + GET_MODE_SIZE ((MODE)) / 4 > 8 \
550 && (REGNO) % (GET_MODE_UNIT_SIZE ((MODE)) / 4) != 0)) \
551 || ((REGNO) >= 16 && (REGNO) < 24 \
552 ? ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
553 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
554 && GET_MODE_UNIT_SIZE (MODE) <= 12) \
555 : ((REGNO) < 56 ? TARGET_FPA && GET_MODE_UNIT_SIZE (MODE) <= 8 : 0)))
557 #endif /* defined SUPPORT_SUN_FPA */
559 /* Value is 1 if it is a good idea to tie two pseudo registers
560 when one has mode MODE1 and one has mode MODE2.
561 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
562 for any hard reg, then this must be 0 for correct output. */
563 #define MODES_TIEABLE_P(MODE1, MODE2) \
565 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
566 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
567 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
568 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
570 /* Specify the registers used for certain standard purposes.
571 The values of these macros are register numbers. */
573 /* m68000 pc isn't overloaded on a register. */
574 /* #define PC_REGNUM */
576 /* Register to use for pushing function arguments. */
577 #define STACK_POINTER_REGNUM 15
579 /* Base register for access to local variables of the function. */
580 #define FRAME_POINTER_REGNUM 14
582 /* Value should be nonzero if functions must have frame pointers.
583 Zero means the frame pointer need not be set up (and parms
584 may be accessed via the stack pointer) in functions that seem suitable.
585 This is computed in `reload', in reload1.c. */
586 #define FRAME_POINTER_REQUIRED 0
588 /* Base register for access to arguments of the function. */
589 #define ARG_POINTER_REGNUM 14
591 /* Register in which static-chain is passed to a function. */
592 #define STATIC_CHAIN_REGNUM 8
594 /* Register in which address to store a structure value
595 is passed to a function. */
596 #define STRUCT_VALUE_REGNUM 9
598 /* Define the classes of registers for register constraints in the
599 machine description. Also define ranges of constants.
601 One of the classes must always be named ALL_REGS and include all hard regs.
602 If there is more than one class, another class must be named NO_REGS
603 and contain no registers.
605 The name GENERAL_REGS must be the name of a class (or an alias for
606 another name such as ALL_REGS). This is the class of registers
607 that is allowed by "g" or "r" in a register constraint.
608 Also, registers outside this class are allocated only when
609 instructions express preferences for them.
611 The classes must be numbered in nondecreasing order; that is,
612 a larger-numbered class must never be contained completely
613 in a smaller-numbered class.
615 For any two classes, it is very desirable that there be another
616 class that represents their union. */
618 /* The 68000 has three kinds of registers, so eight classes would be
619 a complete set. One of them is not needed. */
621 #ifndef SUPPORT_SUN_FPA
626 GENERAL_REGS, DATA_OR_FP_REGS,
627 ADDR_OR_FP_REGS, ALL_REGS,
630 #define N_REG_CLASSES (int) LIM_REG_CLASSES
632 /* Give names of register classes as strings for dump file. */
634 #define REG_CLASS_NAMES \
635 { "NO_REGS", "DATA_REGS", \
636 "ADDR_REGS", "FP_REGS", \
637 "GENERAL_REGS", "DATA_OR_FP_REGS", \
638 "ADDR_OR_FP_REGS", "ALL_REGS" }
640 /* Define which registers fit in which classes.
641 This is an initializer for a vector of HARD_REG_SET
642 of length N_REG_CLASSES. */
644 #define REG_CLASS_CONTENTS \
646 {0x00000000}, /* NO_REGS */ \
647 {0x000000ff}, /* DATA_REGS */ \
648 {0x0000ff00}, /* ADDR_REGS */ \
649 {0x00ff0000}, /* FP_REGS */ \
650 {0x0000ffff}, /* GENERAL_REGS */ \
651 {0x00ff00ff}, /* DATA_OR_FP_REGS */ \
652 {0x00ffff00}, /* ADDR_OR_FP_REGS */ \
653 {0x00ffffff}, /* ALL_REGS */ \
656 /* The same information, inverted:
657 Return the class number of the smallest class containing
658 reg number REGNO. This could be a conditional expression
659 or could index an array. */
661 #define REGNO_REG_CLASS(REGNO) (((REGNO)>>3)+1)
663 #else /* defined SUPPORT_SUN_FPA */
666 * Notes on final choices:
668 * 1) Didn't feel any need to union-ize LOW_FPA_REGS with anything
670 * 2) Removed all unions that involve address registers with
671 * floating point registers (left in unions of address and data with
673 * 3) Defined GENERAL_REGS as ADDR_OR_DATA_REGS.
674 * 4) Defined ALL_REGS as FPA_OR_FP_OR_GENERAL_REGS.
675 * 4) Left in everything else.
677 enum reg_class { NO_REGS, LO_FPA_REGS, FPA_REGS, FP_REGS,
678 FP_OR_FPA_REGS, DATA_REGS, DATA_OR_FPA_REGS, DATA_OR_FP_REGS,
679 DATA_OR_FP_OR_FPA_REGS, ADDR_REGS, GENERAL_REGS,
680 GENERAL_OR_FPA_REGS, GENERAL_OR_FP_REGS, ALL_REGS,
683 #define N_REG_CLASSES (int) LIM_REG_CLASSES
685 /* Give names of register classes as strings for dump file. */
687 #define REG_CLASS_NAMES \
688 { "NO_REGS", "LO_FPA_REGS", "FPA_REGS", "FP_REGS", \
689 "FP_OR_FPA_REGS", "DATA_REGS", "DATA_OR_FPA_REGS", "DATA_OR_FP_REGS", \
690 "DATA_OR_FP_OR_FPA_REGS", "ADDR_REGS", "GENERAL_REGS", \
691 "GENERAL_OR_FPA_REGS", "GENERAL_OR_FP_REGS", "ALL_REGS" }
693 /* Define which registers fit in which classes.
694 This is an initializer for a vector of HARD_REG_SET
695 of length N_REG_CLASSES. */
697 #define REG_CLASS_CONTENTS \
699 {0, 0}, /* NO_REGS */ \
700 {0xff000000, 0x000000ff}, /* LO_FPA_REGS */ \
701 {0xff000000, 0x00ffffff}, /* FPA_REGS */ \
702 {0x00ff0000, 0x00000000}, /* FP_REGS */ \
703 {0xffff0000, 0x00ffffff}, /* FP_OR_FPA_REGS */ \
704 {0x000000ff, 0x00000000}, /* DATA_REGS */ \
705 {0xff0000ff, 0x00ffffff}, /* DATA_OR_FPA_REGS */ \
706 {0x00ff00ff, 0x00000000}, /* DATA_OR_FP_REGS */ \
707 {0xffff00ff, 0x00ffffff}, /* DATA_OR_FP_OR_FPA_REGS */\
708 {0x0000ff00, 0x00000000}, /* ADDR_REGS */ \
709 {0x0000ffff, 0x00000000}, /* GENERAL_REGS */ \
710 {0xff00ffff, 0x00ffffff}, /* GENERAL_OR_FPA_REGS */\
711 {0x00ffffff, 0x00000000}, /* GENERAL_OR_FP_REGS */\
712 {0xffffffff, 0x00ffffff}, /* ALL_REGS */ \
715 /* The same information, inverted:
716 Return the class number of the smallest class containing
717 reg number REGNO. This could be a conditional expression
718 or could index an array. */
720 extern const enum reg_class regno_reg_class[];
721 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)>>3])
723 #endif /* SUPPORT_SUN_FPA */
725 /* The class value for index registers, and the one for base regs. */
727 #define INDEX_REG_CLASS GENERAL_REGS
728 #define BASE_REG_CLASS ADDR_REGS
730 /* Get reg_class from a letter such as appears in the machine description.
731 We do a trick here to modify the effective constraints on the
732 machine description; we zorch the constraint letters that aren't
733 appropriate for a specific target. This allows us to guarantee
734 that a specific kind of register will not be used for a given target
735 without fiddling with the register classes above. */
737 #ifndef SUPPORT_SUN_FPA
739 #define REG_CLASS_FROM_LETTER(C) \
740 ((C) == 'a' ? ADDR_REGS : \
741 ((C) == 'd' ? DATA_REGS : \
742 ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \
746 #else /* defined SUPPORT_SUN_FPA */
748 #define REG_CLASS_FROM_LETTER(C) \
749 ((C) == 'a' ? ADDR_REGS : \
750 ((C) == 'd' ? DATA_REGS : \
751 ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \
753 ((C) == 'x' ? (TARGET_FPA ? FPA_REGS : \
755 ((C) == 'y' ? (TARGET_FPA ? LO_FPA_REGS : \
759 #endif /* defined SUPPORT_SUN_FPA */
761 /* The letters I, J, K, L and M in a register constraint string
762 can be used to stand for particular ranges of immediate operands.
763 This macro defines what the ranges are.
764 C is the letter, and VALUE is a constant value.
765 Return 1 if VALUE is in the range specified by C.
767 For the 68000, `I' is used for the range 1 to 8
768 allowed as immediate shift counts and in addq.
769 `J' is used for the range of signed numbers that fit in 16 bits.
770 `K' is for numbers that moveq can't handle.
771 `L' is for range -8 to -1, range of values that can be added with subq.
772 `M' is for numbers that moveq+notb can't handle.
773 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate.
774 'O' is for 16 (for rotate using swap).
775 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */
777 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
778 ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \
779 (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
780 (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
781 (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \
782 (C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \
783 (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \
784 (C) == 'O' ? (VALUE) == 16 : \
785 (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0)
788 * A small bit of explanation:
789 * "G" defines all of the floating constants that are *NOT* 68881
790 * constants. this is so 68881 constants get reloaded and the
791 * fpmovecr is used. "H" defines *only* the class of constants that
792 * the fpa can use, because these can be gotten at in any fpa
793 * instruction and there is no need to force reloads.
795 #ifndef SUPPORT_SUN_FPA
796 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
797 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 )
798 #else /* defined SUPPORT_SUN_FPA */
799 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
800 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : \
801 (C) == 'H' ? (TARGET_FPA && standard_sun_fpa_constant_p (VALUE)) : 0)
802 #endif /* defined SUPPORT_SUN_FPA */
804 /* A C expression that defines the optional machine-dependent constraint
805 letters that can be used to segregate specific types of operands,
806 usually memory references, for the target machine. It should return 1 if
807 VALUE corresponds to the operand type represented by the constraint letter
808 C. If C is not defined as an extra constraint, the value returned should
809 be 0 regardless of VALUE. */
811 /* Letters in the range `Q' through `U' may be defined in a
812 machine-dependent fashion to stand for arbitrary operand types.
813 The machine description macro `EXTRA_CONSTRAINT' is passed the
814 operand as its first argument and the constraint letter as its
817 `Q' means address register indirect addressing mode.
818 `S' is for operands that satisfy 'm' when -mpcrel is in effect.
819 `T' is for operands that satisfy 's' when -mpcrel is not in effect. */
821 #define EXTRA_CONSTRAINT(OP,CODE) \
824 && GET_CODE (OP) == MEM \
825 && (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
826 || GET_CODE (XEXP (OP, 0)) == LABEL_REF \
827 || GET_CODE (XEXP (OP, 0)) == CONST)) \
831 && (GET_CODE (OP) == SYMBOL_REF \
832 || GET_CODE (OP) == LABEL_REF \
833 || GET_CODE (OP) == CONST)) \
836 ? (GET_CODE (OP) == MEM \
837 && GET_CODE (XEXP (OP, 0)) == REG) \
841 /* Given an rtx X being reloaded into a reg required to be
842 in class CLASS, return the class of reg to actually use.
843 In general this is just CLASS; but on some machines
844 in some cases it is preferable to use a more restrictive class.
845 On the 68000 series, use a data reg if possible when the
846 value is a constant in the range where moveq could be used
847 and we ensure that QImodes are reloaded into data regs. */
849 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
850 ((GET_CODE (X) == CONST_INT \
851 && (unsigned) (INTVAL (X) + 0x80) < 0x100 \
852 && (CLASS) != ADDR_REGS) \
854 : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \
856 : (GET_CODE (X) == CONST_DOUBLE \
857 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
858 ? (TARGET_68881 && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \
859 ? FP_REGS : NO_REGS) \
861 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
862 || GET_CODE (X) == LABEL_REF)) \
866 /* Force QImode output reloads from subregs to be allocated to data regs,
867 since QImode stores from address regs are not supported. We make the
868 assumption that if the class is not ADDR_REGS, then it must be a superset
871 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
872 (((MODE) == QImode && (CLASS) != ADDR_REGS) \
876 /* Return the maximum number of consecutive registers
877 needed to represent mode MODE in a register of class CLASS. */
878 /* On the 68000, this is the size of MODE in words,
879 except in the FP regs, where a single reg is always enough. */
880 #ifndef SUPPORT_SUN_FPA
882 #define CLASS_MAX_NREGS(CLASS, MODE) \
883 ((CLASS) == FP_REGS ? 1 \
884 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
886 /* Moves between fp regs and other regs are two insns. */
887 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
888 (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
889 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
892 #else /* defined SUPPORT_SUN_FPA */
894 #define CLASS_MAX_NREGS(CLASS, MODE) \
895 ((CLASS) == FP_REGS || (CLASS) == FPA_REGS || (CLASS) == LO_FPA_REGS ? 1 \
896 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
898 /* Moves between fp regs and other regs are two insns. */
899 /* Likewise for high fpa regs and other regs. */
900 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
901 ((((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
902 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
903 || ((CLASS1) == FPA_REGS && (CLASS2) != FPA_REGS) \
904 || ((CLASS2) == FPA_REGS && (CLASS1) != FPA_REGS)) \
907 #endif /* define SUPPORT_SUN_FPA */
909 /* Stack layout; function entry, exit and calling. */
911 /* Define this if pushing a word on the stack
912 makes the stack pointer a smaller address. */
913 #define STACK_GROWS_DOWNWARD
915 /* Nonzero if we need to generate stack-probe insns.
916 On most systems they are not needed.
917 When they are needed, define this as the stack offset to probe at. */
920 /* Define this if the nominal address of the stack frame
921 is at the high-address end of the local variables;
922 that is, each additional local variable allocated
923 goes at a more negative offset in the frame. */
924 #define FRAME_GROWS_DOWNWARD
926 /* Offset within stack frame to start allocating local variables at.
927 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
928 first local allocated. Otherwise, it is the offset to the BEGINNING
929 of the first local allocated. */
930 #define STARTING_FRAME_OFFSET 0
932 /* If we generate an insn to push BYTES bytes,
933 this says how many the stack pointer really advances by.
934 On the 68000, sp@- in a byte insn really pushes a word.
935 On the 5200 (coldfire), sp@- in a byte insn pushes just a byte. */
936 #define PUSH_ROUNDING(BYTES) (TARGET_5200 ? BYTES : ((BYTES) + 1) & ~1)
938 /* We want to avoid trying to push bytes. */
939 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
940 (move_by_pieces_ninsns (SIZE, ALIGN) < MOVE_RATIO \
941 && (((SIZE) >=16 && (ALIGN) >= 16) || (TARGET_5200)))
943 /* Offset of first parameter from the argument pointer register value. */
944 #define FIRST_PARM_OFFSET(FNDECL) 8
946 /* Value is the number of byte of arguments automatically
947 popped when returning from a subroutine call.
948 FUNDECL is the declaration node of the function (as a tree),
949 FUNTYPE is the data type of the function (as a tree),
950 or for a library call it is an identifier node for the subroutine name.
951 SIZE is the number of bytes of arguments passed on the stack.
953 On the 68000, the RTS insn cannot pop anything.
954 On the 68010, the RTD insn may be used to pop them if the number
955 of args is fixed, but if the number is variable then the caller
956 must pop them all. RTD can't be used for library calls now
957 because the library is compiled with the Unix compiler.
958 Use of RTD is a selectable option, since it is incompatible with
959 standard Unix calling sequences. If the option is not selected,
960 the caller must always pop the args. */
962 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
963 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \
964 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
965 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
966 == void_type_node))) \
969 /* Define how to find the value returned by a function.
970 VALTYPE is the data type of the value (as a tree).
971 If the precise function being called is known, FUNC is its FUNCTION_DECL;
972 otherwise, FUNC is 0. */
974 /* On the 68000 the return value is in D0 regardless. */
976 #define FUNCTION_VALUE(VALTYPE, FUNC) \
977 gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
979 /* Define how to find the value returned by a library function
980 assuming the value has mode MODE. */
982 /* On the 68000 the return value is in D0 regardless. */
984 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
986 /* 1 if N is a possible register number for a function value.
987 On the 68000, d0 is the only register thus used. */
989 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
991 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
992 more than one register. */
994 #define NEEDS_UNTYPED_CALL 0
996 /* Define this if PCC uses the nonreentrant convention for returning
997 structure and union values. */
999 #define PCC_STATIC_STRUCT_RETURN
1001 /* 1 if N is a possible register number for function argument passing.
1002 On the 68000, no registers are used in this way. */
1004 #define FUNCTION_ARG_REGNO_P(N) 0
1006 /* Define a data type for recording info about an argument list
1007 during the scan of that argument list. This data type should
1008 hold all necessary information about the function itself
1009 and about the args processed so far, enough to enable macros
1010 such as FUNCTION_ARG to determine where the next arg should go.
1012 On the m68k, this is a single integer, which is a number of bytes
1013 of arguments scanned so far. */
1015 #define CUMULATIVE_ARGS int
1017 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1018 for a call to a function whose data type is FNTYPE.
1019 For a library call, FNTYPE is 0.
1021 On the m68k, the offset starts at 0. */
1023 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1026 /* Update the data in CUM to advance over an argument
1027 of mode MODE and data type TYPE.
1028 (TYPE is null for libcalls where that information may not be available.) */
1030 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1031 ((CUM) += ((MODE) != BLKmode \
1032 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
1033 : (int_size_in_bytes (TYPE) + 3) & ~3))
1035 /* Define where to put the arguments to a function.
1036 Value is zero to push the argument on the stack,
1037 or a hard register in which to store the argument.
1039 MODE is the argument's machine mode.
1040 TYPE is the data type of the argument (as a tree).
1041 This is null for libcalls where that information may
1043 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1044 the preceding args and about the function being called.
1045 NAMED is nonzero if this argument is a named parameter
1046 (otherwise it is an extra parameter matching an ellipsis). */
1048 /* On the 68000 all args are pushed, except if -mregparm is specified
1049 then the first two words of arguments are passed in d0, d1.
1050 *NOTE* -mregparm does not work.
1051 It exists only to test register calling conventions. */
1053 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1054 ((TARGET_REGPARM && (CUM) < 8) ? gen_rtx_REG ((MODE), (CUM) / 4) : 0)
1056 /* For an arg passed partly in registers and partly in memory,
1057 this is the number of registers used.
1058 For args passed entirely in registers or entirely in memory, zero. */
1060 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1061 ((TARGET_REGPARM && (CUM) < 8 \
1062 && 8 < ((CUM) + ((MODE) == BLKmode \
1063 ? int_size_in_bytes (TYPE) \
1064 : GET_MODE_SIZE (MODE)))) \
1065 ? 2 - (CUM) / 4 : 0)
1067 /* Output assembler code to FILE to increment profiler label # LABELNO
1068 for profiling a function entry. */
1070 #define FUNCTION_PROFILER(FILE, LABELNO) \
1071 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO))
1073 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1074 the stack pointer does not matter. The value is tested only in
1075 functions that have frame pointers.
1076 No definition is equivalent to always zero. */
1078 #define EXIT_IGNORE_STACK 1
1080 /* This is a hook for other tm files to change. */
1081 /* #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) */
1083 /* Determine if the epilogue should be output as RTL.
1084 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1085 #define USE_RETURN_INSN use_return_insn ()
1087 /* Store in the variable DEPTH the initial difference between the
1088 frame pointer reg contents and the stack pointer reg contents,
1089 as of the start of the function body. This depends on the layout
1090 of the fixed parts of the stack frame and on how registers are saved.
1092 On the 68k, if we have a frame, we must add one word to its length
1093 to allow for the place that a6 is stored when we do have a frame pointer.
1094 Otherwise, we would need to compute the offset from the frame pointer
1095 of a local variable as a function of frame_pointer_needed, which
1098 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
1101 for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \
1102 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1104 for (regno = 0; regno < 16; regno++) \
1105 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1107 if (flag_pic && current_function_uses_pic_offset_table) \
1109 (DEPTH) = (offset + ((get_frame_size () + 3) & -4) \
1110 + (get_frame_size () == 0 ? 0 : 4)); \
1113 /* Output assembler code for a block containing the constant parts
1114 of a trampoline, leaving space for the variable parts. */
1116 /* On the 68k, the trampoline looks like this:
1120 WARNING: Targets that may run on 68040+ cpus must arrange for
1121 the instruction cache to be flushed. Previous incarnations of
1122 the m68k trampoline code attempted to get around this by either
1123 using an out-of-line transfer function or pc-relative data, but
1124 the fact remains that the code to jump to the transfer function
1125 or the code to load the pc-relative data needs to be flushed
1126 just as much as the "variable" portion of the trampoline.
1127 Recognizing that a cache flush is going to be required anyway,
1128 dispense with such notions and build a smaller trampoline. */
1130 /* Since more instructions are required to move a template into
1131 place than to create it on the spot, don't use a template. */
1133 /* Length in units of the trampoline for entering a nested function. */
1135 #define TRAMPOLINE_SIZE 12
1137 /* Alignment required for a trampoline in bits. */
1139 #define TRAMPOLINE_ALIGNMENT 16
1141 /* Targets redefine this to invoke code to either flush the cache,
1142 or enable stack execution (or both). */
1144 #ifndef FINALIZE_TRAMPOLINE
1145 #define FINALIZE_TRAMPOLINE(TRAMP)
1148 /* Emit RTL insns to initialize the variable parts of a trampoline.
1149 FNADDR is an RTX for the address of the function's pure code.
1150 CXT is an RTX for the static chain value for the function.
1152 We generate a two-instructions program at address TRAMP :
1156 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1158 emit_move_insn (gen_rtx_MEM (HImode, TRAMP), GEN_INT(0x207C)); \
1159 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \
1160 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \
1162 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \
1163 FINALIZE_TRAMPOLINE(TRAMP); \
1166 /* This is the library routine that is used
1167 to transfer control from the trampoline
1168 to the actual nested function.
1169 It is defined for backward compatibility,
1170 for linking with object code that used the old
1171 trampoline definition. */
1173 /* A colon is used with no explicit operands
1174 to cause the template string to be scanned for %-constructs. */
1175 /* The function name __transfer_from_trampoline is not actually used.
1176 The function definition just permits use of "asm with operands"
1177 (though the operand list is empty). */
1178 #define TRANSFER_FROM_TRAMPOLINE \
1180 __transfer_from_trampoline () \
1182 register char *a0 asm ("%a0"); \
1183 asm (GLOBAL_ASM_OP "___trampoline"); \
1184 asm ("___trampoline:"); \
1185 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \
1186 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \
1190 /* Addressing modes, and classification of registers for them. */
1192 #define HAVE_POST_INCREMENT 1
1194 #define HAVE_PRE_DECREMENT 1
1196 /* Macros to check register numbers against specific register classes. */
1198 /* These assume that REGNO is a hard or pseudo reg number.
1199 They give nonzero only if REGNO is a hard reg of the suitable class
1200 or a pseudo reg currently allocated to a suitable hard reg.
1201 Since they use reg_renumber, they are safe only once reg_renumber
1202 has been allocated, which happens in local-alloc.c. */
1204 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1205 ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
1206 #define REGNO_OK_FOR_BASE_P(REGNO) \
1207 (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
1208 #define REGNO_OK_FOR_DATA_P(REGNO) \
1209 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
1210 #define REGNO_OK_FOR_FP_P(REGNO) \
1211 (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
1212 #ifdef SUPPORT_SUN_FPA
1213 #define REGNO_OK_FOR_FPA_P(REGNO) \
1214 (((REGNO) >= 24 && (REGNO) < 56) || (reg_renumber[REGNO] >= 24 && reg_renumber[REGNO] < 56))
1217 /* Now macros that check whether X is a register and also,
1218 strictly, whether it is in a specified class.
1220 These macros are specific to the 68000, and may be used only
1221 in code for printing assembler insns and in conditions for
1222 define_optimization. */
1224 /* 1 if X is a data register. */
1226 #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
1228 /* 1 if X is an fp register. */
1230 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1232 /* 1 if X is an address register */
1234 #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
1236 #ifdef SUPPORT_SUN_FPA
1237 /* 1 if X is a register in the Sun FPA. */
1238 #define FPA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FPA_P (REGNO (X)))
1240 /* Answer must be no if we don't have an FPA. */
1241 #define FPA_REG_P(X) 0
1244 /* Maximum number of registers that can appear in a valid memory address. */
1246 #define MAX_REGS_PER_ADDRESS 2
1248 /* Recognize any constant value that is a valid address. */
1250 #define CONSTANT_ADDRESS_P(X) \
1251 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1252 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1253 || GET_CODE (X) == HIGH)
1255 /* Nonzero if the constant value X is a legitimate general operand.
1256 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1258 #define LEGITIMATE_CONSTANT_P(X) 1
1260 /* Nonzero if the constant value X is a legitimate general operand
1261 when generating PIC code. It is given that flag_pic is on and
1262 that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1264 PCREL_GENERAL_OPERAND_OK makes reload accept addresses that are
1265 accepted by insn predicates, but which would otherwise fail the
1266 `general_operand' test. */
1268 #ifndef REG_OK_STRICT
1269 #define PCREL_GENERAL_OPERAND_OK 0
1271 #define PCREL_GENERAL_OPERAND_OK (TARGET_PCREL)
1274 #define LEGITIMATE_PIC_OPERAND_P(X) \
1275 ((! symbolic_operand (X, VOIDmode) \
1276 && ! (GET_CODE (X) == CONST_DOUBLE && mem_for_const_double (X) != 0 \
1277 && GET_CODE (mem_for_const_double (X)) == MEM \
1278 && symbolic_operand (XEXP (mem_for_const_double (X), 0), \
1280 || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \
1281 || PCREL_GENERAL_OPERAND_OK)
1283 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1284 and check its validity for a certain class.
1285 We have two alternate definitions for each of them.
1286 The usual definition accepts all pseudo regs; the other rejects
1287 them unless they have been allocated suitable hard regs.
1288 The symbol REG_OK_STRICT causes the latter definition to be used.
1290 Most source files want to accept pseudo regs in the hope that
1291 they will get allocated to the class that the insn wants them to be in.
1292 Source files for reload pass need to be strict.
1293 After reload, it makes no difference, since pseudo regs have
1294 been eliminated by then. */
1296 #ifndef REG_OK_STRICT
1298 /* Nonzero if X is a hard reg that can be used as an index
1299 or if it is a pseudo reg. */
1300 #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
1301 /* Nonzero if X is a hard reg that can be used as a base reg
1302 or if it is a pseudo reg. */
1303 #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
1307 /* Nonzero if X is a hard reg that can be used as an index. */
1308 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1309 /* Nonzero if X is a hard reg that can be used as a base reg. */
1310 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1314 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1315 that is a valid memory address for an instruction.
1316 The MODE argument is the machine mode for the MEM expression
1317 that wants to use this address.
1319 When generating PIC, an address involving a SYMBOL_REF is legitimate
1320 if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF.
1321 We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses,
1322 and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF.
1324 Likewise for a LABEL_REF when generating PIC.
1326 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1328 /* Allow SUBREG everywhere we allow REG. This results in better code. It
1329 also makes function inlining work when inline functions are called with
1330 arguments that are SUBREGs. */
1332 #define LEGITIMATE_BASE_REG_P(X) \
1333 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1334 || (GET_CODE (X) == SUBREG \
1335 && GET_CODE (SUBREG_REG (X)) == REG \
1336 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1338 #define INDIRECTABLE_1_ADDRESS_P(X) \
1339 ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \
1340 || LEGITIMATE_BASE_REG_P (X) \
1341 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
1342 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
1343 || (GET_CODE (X) == PLUS \
1344 && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
1345 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1347 || ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) \
1348 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1349 && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \
1350 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1351 && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF))
1353 #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
1354 { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
1356 /* Only labels on dispatch tables are valid for indexing from. */
1357 #define GO_IF_INDEXABLE_BASE(X, ADDR) \
1359 if (GET_CODE (X) == LABEL_REF \
1360 && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \
1361 && GET_CODE (temp) == JUMP_INSN \
1362 && (GET_CODE (PATTERN (temp)) == ADDR_VEC \
1363 || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \
1365 if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; }
1367 #define GO_IF_INDEXING(X, ADDR) \
1368 { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
1369 { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
1370 if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
1371 { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
1373 #define GO_IF_INDEXED_ADDRESS(X, ADDR) \
1374 { GO_IF_INDEXING (X, ADDR); \
1375 if (GET_CODE (X) == PLUS) \
1376 { if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1377 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)) \
1378 { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \
1379 if (GET_CODE (XEXP (X, 0)) == CONST_INT \
1380 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)) \
1381 { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
1383 /* coldfire/5200 does not allow HImode index registers. */
1384 #define LEGITIMATE_INDEX_REG_P(X) \
1385 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1387 && GET_CODE (X) == SIGN_EXTEND \
1388 && GET_CODE (XEXP (X, 0)) == REG \
1389 && GET_MODE (XEXP (X, 0)) == HImode \
1390 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
1391 || (GET_CODE (X) == SUBREG \
1392 && GET_CODE (SUBREG_REG (X)) == REG \
1393 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1395 #define LEGITIMATE_INDEX_P(X) \
1396 (LEGITIMATE_INDEX_REG_P (X) \
1397 || ((TARGET_68020 || TARGET_5200) && GET_CODE (X) == MULT \
1398 && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
1399 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1400 && (INTVAL (XEXP (X, 1)) == 2 \
1401 || INTVAL (XEXP (X, 1)) == 4 \
1402 || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_5200))))
1404 /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */
1405 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1406 { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
1407 GO_IF_INDEXED_ADDRESS (X, ADDR); \
1408 if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \
1409 && LEGITIMATE_INDEX_P (XEXP (X, 0)) \
1410 && GET_CODE (XEXP (X, 1)) == LABEL_REF) \
1413 /* Don't call memory_address_noforce for the address to fetch
1414 the switch offset. This address is ok as it stands (see above),
1415 but memory_address_noforce would alter it. */
1416 #define PIC_CASE_VECTOR_ADDRESS(index) index
1418 /* Try machine-dependent ways of modifying an illegitimate address
1419 to be legitimate. If we find one, return the new, valid address.
1420 This macro is used in only one place: `memory_address' in explow.c.
1422 OLDX is the address as it was before break_out_memory_refs was called.
1423 In some cases it is useful to look at this to decide what needs to be done.
1425 MODE and WIN are passed so that this macro can use
1426 GO_IF_LEGITIMATE_ADDRESS.
1428 It is always safe for this macro to do nothing. It exists to recognize
1429 opportunities to optimize the output.
1431 For the 68000, we handle X+REG by loading X into a register R and
1432 using R+REG. R will go in an address reg and indexing will be used.
1433 However, if REG is a broken-out memory address or multiplication,
1434 nothing needs to be done because REG can certainly go in an address reg. */
1436 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1437 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1438 { register int ch = (X) != (OLDX); \
1439 if (GET_CODE (X) == PLUS) \
1441 if (GET_CODE (XEXP (X, 0)) == MULT) \
1442 { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \
1443 if (GET_CODE (XEXP (X, 1)) == MULT) \
1444 { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \
1445 if (ch && GET_CODE (XEXP (X, 1)) == REG \
1446 && GET_CODE (XEXP (X, 0)) == REG) \
1448 if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
1449 if (GET_CODE (XEXP (X, 0)) == REG \
1450 || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
1451 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1452 && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
1453 { register rtx temp = gen_reg_rtx (Pmode); \
1454 register rtx val = force_operand (XEXP (X, 1), 0); \
1455 emit_move_insn (temp, val); \
1457 XEXP (X, 1) = temp; \
1459 else if (GET_CODE (XEXP (X, 1)) == REG \
1460 || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
1461 && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
1462 && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
1463 { register rtx temp = gen_reg_rtx (Pmode); \
1464 register rtx val = force_operand (XEXP (X, 0), 0); \
1465 emit_move_insn (temp, val); \
1467 XEXP (X, 0) = temp; \
1470 /* Go to LABEL if ADDR (a legitimate address expression)
1471 has an effect that depends on the machine mode it is used for.
1472 On the 68000, only predecrement and postincrement address depend thus
1473 (the amount of decrement or increment being the length of the operand). */
1475 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1476 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL
1478 /* Specify the machine mode that this machine uses
1479 for the index in the tablejump instruction. */
1480 #define CASE_VECTOR_MODE HImode
1482 /* Define as C expression which evaluates to nonzero if the tablejump
1483 instruction expects the table to contain offsets from the address of the
1485 Do not define this if the table should contain absolute addresses. */
1486 #define CASE_VECTOR_PC_RELATIVE 1
1488 /* Define this as 1 if `char' should by default be signed; else as 0. */
1489 #define DEFAULT_SIGNED_CHAR 1
1491 /* Don't cse the address of the function being compiled. */
1492 #define NO_RECURSIVE_FUNCTION_CSE
1494 /* Max number of bytes we can move from memory to memory
1495 in one reasonably fast instruction. */
1498 /* Nonzero if access to memory by bytes is slow and undesirable. */
1499 #define SLOW_BYTE_ACCESS 0
1501 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1502 is done just by pretending it is already truncated. */
1503 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1505 /* We assume that the store-condition-codes instructions store 0 for false
1506 and some other value for true. This is the value stored for true. */
1508 #define STORE_FLAG_VALUE (-1)
1510 /* When a prototype says `char' or `short', really pass an `int'. */
1511 #define PROMOTE_PROTOTYPES 1
1513 /* Specify the machine mode that pointers have.
1514 After generation of rtl, the compiler makes no further distinction
1515 between pointers and any other objects of this machine mode. */
1516 #define Pmode SImode
1518 /* A function address in a call instruction
1519 is a byte address (for indexing purposes)
1520 so give the MEM rtx a byte's mode. */
1521 #define FUNCTION_MODE QImode
1524 /* Tell final.c how to eliminate redundant test instructions. */
1526 /* Here we define machine-dependent flags and fields in cc_status
1527 (see `conditions.h'). */
1529 /* Set if the cc value is actually in the 68881, so a floating point
1530 conditional branch must be output. */
1531 #define CC_IN_68881 04000
1533 /* Store in cc_status the expressions that the condition codes will
1534 describe after execution of an instruction whose pattern is EXP.
1535 Do not alter them if the instruction would not alter the cc's. */
1537 /* On the 68000, all the insns to store in an address register fail to
1538 set the cc's. However, in some cases these instructions can make it
1539 possibly invalid to use the saved cc's. In those cases we clear out
1540 some or all of the saved cc's so they won't be used. */
1542 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
1544 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
1545 { if (cc_prev_status.flags & CC_IN_68881) \
1547 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
1551 /* Control the assembler format that we output. */
1553 /* Output at beginning of assembler file. */
1555 #define ASM_FILE_START(FILE) \
1556 fprintf (FILE, "#NO_APP\n");
1558 /* Output to assembler file text saying following lines
1559 may contain character constants, extra white space, comments, etc. */
1561 #define ASM_APP_ON "#APP\n"
1563 /* Output to assembler file text saying following lines
1564 no longer contain unusual constructs. */
1566 #define ASM_APP_OFF "#NO_APP\n"
1568 /* Output before read-only data. */
1570 #define TEXT_SECTION_ASM_OP "\t.text"
1572 /* Output before writable data. */
1574 #define DATA_SECTION_ASM_OP "\t.data"
1576 #define GLOBAL_ASM_OP "\t.globl\t"
1578 /* Here are four prefixes that are used by asm_fprintf to
1579 facilitate customization for alternate assembler syntaxes.
1580 Machines with no likelihood of an alternate syntax need not
1581 define these and need not use asm_fprintf. */
1583 /* The prefix for register names. Note that REGISTER_NAMES
1584 is supposed to include this prefix. */
1586 #define REGISTER_PREFIX ""
1588 /* The prefix for local labels. You should be able to define this as
1589 an empty string, or any arbitrary string (such as ".", ".L%", etc)
1590 without having to make any other changes to account for the specific
1591 definition. Note it is a string literal, not interpreted by printf
1594 #define LOCAL_LABEL_PREFIX ""
1596 /* The prefix to add to user-visible assembler symbols. */
1598 #define USER_LABEL_PREFIX "_"
1600 /* The prefix for immediate operands. */
1602 #define IMMEDIATE_PREFIX "#"
1604 /* How to refer to registers in assembler output.
1605 This sequence is indexed by compiler's hard-register-number (see above). */
1607 #ifndef SUPPORT_SUN_FPA
1609 #define REGISTER_NAMES \
1610 {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \
1611 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \
1612 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7" }
1614 #else /* SUPPORTED_SUN_FPA */
1616 #define REGISTER_NAMES \
1617 {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \
1618 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \
1619 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", \
1620 "fpa0", "fpa1", "fpa2", "fpa3", "fpa4", "fpa5", "fpa6", "fpa7", \
1621 "fpa8", "fpa9", "fpa10", "fpa11", "fpa12", "fpa13", "fpa14", "fpa15", \
1622 "fpa16", "fpa17", "fpa18", "fpa19", "fpa20", "fpa21", "fpa22", "fpa23", \
1623 "fpa24", "fpa25", "fpa26", "fpa27", "fpa28", "fpa29", "fpa30", "fpa31" }
1625 #endif /* defined SUPPORT_SUN_FPA */
1627 /* How to renumber registers for dbx and gdb.
1628 On the Sun-3, the floating point registers have numbers
1629 18 to 25, not 16 to 23 as they do in the compiler. */
1631 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
1633 /* Before the prologue, RA is at 0(%sp). */
1634 #define INCOMING_RETURN_ADDR_RTX \
1635 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
1637 /* We must not use the DBX register numbers for the DWARF 2 CFA column
1638 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
1639 Instead use the identity mapping. */
1640 #define DWARF_FRAME_REGNUM(REG) REG
1642 /* Before the prologue, the top of the frame is at 4(%sp). */
1643 #define INCOMING_FRAME_SP_OFFSET 4
1645 /* Describe how we implement __builtin_eh_return. */
1646 #define EH_RETURN_DATA_REGNO(N) \
1647 ((N) < 2 ? (N) : INVALID_REGNUM)
1648 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 8)
1649 #define EH_RETURN_HANDLER_RTX \
1650 gen_rtx_MEM (Pmode, \
1651 gen_rtx_PLUS (Pmode, arg_pointer_rtx, \
1652 plus_constant (EH_RETURN_STACKADJ_RTX, \
1655 /* Select a format to encode pointers in exception handling data. CODE
1656 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1657 true if the symbol may be affected by dynamic relocations. */
1658 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
1660 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
1663 /* This is how to output a reference to a user-level label named NAME.
1664 `assemble_name' uses this. */
1666 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1667 asm_fprintf (FILE, "%0U%s", NAME)
1669 /* This is how to store into the string LABEL
1670 the symbol_ref name of an internal numbered label where
1671 PREFIX is the class of label and NUM is the number within the class.
1672 This is suitable for output with `assemble_name'. */
1674 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1675 sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM))
1677 /* This is how to output an insn to push a register on the stack.
1678 It need not be very fast code. */
1680 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1681 asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO])
1683 /* This is how to output an insn to pop a register from the stack.
1684 It need not be very fast code. */
1686 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1687 asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO])
1689 /* This is how to output an element of a case-vector that is absolute.
1690 (The 68000 does not use such vectors,
1691 but we must define this macro anyway.) */
1693 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1694 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE)
1696 /* This is how to output an element of a case-vector that is relative. */
1698 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1699 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL)
1701 /* This is how to output an assembler line
1702 that says to advance the location counter
1703 to a multiple of 2**LOG bytes. */
1705 /* We don't have a way to align to more than a two-byte boundary, so do the
1706 best we can and don't complain. */
1707 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1709 fprintf (FILE, "\t.even\n");
1711 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1712 fprintf (FILE, "\t.skip %u\n", (SIZE))
1714 /* This says how to output an assembler line
1715 to define a global common symbol. */
1717 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1718 ( fputs (".comm ", (FILE)), \
1719 assemble_name ((FILE), (NAME)), \
1720 fprintf ((FILE), ",%u\n", (ROUNDED)))
1722 /* This says how to output an assembler line
1723 to define a local common symbol. */
1725 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1726 ( fputs (".lcomm ", (FILE)), \
1727 assemble_name ((FILE), (NAME)), \
1728 fprintf ((FILE), ",%u\n", (ROUNDED)))
1730 /* Output a float value (represented as a C double) as an immediate operand.
1731 This macro is a 68k-specific macro. */
1733 #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
1738 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 9, 0); \
1739 asm_fprintf ((FILE), "%I0r%s", dstr); \
1744 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1745 asm_fprintf ((FILE), "%I0x%lx", l); \
1749 /* Output a double value (represented as a C double) as an immediate operand.
1750 This macro is a 68k-specific macro. */
1751 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
1752 do { char dstr[30]; \
1753 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1754 asm_fprintf (FILE, "%I0r%s", dstr); \
1757 /* Note, long double immediate operands are not actually
1758 generated by m68k.md. */
1759 #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \
1760 do { char dstr[30]; \
1761 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1762 asm_fprintf (FILE, "%I0r%s", dstr); \
1765 /* Print operand X (an rtx) in assembler syntax to file FILE.
1766 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1767 For `%' followed by punctuation, CODE is the punctuation and X is null.
1769 On the 68000, we use several CODE characters:
1770 '.' for dot needed in Motorola-style opcode names.
1771 '-' for an operand pushing on the stack:
1772 sp@-, -(sp) or -(%sp) depending on the style of syntax.
1773 '+' for an operand pushing on the stack:
1774 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
1775 '@' for a reference to the top word on the stack:
1776 sp@, (sp) or (%sp) depending on the style of syntax.
1777 '#' for an immediate operand prefix (# in MIT and Motorola syntax
1778 but & in SGS syntax).
1779 '!' for the fpcr register (used in some float-to-fixed conversions).
1780 '$' for the letter `s' in an op code, but only on the 68040.
1781 '&' for the letter `d' in an op code, but only on the 68040.
1782 '/' for register prefix needed by longlong.h.
1784 'b' for byte insn (no effect, on the Sun; this is for the ISI).
1785 'd' to force memory addressing to be absolute, not relative.
1786 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1787 'o' for operands to go directly to output_operand_address (bypassing
1788 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
1789 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
1790 than directly). Second part of 'y' below.
1791 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
1792 or print pair of registers as rx:ry.
1793 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
1794 CONST_DOUBLE's as SunFPA constant RAM registers if
1795 possible, so it should not be used except for the SunFPA. */
1797 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1798 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
1799 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \
1800 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/')
1802 /* A C compound statement to output to stdio stream STREAM the
1803 assembler syntax for an instruction operand X. X is an RTL
1806 CODE is a value that can be used to specify one of several ways
1807 of printing the operand. It is used when identical operands
1808 must be printed differently depending on the context. CODE
1809 comes from the `%' specification that was used to request
1810 printing of the operand. If the specification was just `%DIGIT'
1811 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
1812 is the ASCII code for LTR.
1814 If X is a register, this macro should print the register's name.
1815 The names can be found in an array `reg_names' whose type is
1816 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
1818 When the machine description has a specification `%PUNCT' (a `%'
1819 followed by a punctuation character), this macro is called with
1820 a null pointer for X and the punctuation character for CODE.
1822 See m68k.c for the m68k specific codes. */
1824 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1826 /* A C compound statement to output to stdio stream STREAM the
1827 assembler syntax for an instruction operand that is a memory
1828 reference whose address is ADDR. ADDR is an RTL expression. */
1830 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1832 /* Variables in m68k.c */
1833 extern const char *m68k_align_loops_string;
1834 extern const char *m68k_align_jumps_string;
1835 extern const char *m68k_align_funcs_string;
1836 extern int m68k_align_loops;
1837 extern int m68k_align_jumps;
1838 extern int m68k_align_funcs;
1839 extern int m68k_last_compare_had_fp_operands;
1842 /* Define the codes that are matched by predicates in m68k.c. */
1844 #define PREDICATE_CODES \
1845 {"general_src_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
1846 LABEL_REF, SUBREG, REG, MEM}}, \
1847 {"nonimmediate_src_operand", {SUBREG, REG, MEM}}, \
1848 {"memory_src_operand", {SUBREG, MEM}}, \
1849 {"not_sp_operand", {SUBREG, REG, MEM}}, \
1850 {"pcrel_address", {SYMBOL_REF, LABEL_REF, CONST}}, \
1851 {"const_uint32_operand", {CONST_INT, CONST_DOUBLE}}, \
1852 {"const_sint32_operand", {CONST_INT}}, \
1853 {"valid_dbcc_comparison_p", {EQ, NE, GTU, LTU, GEU, LEU, \
1855 {"extend_operator", {SIGN_EXTEND, ZERO_EXTEND}},
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