1 /* Definitions of target machine for GCC for Motorola 680x0/ColdFire.
2 Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 /* We need to have MOTOROLA always defined (either 0 or 1) because we use
22 if-statements and ?: on it. This way we have compile-time error checking
23 for both the MOTOROLA and MIT code paths. We do rely on the host compiler
24 to optimize away all constant tests. */
25 #if MOTOROLA /* Use the Motorola assembly syntax. */
26 # define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)")
28 # define MOTOROLA 0 /* Use the MIT assembly syntax. */
29 # define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)")
32 /* Handle --with-cpu default option from configure script. */
33 #define OPTION_DEFAULT_SPECS \
34 { "cpu", "%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:\
35 %{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32:\
36 %{!m68332:%{!m5200:%{!m5206e:%{!m528x:%{!m5307:%{!m5407:%{!mcfv4e:\
37 %{!mcpu=*:%{!march=*:-%(VALUE)}}}}}}}}}}}}}}}}}}}}}" },
39 /* Pass flags to gas indicating which type of processor we have. This
40 can be simplified when we can rely on the assembler supporting .cpu
41 and .arch directives. */
43 #define ASM_CPU_SPEC "\
44 %{m68851}%{mno-68851} %{m68881}%{mno-68881} %{msoft-float:-mno-float} \
45 %{m68000}%{m68302}%{mc68000}%{m68010}%{m68020}%{mc68020}%{m68030}\
46 %{m68040}%{m68020-40:-m68040}%{m68020-60:-m68040}\
47 %{m68060}%{mcpu32}%{m68332}%{m5200}%{m5206e}%{m528x}%{m5307}%{m5407}%{mcfv4e}\
48 %{mcpu=*:-mcpu=%*}%{march=*:-march=%*}\
50 #define ASM_PCREL_SPEC "%{fPIC|fpic|mpcrel:--pcrel} \
51 %{msep-data|mid-shared-library:--pcrel} \
54 #define ASM_SPEC "%(asm_cpu_spec) %(asm_pcrel_spec)"
57 { "asm_cpu_spec", ASM_CPU_SPEC }, \
58 { "asm_pcrel_spec", ASM_PCREL_SPEC }, \
61 #define SUBTARGET_EXTRA_SPECS
63 /* Note that some other tm.h files include this one and then override
64 many of the definitions that relate to assembler syntax. */
66 #define TARGET_CPU_CPP_BUILTINS() \
69 builtin_define ("__m68k__"); \
70 builtin_define_std ("mc68000"); \
71 /* The other mc680x0 macros have traditionally been derived \
72 from the tuning setting. For example, -m68020-60 defines \
73 m68060, even though it generates pure 68020 code. */ \
77 builtin_define_std ("mc68010"); \
81 builtin_define_std ("mc68020"); \
85 builtin_define_std ("mc68030"); \
89 builtin_define_std ("mc68040"); \
93 builtin_define_std ("mc68060"); \
97 builtin_define_std ("mc68060"); \
100 builtin_define_std ("mc68040"); \
101 builtin_define_std ("mc68030"); \
102 builtin_define_std ("mc68020"); \
106 builtin_define_std ("mc68332"); \
107 builtin_define_std ("mcpu32"); \
108 builtin_define_std ("mc68020"); \
112 builtin_define ("__mcfv1__"); \
116 builtin_define ("__mcfv2__"); \
120 builtin_define ("__mcfv3__"); \
124 builtin_define ("__mcfv4__"); \
128 builtin_define ("__mcfv4e__"); \
132 builtin_define ("__mcfv5__"); \
140 builtin_define ("__HAVE_68881__"); \
142 if (TARGET_COLDFIRE) \
146 tmp = m68k_cpp_cpu_ident ("cf"); \
148 builtin_define (tmp); \
149 tmp = m68k_cpp_cpu_family ("cf"); \
151 builtin_define (tmp); \
152 builtin_define ("__mcoldfire__"); \
155 builtin_define ("__mcfisac__"); \
156 else if (TARGET_ISAB) \
158 builtin_define ("__mcfisab__"); \
159 /* ISA_B: Legacy 5407 defines. */ \
160 builtin_define ("__mcf5400__"); \
161 builtin_define ("__mcf5407__"); \
163 else if (TARGET_ISAAPLUS) \
165 builtin_define ("__mcfisaaplus__"); \
166 /* ISA_A+: legacy defines. */ \
167 builtin_define ("__mcf528x__"); \
168 builtin_define ("__mcf5200__"); \
172 builtin_define ("__mcfisaa__"); \
173 /* ISA_A: legacy defines. */ \
177 builtin_define ("__mcf5200__"); \
181 builtin_define ("__mcf5307__"); \
182 builtin_define ("__mcf5300__"); \
191 if (TARGET_COLDFIRE_FPU) \
192 builtin_define ("__mcffpu__"); \
194 if (TARGET_CF_HWDIV) \
195 builtin_define ("__mcfhwdiv__"); \
198 builtin_define ("__mfido__"); \
200 builtin_assert ("cpu=m68k"); \
201 builtin_assert ("machine=m68k"); \
205 /* Classify the groups of pseudo-ops used to assemble QI, HI and SI
207 #define INT_OP_STANDARD 0 /* .byte, .short, .long */
208 #define INT_OP_DOT_WORD 1 /* .byte, .word, .long */
209 #define INT_OP_NO_DOT 2 /* byte, short, long */
210 #define INT_OP_DC 3 /* dc.b, dc.w, dc.l */
212 /* Set the default. */
213 #define INT_OP_GROUP INT_OP_DOT_WORD
215 /* Bit values used by m68k-devices.def to identify processor capabilities. */
216 #define FL_BITFIELD (1 << 0) /* Support bitfield instructions. */
217 #define FL_68881 (1 << 1) /* (Default) support for 68881/2. */
218 #define FL_COLDFIRE (1 << 2) /* ColdFire processor. */
219 #define FL_CF_HWDIV (1 << 3) /* ColdFire hardware divide supported. */
220 #define FL_CF_MAC (1 << 4) /* ColdFire MAC unit supported. */
221 #define FL_CF_EMAC (1 << 5) /* ColdFire eMAC unit supported. */
222 #define FL_CF_EMAC_B (1 << 6) /* ColdFire eMAC-B unit supported. */
223 #define FL_CF_USP (1 << 7) /* ColdFire User Stack Pointer supported. */
224 #define FL_CF_FPU (1 << 8) /* ColdFire FPU supported. */
225 #define FL_ISA_68000 (1 << 9)
226 #define FL_ISA_68010 (1 << 10)
227 #define FL_ISA_68020 (1 << 11)
228 #define FL_ISA_68040 (1 << 12)
229 #define FL_ISA_A (1 << 13)
230 #define FL_ISA_APLUS (1 << 14)
231 #define FL_ISA_B (1 << 15)
232 #define FL_ISA_C (1 << 16)
233 #define FL_FIDOA (1 << 17)
234 #define FL_MMU 0 /* Used by multilib machinery. */
235 #define FL_UCLINUX 0 /* Used by multilib machinery. */
237 #define TARGET_68010 ((m68k_cpu_flags & FL_ISA_68010) != 0)
238 #define TARGET_68020 ((m68k_cpu_flags & FL_ISA_68020) != 0)
239 #define TARGET_68040 ((m68k_cpu_flags & FL_ISA_68040) != 0)
240 #define TARGET_COLDFIRE ((m68k_cpu_flags & FL_COLDFIRE) != 0)
241 #define TARGET_COLDFIRE_FPU (m68k_fpu == FPUTYPE_COLDFIRE)
242 #define TARGET_68881 (m68k_fpu == FPUTYPE_68881)
243 #define TARGET_FIDOA ((m68k_cpu_flags & FL_FIDOA) != 0)
245 /* Size (in bytes) of FPU registers. */
246 #define TARGET_FP_REG_SIZE (TARGET_COLDFIRE ? 8 : 12)
248 #define TARGET_ISAAPLUS ((m68k_cpu_flags & FL_ISA_APLUS) != 0)
249 #define TARGET_ISAB ((m68k_cpu_flags & FL_ISA_B) != 0)
250 #define TARGET_ISAC ((m68k_cpu_flags & FL_ISA_C) != 0)
252 /* Some instructions are common to more than one ISA. */
253 #define ISA_HAS_MVS_MVZ (TARGET_ISAB || TARGET_ISAC)
254 #define ISA_HAS_FF1 (TARGET_ISAAPLUS || TARGET_ISAC)
256 #define TUNE_68000 (m68k_tune == u68000)
257 #define TUNE_68010 (m68k_tune == u68010)
258 #define TUNE_68000_10 (TUNE_68000 || TUNE_68010)
259 #define TUNE_68030 (m68k_tune == u68030 \
260 || m68k_tune == u68020_40 \
261 || m68k_tune == u68020_60)
262 #define TUNE_68040 (m68k_tune == u68040 \
263 || m68k_tune == u68020_40 \
264 || m68k_tune == u68020_60)
265 #define TUNE_68060 (m68k_tune == u68060 || m68k_tune == u68020_60)
266 #define TUNE_68040_60 (TUNE_68040 || TUNE_68060)
267 #define TUNE_CPU32 (m68k_tune == ucpu32)
268 #define TUNE_CFV1 (m68k_tune == ucfv1)
269 #define TUNE_CFV2 (m68k_tune == ucfv2)
270 #define TUNE_CFV3 (m68k_tune == ucfv3)
271 #define TUNE_CFV4 (m68k_tune == ucfv4 || m68k_tune == ucfv4e)
273 #define TUNE_MAC ((m68k_tune_flags & FL_CF_MAC) != 0)
274 #define TUNE_EMAC ((m68k_tune_flags & FL_CF_EMAC) != 0)
276 #define OVERRIDE_OPTIONS override_options()
278 /* These are meant to be redefined in the host dependent files */
279 #define SUBTARGET_OVERRIDE_OPTIONS
281 /* target machine storage layout */
283 /* "long double" is the same as "double" on ColdFire and fido
286 #define LONG_DOUBLE_TYPE_SIZE \
287 ((TARGET_COLDFIRE || TARGET_FIDOA) ? 64 : 80)
289 /* We need to know the size of long double at compile-time in libgcc2. */
291 #if defined(__mcoldfire__) || defined(__mfido__)
292 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
294 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 80
297 /* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
298 instructions, we get proper intermediate rounding, otherwise we
299 get extended precision results. */
300 #define TARGET_FLT_EVAL_METHOD ((TARGET_68040 || ! TARGET_68881) ? 0 : 2)
302 #define BITS_BIG_ENDIAN 1
303 #define BYTES_BIG_ENDIAN 1
304 #define WORDS_BIG_ENDIAN 1
306 #define UNITS_PER_WORD 4
308 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
309 #define STACK_BOUNDARY 16
310 #define FUNCTION_BOUNDARY 16
311 #define EMPTY_FIELD_BOUNDARY 16
312 /* ColdFire and fido strongly prefer a 32-bit aligned stack. */
313 #define PREFERRED_STACK_BOUNDARY \
314 ((TARGET_COLDFIRE || TARGET_FIDOA) ? 32 : 16)
316 /* No data type wants to be aligned rounder than this.
317 Most published ABIs say that ints should be aligned on 16-bit
318 boundaries, but CPUs with 32-bit busses get better performance
319 aligned on 32-bit boundaries. */
320 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
322 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT)
323 #define M68K_HONOR_TARGET_STRICT_ALIGNMENT 1
325 #define DWARF_CIE_DATA_ALIGNMENT -2
327 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
329 /* Define these to avoid dependence on meaning of `int'. */
330 #define WCHAR_TYPE "long int"
331 #define WCHAR_TYPE_SIZE 32
333 /* Maximum number of library IDs we permit with -mid-shared-library. */
334 #define MAX_LIBRARY_ID 255
337 /* Standard register usage. */
339 /* For the m68k, we give the data registers numbers 0-7,
340 the address registers numbers 010-017 (8-15),
341 and the 68881 floating point registers numbers 020-027 (16-23).
342 We also have a fake `arg-pointer' register 030 (24) used for
343 register elimination. */
344 #define FIRST_PSEUDO_REGISTER 25
346 /* All m68k targets (except AmigaOS) use %a5 as the PIC register */
347 #define PIC_OFFSET_TABLE_REGNUM \
348 (!flag_pic ? INVALID_REGNUM \
349 : reload_completed ? REGNO (pic_offset_table_rtx) \
352 /* 1 for registers that have pervasive standard uses
353 and are not available for the register allocator.
354 On the m68k, only the stack pointer is such.
355 Our fake arg-pointer is obviously fixed as well. */
356 #define FIXED_REGISTERS \
357 {/* Data registers. */ \
358 0, 0, 0, 0, 0, 0, 0, 0, \
360 /* Address registers. */ \
361 0, 0, 0, 0, 0, 0, 0, 1, \
363 /* Floating point registers \
365 0, 0, 0, 0, 0, 0, 0, 0, \
370 /* 1 for registers not available across function calls.
371 These must include the FIXED_REGISTERS and also any
372 registers that can be used without being saved.
373 The latter must include the registers where values are returned
374 and the register where structure-value addresses are passed.
375 Aside from that, you can include as many other registers as you like. */
376 #define CALL_USED_REGISTERS \
377 {/* Data registers. */ \
378 1, 1, 0, 0, 0, 0, 0, 0, \
380 /* Address registers. */ \
381 1, 1, 0, 0, 0, 0, 0, 1, \
383 /* Floating point registers \
385 1, 1, 0, 0, 0, 0, 0, 0, \
390 #define REG_ALLOC_ORDER \
391 { /* d0/d1/a0/a1 */ \
396 10, 11, 12, 13, 14, 15, 24, \
398 16, 17, 18, 19, 20, 21, 22, 23\
402 /* Make sure everything's fine if we *don't* have a given processor.
403 This assumes that putting a register in fixed_regs will keep the
404 compiler's mitts completely off it. We don't bother to zero it out
405 of register classes. */
406 #define CONDITIONAL_REGISTER_USAGE \
410 if (!TARGET_HARD_FLOAT) \
412 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
413 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
414 if (TEST_HARD_REG_BIT (x, i)) \
415 fixed_regs[i] = call_used_regs[i] = 1; \
418 fixed_regs[PIC_REG] = call_used_regs[PIC_REG] = 1; \
421 /* On the m68k, ordinary registers hold 32 bits worth;
422 for the 68881 registers, a single register is always enough for
423 anything that can be stored in them at all. */
424 #define HARD_REGNO_NREGS(REGNO, MODE) \
425 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
426 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
428 /* A C expression that is nonzero if hard register NEW_REG can be
429 considered for use as a rename register for OLD_REG register. */
431 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
432 m68k_hard_regno_rename_ok (OLD_REG, NEW_REG)
434 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
435 m68k_regno_mode_ok ((REGNO), (MODE))
437 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
438 m68k_secondary_reload_class (CLASS, MODE, X)
440 #define MODES_TIEABLE_P(MODE1, MODE2) \
441 (! TARGET_HARD_FLOAT \
442 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
443 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
444 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
445 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
447 /* Specify the registers used for certain standard purposes.
448 The values of these macros are register numbers. */
450 #define STACK_POINTER_REGNUM SP_REG
452 /* Most m68k targets use %a6 as a frame pointer. The AmigaOS
453 ABI uses %a6 for shared library calls, therefore the frame
454 pointer is shifted to %a5 on this target. */
455 #define FRAME_POINTER_REGNUM A6_REG
457 /* Base register for access to arguments of the function.
458 * This isn't a hardware register. It will be eliminated to the
459 * stack pointer or frame pointer.
461 #define ARG_POINTER_REGNUM 24
463 #define STATIC_CHAIN_REGNUM A0_REG
464 #define M68K_STATIC_CHAIN_REG_NAME REGISTER_PREFIX "a0"
466 /* Register in which address to store a structure value
467 is passed to a function. */
468 #define M68K_STRUCT_VALUE_REGNUM A1_REG
472 /* The m68k has three kinds of registers, so eight classes would be
473 a complete set. One of them is not needed. */
477 GENERAL_REGS, DATA_OR_FP_REGS,
478 ADDR_OR_FP_REGS, ALL_REGS,
481 #define N_REG_CLASSES (int) LIM_REG_CLASSES
483 #define REG_CLASS_NAMES \
484 { "NO_REGS", "DATA_REGS", \
485 "ADDR_REGS", "FP_REGS", \
486 "GENERAL_REGS", "DATA_OR_FP_REGS", \
487 "ADDR_OR_FP_REGS", "ALL_REGS" }
489 #define REG_CLASS_CONTENTS \
491 {0x00000000}, /* NO_REGS */ \
492 {0x000000ff}, /* DATA_REGS */ \
493 {0x0100ff00}, /* ADDR_REGS */ \
494 {0x00ff0000}, /* FP_REGS */ \
495 {0x0100ffff}, /* GENERAL_REGS */ \
496 {0x00ff00ff}, /* DATA_OR_FP_REGS */ \
497 {0x01ffff00}, /* ADDR_OR_FP_REGS */ \
498 {0x01ffffff}, /* ALL_REGS */ \
501 extern enum reg_class regno_reg_class[];
502 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)])
503 #define INDEX_REG_CLASS GENERAL_REGS
504 #define BASE_REG_CLASS ADDR_REGS
506 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
507 m68k_preferred_reload_class (X, CLASS)
509 /* On the m68k, this is the size of MODE in words,
510 except in the FP regs, where a single reg is always enough. */
511 #define CLASS_MAX_NREGS(CLASS, MODE) \
512 ((CLASS) == FP_REGS ? 1 \
513 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
515 /* Moves between fp regs and other regs are two insns. */
516 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
517 ((((CLASS1) == FP_REGS) != ((CLASS2) == FP_REGS)) ? 4 : 2)
519 #define IRA_COVER_CLASSES \
521 ALL_REGS, LIM_REG_CLASSES \
524 /* Stack layout; function entry, exit and calling. */
526 #define STACK_GROWS_DOWNWARD 1
527 #define FRAME_GROWS_DOWNWARD 1
528 #define STARTING_FRAME_OFFSET 0
530 /* On the 680x0, sp@- in a byte insn really pushes a word.
531 On the ColdFire, sp@- in a byte insn pushes just a byte. */
532 #define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1)
534 #define FIRST_PARM_OFFSET(FNDECL) 8
536 /* On the 68000, the RTS insn cannot pop anything.
537 On the 68010, the RTD insn may be used to pop them if the number
538 of args is fixed, but if the number is variable then the caller
539 must pop them all. RTD can't be used for library calls now
540 because the library is compiled with the Unix compiler.
541 Use of RTD is a selectable option, since it is incompatible with
542 standard Unix calling sequences. If the option is not selected,
543 the caller must always pop the args. */
544 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
545 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \
546 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
547 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
548 == void_type_node))) \
551 /* On the m68k the return value defaults to D0. */
552 #define FUNCTION_VALUE(VALTYPE, FUNC) \
553 gen_rtx_REG (TYPE_MODE (VALTYPE), D0_REG)
555 /* On the m68k the return value defaults to D0. */
556 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, D0_REG)
558 /* On the m68k, D0 is usually the only register used. */
559 #define FUNCTION_VALUE_REGNO_P(N) ((N) == D0_REG)
561 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
562 more than one register.
563 XXX This macro is m68k specific and used only for m68kemb.h. */
564 #define NEEDS_UNTYPED_CALL 0
566 /* On the m68k, all arguments are usually pushed on the stack. */
567 #define FUNCTION_ARG_REGNO_P(N) 0
569 /* On the m68k, this is a single integer, which is a number of bytes
570 of arguments scanned so far. */
571 #define CUMULATIVE_ARGS int
573 /* On the m68k, the offset starts at 0. */
574 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
577 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
578 ((CUM) += ((MODE) != BLKmode \
579 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
580 : (int_size_in_bytes (TYPE) + 3) & ~3))
582 /* On the m68k all args are always pushed. */
583 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
585 #define FUNCTION_PROFILER(FILE, LABELNO) \
586 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO))
588 #define EXIT_IGNORE_STACK 1
590 /* Output assembler code for a block containing the constant parts
591 of a trampoline, leaving space for the variable parts.
593 On the m68k, the trampoline looks like this:
597 WARNING: Targets that may run on 68040+ cpus must arrange for
598 the instruction cache to be flushed. Previous incarnations of
599 the m68k trampoline code attempted to get around this by either
600 using an out-of-line transfer function or pc-relative data, but
601 the fact remains that the code to jump to the transfer function
602 or the code to load the pc-relative data needs to be flushed
603 just as much as the "variable" portion of the trampoline.
604 Recognizing that a cache flush is going to be required anyway,
605 dispense with such notions and build a smaller trampoline.
607 Since more instructions are required to move a template into
608 place than to create it on the spot, don't use a template. */
610 #define TRAMPOLINE_SIZE 12
611 #define TRAMPOLINE_ALIGNMENT 16
613 /* Targets redefine this to invoke code to either flush the cache,
614 or enable stack execution (or both). */
615 #ifndef FINALIZE_TRAMPOLINE
616 #define FINALIZE_TRAMPOLINE(TRAMP)
619 /* We generate a two-instructions program at address TRAMP :
622 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
624 emit_move_insn (gen_rtx_MEM (HImode, TRAMP), \
625 GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM-8) << 9))); \
626 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \
627 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \
629 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \
630 FINALIZE_TRAMPOLINE(TRAMP); \
633 /* This is the library routine that is used to transfer control from the
634 trampoline to the actual nested function. It is defined for backward
635 compatibility, for linking with object code that used the old trampoline
638 A colon is used with no explicit operands to cause the template string
639 to be scanned for %-constructs.
641 The function name __transfer_from_trampoline is not actually used.
642 The function definition just permits use of "asm with operands"
643 (though the operand list is empty). */
644 #define TRANSFER_FROM_TRAMPOLINE \
646 __transfer_from_trampoline () \
648 register char *a0 asm (M68K_STATIC_CHAIN_REG_NAME); \
649 asm (GLOBAL_ASM_OP "___trampoline"); \
650 asm ("___trampoline:"); \
651 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \
652 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \
656 /* There are two registers that can always be eliminated on the m68k.
657 The frame pointer and the arg pointer can be replaced by either the
658 hard frame pointer or to the stack pointer, depending upon the
659 circumstances. The hard frame pointer is not used before reload and
660 so it is not eligible for elimination. */
661 #define ELIMINABLE_REGS \
662 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
663 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
664 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
666 #define CAN_ELIMINATE(FROM, TO) \
667 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
669 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
670 (OFFSET) = m68k_initial_elimination_offset(FROM, TO)
672 /* Addressing modes, and classification of registers for them. */
674 #define HAVE_POST_INCREMENT 1
675 #define HAVE_PRE_DECREMENT 1
677 /* Macros to check register numbers against specific register classes. */
679 /* True for data registers, D0 through D7. */
680 #define DATA_REGNO_P(REGNO) IN_RANGE (REGNO, 0, 7)
682 /* True for address registers, A0 through A7. */
683 #define ADDRESS_REGNO_P(REGNO) IN_RANGE (REGNO, 8, 15)
685 /* True for integer registers, D0 through D7 and A0 through A7. */
686 #define INT_REGNO_P(REGNO) IN_RANGE (REGNO, 0, 15)
688 /* True for floating point registers, FP0 through FP7. */
689 #define FP_REGNO_P(REGNO) IN_RANGE (REGNO, 16, 23)
691 #define REGNO_OK_FOR_INDEX_P(REGNO) \
692 (INT_REGNO_P (REGNO) \
693 || INT_REGNO_P (reg_renumber[REGNO]))
695 #define REGNO_OK_FOR_BASE_P(REGNO) \
696 (ADDRESS_REGNO_P (REGNO) \
697 || ADDRESS_REGNO_P (reg_renumber[REGNO]))
699 #define REGNO_OK_FOR_INDEX_NONSTRICT_P(REGNO) \
700 (INT_REGNO_P (REGNO) \
701 || REGNO == ARG_POINTER_REGNUM \
702 || REGNO >= FIRST_PSEUDO_REGISTER)
704 #define REGNO_OK_FOR_BASE_NONSTRICT_P(REGNO) \
705 (ADDRESS_REGNO_P (REGNO) \
706 || REGNO == ARG_POINTER_REGNUM \
707 || REGNO >= FIRST_PSEUDO_REGISTER)
709 /* Now macros that check whether X is a register and also,
710 strictly, whether it is in a specified class.
712 These macros are specific to the m68k, and may be used only
713 in code for printing assembler insns and in conditions for
714 define_optimization. */
716 /* 1 if X is a data register. */
717 #define DATA_REG_P(X) (REG_P (X) && DATA_REGNO_P (REGNO (X)))
719 /* 1 if X is an fp register. */
720 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
722 /* 1 if X is an address register */
723 #define ADDRESS_REG_P(X) (REG_P (X) && ADDRESS_REGNO_P (REGNO (X)))
725 /* True if SYMBOL + OFFSET constants must refer to something within
727 #ifndef M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
728 #define M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
731 #define MAX_REGS_PER_ADDRESS 2
733 #define CONSTANT_ADDRESS_P(X) \
734 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
735 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
736 || GET_CODE (X) == HIGH) \
737 && LEGITIMATE_CONSTANT_P (X))
739 /* Nonzero if the constant value X is a legitimate general operand.
740 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
741 #define LEGITIMATE_CONSTANT_P(X) \
742 (GET_MODE (X) != XFmode \
743 && !m68k_illegitimate_symbolic_constant_p (X))
745 #ifndef REG_OK_STRICT
746 #define REG_STRICT_P 0
748 #define REG_STRICT_P 1
751 #define LEGITIMATE_PIC_OPERAND_P(X) \
752 (!symbolic_operand (X, VOIDmode) \
753 || (TARGET_PCREL && REG_STRICT_P) \
754 || m68k_tls_reference_p (X, true))
756 #define REG_OK_FOR_BASE_P(X) \
757 m68k_legitimate_base_reg_p (X, REG_STRICT_P)
759 #define REG_OK_FOR_INDEX_P(X) \
760 m68k_legitimate_index_reg_p (X, REG_STRICT_P)
763 /* This address is OK as it stands. */
764 #define PIC_CASE_VECTOR_ADDRESS(index) index
765 #define CASE_VECTOR_MODE HImode
766 #define CASE_VECTOR_PC_RELATIVE 1
768 #define DEFAULT_SIGNED_CHAR 1
770 #define SLOW_BYTE_ACCESS 0
772 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
774 /* The ColdFire FF1 instruction returns 32 for zero. */
775 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
777 #define STORE_FLAG_VALUE (-1)
780 #define FUNCTION_MODE QImode
783 /* Tell final.c how to eliminate redundant test instructions. */
785 /* Here we define machine-dependent flags and fields in cc_status
786 (see `conditions.h'). */
788 /* Set if the cc value is actually in the 68881, so a floating point
789 conditional branch must be output. */
790 #define CC_IN_68881 04000
792 /* On the 68000, all the insns to store in an address register fail to
793 set the cc's. However, in some cases these instructions can make it
794 possibly invalid to use the saved cc's. In those cases we clear out
795 some or all of the saved cc's so they won't be used. */
796 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
798 /* The shift instructions always clear the overflow bit. */
799 #define CC_OVERFLOW_UNUSABLE 01000
801 /* The shift instructions use the carry bit in a way not compatible with
802 conditional branches. conditions.h uses CC_NO_OVERFLOW for this purpose.
803 Rename it to something more understandable. */
804 #define CC_NO_CARRY CC_NO_OVERFLOW
806 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
807 do { if (cc_prev_status.flags & CC_IN_68881) \
809 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
811 return NORMAL; } while (0)
813 /* Control the assembler format that we output. */
815 #define ASM_APP_ON "#APP\n"
816 #define ASM_APP_OFF "#NO_APP\n"
817 #define TEXT_SECTION_ASM_OP "\t.text"
818 #define DATA_SECTION_ASM_OP "\t.data"
819 #define GLOBAL_ASM_OP "\t.globl\t"
820 #define REGISTER_PREFIX ""
821 #define LOCAL_LABEL_PREFIX ""
822 #define USER_LABEL_PREFIX "_"
823 #define IMMEDIATE_PREFIX "#"
825 #define REGISTER_NAMES \
826 {REGISTER_PREFIX"d0", REGISTER_PREFIX"d1", REGISTER_PREFIX"d2", \
827 REGISTER_PREFIX"d3", REGISTER_PREFIX"d4", REGISTER_PREFIX"d5", \
828 REGISTER_PREFIX"d6", REGISTER_PREFIX"d7", \
829 REGISTER_PREFIX"a0", REGISTER_PREFIX"a1", REGISTER_PREFIX"a2", \
830 REGISTER_PREFIX"a3", REGISTER_PREFIX"a4", REGISTER_PREFIX"a5", \
831 REGISTER_PREFIX"a6", REGISTER_PREFIX"sp", \
832 REGISTER_PREFIX"fp0", REGISTER_PREFIX"fp1", REGISTER_PREFIX"fp2", \
833 REGISTER_PREFIX"fp3", REGISTER_PREFIX"fp4", REGISTER_PREFIX"fp5", \
834 REGISTER_PREFIX"fp6", REGISTER_PREFIX"fp7", REGISTER_PREFIX"argptr" }
836 #define M68K_FP_REG_NAME REGISTER_PREFIX"fp"
838 /* Return a register name by index, handling %fp nicely.
839 We don't replace %fp for targets that don't map it to %a6
840 since it may confuse GAS. */
841 #define M68K_REGNAME(r) ( \
842 ((FRAME_POINTER_REGNUM == A6_REG) \
843 && ((r) == FRAME_POINTER_REGNUM) \
844 && frame_pointer_needed) ? \
845 M68K_FP_REG_NAME : reg_names[(r)])
847 /* On the Sun-3, the floating point registers have numbers
848 18 to 25, not 16 to 23 as they do in the compiler. */
849 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
851 /* Before the prologue, RA is at 0(%sp). */
852 #define INCOMING_RETURN_ADDR_RTX \
853 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
855 /* After the prologue, RA is at 4(AP) in the current frame. */
856 #define RETURN_ADDR_RTX(COUNT, FRAME) \
858 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, UNITS_PER_WORD)) \
859 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
861 /* We must not use the DBX register numbers for the DWARF 2 CFA column
862 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
863 Instead use the identity mapping. */
864 #define DWARF_FRAME_REGNUM(REG) \
865 (INT_REGNO_P (REG) || FP_REGNO_P (REG) ? (REG) : INVALID_REGNUM)
867 /* The return column was originally 24, but gcc used 25 for a while too.
868 Define both registers 24 and 25 as Pmode ones and use 24 in our own
869 unwind information. */
870 #define DWARF_FRAME_REGISTERS 25
871 #define DWARF_FRAME_RETURN_COLUMN 24
872 #define DWARF_ALT_FRAME_RETURN_COLUMN 25
874 /* Before the prologue, the top of the frame is at 4(%sp). */
875 #define INCOMING_FRAME_SP_OFFSET 4
877 /* All registers are live on exit from an interrupt routine. */
878 #define EPILOGUE_USES(REGNO) \
880 && (m68k_get_function_kind (current_function_decl) \
881 == m68k_fk_interrupt_handler))
883 /* Describe how we implement __builtin_eh_return. */
884 #define EH_RETURN_DATA_REGNO(N) \
885 ((N) < 2 ? (N) : INVALID_REGNUM)
886 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, A0_REG)
887 #define EH_RETURN_HANDLER_RTX \
888 gen_rtx_MEM (Pmode, \
889 gen_rtx_PLUS (Pmode, arg_pointer_rtx, \
890 plus_constant (EH_RETURN_STACKADJ_RTX, \
893 /* Select a format to encode pointers in exception handling data. CODE
894 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
895 true if the symbol may be affected by dynamic relocations.
897 TARGET_ID_SHARED_LIBRARY and TARGET_SEP_DATA are designed to support
898 a read-only text segment without imposing a fixed gap between the
899 text and data segments. As a result, the text segment cannot refer
900 to anything in the data segment, even in PC-relative form. Because
901 .eh_frame refers to both code and data, it follows that .eh_frame
902 must be in the data segment itself, and that the offset between
903 .eh_frame and code will not be a link-time constant.
905 In theory, we could create a read-only .eh_frame by using DW_EH_PE_pcrel
906 | DW_EH_PE_indirect for all code references. However, gcc currently
907 handles indirect references using a per-TU constant pool. This means
908 that if a function and its eh_frame are removed by the linker, the
909 eh_frame's indirect references to the removed function will not be
910 removed, leading to an unresolved symbol error.
912 It isn't clear that any -msep-data or -mid-shared-library target
913 would benefit from a read-only .eh_frame anyway. In particular,
914 no known target that supports these options has a feature like
915 PT_GNU_RELRO. Without any such feature to motivate them, indirect
916 references would be unnecessary bloat, so we simply use an absolute
917 pointer for code and global references. We still use pc-relative
918 references to data, as this avoids a relocation. */
919 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
921 && !((TARGET_ID_SHARED_LIBRARY || TARGET_SEP_DATA) \
922 && ((GLOBAL) || (CODE))) \
923 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
926 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
927 asm_fprintf (FILE, "%U%s", NAME)
929 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
930 sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM))
932 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
933 asm_fprintf (FILE, (MOTOROLA \
934 ? "\tmove.l %s,-(%Rsp)\n" \
935 : "\tmovel %s,%Rsp@-\n"), \
938 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
939 asm_fprintf (FILE, (MOTOROLA \
940 ? "\tmove.l (%Rsp)+,%s\n" \
941 : "\tmovel %Rsp@+,%s\n"), \
944 /* The m68k does not use absolute case-vectors, but we must define this macro
946 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
947 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE)
949 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
950 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL)
952 /* We don't have a way to align to more than a two-byte boundary, so do the
953 best we can and don't complain. */
954 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
956 fprintf (FILE, "\t.even\n");
958 #ifdef HAVE_GAS_BALIGN_AND_P2ALIGN
959 /* Use "move.l %a4,%a4" to advance within code. */
960 #define ASM_OUTPUT_ALIGN_WITH_NOP(FILE,LOG) \
962 fprintf ((FILE), "\t.balignw %u,0x284c\n", 1 << (LOG));
965 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
966 fprintf (FILE, "\t.skip %u\n", (int)(SIZE))
968 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
969 ( fputs (".comm ", (FILE)), \
970 assemble_name ((FILE), (NAME)), \
971 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
973 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
974 ( fputs (".lcomm ", (FILE)), \
975 assemble_name ((FILE), (NAME)), \
976 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
978 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
979 m68k_final_prescan_insn (INSN, OPVEC, NOPERANDS)
981 /* On the 68000, we use several CODE characters:
982 '.' for dot needed in Motorola-style opcode names.
983 '-' for an operand pushing on the stack:
984 sp@-, -(sp) or -(%sp) depending on the style of syntax.
985 '+' for an operand pushing on the stack:
986 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
987 '@' for a reference to the top word on the stack:
988 sp@, (sp) or (%sp) depending on the style of syntax.
989 '#' for an immediate operand prefix (# in MIT and Motorola syntax
990 but & in SGS syntax).
991 '!' for the fpcr register (used in some float-to-fixed conversions).
992 '$' for the letter `s' in an op code, but only on the 68040.
993 '&' for the letter `d' in an op code, but only on the 68040.
994 '/' for register prefix needed by longlong.h.
995 '?' for m68k_library_id_string
997 'b' for byte insn (no effect, on the Sun; this is for the ISI).
998 'd' to force memory addressing to be absolute, not relative.
999 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1000 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
1001 or print pair of registers as rx:ry. */
1003 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1004 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
1005 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \
1006 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/' || (CODE) == '?')
1009 /* See m68k.c for the m68k specific codes. */
1010 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1012 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1014 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
1016 if (! m68k_output_addr_const_extra (FILE, (X))) \
1020 /* Values used in the MICROARCH argument to M68K_DEVICE. */
1041 /* An enumeration of all supported target devices. */
1044 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
1046 #include "m68k-devices.def"
1058 enum m68k_function_kind
1060 m68k_fk_normal_function,
1061 m68k_fk_interrupt_handler,
1062 m68k_fk_interrupt_thread
1065 /* Variables in m68k.c; see there for details. */
1066 extern const char *m68k_library_id_string;
1067 extern enum target_device m68k_cpu;
1068 extern enum uarch_type m68k_tune;
1069 extern enum fpu_type m68k_fpu;
1070 extern unsigned int m68k_cpu_flags;
1071 extern unsigned int m68k_tune_flags;
1072 extern const char *m68k_symbolic_call;
1073 extern const char *m68k_symbolic_jump;
1075 enum M68K_SYMBOLIC_CALL { M68K_SYMBOLIC_CALL_NONE, M68K_SYMBOLIC_CALL_JSR,
1076 M68K_SYMBOLIC_CALL_BSR_C, M68K_SYMBOLIC_CALL_BSR_P };
1078 extern enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var;
1080 /* ??? HOST_WIDE_INT is not being defined for auto-generated files.
1082 #ifdef HOST_WIDE_INT
1083 typedef enum { MOVL, SWAP, NEGW, NOTW, NOTB, MOVQ, MVS, MVZ }
1086 extern M68K_CONST_METHOD m68k_const_method (HOST_WIDE_INT);
1089 extern void m68k_emit_move_double (rtx [2]);
1091 extern int m68k_sched_address_bypass_p (rtx, rtx);
1092 extern int m68k_sched_indexed_address_bypass_p (rtx, rtx);
1094 #define CPU_UNITS_QUERY 1