1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
42 #include "target-def.h"
47 enum reg_class regno_reg_class[] =
49 DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS,
50 DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS,
51 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
52 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
53 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
54 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
59 /* The minimum number of integer registers that we want to save with the
60 movem instruction. Using two movel instructions instead of a single
61 moveml is about 15% faster for the 68020 and 68030 at no expense in
63 #define MIN_MOVEM_REGS 3
65 /* The minimum number of floating point registers that we want to save
66 with the fmovem instruction. */
67 #define MIN_FMOVEM_REGS 1
69 /* Structure describing stack frame layout. */
72 /* Stack pointer to frame pointer offset. */
75 /* Offset of FPU registers. */
76 HOST_WIDE_INT foffset;
78 /* Frame size in bytes (rounded up). */
81 /* Data and address register. */
83 unsigned int reg_mask;
87 unsigned int fpu_mask;
89 /* Offsets relative to ARG_POINTER. */
90 HOST_WIDE_INT frame_pointer_offset;
91 HOST_WIDE_INT stack_pointer_offset;
93 /* Function which the above information refers to. */
97 /* Current frame information calculated by m68k_compute_frame_layout(). */
98 static struct m68k_frame current_frame;
100 /* Structure describing an m68k address.
102 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
103 with null fields evaluating to 0. Here:
105 - BASE satisfies m68k_legitimate_base_reg_p
106 - INDEX satisfies m68k_legitimate_index_reg_p
107 - OFFSET satisfies m68k_legitimate_constant_address_p
109 INDEX is either HImode or SImode. The other fields are SImode.
111 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
112 the address is (BASE)+. */
113 struct m68k_address {
121 static bool m68k_handle_option (size_t, const char *, int);
122 static rtx find_addr_reg (rtx);
123 static const char *singlemove_string (rtx *);
124 #ifdef M68K_TARGET_COFF
125 static void m68k_coff_asm_named_section (const char *, unsigned int, tree);
126 #endif /* M68K_TARGET_COFF */
127 static void m68k_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
128 HOST_WIDE_INT, tree);
129 static rtx m68k_struct_value_rtx (tree, int);
130 static tree m68k_handle_fndecl_attribute (tree *node, tree name,
131 tree args, int flags,
133 static void m68k_compute_frame_layout (void);
134 static bool m68k_save_reg (unsigned int regno, bool interrupt_handler);
135 static bool m68k_ok_for_sibcall_p (tree, tree);
136 static bool m68k_rtx_costs (rtx, int, int, int *);
137 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
138 static bool m68k_return_in_memory (tree, tree);
142 /* Specify the identification number of the library being built */
143 const char *m68k_library_id_string = "_current_shared_library_a5_offset_";
145 /* Nonzero if the last compare/test insn had FP operands. The
146 sCC expanders peek at this to determine what to do for the
147 68060, which has no fsCC instructions. */
148 int m68k_last_compare_had_fp_operands;
150 /* Initialize the GCC target structure. */
152 #if INT_OP_GROUP == INT_OP_DOT_WORD
153 #undef TARGET_ASM_ALIGNED_HI_OP
154 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
157 #if INT_OP_GROUP == INT_OP_NO_DOT
158 #undef TARGET_ASM_BYTE_OP
159 #define TARGET_ASM_BYTE_OP "\tbyte\t"
160 #undef TARGET_ASM_ALIGNED_HI_OP
161 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
162 #undef TARGET_ASM_ALIGNED_SI_OP
163 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
166 #if INT_OP_GROUP == INT_OP_DC
167 #undef TARGET_ASM_BYTE_OP
168 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
169 #undef TARGET_ASM_ALIGNED_HI_OP
170 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
171 #undef TARGET_ASM_ALIGNED_SI_OP
172 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
175 #undef TARGET_ASM_UNALIGNED_HI_OP
176 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
177 #undef TARGET_ASM_UNALIGNED_SI_OP
178 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
180 #undef TARGET_ASM_OUTPUT_MI_THUNK
181 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
182 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
183 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
185 #undef TARGET_ASM_FILE_START_APP_OFF
186 #define TARGET_ASM_FILE_START_APP_OFF true
188 #undef TARGET_HANDLE_OPTION
189 #define TARGET_HANDLE_OPTION m68k_handle_option
191 #undef TARGET_RTX_COSTS
192 #define TARGET_RTX_COSTS m68k_rtx_costs
194 #undef TARGET_ATTRIBUTE_TABLE
195 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
197 #undef TARGET_PROMOTE_PROTOTYPES
198 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
200 #undef TARGET_STRUCT_VALUE_RTX
201 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
203 #undef TARGET_CANNOT_FORCE_CONST_MEM
204 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_illegitimate_symbolic_constant_p
206 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
207 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
209 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
210 #undef TARGET_RETURN_IN_MEMORY
211 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
214 static const struct attribute_spec m68k_attribute_table[] =
216 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
217 { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute },
218 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute },
219 { "interrupt_thread", 0, 0, true, false, false, m68k_handle_fndecl_attribute },
220 { NULL, 0, 0, false, false, false, NULL }
223 struct gcc_target targetm = TARGET_INITIALIZER;
225 /* Base flags for 68k ISAs. */
226 #define FL_FOR_isa_00 FL_ISA_68000
227 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
228 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
229 generated 68881 code for 68020 and 68030 targets unless explicitly told
231 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
232 | FL_BITFIELD | FL_68881)
233 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
234 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
236 /* Base flags for ColdFire ISAs. */
237 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
238 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
239 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
240 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
241 /* ISA_C is not upwardly compatible with ISA_B. */
242 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
246 /* Traditional 68000 instruction sets. */
252 /* ColdFire instruction set variants. */
260 /* Information about one of the -march, -mcpu or -mtune arguments. */
261 struct m68k_target_selection
263 /* The argument being described. */
266 /* For -mcpu, this is the device selected by the option.
267 For -mtune and -march, it is a representative device
268 for the microarchitecture or ISA respectively. */
269 enum target_device device;
271 /* The M68K_DEVICE fields associated with DEVICE. See the comment
272 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
274 enum uarch_type microarch;
279 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
280 static const struct m68k_target_selection all_devices[] =
282 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
283 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
284 #include "m68k-devices.def"
286 { NULL, unk_device, NULL, unk_arch, isa_max, 0 }
289 /* A list of all ISAs, mapping each one to a representative device.
290 Used for -march selection. */
291 static const struct m68k_target_selection all_isas[] =
293 { "68000", m68000, NULL, u68000, isa_00, FL_FOR_isa_00 },
294 { "68010", m68010, NULL, u68010, isa_10, FL_FOR_isa_10 },
295 { "68020", m68020, NULL, u68020, isa_20, FL_FOR_isa_20 },
296 { "68030", m68030, NULL, u68030, isa_20, FL_FOR_isa_20 },
297 { "68040", m68040, NULL, u68040, isa_40, FL_FOR_isa_40 },
298 { "68060", m68060, NULL, u68060, isa_40, FL_FOR_isa_40 },
299 { "cpu32", cpu32, NULL, ucpu32, isa_20, FL_FOR_isa_cpu32 },
300 { "isaa", mcf5206e, NULL, ucfv2, isa_a, (FL_FOR_isa_a
302 { "isaaplus", mcf5271, NULL, ucfv2, isa_aplus, (FL_FOR_isa_aplus
304 { "isab", mcf5407, NULL, ucfv4, isa_b, FL_FOR_isa_b },
305 { "isac", unk_device, NULL, ucfv4, isa_c, (FL_FOR_isa_c
307 { NULL, unk_device, NULL, unk_arch, isa_max, 0 }
310 /* A list of all microarchitectures, mapping each one to a representative
311 device. Used for -mtune selection. */
312 static const struct m68k_target_selection all_microarchs[] =
314 { "68000", m68000, NULL, u68000, isa_00, FL_FOR_isa_00 },
315 { "68010", m68010, NULL, u68010, isa_10, FL_FOR_isa_10 },
316 { "68020", m68020, NULL, u68020, isa_20, FL_FOR_isa_20 },
317 { "68020-40", m68020, NULL, u68020_40, isa_20, FL_FOR_isa_20 },
318 { "68020-60", m68020, NULL, u68020_60, isa_20, FL_FOR_isa_20 },
319 { "68030", m68030, NULL, u68030, isa_20, FL_FOR_isa_20 },
320 { "68040", m68040, NULL, u68040, isa_40, FL_FOR_isa_40 },
321 { "68060", m68060, NULL, u68060, isa_40, FL_FOR_isa_40 },
322 { "cpu32", cpu32, NULL, ucpu32, isa_20, FL_FOR_isa_cpu32 },
323 { "cfv1", mcf51qe, NULL, ucfv1, isa_c, FL_FOR_isa_c },
324 { "cfv2", mcf5206, NULL, ucfv2, isa_a, FL_FOR_isa_a },
325 { "cfv3", mcf5307, NULL, ucfv3, isa_a, (FL_FOR_isa_a
327 { "cfv4", mcf5407, NULL, ucfv4, isa_b, FL_FOR_isa_b },
328 { "cfv4e", mcf547x, NULL, ucfv4e, isa_b, (FL_FOR_isa_b
332 { NULL, unk_device, NULL, unk_arch, isa_max, 0 }
335 /* The entries associated with the -mcpu, -march and -mtune settings,
336 or null for options that have not been used. */
337 const struct m68k_target_selection *m68k_cpu_entry;
338 const struct m68k_target_selection *m68k_arch_entry;
339 const struct m68k_target_selection *m68k_tune_entry;
341 /* Which CPU we are generating code for. */
342 enum target_device m68k_cpu;
344 /* Which microarchitecture to tune for. */
345 enum uarch_type m68k_tune;
347 /* Which FPU to use. */
348 enum fpu_type m68k_fpu;
350 /* The set of FL_* flags that apply to the target processor. */
351 unsigned int m68k_cpu_flags;
353 /* Asm templates for calling or jumping to an arbitrary symbolic address,
354 or NULL if such calls or jumps are not supported. The address is held
356 const char *m68k_symbolic_call;
357 const char *m68k_symbolic_jump;
359 /* Enum variable that corresponds to m68k_symbolic_call values. */
360 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var;
363 /* See whether TABLE has an entry with name NAME. Return true and
364 store the entry in *ENTRY if so, otherwise return false and
365 leave *ENTRY alone. */
368 m68k_find_selection (const struct m68k_target_selection **entry,
369 const struct m68k_target_selection *table,
374 for (i = 0; table[i].name; i++)
375 if (strcmp (table[i].name, name) == 0)
383 /* Implement TARGET_HANDLE_OPTION. */
386 m68k_handle_option (size_t code, const char *arg, int value)
391 return m68k_find_selection (&m68k_arch_entry, all_isas, arg);
394 return m68k_find_selection (&m68k_cpu_entry, all_devices, arg);
397 return m68k_find_selection (&m68k_tune_entry, all_microarchs, arg);
400 return m68k_find_selection (&m68k_cpu_entry, all_devices, "5206");
403 return m68k_find_selection (&m68k_cpu_entry, all_devices, "5206e");
406 return m68k_find_selection (&m68k_cpu_entry, all_devices, "528x");
409 return m68k_find_selection (&m68k_cpu_entry, all_devices, "5307");
412 return m68k_find_selection (&m68k_cpu_entry, all_devices, "5407");
415 return m68k_find_selection (&m68k_cpu_entry, all_devices, "547x");
419 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68000");
422 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68010");
426 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68020");
429 return (m68k_find_selection (&m68k_tune_entry, all_microarchs,
431 && m68k_find_selection (&m68k_cpu_entry, all_devices, "68020"));
434 return (m68k_find_selection (&m68k_tune_entry, all_microarchs,
436 && m68k_find_selection (&m68k_cpu_entry, all_devices, "68020"));
439 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68030");
442 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68040");
445 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68060");
448 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68302");
452 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68332");
454 case OPT_mshared_library_id_:
455 if (value > MAX_LIBRARY_ID)
456 error ("-mshared-library-id=%s is not between 0 and %d",
457 arg, MAX_LIBRARY_ID);
459 asprintf ((char **) &m68k_library_id_string, "%d", (value * -4) - 4);
467 /* Sometimes certain combinations of command options do not make
468 sense on a particular target machine. You can define a macro
469 `OVERRIDE_OPTIONS' to take account of this. This macro, if
470 defined, is executed once just after all the command options have
473 Don't use this macro to turn on various extra optimizations for
474 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
477 override_options (void)
479 const struct m68k_target_selection *entry;
480 unsigned long target_mask;
488 -march=ARCH should generate code that runs any processor
489 implementing architecture ARCH. -mcpu=CPU should override -march
490 and should generate code that runs on processor CPU, making free
491 use of any instructions that CPU understands. -mtune=UARCH applies
492 on top of -mcpu or -march and optimizes the code for UARCH. It does
493 not change the target architecture. */
496 /* Complain if the -march setting is for a different microarchitecture,
497 or includes flags that the -mcpu setting doesn't. */
499 && (m68k_arch_entry->microarch != m68k_cpu_entry->microarch
500 || (m68k_arch_entry->flags & ~m68k_cpu_entry->flags) != 0))
501 warning (0, "-mcpu=%s conflicts with -march=%s",
502 m68k_cpu_entry->name, m68k_arch_entry->name);
504 entry = m68k_cpu_entry;
507 entry = m68k_arch_entry;
510 entry = all_devices + TARGET_CPU_DEFAULT;
512 m68k_cpu_flags = entry->flags;
514 /* Use the architecture setting to derive default values for
518 /* ColdFire is lenient about alignment. */
519 if (!TARGET_COLDFIRE)
520 target_mask |= MASK_STRICT_ALIGNMENT;
522 if ((m68k_cpu_flags & FL_BITFIELD) != 0)
523 target_mask |= MASK_BITFIELD;
524 if ((m68k_cpu_flags & FL_CF_HWDIV) != 0)
525 target_mask |= MASK_CF_HWDIV;
526 if ((m68k_cpu_flags & (FL_68881 | FL_CF_FPU)) != 0)
527 target_mask |= MASK_HARD_FLOAT;
528 target_flags |= target_mask & ~target_flags_explicit;
530 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
531 m68k_cpu = entry->device;
533 m68k_tune = m68k_tune_entry->microarch;
534 #ifdef M68K_DEFAULT_TUNE
535 else if (!m68k_cpu_entry && !m68k_arch_entry)
536 m68k_tune = M68K_DEFAULT_TUNE;
539 m68k_tune = entry->microarch;
541 /* Set the type of FPU. */
542 m68k_fpu = (!TARGET_HARD_FLOAT ? FPUTYPE_NONE
543 : (m68k_cpu_flags & FL_COLDFIRE) != 0 ? FPUTYPE_COLDFIRE
546 /* Sanity check to ensure that msep-data and mid-sahred-library are not
547 * both specified together. Doing so simply doesn't make sense.
549 if (TARGET_SEP_DATA && TARGET_ID_SHARED_LIBRARY)
550 error ("cannot specify both -msep-data and -mid-shared-library");
552 /* If we're generating code for a separate A5 relative data segment,
553 * we've got to enable -fPIC as well. This might be relaxable to
554 * -fpic but it hasn't been tested properly.
556 if (TARGET_SEP_DATA || TARGET_ID_SHARED_LIBRARY)
559 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
560 error if the target does not support them. */
561 if (TARGET_PCREL && !TARGET_68020 && flag_pic == 2)
562 error ("-mpcrel -fPIC is not currently supported on selected cpu");
564 /* ??? A historic way of turning on pic, or is this intended to
565 be an embedded thing that doesn't have the same name binding
566 significance that it does on hosted ELF systems? */
567 if (TARGET_PCREL && flag_pic == 0)
572 m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_JSR;
574 m68k_symbolic_jump = "jra %a0";
576 else if (TARGET_ID_SHARED_LIBRARY)
577 /* All addresses must be loaded from the GOT. */
579 else if (TARGET_68020 || TARGET_ISAB || TARGET_ISAC)
582 m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_BSR_C;
584 m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_BSR_P;
587 /* No unconditional long branch */;
588 else if (TARGET_PCREL)
589 m68k_symbolic_jump = "bra%.l %c0";
591 m68k_symbolic_jump = "bra%.l %p0";
592 /* Turn off function cse if we are doing PIC. We always want
593 function call to be done as `bsr foo@PLTPC'. */
594 /* ??? It's traditional to do this for -mpcrel too, but it isn't
595 clear how intentional that is. */
596 flag_no_function_cse = 1;
599 switch (m68k_symbolic_call_var)
601 case M68K_SYMBOLIC_CALL_JSR:
602 m68k_symbolic_call = "jsr %a0";
605 case M68K_SYMBOLIC_CALL_BSR_C:
606 m68k_symbolic_call = "bsr%.l %c0";
609 case M68K_SYMBOLIC_CALL_BSR_P:
610 m68k_symbolic_call = "bsr%.l %p0";
613 case M68K_SYMBOLIC_CALL_NONE:
614 gcc_assert (m68k_symbolic_call == NULL);
621 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP
622 if (align_labels > 2)
624 warning (0, "-falign-labels=%d is not supported", align_labels);
629 warning (0, "-falign-loops=%d is not supported", align_loops);
634 SUBTARGET_OVERRIDE_OPTIONS;
636 /* Setup scheduling options. */
638 m68k_sched_cpu = CPU_CF_V2;
641 m68k_sched_cpu = CPU_UNKNOWN;
642 flag_schedule_insns = 0;
643 flag_schedule_insns_after_reload = 0;
644 flag_modulo_sched = 0;
648 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
649 given argument and NAME is the argument passed to -mcpu. Return NULL
650 if -mcpu was not passed. */
653 m68k_cpp_cpu_ident (const char *prefix)
657 return concat ("__m", prefix, "_cpu_", m68k_cpu_entry->name, NULL);
660 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
661 given argument and NAME is the name of the representative device for
662 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
665 m68k_cpp_cpu_family (const char *prefix)
669 return concat ("__m", prefix, "_family_", m68k_cpu_entry->family, NULL);
672 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
673 "interrupt_handler" attribute and interrupt_thread if FUNC has an
674 "interrupt_thread" attribute. Otherwise, return
675 m68k_fk_normal_function. */
677 enum m68k_function_kind
678 m68k_get_function_kind (tree func)
682 gcc_assert (TREE_CODE (func) == FUNCTION_DECL);
684 a = lookup_attribute ("interrupt", DECL_ATTRIBUTES (func));
686 return m68k_fk_interrupt_handler;
688 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
690 return m68k_fk_interrupt_handler;
692 a = lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func));
694 return m68k_fk_interrupt_thread;
696 return m68k_fk_normal_function;
699 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
700 struct attribute_spec.handler. */
702 m68k_handle_fndecl_attribute (tree *node, tree name,
703 tree args ATTRIBUTE_UNUSED,
704 int flags ATTRIBUTE_UNUSED,
707 if (TREE_CODE (*node) != FUNCTION_DECL)
709 warning (OPT_Wattributes, "%qs attribute only applies to functions",
710 IDENTIFIER_POINTER (name));
711 *no_add_attrs = true;
714 if (m68k_get_function_kind (*node) != m68k_fk_normal_function)
716 error ("multiple interrupt attributes not allowed");
717 *no_add_attrs = true;
721 && !strcmp (IDENTIFIER_POINTER (name), "interrupt_thread"))
723 error ("interrupt_thread is available only on fido");
724 *no_add_attrs = true;
731 m68k_compute_frame_layout (void)
735 enum m68k_function_kind func_kind =
736 m68k_get_function_kind (current_function_decl);
737 bool interrupt_handler = func_kind == m68k_fk_interrupt_handler;
738 bool interrupt_thread = func_kind == m68k_fk_interrupt_thread;
740 /* Only compute the frame once per function.
741 Don't cache information until reload has been completed. */
742 if (current_frame.funcdef_no == current_function_funcdef_no
746 current_frame.size = (get_frame_size () + 3) & -4;
750 /* Interrupt thread does not need to save any register. */
751 if (!interrupt_thread)
752 for (regno = 0; regno < 16; regno++)
753 if (m68k_save_reg (regno, interrupt_handler))
755 mask |= 1 << (regno - D0_REG);
758 current_frame.offset = saved * 4;
759 current_frame.reg_no = saved;
760 current_frame.reg_mask = mask;
762 current_frame.foffset = 0;
764 if (TARGET_HARD_FLOAT)
766 /* Interrupt thread does not need to save any register. */
767 if (!interrupt_thread)
768 for (regno = 16; regno < 24; regno++)
769 if (m68k_save_reg (regno, interrupt_handler))
771 mask |= 1 << (regno - FP0_REG);
774 current_frame.foffset = saved * TARGET_FP_REG_SIZE;
775 current_frame.offset += current_frame.foffset;
777 current_frame.fpu_no = saved;
778 current_frame.fpu_mask = mask;
780 /* Remember what function this frame refers to. */
781 current_frame.funcdef_no = current_function_funcdef_no;
785 m68k_initial_elimination_offset (int from, int to)
788 /* The arg pointer points 8 bytes before the start of the arguments,
789 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
790 frame pointer in most frames. */
791 argptr_offset = frame_pointer_needed ? 0 : UNITS_PER_WORD;
792 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
793 return argptr_offset;
795 m68k_compute_frame_layout ();
797 gcc_assert (to == STACK_POINTER_REGNUM);
800 case ARG_POINTER_REGNUM:
801 return current_frame.offset + current_frame.size - argptr_offset;
802 case FRAME_POINTER_REGNUM:
803 return current_frame.offset + current_frame.size;
809 /* Refer to the array `regs_ever_live' to determine which registers
810 to save; `regs_ever_live[I]' is nonzero if register number I
811 is ever used in the function. This function is responsible for
812 knowing which registers should not be saved even if used.
813 Return true if we need to save REGNO. */
816 m68k_save_reg (unsigned int regno, bool interrupt_handler)
818 if (flag_pic && regno == PIC_REG)
820 if (current_function_saves_all_registers)
822 if (current_function_uses_pic_offset_table)
824 /* Reload may introduce constant pool references into a function
825 that thitherto didn't need a PIC register. Note that the test
826 above will not catch that case because we will only set
827 current_function_uses_pic_offset_table when emitting
828 the address reloads. */
829 if (current_function_uses_const_pool)
833 if (current_function_calls_eh_return)
838 unsigned int test = EH_RETURN_DATA_REGNO (i);
839 if (test == INVALID_REGNUM)
846 /* Fixed regs we never touch. */
847 if (fixed_regs[regno])
850 /* The frame pointer (if it is such) is handled specially. */
851 if (regno == FRAME_POINTER_REGNUM && frame_pointer_needed)
854 /* Interrupt handlers must also save call_used_regs
855 if they are live or when calling nested functions. */
856 if (interrupt_handler)
858 if (df_regs_ever_live_p (regno))
861 if (!current_function_is_leaf && call_used_regs[regno])
865 /* Never need to save registers that aren't touched. */
866 if (!df_regs_ever_live_p (regno))
869 /* Otherwise save everything that isn't call-clobbered. */
870 return !call_used_regs[regno];
873 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
874 the lowest memory address. COUNT is the number of registers to be
875 moved, with register REGNO + I being moved if bit I of MASK is set.
876 STORE_P specifies the direction of the move and ADJUST_STACK_P says
877 whether or not this is pre-decrement (if STORE_P) or post-increment
878 (if !STORE_P) operation. */
881 m68k_emit_movem (rtx base, HOST_WIDE_INT offset,
882 unsigned int count, unsigned int regno,
883 unsigned int mask, bool store_p, bool adjust_stack_p)
886 rtx body, addr, src, operands[2];
887 enum machine_mode mode;
889 body = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (adjust_stack_p + count));
890 mode = reg_raw_mode[regno];
895 src = plus_constant (base, (count
896 * GET_MODE_SIZE (mode)
897 * (HOST_WIDE_INT) (store_p ? -1 : 1)));
898 XVECEXP (body, 0, i++) = gen_rtx_SET (VOIDmode, base, src);
901 for (; mask != 0; mask >>= 1, regno++)
904 addr = plus_constant (base, offset);
905 operands[!store_p] = gen_frame_mem (mode, addr);
906 operands[store_p] = gen_rtx_REG (mode, regno);
907 XVECEXP (body, 0, i++)
908 = gen_rtx_SET (VOIDmode, operands[0], operands[1]);
909 offset += GET_MODE_SIZE (mode);
911 gcc_assert (i == XVECLEN (body, 0));
913 return emit_insn (body);
916 /* Make INSN a frame-related instruction. */
919 m68k_set_frame_related (rtx insn)
924 RTX_FRAME_RELATED_P (insn) = 1;
925 body = PATTERN (insn);
926 if (GET_CODE (body) == PARALLEL)
927 for (i = 0; i < XVECLEN (body, 0); i++)
928 RTX_FRAME_RELATED_P (XVECEXP (body, 0, i)) = 1;
931 /* Emit RTL for the "prologue" define_expand. */
934 m68k_expand_prologue (void)
936 HOST_WIDE_INT fsize_with_regs;
937 rtx limit, src, dest, insn;
939 m68k_compute_frame_layout ();
941 /* If the stack limit is a symbol, we can check it here,
942 before actually allocating the space. */
943 if (current_function_limit_stack
944 && GET_CODE (stack_limit_rtx) == SYMBOL_REF)
946 limit = plus_constant (stack_limit_rtx, current_frame.size + 4);
947 if (!LEGITIMATE_CONSTANT_P (limit))
949 emit_move_insn (gen_rtx_REG (Pmode, D0_REG), limit);
950 limit = gen_rtx_REG (Pmode, D0_REG);
952 emit_insn (gen_cmpsi (stack_pointer_rtx, limit));
953 emit_insn (gen_conditional_trap (gen_rtx_LTU (VOIDmode,
954 cc0_rtx, const0_rtx),
958 fsize_with_regs = current_frame.size;
961 /* ColdFire's move multiple instructions do not allow pre-decrement
962 addressing. Add the size of movem saves to the initial stack
963 allocation instead. */
964 if (current_frame.reg_no >= MIN_MOVEM_REGS)
965 fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode);
966 if (current_frame.fpu_no >= MIN_FMOVEM_REGS)
967 fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode);
970 if (frame_pointer_needed)
972 if (fsize_with_regs == 0 && TUNE_68040)
974 /* On the 68040, two separate moves are faster than link.w 0. */
975 dest = gen_frame_mem (Pmode,
976 gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
977 m68k_set_frame_related (emit_move_insn (dest, frame_pointer_rtx));
978 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx,
981 else if (fsize_with_regs < 0x8000 || TARGET_68020)
982 m68k_set_frame_related
983 (emit_insn (gen_link (frame_pointer_rtx,
984 GEN_INT (-4 - fsize_with_regs))));
987 m68k_set_frame_related
988 (emit_insn (gen_link (frame_pointer_rtx, GEN_INT (-4))));
989 m68k_set_frame_related
990 (emit_insn (gen_addsi3 (stack_pointer_rtx,
992 GEN_INT (-fsize_with_regs))));
995 else if (fsize_with_regs != 0)
996 m68k_set_frame_related
997 (emit_insn (gen_addsi3 (stack_pointer_rtx,
999 GEN_INT (-fsize_with_regs))));
1001 if (current_frame.fpu_mask)
1003 gcc_assert (current_frame.fpu_no >= MIN_FMOVEM_REGS);
1005 m68k_set_frame_related
1006 (m68k_emit_movem (stack_pointer_rtx,
1007 current_frame.fpu_no * -GET_MODE_SIZE (XFmode),
1008 current_frame.fpu_no, FP0_REG,
1009 current_frame.fpu_mask, true, true));
1014 /* If we're using moveml to save the integer registers,
1015 the stack pointer will point to the bottom of the moveml
1016 save area. Find the stack offset of the first FP register. */
1017 if (current_frame.reg_no < MIN_MOVEM_REGS)
1020 offset = current_frame.reg_no * GET_MODE_SIZE (SImode);
1021 m68k_set_frame_related
1022 (m68k_emit_movem (stack_pointer_rtx, offset,
1023 current_frame.fpu_no, FP0_REG,
1024 current_frame.fpu_mask, true, false));
1028 /* If the stack limit is not a symbol, check it here.
1029 This has the disadvantage that it may be too late... */
1030 if (current_function_limit_stack)
1032 if (REG_P (stack_limit_rtx))
1034 emit_insn (gen_cmpsi (stack_pointer_rtx, stack_limit_rtx));
1035 emit_insn (gen_conditional_trap (gen_rtx_LTU (VOIDmode,
1036 cc0_rtx, const0_rtx),
1039 else if (GET_CODE (stack_limit_rtx) != SYMBOL_REF)
1040 warning (0, "stack limit expression is not supported");
1043 if (current_frame.reg_no < MIN_MOVEM_REGS)
1045 /* Store each register separately in the same order moveml does. */
1048 for (i = 16; i-- > 0; )
1049 if (current_frame.reg_mask & (1 << i))
1051 src = gen_rtx_REG (SImode, D0_REG + i);
1052 dest = gen_frame_mem (SImode,
1053 gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
1054 m68k_set_frame_related (emit_insn (gen_movsi (dest, src)));
1059 if (TARGET_COLDFIRE)
1060 /* The required register save space has already been allocated.
1061 The first register should be stored at (%sp). */
1062 m68k_set_frame_related
1063 (m68k_emit_movem (stack_pointer_rtx, 0,
1064 current_frame.reg_no, D0_REG,
1065 current_frame.reg_mask, true, false));
1067 m68k_set_frame_related
1068 (m68k_emit_movem (stack_pointer_rtx,
1069 current_frame.reg_no * -GET_MODE_SIZE (SImode),
1070 current_frame.reg_no, D0_REG,
1071 current_frame.reg_mask, true, true));
1076 && current_function_uses_pic_offset_table)
1077 insn = emit_insn (gen_load_got (pic_offset_table_rtx));
1080 /* Return true if a simple (return) instruction is sufficient for this
1081 instruction (i.e. if no epilogue is needed). */
1084 m68k_use_return_insn (void)
1086 if (!reload_completed || frame_pointer_needed || get_frame_size () != 0)
1089 m68k_compute_frame_layout ();
1090 return current_frame.offset == 0;
1093 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1094 SIBCALL_P says which.
1096 The function epilogue should not depend on the current stack pointer!
1097 It should use the frame pointer only, if there is a frame pointer.
1098 This is mandatory because of alloca; we also take advantage of it to
1099 omit stack adjustments before returning. */
1102 m68k_expand_epilogue (bool sibcall_p)
1104 HOST_WIDE_INT fsize, fsize_with_regs;
1105 bool big, restore_from_sp;
1107 m68k_compute_frame_layout ();
1109 fsize = current_frame.size;
1111 restore_from_sp = false;
1113 /* FIXME : current_function_is_leaf below is too strong.
1114 What we really need to know there is if there could be pending
1115 stack adjustment needed at that point. */
1116 restore_from_sp = (!frame_pointer_needed
1117 || (!current_function_calls_alloca
1118 && current_function_is_leaf));
1120 /* fsize_with_regs is the size we need to adjust the sp when
1121 popping the frame. */
1122 fsize_with_regs = fsize;
1123 if (TARGET_COLDFIRE && restore_from_sp)
1125 /* ColdFire's move multiple instructions do not allow post-increment
1126 addressing. Add the size of movem loads to the final deallocation
1128 if (current_frame.reg_no >= MIN_MOVEM_REGS)
1129 fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode);
1130 if (current_frame.fpu_no >= MIN_FMOVEM_REGS)
1131 fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode);
1134 if (current_frame.offset + fsize >= 0x8000
1136 && (current_frame.reg_mask || current_frame.fpu_mask))
1139 && (current_frame.reg_no >= MIN_MOVEM_REGS
1140 || current_frame.fpu_no >= MIN_FMOVEM_REGS))
1142 /* ColdFire's move multiple instructions do not support the
1143 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1144 stack-based restore. */
1145 emit_move_insn (gen_rtx_REG (Pmode, A1_REG),
1146 GEN_INT (-(current_frame.offset + fsize)));
1147 emit_insn (gen_addsi3 (stack_pointer_rtx,
1148 gen_rtx_REG (Pmode, A1_REG),
1149 frame_pointer_rtx));
1150 restore_from_sp = true;
1154 emit_move_insn (gen_rtx_REG (Pmode, A1_REG), GEN_INT (-fsize));
1160 if (current_frame.reg_no < MIN_MOVEM_REGS)
1162 /* Restore each register separately in the same order moveml does. */
1164 HOST_WIDE_INT offset;
1166 offset = current_frame.offset + fsize;
1167 for (i = 0; i < 16; i++)
1168 if (current_frame.reg_mask & (1 << i))
1174 /* Generate the address -OFFSET(%fp,%a1.l). */
1175 addr = gen_rtx_REG (Pmode, A1_REG);
1176 addr = gen_rtx_PLUS (Pmode, addr, frame_pointer_rtx);
1177 addr = plus_constant (addr, -offset);
1179 else if (restore_from_sp)
1180 addr = gen_rtx_POST_INC (Pmode, stack_pointer_rtx);
1182 addr = plus_constant (frame_pointer_rtx, -offset);
1183 emit_move_insn (gen_rtx_REG (SImode, D0_REG + i),
1184 gen_frame_mem (SImode, addr));
1185 offset -= GET_MODE_SIZE (SImode);
1188 else if (current_frame.reg_mask)
1191 m68k_emit_movem (gen_rtx_PLUS (Pmode,
1192 gen_rtx_REG (Pmode, A1_REG),
1194 -(current_frame.offset + fsize),
1195 current_frame.reg_no, D0_REG,
1196 current_frame.reg_mask, false, false);
1197 else if (restore_from_sp)
1198 m68k_emit_movem (stack_pointer_rtx, 0,
1199 current_frame.reg_no, D0_REG,
1200 current_frame.reg_mask, false,
1203 m68k_emit_movem (frame_pointer_rtx,
1204 -(current_frame.offset + fsize),
1205 current_frame.reg_no, D0_REG,
1206 current_frame.reg_mask, false, false);
1209 if (current_frame.fpu_no > 0)
1212 m68k_emit_movem (gen_rtx_PLUS (Pmode,
1213 gen_rtx_REG (Pmode, A1_REG),
1215 -(current_frame.foffset + fsize),
1216 current_frame.fpu_no, FP0_REG,
1217 current_frame.fpu_mask, false, false);
1218 else if (restore_from_sp)
1220 if (TARGET_COLDFIRE)
1224 /* If we used moveml to restore the integer registers, the
1225 stack pointer will still point to the bottom of the moveml
1226 save area. Find the stack offset of the first FP
1228 if (current_frame.reg_no < MIN_MOVEM_REGS)
1231 offset = current_frame.reg_no * GET_MODE_SIZE (SImode);
1232 m68k_emit_movem (stack_pointer_rtx, offset,
1233 current_frame.fpu_no, FP0_REG,
1234 current_frame.fpu_mask, false, false);
1237 m68k_emit_movem (stack_pointer_rtx, 0,
1238 current_frame.fpu_no, FP0_REG,
1239 current_frame.fpu_mask, false, true);
1242 m68k_emit_movem (frame_pointer_rtx,
1243 -(current_frame.foffset + fsize),
1244 current_frame.fpu_no, FP0_REG,
1245 current_frame.fpu_mask, false, false);
1248 if (frame_pointer_needed)
1249 emit_insn (gen_unlink (frame_pointer_rtx));
1250 else if (fsize_with_regs)
1251 emit_insn (gen_addsi3 (stack_pointer_rtx,
1253 GEN_INT (fsize_with_regs)));
1255 if (current_function_calls_eh_return)
1256 emit_insn (gen_addsi3 (stack_pointer_rtx,
1258 EH_RETURN_STACKADJ_RTX));
1261 emit_jump_insn (gen_rtx_RETURN (VOIDmode));
1264 /* Return true if X is a valid comparison operator for the dbcc
1267 Note it rejects floating point comparison operators.
1268 (In the future we could use Fdbcc).
1270 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1273 valid_dbcc_comparison_p_2 (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1275 switch (GET_CODE (x))
1277 case EQ: case NE: case GTU: case LTU:
1281 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1283 case GT: case LT: case GE: case LE:
1284 return ! (cc_prev_status.flags & CC_NO_OVERFLOW);
1290 /* Return nonzero if flags are currently in the 68881 flag register. */
1292 flags_in_68881 (void)
1294 /* We could add support for these in the future */
1295 return cc_status.flags & CC_IN_68881;
1298 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1301 m68k_ok_for_sibcall_p (tree decl, tree exp)
1303 enum m68k_function_kind kind;
1305 /* We cannot use sibcalls for nested functions because we use the
1306 static chain register for indirect calls. */
1307 if (CALL_EXPR_STATIC_CHAIN (exp))
1310 kind = m68k_get_function_kind (current_function_decl);
1311 if (kind == m68k_fk_normal_function)
1312 /* We can always sibcall from a normal function, because it's
1313 undefined if it is calling an interrupt function. */
1316 /* Otherwise we can only sibcall if the function kind is known to be
1318 if (decl && m68k_get_function_kind (decl) == kind)
1324 /* Convert X to a legitimate function call memory reference and return the
1328 m68k_legitimize_call_address (rtx x)
1330 gcc_assert (MEM_P (x));
1331 if (call_operand (XEXP (x, 0), VOIDmode))
1333 return replace_equiv_address (x, force_reg (Pmode, XEXP (x, 0)));
1336 /* Likewise for sibling calls. */
1339 m68k_legitimize_sibcall_address (rtx x)
1341 gcc_assert (MEM_P (x));
1342 if (sibcall_operand (XEXP (x, 0), VOIDmode))
1345 emit_move_insn (gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM), XEXP (x, 0));
1346 return replace_equiv_address (x, gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM));
1349 /* Output a dbCC; jCC sequence. Note we do not handle the
1350 floating point version of this sequence (Fdbcc). We also
1351 do not handle alternative conditions when CC_NO_OVERFLOW is
1352 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1353 kick those out before we get here. */
1356 output_dbcc_and_branch (rtx *operands)
1358 switch (GET_CODE (operands[3]))
1361 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands);
1365 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands);
1369 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands);
1373 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands);
1377 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands);
1381 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands);
1385 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands);
1389 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands);
1393 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands);
1397 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands);
1404 /* If the decrement is to be done in SImode, then we have
1405 to compensate for the fact that dbcc decrements in HImode. */
1406 switch (GET_MODE (operands[0]))
1409 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands);
1421 output_scc_di (rtx op, rtx operand1, rtx operand2, rtx dest)
1424 enum rtx_code op_code = GET_CODE (op);
1426 /* This does not produce a useful cc. */
1429 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1430 below. Swap the operands and change the op if these requirements
1431 are not fulfilled. */
1432 if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG)
1436 operand1 = operand2;
1438 op_code = swap_condition (op_code);
1440 loperands[0] = operand1;
1441 if (GET_CODE (operand1) == REG)
1442 loperands[1] = gen_rtx_REG (SImode, REGNO (operand1) + 1);
1444 loperands[1] = adjust_address (operand1, SImode, 4);
1445 if (operand2 != const0_rtx)
1447 loperands[2] = operand2;
1448 if (GET_CODE (operand2) == REG)
1449 loperands[3] = gen_rtx_REG (SImode, REGNO (operand2) + 1);
1451 loperands[3] = adjust_address (operand2, SImode, 4);
1453 loperands[4] = gen_label_rtx ();
1454 if (operand2 != const0_rtx)
1455 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands);
1458 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[0]))
1459 output_asm_insn ("tst%.l %0", loperands);
1461 output_asm_insn ("cmp%.w #0,%0", loperands);
1463 output_asm_insn ("jne %l4", loperands);
1465 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[1]))
1466 output_asm_insn ("tst%.l %1", loperands);
1468 output_asm_insn ("cmp%.w #0,%1", loperands);
1471 loperands[5] = dest;
1476 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1477 CODE_LABEL_NUMBER (loperands[4]));
1478 output_asm_insn ("seq %5", loperands);
1482 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1483 CODE_LABEL_NUMBER (loperands[4]));
1484 output_asm_insn ("sne %5", loperands);
1488 loperands[6] = gen_label_rtx ();
1489 output_asm_insn ("shi %5\n\tjra %l6", loperands);
1490 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1491 CODE_LABEL_NUMBER (loperands[4]));
1492 output_asm_insn ("sgt %5", loperands);
1493 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1494 CODE_LABEL_NUMBER (loperands[6]));
1498 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1499 CODE_LABEL_NUMBER (loperands[4]));
1500 output_asm_insn ("shi %5", loperands);
1504 loperands[6] = gen_label_rtx ();
1505 output_asm_insn ("scs %5\n\tjra %l6", loperands);
1506 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1507 CODE_LABEL_NUMBER (loperands[4]));
1508 output_asm_insn ("slt %5", loperands);
1509 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1510 CODE_LABEL_NUMBER (loperands[6]));
1514 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1515 CODE_LABEL_NUMBER (loperands[4]));
1516 output_asm_insn ("scs %5", loperands);
1520 loperands[6] = gen_label_rtx ();
1521 output_asm_insn ("scc %5\n\tjra %l6", loperands);
1522 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1523 CODE_LABEL_NUMBER (loperands[4]));
1524 output_asm_insn ("sge %5", loperands);
1525 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1526 CODE_LABEL_NUMBER (loperands[6]));
1530 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1531 CODE_LABEL_NUMBER (loperands[4]));
1532 output_asm_insn ("scc %5", loperands);
1536 loperands[6] = gen_label_rtx ();
1537 output_asm_insn ("sls %5\n\tjra %l6", loperands);
1538 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1539 CODE_LABEL_NUMBER (loperands[4]));
1540 output_asm_insn ("sle %5", loperands);
1541 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1542 CODE_LABEL_NUMBER (loperands[6]));
1546 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1547 CODE_LABEL_NUMBER (loperands[4]));
1548 output_asm_insn ("sls %5", loperands);
1558 output_btst (rtx *operands, rtx countop, rtx dataop, rtx insn, int signpos)
1560 operands[0] = countop;
1561 operands[1] = dataop;
1563 if (GET_CODE (countop) == CONST_INT)
1565 register int count = INTVAL (countop);
1566 /* If COUNT is bigger than size of storage unit in use,
1567 advance to the containing unit of same size. */
1568 if (count > signpos)
1570 int offset = (count & ~signpos) / 8;
1571 count = count & signpos;
1572 operands[1] = dataop = adjust_address (dataop, QImode, offset);
1574 if (count == signpos)
1575 cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N;
1577 cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N;
1579 /* These three statements used to use next_insns_test_no...
1580 but it appears that this should do the same job. */
1582 && next_insn_tests_no_inequality (insn))
1585 && next_insn_tests_no_inequality (insn))
1588 && next_insn_tests_no_inequality (insn))
1590 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1591 On some m68k variants unfortunately that's slower than btst.
1592 On 68000 and higher, that should also work for all HImode operands. */
1593 if (TUNE_CPU32 || TARGET_COLDFIRE || optimize_size)
1595 if (count == 3 && DATA_REG_P (operands[1])
1596 && next_insn_tests_no_inequality (insn))
1598 cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N | CC_NO_OVERFLOW;
1599 return "move%.w %1,%%ccr";
1601 if (count == 2 && DATA_REG_P (operands[1])
1602 && next_insn_tests_no_inequality (insn))
1604 cc_status.flags = CC_NOT_NEGATIVE | CC_INVERTED | CC_NO_OVERFLOW;
1605 return "move%.w %1,%%ccr";
1607 /* count == 1 followed by bvc/bvs and
1608 count == 0 followed by bcc/bcs are also possible, but need
1609 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1612 cc_status.flags = CC_NOT_NEGATIVE;
1614 return "btst %0,%1";
1617 /* Return true if X is a legitimate base register. STRICT_P says
1618 whether we need strict checking. */
1621 m68k_legitimate_base_reg_p (rtx x, bool strict_p)
1623 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1624 if (!strict_p && GET_CODE (x) == SUBREG)
1629 ? REGNO_OK_FOR_BASE_P (REGNO (x))
1630 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x))));
1633 /* Return true if X is a legitimate index register. STRICT_P says
1634 whether we need strict checking. */
1637 m68k_legitimate_index_reg_p (rtx x, bool strict_p)
1639 if (!strict_p && GET_CODE (x) == SUBREG)
1644 ? REGNO_OK_FOR_INDEX_P (REGNO (x))
1645 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x))));
1648 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1649 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1650 ADDRESS if so. STRICT_P says whether we need strict checking. */
1653 m68k_decompose_index (rtx x, bool strict_p, struct m68k_address *address)
1657 /* Check for a scale factor. */
1659 if ((TARGET_68020 || TARGET_COLDFIRE)
1660 && GET_CODE (x) == MULT
1661 && GET_CODE (XEXP (x, 1)) == CONST_INT
1662 && (INTVAL (XEXP (x, 1)) == 2
1663 || INTVAL (XEXP (x, 1)) == 4
1664 || (INTVAL (XEXP (x, 1)) == 8
1665 && (TARGET_COLDFIRE_FPU || !TARGET_COLDFIRE))))
1667 scale = INTVAL (XEXP (x, 1));
1671 /* Check for a word extension. */
1672 if (!TARGET_COLDFIRE
1673 && GET_CODE (x) == SIGN_EXTEND
1674 && GET_MODE (XEXP (x, 0)) == HImode)
1677 if (m68k_legitimate_index_reg_p (x, strict_p))
1679 address->scale = scale;
1687 /* Return true if X is an illegitimate symbolic constant. */
1690 m68k_illegitimate_symbolic_constant_p (rtx x)
1694 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P)
1696 split_const (x, &base, &offset);
1697 if (GET_CODE (base) == SYMBOL_REF
1698 && !offset_within_block_p (base, INTVAL (offset)))
1704 /* Return true if X is a legitimate constant address that can reach
1705 bytes in the range [X, X + REACH). STRICT_P says whether we need
1709 m68k_legitimate_constant_address_p (rtx x, unsigned int reach, bool strict_p)
1713 if (!CONSTANT_ADDRESS_P (x))
1717 && !(strict_p && TARGET_PCREL)
1718 && symbolic_operand (x, VOIDmode))
1721 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P && reach > 1)
1723 split_const (x, &base, &offset);
1724 if (GET_CODE (base) == SYMBOL_REF
1725 && !offset_within_block_p (base, INTVAL (offset) + reach - 1))
1732 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1733 labels will become jump tables. */
1736 m68k_jump_table_ref_p (rtx x)
1738 if (GET_CODE (x) != LABEL_REF)
1742 if (!NEXT_INSN (x) && !PREV_INSN (x))
1745 x = next_nonnote_insn (x);
1746 return x && JUMP_TABLE_DATA_P (x);
1749 /* Return true if X is a legitimate address for values of mode MODE.
1750 STRICT_P says whether strict checking is needed. If the address
1751 is valid, describe its components in *ADDRESS. */
1754 m68k_decompose_address (enum machine_mode mode, rtx x,
1755 bool strict_p, struct m68k_address *address)
1759 memset (address, 0, sizeof (*address));
1761 if (mode == BLKmode)
1764 reach = GET_MODE_SIZE (mode);
1766 /* Check for (An) (mode 2). */
1767 if (m68k_legitimate_base_reg_p (x, strict_p))
1773 /* Check for -(An) and (An)+ (modes 3 and 4). */
1774 if ((GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC)
1775 && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p))
1777 address->code = GET_CODE (x);
1778 address->base = XEXP (x, 0);
1782 /* Check for (d16,An) (mode 5). */
1783 if (GET_CODE (x) == PLUS
1784 && GET_CODE (XEXP (x, 1)) == CONST_INT
1785 && IN_RANGE (INTVAL (XEXP (x, 1)), -0x8000, 0x8000 - reach)
1786 && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p))
1788 address->base = XEXP (x, 0);
1789 address->offset = XEXP (x, 1);
1793 /* Check for GOT loads. These are (bd,An,Xn) addresses if
1794 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
1797 && GET_CODE (x) == PLUS
1798 && XEXP (x, 0) == pic_offset_table_rtx
1799 && (GET_CODE (XEXP (x, 1)) == SYMBOL_REF
1800 || GET_CODE (XEXP (x, 1)) == LABEL_REF))
1802 address->base = XEXP (x, 0);
1803 address->offset = XEXP (x, 1);
1807 /* The ColdFire FPU only accepts addressing modes 2-5. */
1808 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT)
1811 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
1812 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
1813 All these modes are variations of mode 7. */
1814 if (m68k_legitimate_constant_address_p (x, reach, strict_p))
1816 address->offset = x;
1820 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
1823 ??? do_tablejump creates these addresses before placing the target
1824 label, so we have to assume that unplaced labels are jump table
1825 references. It seems unlikely that we would ever generate indexed
1826 accesses to unplaced labels in other cases. */
1827 if (GET_CODE (x) == PLUS
1828 && m68k_jump_table_ref_p (XEXP (x, 1))
1829 && m68k_decompose_index (XEXP (x, 0), strict_p, address))
1831 address->offset = XEXP (x, 1);
1835 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
1836 (bd,An,Xn.SIZE*SCALE) addresses. */
1840 /* Check for a nonzero base displacement. */
1841 if (GET_CODE (x) == PLUS
1842 && m68k_legitimate_constant_address_p (XEXP (x, 1), reach, strict_p))
1844 address->offset = XEXP (x, 1);
1848 /* Check for a suppressed index register. */
1849 if (m68k_legitimate_base_reg_p (x, strict_p))
1855 /* Check for a suppressed base register. Do not allow this case
1856 for non-symbolic offsets as it effectively gives gcc freedom
1857 to treat data registers as base registers, which can generate
1860 && symbolic_operand (address->offset, VOIDmode)
1861 && m68k_decompose_index (x, strict_p, address))
1866 /* Check for a nonzero base displacement. */
1867 if (GET_CODE (x) == PLUS
1868 && GET_CODE (XEXP (x, 1)) == CONST_INT
1869 && IN_RANGE (INTVAL (XEXP (x, 1)), -0x80, 0x80 - reach))
1871 address->offset = XEXP (x, 1);
1876 /* We now expect the sum of a base and an index. */
1877 if (GET_CODE (x) == PLUS)
1879 if (m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p)
1880 && m68k_decompose_index (XEXP (x, 1), strict_p, address))
1882 address->base = XEXP (x, 0);
1886 if (m68k_legitimate_base_reg_p (XEXP (x, 1), strict_p)
1887 && m68k_decompose_index (XEXP (x, 0), strict_p, address))
1889 address->base = XEXP (x, 1);
1896 /* Return true if X is a legitimate address for values of mode MODE.
1897 STRICT_P says whether strict checking is needed. */
1900 m68k_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
1902 struct m68k_address address;
1904 return m68k_decompose_address (mode, x, strict_p, &address);
1907 /* Return true if X is a memory, describing its address in ADDRESS if so.
1908 Apply strict checking if called during or after reload. */
1911 m68k_legitimate_mem_p (rtx x, struct m68k_address *address)
1914 && m68k_decompose_address (GET_MODE (x), XEXP (x, 0),
1915 reload_in_progress || reload_completed,
1919 /* Return true if X matches the 'Q' constraint. It must be a memory
1920 with a base address and no constant offset or index. */
1923 m68k_matches_q_p (rtx x)
1925 struct m68k_address address;
1927 return (m68k_legitimate_mem_p (x, &address)
1928 && address.code == UNKNOWN
1934 /* Return true if X matches the 'U' constraint. It must be a base address
1935 with a constant offset and no index. */
1938 m68k_matches_u_p (rtx x)
1940 struct m68k_address address;
1942 return (m68k_legitimate_mem_p (x, &address)
1943 && address.code == UNKNOWN
1949 /* Legitimize PIC addresses. If the address is already
1950 position-independent, we return ORIG. Newly generated
1951 position-independent addresses go to REG. If we need more
1952 than one register, we lose.
1954 An address is legitimized by making an indirect reference
1955 through the Global Offset Table with the name of the symbol
1958 The assembler and linker are responsible for placing the
1959 address of the symbol in the GOT. The function prologue
1960 is responsible for initializing a5 to the starting address
1963 The assembler is also responsible for translating a symbol name
1964 into a constant displacement from the start of the GOT.
1966 A quick example may make things a little clearer:
1968 When not generating PIC code to store the value 12345 into _foo
1969 we would generate the following code:
1973 When generating PIC two transformations are made. First, the compiler
1974 loads the address of foo into a register. So the first transformation makes:
1979 The code in movsi will intercept the lea instruction and call this
1980 routine which will transform the instructions into:
1982 movel a5@(_foo:w), a0
1986 That (in a nutshell) is how *all* symbol and label references are
1990 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
1995 /* First handle a simple SYMBOL_REF or LABEL_REF */
1996 if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
2000 pic_ref = gen_rtx_MEM (Pmode,
2001 gen_rtx_PLUS (Pmode,
2002 pic_offset_table_rtx, orig));
2003 current_function_uses_pic_offset_table = 1;
2004 MEM_READONLY_P (pic_ref) = 1;
2005 emit_move_insn (reg, pic_ref);
2008 else if (GET_CODE (orig) == CONST)
2012 /* Make sure this has not already been legitimized. */
2013 if (GET_CODE (XEXP (orig, 0)) == PLUS
2014 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2019 /* legitimize both operands of the PLUS */
2020 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
2022 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2023 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2024 base == reg ? 0 : reg);
2026 if (GET_CODE (orig) == CONST_INT)
2027 return plus_constant (base, INTVAL (orig));
2028 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
2029 /* Likewise, should we set special REG_NOTEs here? */
2036 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2038 /* Return the type of move that should be used for integer I. */
2041 m68k_const_method (HOST_WIDE_INT i)
2048 /* The ColdFire doesn't have byte or word operations. */
2049 /* FIXME: This may not be useful for the m68060 either. */
2050 if (!TARGET_COLDFIRE)
2052 /* if -256 < N < 256 but N is not in range for a moveq
2053 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2054 if (USE_MOVQ (i ^ 0xff))
2056 /* Likewise, try with not.w */
2057 if (USE_MOVQ (i ^ 0xffff))
2059 /* This is the only value where neg.w is useful */
2064 /* Try also with swap. */
2066 if (USE_MOVQ ((u >> 16) | (u << 16)))
2071 /* Try using MVZ/MVS with an immediate value to load constants. */
2072 if (i >= 0 && i <= 65535)
2074 if (i >= -32768 && i <= 32767)
2078 /* Otherwise, use move.l */
2082 /* Return the cost of moving constant I into a data register. */
2085 const_int_cost (HOST_WIDE_INT i)
2087 switch (m68k_const_method (i))
2090 /* Constants between -128 and 127 are cheap due to moveq. */
2098 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2108 m68k_rtx_costs (rtx x, int code, int outer_code, int *total)
2113 /* Constant zero is super cheap due to clr instruction. */
2114 if (x == const0_rtx)
2117 *total = const_int_cost (INTVAL (x));
2127 /* Make 0.0 cheaper than other floating constants to
2128 encourage creating tstsf and tstdf insns. */
2129 if (outer_code == COMPARE
2130 && (x == CONST0_RTX (SFmode) || x == CONST0_RTX (DFmode)))
2136 /* These are vaguely right for a 68020. */
2137 /* The costs for long multiply have been adjusted to work properly
2138 in synth_mult on the 68020, relative to an average of the time
2139 for add and the time for shift, taking away a little more because
2140 sometimes move insns are needed. */
2141 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2147 : TARGET_COLDFIRE ? 3 : 13)
2152 : TUNE_68000_10 || TUNE_CFV2 ? 5 \
2153 : TARGET_COLDFIRE ? 2 : 8)
2156 (TARGET_CF_HWDIV ? 11 \
2157 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2160 /* An lea costs about three times as much as a simple add. */
2161 if (GET_MODE (x) == SImode
2162 && GET_CODE (XEXP (x, 1)) == REG
2163 && GET_CODE (XEXP (x, 0)) == MULT
2164 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
2165 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2166 && (INTVAL (XEXP (XEXP (x, 0), 1)) == 2
2167 || INTVAL (XEXP (XEXP (x, 0), 1)) == 4
2168 || INTVAL (XEXP (XEXP (x, 0), 1)) == 8))
2170 /* lea an@(dx:l:i),am */
2171 *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 2 : 3);
2181 *total = COSTS_N_INSNS(1);
2186 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2188 if (INTVAL (XEXP (x, 1)) < 16)
2189 *total = COSTS_N_INSNS (2) + INTVAL (XEXP (x, 1)) / 2;
2191 /* We're using clrw + swap for these cases. */
2192 *total = COSTS_N_INSNS (4) + (INTVAL (XEXP (x, 1)) - 16) / 2;
2195 *total = COSTS_N_INSNS (10); /* Worst case. */
2198 /* A shift by a big integer takes an extra instruction. */
2199 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2200 && (INTVAL (XEXP (x, 1)) == 16))
2202 *total = COSTS_N_INSNS (2); /* clrw;swap */
2205 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2206 && !(INTVAL (XEXP (x, 1)) > 0
2207 && INTVAL (XEXP (x, 1)) <= 8))
2209 *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 1 : 3); /* lsr #i,dn */
2215 if ((GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
2216 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
2217 && GET_MODE (x) == SImode)
2218 *total = COSTS_N_INSNS (MULW_COST);
2219 else if (GET_MODE (x) == QImode || GET_MODE (x) == HImode)
2220 *total = COSTS_N_INSNS (MULW_COST);
2222 *total = COSTS_N_INSNS (MULL_COST);
2229 if (GET_MODE (x) == QImode || GET_MODE (x) == HImode)
2230 *total = COSTS_N_INSNS (DIVW_COST); /* div.w */
2231 else if (TARGET_CF_HWDIV)
2232 *total = COSTS_N_INSNS (18);
2234 *total = COSTS_N_INSNS (43); /* div.l */
2242 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2246 output_move_const_into_data_reg (rtx *operands)
2250 i = INTVAL (operands[1]);
2251 switch (m68k_const_method (i))
2254 return "mvzw %1,%0";
2256 return "mvsw %1,%0";
2258 return "moveq %1,%0";
2261 operands[1] = GEN_INT (i ^ 0xff);
2262 return "moveq %1,%0\n\tnot%.b %0";
2265 operands[1] = GEN_INT (i ^ 0xffff);
2266 return "moveq %1,%0\n\tnot%.w %0";
2269 return "moveq #-128,%0\n\tneg%.w %0";
2274 operands[1] = GEN_INT ((u << 16) | (u >> 16));
2275 return "moveq %1,%0\n\tswap %0";
2278 return "move%.l %1,%0";
2284 /* Return true if I can be handled by ISA B's mov3q instruction. */
2287 valid_mov3q_const (HOST_WIDE_INT i)
2289 return TARGET_ISAB && (i == -1 || IN_RANGE (i, 1, 7));
2292 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
2293 I is the value of OPERANDS[1]. */
2296 output_move_simode_const (rtx *operands)
2302 src = INTVAL (operands[1]);
2304 && (DATA_REG_P (dest) || MEM_P (dest))
2305 /* clr insns on 68000 read before writing. */
2306 && ((TARGET_68010 || TARGET_COLDFIRE)
2307 || !(MEM_P (dest) && MEM_VOLATILE_P (dest))))
2309 else if (GET_MODE (dest) == SImode && valid_mov3q_const (src))
2310 return "mov3q%.l %1,%0";
2311 else if (src == 0 && ADDRESS_REG_P (dest))
2312 return "sub%.l %0,%0";
2313 else if (DATA_REG_P (dest))
2314 return output_move_const_into_data_reg (operands);
2315 else if (ADDRESS_REG_P (dest) && IN_RANGE (src, -0x8000, 0x7fff))
2317 if (valid_mov3q_const (src))
2318 return "mov3q%.l %1,%0";
2319 return "move%.w %1,%0";
2321 else if (MEM_P (dest)
2322 && GET_CODE (XEXP (dest, 0)) == PRE_DEC
2323 && REGNO (XEXP (XEXP (dest, 0), 0)) == STACK_POINTER_REGNUM
2324 && IN_RANGE (src, -0x8000, 0x7fff))
2326 if (valid_mov3q_const (src))
2327 return "mov3q%.l %1,%-";
2330 return "move%.l %1,%0";
2334 output_move_simode (rtx *operands)
2336 if (GET_CODE (operands[1]) == CONST_INT)
2337 return output_move_simode_const (operands);
2338 else if ((GET_CODE (operands[1]) == SYMBOL_REF
2339 || GET_CODE (operands[1]) == CONST)
2340 && push_operand (operands[0], SImode))
2342 else if ((GET_CODE (operands[1]) == SYMBOL_REF
2343 || GET_CODE (operands[1]) == CONST)
2344 && ADDRESS_REG_P (operands[0]))
2345 return "lea %a1,%0";
2346 return "move%.l %1,%0";
2350 output_move_himode (rtx *operands)
2352 if (GET_CODE (operands[1]) == CONST_INT)
2354 if (operands[1] == const0_rtx
2355 && (DATA_REG_P (operands[0])
2356 || GET_CODE (operands[0]) == MEM)
2357 /* clr insns on 68000 read before writing. */
2358 && ((TARGET_68010 || TARGET_COLDFIRE)
2359 || !(GET_CODE (operands[0]) == MEM
2360 && MEM_VOLATILE_P (operands[0]))))
2362 else if (operands[1] == const0_rtx
2363 && ADDRESS_REG_P (operands[0]))
2364 return "sub%.l %0,%0";
2365 else if (DATA_REG_P (operands[0])
2366 && INTVAL (operands[1]) < 128
2367 && INTVAL (operands[1]) >= -128)
2368 return "moveq %1,%0";
2369 else if (INTVAL (operands[1]) < 0x8000
2370 && INTVAL (operands[1]) >= -0x8000)
2371 return "move%.w %1,%0";
2373 else if (CONSTANT_P (operands[1]))
2374 return "move%.l %1,%0";
2375 return "move%.w %1,%0";
2379 output_move_qimode (rtx *operands)
2381 /* 68k family always modifies the stack pointer by at least 2, even for
2382 byte pushes. The 5200 (ColdFire) does not do this. */
2384 /* This case is generated by pushqi1 pattern now. */
2385 gcc_assert (!(GET_CODE (operands[0]) == MEM
2386 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
2387 && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx
2388 && ! ADDRESS_REG_P (operands[1])
2389 && ! TARGET_COLDFIRE));
2391 /* clr and st insns on 68000 read before writing. */
2392 if (!ADDRESS_REG_P (operands[0])
2393 && ((TARGET_68010 || TARGET_COLDFIRE)
2394 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
2396 if (operands[1] == const0_rtx)
2398 if ((!TARGET_COLDFIRE || DATA_REG_P (operands[0]))
2399 && GET_CODE (operands[1]) == CONST_INT
2400 && (INTVAL (operands[1]) & 255) == 255)
2406 if (GET_CODE (operands[1]) == CONST_INT
2407 && DATA_REG_P (operands[0])
2408 && INTVAL (operands[1]) < 128
2409 && INTVAL (operands[1]) >= -128)
2410 return "moveq %1,%0";
2411 if (operands[1] == const0_rtx && ADDRESS_REG_P (operands[0]))
2412 return "sub%.l %0,%0";
2413 if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
2414 return "move%.l %1,%0";
2415 /* 68k family (including the 5200 ColdFire) does not support byte moves to
2416 from address registers. */
2417 if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
2418 return "move%.w %1,%0";
2419 return "move%.b %1,%0";
2423 output_move_stricthi (rtx *operands)
2425 if (operands[1] == const0_rtx
2426 /* clr insns on 68000 read before writing. */
2427 && ((TARGET_68010 || TARGET_COLDFIRE)
2428 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
2430 return "move%.w %1,%0";
2434 output_move_strictqi (rtx *operands)
2436 if (operands[1] == const0_rtx
2437 /* clr insns on 68000 read before writing. */
2438 && ((TARGET_68010 || TARGET_COLDFIRE)
2439 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
2441 return "move%.b %1,%0";
2444 /* Return the best assembler insn template
2445 for moving operands[1] into operands[0] as a fullword. */
2448 singlemove_string (rtx *operands)
2450 if (GET_CODE (operands[1]) == CONST_INT)
2451 return output_move_simode_const (operands);
2452 return "move%.l %1,%0";
2456 /* Output assembler or rtl code to perform a doubleword move insn
2457 with operands OPERANDS.
2458 Pointers to 3 helper functions should be specified:
2459 HANDLE_REG_ADJUST to adjust a register by a small value,
2460 HANDLE_COMPADR to compute an address and
2461 HANDLE_MOVSI to move 4 bytes. */
2464 handle_move_double (rtx operands[2],
2465 void (*handle_reg_adjust) (rtx, int),
2466 void (*handle_compadr) (rtx [2]),
2467 void (*handle_movsi) (rtx [2]))
2471 REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP
2476 rtx addreg0 = 0, addreg1 = 0;
2477 int dest_overlapped_low = 0;
2478 int size = GET_MODE_SIZE (GET_MODE (operands[0]));
2483 /* First classify both operands. */
2485 if (REG_P (operands[0]))
2487 else if (offsettable_memref_p (operands[0]))
2489 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2491 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2493 else if (GET_CODE (operands[0]) == MEM)
2498 if (REG_P (operands[1]))
2500 else if (CONSTANT_P (operands[1]))
2502 else if (offsettable_memref_p (operands[1]))
2504 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
2506 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2508 else if (GET_CODE (operands[1]) == MEM)
2513 /* Check for the cases that the operand constraints are not supposed
2514 to allow to happen. Generating code for these cases is
2516 gcc_assert (optype0 != RNDOP && optype1 != RNDOP);
2518 /* If one operand is decrementing and one is incrementing
2519 decrement the former register explicitly
2520 and change that operand into ordinary indexing. */
2522 if (optype0 == PUSHOP && optype1 == POPOP)
2524 operands[0] = XEXP (XEXP (operands[0], 0), 0);
2526 handle_reg_adjust (operands[0], -size);
2528 if (GET_MODE (operands[1]) == XFmode)
2529 operands[0] = gen_rtx_MEM (XFmode, operands[0]);
2530 else if (GET_MODE (operands[0]) == DFmode)
2531 operands[0] = gen_rtx_MEM (DFmode, operands[0]);
2533 operands[0] = gen_rtx_MEM (DImode, operands[0]);
2536 if (optype0 == POPOP && optype1 == PUSHOP)
2538 operands[1] = XEXP (XEXP (operands[1], 0), 0);
2540 handle_reg_adjust (operands[1], -size);
2542 if (GET_MODE (operands[1]) == XFmode)
2543 operands[1] = gen_rtx_MEM (XFmode, operands[1]);
2544 else if (GET_MODE (operands[1]) == DFmode)
2545 operands[1] = gen_rtx_MEM (DFmode, operands[1]);
2547 operands[1] = gen_rtx_MEM (DImode, operands[1]);
2551 /* If an operand is an unoffsettable memory ref, find a register
2552 we can increment temporarily to make it refer to the second word. */
2554 if (optype0 == MEMOP)
2555 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2557 if (optype1 == MEMOP)
2558 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2560 /* Ok, we can do one word at a time.
2561 Normally we do the low-numbered word first,
2562 but if either operand is autodecrementing then we
2563 do the high-numbered word first.
2565 In either case, set up in LATEHALF the operands to use
2566 for the high-numbered word and in some cases alter the
2567 operands in OPERANDS to be suitable for the low-numbered word. */
2571 if (optype0 == REGOP)
2573 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2);
2574 middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2576 else if (optype0 == OFFSOP)
2578 middlehalf[0] = adjust_address (operands[0], SImode, 4);
2579 latehalf[0] = adjust_address (operands[0], SImode, size - 4);
2583 middlehalf[0] = adjust_address (operands[0], SImode, 0);
2584 latehalf[0] = adjust_address (operands[0], SImode, 0);
2587 if (optype1 == REGOP)
2589 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
2590 middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2592 else if (optype1 == OFFSOP)
2594 middlehalf[1] = adjust_address (operands[1], SImode, 4);
2595 latehalf[1] = adjust_address (operands[1], SImode, size - 4);
2597 else if (optype1 == CNSTOP)
2599 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2604 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
2605 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
2606 operands[1] = GEN_INT (l[0]);
2607 middlehalf[1] = GEN_INT (l[1]);
2608 latehalf[1] = GEN_INT (l[2]);
2612 /* No non-CONST_DOUBLE constant should ever appear
2614 gcc_assert (!CONSTANT_P (operands[1]));
2619 middlehalf[1] = adjust_address (operands[1], SImode, 0);
2620 latehalf[1] = adjust_address (operands[1], SImode, 0);
2624 /* size is not 12: */
2626 if (optype0 == REGOP)
2627 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2628 else if (optype0 == OFFSOP)
2629 latehalf[0] = adjust_address (operands[0], SImode, size - 4);
2631 latehalf[0] = adjust_address (operands[0], SImode, 0);
2633 if (optype1 == REGOP)
2634 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2635 else if (optype1 == OFFSOP)
2636 latehalf[1] = adjust_address (operands[1], SImode, size - 4);
2637 else if (optype1 == CNSTOP)
2638 split_double (operands[1], &operands[1], &latehalf[1]);
2640 latehalf[1] = adjust_address (operands[1], SImode, 0);
2643 /* If insn is effectively movd N(sp),-(sp) then we will do the
2644 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2645 for the low word as well, to compensate for the first decrement of sp. */
2646 if (optype0 == PUSHOP
2647 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
2648 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
2649 operands[1] = middlehalf[1] = latehalf[1];
2651 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2652 if the upper part of reg N does not appear in the MEM, arrange to
2653 emit the move late-half first. Otherwise, compute the MEM address
2654 into the upper part of N and use that as a pointer to the memory
2656 if (optype0 == REGOP
2657 && (optype1 == OFFSOP || optype1 == MEMOP))
2659 rtx testlow = gen_rtx_REG (SImode, REGNO (operands[0]));
2661 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
2662 && reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
2664 /* If both halves of dest are used in the src memory address,
2665 compute the address into latehalf of dest.
2666 Note that this can't happen if the dest is two data regs. */
2668 xops[0] = latehalf[0];
2669 xops[1] = XEXP (operands[1], 0);
2671 handle_compadr (xops);
2672 if (GET_MODE (operands[1]) == XFmode)
2674 operands[1] = gen_rtx_MEM (XFmode, latehalf[0]);
2675 middlehalf[1] = adjust_address (operands[1], DImode, size - 8);
2676 latehalf[1] = adjust_address (operands[1], DImode, size - 4);
2680 operands[1] = gen_rtx_MEM (DImode, latehalf[0]);
2681 latehalf[1] = adjust_address (operands[1], DImode, size - 4);
2685 && reg_overlap_mentioned_p (middlehalf[0],
2686 XEXP (operands[1], 0)))
2688 /* Check for two regs used by both source and dest.
2689 Note that this can't happen if the dest is all data regs.
2690 It can happen if the dest is d6, d7, a0.
2691 But in that case, latehalf is an addr reg, so
2692 the code at compadr does ok. */
2694 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
2695 || reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
2698 /* JRV says this can't happen: */
2699 gcc_assert (!addreg0 && !addreg1);
2701 /* Only the middle reg conflicts; simply put it last. */
2702 handle_movsi (operands);
2703 handle_movsi (latehalf);
2704 handle_movsi (middlehalf);
2708 else if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)))
2709 /* If the low half of dest is mentioned in the source memory
2710 address, the arrange to emit the move late half first. */
2711 dest_overlapped_low = 1;
2714 /* If one or both operands autodecrementing,
2715 do the two words, high-numbered first. */
2717 /* Likewise, the first move would clobber the source of the second one,
2718 do them in the other order. This happens only for registers;
2719 such overlap can't happen in memory unless the user explicitly
2720 sets it up, and that is an undefined circumstance. */
2722 if (optype0 == PUSHOP || optype1 == PUSHOP
2723 || (optype0 == REGOP && optype1 == REGOP
2724 && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1]))
2725 || REGNO (operands[0]) == REGNO (latehalf[1])))
2726 || dest_overlapped_low)
2728 /* Make any unoffsettable addresses point at high-numbered word. */
2730 handle_reg_adjust (addreg0, size - 4);
2732 handle_reg_adjust (addreg1, size - 4);
2735 handle_movsi (latehalf);
2737 /* Undo the adds we just did. */
2739 handle_reg_adjust (addreg0, -4);
2741 handle_reg_adjust (addreg1, -4);
2745 handle_movsi (middlehalf);
2748 handle_reg_adjust (addreg0, -4);
2750 handle_reg_adjust (addreg1, -4);
2753 /* Do low-numbered word. */
2755 handle_movsi (operands);
2759 /* Normal case: do the two words, low-numbered first. */
2761 handle_movsi (operands);
2763 /* Do the middle one of the three words for long double */
2767 handle_reg_adjust (addreg0, 4);
2769 handle_reg_adjust (addreg1, 4);
2771 handle_movsi (middlehalf);
2774 /* Make any unoffsettable addresses point at high-numbered word. */
2776 handle_reg_adjust (addreg0, 4);
2778 handle_reg_adjust (addreg1, 4);
2781 handle_movsi (latehalf);
2783 /* Undo the adds we just did. */
2785 handle_reg_adjust (addreg0, -(size - 4));
2787 handle_reg_adjust (addreg1, -(size - 4));
2792 /* Output assembler code to adjust REG by N. */
2794 output_reg_adjust (rtx reg, int n)
2798 gcc_assert (GET_MODE (reg) == SImode
2799 && -12 <= n && n != 0 && n <= 12);
2804 s = "add%.l #12,%0";
2808 s = "addq%.l #8,%0";
2812 s = "addq%.l #4,%0";
2816 s = "sub%.l #12,%0";
2820 s = "subq%.l #8,%0";
2824 s = "subq%.l #4,%0";
2832 output_asm_insn (s, ®);
2835 /* Emit rtl code to adjust REG by N. */
2837 emit_reg_adjust (rtx reg1, int n)
2841 gcc_assert (GET_MODE (reg1) == SImode
2842 && -12 <= n && n != 0 && n <= 12);
2844 reg1 = copy_rtx (reg1);
2845 reg2 = copy_rtx (reg1);
2848 emit_insn (gen_subsi3 (reg1, reg2, GEN_INT (-n)));
2850 emit_insn (gen_addsi3 (reg1, reg2, GEN_INT (n)));
2855 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
2857 output_compadr (rtx operands[2])
2859 output_asm_insn ("lea %a1,%0", operands);
2862 /* Output the best assembler insn for moving operands[1] into operands[0]
2865 output_movsi (rtx operands[2])
2867 output_asm_insn (singlemove_string (operands), operands);
2870 /* Copy OP and change its mode to MODE. */
2872 copy_operand (rtx op, enum machine_mode mode)
2874 /* ??? This looks really ugly. There must be a better way
2875 to change a mode on the operand. */
2876 if (GET_MODE (op) != VOIDmode)
2879 op = gen_rtx_REG (mode, REGNO (op));
2883 PUT_MODE (op, mode);
2890 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
2892 emit_movsi (rtx operands[2])
2894 operands[0] = copy_operand (operands[0], SImode);
2895 operands[1] = copy_operand (operands[1], SImode);
2897 emit_insn (gen_movsi (operands[0], operands[1]));
2900 /* Output assembler code to perform a doubleword move insn
2901 with operands OPERANDS. */
2903 output_move_double (rtx *operands)
2905 handle_move_double (operands,
2906 output_reg_adjust, output_compadr, output_movsi);
2911 /* Output rtl code to perform a doubleword move insn
2912 with operands OPERANDS. */
2914 m68k_emit_move_double (rtx operands[2])
2916 handle_move_double (operands, emit_reg_adjust, emit_movsi, emit_movsi);
2919 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
2920 new rtx with the correct mode. */
2923 force_mode (enum machine_mode mode, rtx orig)
2925 if (mode == GET_MODE (orig))
2928 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
2931 return gen_rtx_REG (mode, REGNO (orig));
2935 fp_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2937 return reg_renumber && FP_REG_P (op);
2940 /* Emit insns to move operands[1] into operands[0].
2942 Return 1 if we have written out everything that needs to be done to
2943 do the move. Otherwise, return 0 and the caller will emit the move
2946 Note SCRATCH_REG may not be in the proper mode depending on how it
2947 will be used. This routine is responsible for creating a new copy
2948 of SCRATCH_REG in the proper mode. */
2951 emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
2953 register rtx operand0 = operands[0];
2954 register rtx operand1 = operands[1];
2958 && reload_in_progress && GET_CODE (operand0) == REG
2959 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
2960 operand0 = reg_equiv_mem[REGNO (operand0)];
2961 else if (scratch_reg
2962 && reload_in_progress && GET_CODE (operand0) == SUBREG
2963 && GET_CODE (SUBREG_REG (operand0)) == REG
2964 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
2966 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2967 the code which tracks sets/uses for delete_output_reload. */
2968 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
2969 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
2970 SUBREG_BYTE (operand0));
2971 operand0 = alter_subreg (&temp);
2975 && reload_in_progress && GET_CODE (operand1) == REG
2976 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
2977 operand1 = reg_equiv_mem[REGNO (operand1)];
2978 else if (scratch_reg
2979 && reload_in_progress && GET_CODE (operand1) == SUBREG
2980 && GET_CODE (SUBREG_REG (operand1)) == REG
2981 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
2983 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2984 the code which tracks sets/uses for delete_output_reload. */
2985 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
2986 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
2987 SUBREG_BYTE (operand1));
2988 operand1 = alter_subreg (&temp);
2991 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
2992 && ((tem = find_replacement (&XEXP (operand0, 0)))
2993 != XEXP (operand0, 0)))
2994 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
2995 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
2996 && ((tem = find_replacement (&XEXP (operand1, 0)))
2997 != XEXP (operand1, 0)))
2998 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
3000 /* Handle secondary reloads for loads/stores of FP registers where
3001 the address is symbolic by using the scratch register */
3002 if (fp_reg_operand (operand0, mode)
3003 && ((GET_CODE (operand1) == MEM
3004 && ! memory_address_p (DFmode, XEXP (operand1, 0)))
3005 || ((GET_CODE (operand1) == SUBREG
3006 && GET_CODE (XEXP (operand1, 0)) == MEM
3007 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
3010 if (GET_CODE (operand1) == SUBREG)
3011 operand1 = XEXP (operand1, 0);
3013 /* SCRATCH_REG will hold an address. We want
3014 it in SImode regardless of what mode it was originally given
3016 scratch_reg = force_mode (SImode, scratch_reg);
3018 /* D might not fit in 14 bits either; for such cases load D into
3020 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
3022 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
3023 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
3025 XEXP (XEXP (operand1, 0), 0),
3029 emit_move_insn (scratch_reg, XEXP (operand1, 0));
3030 emit_insn (gen_rtx_SET (VOIDmode, operand0,
3031 gen_rtx_MEM (mode, scratch_reg)));
3034 else if (fp_reg_operand (operand1, mode)
3035 && ((GET_CODE (operand0) == MEM
3036 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
3037 || ((GET_CODE (operand0) == SUBREG)
3038 && GET_CODE (XEXP (operand0, 0)) == MEM
3039 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
3042 if (GET_CODE (operand0) == SUBREG)
3043 operand0 = XEXP (operand0, 0);
3045 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3046 it in SIMODE regardless of what mode it was originally given
3048 scratch_reg = force_mode (SImode, scratch_reg);
3050 /* D might not fit in 14 bits either; for such cases load D into
3052 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
3054 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
3055 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
3058 XEXP (XEXP (operand0, 0),
3063 emit_move_insn (scratch_reg, XEXP (operand0, 0));
3064 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
3068 /* Handle secondary reloads for loads of FP registers from constant
3069 expressions by forcing the constant into memory.
3071 use scratch_reg to hold the address of the memory location.
3073 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3074 NO_REGS when presented with a const_int and an register class
3075 containing only FP registers. Doing so unfortunately creates
3076 more problems than it solves. Fix this for 2.5. */
3077 else if (fp_reg_operand (operand0, mode)
3078 && CONSTANT_P (operand1)
3083 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3084 it in SIMODE regardless of what mode it was originally given
3086 scratch_reg = force_mode (SImode, scratch_reg);
3088 /* Force the constant into memory and put the address of the
3089 memory location into scratch_reg. */
3090 xoperands[0] = scratch_reg;
3091 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
3092 emit_insn (gen_rtx_SET (mode, scratch_reg, xoperands[1]));
3094 /* Now load the destination register. */
3095 emit_insn (gen_rtx_SET (mode, operand0,
3096 gen_rtx_MEM (mode, scratch_reg)));
3100 /* Now have insn-emit do whatever it normally does. */
3104 /* Split one or more DImode RTL references into pairs of SImode
3105 references. The RTL can be REG, offsettable MEM, integer constant, or
3106 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3107 split and "num" is its length. lo_half and hi_half are output arrays
3108 that parallel "operands". */
3111 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
3115 rtx op = operands[num];
3117 /* simplify_subreg refuses to split volatile memory addresses,
3118 but we still have to handle it. */
3119 if (GET_CODE (op) == MEM)
3121 lo_half[num] = adjust_address (op, SImode, 4);
3122 hi_half[num] = adjust_address (op, SImode, 0);
3126 lo_half[num] = simplify_gen_subreg (SImode, op,
3127 GET_MODE (op) == VOIDmode
3128 ? DImode : GET_MODE (op), 4);
3129 hi_half[num] = simplify_gen_subreg (SImode, op,
3130 GET_MODE (op) == VOIDmode
3131 ? DImode : GET_MODE (op), 0);
3136 /* Split X into a base and a constant offset, storing them in *BASE
3137 and *OFFSET respectively. */
3140 m68k_split_offset (rtx x, rtx *base, HOST_WIDE_INT *offset)
3143 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
3145 *offset += INTVAL (XEXP (x, 1));
3151 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3152 instruction. STORE_P says whether the move is a load or store.
3154 If the instruction uses post-increment or pre-decrement addressing,
3155 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3156 adjustment. This adjustment will be made by the first element of
3157 PARALLEL, with the loads or stores starting at element 1. If the
3158 instruction does not use post-increment or pre-decrement addressing,
3159 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3160 start at element 0. */
3163 m68k_movem_pattern_p (rtx pattern, rtx automod_base,
3164 HOST_WIDE_INT automod_offset, bool store_p)
3166 rtx base, mem_base, set, mem, reg, last_reg;
3167 HOST_WIDE_INT offset, mem_offset;
3169 enum reg_class rclass;
3171 len = XVECLEN (pattern, 0);
3172 first = (automod_base != NULL);
3176 /* Stores must be pre-decrement and loads must be post-increment. */
3177 if (store_p != (automod_offset < 0))
3180 /* Work out the base and offset for lowest memory location. */
3181 base = automod_base;
3182 offset = (automod_offset < 0 ? automod_offset : 0);
3186 /* Allow any valid base and offset in the first access. */
3193 for (i = first; i < len; i++)
3195 /* We need a plain SET. */
3196 set = XVECEXP (pattern, 0, i);
3197 if (GET_CODE (set) != SET)
3200 /* Check that we have a memory location... */
3201 mem = XEXP (set, !store_p);
3202 if (!MEM_P (mem) || !memory_operand (mem, VOIDmode))
3205 /* ...with the right address. */
3208 m68k_split_offset (XEXP (mem, 0), &base, &offset);
3209 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3210 There are no mode restrictions for 680x0 besides the
3211 automodification rules enforced above. */
3213 && !m68k_legitimate_base_reg_p (base, reload_completed))
3218 m68k_split_offset (XEXP (mem, 0), &mem_base, &mem_offset);
3219 if (!rtx_equal_p (base, mem_base) || offset != mem_offset)
3223 /* Check that we have a register of the required mode and class. */
3224 reg = XEXP (set, store_p);
3226 || !HARD_REGISTER_P (reg)
3227 || GET_MODE (reg) != reg_raw_mode[REGNO (reg)])
3232 /* The register must belong to RCLASS and have a higher number
3233 than the register in the previous SET. */
3234 if (!TEST_HARD_REG_BIT (reg_class_contents[rclass], REGNO (reg))
3235 || REGNO (last_reg) >= REGNO (reg))
3240 /* Work out which register class we need. */
3241 if (INT_REGNO_P (REGNO (reg)))
3242 rclass = GENERAL_REGS;
3243 else if (FP_REGNO_P (REGNO (reg)))
3250 offset += GET_MODE_SIZE (GET_MODE (reg));
3253 /* If we have an automodification, check whether the final offset is OK. */
3254 if (automod_base && offset != (automod_offset < 0 ? 0 : automod_offset))
3257 /* Reject unprofitable cases. */
3258 if (len < first + (rclass == FP_REGS ? MIN_FMOVEM_REGS : MIN_MOVEM_REGS))
3264 /* Return the assembly code template for a movem or fmovem instruction
3265 whose pattern is given by PATTERN. Store the template's operands
3268 If the instruction uses post-increment or pre-decrement addressing,
3269 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3270 is true if this is a store instruction. */
3273 m68k_output_movem (rtx *operands, rtx pattern,
3274 HOST_WIDE_INT automod_offset, bool store_p)
3279 gcc_assert (GET_CODE (pattern) == PARALLEL);
3281 first = (automod_offset != 0);
3282 for (i = first; i < XVECLEN (pattern, 0); i++)
3284 /* When using movem with pre-decrement addressing, register X + D0_REG
3285 is controlled by bit 15 - X. For all other addressing modes,
3286 register X + D0_REG is controlled by bit X. Confusingly, the
3287 register mask for fmovem is in the opposite order to that for
3291 gcc_assert (MEM_P (XEXP (XVECEXP (pattern, 0, i), !store_p)));
3292 gcc_assert (REG_P (XEXP (XVECEXP (pattern, 0, i), store_p)));
3293 regno = REGNO (XEXP (XVECEXP (pattern, 0, i), store_p));
3294 if (automod_offset < 0)
3296 if (FP_REGNO_P (regno))
3297 mask |= 1 << (regno - FP0_REG);
3299 mask |= 1 << (15 - (regno - D0_REG));
3303 if (FP_REGNO_P (regno))
3304 mask |= 1 << (7 - (regno - FP0_REG));
3306 mask |= 1 << (regno - D0_REG);
3311 if (automod_offset == 0)
3312 operands[0] = XEXP (XEXP (XVECEXP (pattern, 0, first), !store_p), 0);
3313 else if (automod_offset < 0)
3314 operands[0] = gen_rtx_PRE_DEC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0)));
3316 operands[0] = gen_rtx_POST_INC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0)));
3317 operands[1] = GEN_INT (mask);
3318 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern, 0, first), store_p))))
3321 return "fmovem %1,%a0";
3323 return "fmovem %a0,%1";
3328 return "movem%.l %1,%a0";
3330 return "movem%.l %a0,%1";
3334 /* Return a REG that occurs in ADDR with coefficient 1.
3335 ADDR can be effectively incremented by incrementing REG. */
3338 find_addr_reg (rtx addr)
3340 while (GET_CODE (addr) == PLUS)
3342 if (GET_CODE (XEXP (addr, 0)) == REG)
3343 addr = XEXP (addr, 0);
3344 else if (GET_CODE (XEXP (addr, 1)) == REG)
3345 addr = XEXP (addr, 1);
3346 else if (CONSTANT_P (XEXP (addr, 0)))
3347 addr = XEXP (addr, 1);
3348 else if (CONSTANT_P (XEXP (addr, 1)))
3349 addr = XEXP (addr, 0);
3353 gcc_assert (GET_CODE (addr) == REG);
3357 /* Output assembler code to perform a 32-bit 3-operand add. */
3360 output_addsi3 (rtx *operands)
3362 if (! operands_match_p (operands[0], operands[1]))
3364 if (!ADDRESS_REG_P (operands[1]))
3366 rtx tmp = operands[1];
3368 operands[1] = operands[2];
3372 /* These insns can result from reloads to access
3373 stack slots over 64k from the frame pointer. */
3374 if (GET_CODE (operands[2]) == CONST_INT
3375 && (INTVAL (operands[2]) < -32768 || INTVAL (operands[2]) > 32767))
3376 return "move%.l %2,%0\n\tadd%.l %1,%0";
3377 if (GET_CODE (operands[2]) == REG)
3378 return MOTOROLA ? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
3379 return MOTOROLA ? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
3381 if (GET_CODE (operands[2]) == CONST_INT)
3383 if (INTVAL (operands[2]) > 0
3384 && INTVAL (operands[2]) <= 8)
3385 return "addq%.l %2,%0";
3386 if (INTVAL (operands[2]) < 0
3387 && INTVAL (operands[2]) >= -8)
3389 operands[2] = GEN_INT (- INTVAL (operands[2]));
3390 return "subq%.l %2,%0";
3392 /* On the CPU32 it is faster to use two addql instructions to
3393 add a small integer (8 < N <= 16) to a register.
3394 Likewise for subql. */
3395 if (TUNE_CPU32 && REG_P (operands[0]))
3397 if (INTVAL (operands[2]) > 8
3398 && INTVAL (operands[2]) <= 16)
3400 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
3401 return "addq%.l #8,%0\n\taddq%.l %2,%0";
3403 if (INTVAL (operands[2]) < -8
3404 && INTVAL (operands[2]) >= -16)
3406 operands[2] = GEN_INT (- INTVAL (operands[2]) - 8);
3407 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
3410 if (ADDRESS_REG_P (operands[0])
3411 && INTVAL (operands[2]) >= -0x8000
3412 && INTVAL (operands[2]) < 0x8000)
3415 return "add%.w %2,%0";
3417 return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
3420 return "add%.l %2,%0";
3423 /* Store in cc_status the expressions that the condition codes will
3424 describe after execution of an instruction whose pattern is EXP.
3425 Do not alter them if the instruction would not alter the cc's. */
3427 /* On the 68000, all the insns to store in an address register fail to
3428 set the cc's. However, in some cases these instructions can make it
3429 possibly invalid to use the saved cc's. In those cases we clear out
3430 some or all of the saved cc's so they won't be used. */
3433 notice_update_cc (rtx exp, rtx insn)
3435 if (GET_CODE (exp) == SET)
3437 if (GET_CODE (SET_SRC (exp)) == CALL)
3439 else if (ADDRESS_REG_P (SET_DEST (exp)))
3441 if (cc_status.value1 && modified_in_p (cc_status.value1, insn))
3442 cc_status.value1 = 0;
3443 if (cc_status.value2 && modified_in_p (cc_status.value2, insn))
3444 cc_status.value2 = 0;
3446 /* fmoves to memory or data registers do not set the condition
3447 codes. Normal moves _do_ set the condition codes, but not in
3448 a way that is appropriate for comparison with 0, because -0.0
3449 would be treated as a negative nonzero number. Note that it
3450 isn't appropriate to conditionalize this restriction on
3451 HONOR_SIGNED_ZEROS because that macro merely indicates whether
3452 we care about the difference between -0.0 and +0.0. */
3453 else if (!FP_REG_P (SET_DEST (exp))
3454 && SET_DEST (exp) != cc0_rtx
3455 && (FP_REG_P (SET_SRC (exp))
3456 || GET_CODE (SET_SRC (exp)) == FIX
3457 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp)))))
3459 /* A pair of move insns doesn't produce a useful overall cc. */
3460 else if (!FP_REG_P (SET_DEST (exp))
3461 && !FP_REG_P (SET_SRC (exp))
3462 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4
3463 && (GET_CODE (SET_SRC (exp)) == REG
3464 || GET_CODE (SET_SRC (exp)) == MEM
3465 || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE))
3467 else if (SET_DEST (exp) != pc_rtx)
3469 cc_status.flags = 0;
3470 cc_status.value1 = SET_DEST (exp);
3471 cc_status.value2 = SET_SRC (exp);
3474 else if (GET_CODE (exp) == PARALLEL
3475 && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
3477 rtx dest = SET_DEST (XVECEXP (exp, 0, 0));
3478 rtx src = SET_SRC (XVECEXP (exp, 0, 0));
3480 if (ADDRESS_REG_P (dest))
3482 else if (dest != pc_rtx)
3484 cc_status.flags = 0;
3485 cc_status.value1 = dest;
3486 cc_status.value2 = src;
3491 if (cc_status.value2 != 0
3492 && ADDRESS_REG_P (cc_status.value2)
3493 && GET_MODE (cc_status.value2) == QImode)
3495 if (cc_status.value2 != 0)
3496 switch (GET_CODE (cc_status.value2))
3498 case ASHIFT: case ASHIFTRT: case LSHIFTRT:
3499 case ROTATE: case ROTATERT:
3500 /* These instructions always clear the overflow bit, and set
3501 the carry to the bit shifted out. */
3502 /* ??? We don't currently have a way to signal carry not valid,
3503 nor do we check for it in the branch insns. */
3507 case PLUS: case MINUS: case MULT:
3508 case DIV: case UDIV: case MOD: case UMOD: case NEG:
3509 if (GET_MODE (cc_status.value2) != VOIDmode)
3510 cc_status.flags |= CC_NO_OVERFLOW;
3513 /* (SET r1 (ZERO_EXTEND r2)) on this machine
3514 ends with a move insn moving r2 in r2's mode.
3515 Thus, the cc's are set for r2.
3516 This can set N bit spuriously. */
3517 cc_status.flags |= CC_NOT_NEGATIVE;
3522 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG
3524 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
3525 cc_status.value2 = 0;
3526 if (((cc_status.value1 && FP_REG_P (cc_status.value1))
3527 || (cc_status.value2 && FP_REG_P (cc_status.value2))))
3528 cc_status.flags = CC_IN_68881;
3529 if (cc_status.value2 && GET_CODE (cc_status.value2) == COMPARE
3530 && GET_MODE_CLASS (GET_MODE (XEXP (cc_status.value2, 0))) == MODE_FLOAT)
3532 cc_status.flags = CC_IN_68881;
3533 if (!FP_REG_P (XEXP (cc_status.value2, 0)))
3534 cc_status.flags |= CC_REVERSED;
3539 output_move_const_double (rtx *operands)
3541 int code = standard_68881_constant_p (operands[1]);
3545 static char buf[40];
3547 sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff);
3550 return "fmove%.d %1,%0";
3554 output_move_const_single (rtx *operands)
3556 int code = standard_68881_constant_p (operands[1]);
3560 static char buf[40];
3562 sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff);
3565 return "fmove%.s %f1,%0";
3568 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
3569 from the "fmovecr" instruction.
3570 The value, anded with 0xff, gives the code to use in fmovecr
3571 to get the desired constant. */
3573 /* This code has been fixed for cross-compilation. */
3575 static int inited_68881_table = 0;
3577 static const char *const strings_68881[7] = {
3587 static const int codes_68881[7] = {
3597 REAL_VALUE_TYPE values_68881[7];
3599 /* Set up values_68881 array by converting the decimal values
3600 strings_68881 to binary. */
3603 init_68881_table (void)
3607 enum machine_mode mode;
3610 for (i = 0; i < 7; i++)
3614 r = REAL_VALUE_ATOF (strings_68881[i], mode);
3615 values_68881[i] = r;
3617 inited_68881_table = 1;
3621 standard_68881_constant_p (rtx x)
3626 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
3627 used at all on those chips. */
3631 if (! inited_68881_table)
3632 init_68881_table ();
3634 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3636 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
3638 for (i = 0; i < 6; i++)
3640 if (REAL_VALUES_IDENTICAL (r, values_68881[i]))
3641 return (codes_68881[i]);
3644 if (GET_MODE (x) == SFmode)
3647 if (REAL_VALUES_EQUAL (r, values_68881[6]))
3648 return (codes_68881[6]);
3650 /* larger powers of ten in the constants ram are not used
3651 because they are not equal to a `double' C constant. */
3655 /* If X is a floating-point constant, return the logarithm of X base 2,
3656 or 0 if X is not a power of 2. */
3659 floating_exact_log2 (rtx x)
3661 REAL_VALUE_TYPE r, r1;
3664 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3666 if (REAL_VALUES_LESS (r, dconst1))
3669 exp = real_exponent (&r);
3670 real_2expN (&r1, exp, DFmode);
3671 if (REAL_VALUES_EQUAL (r1, r))
3677 /* A C compound statement to output to stdio stream STREAM the
3678 assembler syntax for an instruction operand X. X is an RTL
3681 CODE is a value that can be used to specify one of several ways
3682 of printing the operand. It is used when identical operands
3683 must be printed differently depending on the context. CODE
3684 comes from the `%' specification that was used to request
3685 printing of the operand. If the specification was just `%DIGIT'
3686 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3687 is the ASCII code for LTR.
3689 If X is a register, this macro should print the register's name.
3690 The names can be found in an array `reg_names' whose type is
3691 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3693 When the machine description has a specification `%PUNCT' (a `%'
3694 followed by a punctuation character), this macro is called with
3695 a null pointer for X and the punctuation character for CODE.
3697 The m68k specific codes are:
3699 '.' for dot needed in Motorola-style opcode names.
3700 '-' for an operand pushing on the stack:
3701 sp@-, -(sp) or -(%sp) depending on the style of syntax.
3702 '+' for an operand pushing on the stack:
3703 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
3704 '@' for a reference to the top word on the stack:
3705 sp@, (sp) or (%sp) depending on the style of syntax.
3706 '#' for an immediate operand prefix (# in MIT and Motorola syntax
3707 but & in SGS syntax).
3708 '!' for the cc register (used in an `and to cc' insn).
3709 '$' for the letter `s' in an op code, but only on the 68040.
3710 '&' for the letter `d' in an op code, but only on the 68040.
3711 '/' for register prefix needed by longlong.h.
3712 '?' for m68k_library_id_string
3714 'b' for byte insn (no effect, on the Sun; this is for the ISI).
3715 'd' to force memory addressing to be absolute, not relative.
3716 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
3717 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
3718 or print pair of registers as rx:ry.
3719 'p' print an address with @PLTPC attached, but only if the operand
3720 is not locally-bound. */
3723 print_operand (FILE *file, rtx op, int letter)
3728 fprintf (file, ".");
3730 else if (letter == '#')
3731 asm_fprintf (file, "%I");
3732 else if (letter == '-')
3733 asm_fprintf (file, MOTOROLA ? "-(%Rsp)" : "%Rsp@-");
3734 else if (letter == '+')
3735 asm_fprintf (file, MOTOROLA ? "(%Rsp)+" : "%Rsp@+");
3736 else if (letter == '@')
3737 asm_fprintf (file, MOTOROLA ? "(%Rsp)" : "%Rsp@");
3738 else if (letter == '!')
3739 asm_fprintf (file, "%Rfpcr");
3740 else if (letter == '$')
3743 fprintf (file, "s");
3745 else if (letter == '&')
3748 fprintf (file, "d");
3750 else if (letter == '/')
3751 asm_fprintf (file, "%R");
3752 else if (letter == '?')
3753 asm_fprintf (file, m68k_library_id_string);
3754 else if (letter == 'p')
3756 output_addr_const (file, op);
3757 if (!(GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op)))
3758 fprintf (file, "@PLTPC");
3760 else if (GET_CODE (op) == REG)
3763 /* Print out the second register name of a register pair.
3764 I.e., R (6) => 7. */
3765 fputs (M68K_REGNAME(REGNO (op) + 1), file);
3767 fputs (M68K_REGNAME(REGNO (op)), file);
3769 else if (GET_CODE (op) == MEM)
3771 output_address (XEXP (op, 0));
3772 if (letter == 'd' && ! TARGET_68020
3773 && CONSTANT_ADDRESS_P (XEXP (op, 0))
3774 && !(GET_CODE (XEXP (op, 0)) == CONST_INT
3775 && INTVAL (XEXP (op, 0)) < 0x8000
3776 && INTVAL (XEXP (op, 0)) >= -0x8000))
3777 fprintf (file, MOTOROLA ? ".l" : ":l");
3779 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode)
3782 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
3783 ASM_OUTPUT_FLOAT_OPERAND (letter, file, r);
3785 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode)
3788 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
3789 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file, r);
3791 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode)
3794 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
3795 ASM_OUTPUT_DOUBLE_OPERAND (file, r);
3799 /* Use `print_operand_address' instead of `output_addr_const'
3800 to ensure that we print relevant PIC stuff. */
3801 asm_fprintf (file, "%I");
3803 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST))
3804 print_operand_address (file, op);
3806 output_addr_const (file, op);
3811 /* A C compound statement to output to stdio stream STREAM the
3812 assembler syntax for an instruction operand that is a memory
3813 reference whose address is ADDR. ADDR is an RTL expression.
3815 Note that this contains a kludge that knows that the only reason
3816 we have an address (plus (label_ref...) (reg...)) when not generating
3817 PIC code is in the insn before a tablejump, and we know that m68k.md
3818 generates a label LInnn: on such an insn.
3820 It is possible for PIC to generate a (plus (label_ref...) (reg...))
3821 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
3823 This routine is responsible for distinguishing between -fpic and -fPIC
3824 style relocations in an address. When generating -fpic code the
3825 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
3826 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
3829 print_operand_address (FILE *file, rtx addr)
3831 struct m68k_address address;
3833 if (!m68k_decompose_address (QImode, addr, true, &address))
3836 if (address.code == PRE_DEC)
3837 fprintf (file, MOTOROLA ? "-(%s)" : "%s@-",
3838 M68K_REGNAME (REGNO (address.base)));
3839 else if (address.code == POST_INC)
3840 fprintf (file, MOTOROLA ? "(%s)+" : "%s@+",
3841 M68K_REGNAME (REGNO (address.base)));
3842 else if (!address.base && !address.index)
3844 /* A constant address. */
3845 gcc_assert (address.offset == addr);
3846 if (GET_CODE (addr) == CONST_INT)
3848 /* (xxx).w or (xxx).l. */
3849 if (IN_RANGE (INTVAL (addr), -0x8000, 0x7fff))
3850 fprintf (file, MOTOROLA ? "%d.w" : "%d:w", (int) INTVAL (addr));
3852 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (addr));
3854 else if (TARGET_PCREL)
3856 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
3858 output_addr_const (file, addr);
3859 asm_fprintf (file, flag_pic == 1 ? ":w,%Rpc)" : ":l,%Rpc)");
3863 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
3864 name ends in `.<letter>', as the last 2 characters can be
3865 mistaken as a size suffix. Put the name in parentheses. */
3866 if (GET_CODE (addr) == SYMBOL_REF
3867 && strlen (XSTR (addr, 0)) > 2
3868 && XSTR (addr, 0)[strlen (XSTR (addr, 0)) - 2] == '.')
3871 output_addr_const (file, addr);
3875 output_addr_const (file, addr);
3882 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
3883 label being accessed, otherwise it is -1. */
3884 labelno = (address.offset
3886 && GET_CODE (address.offset) == LABEL_REF
3887 ? CODE_LABEL_NUMBER (XEXP (address.offset, 0))
3891 /* Print the "offset(base" component. */
3893 asm_fprintf (file, "%LL%d(%Rpc,", labelno);
3898 output_addr_const (file, address.offset);
3899 if (flag_pic && address.base == pic_offset_table_rtx)
3901 fprintf (file, "@GOT");
3902 if (flag_pic == 1 && TARGET_68020)
3903 fprintf (file, ".w");
3908 fputs (M68K_REGNAME (REGNO (address.base)), file);
3910 /* Print the ",index" component, if any. */
3915 fprintf (file, "%s.%c",
3916 M68K_REGNAME (REGNO (address.index)),
3917 GET_MODE (address.index) == HImode ? 'w' : 'l');
3918 if (address.scale != 1)
3919 fprintf (file, "*%d", address.scale);
3923 else /* !MOTOROLA */
3925 if (!address.offset && !address.index)
3926 fprintf (file, "%s@", M68K_REGNAME (REGNO (address.base)));
3929 /* Print the "base@(offset" component. */
3931 asm_fprintf (file, "%Rpc@(%LL%d", labelno);
3935 fputs (M68K_REGNAME (REGNO (address.base)), file);
3936 fprintf (file, "@(");
3939 output_addr_const (file, address.offset);
3940 if (address.base == pic_offset_table_rtx && TARGET_68020)
3944 fprintf (file, ":w"); break;
3946 fprintf (file, ":l"); break;
3952 /* Print the ",index" component, if any. */
3955 fprintf (file, ",%s:%c",
3956 M68K_REGNAME (REGNO (address.index)),
3957 GET_MODE (address.index) == HImode ? 'w' : 'l');
3958 if (address.scale != 1)
3959 fprintf (file, ":%d", address.scale);
3967 /* Check for cases where a clr insns can be omitted from code using
3968 strict_low_part sets. For example, the second clrl here is not needed:
3969 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3971 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3972 insn we are checking for redundancy. TARGET is the register set by the
3976 strict_low_part_peephole_ok (enum machine_mode mode, rtx first_insn,
3981 while ((p = PREV_INSN (p)))
3983 if (NOTE_INSN_BASIC_BLOCK_P (p))
3989 /* If it isn't an insn, then give up. */
3993 if (reg_set_p (target, p))
3995 rtx set = single_set (p);
3998 /* If it isn't an easy to recognize insn, then give up. */
4002 dest = SET_DEST (set);
4004 /* If this sets the entire target register to zero, then our
4005 first_insn is redundant. */
4006 if (rtx_equal_p (dest, target)
4007 && SET_SRC (set) == const0_rtx)
4009 else if (GET_CODE (dest) == STRICT_LOW_PART
4010 && GET_CODE (XEXP (dest, 0)) == REG
4011 && REGNO (XEXP (dest, 0)) == REGNO (target)
4012 && (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0)))
4013 <= GET_MODE_SIZE (mode)))
4014 /* This is a strict low part set which modifies less than
4015 we are using, so it is safe. */
4025 /* Operand predicates for implementing asymmetric pc-relative addressing
4026 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4027 when used as a source operand, but not as a destination operand.
4029 We model this by restricting the meaning of the basic predicates
4030 (general_operand, memory_operand, etc) to forbid the use of this
4031 addressing mode, and then define the following predicates that permit
4032 this addressing mode. These predicates can then be used for the
4033 source operands of the appropriate instructions.
4035 n.b. While it is theoretically possible to change all machine patterns
4036 to use this addressing more where permitted by the architecture,
4037 it has only been implemented for "common" cases: SImode, HImode, and
4038 QImode operands, and only for the principle operations that would
4039 require this addressing mode: data movement and simple integer operations.
4041 In parallel with these new predicates, two new constraint letters
4042 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4043 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4044 In the pcrel case 's' is only valid in combination with 'a' registers.
4045 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4046 of how these constraints are used.
4048 The use of these predicates is strictly optional, though patterns that
4049 don't will cause an extra reload register to be allocated where one
4052 lea (abc:w,%pc),%a0 ; need to reload address
4053 moveq &1,%d1 ; since write to pc-relative space
4054 movel %d1,%a0@ ; is not allowed
4056 lea (abc:w,%pc),%a1 ; no need to reload address here
4057 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4059 For more info, consult tiemann@cygnus.com.
4062 All of the ugliness with predicates and constraints is due to the
4063 simple fact that the m68k does not allow a pc-relative addressing
4064 mode as a destination. gcc does not distinguish between source and
4065 destination addresses. Hence, if we claim that pc-relative address
4066 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
4067 end up with invalid code. To get around this problem, we left
4068 pc-relative modes as invalid addresses, and then added special
4069 predicates and constraints to accept them.
4071 A cleaner way to handle this is to modify gcc to distinguish
4072 between source and destination addresses. We can then say that
4073 pc-relative is a valid source address but not a valid destination
4074 address, and hopefully avoid a lot of the predicate and constraint
4075 hackery. Unfortunately, this would be a pretty big change. It would
4076 be a useful change for a number of ports, but there aren't any current
4077 plans to undertake this.
4079 ***************************************************************************/
4083 output_andsi3 (rtx *operands)
4086 if (GET_CODE (operands[2]) == CONST_INT
4087 && (INTVAL (operands[2]) | 0xffff) == -1
4088 && (DATA_REG_P (operands[0])
4089 || offsettable_memref_p (operands[0]))
4090 && !TARGET_COLDFIRE)
4092 if (GET_CODE (operands[0]) != REG)
4093 operands[0] = adjust_address (operands[0], HImode, 2);
4094 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
4095 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4097 if (operands[2] == const0_rtx)
4099 return "and%.w %2,%0";
4101 if (GET_CODE (operands[2]) == CONST_INT
4102 && (logval = exact_log2 (~ INTVAL (operands[2]))) >= 0
4103 && (DATA_REG_P (operands[0])
4104 || offsettable_memref_p (operands[0])))
4106 if (DATA_REG_P (operands[0]))
4107 operands[1] = GEN_INT (logval);
4110 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
4111 operands[1] = GEN_INT (logval % 8);
4113 /* This does not set condition codes in a standard way. */
4115 return "bclr %1,%0";
4117 return "and%.l %2,%0";
4121 output_iorsi3 (rtx *operands)
4123 register int logval;
4124 if (GET_CODE (operands[2]) == CONST_INT
4125 && INTVAL (operands[2]) >> 16 == 0
4126 && (DATA_REG_P (operands[0])
4127 || offsettable_memref_p (operands[0]))
4128 && !TARGET_COLDFIRE)
4130 if (GET_CODE (operands[0]) != REG)
4131 operands[0] = adjust_address (operands[0], HImode, 2);
4132 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4134 if (INTVAL (operands[2]) == 0xffff)
4135 return "mov%.w %2,%0";
4136 return "or%.w %2,%0";
4138 if (GET_CODE (operands[2]) == CONST_INT
4139 && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
4140 && (DATA_REG_P (operands[0])
4141 || offsettable_memref_p (operands[0])))
4143 if (DATA_REG_P (operands[0]))
4144 operands[1] = GEN_INT (logval);
4147 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
4148 operands[1] = GEN_INT (logval % 8);
4151 return "bset %1,%0";
4153 return "or%.l %2,%0";
4157 output_xorsi3 (rtx *operands)
4159 register int logval;
4160 if (GET_CODE (operands[2]) == CONST_INT
4161 && INTVAL (operands[2]) >> 16 == 0
4162 && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0]))
4163 && !TARGET_COLDFIRE)
4165 if (! DATA_REG_P (operands[0]))
4166 operands[0] = adjust_address (operands[0], HImode, 2);
4167 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4169 if (INTVAL (operands[2]) == 0xffff)
4171 return "eor%.w %2,%0";
4173 if (GET_CODE (operands[2]) == CONST_INT
4174 && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
4175 && (DATA_REG_P (operands[0])
4176 || offsettable_memref_p (operands[0])))
4178 if (DATA_REG_P (operands[0]))
4179 operands[1] = GEN_INT (logval);
4182 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
4183 operands[1] = GEN_INT (logval % 8);
4186 return "bchg %1,%0";
4188 return "eor%.l %2,%0";
4191 /* Return the instruction that should be used for a call to address X,
4192 which is known to be in operand 0. */
4197 if (symbolic_operand (x, VOIDmode))
4198 return m68k_symbolic_call;
4203 /* Likewise sibling calls. */
4206 output_sibcall (rtx x)
4208 if (symbolic_operand (x, VOIDmode))
4209 return m68k_symbolic_jump;
4214 #ifdef M68K_TARGET_COFF
4216 /* Output assembly to switch to section NAME with attribute FLAGS. */
4219 m68k_coff_asm_named_section (const char *name, unsigned int flags,
4220 tree decl ATTRIBUTE_UNUSED)
4224 if (flags & SECTION_WRITE)
4229 fprintf (asm_out_file, "\t.section\t%s,\"%c\"\n", name, flagchar);
4232 #endif /* M68K_TARGET_COFF */
4235 m68k_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
4236 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
4239 rtx this_slot, offset, addr, mem, insn;
4241 /* Pretend to be a post-reload pass while generating rtl. */
4242 reload_completed = 1;
4244 /* The "this" pointer is stored at 4(%sp). */
4245 this_slot = gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, 4));
4247 /* Add DELTA to THIS. */
4250 /* Make the offset a legitimate operand for memory addition. */
4251 offset = GEN_INT (delta);
4252 if ((delta < -8 || delta > 8)
4253 && (TARGET_COLDFIRE || USE_MOVQ (delta)))
4255 emit_move_insn (gen_rtx_REG (Pmode, D0_REG), offset);
4256 offset = gen_rtx_REG (Pmode, D0_REG);
4258 emit_insn (gen_add3_insn (copy_rtx (this_slot),
4259 copy_rtx (this_slot), offset));
4262 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
4263 if (vcall_offset != 0)
4265 /* Set the static chain register to *THIS. */
4266 emit_move_insn (static_chain_rtx, this_slot);
4267 emit_move_insn (static_chain_rtx, gen_rtx_MEM (Pmode, static_chain_rtx));
4269 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
4270 addr = plus_constant (static_chain_rtx, vcall_offset);
4271 if (!m68k_legitimate_address_p (Pmode, addr, true))
4273 emit_insn (gen_rtx_SET (VOIDmode, static_chain_rtx, addr));
4274 addr = static_chain_rtx;
4277 /* Load the offset into %d0 and add it to THIS. */
4278 emit_move_insn (gen_rtx_REG (Pmode, D0_REG),
4279 gen_rtx_MEM (Pmode, addr));
4280 emit_insn (gen_add3_insn (copy_rtx (this_slot),
4281 copy_rtx (this_slot),
4282 gen_rtx_REG (Pmode, D0_REG)));
4285 /* Jump to the target function. Use a sibcall if direct jumps are
4286 allowed, otherwise load the address into a register first. */
4287 mem = DECL_RTL (function);
4288 if (!sibcall_operand (XEXP (mem, 0), VOIDmode))
4290 gcc_assert (flag_pic);
4292 if (!TARGET_SEP_DATA)
4294 /* Use the static chain register as a temporary (call-clobbered)
4295 GOT pointer for this function. We can use the static chain
4296 register because it isn't live on entry to the thunk. */
4297 SET_REGNO (pic_offset_table_rtx, STATIC_CHAIN_REGNUM);
4298 emit_insn (gen_load_got (pic_offset_table_rtx));
4300 legitimize_pic_address (XEXP (mem, 0), Pmode, static_chain_rtx);
4301 mem = replace_equiv_address (mem, static_chain_rtx);
4303 insn = emit_call_insn (gen_sibcall (mem, const0_rtx));
4304 SIBLING_CALL_P (insn) = 1;
4306 /* Run just enough of rest_of_compilation. */
4307 insn = get_insns ();
4308 split_all_insns_noflow ();
4309 final_start_function (insn, file, 1);
4310 final (insn, file, 1);
4311 final_end_function ();
4313 /* Clean up the vars set above. */
4314 reload_completed = 0;
4316 /* Restore the original PIC register. */
4318 SET_REGNO (pic_offset_table_rtx, PIC_REG);
4321 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
4324 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
4325 int incoming ATTRIBUTE_UNUSED)
4327 return gen_rtx_REG (Pmode, M68K_STRUCT_VALUE_REGNUM);
4330 /* Return nonzero if register old_reg can be renamed to register new_reg. */
4332 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
4333 unsigned int new_reg)
4336 /* Interrupt functions can only use registers that have already been
4337 saved by the prologue, even if they would normally be
4340 if ((m68k_get_function_kind (current_function_decl)
4341 == m68k_fk_interrupt_handler)
4342 && !df_regs_ever_live_p (new_reg))
4348 /* Value is true if hard register REGNO can hold a value of machine-mode
4349 MODE. On the 68000, we let the cpu registers can hold any mode, but
4350 restrict the 68881 registers to floating-point modes. */
4353 m68k_regno_mode_ok (int regno, enum machine_mode mode)
4355 if (DATA_REGNO_P (regno))
4357 /* Data Registers, can hold aggregate if fits in. */
4358 if (regno + GET_MODE_SIZE (mode) / 4 <= 8)
4361 else if (ADDRESS_REGNO_P (regno))
4363 if (regno + GET_MODE_SIZE (mode) / 4 <= 16)
4366 else if (FP_REGNO_P (regno))
4368 /* FPU registers, hold float or complex float of long double or
4370 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
4371 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4372 && GET_MODE_UNIT_SIZE (mode) <= TARGET_FP_REG_SIZE)
4378 /* Implement SECONDARY_RELOAD_CLASS. */
4381 m68k_secondary_reload_class (enum reg_class rclass,
4382 enum machine_mode mode, rtx x)
4386 regno = true_regnum (x);
4388 /* If one operand of a movqi is an address register, the other
4389 operand must be a general register or constant. Other types
4390 of operand must be reloaded through a data register. */
4391 if (GET_MODE_SIZE (mode) == 1
4392 && reg_classes_intersect_p (rclass, ADDR_REGS)
4393 && !(INT_REGNO_P (regno) || CONSTANT_P (x)))
4396 /* PC-relative addresses must be loaded into an address register first. */
4398 && !reg_class_subset_p (rclass, ADDR_REGS)
4399 && symbolic_operand (x, VOIDmode))
4405 /* Implement PREFERRED_RELOAD_CLASS. */
4408 m68k_preferred_reload_class (rtx x, enum reg_class rclass)
4410 enum reg_class secondary_class;
4412 /* If RCLASS might need a secondary reload, try restricting it to
4413 a class that doesn't. */
4414 secondary_class = m68k_secondary_reload_class (rclass, GET_MODE (x), x);
4415 if (secondary_class != NO_REGS
4416 && reg_class_subset_p (secondary_class, rclass))
4417 return secondary_class;
4419 /* Prefer to use moveq for in-range constants. */
4420 if (GET_CODE (x) == CONST_INT
4421 && reg_class_subset_p (DATA_REGS, rclass)
4422 && IN_RANGE (INTVAL (x), -0x80, 0x7f))
4425 /* ??? Do we really need this now? */
4426 if (GET_CODE (x) == CONST_DOUBLE
4427 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
4429 if (TARGET_HARD_FLOAT && reg_class_subset_p (FP_REGS, rclass))
4438 /* Return floating point values in a 68881 register. This makes 68881 code
4439 a little bit faster. It also makes -msoft-float code incompatible with
4440 hard-float code, so people have to be careful not to mix the two.
4441 For ColdFire it was decided the ABI incompatibility is undesirable.
4442 If there is need for a hard-float ABI it is probably worth doing it
4443 properly and also passing function arguments in FP registers. */
4445 m68k_libcall_value (enum machine_mode mode)
4452 return gen_rtx_REG (mode, FP0_REG);
4457 return gen_rtx_REG (mode, D0_REG);
4461 m68k_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED)
4463 enum machine_mode mode;
4465 mode = TYPE_MODE (valtype);
4471 return gen_rtx_REG (mode, FP0_REG);
4477 /* If the function returns a pointer, push that into %a0. */
4478 if (func && POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func))))
4479 /* For compatibility with the large body of existing code which
4480 does not always properly declare external functions returning
4481 pointer types, the m68k/SVR4 convention is to copy the value
4482 returned for pointer functions from a0 to d0 in the function
4483 epilogue, so that callers that have neglected to properly
4484 declare the callee can still find the correct return value in
4486 return gen_rtx_PARALLEL
4489 gen_rtx_EXPR_LIST (VOIDmode,
4490 gen_rtx_REG (mode, A0_REG),
4492 gen_rtx_EXPR_LIST (VOIDmode,
4493 gen_rtx_REG (mode, D0_REG),
4495 else if (POINTER_TYPE_P (valtype))
4496 return gen_rtx_REG (mode, A0_REG);
4498 return gen_rtx_REG (mode, D0_REG);
4501 /* Worker function for TARGET_RETURN_IN_MEMORY. */
4502 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
4504 m68k_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4506 enum machine_mode mode = TYPE_MODE (type);
4508 if (mode == BLKmode)
4511 /* If TYPE's known alignment is less than the alignment of MODE that
4512 would contain the structure, then return in memory. We need to
4513 do so to maintain the compatibility between code compiled with
4514 -mstrict-align and that compiled with -mno-strict-align. */
4515 if (AGGREGATE_TYPE_P (type)
4516 && TYPE_ALIGN (type) < GET_MODE_ALIGNMENT (mode))
4523 /* CPU to schedule the program for. */
4524 enum attr_cpu m68k_sched_cpu;
4535 /* Implicit mem reference (e.g. stack). */
4538 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
4541 /* Memory with offset but without indexing. EA mode 5. */
4544 /* Memory with indexing. EA mode 6. */
4547 /* Memory referenced by absolute address. EA mode 7. */
4550 /* Immediate operand that doesn't require extension word. */
4553 /* Immediate 16 bit operand. */
4556 /* Immediate 32 bit operand. */
4560 /* True if current insn doesn't have complete pipeline description. */
4561 static bool sched_guess_p;
4563 /* Return type of memory ADDR_RTX refers to. */
4564 static enum attr_op_type
4565 sched_address_type (enum machine_mode mode, rtx addr_rtx)
4567 struct m68k_address address;
4569 if (!m68k_decompose_address (mode, addr_rtx,
4570 reload_completed, &address))
4572 gcc_assert (sched_guess_p);
4573 /* Reload will likely fix the address to be in the register. */
4574 return OP_TYPE_MEM234;
4577 if (address.scale != 0)
4578 return OP_TYPE_MEM6;
4580 if (address.base != NULL_RTX)
4582 if (address.offset == NULL_RTX)
4583 return OP_TYPE_MEM234;
4585 return OP_TYPE_MEM5;
4588 gcc_assert (address.offset != NULL_RTX);
4590 return OP_TYPE_MEM7;
4593 /* Return type of the operand OP.
4594 If ADDRESS_P is true, return type of memory location OP refers to. */
4595 static enum attr_op_type
4596 sched_operand_type (rtx op, bool address_p)
4598 gcc_assert (op != NULL_RTX);
4601 return sched_address_type (QImode, op);
4603 if (memory_operand (op, VOIDmode))
4604 return sched_address_type (GET_MODE (op), XEXP (op, 0));
4606 if (register_operand (op, VOIDmode))
4609 if (GET_CODE (op) == CONST_INT)
4611 /* ??? Below condition should probably check if the operation is
4612 signed or unsigned. */
4613 if (IN_RANGE (INTVAL (op), -0x8000, 0x7fff))
4614 return OP_TYPE_IMM_W;
4616 return OP_TYPE_IMM_L;
4619 if (GET_CODE (op) == CONST_DOUBLE)
4621 switch (GET_MODE (op))
4624 return OP_TYPE_IMM_W;
4628 return OP_TYPE_IMM_L;
4635 if (symbolic_operand (op, VOIDmode)
4638 switch (GET_MODE (op))
4641 return OP_TYPE_IMM_Q;
4644 return OP_TYPE_IMM_W;
4647 return OP_TYPE_IMM_L;
4650 if (GET_CODE (op) == SYMBOL_REF)
4651 /* ??? Just a guess. Probably we can guess better using length
4652 attribute of the instructions. */
4653 return OP_TYPE_IMM_W;
4655 return OP_TYPE_IMM_L;
4659 gcc_assert (sched_guess_p);
4664 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
4665 If ADDRESS_P is true, return type of memory location operand refers to. */
4666 static enum attr_op_type
4667 sched_attr_op_type (rtx insn, bool opx_p, bool address_p)
4671 extract_constrain_insn_cached (insn);
4674 i = get_attr_opx (insn);
4676 i = get_attr_opy (insn);
4678 if (i >= recog_data.n_operands)
4680 gcc_assert (sched_guess_p);
4684 return sched_operand_type (recog_data.operand[i], address_p);
4687 /* Implement opx_type attribute.
4688 Return type of INSN's operand X.
4689 If ADDRESS_P is true, return type of memory location operand refers to. */
4691 m68k_sched_attr_opx_type (rtx insn, int address_p)
4693 sched_guess_p = (get_attr_guess (insn) == GUESS_YES);
4695 switch (sched_attr_op_type (insn, true, address_p != 0))
4698 return OPX_TYPE_REG;
4701 return OPX_TYPE_MEM1;
4703 case OP_TYPE_MEM234:
4704 return OPX_TYPE_MEM234;
4707 return OPX_TYPE_MEM5;
4710 return OPX_TYPE_MEM6;
4713 return OPX_TYPE_MEM7;
4716 return OPX_TYPE_IMM_Q;
4719 return OPX_TYPE_IMM_W;
4722 return OPX_TYPE_IMM_L;
4730 /* Implement opy_type attribute.
4731 Return type of INSN's operand Y.
4732 If ADDRESS_P is true, return type of memory location operand refers to. */
4734 m68k_sched_attr_opy_type (rtx insn, int address_p)
4736 sched_guess_p = (get_attr_guess (insn) == GUESS_YES);
4738 switch (sched_attr_op_type (insn, false, address_p != 0))
4741 return OPY_TYPE_REG;
4744 return OPY_TYPE_MEM1;
4746 case OP_TYPE_MEM234:
4747 return OPY_TYPE_MEM234;
4750 return OPY_TYPE_MEM5;
4753 return OPY_TYPE_MEM6;
4756 return OPY_TYPE_MEM7;
4759 return OPY_TYPE_IMM_Q;
4762 return OPY_TYPE_IMM_W;
4765 return OPY_TYPE_IMM_L;
4773 /* Return the size of INSN. */
4775 m68k_sched_attr_size (rtx insn)
4779 sched_guess_p = (get_attr_guess (insn) == GUESS_YES);
4781 switch (get_attr_type1 (insn))
4792 switch (get_attr_opx_type (insn))
4797 case OPX_TYPE_MEM234:
4798 case OPY_TYPE_IMM_Q:
4803 /* Here we assume that most absolute references are short. */
4805 case OPY_TYPE_IMM_W:
4809 case OPY_TYPE_IMM_L:
4817 switch (get_attr_opy_type (insn))
4822 case OPY_TYPE_MEM234:
4823 case OPY_TYPE_IMM_Q:
4828 /* Here we assume that most absolute references are short. */
4830 case OPY_TYPE_IMM_W:
4834 case OPY_TYPE_IMM_L:
4844 gcc_assert (sched_guess_p);
4852 /* Implement op_mem attribute. */
4854 m68k_sched_attr_op_mem (rtx insn)
4856 enum attr_opy_mem opy;
4857 enum attr_opx_mem opx;
4859 sched_guess_p = (get_attr_guess (insn) == GUESS_YES);
4861 opy = get_attr_opy_mem (insn);
4862 opx = get_attr_opx_mem (insn);
4864 if (opy == OPY_MEM_R && opx == OPX_MEM_R)
4867 if (opy == OPY_MEM_R && opx == OPX_MEM_M)
4869 switch (get_attr_opx_access (insn))
4881 gcc_assert (sched_guess_p);
4882 return OP_MEM_UNKNOWN;
4886 if (opy == OPY_MEM_R && opx == OPX_MEM_I)
4888 switch (get_attr_opx_access (insn))
4900 gcc_assert (sched_guess_p);
4901 return OP_MEM_UNKNOWN;
4905 if (opy == OPY_MEM_M && opx == OPX_MEM_R)
4908 if (opy == OPY_MEM_M && opx == OPX_MEM_M)
4910 switch (get_attr_opx_access (insn))
4916 gcc_assert (sched_guess_p);
4917 return OP_MEM_UNKNOWN;
4921 if (opy == OPY_MEM_M && opx == OPX_MEM_I)
4923 switch (get_attr_opx_access (insn))
4929 gcc_assert (sched_guess_p);
4930 return OP_MEM_UNKNOWN;
4934 if (opy == OPY_MEM_I && opx == OPX_MEM_R)
4938 if (opy == OPY_MEM_I && opx == OPX_MEM_M)
4940 switch (get_attr_opx_access (insn))
4946 gcc_assert (sched_guess_p);
4947 return OP_MEM_UNKNOWN;
4951 gcc_assert (sched_guess_p);
4952 return OP_MEM_UNKNOWN;
4955 /* Jump instructions types. Indexed by INSN_UID.
4956 The same rtl insn can be expanded into different asm instructions
4957 depending on the cc0_status. To properly determine type of jump
4958 instructions we scan instruction stream and map jumps types to this
4960 static enum attr_type *sched_branch_type;
4962 /* Return the type of the jump insn. */
4964 m68k_sched_branch_type (rtx insn)
4966 enum attr_type type;
4968 type = sched_branch_type[INSN_UID (insn)];
4970 gcc_assert (type != 0);