1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "target-def.h"
48 enum reg_class regno_reg_class[] =
50 DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS,
51 DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS,
52 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
53 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
54 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
55 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
60 /* The ASM_DOT macro allows easy string pasting to handle the differences
61 between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't
62 support the %. option. */
65 # define ASM_DOTW ".w"
66 # define ASM_DOTL ".l"
74 /* The minimum number of integer registers that we want to save with the
75 movem instruction. Using two movel instructions instead of a single
76 moveml is about 15% faster for the 68020 and 68030 at no expense in
78 #define MIN_MOVEM_REGS 3
80 /* The minimum number of floating point registers that we want to save
81 with the fmovem instruction. */
82 #define MIN_FMOVEM_REGS 1
84 /* Structure describing stack frame layout. */
87 /* Stack pointer to frame pointer offset. */
90 /* Offset of FPU registers. */
91 HOST_WIDE_INT foffset;
93 /* Frame size in bytes (rounded up). */
96 /* Data and address register. */
98 unsigned int reg_mask;
102 unsigned int fpu_mask;
104 /* Offsets relative to ARG_POINTER. */
105 HOST_WIDE_INT frame_pointer_offset;
106 HOST_WIDE_INT stack_pointer_offset;
108 /* Function which the above information refers to. */
112 /* Current frame information calculated by m68k_compute_frame_layout(). */
113 static struct m68k_frame current_frame;
115 /* Structure describing an m68k address.
117 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
118 with null fields evaluating to 0. Here:
120 - BASE satisfies m68k_legitimate_base_reg_p
121 - INDEX satisfies m68k_legitimate_index_reg_p
122 - OFFSET satisfies m68k_legitimate_constant_address_p
124 INDEX is either HImode or SImode. The other fields are SImode.
126 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
127 the address is (BASE)+. */
128 struct m68k_address {
136 static bool m68k_handle_option (size_t, const char *, int);
137 static rtx find_addr_reg (rtx);
138 static const char *singlemove_string (rtx *);
139 #ifdef M68K_TARGET_COFF
140 static void m68k_coff_asm_named_section (const char *, unsigned int, tree);
141 #endif /* M68K_TARGET_COFF */
142 static void m68k_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
143 HOST_WIDE_INT, tree);
144 static rtx m68k_struct_value_rtx (tree, int);
145 static tree m68k_handle_fndecl_attribute (tree *node, tree name,
146 tree args, int flags,
148 static void m68k_compute_frame_layout (void);
149 static bool m68k_save_reg (unsigned int regno, bool interrupt_handler);
150 static bool m68k_ok_for_sibcall_p (tree, tree);
151 static bool m68k_rtx_costs (rtx, int, int, int *);
154 /* Specify the identification number of the library being built */
155 const char *m68k_library_id_string = "_current_shared_library_a5_offset_";
157 /* Nonzero if the last compare/test insn had FP operands. The
158 sCC expanders peek at this to determine what to do for the
159 68060, which has no fsCC instructions. */
160 int m68k_last_compare_had_fp_operands;
162 /* Initialize the GCC target structure. */
164 #if INT_OP_GROUP == INT_OP_DOT_WORD
165 #undef TARGET_ASM_ALIGNED_HI_OP
166 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
169 #if INT_OP_GROUP == INT_OP_NO_DOT
170 #undef TARGET_ASM_BYTE_OP
171 #define TARGET_ASM_BYTE_OP "\tbyte\t"
172 #undef TARGET_ASM_ALIGNED_HI_OP
173 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
174 #undef TARGET_ASM_ALIGNED_SI_OP
175 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
178 #if INT_OP_GROUP == INT_OP_DC
179 #undef TARGET_ASM_BYTE_OP
180 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
181 #undef TARGET_ASM_ALIGNED_HI_OP
182 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
183 #undef TARGET_ASM_ALIGNED_SI_OP
184 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
187 #undef TARGET_ASM_UNALIGNED_HI_OP
188 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
189 #undef TARGET_ASM_UNALIGNED_SI_OP
190 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
192 #undef TARGET_ASM_OUTPUT_MI_THUNK
193 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
194 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
195 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
197 #undef TARGET_ASM_FILE_START_APP_OFF
198 #define TARGET_ASM_FILE_START_APP_OFF true
200 #undef TARGET_DEFAULT_TARGET_FLAGS
201 #define TARGET_DEFAULT_TARGET_FLAGS MASK_STRICT_ALIGNMENT
202 #undef TARGET_HANDLE_OPTION
203 #define TARGET_HANDLE_OPTION m68k_handle_option
205 #undef TARGET_RTX_COSTS
206 #define TARGET_RTX_COSTS m68k_rtx_costs
208 #undef TARGET_ATTRIBUTE_TABLE
209 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
211 #undef TARGET_PROMOTE_PROTOTYPES
212 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
214 #undef TARGET_STRUCT_VALUE_RTX
215 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
217 #undef TARGET_CANNOT_FORCE_CONST_MEM
218 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_illegitimate_symbolic_constant_p
220 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
221 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
223 static const struct attribute_spec m68k_attribute_table[] =
225 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
226 { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute },
227 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute },
228 { "interrupt_thread", 0, 0, true, false, false, m68k_handle_fndecl_attribute },
229 { NULL, 0, 0, false, false, false, NULL }
232 struct gcc_target targetm = TARGET_INITIALIZER;
234 /* Base flags for 68k ISAs. */
235 #define FL_FOR_isa_00 FL_ISA_68000
236 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
237 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
238 generated 68881 code for 68020 and 68030 targets unless explicitly told
240 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
241 | FL_BITFIELD | FL_68881)
242 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
243 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
245 /* Base flags for ColdFire ISAs. */
246 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
247 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
248 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
249 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
250 #define FL_FOR_isa_c (FL_FOR_isa_b | FL_ISA_C | FL_CF_USP)
254 /* Traditional 68000 instruction sets. */
260 /* ColdFire instruction set variants. */
268 /* Information about one of the -march, -mcpu or -mtune arguments. */
269 struct m68k_target_selection
271 /* The argument being described. */
274 /* For -mcpu, this is the device selected by the option.
275 For -mtune and -march, it is a representative device
276 for the microarchitecture or ISA respectively. */
277 enum target_device device;
279 /* The M68K_DEVICE fields associated with DEVICE. See the comment
280 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
282 enum uarch_type microarch;
287 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
288 static const struct m68k_target_selection all_devices[] =
290 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
291 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
292 #include "m68k-devices.def"
294 { NULL, unk_device, NULL, unk_arch, isa_max, 0 }
297 /* A list of all ISAs, mapping each one to a representative device.
298 Used for -march selection. */
299 static const struct m68k_target_selection all_isas[] =
301 { "68000", m68000, NULL, u68000, isa_00, FL_FOR_isa_00 },
302 { "68010", m68010, NULL, u68010, isa_10, FL_FOR_isa_10 },
303 { "68020", m68020, NULL, u68020, isa_20, FL_FOR_isa_20 },
304 { "68030", m68030, NULL, u68030, isa_20, FL_FOR_isa_20 },
305 { "68040", m68040, NULL, u68040, isa_40, FL_FOR_isa_40 },
306 { "68060", m68060, NULL, u68060, isa_40, FL_FOR_isa_40 },
307 { "cpu32", cpu32, NULL, ucpu32, isa_20, FL_FOR_isa_cpu32 },
308 { "isaa", mcf5206e, NULL, ucfv2, isa_a, (FL_FOR_isa_a
310 { "isaaplus", mcf5271, NULL, ucfv2, isa_aplus, (FL_FOR_isa_aplus
312 { "isab", mcf5407, NULL, ucfv4, isa_b, FL_FOR_isa_b },
313 { "isac", unk_device, NULL, ucfv4, isa_c, (FL_FOR_isa_c
316 { NULL, unk_device, NULL, unk_arch, isa_max, 0 }
319 /* A list of all microarchitectures, mapping each one to a representative
320 device. Used for -mtune selection. */
321 static const struct m68k_target_selection all_microarchs[] =
323 { "68000", m68000, NULL, u68000, isa_00, FL_FOR_isa_00 },
324 { "68010", m68010, NULL, u68010, isa_10, FL_FOR_isa_10 },
325 { "68020", m68020, NULL, u68020, isa_20, FL_FOR_isa_20 },
326 { "68020-40", m68020, NULL, u68020_40, isa_20, FL_FOR_isa_20 },
327 { "68020-60", m68020, NULL, u68020_60, isa_20, FL_FOR_isa_20 },
328 { "68030", m68030, NULL, u68030, isa_20, FL_FOR_isa_20 },
329 { "68040", m68040, NULL, u68040, isa_40, FL_FOR_isa_40 },
330 { "68060", m68060, NULL, u68060, isa_40, FL_FOR_isa_40 },
331 { "cpu32", cpu32, NULL, ucpu32, isa_20, FL_FOR_isa_cpu32 },
332 { "cfv2", mcf5206, NULL, ucfv2, isa_a, FL_FOR_isa_a },
333 { "cfv3", mcf5307, NULL, ucfv3, isa_a, (FL_FOR_isa_a
335 { "cfv4", mcf5407, NULL, ucfv4, isa_b, FL_FOR_isa_b },
336 { "cfv4e", mcf547x, NULL, ucfv4e, isa_b, (FL_FOR_isa_b
340 { NULL, unk_device, NULL, unk_arch, isa_max, 0 }
343 /* The entries associated with the -mcpu, -march and -mtune settings,
344 or null for options that have not been used. */
345 const struct m68k_target_selection *m68k_cpu_entry;
346 const struct m68k_target_selection *m68k_arch_entry;
347 const struct m68k_target_selection *m68k_tune_entry;
349 /* Which CPU we are generating code for. */
350 enum target_device m68k_cpu;
352 /* Which microarchitecture to tune for. */
353 enum uarch_type m68k_tune;
355 /* Which FPU to use. */
356 enum fpu_type m68k_fpu;
358 /* The set of FL_* flags that apply to the target processor. */
359 unsigned int m68k_cpu_flags;
361 /* Asm templates for calling or jumping to an arbitrary symbolic address,
362 or NULL if such calls or jumps are not supported. The address is held
364 const char *m68k_symbolic_call;
365 const char *m68k_symbolic_jump;
367 /* See whether TABLE has an entry with name NAME. Return true and
368 store the entry in *ENTRY if so, otherwise return false and
369 leave *ENTRY alone. */
372 m68k_find_selection (const struct m68k_target_selection **entry,
373 const struct m68k_target_selection *table,
378 for (i = 0; table[i].name; i++)
379 if (strcmp (table[i].name, name) == 0)
387 /* Implement TARGET_HANDLE_OPTION. */
390 m68k_handle_option (size_t code, const char *arg, int value)
395 return m68k_find_selection (&m68k_arch_entry, all_isas, arg);
398 return m68k_find_selection (&m68k_cpu_entry, all_devices, arg);
401 return m68k_find_selection (&m68k_tune_entry, all_microarchs, arg);
404 return m68k_find_selection (&m68k_cpu_entry, all_devices, "5206");
407 return m68k_find_selection (&m68k_cpu_entry, all_devices, "5206e");
410 return m68k_find_selection (&m68k_cpu_entry, all_devices, "528x");
413 return m68k_find_selection (&m68k_cpu_entry, all_devices, "5307");
416 return m68k_find_selection (&m68k_cpu_entry, all_devices, "5407");
419 return m68k_find_selection (&m68k_cpu_entry, all_devices, "547x");
423 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68000");
426 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68010");
430 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68020");
433 return (m68k_find_selection (&m68k_tune_entry, all_microarchs,
435 && m68k_find_selection (&m68k_cpu_entry, all_devices, "68020"));
438 return (m68k_find_selection (&m68k_tune_entry, all_microarchs,
440 && m68k_find_selection (&m68k_cpu_entry, all_devices, "68020"));
443 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68030");
446 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68040");
449 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68060");
452 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68302");
456 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68332");
458 case OPT_mshared_library_id_:
459 if (value > MAX_LIBRARY_ID)
460 error ("-mshared-library-id=%s is not between 0 and %d",
461 arg, MAX_LIBRARY_ID);
463 asprintf ((char **) &m68k_library_id_string, "%d", (value * -4) - 4);
471 /* Sometimes certain combinations of command options do not make
472 sense on a particular target machine. You can define a macro
473 `OVERRIDE_OPTIONS' to take account of this. This macro, if
474 defined, is executed once just after all the command options have
477 Don't use this macro to turn on various extra optimizations for
478 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
481 override_options (void)
483 const struct m68k_target_selection *entry;
484 unsigned long target_mask;
492 -march=ARCH should generate code that runs any processor
493 implementing architecture ARCH. -mcpu=CPU should override -march
494 and should generate code that runs on processor CPU, making free
495 use of any instructions that CPU understands. -mtune=UARCH applies
496 on top of -mcpu or -march and optimizes the code for UARCH. It does
497 not change the target architecture. */
500 /* Complain if the -march setting is for a different microarchitecture,
501 or includes flags that the -mcpu setting doesn't. */
503 && (m68k_arch_entry->microarch != m68k_cpu_entry->microarch
504 || (m68k_arch_entry->flags & ~m68k_cpu_entry->flags) != 0))
505 warning (0, "-mcpu=%s conflicts with -march=%s",
506 m68k_cpu_entry->name, m68k_arch_entry->name);
508 entry = m68k_cpu_entry;
511 entry = m68k_arch_entry;
514 entry = all_devices + TARGET_CPU_DEFAULT;
516 m68k_cpu_flags = entry->flags;
518 /* Use the architecture setting to derive default values for
521 if ((m68k_cpu_flags & FL_BITFIELD) != 0)
522 target_mask |= MASK_BITFIELD;
523 if ((m68k_cpu_flags & FL_CF_HWDIV) != 0)
524 target_mask |= MASK_CF_HWDIV;
525 if ((m68k_cpu_flags & (FL_68881 | FL_CF_FPU)) != 0)
526 target_mask |= MASK_HARD_FLOAT;
527 target_flags |= target_mask & ~target_flags_explicit;
529 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
530 m68k_cpu = entry->device;
532 m68k_tune = m68k_tune_entry->microarch;
533 #ifdef M68K_DEFAULT_TUNE
534 else if (!m68k_cpu_entry && !m68k_arch_entry)
535 m68k_tune = M68K_DEFAULT_TUNE;
538 m68k_tune = entry->microarch;
540 /* Set the type of FPU. */
541 m68k_fpu = (!TARGET_HARD_FLOAT ? FPUTYPE_NONE
542 : (m68k_cpu_flags & FL_COLDFIRE) != 0 ? FPUTYPE_COLDFIRE
545 /* Sanity check to ensure that msep-data and mid-sahred-library are not
546 * both specified together. Doing so simply doesn't make sense.
548 if (TARGET_SEP_DATA && TARGET_ID_SHARED_LIBRARY)
549 error ("cannot specify both -msep-data and -mid-shared-library");
551 /* If we're generating code for a separate A5 relative data segment,
552 * we've got to enable -fPIC as well. This might be relaxable to
553 * -fpic but it hasn't been tested properly.
555 if (TARGET_SEP_DATA || TARGET_ID_SHARED_LIBRARY)
558 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
559 error if the target does not support them. */
560 if (TARGET_PCREL && !TARGET_68020 && flag_pic == 2)
561 error ("-mpcrel -fPIC is not currently supported on selected cpu");
563 /* ??? A historic way of turning on pic, or is this intended to
564 be an embedded thing that doesn't have the same name binding
565 significance that it does on hosted ELF systems? */
566 if (TARGET_PCREL && flag_pic == 0)
571 #if MOTOROLA && !defined (USE_GAS)
572 m68k_symbolic_call = "jsr %a0";
573 m68k_symbolic_jump = "jmp %a0";
575 m68k_symbolic_call = "jbsr %a0";
576 m68k_symbolic_jump = "jra %a0";
579 else if (TARGET_ID_SHARED_LIBRARY)
580 /* All addresses must be loaded from the GOT. */
582 else if (TARGET_68020 || TARGET_ISAB)
586 m68k_symbolic_call = "bsr.l %c0";
587 m68k_symbolic_jump = "bra.l %c0";
592 m68k_symbolic_call = "bsr.l %p0";
593 m68k_symbolic_jump = "bra.l %p0";
595 m68k_symbolic_call = "bsr %p0";
596 m68k_symbolic_jump = "bra %p0";
599 /* Turn off function cse if we are doing PIC. We always want
600 function call to be done as `bsr foo@PLTPC'. */
601 /* ??? It's traditional to do this for -mpcrel too, but it isn't
602 clear how intentional that is. */
603 flag_no_function_cse = 1;
606 SUBTARGET_OVERRIDE_OPTIONS;
609 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
610 given argument and NAME is the argument passed to -mcpu. Return NULL
611 if -mcpu was not passed. */
614 m68k_cpp_cpu_ident (const char *prefix)
618 return concat ("__m", prefix, "_cpu_", m68k_cpu_entry->name, NULL);
621 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
622 given argument and NAME is the name of the representative device for
623 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
626 m68k_cpp_cpu_family (const char *prefix)
630 return concat ("__m", prefix, "_family_", m68k_cpu_entry->family, NULL);
633 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
634 "interrupt_handler" attribute and interrupt_thread if FUNC has an
635 "interrupt_thread" attribute. Otherwise, return
636 m68k_fk_normal_function. */
638 enum m68k_function_kind
639 m68k_get_function_kind (tree func)
643 if (TREE_CODE (func) != FUNCTION_DECL)
646 a = lookup_attribute ("interrupt", DECL_ATTRIBUTES (func));
648 return m68k_fk_interrupt_handler;
650 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
652 return m68k_fk_interrupt_handler;
654 a = lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func));
656 return m68k_fk_interrupt_thread;
658 return m68k_fk_normal_function;
661 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
662 struct attribute_spec.handler. */
664 m68k_handle_fndecl_attribute (tree *node, tree name,
665 tree args ATTRIBUTE_UNUSED,
666 int flags ATTRIBUTE_UNUSED,
669 if (TREE_CODE (*node) != FUNCTION_DECL)
671 warning (OPT_Wattributes, "%qs attribute only applies to functions",
672 IDENTIFIER_POINTER (name));
673 *no_add_attrs = true;
676 if (m68k_get_function_kind (*node) != m68k_fk_normal_function)
678 error ("multiple interrupt attributes not allowed");
679 *no_add_attrs = true;
683 && !strcmp (IDENTIFIER_POINTER (name), "interrupt_thread"))
685 error ("interrupt_thread is available only on fido");
686 *no_add_attrs = true;
693 m68k_compute_frame_layout (void)
697 enum m68k_function_kind func_kind =
698 m68k_get_function_kind (current_function_decl);
699 bool interrupt_handler = func_kind == m68k_fk_interrupt_handler;
700 bool interrupt_thread = func_kind == m68k_fk_interrupt_thread;
702 /* Only compute the frame once per function.
703 Don't cache information until reload has been completed. */
704 if (current_frame.funcdef_no == current_function_funcdef_no
708 current_frame.size = (get_frame_size () + 3) & -4;
712 /* Interrupt thread does not need to save any register. */
713 if (!interrupt_thread)
714 for (regno = 0; regno < 16; regno++)
715 if (m68k_save_reg (regno, interrupt_handler))
717 mask |= 1 << (regno - D0_REG);
720 current_frame.offset = saved * 4;
721 current_frame.reg_no = saved;
722 current_frame.reg_mask = mask;
724 current_frame.foffset = 0;
726 if (TARGET_HARD_FLOAT)
728 /* Interrupt thread does not need to save any register. */
729 if (!interrupt_thread)
730 for (regno = 16; regno < 24; regno++)
731 if (m68k_save_reg (regno, interrupt_handler))
733 mask |= 1 << (regno - FP0_REG);
736 current_frame.foffset = saved * TARGET_FP_REG_SIZE;
737 current_frame.offset += current_frame.foffset;
739 current_frame.fpu_no = saved;
740 current_frame.fpu_mask = mask;
742 /* Remember what function this frame refers to. */
743 current_frame.funcdef_no = current_function_funcdef_no;
747 m68k_initial_elimination_offset (int from, int to)
750 /* The arg pointer points 8 bytes before the start of the arguments,
751 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
752 frame pointer in most frames. */
753 argptr_offset = frame_pointer_needed ? 0 : UNITS_PER_WORD;
754 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
755 return argptr_offset;
757 m68k_compute_frame_layout ();
759 gcc_assert (to == STACK_POINTER_REGNUM);
762 case ARG_POINTER_REGNUM:
763 return current_frame.offset + current_frame.size - argptr_offset;
764 case FRAME_POINTER_REGNUM:
765 return current_frame.offset + current_frame.size;
771 /* Refer to the array `regs_ever_live' to determine which registers
772 to save; `regs_ever_live[I]' is nonzero if register number I
773 is ever used in the function. This function is responsible for
774 knowing which registers should not be saved even if used.
775 Return true if we need to save REGNO. */
778 m68k_save_reg (unsigned int regno, bool interrupt_handler)
780 if (flag_pic && regno == PIC_REG)
782 /* A function that receives a nonlocal goto must save all call-saved
784 if (current_function_has_nonlocal_label)
786 if (current_function_uses_pic_offset_table)
788 /* Reload may introduce constant pool references into a function
789 that thitherto didn't need a PIC register. Note that the test
790 above will not catch that case because we will only set
791 current_function_uses_pic_offset_table when emitting
792 the address reloads. */
793 if (current_function_uses_const_pool)
797 if (current_function_calls_eh_return)
802 unsigned int test = EH_RETURN_DATA_REGNO (i);
803 if (test == INVALID_REGNUM)
810 /* Fixed regs we never touch. */
811 if (fixed_regs[regno])
814 /* The frame pointer (if it is such) is handled specially. */
815 if (regno == FRAME_POINTER_REGNUM && frame_pointer_needed)
818 /* Interrupt handlers must also save call_used_regs
819 if they are live or when calling nested functions. */
820 if (interrupt_handler)
822 if (df_regs_ever_live_p (regno))
825 if (!current_function_is_leaf && call_used_regs[regno])
829 /* Never need to save registers that aren't touched. */
830 if (!df_regs_ever_live_p (regno))
833 /* Otherwise save everything that isn't call-clobbered. */
834 return !call_used_regs[regno];
837 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
838 the lowest memory address. COUNT is the number of registers to be
839 moved, with register REGNO + I being moved if bit I of MASK is set.
840 STORE_P specifies the direction of the move and ADJUST_STACK_P says
841 whether or not this is pre-decrement (if STORE_P) or post-increment
842 (if !STORE_P) operation. */
845 m68k_emit_movem (rtx base, HOST_WIDE_INT offset,
846 unsigned int count, unsigned int regno,
847 unsigned int mask, bool store_p, bool adjust_stack_p)
850 rtx body, addr, src, operands[2];
851 enum machine_mode mode;
853 body = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (adjust_stack_p + count));
854 mode = reg_raw_mode[regno];
859 src = plus_constant (base, (count
860 * GET_MODE_SIZE (mode)
861 * (HOST_WIDE_INT) (store_p ? -1 : 1)));
862 XVECEXP (body, 0, i++) = gen_rtx_SET (VOIDmode, base, src);
865 for (; mask != 0; mask >>= 1, regno++)
868 addr = plus_constant (base, offset);
869 operands[!store_p] = gen_frame_mem (mode, addr);
870 operands[store_p] = gen_rtx_REG (mode, regno);
871 XVECEXP (body, 0, i++)
872 = gen_rtx_SET (VOIDmode, operands[0], operands[1]);
873 offset += GET_MODE_SIZE (mode);
875 gcc_assert (i == XVECLEN (body, 0));
877 return emit_insn (body);
880 /* Make INSN a frame-related instruction. */
883 m68k_set_frame_related (rtx insn)
888 RTX_FRAME_RELATED_P (insn) = 1;
889 body = PATTERN (insn);
890 if (GET_CODE (body) == PARALLEL)
891 for (i = 0; i < XVECLEN (body, 0); i++)
892 RTX_FRAME_RELATED_P (XVECEXP (body, 0, i)) = 1;
895 /* Emit RTL for the "prologue" define_expand. */
898 m68k_expand_prologue (void)
900 HOST_WIDE_INT fsize_with_regs;
901 rtx limit, src, dest, insn;
903 m68k_compute_frame_layout ();
905 /* If the stack limit is a symbol, we can check it here,
906 before actually allocating the space. */
907 if (current_function_limit_stack
908 && GET_CODE (stack_limit_rtx) == SYMBOL_REF)
910 limit = plus_constant (stack_limit_rtx, current_frame.size + 4);
911 if (!LEGITIMATE_CONSTANT_P (limit))
913 emit_move_insn (gen_rtx_REG (Pmode, D0_REG), limit);
914 limit = gen_rtx_REG (Pmode, D0_REG);
916 emit_insn (gen_cmpsi (stack_pointer_rtx, limit));
917 emit_insn (gen_conditional_trap (gen_rtx_LTU (VOIDmode,
918 cc0_rtx, const0_rtx),
922 fsize_with_regs = current_frame.size;
925 /* ColdFire's move multiple instructions do not allow pre-decrement
926 addressing. Add the size of movem saves to the initial stack
927 allocation instead. */
928 if (current_frame.reg_no >= MIN_MOVEM_REGS)
929 fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode);
930 if (current_frame.fpu_no >= MIN_FMOVEM_REGS)
931 fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode);
934 if (frame_pointer_needed)
936 if (fsize_with_regs == 0 && TUNE_68040)
938 /* On the 68040, two separate moves are faster than link.w 0. */
939 dest = gen_frame_mem (Pmode,
940 gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
941 m68k_set_frame_related (emit_move_insn (dest, frame_pointer_rtx));
942 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx,
945 else if (fsize_with_regs < 0x8000 || TARGET_68020)
946 m68k_set_frame_related
947 (emit_insn (gen_link (frame_pointer_rtx,
948 GEN_INT (-4 - fsize_with_regs))));
951 m68k_set_frame_related
952 (emit_insn (gen_link (frame_pointer_rtx, GEN_INT (-4))));
953 m68k_set_frame_related
954 (emit_insn (gen_addsi3 (stack_pointer_rtx,
956 GEN_INT (-fsize_with_regs))));
959 else if (fsize_with_regs != 0)
960 m68k_set_frame_related
961 (emit_insn (gen_addsi3 (stack_pointer_rtx,
963 GEN_INT (-fsize_with_regs))));
965 if (current_frame.fpu_mask)
967 gcc_assert (current_frame.fpu_no >= MIN_FMOVEM_REGS);
969 m68k_set_frame_related
970 (m68k_emit_movem (stack_pointer_rtx,
971 current_frame.fpu_no * -GET_MODE_SIZE (XFmode),
972 current_frame.fpu_no, FP0_REG,
973 current_frame.fpu_mask, true, true));
978 /* If we're using moveml to save the integer registers,
979 the stack pointer will point to the bottom of the moveml
980 save area. Find the stack offset of the first FP register. */
981 if (current_frame.reg_no < MIN_MOVEM_REGS)
984 offset = current_frame.reg_no * GET_MODE_SIZE (SImode);
985 m68k_set_frame_related
986 (m68k_emit_movem (stack_pointer_rtx, offset,
987 current_frame.fpu_no, FP0_REG,
988 current_frame.fpu_mask, true, false));
992 /* If the stack limit is not a symbol, check it here.
993 This has the disadvantage that it may be too late... */
994 if (current_function_limit_stack)
996 if (REG_P (stack_limit_rtx))
998 emit_insn (gen_cmpsi (stack_pointer_rtx, stack_limit_rtx));
999 emit_insn (gen_conditional_trap (gen_rtx_LTU (VOIDmode,
1000 cc0_rtx, const0_rtx),
1003 else if (GET_CODE (stack_limit_rtx) != SYMBOL_REF)
1004 warning (0, "stack limit expression is not supported");
1007 if (current_frame.reg_no < MIN_MOVEM_REGS)
1009 /* Store each register separately in the same order moveml does. */
1012 for (i = 16; i-- > 0; )
1013 if (current_frame.reg_mask & (1 << i))
1015 src = gen_rtx_REG (SImode, D0_REG + i);
1016 dest = gen_frame_mem (SImode,
1017 gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
1018 m68k_set_frame_related (emit_insn (gen_movsi (dest, src)));
1023 if (TARGET_COLDFIRE)
1024 /* The required register save space has already been allocated.
1025 The first register should be stored at (%sp). */
1026 m68k_set_frame_related
1027 (m68k_emit_movem (stack_pointer_rtx, 0,
1028 current_frame.reg_no, D0_REG,
1029 current_frame.reg_mask, true, false));
1031 m68k_set_frame_related
1032 (m68k_emit_movem (stack_pointer_rtx,
1033 current_frame.reg_no * -GET_MODE_SIZE (SImode),
1034 current_frame.reg_no, D0_REG,
1035 current_frame.reg_mask, true, true));
1040 && current_function_uses_pic_offset_table)
1041 insn = emit_insn (gen_load_got (pic_offset_table_rtx));
1044 /* Return true if a simple (return) instruction is sufficient for this
1045 instruction (i.e. if no epilogue is needed). */
1048 m68k_use_return_insn (void)
1050 if (!reload_completed || frame_pointer_needed || get_frame_size () != 0)
1053 m68k_compute_frame_layout ();
1054 return current_frame.offset == 0;
1057 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1058 SIBCALL_P says which.
1060 The function epilogue should not depend on the current stack pointer!
1061 It should use the frame pointer only, if there is a frame pointer.
1062 This is mandatory because of alloca; we also take advantage of it to
1063 omit stack adjustments before returning. */
1066 m68k_expand_epilogue (bool sibcall_p)
1068 HOST_WIDE_INT fsize, fsize_with_regs;
1069 bool big, restore_from_sp;
1071 m68k_compute_frame_layout ();
1073 fsize = current_frame.size;
1075 restore_from_sp = false;
1077 /* FIXME : current_function_is_leaf below is too strong.
1078 What we really need to know there is if there could be pending
1079 stack adjustment needed at that point. */
1080 restore_from_sp = (!frame_pointer_needed
1081 || (!current_function_calls_alloca
1082 && current_function_is_leaf));
1084 /* fsize_with_regs is the size we need to adjust the sp when
1085 popping the frame. */
1086 fsize_with_regs = fsize;
1087 if (TARGET_COLDFIRE && restore_from_sp)
1089 /* ColdFire's move multiple instructions do not allow post-increment
1090 addressing. Add the size of movem loads to the final deallocation
1092 if (current_frame.reg_no >= MIN_MOVEM_REGS)
1093 fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode);
1094 if (current_frame.fpu_no >= MIN_FMOVEM_REGS)
1095 fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode);
1098 if (current_frame.offset + fsize >= 0x8000
1100 && (current_frame.reg_mask || current_frame.fpu_mask))
1103 && (current_frame.reg_no >= MIN_MOVEM_REGS
1104 || current_frame.fpu_no >= MIN_FMOVEM_REGS))
1106 /* ColdFire's move multiple instructions do not support the
1107 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1108 stack-based restore. */
1109 emit_move_insn (gen_rtx_REG (Pmode, A1_REG),
1110 GEN_INT (-(current_frame.offset + fsize)));
1111 emit_insn (gen_addsi3 (stack_pointer_rtx,
1112 gen_rtx_REG (Pmode, A1_REG),
1113 frame_pointer_rtx));
1114 restore_from_sp = true;
1118 emit_move_insn (gen_rtx_REG (Pmode, A1_REG), GEN_INT (-fsize));
1124 if (current_frame.reg_no < MIN_MOVEM_REGS)
1126 /* Restore each register separately in the same order moveml does. */
1128 HOST_WIDE_INT offset;
1130 offset = current_frame.offset + fsize;
1131 for (i = 0; i < 16; i++)
1132 if (current_frame.reg_mask & (1 << i))
1138 /* Generate the address -OFFSET(%fp,%a1.l). */
1139 addr = gen_rtx_REG (Pmode, A1_REG);
1140 addr = gen_rtx_PLUS (Pmode, addr, frame_pointer_rtx);
1141 addr = plus_constant (addr, -offset);
1143 else if (restore_from_sp)
1144 addr = gen_rtx_POST_INC (Pmode, stack_pointer_rtx);
1146 addr = plus_constant (frame_pointer_rtx, -offset);
1147 emit_move_insn (gen_rtx_REG (SImode, D0_REG + i),
1148 gen_frame_mem (SImode, addr));
1149 offset -= GET_MODE_SIZE (SImode);
1152 else if (current_frame.reg_mask)
1155 m68k_emit_movem (gen_rtx_PLUS (Pmode,
1156 gen_rtx_REG (Pmode, A1_REG),
1158 -(current_frame.offset + fsize),
1159 current_frame.reg_no, D0_REG,
1160 current_frame.reg_mask, false, false);
1161 else if (restore_from_sp)
1162 m68k_emit_movem (stack_pointer_rtx, 0,
1163 current_frame.reg_no, D0_REG,
1164 current_frame.reg_mask, false,
1167 m68k_emit_movem (frame_pointer_rtx,
1168 -(current_frame.offset + fsize),
1169 current_frame.reg_no, D0_REG,
1170 current_frame.reg_mask, false, false);
1173 if (current_frame.fpu_no > 0)
1176 m68k_emit_movem (gen_rtx_PLUS (Pmode,
1177 gen_rtx_REG (Pmode, A1_REG),
1179 -(current_frame.foffset + fsize),
1180 current_frame.fpu_no, FP0_REG,
1181 current_frame.fpu_mask, false, false);
1182 else if (restore_from_sp)
1184 if (TARGET_COLDFIRE)
1188 /* If we used moveml to restore the integer registers, the
1189 stack pointer will still point to the bottom of the moveml
1190 save area. Find the stack offset of the first FP
1192 if (current_frame.reg_no < MIN_MOVEM_REGS)
1195 offset = current_frame.reg_no * GET_MODE_SIZE (SImode);
1196 m68k_emit_movem (stack_pointer_rtx, offset,
1197 current_frame.fpu_no, FP0_REG,
1198 current_frame.fpu_mask, false, false);
1201 m68k_emit_movem (stack_pointer_rtx, 0,
1202 current_frame.fpu_no, FP0_REG,
1203 current_frame.fpu_mask, false, true);
1206 m68k_emit_movem (frame_pointer_rtx,
1207 -(current_frame.foffset + fsize),
1208 current_frame.fpu_no, FP0_REG,
1209 current_frame.fpu_mask, false, false);
1212 if (frame_pointer_needed)
1213 emit_insn (gen_unlink (frame_pointer_rtx));
1214 else if (fsize_with_regs)
1215 emit_insn (gen_addsi3 (stack_pointer_rtx,
1217 GEN_INT (fsize_with_regs)));
1219 if (current_function_calls_eh_return)
1220 emit_insn (gen_addsi3 (stack_pointer_rtx,
1222 EH_RETURN_STACKADJ_RTX));
1225 emit_insn (gen_rtx_RETURN (VOIDmode));
1228 /* Return true if X is a valid comparison operator for the dbcc
1231 Note it rejects floating point comparison operators.
1232 (In the future we could use Fdbcc).
1234 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1237 valid_dbcc_comparison_p_2 (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1239 switch (GET_CODE (x))
1241 case EQ: case NE: case GTU: case LTU:
1245 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1247 case GT: case LT: case GE: case LE:
1248 return ! (cc_prev_status.flags & CC_NO_OVERFLOW);
1254 /* Return nonzero if flags are currently in the 68881 flag register. */
1256 flags_in_68881 (void)
1258 /* We could add support for these in the future */
1259 return cc_status.flags & CC_IN_68881;
1262 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. We cannot use sibcalls
1263 for nested functions because we use the static chain register for
1267 m68k_ok_for_sibcall_p (tree decl ATTRIBUTE_UNUSED, tree exp)
1269 return TREE_OPERAND (exp, 2) == NULL;
1272 /* Convert X to a legitimate function call memory reference and return the
1276 m68k_legitimize_call_address (rtx x)
1278 gcc_assert (MEM_P (x));
1279 if (call_operand (XEXP (x, 0), VOIDmode))
1281 return replace_equiv_address (x, force_reg (Pmode, XEXP (x, 0)));
1284 /* Likewise for sibling calls. */
1287 m68k_legitimize_sibcall_address (rtx x)
1289 gcc_assert (MEM_P (x));
1290 if (sibcall_operand (XEXP (x, 0), VOIDmode))
1293 emit_move_insn (gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM), XEXP (x, 0));
1294 return replace_equiv_address (x, gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM));
1297 /* Output a dbCC; jCC sequence. Note we do not handle the
1298 floating point version of this sequence (Fdbcc). We also
1299 do not handle alternative conditions when CC_NO_OVERFLOW is
1300 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1301 kick those out before we get here. */
1304 output_dbcc_and_branch (rtx *operands)
1306 switch (GET_CODE (operands[3]))
1309 output_asm_insn (MOTOROLA
1310 ? "dbeq %0,%l1\n\tjbeq %l2"
1311 : "dbeq %0,%l1\n\tjeq %l2",
1316 output_asm_insn (MOTOROLA
1317 ? "dbne %0,%l1\n\tjbne %l2"
1318 : "dbne %0,%l1\n\tjne %l2",
1323 output_asm_insn (MOTOROLA
1324 ? "dbgt %0,%l1\n\tjbgt %l2"
1325 : "dbgt %0,%l1\n\tjgt %l2",
1330 output_asm_insn (MOTOROLA
1331 ? "dbhi %0,%l1\n\tjbhi %l2"
1332 : "dbhi %0,%l1\n\tjhi %l2",
1337 output_asm_insn (MOTOROLA
1338 ? "dblt %0,%l1\n\tjblt %l2"
1339 : "dblt %0,%l1\n\tjlt %l2",
1344 output_asm_insn (MOTOROLA
1345 ? "dbcs %0,%l1\n\tjbcs %l2"
1346 : "dbcs %0,%l1\n\tjcs %l2",
1351 output_asm_insn (MOTOROLA
1352 ? "dbge %0,%l1\n\tjbge %l2"
1353 : "dbge %0,%l1\n\tjge %l2",
1358 output_asm_insn (MOTOROLA
1359 ? "dbcc %0,%l1\n\tjbcc %l2"
1360 : "dbcc %0,%l1\n\tjcc %l2",
1365 output_asm_insn (MOTOROLA
1366 ? "dble %0,%l1\n\tjble %l2"
1367 : "dble %0,%l1\n\tjle %l2",
1372 output_asm_insn (MOTOROLA
1373 ? "dbls %0,%l1\n\tjbls %l2"
1374 : "dbls %0,%l1\n\tjls %l2",
1382 /* If the decrement is to be done in SImode, then we have
1383 to compensate for the fact that dbcc decrements in HImode. */
1384 switch (GET_MODE (operands[0]))
1387 output_asm_insn (MOTOROLA
1388 ? "clr%.w %0\n\tsubq%.l #1,%0\n\tjbpl %l1"
1389 : "clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1",
1402 output_scc_di (rtx op, rtx operand1, rtx operand2, rtx dest)
1405 enum rtx_code op_code = GET_CODE (op);
1407 /* This does not produce a useful cc. */
1410 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1411 below. Swap the operands and change the op if these requirements
1412 are not fulfilled. */
1413 if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG)
1417 operand1 = operand2;
1419 op_code = swap_condition (op_code);
1421 loperands[0] = operand1;
1422 if (GET_CODE (operand1) == REG)
1423 loperands[1] = gen_rtx_REG (SImode, REGNO (operand1) + 1);
1425 loperands[1] = adjust_address (operand1, SImode, 4);
1426 if (operand2 != const0_rtx)
1428 loperands[2] = operand2;
1429 if (GET_CODE (operand2) == REG)
1430 loperands[3] = gen_rtx_REG (SImode, REGNO (operand2) + 1);
1432 loperands[3] = adjust_address (operand2, SImode, 4);
1434 loperands[4] = gen_label_rtx ();
1435 if (operand2 != const0_rtx)
1437 output_asm_insn (MOTOROLA
1438 ? "cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1"
1439 : "cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1",
1444 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[0]))
1445 output_asm_insn ("tst%.l %0", loperands);
1447 output_asm_insn ("cmp%.w #0,%0", loperands);
1449 output_asm_insn (MOTOROLA ? "jbne %l4" : "jne %l4", loperands);
1451 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[1]))
1452 output_asm_insn ("tst%.l %1", loperands);
1454 output_asm_insn ("cmp%.w #0,%1", loperands);
1457 loperands[5] = dest;
1462 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1463 CODE_LABEL_NUMBER (loperands[4]));
1464 output_asm_insn ("seq %5", loperands);
1468 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1469 CODE_LABEL_NUMBER (loperands[4]));
1470 output_asm_insn ("sne %5", loperands);
1474 loperands[6] = gen_label_rtx ();
1475 output_asm_insn (MOTOROLA ? "shi %5\n\tjbra %l6" : "shi %5\n\tjra %l6",
1477 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1478 CODE_LABEL_NUMBER (loperands[4]));
1479 output_asm_insn ("sgt %5", loperands);
1480 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1481 CODE_LABEL_NUMBER (loperands[6]));
1485 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1486 CODE_LABEL_NUMBER (loperands[4]));
1487 output_asm_insn ("shi %5", loperands);
1491 loperands[6] = gen_label_rtx ();
1492 output_asm_insn (MOTOROLA ? "scs %5\n\tjbra %l6" : "scs %5\n\tjra %l6",
1494 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1495 CODE_LABEL_NUMBER (loperands[4]));
1496 output_asm_insn ("slt %5", loperands);
1497 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1498 CODE_LABEL_NUMBER (loperands[6]));
1502 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1503 CODE_LABEL_NUMBER (loperands[4]));
1504 output_asm_insn ("scs %5", loperands);
1508 loperands[6] = gen_label_rtx ();
1509 output_asm_insn (MOTOROLA ? "scc %5\n\tjbra %l6" : "scc %5\n\tjra %l6",
1511 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1512 CODE_LABEL_NUMBER (loperands[4]));
1513 output_asm_insn ("sge %5", loperands);
1514 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1515 CODE_LABEL_NUMBER (loperands[6]));
1519 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1520 CODE_LABEL_NUMBER (loperands[4]));
1521 output_asm_insn ("scc %5", loperands);
1525 loperands[6] = gen_label_rtx ();
1526 output_asm_insn (MOTOROLA ? "sls %5\n\tjbra %l6" : "sls %5\n\tjra %l6",
1528 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1529 CODE_LABEL_NUMBER (loperands[4]));
1530 output_asm_insn ("sle %5", loperands);
1531 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1532 CODE_LABEL_NUMBER (loperands[6]));
1536 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1537 CODE_LABEL_NUMBER (loperands[4]));
1538 output_asm_insn ("sls %5", loperands);
1548 output_btst (rtx *operands, rtx countop, rtx dataop, rtx insn, int signpos)
1550 operands[0] = countop;
1551 operands[1] = dataop;
1553 if (GET_CODE (countop) == CONST_INT)
1555 register int count = INTVAL (countop);
1556 /* If COUNT is bigger than size of storage unit in use,
1557 advance to the containing unit of same size. */
1558 if (count > signpos)
1560 int offset = (count & ~signpos) / 8;
1561 count = count & signpos;
1562 operands[1] = dataop = adjust_address (dataop, QImode, offset);
1564 if (count == signpos)
1565 cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N;
1567 cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N;
1569 /* These three statements used to use next_insns_test_no...
1570 but it appears that this should do the same job. */
1572 && next_insn_tests_no_inequality (insn))
1575 && next_insn_tests_no_inequality (insn))
1578 && next_insn_tests_no_inequality (insn))
1580 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1581 On some m68k variants unfortunately that's slower than btst.
1582 On 68000 and higher, that should also work for all HImode operands. */
1583 if (TUNE_CPU32 || TARGET_COLDFIRE || optimize_size)
1585 if (count == 3 && DATA_REG_P (operands[1])
1586 && next_insn_tests_no_inequality (insn))
1588 cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N | CC_NO_OVERFLOW;
1589 return "move%.w %1,%%ccr";
1591 if (count == 2 && DATA_REG_P (operands[1])
1592 && next_insn_tests_no_inequality (insn))
1594 cc_status.flags = CC_NOT_NEGATIVE | CC_INVERTED | CC_NO_OVERFLOW;
1595 return "move%.w %1,%%ccr";
1597 /* count == 1 followed by bvc/bvs and
1598 count == 0 followed by bcc/bcs are also possible, but need
1599 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1602 cc_status.flags = CC_NOT_NEGATIVE;
1604 return "btst %0,%1";
1607 /* Return true if X is a legitimate base register. STRICT_P says
1608 whether we need strict checking. */
1611 m68k_legitimate_base_reg_p (rtx x, bool strict_p)
1613 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1614 if (!strict_p && GET_CODE (x) == SUBREG)
1619 ? REGNO_OK_FOR_BASE_P (REGNO (x))
1620 : !DATA_REGNO_P (REGNO (x)) && !FP_REGNO_P (REGNO (x))));
1623 /* Return true if X is a legitimate index register. STRICT_P says
1624 whether we need strict checking. */
1627 m68k_legitimate_index_reg_p (rtx x, bool strict_p)
1629 if (!strict_p && GET_CODE (x) == SUBREG)
1634 ? REGNO_OK_FOR_INDEX_P (REGNO (x))
1635 : !FP_REGNO_P (REGNO (x))));
1638 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1639 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1640 ADDRESS if so. STRICT_P says whether we need strict checking. */
1643 m68k_decompose_index (rtx x, bool strict_p, struct m68k_address *address)
1647 /* Check for a scale factor. */
1649 if ((TARGET_68020 || TARGET_COLDFIRE)
1650 && GET_CODE (x) == MULT
1651 && GET_CODE (XEXP (x, 1)) == CONST_INT
1652 && (INTVAL (XEXP (x, 1)) == 2
1653 || INTVAL (XEXP (x, 1)) == 4
1654 || (INTVAL (XEXP (x, 1)) == 8
1655 && (TARGET_COLDFIRE_FPU || !TARGET_COLDFIRE))))
1657 scale = INTVAL (XEXP (x, 1));
1661 /* Check for a word extension. */
1662 if (!TARGET_COLDFIRE
1663 && GET_CODE (x) == SIGN_EXTEND
1664 && GET_MODE (XEXP (x, 0)) == HImode)
1667 if (m68k_legitimate_index_reg_p (x, strict_p))
1669 address->scale = scale;
1677 /* Return true if X is an illegitimate symbolic constant. */
1680 m68k_illegitimate_symbolic_constant_p (rtx x)
1684 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P)
1686 split_const (x, &base, &offset);
1687 if (GET_CODE (base) == SYMBOL_REF
1688 && !offset_within_block_p (base, INTVAL (offset)))
1694 /* Return true if X is a legitimate constant address that can reach
1695 bytes in the range [X, X + REACH). STRICT_P says whether we need
1699 m68k_legitimate_constant_address_p (rtx x, unsigned int reach, bool strict_p)
1703 if (!CONSTANT_ADDRESS_P (x))
1707 && !(strict_p && TARGET_PCREL)
1708 && symbolic_operand (x, VOIDmode))
1711 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P && reach > 1)
1713 split_const (x, &base, &offset);
1714 if (GET_CODE (base) == SYMBOL_REF
1715 && !offset_within_block_p (base, INTVAL (offset) + reach - 1))
1722 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1723 labels will become jump tables. */
1726 m68k_jump_table_ref_p (rtx x)
1728 if (GET_CODE (x) != LABEL_REF)
1732 if (!NEXT_INSN (x) && !PREV_INSN (x))
1735 x = next_nonnote_insn (x);
1736 return x && JUMP_TABLE_DATA_P (x);
1739 /* Return true if X is a legitimate address for values of mode MODE.
1740 STRICT_P says whether strict checking is needed. If the address
1741 is valid, describe its components in *ADDRESS. */
1744 m68k_decompose_address (enum machine_mode mode, rtx x,
1745 bool strict_p, struct m68k_address *address)
1749 memset (address, 0, sizeof (*address));
1751 if (mode == BLKmode)
1754 reach = GET_MODE_SIZE (mode);
1756 /* Check for (An) (mode 2). */
1757 if (m68k_legitimate_base_reg_p (x, strict_p))
1763 /* Check for -(An) and (An)+ (modes 3 and 4). */
1764 if ((GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC)
1765 && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p))
1767 address->code = GET_CODE (x);
1768 address->base = XEXP (x, 0);
1772 /* Check for (d16,An) (mode 5). */
1773 if (GET_CODE (x) == PLUS
1774 && GET_CODE (XEXP (x, 1)) == CONST_INT
1775 && IN_RANGE (INTVAL (XEXP (x, 1)), -0x8000, 0x8000 - reach)
1776 && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p))
1778 address->base = XEXP (x, 0);
1779 address->offset = XEXP (x, 1);
1783 /* Check for GOT loads. These are (bd,An,Xn) addresses if
1784 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
1787 && GET_CODE (x) == PLUS
1788 && XEXP (x, 0) == pic_offset_table_rtx
1789 && (GET_CODE (XEXP (x, 1)) == SYMBOL_REF
1790 || GET_CODE (XEXP (x, 1)) == LABEL_REF))
1792 address->base = XEXP (x, 0);
1793 address->offset = XEXP (x, 1);
1797 /* The ColdFire FPU only accepts addressing modes 2-5. */
1798 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT)
1801 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
1802 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
1803 All these modes are variations of mode 7. */
1804 if (m68k_legitimate_constant_address_p (x, reach, strict_p))
1806 address->offset = x;
1810 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
1813 ??? do_tablejump creates these addresses before placing the target
1814 label, so we have to assume that unplaced labels are jump table
1815 references. It seems unlikely that we would ever generate indexed
1816 accesses to unplaced labels in other cases. */
1817 if (GET_CODE (x) == PLUS
1818 && m68k_jump_table_ref_p (XEXP (x, 1))
1819 && m68k_decompose_index (XEXP (x, 0), strict_p, address))
1821 address->offset = XEXP (x, 1);
1825 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
1826 (bd,An,Xn.SIZE*SCALE) addresses. */
1830 /* Check for a nonzero base displacement. */
1831 if (GET_CODE (x) == PLUS
1832 && m68k_legitimate_constant_address_p (XEXP (x, 1), reach, strict_p))
1834 address->offset = XEXP (x, 1);
1838 /* Check for a suppressed index register. */
1839 if (m68k_legitimate_base_reg_p (x, strict_p))
1845 /* Check for a suppressed base register. Do not allow this case
1846 for non-symbolic offsets as it effectively gives gcc freedom
1847 to treat data registers as base registers, which can generate
1850 && symbolic_operand (address->offset, VOIDmode)
1851 && m68k_decompose_index (x, strict_p, address))
1856 /* Check for a nonzero base displacement. */
1857 if (GET_CODE (x) == PLUS
1858 && GET_CODE (XEXP (x, 1)) == CONST_INT
1859 && IN_RANGE (INTVAL (XEXP (x, 1)), -0x80, 0x80 - reach))
1861 address->offset = XEXP (x, 1);
1866 /* We now expect the sum of a base and an index. */
1867 if (GET_CODE (x) == PLUS)
1869 if (m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p)
1870 && m68k_decompose_index (XEXP (x, 1), strict_p, address))
1872 address->base = XEXP (x, 0);
1876 if (m68k_legitimate_base_reg_p (XEXP (x, 1), strict_p)
1877 && m68k_decompose_index (XEXP (x, 0), strict_p, address))
1879 address->base = XEXP (x, 1);
1886 /* Return true if X is a legitimate address for values of mode MODE.
1887 STRICT_P says whether strict checking is needed. */
1890 m68k_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
1892 struct m68k_address address;
1894 return m68k_decompose_address (mode, x, strict_p, &address);
1897 /* Return true if X is a memory, describing its address in ADDRESS if so.
1898 Apply strict checking if called during or after reload. */
1901 m68k_legitimate_mem_p (rtx x, struct m68k_address *address)
1904 && m68k_decompose_address (GET_MODE (x), XEXP (x, 0),
1905 reload_in_progress || reload_completed,
1909 /* Return true if X matches the 'Q' constraint. It must be a memory
1910 with a base address and no constant offset or index. */
1913 m68k_matches_q_p (rtx x)
1915 struct m68k_address address;
1917 return (m68k_legitimate_mem_p (x, &address)
1918 && address.code == UNKNOWN
1924 /* Return true if X matches the 'U' constraint. It must be a base address
1925 with a constant offset and no index. */
1928 m68k_matches_u_p (rtx x)
1930 struct m68k_address address;
1932 return (m68k_legitimate_mem_p (x, &address)
1933 && address.code == UNKNOWN
1939 /* Legitimize PIC addresses. If the address is already
1940 position-independent, we return ORIG. Newly generated
1941 position-independent addresses go to REG. If we need more
1942 than one register, we lose.
1944 An address is legitimized by making an indirect reference
1945 through the Global Offset Table with the name of the symbol
1948 The assembler and linker are responsible for placing the
1949 address of the symbol in the GOT. The function prologue
1950 is responsible for initializing a5 to the starting address
1953 The assembler is also responsible for translating a symbol name
1954 into a constant displacement from the start of the GOT.
1956 A quick example may make things a little clearer:
1958 When not generating PIC code to store the value 12345 into _foo
1959 we would generate the following code:
1963 When generating PIC two transformations are made. First, the compiler
1964 loads the address of foo into a register. So the first transformation makes:
1969 The code in movsi will intercept the lea instruction and call this
1970 routine which will transform the instructions into:
1972 movel a5@(_foo:w), a0
1976 That (in a nutshell) is how *all* symbol and label references are
1980 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
1985 /* First handle a simple SYMBOL_REF or LABEL_REF */
1986 if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
1990 pic_ref = gen_rtx_MEM (Pmode,
1991 gen_rtx_PLUS (Pmode,
1992 pic_offset_table_rtx, orig));
1993 current_function_uses_pic_offset_table = 1;
1994 MEM_READONLY_P (pic_ref) = 1;
1995 emit_move_insn (reg, pic_ref);
1998 else if (GET_CODE (orig) == CONST)
2002 /* Make sure this has not already been legitimized. */
2003 if (GET_CODE (XEXP (orig, 0)) == PLUS
2004 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2009 /* legitimize both operands of the PLUS */
2010 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
2012 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2013 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2014 base == reg ? 0 : reg);
2016 if (GET_CODE (orig) == CONST_INT)
2017 return plus_constant (base, INTVAL (orig));
2018 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
2019 /* Likewise, should we set special REG_NOTEs here? */
2025 typedef enum { MOVL, SWAP, NEGW, NOTW, NOTB, MOVQ, MVS, MVZ } CONST_METHOD;
2027 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2029 /* Return the type of move that should be used for integer I. */
2032 const_method (HOST_WIDE_INT i)
2039 /* The ColdFire doesn't have byte or word operations. */
2040 /* FIXME: This may not be useful for the m68060 either. */
2041 if (!TARGET_COLDFIRE)
2043 /* if -256 < N < 256 but N is not in range for a moveq
2044 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2045 if (USE_MOVQ (i ^ 0xff))
2047 /* Likewise, try with not.w */
2048 if (USE_MOVQ (i ^ 0xffff))
2050 /* This is the only value where neg.w is useful */
2055 /* Try also with swap. */
2057 if (USE_MOVQ ((u >> 16) | (u << 16)))
2062 /* Try using MVZ/MVS with an immediate value to load constants. */
2063 if (i >= 0 && i <= 65535)
2065 if (i >= -32768 && i <= 32767)
2069 /* Otherwise, use move.l */
2073 /* Return the cost of moving constant I into a data register. */
2076 const_int_cost (HOST_WIDE_INT i)
2078 switch (const_method (i))
2081 /* Constants between -128 and 127 are cheap due to moveq. */
2089 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2099 m68k_rtx_costs (rtx x, int code, int outer_code, int *total)
2104 /* Constant zero is super cheap due to clr instruction. */
2105 if (x == const0_rtx)
2108 *total = const_int_cost (INTVAL (x));
2118 /* Make 0.0 cheaper than other floating constants to
2119 encourage creating tstsf and tstdf insns. */
2120 if (outer_code == COMPARE
2121 && (x == CONST0_RTX (SFmode) || x == CONST0_RTX (DFmode)))
2127 /* These are vaguely right for a 68020. */
2128 /* The costs for long multiply have been adjusted to work properly
2129 in synth_mult on the 68020, relative to an average of the time
2130 for add and the time for shift, taking away a little more because
2131 sometimes move insns are needed. */
2132 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2138 : TARGET_COLDFIRE ? 3 : 13)
2143 : TUNE_68000_10 || TUNE_CFV2 ? 5 \
2144 : TARGET_COLDFIRE ? 2 : 8)
2147 (TARGET_CF_HWDIV ? 11 \
2148 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2151 /* An lea costs about three times as much as a simple add. */
2152 if (GET_MODE (x) == SImode
2153 && GET_CODE (XEXP (x, 1)) == REG
2154 && GET_CODE (XEXP (x, 0)) == MULT
2155 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
2156 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2157 && (INTVAL (XEXP (XEXP (x, 0), 1)) == 2
2158 || INTVAL (XEXP (XEXP (x, 0), 1)) == 4
2159 || INTVAL (XEXP (XEXP (x, 0), 1)) == 8))
2161 /* lea an@(dx:l:i),am */
2162 *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 2 : 3);
2172 *total = COSTS_N_INSNS(1);
2177 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2179 if (INTVAL (XEXP (x, 1)) < 16)
2180 *total = COSTS_N_INSNS (2) + INTVAL (XEXP (x, 1)) / 2;
2182 /* We're using clrw + swap for these cases. */
2183 *total = COSTS_N_INSNS (4) + (INTVAL (XEXP (x, 1)) - 16) / 2;
2186 *total = COSTS_N_INSNS (10); /* Worst case. */
2189 /* A shift by a big integer takes an extra instruction. */
2190 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2191 && (INTVAL (XEXP (x, 1)) == 16))
2193 *total = COSTS_N_INSNS (2); /* clrw;swap */
2196 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2197 && !(INTVAL (XEXP (x, 1)) > 0
2198 && INTVAL (XEXP (x, 1)) <= 8))
2200 *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 1 : 3); /* lsr #i,dn */
2206 if ((GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
2207 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
2208 && GET_MODE (x) == SImode)
2209 *total = COSTS_N_INSNS (MULW_COST);
2210 else if (GET_MODE (x) == QImode || GET_MODE (x) == HImode)
2211 *total = COSTS_N_INSNS (MULW_COST);
2213 *total = COSTS_N_INSNS (MULL_COST);
2220 if (GET_MODE (x) == QImode || GET_MODE (x) == HImode)
2221 *total = COSTS_N_INSNS (DIVW_COST); /* div.w */
2222 else if (TARGET_CF_HWDIV)
2223 *total = COSTS_N_INSNS (18);
2225 *total = COSTS_N_INSNS (43); /* div.l */
2233 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2237 output_move_const_into_data_reg (rtx *operands)
2241 i = INTVAL (operands[1]);
2242 switch (const_method (i))
2245 return "mvzw %1,%0";
2247 return "mvsw %1,%0";
2249 return "moveq %1,%0";
2252 operands[1] = GEN_INT (i ^ 0xff);
2253 return "moveq %1,%0\n\tnot%.b %0";
2256 operands[1] = GEN_INT (i ^ 0xffff);
2257 return "moveq %1,%0\n\tnot%.w %0";
2260 return "moveq #-128,%0\n\tneg%.w %0";
2265 operands[1] = GEN_INT ((u << 16) | (u >> 16));
2266 return "moveq %1,%0\n\tswap %0";
2269 return "move%.l %1,%0";
2275 /* Return true if I can be handled by ISA B's mov3q instruction. */
2278 valid_mov3q_const (HOST_WIDE_INT i)
2280 return TARGET_ISAB && (i == -1 || IN_RANGE (i, 1, 7));
2283 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
2284 I is the value of OPERANDS[1]. */
2287 output_move_simode_const (rtx *operands)
2293 src = INTVAL (operands[1]);
2295 && (DATA_REG_P (dest) || MEM_P (dest))
2296 /* clr insns on 68000 read before writing. */
2297 && ((TARGET_68010 || TARGET_COLDFIRE)
2298 || !(MEM_P (dest) && MEM_VOLATILE_P (dest))))
2300 else if (GET_MODE (dest) == SImode && valid_mov3q_const (src))
2301 return "mov3q%.l %1,%0";
2302 else if (src == 0 && ADDRESS_REG_P (dest))
2303 return "sub%.l %0,%0";
2304 else if (DATA_REG_P (dest))
2305 return output_move_const_into_data_reg (operands);
2306 else if (ADDRESS_REG_P (dest) && IN_RANGE (src, -0x8000, 0x7fff))
2308 if (valid_mov3q_const (src))
2309 return "mov3q%.l %1,%0";
2310 return "move%.w %1,%0";
2312 else if (MEM_P (dest)
2313 && GET_CODE (XEXP (dest, 0)) == PRE_DEC
2314 && REGNO (XEXP (XEXP (dest, 0), 0)) == STACK_POINTER_REGNUM
2315 && IN_RANGE (src, -0x8000, 0x7fff))
2317 if (valid_mov3q_const (src))
2318 return "mov3q%.l %1,%-";
2321 return "move%.l %1,%0";
2325 output_move_simode (rtx *operands)
2327 if (GET_CODE (operands[1]) == CONST_INT)
2328 return output_move_simode_const (operands);
2329 else if ((GET_CODE (operands[1]) == SYMBOL_REF
2330 || GET_CODE (operands[1]) == CONST)
2331 && push_operand (operands[0], SImode))
2333 else if ((GET_CODE (operands[1]) == SYMBOL_REF
2334 || GET_CODE (operands[1]) == CONST)
2335 && ADDRESS_REG_P (operands[0]))
2336 return "lea %a1,%0";
2337 return "move%.l %1,%0";
2341 output_move_himode (rtx *operands)
2343 if (GET_CODE (operands[1]) == CONST_INT)
2345 if (operands[1] == const0_rtx
2346 && (DATA_REG_P (operands[0])
2347 || GET_CODE (operands[0]) == MEM)
2348 /* clr insns on 68000 read before writing. */
2349 && ((TARGET_68010 || TARGET_COLDFIRE)
2350 || !(GET_CODE (operands[0]) == MEM
2351 && MEM_VOLATILE_P (operands[0]))))
2353 else if (operands[1] == const0_rtx
2354 && ADDRESS_REG_P (operands[0]))
2355 return "sub%.l %0,%0";
2356 else if (DATA_REG_P (operands[0])
2357 && INTVAL (operands[1]) < 128
2358 && INTVAL (operands[1]) >= -128)
2359 return "moveq %1,%0";
2360 else if (INTVAL (operands[1]) < 0x8000
2361 && INTVAL (operands[1]) >= -0x8000)
2362 return "move%.w %1,%0";
2364 else if (CONSTANT_P (operands[1]))
2365 return "move%.l %1,%0";
2366 /* Recognize the insn before a tablejump, one that refers
2367 to a table of offsets. Such an insn will need to refer
2368 to a label on the insn. So output one. Use the label-number
2369 of the table of offsets to generate this label. This code,
2370 and similar code below, assumes that there will be at most one
2371 reference to each table. */
2372 if (GET_CODE (operands[1]) == MEM
2373 && GET_CODE (XEXP (operands[1], 0)) == PLUS
2374 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF
2375 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS)
2377 rtx labelref = XEXP (XEXP (operands[1], 0), 1);
2379 asm_fprintf (asm_out_file, "\t.set %LLI%d,.+2\n",
2380 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
2382 (*targetm.asm_out.internal_label) (asm_out_file, "LI",
2383 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
2385 return "move%.w %1,%0";
2389 output_move_qimode (rtx *operands)
2391 /* 68k family always modifies the stack pointer by at least 2, even for
2392 byte pushes. The 5200 (ColdFire) does not do this. */
2394 /* This case is generated by pushqi1 pattern now. */
2395 gcc_assert (!(GET_CODE (operands[0]) == MEM
2396 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
2397 && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx
2398 && ! ADDRESS_REG_P (operands[1])
2399 && ! TARGET_COLDFIRE));
2401 /* clr and st insns on 68000 read before writing. */
2402 if (!ADDRESS_REG_P (operands[0])
2403 && ((TARGET_68010 || TARGET_COLDFIRE)
2404 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
2406 if (operands[1] == const0_rtx)
2408 if ((!TARGET_COLDFIRE || DATA_REG_P (operands[0]))
2409 && GET_CODE (operands[1]) == CONST_INT
2410 && (INTVAL (operands[1]) & 255) == 255)
2416 if (GET_CODE (operands[1]) == CONST_INT
2417 && DATA_REG_P (operands[0])
2418 && INTVAL (operands[1]) < 128
2419 && INTVAL (operands[1]) >= -128)
2420 return "moveq %1,%0";
2421 if (operands[1] == const0_rtx && ADDRESS_REG_P (operands[0]))
2422 return "sub%.l %0,%0";
2423 if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
2424 return "move%.l %1,%0";
2425 /* 68k family (including the 5200 ColdFire) does not support byte moves to
2426 from address registers. */
2427 if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
2428 return "move%.w %1,%0";
2429 return "move%.b %1,%0";
2433 output_move_stricthi (rtx *operands)
2435 if (operands[1] == const0_rtx
2436 /* clr insns on 68000 read before writing. */
2437 && ((TARGET_68010 || TARGET_COLDFIRE)
2438 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
2440 return "move%.w %1,%0";
2444 output_move_strictqi (rtx *operands)
2446 if (operands[1] == const0_rtx
2447 /* clr insns on 68000 read before writing. */
2448 && ((TARGET_68010 || TARGET_COLDFIRE)
2449 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
2451 return "move%.b %1,%0";
2454 /* Return the best assembler insn template
2455 for moving operands[1] into operands[0] as a fullword. */
2458 singlemove_string (rtx *operands)
2460 if (GET_CODE (operands[1]) == CONST_INT)
2461 return output_move_simode_const (operands);
2462 return "move%.l %1,%0";
2466 /* Output assembler code to perform a doubleword move insn
2467 with operands OPERANDS. */
2470 output_move_double (rtx *operands)
2474 REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP
2479 rtx addreg0 = 0, addreg1 = 0;
2480 int dest_overlapped_low = 0;
2481 int size = GET_MODE_SIZE (GET_MODE (operands[0]));
2486 /* First classify both operands. */
2488 if (REG_P (operands[0]))
2490 else if (offsettable_memref_p (operands[0]))
2492 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2494 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2496 else if (GET_CODE (operands[0]) == MEM)
2501 if (REG_P (operands[1]))
2503 else if (CONSTANT_P (operands[1]))
2505 else if (offsettable_memref_p (operands[1]))
2507 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
2509 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2511 else if (GET_CODE (operands[1]) == MEM)
2516 /* Check for the cases that the operand constraints are not supposed
2517 to allow to happen. Generating code for these cases is
2519 gcc_assert (optype0 != RNDOP && optype1 != RNDOP);
2521 /* If one operand is decrementing and one is incrementing
2522 decrement the former register explicitly
2523 and change that operand into ordinary indexing. */
2525 if (optype0 == PUSHOP && optype1 == POPOP)
2527 operands[0] = XEXP (XEXP (operands[0], 0), 0);
2529 output_asm_insn ("sub%.l #12,%0", operands);
2531 output_asm_insn ("subq%.l #8,%0", operands);
2532 if (GET_MODE (operands[1]) == XFmode)
2533 operands[0] = gen_rtx_MEM (XFmode, operands[0]);
2534 else if (GET_MODE (operands[0]) == DFmode)
2535 operands[0] = gen_rtx_MEM (DFmode, operands[0]);
2537 operands[0] = gen_rtx_MEM (DImode, operands[0]);
2540 if (optype0 == POPOP && optype1 == PUSHOP)
2542 operands[1] = XEXP (XEXP (operands[1], 0), 0);
2544 output_asm_insn ("sub%.l #12,%1", operands);
2546 output_asm_insn ("subq%.l #8,%1", operands);
2547 if (GET_MODE (operands[1]) == XFmode)
2548 operands[1] = gen_rtx_MEM (XFmode, operands[1]);
2549 else if (GET_MODE (operands[1]) == DFmode)
2550 operands[1] = gen_rtx_MEM (DFmode, operands[1]);
2552 operands[1] = gen_rtx_MEM (DImode, operands[1]);
2556 /* If an operand is an unoffsettable memory ref, find a register
2557 we can increment temporarily to make it refer to the second word. */
2559 if (optype0 == MEMOP)
2560 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2562 if (optype1 == MEMOP)
2563 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2565 /* Ok, we can do one word at a time.
2566 Normally we do the low-numbered word first,
2567 but if either operand is autodecrementing then we
2568 do the high-numbered word first.
2570 In either case, set up in LATEHALF the operands to use
2571 for the high-numbered word and in some cases alter the
2572 operands in OPERANDS to be suitable for the low-numbered word. */
2576 if (optype0 == REGOP)
2578 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2);
2579 middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2581 else if (optype0 == OFFSOP)
2583 middlehalf[0] = adjust_address (operands[0], SImode, 4);
2584 latehalf[0] = adjust_address (operands[0], SImode, size - 4);
2588 middlehalf[0] = operands[0];
2589 latehalf[0] = operands[0];
2592 if (optype1 == REGOP)
2594 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
2595 middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2597 else if (optype1 == OFFSOP)
2599 middlehalf[1] = adjust_address (operands[1], SImode, 4);
2600 latehalf[1] = adjust_address (operands[1], SImode, size - 4);
2602 else if (optype1 == CNSTOP)
2604 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2609 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
2610 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
2611 operands[1] = GEN_INT (l[0]);
2612 middlehalf[1] = GEN_INT (l[1]);
2613 latehalf[1] = GEN_INT (l[2]);
2617 /* No non-CONST_DOUBLE constant should ever appear
2619 gcc_assert (!CONSTANT_P (operands[1]));
2624 middlehalf[1] = operands[1];
2625 latehalf[1] = operands[1];
2629 /* size is not 12: */
2631 if (optype0 == REGOP)
2632 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2633 else if (optype0 == OFFSOP)
2634 latehalf[0] = adjust_address (operands[0], SImode, size - 4);
2636 latehalf[0] = operands[0];
2638 if (optype1 == REGOP)
2639 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2640 else if (optype1 == OFFSOP)
2641 latehalf[1] = adjust_address (operands[1], SImode, size - 4);
2642 else if (optype1 == CNSTOP)
2643 split_double (operands[1], &operands[1], &latehalf[1]);
2645 latehalf[1] = operands[1];
2648 /* If insn is effectively movd N(sp),-(sp) then we will do the
2649 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2650 for the low word as well, to compensate for the first decrement of sp. */
2651 if (optype0 == PUSHOP
2652 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
2653 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
2654 operands[1] = middlehalf[1] = latehalf[1];
2656 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2657 if the upper part of reg N does not appear in the MEM, arrange to
2658 emit the move late-half first. Otherwise, compute the MEM address
2659 into the upper part of N and use that as a pointer to the memory
2661 if (optype0 == REGOP
2662 && (optype1 == OFFSOP || optype1 == MEMOP))
2664 rtx testlow = gen_rtx_REG (SImode, REGNO (operands[0]));
2666 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
2667 && reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
2669 /* If both halves of dest are used in the src memory address,
2670 compute the address into latehalf of dest.
2671 Note that this can't happen if the dest is two data regs. */
2673 xops[0] = latehalf[0];
2674 xops[1] = XEXP (operands[1], 0);
2675 output_asm_insn ("lea %a1,%0", xops);
2676 if (GET_MODE (operands[1]) == XFmode )
2678 operands[1] = gen_rtx_MEM (XFmode, latehalf[0]);
2679 middlehalf[1] = adjust_address (operands[1], DImode, size - 8);
2680 latehalf[1] = adjust_address (operands[1], DImode, size - 4);
2684 operands[1] = gen_rtx_MEM (DImode, latehalf[0]);
2685 latehalf[1] = adjust_address (operands[1], DImode, size - 4);
2689 && reg_overlap_mentioned_p (middlehalf[0],
2690 XEXP (operands[1], 0)))
2692 /* Check for two regs used by both source and dest.
2693 Note that this can't happen if the dest is all data regs.
2694 It can happen if the dest is d6, d7, a0.
2695 But in that case, latehalf is an addr reg, so
2696 the code at compadr does ok. */
2698 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
2699 || reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
2702 /* JRV says this can't happen: */
2703 gcc_assert (!addreg0 && !addreg1);
2705 /* Only the middle reg conflicts; simply put it last. */
2706 output_asm_insn (singlemove_string (operands), operands);
2707 output_asm_insn (singlemove_string (latehalf), latehalf);
2708 output_asm_insn (singlemove_string (middlehalf), middlehalf);
2711 else if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)))
2712 /* If the low half of dest is mentioned in the source memory
2713 address, the arrange to emit the move late half first. */
2714 dest_overlapped_low = 1;
2717 /* If one or both operands autodecrementing,
2718 do the two words, high-numbered first. */
2720 /* Likewise, the first move would clobber the source of the second one,
2721 do them in the other order. This happens only for registers;
2722 such overlap can't happen in memory unless the user explicitly
2723 sets it up, and that is an undefined circumstance. */
2725 if (optype0 == PUSHOP || optype1 == PUSHOP
2726 || (optype0 == REGOP && optype1 == REGOP
2727 && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1]))
2728 || REGNO (operands[0]) == REGNO (latehalf[1])))
2729 || dest_overlapped_low)
2731 /* Make any unoffsettable addresses point at high-numbered word. */
2735 output_asm_insn ("addq%.l #8,%0", &addreg0);
2737 output_asm_insn ("addq%.l #4,%0", &addreg0);
2742 output_asm_insn ("addq%.l #8,%0", &addreg1);
2744 output_asm_insn ("addq%.l #4,%0", &addreg1);
2748 output_asm_insn (singlemove_string (latehalf), latehalf);
2750 /* Undo the adds we just did. */
2752 output_asm_insn ("subq%.l #4,%0", &addreg0);
2754 output_asm_insn ("subq%.l #4,%0", &addreg1);
2758 output_asm_insn (singlemove_string (middlehalf), middlehalf);
2760 output_asm_insn ("subq%.l #4,%0", &addreg0);
2762 output_asm_insn ("subq%.l #4,%0", &addreg1);
2765 /* Do low-numbered word. */
2766 return singlemove_string (operands);
2769 /* Normal case: do the two words, low-numbered first. */
2771 output_asm_insn (singlemove_string (operands), operands);
2773 /* Do the middle one of the three words for long double */
2777 output_asm_insn ("addq%.l #4,%0", &addreg0);
2779 output_asm_insn ("addq%.l #4,%0", &addreg1);
2781 output_asm_insn (singlemove_string (middlehalf), middlehalf);
2784 /* Make any unoffsettable addresses point at high-numbered word. */
2786 output_asm_insn ("addq%.l #4,%0", &addreg0);
2788 output_asm_insn ("addq%.l #4,%0", &addreg1);
2791 output_asm_insn (singlemove_string (latehalf), latehalf);
2793 /* Undo the adds we just did. */
2797 output_asm_insn ("subq%.l #8,%0", &addreg0);
2799 output_asm_insn ("subq%.l #4,%0", &addreg0);
2804 output_asm_insn ("subq%.l #8,%0", &addreg1);
2806 output_asm_insn ("subq%.l #4,%0", &addreg1);
2813 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
2814 new rtx with the correct mode. */
2817 force_mode (enum machine_mode mode, rtx orig)
2819 if (mode == GET_MODE (orig))
2822 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
2825 return gen_rtx_REG (mode, REGNO (orig));
2829 fp_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2831 return reg_renumber && FP_REG_P (op);
2834 /* Emit insns to move operands[1] into operands[0].
2836 Return 1 if we have written out everything that needs to be done to
2837 do the move. Otherwise, return 0 and the caller will emit the move
2840 Note SCRATCH_REG may not be in the proper mode depending on how it
2841 will be used. This routine is responsible for creating a new copy
2842 of SCRATCH_REG in the proper mode. */
2845 emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
2847 register rtx operand0 = operands[0];
2848 register rtx operand1 = operands[1];
2852 && reload_in_progress && GET_CODE (operand0) == REG
2853 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
2854 operand0 = reg_equiv_mem[REGNO (operand0)];
2855 else if (scratch_reg
2856 && reload_in_progress && GET_CODE (operand0) == SUBREG
2857 && GET_CODE (SUBREG_REG (operand0)) == REG
2858 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
2860 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2861 the code which tracks sets/uses for delete_output_reload. */
2862 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
2863 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
2864 SUBREG_BYTE (operand0));
2865 operand0 = alter_subreg (&temp);
2869 && reload_in_progress && GET_CODE (operand1) == REG
2870 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
2871 operand1 = reg_equiv_mem[REGNO (operand1)];
2872 else if (scratch_reg
2873 && reload_in_progress && GET_CODE (operand1) == SUBREG
2874 && GET_CODE (SUBREG_REG (operand1)) == REG
2875 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
2877 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2878 the code which tracks sets/uses for delete_output_reload. */
2879 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
2880 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
2881 SUBREG_BYTE (operand1));
2882 operand1 = alter_subreg (&temp);
2885 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
2886 && ((tem = find_replacement (&XEXP (operand0, 0)))
2887 != XEXP (operand0, 0)))
2888 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
2889 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
2890 && ((tem = find_replacement (&XEXP (operand1, 0)))
2891 != XEXP (operand1, 0)))
2892 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
2894 /* Handle secondary reloads for loads/stores of FP registers where
2895 the address is symbolic by using the scratch register */
2896 if (fp_reg_operand (operand0, mode)
2897 && ((GET_CODE (operand1) == MEM
2898 && ! memory_address_p (DFmode, XEXP (operand1, 0)))
2899 || ((GET_CODE (operand1) == SUBREG
2900 && GET_CODE (XEXP (operand1, 0)) == MEM
2901 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
2904 if (GET_CODE (operand1) == SUBREG)
2905 operand1 = XEXP (operand1, 0);
2907 /* SCRATCH_REG will hold an address. We want
2908 it in SImode regardless of what mode it was originally given
2910 scratch_reg = force_mode (SImode, scratch_reg);
2912 /* D might not fit in 14 bits either; for such cases load D into
2914 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
2916 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
2917 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
2919 XEXP (XEXP (operand1, 0), 0),
2923 emit_move_insn (scratch_reg, XEXP (operand1, 0));
2924 emit_insn (gen_rtx_SET (VOIDmode, operand0,
2925 gen_rtx_MEM (mode, scratch_reg)));
2928 else if (fp_reg_operand (operand1, mode)
2929 && ((GET_CODE (operand0) == MEM
2930 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
2931 || ((GET_CODE (operand0) == SUBREG)
2932 && GET_CODE (XEXP (operand0, 0)) == MEM
2933 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
2936 if (GET_CODE (operand0) == SUBREG)
2937 operand0 = XEXP (operand0, 0);
2939 /* SCRATCH_REG will hold an address and maybe the actual data. We want
2940 it in SIMODE regardless of what mode it was originally given
2942 scratch_reg = force_mode (SImode, scratch_reg);
2944 /* D might not fit in 14 bits either; for such cases load D into
2946 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
2948 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
2949 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
2952 XEXP (XEXP (operand0, 0),
2957 emit_move_insn (scratch_reg, XEXP (operand0, 0));
2958 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
2962 /* Handle secondary reloads for loads of FP registers from constant
2963 expressions by forcing the constant into memory.
2965 use scratch_reg to hold the address of the memory location.
2967 The proper fix is to change PREFERRED_RELOAD_CLASS to return
2968 NO_REGS when presented with a const_int and an register class
2969 containing only FP registers. Doing so unfortunately creates
2970 more problems than it solves. Fix this for 2.5. */
2971 else if (fp_reg_operand (operand0, mode)
2972 && CONSTANT_P (operand1)
2977 /* SCRATCH_REG will hold an address and maybe the actual data. We want
2978 it in SIMODE regardless of what mode it was originally given
2980 scratch_reg = force_mode (SImode, scratch_reg);
2982 /* Force the constant into memory and put the address of the
2983 memory location into scratch_reg. */
2984 xoperands[0] = scratch_reg;
2985 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
2986 emit_insn (gen_rtx_SET (mode, scratch_reg, xoperands[1]));
2988 /* Now load the destination register. */
2989 emit_insn (gen_rtx_SET (mode, operand0,
2990 gen_rtx_MEM (mode, scratch_reg)));
2994 /* Now have insn-emit do whatever it normally does. */
2998 /* Split one or more DImode RTL references into pairs of SImode
2999 references. The RTL can be REG, offsettable MEM, integer constant, or
3000 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3001 split and "num" is its length. lo_half and hi_half are output arrays
3002 that parallel "operands". */
3005 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
3009 rtx op = operands[num];
3011 /* simplify_subreg refuses to split volatile memory addresses,
3012 but we still have to handle it. */
3013 if (GET_CODE (op) == MEM)
3015 lo_half[num] = adjust_address (op, SImode, 4);
3016 hi_half[num] = adjust_address (op, SImode, 0);
3020 lo_half[num] = simplify_gen_subreg (SImode, op,
3021 GET_MODE (op) == VOIDmode
3022 ? DImode : GET_MODE (op), 4);
3023 hi_half[num] = simplify_gen_subreg (SImode, op,
3024 GET_MODE (op) == VOIDmode
3025 ? DImode : GET_MODE (op), 0);
3030 /* Split X into a base and a constant offset, storing them in *BASE
3031 and *OFFSET respectively. */
3034 m68k_split_offset (rtx x, rtx *base, HOST_WIDE_INT *offset)
3037 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
3039 *offset += INTVAL (XEXP (x, 1));
3045 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3046 instruction. STORE_P says whether the move is a load or store.
3048 If the instruction uses post-increment or pre-decrement addressing,
3049 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3050 adjustment. This adjustment will be made by the first element of
3051 PARALLEL, with the loads or stores starting at element 1. If the
3052 instruction does not use post-increment or pre-decrement addressing,
3053 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3054 start at element 0. */
3057 m68k_movem_pattern_p (rtx pattern, rtx automod_base,
3058 HOST_WIDE_INT automod_offset, bool store_p)
3060 rtx base, mem_base, set, mem, reg, last_reg;
3061 HOST_WIDE_INT offset, mem_offset;
3063 enum reg_class rclass;
3065 len = XVECLEN (pattern, 0);
3066 first = (automod_base != NULL);
3070 /* Stores must be pre-decrement and loads must be post-increment. */
3071 if (store_p != (automod_offset < 0))
3074 /* Work out the base and offset for lowest memory location. */
3075 base = automod_base;
3076 offset = (automod_offset < 0 ? automod_offset : 0);
3080 /* Allow any valid base and offset in the first access. */
3087 for (i = first; i < len; i++)
3089 /* We need a plain SET. */
3090 set = XVECEXP (pattern, 0, i);
3091 if (GET_CODE (set) != SET)
3094 /* Check that we have a memory location... */
3095 mem = XEXP (set, !store_p);
3096 if (!MEM_P (mem) || !memory_operand (mem, VOIDmode))
3099 /* ...with the right address. */
3102 m68k_split_offset (XEXP (mem, 0), &base, &offset);
3103 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3104 There are no mode restrictions for 680x0 besides the
3105 automodification rules enforced above. */
3107 && !m68k_legitimate_base_reg_p (base, reload_completed))
3112 m68k_split_offset (XEXP (mem, 0), &mem_base, &mem_offset);
3113 if (!rtx_equal_p (base, mem_base) || offset != mem_offset)
3117 /* Check that we have a register of the required mode and class. */
3118 reg = XEXP (set, store_p);
3120 || !HARD_REGISTER_P (reg)
3121 || GET_MODE (reg) != reg_raw_mode[REGNO (reg)])
3126 /* The register must belong to RCLASS and have a higher number
3127 than the register in the previous SET. */
3128 if (!TEST_HARD_REG_BIT (reg_class_contents[rclass], REGNO (reg))
3129 || REGNO (last_reg) >= REGNO (reg))
3134 /* Work out which register class we need. */
3135 if (INT_REGNO_P (REGNO (reg)))
3136 rclass = GENERAL_REGS;
3137 else if (FP_REGNO_P (REGNO (reg)))
3144 offset += GET_MODE_SIZE (GET_MODE (reg));
3147 /* If we have an automodification, check whether the final offset is OK. */
3148 if (automod_base && offset != (automod_offset < 0 ? 0 : automod_offset))
3151 /* Reject unprofitable cases. */
3152 if (len < first + (rclass == FP_REGS ? MIN_FMOVEM_REGS : MIN_MOVEM_REGS))
3158 /* Return the assembly code template for a movem or fmovem instruction
3159 whose pattern is given by PATTERN. Store the template's operands
3162 If the instruction uses post-increment or pre-decrement addressing,
3163 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3164 is true if this is a store instruction. */
3167 m68k_output_movem (rtx *operands, rtx pattern,
3168 HOST_WIDE_INT automod_offset, bool store_p)
3173 gcc_assert (GET_CODE (pattern) == PARALLEL);
3175 first = (automod_offset != 0);
3176 for (i = first; i < XVECLEN (pattern, 0); i++)
3178 /* When using movem with pre-decrement addressing, register X + D0_REG
3179 is controlled by bit 15 - X. For all other addressing modes,
3180 register X + D0_REG is controlled by bit X. Confusingly, the
3181 register mask for fmovem is in the opposite order to that for
3185 gcc_assert (MEM_P (XEXP (XVECEXP (pattern, 0, i), !store_p)));
3186 gcc_assert (REG_P (XEXP (XVECEXP (pattern, 0, i), store_p)));
3187 regno = REGNO (XEXP (XVECEXP (pattern, 0, i), store_p));
3188 if (automod_offset < 0)
3190 if (FP_REGNO_P (regno))
3191 mask |= 1 << (regno - FP0_REG);
3193 mask |= 1 << (15 - (regno - D0_REG));
3197 if (FP_REGNO_P (regno))
3198 mask |= 1 << (7 - (regno - FP0_REG));
3200 mask |= 1 << (regno - D0_REG);
3205 if (automod_offset == 0)
3206 operands[0] = XEXP (XEXP (XVECEXP (pattern, 0, first), !store_p), 0);
3207 else if (automod_offset < 0)
3208 operands[0] = gen_rtx_PRE_DEC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0)));
3210 operands[0] = gen_rtx_POST_INC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0)));
3211 operands[1] = GEN_INT (mask);
3212 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern, 0, first), store_p))))
3215 return MOTOROLA ? "fmovm %1,%a0" : "fmovem %1,%a0";
3217 return MOTOROLA ? "fmovm %a0,%1" : "fmovem %a0,%1";
3222 return MOTOROLA ? "movm.l %1,%a0" : "moveml %1,%a0";
3224 return MOTOROLA ? "movm.l %a0,%1" : "moveml %a0,%1";
3228 /* Return a REG that occurs in ADDR with coefficient 1.
3229 ADDR can be effectively incremented by incrementing REG. */
3232 find_addr_reg (rtx addr)
3234 while (GET_CODE (addr) == PLUS)
3236 if (GET_CODE (XEXP (addr, 0)) == REG)
3237 addr = XEXP (addr, 0);
3238 else if (GET_CODE (XEXP (addr, 1)) == REG)
3239 addr = XEXP (addr, 1);
3240 else if (CONSTANT_P (XEXP (addr, 0)))
3241 addr = XEXP (addr, 1);
3242 else if (CONSTANT_P (XEXP (addr, 1)))
3243 addr = XEXP (addr, 0);
3247 gcc_assert (GET_CODE (addr) == REG);
3251 /* Output assembler code to perform a 32-bit 3-operand add. */
3254 output_addsi3 (rtx *operands)
3256 if (! operands_match_p (operands[0], operands[1]))
3258 if (!ADDRESS_REG_P (operands[1]))
3260 rtx tmp = operands[1];
3262 operands[1] = operands[2];
3266 /* These insns can result from reloads to access
3267 stack slots over 64k from the frame pointer. */
3268 if (GET_CODE (operands[2]) == CONST_INT
3269 && (INTVAL (operands[2]) < -32768 || INTVAL (operands[2]) > 32767))
3270 return "move%.l %2,%0\n\tadd%.l %1,%0";
3271 if (GET_CODE (operands[2]) == REG)
3272 return MOTOROLA ? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
3273 return MOTOROLA ? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
3275 if (GET_CODE (operands[2]) == CONST_INT)
3277 if (INTVAL (operands[2]) > 0
3278 && INTVAL (operands[2]) <= 8)
3279 return "addq%.l %2,%0";
3280 if (INTVAL (operands[2]) < 0
3281 && INTVAL (operands[2]) >= -8)
3283 operands[2] = GEN_INT (- INTVAL (operands[2]));
3284 return "subq%.l %2,%0";
3286 /* On the CPU32 it is faster to use two addql instructions to
3287 add a small integer (8 < N <= 16) to a register.
3288 Likewise for subql. */
3289 if (TUNE_CPU32 && REG_P (operands[0]))
3291 if (INTVAL (operands[2]) > 8
3292 && INTVAL (operands[2]) <= 16)
3294 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
3295 return "addq%.l #8,%0\n\taddq%.l %2,%0";
3297 if (INTVAL (operands[2]) < -8
3298 && INTVAL (operands[2]) >= -16)
3300 operands[2] = GEN_INT (- INTVAL (operands[2]) - 8);
3301 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
3304 if (ADDRESS_REG_P (operands[0])
3305 && INTVAL (operands[2]) >= -0x8000
3306 && INTVAL (operands[2]) < 0x8000)
3309 return "add%.w %2,%0";
3311 return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
3314 return "add%.l %2,%0";
3317 /* Store in cc_status the expressions that the condition codes will
3318 describe after execution of an instruction whose pattern is EXP.
3319 Do not alter them if the instruction would not alter the cc's. */
3321 /* On the 68000, all the insns to store in an address register fail to
3322 set the cc's. However, in some cases these instructions can make it
3323 possibly invalid to use the saved cc's. In those cases we clear out
3324 some or all of the saved cc's so they won't be used. */
3327 notice_update_cc (rtx exp, rtx insn)
3329 if (GET_CODE (exp) == SET)
3331 if (GET_CODE (SET_SRC (exp)) == CALL)
3333 else if (ADDRESS_REG_P (SET_DEST (exp)))
3335 if (cc_status.value1 && modified_in_p (cc_status.value1, insn))
3336 cc_status.value1 = 0;
3337 if (cc_status.value2 && modified_in_p (cc_status.value2, insn))
3338 cc_status.value2 = 0;
3340 /* fmoves to memory or data registers do not set the condition
3341 codes. Normal moves _do_ set the condition codes, but not in
3342 a way that is appropriate for comparison with 0, because -0.0
3343 would be treated as a negative nonzero number. Note that it
3344 isn't appropriate to conditionalize this restriction on
3345 HONOR_SIGNED_ZEROS because that macro merely indicates whether
3346 we care about the difference between -0.0 and +0.0. */
3347 else if (!FP_REG_P (SET_DEST (exp))
3348 && SET_DEST (exp) != cc0_rtx
3349 && (FP_REG_P (SET_SRC (exp))
3350 || GET_CODE (SET_SRC (exp)) == FIX
3351 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp)))))
3353 /* A pair of move insns doesn't produce a useful overall cc. */
3354 else if (!FP_REG_P (SET_DEST (exp))
3355 && !FP_REG_P (SET_SRC (exp))
3356 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4
3357 && (GET_CODE (SET_SRC (exp)) == REG
3358 || GET_CODE (SET_SRC (exp)) == MEM
3359 || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE))
3361 else if (SET_DEST (exp) != pc_rtx)
3363 cc_status.flags = 0;
3364 cc_status.value1 = SET_DEST (exp);
3365 cc_status.value2 = SET_SRC (exp);
3368 else if (GET_CODE (exp) == PARALLEL
3369 && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
3371 rtx dest = SET_DEST (XVECEXP (exp, 0, 0));
3372 rtx src = SET_SRC (XVECEXP (exp, 0, 0));
3374 if (ADDRESS_REG_P (dest))
3376 else if (dest != pc_rtx)
3378 cc_status.flags = 0;
3379 cc_status.value1 = dest;
3380 cc_status.value2 = src;
3385 if (cc_status.value2 != 0
3386 && ADDRESS_REG_P (cc_status.value2)
3387 && GET_MODE (cc_status.value2) == QImode)
3389 if (cc_status.value2 != 0)
3390 switch (GET_CODE (cc_status.value2))
3392 case ASHIFT: case ASHIFTRT: case LSHIFTRT:
3393 case ROTATE: case ROTATERT:
3394 /* These instructions always clear the overflow bit, and set
3395 the carry to the bit shifted out. */
3396 /* ??? We don't currently have a way to signal carry not valid,
3397 nor do we check for it in the branch insns. */
3401 case PLUS: case MINUS: case MULT:
3402 case DIV: case UDIV: case MOD: case UMOD: case NEG:
3403 if (GET_MODE (cc_status.value2) != VOIDmode)
3404 cc_status.flags |= CC_NO_OVERFLOW;
3407 /* (SET r1 (ZERO_EXTEND r2)) on this machine
3408 ends with a move insn moving r2 in r2's mode.
3409 Thus, the cc's are set for r2.
3410 This can set N bit spuriously. */
3411 cc_status.flags |= CC_NOT_NEGATIVE;
3416 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG
3418 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
3419 cc_status.value2 = 0;
3420 if (((cc_status.value1 && FP_REG_P (cc_status.value1))
3421 || (cc_status.value2 && FP_REG_P (cc_status.value2))))
3422 cc_status.flags = CC_IN_68881;
3426 output_move_const_double (rtx *operands)
3428 int code = standard_68881_constant_p (operands[1]);
3432 static char buf[40];
3434 sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff);
3437 return "fmove%.d %1,%0";
3441 output_move_const_single (rtx *operands)
3443 int code = standard_68881_constant_p (operands[1]);
3447 static char buf[40];
3449 sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff);
3452 return "fmove%.s %f1,%0";
3455 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
3456 from the "fmovecr" instruction.
3457 The value, anded with 0xff, gives the code to use in fmovecr
3458 to get the desired constant. */
3460 /* This code has been fixed for cross-compilation. */
3462 static int inited_68881_table = 0;
3464 static const char *const strings_68881[7] = {
3474 static const int codes_68881[7] = {
3484 REAL_VALUE_TYPE values_68881[7];
3486 /* Set up values_68881 array by converting the decimal values
3487 strings_68881 to binary. */
3490 init_68881_table (void)
3494 enum machine_mode mode;
3497 for (i = 0; i < 7; i++)
3501 r = REAL_VALUE_ATOF (strings_68881[i], mode);
3502 values_68881[i] = r;
3504 inited_68881_table = 1;
3508 standard_68881_constant_p (rtx x)
3513 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
3514 used at all on those chips. */
3518 if (! inited_68881_table)
3519 init_68881_table ();
3521 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3523 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
3525 for (i = 0; i < 6; i++)
3527 if (REAL_VALUES_IDENTICAL (r, values_68881[i]))
3528 return (codes_68881[i]);
3531 if (GET_MODE (x) == SFmode)
3534 if (REAL_VALUES_EQUAL (r, values_68881[6]))
3535 return (codes_68881[6]);
3537 /* larger powers of ten in the constants ram are not used
3538 because they are not equal to a `double' C constant. */
3542 /* If X is a floating-point constant, return the logarithm of X base 2,
3543 or 0 if X is not a power of 2. */
3546 floating_exact_log2 (rtx x)
3548 REAL_VALUE_TYPE r, r1;
3551 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3553 if (REAL_VALUES_LESS (r, dconst1))
3556 exp = real_exponent (&r);
3557 real_2expN (&r1, exp);
3558 if (REAL_VALUES_EQUAL (r1, r))
3564 /* A C compound statement to output to stdio stream STREAM the
3565 assembler syntax for an instruction operand X. X is an RTL
3568 CODE is a value that can be used to specify one of several ways
3569 of printing the operand. It is used when identical operands
3570 must be printed differently depending on the context. CODE
3571 comes from the `%' specification that was used to request
3572 printing of the operand. If the specification was just `%DIGIT'
3573 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3574 is the ASCII code for LTR.
3576 If X is a register, this macro should print the register's name.
3577 The names can be found in an array `reg_names' whose type is
3578 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3580 When the machine description has a specification `%PUNCT' (a `%'
3581 followed by a punctuation character), this macro is called with
3582 a null pointer for X and the punctuation character for CODE.
3584 The m68k specific codes are:
3586 '.' for dot needed in Motorola-style opcode names.
3587 '-' for an operand pushing on the stack:
3588 sp@-, -(sp) or -(%sp) depending on the style of syntax.
3589 '+' for an operand pushing on the stack:
3590 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
3591 '@' for a reference to the top word on the stack:
3592 sp@, (sp) or (%sp) depending on the style of syntax.
3593 '#' for an immediate operand prefix (# in MIT and Motorola syntax
3594 but & in SGS syntax).
3595 '!' for the cc register (used in an `and to cc' insn).
3596 '$' for the letter `s' in an op code, but only on the 68040.
3597 '&' for the letter `d' in an op code, but only on the 68040.
3598 '/' for register prefix needed by longlong.h.
3599 '?' for m68k_library_id_string
3601 'b' for byte insn (no effect, on the Sun; this is for the ISI).
3602 'd' to force memory addressing to be absolute, not relative.
3603 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
3604 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
3605 or print pair of registers as rx:ry.
3606 'p' print an address with @PLTPC attached, but only if the operand
3607 is not locally-bound. */
3610 print_operand (FILE *file, rtx op, int letter)
3615 fprintf (file, ".");
3617 else if (letter == '#')
3618 asm_fprintf (file, "%I");
3619 else if (letter == '-')
3620 asm_fprintf (file, MOTOROLA ? "-(%Rsp)" : "%Rsp@-");
3621 else if (letter == '+')
3622 asm_fprintf (file, MOTOROLA ? "(%Rsp)+" : "%Rsp@+");
3623 else if (letter == '@')
3624 asm_fprintf (file, MOTOROLA ? "(%Rsp)" : "%Rsp@");
3625 else if (letter == '!')
3626 asm_fprintf (file, "%Rfpcr");
3627 else if (letter == '$')
3630 fprintf (file, "s");
3632 else if (letter == '&')
3635 fprintf (file, "d");
3637 else if (letter == '/')
3638 asm_fprintf (file, "%R");
3639 else if (letter == '?')
3640 asm_fprintf (file, m68k_library_id_string);
3641 else if (letter == 'p')
3643 output_addr_const (file, op);
3644 if (!(GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op)))
3645 fprintf (file, "@PLTPC");
3647 else if (GET_CODE (op) == REG)
3650 /* Print out the second register name of a register pair.
3651 I.e., R (6) => 7. */
3652 fputs (M68K_REGNAME(REGNO (op) + 1), file);
3654 fputs (M68K_REGNAME(REGNO (op)), file);
3656 else if (GET_CODE (op) == MEM)
3658 output_address (XEXP (op, 0));
3659 if (letter == 'd' && ! TARGET_68020
3660 && CONSTANT_ADDRESS_P (XEXP (op, 0))
3661 && !(GET_CODE (XEXP (op, 0)) == CONST_INT
3662 && INTVAL (XEXP (op, 0)) < 0x8000
3663 && INTVAL (XEXP (op, 0)) >= -0x8000))
3664 fprintf (file, MOTOROLA ? ".l" : ":l");
3666 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode)
3669 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
3670 ASM_OUTPUT_FLOAT_OPERAND (letter, file, r);
3672 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode)
3675 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
3676 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file, r);
3678 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode)
3681 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
3682 ASM_OUTPUT_DOUBLE_OPERAND (file, r);
3686 /* Use `print_operand_address' instead of `output_addr_const'
3687 to ensure that we print relevant PIC stuff. */
3688 asm_fprintf (file, "%I");
3690 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST))
3691 print_operand_address (file, op);
3693 output_addr_const (file, op);
3698 /* A C compound statement to output to stdio stream STREAM the
3699 assembler syntax for an instruction operand that is a memory
3700 reference whose address is ADDR. ADDR is an RTL expression.
3702 Note that this contains a kludge that knows that the only reason
3703 we have an address (plus (label_ref...) (reg...)) when not generating
3704 PIC code is in the insn before a tablejump, and we know that m68k.md
3705 generates a label LInnn: on such an insn.
3707 It is possible for PIC to generate a (plus (label_ref...) (reg...))
3708 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
3710 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
3711 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
3712 we want. This difference can be accommodated by using an assembler
3713 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
3714 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
3715 macro. See m68k/sgs.h for an example; for versions without the bug.
3716 Some assemblers refuse all the above solutions. The workaround is to
3717 emit "K(pc,d0.l*2)" with K being a small constant known to give the
3720 They also do not like things like "pea 1.w", so we simple leave off
3721 the .w on small constants.
3723 This routine is responsible for distinguishing between -fpic and -fPIC
3724 style relocations in an address. When generating -fpic code the
3725 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
3726 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
3729 print_operand_address (FILE *file, rtx addr)
3731 struct m68k_address address;
3733 if (!m68k_decompose_address (QImode, addr, true, &address))
3736 if (address.code == PRE_DEC)
3737 fprintf (file, MOTOROLA ? "-(%s)" : "%s@-",
3738 M68K_REGNAME (REGNO (address.base)));
3739 else if (address.code == POST_INC)
3740 fprintf (file, MOTOROLA ? "(%s)+" : "%s@+",
3741 M68K_REGNAME (REGNO (address.base)));
3742 else if (!address.base && !address.index)
3744 /* A constant address. */
3745 gcc_assert (address.offset == addr);
3746 if (GET_CODE (addr) == CONST_INT)
3748 /* (xxx).w or (xxx).l. */
3749 if (IN_RANGE (INTVAL (addr), -0x8000, 0x7fff))
3750 fprintf (file, MOTOROLA ? "%d.w" : "%d:w", (int) INTVAL (addr));
3752 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (addr));
3754 else if (TARGET_PCREL)
3756 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
3758 output_addr_const (file, addr);
3759 asm_fprintf (file, flag_pic == 1 ? ":w,%Rpc)" : ":l,%Rpc)");
3763 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
3764 name ends in `.<letter>', as the last 2 characters can be
3765 mistaken as a size suffix. Put the name in parentheses. */
3766 if (GET_CODE (addr) == SYMBOL_REF
3767 && strlen (XSTR (addr, 0)) > 2
3768 && XSTR (addr, 0)[strlen (XSTR (addr, 0)) - 2] == '.')
3771 output_addr_const (file, addr);
3775 output_addr_const (file, addr);
3782 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
3783 label being accessed, otherwise it is -1. */
3784 labelno = (address.offset
3786 && GET_CODE (address.offset) == LABEL_REF
3787 ? CODE_LABEL_NUMBER (XEXP (address.offset, 0))
3791 /* Print the "offset(base" component. */
3793 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,", labelno, labelno);
3798 output_addr_const (file, address.offset);
3799 if (flag_pic && address.base == pic_offset_table_rtx)
3801 fprintf (file, "@GOT");
3802 if (flag_pic == 1 && TARGET_68020)
3803 fprintf (file, ".w");
3808 fputs (M68K_REGNAME (REGNO (address.base)), file);
3810 /* Print the ",index" component, if any. */
3815 fprintf (file, "%s.%c",
3816 M68K_REGNAME (REGNO (address.index)),
3817 GET_MODE (address.index) == HImode ? 'w' : 'l');
3818 if (address.scale != 1)
3819 fprintf (file, "*%d", address.scale);
3823 else /* !MOTOROLA */
3825 if (!address.offset && !address.index)
3826 fprintf (file, "%s@", M68K_REGNAME (REGNO (address.base)));
3829 /* Print the "base@(offset" component. */
3831 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b", labelno, labelno);
3835 fputs (M68K_REGNAME (REGNO (address.base)), file);
3836 fprintf (file, "@(");
3839 output_addr_const (file, address.offset);
3840 if (address.base == pic_offset_table_rtx && TARGET_68020)
3844 fprintf (file, ":w"); break;
3846 fprintf (file, ":l"); break;
3852 /* Print the ",index" component, if any. */
3855 fprintf (file, ",%s:%c",
3856 M68K_REGNAME (REGNO (address.index)),
3857 GET_MODE (address.index) == HImode ? 'w' : 'l');
3858 if (address.scale != 1)
3859 fprintf (file, ":%d", address.scale);
3867 /* Check for cases where a clr insns can be omitted from code using
3868 strict_low_part sets. For example, the second clrl here is not needed:
3869 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3871 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3872 insn we are checking for redundancy. TARGET is the register set by the
3876 strict_low_part_peephole_ok (enum machine_mode mode, rtx first_insn,
3881 p = prev_nonnote_insn (first_insn);
3885 /* If it isn't an insn, then give up. */
3886 if (GET_CODE (p) != INSN)
3889 if (reg_set_p (target, p))
3891 rtx set = single_set (p);
3894 /* If it isn't an easy to recognize insn, then give up. */
3898 dest = SET_DEST (set);
3900 /* If this sets the entire target register to zero, then our
3901 first_insn is redundant. */
3902 if (rtx_equal_p (dest, target)
3903 && SET_SRC (set) == const0_rtx)
3905 else if (GET_CODE (dest) == STRICT_LOW_PART
3906 && GET_CODE (XEXP (dest, 0)) == REG
3907 && REGNO (XEXP (dest, 0)) == REGNO (target)
3908 && (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0)))
3909 <= GET_MODE_SIZE (mode)))
3910 /* This is a strict low part set which modifies less than
3911 we are using, so it is safe. */
3917 p = prev_nonnote_insn (p);
3923 /* Operand predicates for implementing asymmetric pc-relative addressing
3924 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3925 when used as a source operand, but not as a destination operand.
3927 We model this by restricting the meaning of the basic predicates
3928 (general_operand, memory_operand, etc) to forbid the use of this
3929 addressing mode, and then define the following predicates that permit
3930 this addressing mode. These predicates can then be used for the
3931 source operands of the appropriate instructions.
3933 n.b. While it is theoretically possible to change all machine patterns
3934 to use this addressing more where permitted by the architecture,
3935 it has only been implemented for "common" cases: SImode, HImode, and
3936 QImode operands, and only for the principle operations that would
3937 require this addressing mode: data movement and simple integer operations.
3939 In parallel with these new predicates, two new constraint letters
3940 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3941 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3942 In the pcrel case 's' is only valid in combination with 'a' registers.
3943 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3944 of how these constraints are used.
3946 The use of these predicates is strictly optional, though patterns that
3947 don't will cause an extra reload register to be allocated where one
3950 lea (abc:w,%pc),%a0 ; need to reload address
3951 moveq &1,%d1 ; since write to pc-relative space
3952 movel %d1,%a0@ ; is not allowed
3954 lea (abc:w,%pc),%a1 ; no need to reload address here
3955 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3957 For more info, consult tiemann@cygnus.com.
3960 All of the ugliness with predicates and constraints is due to the
3961 simple fact that the m68k does not allow a pc-relative addressing
3962 mode as a destination. gcc does not distinguish between source and
3963 destination addresses. Hence, if we claim that pc-relative address
3964 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3965 end up with invalid code. To get around this problem, we left
3966 pc-relative modes as invalid addresses, and then added special
3967 predicates and constraints to accept them.
3969 A cleaner way to handle this is to modify gcc to distinguish
3970 between source and destination addresses. We can then say that
3971 pc-relative is a valid source address but not a valid destination
3972 address, and hopefully avoid a lot of the predicate and constraint
3973 hackery. Unfortunately, this would be a pretty big change. It would
3974 be a useful change for a number of ports, but there aren't any current
3975 plans to undertake this.
3977 ***************************************************************************/
3981 output_andsi3 (rtx *operands)
3984 if (GET_CODE (operands[2]) == CONST_INT
3985 && (INTVAL (operands[2]) | 0xffff) == -1
3986 && (DATA_REG_P (operands[0])
3987 || offsettable_memref_p (operands[0]))
3988 && !TARGET_COLDFIRE)
3990 if (GET_CODE (operands[0]) != REG)
3991 operands[0] = adjust_address (operands[0], HImode, 2);
3992 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
3993 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3995 if (operands[2] == const0_rtx)
3997 return "and%.w %2,%0";
3999 if (GET_CODE (operands[2]) == CONST_INT
4000 && (logval = exact_log2 (~ INTVAL (operands[2]))) >= 0
4001 && (DATA_REG_P (operands[0])
4002 || offsettable_memref_p (operands[0])))
4004 if (DATA_REG_P (operands[0]))
4005 operands[1] = GEN_INT (logval);
4008 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
4009 operands[1] = GEN_INT (logval % 8);
4011 /* This does not set condition codes in a standard way. */
4013 return "bclr %1,%0";
4015 return "and%.l %2,%0";
4019 output_iorsi3 (rtx *operands)
4021 register int logval;
4022 if (GET_CODE (operands[2]) == CONST_INT
4023 && INTVAL (operands[2]) >> 16 == 0
4024 && (DATA_REG_P (operands[0])
4025 || offsettable_memref_p (operands[0]))
4026 && !TARGET_COLDFIRE)
4028 if (GET_CODE (operands[0]) != REG)
4029 operands[0] = adjust_address (operands[0], HImode, 2);
4030 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4032 if (INTVAL (operands[2]) == 0xffff)
4033 return "mov%.w %2,%0";
4034 return "or%.w %2,%0";
4036 if (GET_CODE (operands[2]) == CONST_INT
4037 && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
4038 && (DATA_REG_P (operands[0])
4039 || offsettable_memref_p (operands[0])))
4041 if (DATA_REG_P (operands[0]))
4042 operands[1] = GEN_INT (logval);
4045 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
4046 operands[1] = GEN_INT (logval % 8);
4049 return "bset %1,%0";
4051 return "or%.l %2,%0";
4055 output_xorsi3 (rtx *operands)
4057 register int logval;
4058 if (GET_CODE (operands[2]) == CONST_INT
4059 && INTVAL (operands[2]) >> 16 == 0
4060 && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0]))
4061 && !TARGET_COLDFIRE)
4063 if (! DATA_REG_P (operands[0]))
4064 operands[0] = adjust_address (operands[0], HImode, 2);
4065 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4067 if (INTVAL (operands[2]) == 0xffff)
4069 return "eor%.w %2,%0";
4071 if (GET_CODE (operands[2]) == CONST_INT
4072 && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
4073 && (DATA_REG_P (operands[0])
4074 || offsettable_memref_p (operands[0])))
4076 if (DATA_REG_P (operands[0]))
4077 operands[1] = GEN_INT (logval);
4080 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
4081 operands[1] = GEN_INT (logval % 8);
4084 return "bchg %1,%0";
4086 return "eor%.l %2,%0";
4089 /* Return the instruction that should be used for a call to address X,
4090 which is known to be in operand 0. */
4095 if (symbolic_operand (x, VOIDmode))
4096 return m68k_symbolic_call;
4101 /* Likewise sibling calls. */
4104 output_sibcall (rtx x)
4106 if (symbolic_operand (x, VOIDmode))
4107 return m68k_symbolic_jump;
4112 #ifdef M68K_TARGET_COFF
4114 /* Output assembly to switch to section NAME with attribute FLAGS. */
4117 m68k_coff_asm_named_section (const char *name, unsigned int flags,
4118 tree decl ATTRIBUTE_UNUSED)
4122 if (flags & SECTION_WRITE)
4127 fprintf (asm_out_file, "\t.section\t%s,\"%c\"\n", name, flagchar);
4130 #endif /* M68K_TARGET_COFF */
4133 m68k_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
4134 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
4137 rtx this_slot, offset, addr, mem, insn;
4139 /* Pretend to be a post-reload pass while generating rtl. */
4141 reload_completed = 1;
4143 /* The "this" pointer is stored at 4(%sp). */
4144 this_slot = gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, 4));
4146 /* Add DELTA to THIS. */
4149 /* Make the offset a legitimate operand for memory addition. */
4150 offset = GEN_INT (delta);
4151 if ((delta < -8 || delta > 8)
4152 && (TARGET_COLDFIRE || USE_MOVQ (delta)))
4154 emit_move_insn (gen_rtx_REG (Pmode, D0_REG), offset);
4155 offset = gen_rtx_REG (Pmode, D0_REG);
4157 emit_insn (gen_add3_insn (copy_rtx (this_slot),
4158 copy_rtx (this_slot), offset));
4161 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
4162 if (vcall_offset != 0)
4164 /* Set the static chain register to *THIS. */
4165 emit_move_insn (static_chain_rtx, this_slot);
4166 emit_move_insn (static_chain_rtx, gen_rtx_MEM (Pmode, static_chain_rtx));
4168 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
4169 addr = plus_constant (static_chain_rtx, vcall_offset);
4170 if (!m68k_legitimate_address_p (Pmode, addr, true))
4172 emit_insn (gen_rtx_SET (VOIDmode, static_chain_rtx, addr));
4173 addr = static_chain_rtx;
4176 /* Load the offset into %d0 and add it to THIS. */
4177 emit_move_insn (gen_rtx_REG (Pmode, D0_REG),
4178 gen_rtx_MEM (Pmode, addr));
4179 emit_insn (gen_add3_insn (copy_rtx (this_slot),
4180 copy_rtx (this_slot),
4181 gen_rtx_REG (Pmode, D0_REG)));
4184 /* Jump to the target function. Use a sibcall if direct jumps are
4185 allowed, otherwise load the address into a register first. */
4186 mem = DECL_RTL (function);
4187 if (!sibcall_operand (XEXP (mem, 0), VOIDmode))
4189 gcc_assert (flag_pic);
4191 if (!TARGET_SEP_DATA)
4193 /* Use the static chain register as a temporary (call-clobbered)
4194 GOT pointer for this function. We can use the static chain
4195 register because it isn't live on entry to the thunk. */
4196 SET_REGNO (pic_offset_table_rtx, STATIC_CHAIN_REGNUM);
4197 emit_insn (gen_load_got (pic_offset_table_rtx));
4199 legitimize_pic_address (XEXP (mem, 0), Pmode, static_chain_rtx);
4200 mem = replace_equiv_address (mem, static_chain_rtx);
4202 insn = emit_call_insn (gen_sibcall (mem, const0_rtx));
4203 SIBLING_CALL_P (insn) = 1;
4205 /* Run just enough of rest_of_compilation. */
4206 insn = get_insns ();
4207 split_all_insns_noflow ();
4208 final_start_function (insn, file, 1);
4209 final (insn, file, 1);
4210 final_end_function ();
4212 /* Clean up the vars set above. */
4213 reload_completed = 0;
4216 /* Restore the original PIC register. */
4218 SET_REGNO (pic_offset_table_rtx, PIC_REG);
4221 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
4224 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
4225 int incoming ATTRIBUTE_UNUSED)
4227 return gen_rtx_REG (Pmode, M68K_STRUCT_VALUE_REGNUM);
4230 /* Return nonzero if register old_reg can be renamed to register new_reg. */
4232 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
4233 unsigned int new_reg)
4236 /* Interrupt functions can only use registers that have already been
4237 saved by the prologue, even if they would normally be
4240 if ((m68k_get_function_kind (current_function_decl)
4241 == m68k_fk_interrupt_handler)
4242 && !df_regs_ever_live_p (new_reg))
4248 /* Value is true if hard register REGNO can hold a value of machine-mode
4249 MODE. On the 68000, we let the cpu registers can hold any mode, but
4250 restrict the 68881 registers to floating-point modes. */
4253 m68k_regno_mode_ok (int regno, enum machine_mode mode)
4255 if (DATA_REGNO_P (regno))
4257 /* Data Registers, can hold aggregate if fits in. */
4258 if (regno + GET_MODE_SIZE (mode) / 4 <= 8)
4261 else if (ADDRESS_REGNO_P (regno))
4263 if (regno + GET_MODE_SIZE (mode) / 4 <= 16)
4266 else if (FP_REGNO_P (regno))
4268 /* FPU registers, hold float or complex float of long double or
4270 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
4271 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4272 && GET_MODE_UNIT_SIZE (mode) <= TARGET_FP_REG_SIZE)
4278 /* Implement SECONDARY_RELOAD_CLASS. */
4281 m68k_secondary_reload_class (enum reg_class rclass,
4282 enum machine_mode mode, rtx x)
4286 regno = true_regnum (x);
4288 /* If one operand of a movqi is an address register, the other
4289 operand must be a general register or constant. Other types
4290 of operand must be reloaded through a data register. */
4291 if (GET_MODE_SIZE (mode) == 1
4292 && reg_classes_intersect_p (rclass, ADDR_REGS)
4293 && !(INT_REGNO_P (regno) || CONSTANT_P (x)))
4296 /* PC-relative addresses must be loaded into an address register first. */
4298 && !reg_class_subset_p (rclass, ADDR_REGS)
4299 && symbolic_operand (x, VOIDmode))
4305 /* Implement PREFERRED_RELOAD_CLASS. */
4308 m68k_preferred_reload_class (rtx x, enum reg_class rclass)
4310 enum reg_class secondary_class;
4312 /* If RCLASS might need a secondary reload, try restricting it to
4313 a class that doesn't. */
4314 secondary_class = m68k_secondary_reload_class (rclass, GET_MODE (x), x);
4315 if (secondary_class != NO_REGS
4316 && reg_class_subset_p (secondary_class, rclass))
4317 return secondary_class;
4319 /* Prefer to use moveq for in-range constants. */
4320 if (GET_CODE (x) == CONST_INT
4321 && reg_class_subset_p (DATA_REGS, rclass)
4322 && IN_RANGE (INTVAL (x), -0x80, 0x7f))
4325 /* ??? Do we really need this now? */
4326 if (GET_CODE (x) == CONST_DOUBLE
4327 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
4329 if (TARGET_HARD_FLOAT && reg_class_subset_p (FP_REGS, rclass))
4338 /* Return floating point values in a 68881 register. This makes 68881 code
4339 a little bit faster. It also makes -msoft-float code incompatible with
4340 hard-float code, so people have to be careful not to mix the two.
4341 For ColdFire it was decided the ABI incompatibility is undesirable.
4342 If there is need for a hard-float ABI it is probably worth doing it
4343 properly and also passing function arguments in FP registers. */
4345 m68k_libcall_value (enum machine_mode mode)
4352 return gen_rtx_REG (mode, FP0_REG);
4357 return gen_rtx_REG (mode, D0_REG);
4361 m68k_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
4363 enum machine_mode mode;
4365 mode = TYPE_MODE (valtype);
4371 return gen_rtx_REG (mode, FP0_REG);
4377 /* If the function returns a pointer, push that into %a0. */
4378 if (func && POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func))))
4379 /* For compatibility with the large body of existing code which
4380 does not always properly declare external functions returning
4381 pointer types, the m68k/SVR4 convention is to copy the value
4382 returned for pointer functions from a0 to d0 in the function
4383 epilogue, so that callers that have neglected to properly
4384 declare the callee can still find the correct return value in
4386 return gen_rtx_PARALLEL
4389 gen_rtx_EXPR_LIST (VOIDmode,
4390 gen_rtx_REG (mode, A0_REG),
4392 gen_rtx_EXPR_LIST (VOIDmode,
4393 gen_rtx_REG (mode, D0_REG),
4395 else if (POINTER_TYPE_P (valtype))
4396 return gen_rtx_REG (mode, A0_REG);
4398 return gen_rtx_REG (mode, D0_REG);