1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
42 #include "target-def.h"
46 /* ??? Need to add a dependency between m68k.o and sched-int.h. */
47 #include "sched-int.h"
48 #include "insn-codes.h"
50 enum reg_class regno_reg_class[] =
52 DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS,
53 DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS,
54 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
55 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
56 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
57 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
62 /* The minimum number of integer registers that we want to save with the
63 movem instruction. Using two movel instructions instead of a single
64 moveml is about 15% faster for the 68020 and 68030 at no expense in
66 #define MIN_MOVEM_REGS 3
68 /* The minimum number of floating point registers that we want to save
69 with the fmovem instruction. */
70 #define MIN_FMOVEM_REGS 1
72 /* Structure describing stack frame layout. */
75 /* Stack pointer to frame pointer offset. */
78 /* Offset of FPU registers. */
79 HOST_WIDE_INT foffset;
81 /* Frame size in bytes (rounded up). */
84 /* Data and address register. */
86 unsigned int reg_mask;
90 unsigned int fpu_mask;
92 /* Offsets relative to ARG_POINTER. */
93 HOST_WIDE_INT frame_pointer_offset;
94 HOST_WIDE_INT stack_pointer_offset;
96 /* Function which the above information refers to. */
100 /* Current frame information calculated by m68k_compute_frame_layout(). */
101 static struct m68k_frame current_frame;
103 /* Structure describing an m68k address.
105 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
106 with null fields evaluating to 0. Here:
108 - BASE satisfies m68k_legitimate_base_reg_p
109 - INDEX satisfies m68k_legitimate_index_reg_p
110 - OFFSET satisfies m68k_legitimate_constant_address_p
112 INDEX is either HImode or SImode. The other fields are SImode.
114 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
115 the address is (BASE)+. */
116 struct m68k_address {
124 static int m68k_sched_adjust_cost (rtx, rtx, rtx, int);
125 static int m68k_sched_variable_issue (FILE *, int, rtx, int);
126 static void m68k_sched_md_init_global (FILE *, int, int);
127 static void m68k_sched_md_finish_global (FILE *, int);
128 static void m68k_sched_md_init (FILE *, int, int);
129 static void m68k_sched_dfa_pre_advance_cycle (void);
130 static void m68k_sched_dfa_post_advance_cycle (void);
132 static bool m68k_handle_option (size_t, const char *, int);
133 static rtx find_addr_reg (rtx);
134 static const char *singlemove_string (rtx *);
135 #ifdef M68K_TARGET_COFF
136 static void m68k_coff_asm_named_section (const char *, unsigned int, tree);
137 #endif /* M68K_TARGET_COFF */
138 static void m68k_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
139 HOST_WIDE_INT, tree);
140 static rtx m68k_struct_value_rtx (tree, int);
141 static tree m68k_handle_fndecl_attribute (tree *node, tree name,
142 tree args, int flags,
144 static void m68k_compute_frame_layout (void);
145 static bool m68k_save_reg (unsigned int regno, bool interrupt_handler);
146 static bool m68k_ok_for_sibcall_p (tree, tree);
147 static bool m68k_rtx_costs (rtx, int, int, int *);
148 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
149 static bool m68k_return_in_memory (tree, tree);
153 /* Specify the identification number of the library being built */
154 const char *m68k_library_id_string = "_current_shared_library_a5_offset_";
156 /* Nonzero if the last compare/test insn had FP operands. The
157 sCC expanders peek at this to determine what to do for the
158 68060, which has no fsCC instructions. */
159 int m68k_last_compare_had_fp_operands;
161 /* Initialize the GCC target structure. */
163 #if INT_OP_GROUP == INT_OP_DOT_WORD
164 #undef TARGET_ASM_ALIGNED_HI_OP
165 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
168 #if INT_OP_GROUP == INT_OP_NO_DOT
169 #undef TARGET_ASM_BYTE_OP
170 #define TARGET_ASM_BYTE_OP "\tbyte\t"
171 #undef TARGET_ASM_ALIGNED_HI_OP
172 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
173 #undef TARGET_ASM_ALIGNED_SI_OP
174 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
177 #if INT_OP_GROUP == INT_OP_DC
178 #undef TARGET_ASM_BYTE_OP
179 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
180 #undef TARGET_ASM_ALIGNED_HI_OP
181 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
182 #undef TARGET_ASM_ALIGNED_SI_OP
183 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
186 #undef TARGET_ASM_UNALIGNED_HI_OP
187 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
188 #undef TARGET_ASM_UNALIGNED_SI_OP
189 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
191 #undef TARGET_ASM_OUTPUT_MI_THUNK
192 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
193 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
194 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
196 #undef TARGET_ASM_FILE_START_APP_OFF
197 #define TARGET_ASM_FILE_START_APP_OFF true
199 #undef TARGET_SCHED_ADJUST_COST
200 #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost
202 #undef TARGET_SCHED_VARIABLE_ISSUE
203 #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue
205 #undef TARGET_SCHED_INIT_GLOBAL
206 #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global
208 #undef TARGET_SCHED_FINISH_GLOBAL
209 #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global
211 #undef TARGET_SCHED_INIT
212 #define TARGET_SCHED_INIT m68k_sched_md_init
214 #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE
215 #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle
217 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
218 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle
220 #undef TARGET_HANDLE_OPTION
221 #define TARGET_HANDLE_OPTION m68k_handle_option
223 #undef TARGET_RTX_COSTS
224 #define TARGET_RTX_COSTS m68k_rtx_costs
226 #undef TARGET_ATTRIBUTE_TABLE
227 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
229 #undef TARGET_PROMOTE_PROTOTYPES
230 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
232 #undef TARGET_STRUCT_VALUE_RTX
233 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
235 #undef TARGET_CANNOT_FORCE_CONST_MEM
236 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_illegitimate_symbolic_constant_p
238 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
239 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
241 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
242 #undef TARGET_RETURN_IN_MEMORY
243 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
246 static const struct attribute_spec m68k_attribute_table[] =
248 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
249 { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute },
250 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute },
251 { "interrupt_thread", 0, 0, true, false, false, m68k_handle_fndecl_attribute },
252 { NULL, 0, 0, false, false, false, NULL }
255 struct gcc_target targetm = TARGET_INITIALIZER;
257 /* Base flags for 68k ISAs. */
258 #define FL_FOR_isa_00 FL_ISA_68000
259 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
260 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
261 generated 68881 code for 68020 and 68030 targets unless explicitly told
263 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
264 | FL_BITFIELD | FL_68881)
265 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
266 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
268 /* Base flags for ColdFire ISAs. */
269 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
270 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
271 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
272 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
273 /* ISA_C is not upwardly compatible with ISA_B. */
274 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
278 /* Traditional 68000 instruction sets. */
284 /* ColdFire instruction set variants. */
292 /* Information about one of the -march, -mcpu or -mtune arguments. */
293 struct m68k_target_selection
295 /* The argument being described. */
298 /* For -mcpu, this is the device selected by the option.
299 For -mtune and -march, it is a representative device
300 for the microarchitecture or ISA respectively. */
301 enum target_device device;
303 /* The M68K_DEVICE fields associated with DEVICE. See the comment
304 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
306 enum uarch_type microarch;
311 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
312 static const struct m68k_target_selection all_devices[] =
314 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
315 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
316 #include "m68k-devices.def"
318 { NULL, unk_device, NULL, unk_arch, isa_max, 0 }
321 /* A list of all ISAs, mapping each one to a representative device.
322 Used for -march selection. */
323 static const struct m68k_target_selection all_isas[] =
325 { "68000", m68000, NULL, u68000, isa_00, FL_FOR_isa_00 },
326 { "68010", m68010, NULL, u68010, isa_10, FL_FOR_isa_10 },
327 { "68020", m68020, NULL, u68020, isa_20, FL_FOR_isa_20 },
328 { "68030", m68030, NULL, u68030, isa_20, FL_FOR_isa_20 },
329 { "68040", m68040, NULL, u68040, isa_40, FL_FOR_isa_40 },
330 { "68060", m68060, NULL, u68060, isa_40, FL_FOR_isa_40 },
331 { "cpu32", cpu32, NULL, ucpu32, isa_20, FL_FOR_isa_cpu32 },
332 { "isaa", mcf5206e, NULL, ucfv2, isa_a, (FL_FOR_isa_a
334 { "isaaplus", mcf5271, NULL, ucfv2, isa_aplus, (FL_FOR_isa_aplus
336 { "isab", mcf5407, NULL, ucfv4, isa_b, FL_FOR_isa_b },
337 { "isac", unk_device, NULL, ucfv4, isa_c, (FL_FOR_isa_c
339 { NULL, unk_device, NULL, unk_arch, isa_max, 0 }
342 /* A list of all microarchitectures, mapping each one to a representative
343 device. Used for -mtune selection. */
344 static const struct m68k_target_selection all_microarchs[] =
346 { "68000", m68000, NULL, u68000, isa_00, FL_FOR_isa_00 },
347 { "68010", m68010, NULL, u68010, isa_10, FL_FOR_isa_10 },
348 { "68020", m68020, NULL, u68020, isa_20, FL_FOR_isa_20 },
349 { "68020-40", m68020, NULL, u68020_40, isa_20, FL_FOR_isa_20 },
350 { "68020-60", m68020, NULL, u68020_60, isa_20, FL_FOR_isa_20 },
351 { "68030", m68030, NULL, u68030, isa_20, FL_FOR_isa_20 },
352 { "68040", m68040, NULL, u68040, isa_40, FL_FOR_isa_40 },
353 { "68060", m68060, NULL, u68060, isa_40, FL_FOR_isa_40 },
354 { "cpu32", cpu32, NULL, ucpu32, isa_20, FL_FOR_isa_cpu32 },
355 { "cfv1", mcf51qe, NULL, ucfv1, isa_c, FL_FOR_isa_c },
356 { "cfv2", mcf5206, NULL, ucfv2, isa_a, FL_FOR_isa_a },
357 { "cfv3", mcf5307, NULL, ucfv3, isa_a, (FL_FOR_isa_a
359 { "cfv4", mcf5407, NULL, ucfv4, isa_b, FL_FOR_isa_b },
360 { "cfv4e", mcf547x, NULL, ucfv4e, isa_b, (FL_FOR_isa_b
364 { NULL, unk_device, NULL, unk_arch, isa_max, 0 }
367 /* The entries associated with the -mcpu, -march and -mtune settings,
368 or null for options that have not been used. */
369 const struct m68k_target_selection *m68k_cpu_entry;
370 const struct m68k_target_selection *m68k_arch_entry;
371 const struct m68k_target_selection *m68k_tune_entry;
373 /* Which CPU we are generating code for. */
374 enum target_device m68k_cpu;
376 /* Which microarchitecture to tune for. */
377 enum uarch_type m68k_tune;
379 /* Which FPU to use. */
380 enum fpu_type m68k_fpu;
382 /* The set of FL_* flags that apply to the target processor. */
383 unsigned int m68k_cpu_flags;
385 /* Asm templates for calling or jumping to an arbitrary symbolic address,
386 or NULL if such calls or jumps are not supported. The address is held
388 const char *m68k_symbolic_call;
389 const char *m68k_symbolic_jump;
391 /* Enum variable that corresponds to m68k_symbolic_call values. */
392 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var;
395 /* See whether TABLE has an entry with name NAME. Return true and
396 store the entry in *ENTRY if so, otherwise return false and
397 leave *ENTRY alone. */
400 m68k_find_selection (const struct m68k_target_selection **entry,
401 const struct m68k_target_selection *table,
406 for (i = 0; table[i].name; i++)
407 if (strcmp (table[i].name, name) == 0)
415 /* Implement TARGET_HANDLE_OPTION. */
418 m68k_handle_option (size_t code, const char *arg, int value)
423 return m68k_find_selection (&m68k_arch_entry, all_isas, arg);
426 return m68k_find_selection (&m68k_cpu_entry, all_devices, arg);
429 return m68k_find_selection (&m68k_tune_entry, all_microarchs, arg);
432 return m68k_find_selection (&m68k_cpu_entry, all_devices, "5206");
435 return m68k_find_selection (&m68k_cpu_entry, all_devices, "5206e");
438 return m68k_find_selection (&m68k_cpu_entry, all_devices, "528x");
441 return m68k_find_selection (&m68k_cpu_entry, all_devices, "5307");
444 return m68k_find_selection (&m68k_cpu_entry, all_devices, "5407");
447 return m68k_find_selection (&m68k_cpu_entry, all_devices, "547x");
451 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68000");
454 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68010");
458 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68020");
461 return (m68k_find_selection (&m68k_tune_entry, all_microarchs,
463 && m68k_find_selection (&m68k_cpu_entry, all_devices, "68020"));
466 return (m68k_find_selection (&m68k_tune_entry, all_microarchs,
468 && m68k_find_selection (&m68k_cpu_entry, all_devices, "68020"));
471 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68030");
474 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68040");
477 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68060");
480 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68302");
484 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68332");
486 case OPT_mshared_library_id_:
487 if (value > MAX_LIBRARY_ID)
488 error ("-mshared-library-id=%s is not between 0 and %d",
489 arg, MAX_LIBRARY_ID);
491 asprintf ((char **) &m68k_library_id_string, "%d", (value * -4) - 4);
499 /* Sometimes certain combinations of command options do not make
500 sense on a particular target machine. You can define a macro
501 `OVERRIDE_OPTIONS' to take account of this. This macro, if
502 defined, is executed once just after all the command options have
505 Don't use this macro to turn on various extra optimizations for
506 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
509 override_options (void)
511 const struct m68k_target_selection *entry;
512 unsigned long target_mask;
520 -march=ARCH should generate code that runs any processor
521 implementing architecture ARCH. -mcpu=CPU should override -march
522 and should generate code that runs on processor CPU, making free
523 use of any instructions that CPU understands. -mtune=UARCH applies
524 on top of -mcpu or -march and optimizes the code for UARCH. It does
525 not change the target architecture. */
528 /* Complain if the -march setting is for a different microarchitecture,
529 or includes flags that the -mcpu setting doesn't. */
531 && (m68k_arch_entry->microarch != m68k_cpu_entry->microarch
532 || (m68k_arch_entry->flags & ~m68k_cpu_entry->flags) != 0))
533 warning (0, "-mcpu=%s conflicts with -march=%s",
534 m68k_cpu_entry->name, m68k_arch_entry->name);
536 entry = m68k_cpu_entry;
539 entry = m68k_arch_entry;
542 entry = all_devices + TARGET_CPU_DEFAULT;
544 m68k_cpu_flags = entry->flags;
546 /* Use the architecture setting to derive default values for
550 /* ColdFire is lenient about alignment. */
551 if (!TARGET_COLDFIRE)
552 target_mask |= MASK_STRICT_ALIGNMENT;
554 if ((m68k_cpu_flags & FL_BITFIELD) != 0)
555 target_mask |= MASK_BITFIELD;
556 if ((m68k_cpu_flags & FL_CF_HWDIV) != 0)
557 target_mask |= MASK_CF_HWDIV;
558 if ((m68k_cpu_flags & (FL_68881 | FL_CF_FPU)) != 0)
559 target_mask |= MASK_HARD_FLOAT;
560 target_flags |= target_mask & ~target_flags_explicit;
562 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
563 m68k_cpu = entry->device;
565 m68k_tune = m68k_tune_entry->microarch;
566 #ifdef M68K_DEFAULT_TUNE
567 else if (!m68k_cpu_entry && !m68k_arch_entry)
568 m68k_tune = M68K_DEFAULT_TUNE;
571 m68k_tune = entry->microarch;
573 /* Set the type of FPU. */
574 m68k_fpu = (!TARGET_HARD_FLOAT ? FPUTYPE_NONE
575 : (m68k_cpu_flags & FL_COLDFIRE) != 0 ? FPUTYPE_COLDFIRE
578 /* Sanity check to ensure that msep-data and mid-sahred-library are not
579 * both specified together. Doing so simply doesn't make sense.
581 if (TARGET_SEP_DATA && TARGET_ID_SHARED_LIBRARY)
582 error ("cannot specify both -msep-data and -mid-shared-library");
584 /* If we're generating code for a separate A5 relative data segment,
585 * we've got to enable -fPIC as well. This might be relaxable to
586 * -fpic but it hasn't been tested properly.
588 if (TARGET_SEP_DATA || TARGET_ID_SHARED_LIBRARY)
591 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
592 error if the target does not support them. */
593 if (TARGET_PCREL && !TARGET_68020 && flag_pic == 2)
594 error ("-mpcrel -fPIC is not currently supported on selected cpu");
596 /* ??? A historic way of turning on pic, or is this intended to
597 be an embedded thing that doesn't have the same name binding
598 significance that it does on hosted ELF systems? */
599 if (TARGET_PCREL && flag_pic == 0)
604 m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_JSR;
606 m68k_symbolic_jump = "jra %a0";
608 else if (TARGET_ID_SHARED_LIBRARY)
609 /* All addresses must be loaded from the GOT. */
611 else if (TARGET_68020 || TARGET_ISAB || TARGET_ISAC)
614 m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_BSR_C;
616 m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_BSR_P;
619 /* No unconditional long branch */;
620 else if (TARGET_PCREL)
621 m68k_symbolic_jump = "bra%.l %c0";
623 m68k_symbolic_jump = "bra%.l %p0";
624 /* Turn off function cse if we are doing PIC. We always want
625 function call to be done as `bsr foo@PLTPC'. */
626 /* ??? It's traditional to do this for -mpcrel too, but it isn't
627 clear how intentional that is. */
628 flag_no_function_cse = 1;
631 switch (m68k_symbolic_call_var)
633 case M68K_SYMBOLIC_CALL_JSR:
634 m68k_symbolic_call = "jsr %a0";
637 case M68K_SYMBOLIC_CALL_BSR_C:
638 m68k_symbolic_call = "bsr%.l %c0";
641 case M68K_SYMBOLIC_CALL_BSR_P:
642 m68k_symbolic_call = "bsr%.l %p0";
645 case M68K_SYMBOLIC_CALL_NONE:
646 gcc_assert (m68k_symbolic_call == NULL);
653 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP
654 if (align_labels > 2)
656 warning (0, "-falign-labels=%d is not supported", align_labels);
661 warning (0, "-falign-loops=%d is not supported", align_loops);
666 SUBTARGET_OVERRIDE_OPTIONS;
668 /* Setup scheduling options. */
670 m68k_sched_cpu = CPU_CFV1;
672 m68k_sched_cpu = CPU_CFV2;
674 m68k_sched_cpu = CPU_CFV3;
677 m68k_sched_cpu = CPU_UNKNOWN;
678 flag_schedule_insns = 0;
679 flag_schedule_insns_after_reload = 0;
680 flag_modulo_sched = 0;
683 if (m68k_sched_cpu != CPU_UNKNOWN)
685 if ((m68k_cpu_flags & (FL_CF_EMAC | FL_CF_EMAC_B)) != 0)
686 m68k_sched_mac = MAC_CF_EMAC;
687 else if ((m68k_cpu_flags & FL_CF_MAC) != 0)
688 m68k_sched_mac = MAC_CF_MAC;
690 m68k_sched_mac = MAC_NO;
694 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
695 given argument and NAME is the argument passed to -mcpu. Return NULL
696 if -mcpu was not passed. */
699 m68k_cpp_cpu_ident (const char *prefix)
703 return concat ("__m", prefix, "_cpu_", m68k_cpu_entry->name, NULL);
706 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
707 given argument and NAME is the name of the representative device for
708 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
711 m68k_cpp_cpu_family (const char *prefix)
715 return concat ("__m", prefix, "_family_", m68k_cpu_entry->family, NULL);
718 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
719 "interrupt_handler" attribute and interrupt_thread if FUNC has an
720 "interrupt_thread" attribute. Otherwise, return
721 m68k_fk_normal_function. */
723 enum m68k_function_kind
724 m68k_get_function_kind (tree func)
728 gcc_assert (TREE_CODE (func) == FUNCTION_DECL);
730 a = lookup_attribute ("interrupt", DECL_ATTRIBUTES (func));
732 return m68k_fk_interrupt_handler;
734 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
736 return m68k_fk_interrupt_handler;
738 a = lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func));
740 return m68k_fk_interrupt_thread;
742 return m68k_fk_normal_function;
745 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
746 struct attribute_spec.handler. */
748 m68k_handle_fndecl_attribute (tree *node, tree name,
749 tree args ATTRIBUTE_UNUSED,
750 int flags ATTRIBUTE_UNUSED,
753 if (TREE_CODE (*node) != FUNCTION_DECL)
755 warning (OPT_Wattributes, "%qs attribute only applies to functions",
756 IDENTIFIER_POINTER (name));
757 *no_add_attrs = true;
760 if (m68k_get_function_kind (*node) != m68k_fk_normal_function)
762 error ("multiple interrupt attributes not allowed");
763 *no_add_attrs = true;
767 && !strcmp (IDENTIFIER_POINTER (name), "interrupt_thread"))
769 error ("interrupt_thread is available only on fido");
770 *no_add_attrs = true;
777 m68k_compute_frame_layout (void)
781 enum m68k_function_kind func_kind =
782 m68k_get_function_kind (current_function_decl);
783 bool interrupt_handler = func_kind == m68k_fk_interrupt_handler;
784 bool interrupt_thread = func_kind == m68k_fk_interrupt_thread;
786 /* Only compute the frame once per function.
787 Don't cache information until reload has been completed. */
788 if (current_frame.funcdef_no == current_function_funcdef_no
792 current_frame.size = (get_frame_size () + 3) & -4;
796 /* Interrupt thread does not need to save any register. */
797 if (!interrupt_thread)
798 for (regno = 0; regno < 16; regno++)
799 if (m68k_save_reg (regno, interrupt_handler))
801 mask |= 1 << (regno - D0_REG);
804 current_frame.offset = saved * 4;
805 current_frame.reg_no = saved;
806 current_frame.reg_mask = mask;
808 current_frame.foffset = 0;
810 if (TARGET_HARD_FLOAT)
812 /* Interrupt thread does not need to save any register. */
813 if (!interrupt_thread)
814 for (regno = 16; regno < 24; regno++)
815 if (m68k_save_reg (regno, interrupt_handler))
817 mask |= 1 << (regno - FP0_REG);
820 current_frame.foffset = saved * TARGET_FP_REG_SIZE;
821 current_frame.offset += current_frame.foffset;
823 current_frame.fpu_no = saved;
824 current_frame.fpu_mask = mask;
826 /* Remember what function this frame refers to. */
827 current_frame.funcdef_no = current_function_funcdef_no;
831 m68k_initial_elimination_offset (int from, int to)
834 /* The arg pointer points 8 bytes before the start of the arguments,
835 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
836 frame pointer in most frames. */
837 argptr_offset = frame_pointer_needed ? 0 : UNITS_PER_WORD;
838 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
839 return argptr_offset;
841 m68k_compute_frame_layout ();
843 gcc_assert (to == STACK_POINTER_REGNUM);
846 case ARG_POINTER_REGNUM:
847 return current_frame.offset + current_frame.size - argptr_offset;
848 case FRAME_POINTER_REGNUM:
849 return current_frame.offset + current_frame.size;
855 /* Refer to the array `regs_ever_live' to determine which registers
856 to save; `regs_ever_live[I]' is nonzero if register number I
857 is ever used in the function. This function is responsible for
858 knowing which registers should not be saved even if used.
859 Return true if we need to save REGNO. */
862 m68k_save_reg (unsigned int regno, bool interrupt_handler)
864 if (flag_pic && regno == PIC_REG)
866 if (current_function_saves_all_registers)
868 if (current_function_uses_pic_offset_table)
870 /* Reload may introduce constant pool references into a function
871 that thitherto didn't need a PIC register. Note that the test
872 above will not catch that case because we will only set
873 current_function_uses_pic_offset_table when emitting
874 the address reloads. */
875 if (current_function_uses_const_pool)
879 if (current_function_calls_eh_return)
884 unsigned int test = EH_RETURN_DATA_REGNO (i);
885 if (test == INVALID_REGNUM)
892 /* Fixed regs we never touch. */
893 if (fixed_regs[regno])
896 /* The frame pointer (if it is such) is handled specially. */
897 if (regno == FRAME_POINTER_REGNUM && frame_pointer_needed)
900 /* Interrupt handlers must also save call_used_regs
901 if they are live or when calling nested functions. */
902 if (interrupt_handler)
904 if (df_regs_ever_live_p (regno))
907 if (!current_function_is_leaf && call_used_regs[regno])
911 /* Never need to save registers that aren't touched. */
912 if (!df_regs_ever_live_p (regno))
915 /* Otherwise save everything that isn't call-clobbered. */
916 return !call_used_regs[regno];
919 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
920 the lowest memory address. COUNT is the number of registers to be
921 moved, with register REGNO + I being moved if bit I of MASK is set.
922 STORE_P specifies the direction of the move and ADJUST_STACK_P says
923 whether or not this is pre-decrement (if STORE_P) or post-increment
924 (if !STORE_P) operation. */
927 m68k_emit_movem (rtx base, HOST_WIDE_INT offset,
928 unsigned int count, unsigned int regno,
929 unsigned int mask, bool store_p, bool adjust_stack_p)
932 rtx body, addr, src, operands[2];
933 enum machine_mode mode;
935 body = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (adjust_stack_p + count));
936 mode = reg_raw_mode[regno];
941 src = plus_constant (base, (count
942 * GET_MODE_SIZE (mode)
943 * (HOST_WIDE_INT) (store_p ? -1 : 1)));
944 XVECEXP (body, 0, i++) = gen_rtx_SET (VOIDmode, base, src);
947 for (; mask != 0; mask >>= 1, regno++)
950 addr = plus_constant (base, offset);
951 operands[!store_p] = gen_frame_mem (mode, addr);
952 operands[store_p] = gen_rtx_REG (mode, regno);
953 XVECEXP (body, 0, i++)
954 = gen_rtx_SET (VOIDmode, operands[0], operands[1]);
955 offset += GET_MODE_SIZE (mode);
957 gcc_assert (i == XVECLEN (body, 0));
959 return emit_insn (body);
962 /* Make INSN a frame-related instruction. */
965 m68k_set_frame_related (rtx insn)
970 RTX_FRAME_RELATED_P (insn) = 1;
971 body = PATTERN (insn);
972 if (GET_CODE (body) == PARALLEL)
973 for (i = 0; i < XVECLEN (body, 0); i++)
974 RTX_FRAME_RELATED_P (XVECEXP (body, 0, i)) = 1;
977 /* Emit RTL for the "prologue" define_expand. */
980 m68k_expand_prologue (void)
982 HOST_WIDE_INT fsize_with_regs;
983 rtx limit, src, dest, insn;
985 m68k_compute_frame_layout ();
987 /* If the stack limit is a symbol, we can check it here,
988 before actually allocating the space. */
989 if (current_function_limit_stack
990 && GET_CODE (stack_limit_rtx) == SYMBOL_REF)
992 limit = plus_constant (stack_limit_rtx, current_frame.size + 4);
993 if (!LEGITIMATE_CONSTANT_P (limit))
995 emit_move_insn (gen_rtx_REG (Pmode, D0_REG), limit);
996 limit = gen_rtx_REG (Pmode, D0_REG);
998 emit_insn (gen_cmpsi (stack_pointer_rtx, limit));
999 emit_insn (gen_conditional_trap (gen_rtx_LTU (VOIDmode,
1000 cc0_rtx, const0_rtx),
1004 fsize_with_regs = current_frame.size;
1005 if (TARGET_COLDFIRE)
1007 /* ColdFire's move multiple instructions do not allow pre-decrement
1008 addressing. Add the size of movem saves to the initial stack
1009 allocation instead. */
1010 if (current_frame.reg_no >= MIN_MOVEM_REGS)
1011 fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode);
1012 if (current_frame.fpu_no >= MIN_FMOVEM_REGS)
1013 fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode);
1016 if (frame_pointer_needed)
1018 if (fsize_with_regs == 0 && TUNE_68040)
1020 /* On the 68040, two separate moves are faster than link.w 0. */
1021 dest = gen_frame_mem (Pmode,
1022 gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
1023 m68k_set_frame_related (emit_move_insn (dest, frame_pointer_rtx));
1024 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx,
1025 stack_pointer_rtx));
1027 else if (fsize_with_regs < 0x8000 || TARGET_68020)
1028 m68k_set_frame_related
1029 (emit_insn (gen_link (frame_pointer_rtx,
1030 GEN_INT (-4 - fsize_with_regs))));
1033 m68k_set_frame_related
1034 (emit_insn (gen_link (frame_pointer_rtx, GEN_INT (-4))));
1035 m68k_set_frame_related
1036 (emit_insn (gen_addsi3 (stack_pointer_rtx,
1038 GEN_INT (-fsize_with_regs))));
1041 else if (fsize_with_regs != 0)
1042 m68k_set_frame_related
1043 (emit_insn (gen_addsi3 (stack_pointer_rtx,
1045 GEN_INT (-fsize_with_regs))));
1047 if (current_frame.fpu_mask)
1049 gcc_assert (current_frame.fpu_no >= MIN_FMOVEM_REGS);
1051 m68k_set_frame_related
1052 (m68k_emit_movem (stack_pointer_rtx,
1053 current_frame.fpu_no * -GET_MODE_SIZE (XFmode),
1054 current_frame.fpu_no, FP0_REG,
1055 current_frame.fpu_mask, true, true));
1060 /* If we're using moveml to save the integer registers,
1061 the stack pointer will point to the bottom of the moveml
1062 save area. Find the stack offset of the first FP register. */
1063 if (current_frame.reg_no < MIN_MOVEM_REGS)
1066 offset = current_frame.reg_no * GET_MODE_SIZE (SImode);
1067 m68k_set_frame_related
1068 (m68k_emit_movem (stack_pointer_rtx, offset,
1069 current_frame.fpu_no, FP0_REG,
1070 current_frame.fpu_mask, true, false));
1074 /* If the stack limit is not a symbol, check it here.
1075 This has the disadvantage that it may be too late... */
1076 if (current_function_limit_stack)
1078 if (REG_P (stack_limit_rtx))
1080 emit_insn (gen_cmpsi (stack_pointer_rtx, stack_limit_rtx));
1081 emit_insn (gen_conditional_trap (gen_rtx_LTU (VOIDmode,
1082 cc0_rtx, const0_rtx),
1085 else if (GET_CODE (stack_limit_rtx) != SYMBOL_REF)
1086 warning (0, "stack limit expression is not supported");
1089 if (current_frame.reg_no < MIN_MOVEM_REGS)
1091 /* Store each register separately in the same order moveml does. */
1094 for (i = 16; i-- > 0; )
1095 if (current_frame.reg_mask & (1 << i))
1097 src = gen_rtx_REG (SImode, D0_REG + i);
1098 dest = gen_frame_mem (SImode,
1099 gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
1100 m68k_set_frame_related (emit_insn (gen_movsi (dest, src)));
1105 if (TARGET_COLDFIRE)
1106 /* The required register save space has already been allocated.
1107 The first register should be stored at (%sp). */
1108 m68k_set_frame_related
1109 (m68k_emit_movem (stack_pointer_rtx, 0,
1110 current_frame.reg_no, D0_REG,
1111 current_frame.reg_mask, true, false));
1113 m68k_set_frame_related
1114 (m68k_emit_movem (stack_pointer_rtx,
1115 current_frame.reg_no * -GET_MODE_SIZE (SImode),
1116 current_frame.reg_no, D0_REG,
1117 current_frame.reg_mask, true, true));
1122 && current_function_uses_pic_offset_table)
1123 insn = emit_insn (gen_load_got (pic_offset_table_rtx));
1126 /* Return true if a simple (return) instruction is sufficient for this
1127 instruction (i.e. if no epilogue is needed). */
1130 m68k_use_return_insn (void)
1132 if (!reload_completed || frame_pointer_needed || get_frame_size () != 0)
1135 m68k_compute_frame_layout ();
1136 return current_frame.offset == 0;
1139 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1140 SIBCALL_P says which.
1142 The function epilogue should not depend on the current stack pointer!
1143 It should use the frame pointer only, if there is a frame pointer.
1144 This is mandatory because of alloca; we also take advantage of it to
1145 omit stack adjustments before returning. */
1148 m68k_expand_epilogue (bool sibcall_p)
1150 HOST_WIDE_INT fsize, fsize_with_regs;
1151 bool big, restore_from_sp;
1153 m68k_compute_frame_layout ();
1155 fsize = current_frame.size;
1157 restore_from_sp = false;
1159 /* FIXME : current_function_is_leaf below is too strong.
1160 What we really need to know there is if there could be pending
1161 stack adjustment needed at that point. */
1162 restore_from_sp = (!frame_pointer_needed
1163 || (!current_function_calls_alloca
1164 && current_function_is_leaf));
1166 /* fsize_with_regs is the size we need to adjust the sp when
1167 popping the frame. */
1168 fsize_with_regs = fsize;
1169 if (TARGET_COLDFIRE && restore_from_sp)
1171 /* ColdFire's move multiple instructions do not allow post-increment
1172 addressing. Add the size of movem loads to the final deallocation
1174 if (current_frame.reg_no >= MIN_MOVEM_REGS)
1175 fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode);
1176 if (current_frame.fpu_no >= MIN_FMOVEM_REGS)
1177 fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode);
1180 if (current_frame.offset + fsize >= 0x8000
1182 && (current_frame.reg_mask || current_frame.fpu_mask))
1185 && (current_frame.reg_no >= MIN_MOVEM_REGS
1186 || current_frame.fpu_no >= MIN_FMOVEM_REGS))
1188 /* ColdFire's move multiple instructions do not support the
1189 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1190 stack-based restore. */
1191 emit_move_insn (gen_rtx_REG (Pmode, A1_REG),
1192 GEN_INT (-(current_frame.offset + fsize)));
1193 emit_insn (gen_addsi3 (stack_pointer_rtx,
1194 gen_rtx_REG (Pmode, A1_REG),
1195 frame_pointer_rtx));
1196 restore_from_sp = true;
1200 emit_move_insn (gen_rtx_REG (Pmode, A1_REG), GEN_INT (-fsize));
1206 if (current_frame.reg_no < MIN_MOVEM_REGS)
1208 /* Restore each register separately in the same order moveml does. */
1210 HOST_WIDE_INT offset;
1212 offset = current_frame.offset + fsize;
1213 for (i = 0; i < 16; i++)
1214 if (current_frame.reg_mask & (1 << i))
1220 /* Generate the address -OFFSET(%fp,%a1.l). */
1221 addr = gen_rtx_REG (Pmode, A1_REG);
1222 addr = gen_rtx_PLUS (Pmode, addr, frame_pointer_rtx);
1223 addr = plus_constant (addr, -offset);
1225 else if (restore_from_sp)
1226 addr = gen_rtx_POST_INC (Pmode, stack_pointer_rtx);
1228 addr = plus_constant (frame_pointer_rtx, -offset);
1229 emit_move_insn (gen_rtx_REG (SImode, D0_REG + i),
1230 gen_frame_mem (SImode, addr));
1231 offset -= GET_MODE_SIZE (SImode);
1234 else if (current_frame.reg_mask)
1237 m68k_emit_movem (gen_rtx_PLUS (Pmode,
1238 gen_rtx_REG (Pmode, A1_REG),
1240 -(current_frame.offset + fsize),
1241 current_frame.reg_no, D0_REG,
1242 current_frame.reg_mask, false, false);
1243 else if (restore_from_sp)
1244 m68k_emit_movem (stack_pointer_rtx, 0,
1245 current_frame.reg_no, D0_REG,
1246 current_frame.reg_mask, false,
1249 m68k_emit_movem (frame_pointer_rtx,
1250 -(current_frame.offset + fsize),
1251 current_frame.reg_no, D0_REG,
1252 current_frame.reg_mask, false, false);
1255 if (current_frame.fpu_no > 0)
1258 m68k_emit_movem (gen_rtx_PLUS (Pmode,
1259 gen_rtx_REG (Pmode, A1_REG),
1261 -(current_frame.foffset + fsize),
1262 current_frame.fpu_no, FP0_REG,
1263 current_frame.fpu_mask, false, false);
1264 else if (restore_from_sp)
1266 if (TARGET_COLDFIRE)
1270 /* If we used moveml to restore the integer registers, the
1271 stack pointer will still point to the bottom of the moveml
1272 save area. Find the stack offset of the first FP
1274 if (current_frame.reg_no < MIN_MOVEM_REGS)
1277 offset = current_frame.reg_no * GET_MODE_SIZE (SImode);
1278 m68k_emit_movem (stack_pointer_rtx, offset,
1279 current_frame.fpu_no, FP0_REG,
1280 current_frame.fpu_mask, false, false);
1283 m68k_emit_movem (stack_pointer_rtx, 0,
1284 current_frame.fpu_no, FP0_REG,
1285 current_frame.fpu_mask, false, true);
1288 m68k_emit_movem (frame_pointer_rtx,
1289 -(current_frame.foffset + fsize),
1290 current_frame.fpu_no, FP0_REG,
1291 current_frame.fpu_mask, false, false);
1294 if (frame_pointer_needed)
1295 emit_insn (gen_unlink (frame_pointer_rtx));
1296 else if (fsize_with_regs)
1297 emit_insn (gen_addsi3 (stack_pointer_rtx,
1299 GEN_INT (fsize_with_regs)));
1301 if (current_function_calls_eh_return)
1302 emit_insn (gen_addsi3 (stack_pointer_rtx,
1304 EH_RETURN_STACKADJ_RTX));
1307 emit_jump_insn (gen_rtx_RETURN (VOIDmode));
1310 /* Return true if X is a valid comparison operator for the dbcc
1313 Note it rejects floating point comparison operators.
1314 (In the future we could use Fdbcc).
1316 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1319 valid_dbcc_comparison_p_2 (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1321 switch (GET_CODE (x))
1323 case EQ: case NE: case GTU: case LTU:
1327 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1329 case GT: case LT: case GE: case LE:
1330 return ! (cc_prev_status.flags & CC_NO_OVERFLOW);
1336 /* Return nonzero if flags are currently in the 68881 flag register. */
1338 flags_in_68881 (void)
1340 /* We could add support for these in the future */
1341 return cc_status.flags & CC_IN_68881;
1344 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1347 m68k_ok_for_sibcall_p (tree decl, tree exp)
1349 enum m68k_function_kind kind;
1351 /* We cannot use sibcalls for nested functions because we use the
1352 static chain register for indirect calls. */
1353 if (CALL_EXPR_STATIC_CHAIN (exp))
1356 kind = m68k_get_function_kind (current_function_decl);
1357 if (kind == m68k_fk_normal_function)
1358 /* We can always sibcall from a normal function, because it's
1359 undefined if it is calling an interrupt function. */
1362 /* Otherwise we can only sibcall if the function kind is known to be
1364 if (decl && m68k_get_function_kind (decl) == kind)
1370 /* Convert X to a legitimate function call memory reference and return the
1374 m68k_legitimize_call_address (rtx x)
1376 gcc_assert (MEM_P (x));
1377 if (call_operand (XEXP (x, 0), VOIDmode))
1379 return replace_equiv_address (x, force_reg (Pmode, XEXP (x, 0)));
1382 /* Likewise for sibling calls. */
1385 m68k_legitimize_sibcall_address (rtx x)
1387 gcc_assert (MEM_P (x));
1388 if (sibcall_operand (XEXP (x, 0), VOIDmode))
1391 emit_move_insn (gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM), XEXP (x, 0));
1392 return replace_equiv_address (x, gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM));
1395 /* Output a dbCC; jCC sequence. Note we do not handle the
1396 floating point version of this sequence (Fdbcc). We also
1397 do not handle alternative conditions when CC_NO_OVERFLOW is
1398 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1399 kick those out before we get here. */
1402 output_dbcc_and_branch (rtx *operands)
1404 switch (GET_CODE (operands[3]))
1407 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands);
1411 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands);
1415 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands);
1419 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands);
1423 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands);
1427 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands);
1431 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands);
1435 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands);
1439 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands);
1443 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands);
1450 /* If the decrement is to be done in SImode, then we have
1451 to compensate for the fact that dbcc decrements in HImode. */
1452 switch (GET_MODE (operands[0]))
1455 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands);
1467 output_scc_di (rtx op, rtx operand1, rtx operand2, rtx dest)
1470 enum rtx_code op_code = GET_CODE (op);
1472 /* This does not produce a useful cc. */
1475 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1476 below. Swap the operands and change the op if these requirements
1477 are not fulfilled. */
1478 if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG)
1482 operand1 = operand2;
1484 op_code = swap_condition (op_code);
1486 loperands[0] = operand1;
1487 if (GET_CODE (operand1) == REG)
1488 loperands[1] = gen_rtx_REG (SImode, REGNO (operand1) + 1);
1490 loperands[1] = adjust_address (operand1, SImode, 4);
1491 if (operand2 != const0_rtx)
1493 loperands[2] = operand2;
1494 if (GET_CODE (operand2) == REG)
1495 loperands[3] = gen_rtx_REG (SImode, REGNO (operand2) + 1);
1497 loperands[3] = adjust_address (operand2, SImode, 4);
1499 loperands[4] = gen_label_rtx ();
1500 if (operand2 != const0_rtx)
1501 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands);
1504 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[0]))
1505 output_asm_insn ("tst%.l %0", loperands);
1507 output_asm_insn ("cmp%.w #0,%0", loperands);
1509 output_asm_insn ("jne %l4", loperands);
1511 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[1]))
1512 output_asm_insn ("tst%.l %1", loperands);
1514 output_asm_insn ("cmp%.w #0,%1", loperands);
1517 loperands[5] = dest;
1522 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1523 CODE_LABEL_NUMBER (loperands[4]));
1524 output_asm_insn ("seq %5", loperands);
1528 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1529 CODE_LABEL_NUMBER (loperands[4]));
1530 output_asm_insn ("sne %5", loperands);
1534 loperands[6] = gen_label_rtx ();
1535 output_asm_insn ("shi %5\n\tjra %l6", loperands);
1536 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1537 CODE_LABEL_NUMBER (loperands[4]));
1538 output_asm_insn ("sgt %5", loperands);
1539 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1540 CODE_LABEL_NUMBER (loperands[6]));
1544 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1545 CODE_LABEL_NUMBER (loperands[4]));
1546 output_asm_insn ("shi %5", loperands);
1550 loperands[6] = gen_label_rtx ();
1551 output_asm_insn ("scs %5\n\tjra %l6", loperands);
1552 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1553 CODE_LABEL_NUMBER (loperands[4]));
1554 output_asm_insn ("slt %5", loperands);
1555 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1556 CODE_LABEL_NUMBER (loperands[6]));
1560 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1561 CODE_LABEL_NUMBER (loperands[4]));
1562 output_asm_insn ("scs %5", loperands);
1566 loperands[6] = gen_label_rtx ();
1567 output_asm_insn ("scc %5\n\tjra %l6", loperands);
1568 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1569 CODE_LABEL_NUMBER (loperands[4]));
1570 output_asm_insn ("sge %5", loperands);
1571 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1572 CODE_LABEL_NUMBER (loperands[6]));
1576 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1577 CODE_LABEL_NUMBER (loperands[4]));
1578 output_asm_insn ("scc %5", loperands);
1582 loperands[6] = gen_label_rtx ();
1583 output_asm_insn ("sls %5\n\tjra %l6", loperands);
1584 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1585 CODE_LABEL_NUMBER (loperands[4]));
1586 output_asm_insn ("sle %5", loperands);
1587 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1588 CODE_LABEL_NUMBER (loperands[6]));
1592 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1593 CODE_LABEL_NUMBER (loperands[4]));
1594 output_asm_insn ("sls %5", loperands);
1604 output_btst (rtx *operands, rtx countop, rtx dataop, rtx insn, int signpos)
1606 operands[0] = countop;
1607 operands[1] = dataop;
1609 if (GET_CODE (countop) == CONST_INT)
1611 register int count = INTVAL (countop);
1612 /* If COUNT is bigger than size of storage unit in use,
1613 advance to the containing unit of same size. */
1614 if (count > signpos)
1616 int offset = (count & ~signpos) / 8;
1617 count = count & signpos;
1618 operands[1] = dataop = adjust_address (dataop, QImode, offset);
1620 if (count == signpos)
1621 cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N;
1623 cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N;
1625 /* These three statements used to use next_insns_test_no...
1626 but it appears that this should do the same job. */
1628 && next_insn_tests_no_inequality (insn))
1631 && next_insn_tests_no_inequality (insn))
1634 && next_insn_tests_no_inequality (insn))
1636 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1637 On some m68k variants unfortunately that's slower than btst.
1638 On 68000 and higher, that should also work for all HImode operands. */
1639 if (TUNE_CPU32 || TARGET_COLDFIRE || optimize_size)
1641 if (count == 3 && DATA_REG_P (operands[1])
1642 && next_insn_tests_no_inequality (insn))
1644 cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N | CC_NO_OVERFLOW;
1645 return "move%.w %1,%%ccr";
1647 if (count == 2 && DATA_REG_P (operands[1])
1648 && next_insn_tests_no_inequality (insn))
1650 cc_status.flags = CC_NOT_NEGATIVE | CC_INVERTED | CC_NO_OVERFLOW;
1651 return "move%.w %1,%%ccr";
1653 /* count == 1 followed by bvc/bvs and
1654 count == 0 followed by bcc/bcs are also possible, but need
1655 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1658 cc_status.flags = CC_NOT_NEGATIVE;
1660 return "btst %0,%1";
1663 /* Return true if X is a legitimate base register. STRICT_P says
1664 whether we need strict checking. */
1667 m68k_legitimate_base_reg_p (rtx x, bool strict_p)
1669 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1670 if (!strict_p && GET_CODE (x) == SUBREG)
1675 ? REGNO_OK_FOR_BASE_P (REGNO (x))
1676 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x))));
1679 /* Return true if X is a legitimate index register. STRICT_P says
1680 whether we need strict checking. */
1683 m68k_legitimate_index_reg_p (rtx x, bool strict_p)
1685 if (!strict_p && GET_CODE (x) == SUBREG)
1690 ? REGNO_OK_FOR_INDEX_P (REGNO (x))
1691 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x))));
1694 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1695 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1696 ADDRESS if so. STRICT_P says whether we need strict checking. */
1699 m68k_decompose_index (rtx x, bool strict_p, struct m68k_address *address)
1703 /* Check for a scale factor. */
1705 if ((TARGET_68020 || TARGET_COLDFIRE)
1706 && GET_CODE (x) == MULT
1707 && GET_CODE (XEXP (x, 1)) == CONST_INT
1708 && (INTVAL (XEXP (x, 1)) == 2
1709 || INTVAL (XEXP (x, 1)) == 4
1710 || (INTVAL (XEXP (x, 1)) == 8
1711 && (TARGET_COLDFIRE_FPU || !TARGET_COLDFIRE))))
1713 scale = INTVAL (XEXP (x, 1));
1717 /* Check for a word extension. */
1718 if (!TARGET_COLDFIRE
1719 && GET_CODE (x) == SIGN_EXTEND
1720 && GET_MODE (XEXP (x, 0)) == HImode)
1723 if (m68k_legitimate_index_reg_p (x, strict_p))
1725 address->scale = scale;
1733 /* Return true if X is an illegitimate symbolic constant. */
1736 m68k_illegitimate_symbolic_constant_p (rtx x)
1740 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P)
1742 split_const (x, &base, &offset);
1743 if (GET_CODE (base) == SYMBOL_REF
1744 && !offset_within_block_p (base, INTVAL (offset)))
1750 /* Return true if X is a legitimate constant address that can reach
1751 bytes in the range [X, X + REACH). STRICT_P says whether we need
1755 m68k_legitimate_constant_address_p (rtx x, unsigned int reach, bool strict_p)
1759 if (!CONSTANT_ADDRESS_P (x))
1763 && !(strict_p && TARGET_PCREL)
1764 && symbolic_operand (x, VOIDmode))
1767 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P && reach > 1)
1769 split_const (x, &base, &offset);
1770 if (GET_CODE (base) == SYMBOL_REF
1771 && !offset_within_block_p (base, INTVAL (offset) + reach - 1))
1778 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1779 labels will become jump tables. */
1782 m68k_jump_table_ref_p (rtx x)
1784 if (GET_CODE (x) != LABEL_REF)
1788 if (!NEXT_INSN (x) && !PREV_INSN (x))
1791 x = next_nonnote_insn (x);
1792 return x && JUMP_TABLE_DATA_P (x);
1795 /* Return true if X is a legitimate address for values of mode MODE.
1796 STRICT_P says whether strict checking is needed. If the address
1797 is valid, describe its components in *ADDRESS. */
1800 m68k_decompose_address (enum machine_mode mode, rtx x,
1801 bool strict_p, struct m68k_address *address)
1805 memset (address, 0, sizeof (*address));
1807 if (mode == BLKmode)
1810 reach = GET_MODE_SIZE (mode);
1812 /* Check for (An) (mode 2). */
1813 if (m68k_legitimate_base_reg_p (x, strict_p))
1819 /* Check for -(An) and (An)+ (modes 3 and 4). */
1820 if ((GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC)
1821 && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p))
1823 address->code = GET_CODE (x);
1824 address->base = XEXP (x, 0);
1828 /* Check for (d16,An) (mode 5). */
1829 if (GET_CODE (x) == PLUS
1830 && GET_CODE (XEXP (x, 1)) == CONST_INT
1831 && IN_RANGE (INTVAL (XEXP (x, 1)), -0x8000, 0x8000 - reach)
1832 && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p))
1834 address->base = XEXP (x, 0);
1835 address->offset = XEXP (x, 1);
1839 /* Check for GOT loads. These are (bd,An,Xn) addresses if
1840 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
1843 && GET_CODE (x) == PLUS
1844 && XEXP (x, 0) == pic_offset_table_rtx
1845 && (GET_CODE (XEXP (x, 1)) == SYMBOL_REF
1846 || GET_CODE (XEXP (x, 1)) == LABEL_REF))
1848 address->base = XEXP (x, 0);
1849 address->offset = XEXP (x, 1);
1853 /* The ColdFire FPU only accepts addressing modes 2-5. */
1854 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT)
1857 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
1858 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
1859 All these modes are variations of mode 7. */
1860 if (m68k_legitimate_constant_address_p (x, reach, strict_p))
1862 address->offset = x;
1866 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
1869 ??? do_tablejump creates these addresses before placing the target
1870 label, so we have to assume that unplaced labels are jump table
1871 references. It seems unlikely that we would ever generate indexed
1872 accesses to unplaced labels in other cases. */
1873 if (GET_CODE (x) == PLUS
1874 && m68k_jump_table_ref_p (XEXP (x, 1))
1875 && m68k_decompose_index (XEXP (x, 0), strict_p, address))
1877 address->offset = XEXP (x, 1);
1881 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
1882 (bd,An,Xn.SIZE*SCALE) addresses. */
1886 /* Check for a nonzero base displacement. */
1887 if (GET_CODE (x) == PLUS
1888 && m68k_legitimate_constant_address_p (XEXP (x, 1), reach, strict_p))
1890 address->offset = XEXP (x, 1);
1894 /* Check for a suppressed index register. */
1895 if (m68k_legitimate_base_reg_p (x, strict_p))
1901 /* Check for a suppressed base register. Do not allow this case
1902 for non-symbolic offsets as it effectively gives gcc freedom
1903 to treat data registers as base registers, which can generate
1906 && symbolic_operand (address->offset, VOIDmode)
1907 && m68k_decompose_index (x, strict_p, address))
1912 /* Check for a nonzero base displacement. */
1913 if (GET_CODE (x) == PLUS
1914 && GET_CODE (XEXP (x, 1)) == CONST_INT
1915 && IN_RANGE (INTVAL (XEXP (x, 1)), -0x80, 0x80 - reach))
1917 address->offset = XEXP (x, 1);
1922 /* We now expect the sum of a base and an index. */
1923 if (GET_CODE (x) == PLUS)
1925 if (m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p)
1926 && m68k_decompose_index (XEXP (x, 1), strict_p, address))
1928 address->base = XEXP (x, 0);
1932 if (m68k_legitimate_base_reg_p (XEXP (x, 1), strict_p)
1933 && m68k_decompose_index (XEXP (x, 0), strict_p, address))
1935 address->base = XEXP (x, 1);
1942 /* Return true if X is a legitimate address for values of mode MODE.
1943 STRICT_P says whether strict checking is needed. */
1946 m68k_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
1948 struct m68k_address address;
1950 return m68k_decompose_address (mode, x, strict_p, &address);
1953 /* Return true if X is a memory, describing its address in ADDRESS if so.
1954 Apply strict checking if called during or after reload. */
1957 m68k_legitimate_mem_p (rtx x, struct m68k_address *address)
1960 && m68k_decompose_address (GET_MODE (x), XEXP (x, 0),
1961 reload_in_progress || reload_completed,
1965 /* Return true if X matches the 'Q' constraint. It must be a memory
1966 with a base address and no constant offset or index. */
1969 m68k_matches_q_p (rtx x)
1971 struct m68k_address address;
1973 return (m68k_legitimate_mem_p (x, &address)
1974 && address.code == UNKNOWN
1980 /* Return true if X matches the 'U' constraint. It must be a base address
1981 with a constant offset and no index. */
1984 m68k_matches_u_p (rtx x)
1986 struct m68k_address address;
1988 return (m68k_legitimate_mem_p (x, &address)
1989 && address.code == UNKNOWN
1995 /* Legitimize PIC addresses. If the address is already
1996 position-independent, we return ORIG. Newly generated
1997 position-independent addresses go to REG. If we need more
1998 than one register, we lose.
2000 An address is legitimized by making an indirect reference
2001 through the Global Offset Table with the name of the symbol
2004 The assembler and linker are responsible for placing the
2005 address of the symbol in the GOT. The function prologue
2006 is responsible for initializing a5 to the starting address
2009 The assembler is also responsible for translating a symbol name
2010 into a constant displacement from the start of the GOT.
2012 A quick example may make things a little clearer:
2014 When not generating PIC code to store the value 12345 into _foo
2015 we would generate the following code:
2019 When generating PIC two transformations are made. First, the compiler
2020 loads the address of foo into a register. So the first transformation makes:
2025 The code in movsi will intercept the lea instruction and call this
2026 routine which will transform the instructions into:
2028 movel a5@(_foo:w), a0
2032 That (in a nutshell) is how *all* symbol and label references are
2036 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
2041 /* First handle a simple SYMBOL_REF or LABEL_REF */
2042 if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
2046 pic_ref = gen_rtx_MEM (Pmode,
2047 gen_rtx_PLUS (Pmode,
2048 pic_offset_table_rtx, orig));
2049 current_function_uses_pic_offset_table = 1;
2050 MEM_READONLY_P (pic_ref) = 1;
2051 emit_move_insn (reg, pic_ref);
2054 else if (GET_CODE (orig) == CONST)
2058 /* Make sure this has not already been legitimized. */
2059 if (GET_CODE (XEXP (orig, 0)) == PLUS
2060 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2065 /* legitimize both operands of the PLUS */
2066 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
2068 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2069 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2070 base == reg ? 0 : reg);
2072 if (GET_CODE (orig) == CONST_INT)
2073 return plus_constant (base, INTVAL (orig));
2074 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
2075 /* Likewise, should we set special REG_NOTEs here? */
2082 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2084 /* Return the type of move that should be used for integer I. */
2087 m68k_const_method (HOST_WIDE_INT i)
2094 /* The ColdFire doesn't have byte or word operations. */
2095 /* FIXME: This may not be useful for the m68060 either. */
2096 if (!TARGET_COLDFIRE)
2098 /* if -256 < N < 256 but N is not in range for a moveq
2099 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2100 if (USE_MOVQ (i ^ 0xff))
2102 /* Likewise, try with not.w */
2103 if (USE_MOVQ (i ^ 0xffff))
2105 /* This is the only value where neg.w is useful */
2110 /* Try also with swap. */
2112 if (USE_MOVQ ((u >> 16) | (u << 16)))
2117 /* Try using MVZ/MVS with an immediate value to load constants. */
2118 if (i >= 0 && i <= 65535)
2120 if (i >= -32768 && i <= 32767)
2124 /* Otherwise, use move.l */
2128 /* Return the cost of moving constant I into a data register. */
2131 const_int_cost (HOST_WIDE_INT i)
2133 switch (m68k_const_method (i))
2136 /* Constants between -128 and 127 are cheap due to moveq. */
2144 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2154 m68k_rtx_costs (rtx x, int code, int outer_code, int *total)
2159 /* Constant zero is super cheap due to clr instruction. */
2160 if (x == const0_rtx)
2163 *total = const_int_cost (INTVAL (x));
2173 /* Make 0.0 cheaper than other floating constants to
2174 encourage creating tstsf and tstdf insns. */
2175 if (outer_code == COMPARE
2176 && (x == CONST0_RTX (SFmode) || x == CONST0_RTX (DFmode)))
2182 /* These are vaguely right for a 68020. */
2183 /* The costs for long multiply have been adjusted to work properly
2184 in synth_mult on the 68020, relative to an average of the time
2185 for add and the time for shift, taking away a little more because
2186 sometimes move insns are needed. */
2187 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2193 : TARGET_COLDFIRE ? 3 : 13)
2198 : TUNE_68000_10 || TUNE_CFV2 ? 5 \
2199 : TARGET_COLDFIRE ? 2 : 8)
2202 (TARGET_CF_HWDIV ? 11 \
2203 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2206 /* An lea costs about three times as much as a simple add. */
2207 if (GET_MODE (x) == SImode
2208 && GET_CODE (XEXP (x, 1)) == REG
2209 && GET_CODE (XEXP (x, 0)) == MULT
2210 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
2211 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2212 && (INTVAL (XEXP (XEXP (x, 0), 1)) == 2
2213 || INTVAL (XEXP (XEXP (x, 0), 1)) == 4
2214 || INTVAL (XEXP (XEXP (x, 0), 1)) == 8))
2216 /* lea an@(dx:l:i),am */
2217 *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 2 : 3);
2227 *total = COSTS_N_INSNS(1);
2232 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2234 if (INTVAL (XEXP (x, 1)) < 16)
2235 *total = COSTS_N_INSNS (2) + INTVAL (XEXP (x, 1)) / 2;
2237 /* We're using clrw + swap for these cases. */
2238 *total = COSTS_N_INSNS (4) + (INTVAL (XEXP (x, 1)) - 16) / 2;
2241 *total = COSTS_N_INSNS (10); /* Worst case. */
2244 /* A shift by a big integer takes an extra instruction. */
2245 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2246 && (INTVAL (XEXP (x, 1)) == 16))
2248 *total = COSTS_N_INSNS (2); /* clrw;swap */
2251 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2252 && !(INTVAL (XEXP (x, 1)) > 0
2253 && INTVAL (XEXP (x, 1)) <= 8))
2255 *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 1 : 3); /* lsr #i,dn */
2261 if ((GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
2262 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
2263 && GET_MODE (x) == SImode)
2264 *total = COSTS_N_INSNS (MULW_COST);
2265 else if (GET_MODE (x) == QImode || GET_MODE (x) == HImode)
2266 *total = COSTS_N_INSNS (MULW_COST);
2268 *total = COSTS_N_INSNS (MULL_COST);
2275 if (GET_MODE (x) == QImode || GET_MODE (x) == HImode)
2276 *total = COSTS_N_INSNS (DIVW_COST); /* div.w */
2277 else if (TARGET_CF_HWDIV)
2278 *total = COSTS_N_INSNS (18);
2280 *total = COSTS_N_INSNS (43); /* div.l */
2288 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2292 output_move_const_into_data_reg (rtx *operands)
2296 i = INTVAL (operands[1]);
2297 switch (m68k_const_method (i))
2300 return "mvzw %1,%0";
2302 return "mvsw %1,%0";
2304 return "moveq %1,%0";
2307 operands[1] = GEN_INT (i ^ 0xff);
2308 return "moveq %1,%0\n\tnot%.b %0";
2311 operands[1] = GEN_INT (i ^ 0xffff);
2312 return "moveq %1,%0\n\tnot%.w %0";
2315 return "moveq #-128,%0\n\tneg%.w %0";
2320 operands[1] = GEN_INT ((u << 16) | (u >> 16));
2321 return "moveq %1,%0\n\tswap %0";
2324 return "move%.l %1,%0";
2330 /* Return true if I can be handled by ISA B's mov3q instruction. */
2333 valid_mov3q_const (HOST_WIDE_INT i)
2335 return TARGET_ISAB && (i == -1 || IN_RANGE (i, 1, 7));
2338 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
2339 I is the value of OPERANDS[1]. */
2342 output_move_simode_const (rtx *operands)
2348 src = INTVAL (operands[1]);
2350 && (DATA_REG_P (dest) || MEM_P (dest))
2351 /* clr insns on 68000 read before writing. */
2352 && ((TARGET_68010 || TARGET_COLDFIRE)
2353 || !(MEM_P (dest) && MEM_VOLATILE_P (dest))))
2355 else if (GET_MODE (dest) == SImode && valid_mov3q_const (src))
2356 return "mov3q%.l %1,%0";
2357 else if (src == 0 && ADDRESS_REG_P (dest))
2358 return "sub%.l %0,%0";
2359 else if (DATA_REG_P (dest))
2360 return output_move_const_into_data_reg (operands);
2361 else if (ADDRESS_REG_P (dest) && IN_RANGE (src, -0x8000, 0x7fff))
2363 if (valid_mov3q_const (src))
2364 return "mov3q%.l %1,%0";
2365 return "move%.w %1,%0";
2367 else if (MEM_P (dest)
2368 && GET_CODE (XEXP (dest, 0)) == PRE_DEC
2369 && REGNO (XEXP (XEXP (dest, 0), 0)) == STACK_POINTER_REGNUM
2370 && IN_RANGE (src, -0x8000, 0x7fff))
2372 if (valid_mov3q_const (src))
2373 return "mov3q%.l %1,%-";
2376 return "move%.l %1,%0";
2380 output_move_simode (rtx *operands)
2382 if (GET_CODE (operands[1]) == CONST_INT)
2383 return output_move_simode_const (operands);
2384 else if ((GET_CODE (operands[1]) == SYMBOL_REF
2385 || GET_CODE (operands[1]) == CONST)
2386 && push_operand (operands[0], SImode))
2388 else if ((GET_CODE (operands[1]) == SYMBOL_REF
2389 || GET_CODE (operands[1]) == CONST)
2390 && ADDRESS_REG_P (operands[0]))
2391 return "lea %a1,%0";
2392 return "move%.l %1,%0";
2396 output_move_himode (rtx *operands)
2398 if (GET_CODE (operands[1]) == CONST_INT)
2400 if (operands[1] == const0_rtx
2401 && (DATA_REG_P (operands[0])
2402 || GET_CODE (operands[0]) == MEM)
2403 /* clr insns on 68000 read before writing. */
2404 && ((TARGET_68010 || TARGET_COLDFIRE)
2405 || !(GET_CODE (operands[0]) == MEM
2406 && MEM_VOLATILE_P (operands[0]))))
2408 else if (operands[1] == const0_rtx
2409 && ADDRESS_REG_P (operands[0]))
2410 return "sub%.l %0,%0";
2411 else if (DATA_REG_P (operands[0])
2412 && INTVAL (operands[1]) < 128
2413 && INTVAL (operands[1]) >= -128)
2414 return "moveq %1,%0";
2415 else if (INTVAL (operands[1]) < 0x8000
2416 && INTVAL (operands[1]) >= -0x8000)
2417 return "move%.w %1,%0";
2419 else if (CONSTANT_P (operands[1]))
2420 return "move%.l %1,%0";
2421 return "move%.w %1,%0";
2425 output_move_qimode (rtx *operands)
2427 /* 68k family always modifies the stack pointer by at least 2, even for
2428 byte pushes. The 5200 (ColdFire) does not do this. */
2430 /* This case is generated by pushqi1 pattern now. */
2431 gcc_assert (!(GET_CODE (operands[0]) == MEM
2432 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
2433 && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx
2434 && ! ADDRESS_REG_P (operands[1])
2435 && ! TARGET_COLDFIRE));
2437 /* clr and st insns on 68000 read before writing. */
2438 if (!ADDRESS_REG_P (operands[0])
2439 && ((TARGET_68010 || TARGET_COLDFIRE)
2440 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
2442 if (operands[1] == const0_rtx)
2444 if ((!TARGET_COLDFIRE || DATA_REG_P (operands[0]))
2445 && GET_CODE (operands[1]) == CONST_INT
2446 && (INTVAL (operands[1]) & 255) == 255)
2452 if (GET_CODE (operands[1]) == CONST_INT
2453 && DATA_REG_P (operands[0])
2454 && INTVAL (operands[1]) < 128
2455 && INTVAL (operands[1]) >= -128)
2456 return "moveq %1,%0";
2457 if (operands[1] == const0_rtx && ADDRESS_REG_P (operands[0]))
2458 return "sub%.l %0,%0";
2459 if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
2460 return "move%.l %1,%0";
2461 /* 68k family (including the 5200 ColdFire) does not support byte moves to
2462 from address registers. */
2463 if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
2464 return "move%.w %1,%0";
2465 return "move%.b %1,%0";
2469 output_move_stricthi (rtx *operands)
2471 if (operands[1] == const0_rtx
2472 /* clr insns on 68000 read before writing. */
2473 && ((TARGET_68010 || TARGET_COLDFIRE)
2474 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
2476 return "move%.w %1,%0";
2480 output_move_strictqi (rtx *operands)
2482 if (operands[1] == const0_rtx
2483 /* clr insns on 68000 read before writing. */
2484 && ((TARGET_68010 || TARGET_COLDFIRE)
2485 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
2487 return "move%.b %1,%0";
2490 /* Return the best assembler insn template
2491 for moving operands[1] into operands[0] as a fullword. */
2494 singlemove_string (rtx *operands)
2496 if (GET_CODE (operands[1]) == CONST_INT)
2497 return output_move_simode_const (operands);
2498 return "move%.l %1,%0";
2502 /* Output assembler or rtl code to perform a doubleword move insn
2503 with operands OPERANDS.
2504 Pointers to 3 helper functions should be specified:
2505 HANDLE_REG_ADJUST to adjust a register by a small value,
2506 HANDLE_COMPADR to compute an address and
2507 HANDLE_MOVSI to move 4 bytes. */
2510 handle_move_double (rtx operands[2],
2511 void (*handle_reg_adjust) (rtx, int),
2512 void (*handle_compadr) (rtx [2]),
2513 void (*handle_movsi) (rtx [2]))
2517 REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP
2522 rtx addreg0 = 0, addreg1 = 0;
2523 int dest_overlapped_low = 0;
2524 int size = GET_MODE_SIZE (GET_MODE (operands[0]));
2529 /* First classify both operands. */
2531 if (REG_P (operands[0]))
2533 else if (offsettable_memref_p (operands[0]))
2535 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2537 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2539 else if (GET_CODE (operands[0]) == MEM)
2544 if (REG_P (operands[1]))
2546 else if (CONSTANT_P (operands[1]))
2548 else if (offsettable_memref_p (operands[1]))
2550 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
2552 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2554 else if (GET_CODE (operands[1]) == MEM)
2559 /* Check for the cases that the operand constraints are not supposed
2560 to allow to happen. Generating code for these cases is
2562 gcc_assert (optype0 != RNDOP && optype1 != RNDOP);
2564 /* If one operand is decrementing and one is incrementing
2565 decrement the former register explicitly
2566 and change that operand into ordinary indexing. */
2568 if (optype0 == PUSHOP && optype1 == POPOP)
2570 operands[0] = XEXP (XEXP (operands[0], 0), 0);
2572 handle_reg_adjust (operands[0], -size);
2574 if (GET_MODE (operands[1]) == XFmode)
2575 operands[0] = gen_rtx_MEM (XFmode, operands[0]);
2576 else if (GET_MODE (operands[0]) == DFmode)
2577 operands[0] = gen_rtx_MEM (DFmode, operands[0]);
2579 operands[0] = gen_rtx_MEM (DImode, operands[0]);
2582 if (optype0 == POPOP && optype1 == PUSHOP)
2584 operands[1] = XEXP (XEXP (operands[1], 0), 0);
2586 handle_reg_adjust (operands[1], -size);
2588 if (GET_MODE (operands[1]) == XFmode)
2589 operands[1] = gen_rtx_MEM (XFmode, operands[1]);
2590 else if (GET_MODE (operands[1]) == DFmode)
2591 operands[1] = gen_rtx_MEM (DFmode, operands[1]);
2593 operands[1] = gen_rtx_MEM (DImode, operands[1]);
2597 /* If an operand is an unoffsettable memory ref, find a register
2598 we can increment temporarily to make it refer to the second word. */
2600 if (optype0 == MEMOP)
2601 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2603 if (optype1 == MEMOP)
2604 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2606 /* Ok, we can do one word at a time.
2607 Normally we do the low-numbered word first,
2608 but if either operand is autodecrementing then we
2609 do the high-numbered word first.
2611 In either case, set up in LATEHALF the operands to use
2612 for the high-numbered word and in some cases alter the
2613 operands in OPERANDS to be suitable for the low-numbered word. */
2617 if (optype0 == REGOP)
2619 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2);
2620 middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2622 else if (optype0 == OFFSOP)
2624 middlehalf[0] = adjust_address (operands[0], SImode, 4);
2625 latehalf[0] = adjust_address (operands[0], SImode, size - 4);
2629 middlehalf[0] = adjust_address (operands[0], SImode, 0);
2630 latehalf[0] = adjust_address (operands[0], SImode, 0);
2633 if (optype1 == REGOP)
2635 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
2636 middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2638 else if (optype1 == OFFSOP)
2640 middlehalf[1] = adjust_address (operands[1], SImode, 4);
2641 latehalf[1] = adjust_address (operands[1], SImode, size - 4);
2643 else if (optype1 == CNSTOP)
2645 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2650 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
2651 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
2652 operands[1] = GEN_INT (l[0]);
2653 middlehalf[1] = GEN_INT (l[1]);
2654 latehalf[1] = GEN_INT (l[2]);
2658 /* No non-CONST_DOUBLE constant should ever appear
2660 gcc_assert (!CONSTANT_P (operands[1]));
2665 middlehalf[1] = adjust_address (operands[1], SImode, 0);
2666 latehalf[1] = adjust_address (operands[1], SImode, 0);
2670 /* size is not 12: */
2672 if (optype0 == REGOP)
2673 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2674 else if (optype0 == OFFSOP)
2675 latehalf[0] = adjust_address (operands[0], SImode, size - 4);
2677 latehalf[0] = adjust_address (operands[0], SImode, 0);
2679 if (optype1 == REGOP)
2680 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2681 else if (optype1 == OFFSOP)
2682 latehalf[1] = adjust_address (operands[1], SImode, size - 4);
2683 else if (optype1 == CNSTOP)
2684 split_double (operands[1], &operands[1], &latehalf[1]);
2686 latehalf[1] = adjust_address (operands[1], SImode, 0);
2689 /* If insn is effectively movd N(sp),-(sp) then we will do the
2690 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2691 for the low word as well, to compensate for the first decrement of sp. */
2692 if (optype0 == PUSHOP
2693 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
2694 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
2695 operands[1] = middlehalf[1] = latehalf[1];
2697 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2698 if the upper part of reg N does not appear in the MEM, arrange to
2699 emit the move late-half first. Otherwise, compute the MEM address
2700 into the upper part of N and use that as a pointer to the memory
2702 if (optype0 == REGOP
2703 && (optype1 == OFFSOP || optype1 == MEMOP))
2705 rtx testlow = gen_rtx_REG (SImode, REGNO (operands[0]));
2707 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
2708 && reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
2710 /* If both halves of dest are used in the src memory address,
2711 compute the address into latehalf of dest.
2712 Note that this can't happen if the dest is two data regs. */
2714 xops[0] = latehalf[0];
2715 xops[1] = XEXP (operands[1], 0);
2717 handle_compadr (xops);
2718 if (GET_MODE (operands[1]) == XFmode)
2720 operands[1] = gen_rtx_MEM (XFmode, latehalf[0]);
2721 middlehalf[1] = adjust_address (operands[1], DImode, size - 8);
2722 latehalf[1] = adjust_address (operands[1], DImode, size - 4);
2726 operands[1] = gen_rtx_MEM (DImode, latehalf[0]);
2727 latehalf[1] = adjust_address (operands[1], DImode, size - 4);
2731 && reg_overlap_mentioned_p (middlehalf[0],
2732 XEXP (operands[1], 0)))
2734 /* Check for two regs used by both source and dest.
2735 Note that this can't happen if the dest is all data regs.
2736 It can happen if the dest is d6, d7, a0.
2737 But in that case, latehalf is an addr reg, so
2738 the code at compadr does ok. */
2740 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
2741 || reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
2744 /* JRV says this can't happen: */
2745 gcc_assert (!addreg0 && !addreg1);
2747 /* Only the middle reg conflicts; simply put it last. */
2748 handle_movsi (operands);
2749 handle_movsi (latehalf);
2750 handle_movsi (middlehalf);
2754 else if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)))
2755 /* If the low half of dest is mentioned in the source memory
2756 address, the arrange to emit the move late half first. */
2757 dest_overlapped_low = 1;
2760 /* If one or both operands autodecrementing,
2761 do the two words, high-numbered first. */
2763 /* Likewise, the first move would clobber the source of the second one,
2764 do them in the other order. This happens only for registers;
2765 such overlap can't happen in memory unless the user explicitly
2766 sets it up, and that is an undefined circumstance. */
2768 if (optype0 == PUSHOP || optype1 == PUSHOP
2769 || (optype0 == REGOP && optype1 == REGOP
2770 && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1]))
2771 || REGNO (operands[0]) == REGNO (latehalf[1])))
2772 || dest_overlapped_low)
2774 /* Make any unoffsettable addresses point at high-numbered word. */
2776 handle_reg_adjust (addreg0, size - 4);
2778 handle_reg_adjust (addreg1, size - 4);
2781 handle_movsi (latehalf);
2783 /* Undo the adds we just did. */
2785 handle_reg_adjust (addreg0, -4);
2787 handle_reg_adjust (addreg1, -4);
2791 handle_movsi (middlehalf);
2794 handle_reg_adjust (addreg0, -4);
2796 handle_reg_adjust (addreg1, -4);
2799 /* Do low-numbered word. */
2801 handle_movsi (operands);
2805 /* Normal case: do the two words, low-numbered first. */
2807 handle_movsi (operands);
2809 /* Do the middle one of the three words for long double */
2813 handle_reg_adjust (addreg0, 4);
2815 handle_reg_adjust (addreg1, 4);
2817 handle_movsi (middlehalf);
2820 /* Make any unoffsettable addresses point at high-numbered word. */
2822 handle_reg_adjust (addreg0, 4);
2824 handle_reg_adjust (addreg1, 4);
2827 handle_movsi (latehalf);
2829 /* Undo the adds we just did. */
2831 handle_reg_adjust (addreg0, -(size - 4));
2833 handle_reg_adjust (addreg1, -(size - 4));
2838 /* Output assembler code to adjust REG by N. */
2840 output_reg_adjust (rtx reg, int n)
2844 gcc_assert (GET_MODE (reg) == SImode
2845 && -12 <= n && n != 0 && n <= 12);
2850 s = "add%.l #12,%0";
2854 s = "addq%.l #8,%0";
2858 s = "addq%.l #4,%0";
2862 s = "sub%.l #12,%0";
2866 s = "subq%.l #8,%0";
2870 s = "subq%.l #4,%0";
2878 output_asm_insn (s, ®);
2881 /* Emit rtl code to adjust REG by N. */
2883 emit_reg_adjust (rtx reg1, int n)
2887 gcc_assert (GET_MODE (reg1) == SImode
2888 && -12 <= n && n != 0 && n <= 12);
2890 reg1 = copy_rtx (reg1);
2891 reg2 = copy_rtx (reg1);
2894 emit_insn (gen_subsi3 (reg1, reg2, GEN_INT (-n)));
2896 emit_insn (gen_addsi3 (reg1, reg2, GEN_INT (n)));
2901 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
2903 output_compadr (rtx operands[2])
2905 output_asm_insn ("lea %a1,%0", operands);
2908 /* Output the best assembler insn for moving operands[1] into operands[0]
2911 output_movsi (rtx operands[2])
2913 output_asm_insn (singlemove_string (operands), operands);
2916 /* Copy OP and change its mode to MODE. */
2918 copy_operand (rtx op, enum machine_mode mode)
2920 /* ??? This looks really ugly. There must be a better way
2921 to change a mode on the operand. */
2922 if (GET_MODE (op) != VOIDmode)
2925 op = gen_rtx_REG (mode, REGNO (op));
2929 PUT_MODE (op, mode);
2936 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
2938 emit_movsi (rtx operands[2])
2940 operands[0] = copy_operand (operands[0], SImode);
2941 operands[1] = copy_operand (operands[1], SImode);
2943 emit_insn (gen_movsi (operands[0], operands[1]));
2946 /* Output assembler code to perform a doubleword move insn
2947 with operands OPERANDS. */
2949 output_move_double (rtx *operands)
2951 handle_move_double (operands,
2952 output_reg_adjust, output_compadr, output_movsi);
2957 /* Output rtl code to perform a doubleword move insn
2958 with operands OPERANDS. */
2960 m68k_emit_move_double (rtx operands[2])
2962 handle_move_double (operands, emit_reg_adjust, emit_movsi, emit_movsi);
2965 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
2966 new rtx with the correct mode. */
2969 force_mode (enum machine_mode mode, rtx orig)
2971 if (mode == GET_MODE (orig))
2974 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
2977 return gen_rtx_REG (mode, REGNO (orig));
2981 fp_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2983 return reg_renumber && FP_REG_P (op);
2986 /* Emit insns to move operands[1] into operands[0].
2988 Return 1 if we have written out everything that needs to be done to
2989 do the move. Otherwise, return 0 and the caller will emit the move
2992 Note SCRATCH_REG may not be in the proper mode depending on how it
2993 will be used. This routine is responsible for creating a new copy
2994 of SCRATCH_REG in the proper mode. */
2997 emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
2999 register rtx operand0 = operands[0];
3000 register rtx operand1 = operands[1];
3004 && reload_in_progress && GET_CODE (operand0) == REG
3005 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
3006 operand0 = reg_equiv_mem[REGNO (operand0)];
3007 else if (scratch_reg
3008 && reload_in_progress && GET_CODE (operand0) == SUBREG
3009 && GET_CODE (SUBREG_REG (operand0)) == REG
3010 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
3012 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3013 the code which tracks sets/uses for delete_output_reload. */
3014 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
3015 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
3016 SUBREG_BYTE (operand0));
3017 operand0 = alter_subreg (&temp);
3021 && reload_in_progress && GET_CODE (operand1) == REG
3022 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
3023 operand1 = reg_equiv_mem[REGNO (operand1)];
3024 else if (scratch_reg
3025 && reload_in_progress && GET_CODE (operand1) == SUBREG
3026 && GET_CODE (SUBREG_REG (operand1)) == REG
3027 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
3029 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3030 the code which tracks sets/uses for delete_output_reload. */
3031 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
3032 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
3033 SUBREG_BYTE (operand1));
3034 operand1 = alter_subreg (&temp);
3037 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
3038 && ((tem = find_replacement (&XEXP (operand0, 0)))
3039 != XEXP (operand0, 0)))
3040 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
3041 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
3042 && ((tem = find_replacement (&XEXP (operand1, 0)))
3043 != XEXP (operand1, 0)))
3044 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
3046 /* Handle secondary reloads for loads/stores of FP registers where
3047 the address is symbolic by using the scratch register */
3048 if (fp_reg_operand (operand0, mode)
3049 && ((GET_CODE (operand1) == MEM
3050 && ! memory_address_p (DFmode, XEXP (operand1, 0)))
3051 || ((GET_CODE (operand1) == SUBREG
3052 && GET_CODE (XEXP (operand1, 0)) == MEM
3053 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
3056 if (GET_CODE (operand1) == SUBREG)
3057 operand1 = XEXP (operand1, 0);
3059 /* SCRATCH_REG will hold an address. We want
3060 it in SImode regardless of what mode it was originally given
3062 scratch_reg = force_mode (SImode, scratch_reg);
3064 /* D might not fit in 14 bits either; for such cases load D into
3066 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
3068 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
3069 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
3071 XEXP (XEXP (operand1, 0), 0),
3075 emit_move_insn (scratch_reg, XEXP (operand1, 0));
3076 emit_insn (gen_rtx_SET (VOIDmode, operand0,
3077 gen_rtx_MEM (mode, scratch_reg)));
3080 else if (fp_reg_operand (operand1, mode)
3081 && ((GET_CODE (operand0) == MEM
3082 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
3083 || ((GET_CODE (operand0) == SUBREG)
3084 && GET_CODE (XEXP (operand0, 0)) == MEM
3085 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
3088 if (GET_CODE (operand0) == SUBREG)
3089 operand0 = XEXP (operand0, 0);
3091 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3092 it in SIMODE regardless of what mode it was originally given
3094 scratch_reg = force_mode (SImode, scratch_reg);
3096 /* D might not fit in 14 bits either; for such cases load D into
3098 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
3100 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
3101 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
3104 XEXP (XEXP (operand0, 0),
3109 emit_move_insn (scratch_reg, XEXP (operand0, 0));
3110 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
3114 /* Handle secondary reloads for loads of FP registers from constant
3115 expressions by forcing the constant into memory.
3117 use scratch_reg to hold the address of the memory location.
3119 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3120 NO_REGS when presented with a const_int and an register class
3121 containing only FP registers. Doing so unfortunately creates
3122 more problems than it solves. Fix this for 2.5. */
3123 else if (fp_reg_operand (operand0, mode)
3124 && CONSTANT_P (operand1)
3129 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3130 it in SIMODE regardless of what mode it was originally given
3132 scratch_reg = force_mode (SImode, scratch_reg);
3134 /* Force the constant into memory and put the address of the
3135 memory location into scratch_reg. */
3136 xoperands[0] = scratch_reg;
3137 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
3138 emit_insn (gen_rtx_SET (mode, scratch_reg, xoperands[1]));
3140 /* Now load the destination register. */
3141 emit_insn (gen_rtx_SET (mode, operand0,
3142 gen_rtx_MEM (mode, scratch_reg)));
3146 /* Now have insn-emit do whatever it normally does. */
3150 /* Split one or more DImode RTL references into pairs of SImode
3151 references. The RTL can be REG, offsettable MEM, integer constant, or
3152 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3153 split and "num" is its length. lo_half and hi_half are output arrays
3154 that parallel "operands". */
3157 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
3161 rtx op = operands[num];
3163 /* simplify_subreg refuses to split volatile memory addresses,
3164 but we still have to handle it. */
3165 if (GET_CODE (op) == MEM)
3167 lo_half[num] = adjust_address (op, SImode, 4);
3168 hi_half[num] = adjust_address (op, SImode, 0);
3172 lo_half[num] = simplify_gen_subreg (SImode, op,
3173 GET_MODE (op) == VOIDmode
3174 ? DImode : GET_MODE (op), 4);
3175 hi_half[num] = simplify_gen_subreg (SImode, op,
3176 GET_MODE (op) == VOIDmode
3177 ? DImode : GET_MODE (op), 0);
3182 /* Split X into a base and a constant offset, storing them in *BASE
3183 and *OFFSET respectively. */
3186 m68k_split_offset (rtx x, rtx *base, HOST_WIDE_INT *offset)
3189 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
3191 *offset += INTVAL (XEXP (x, 1));
3197 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3198 instruction. STORE_P says whether the move is a load or store.
3200 If the instruction uses post-increment or pre-decrement addressing,
3201 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3202 adjustment. This adjustment will be made by the first element of
3203 PARALLEL, with the loads or stores starting at element 1. If the
3204 instruction does not use post-increment or pre-decrement addressing,
3205 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3206 start at element 0. */
3209 m68k_movem_pattern_p (rtx pattern, rtx automod_base,
3210 HOST_WIDE_INT automod_offset, bool store_p)
3212 rtx base, mem_base, set, mem, reg, last_reg;
3213 HOST_WIDE_INT offset, mem_offset;
3215 enum reg_class rclass;
3217 len = XVECLEN (pattern, 0);
3218 first = (automod_base != NULL);
3222 /* Stores must be pre-decrement and loads must be post-increment. */
3223 if (store_p != (automod_offset < 0))
3226 /* Work out the base and offset for lowest memory location. */
3227 base = automod_base;
3228 offset = (automod_offset < 0 ? automod_offset : 0);
3232 /* Allow any valid base and offset in the first access. */
3239 for (i = first; i < len; i++)
3241 /* We need a plain SET. */
3242 set = XVECEXP (pattern, 0, i);
3243 if (GET_CODE (set) != SET)
3246 /* Check that we have a memory location... */
3247 mem = XEXP (set, !store_p);
3248 if (!MEM_P (mem) || !memory_operand (mem, VOIDmode))
3251 /* ...with the right address. */
3254 m68k_split_offset (XEXP (mem, 0), &base, &offset);
3255 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3256 There are no mode restrictions for 680x0 besides the
3257 automodification rules enforced above. */
3259 && !m68k_legitimate_base_reg_p (base, reload_completed))
3264 m68k_split_offset (XEXP (mem, 0), &mem_base, &mem_offset);
3265 if (!rtx_equal_p (base, mem_base) || offset != mem_offset)
3269 /* Check that we have a register of the required mode and class. */
3270 reg = XEXP (set, store_p);
3272 || !HARD_REGISTER_P (reg)
3273 || GET_MODE (reg) != reg_raw_mode[REGNO (reg)])
3278 /* The register must belong to RCLASS and have a higher number
3279 than the register in the previous SET. */
3280 if (!TEST_HARD_REG_BIT (reg_class_contents[rclass], REGNO (reg))
3281 || REGNO (last_reg) >= REGNO (reg))
3286 /* Work out which register class we need. */
3287 if (INT_REGNO_P (REGNO (reg)))
3288 rclass = GENERAL_REGS;
3289 else if (FP_REGNO_P (REGNO (reg)))
3296 offset += GET_MODE_SIZE (GET_MODE (reg));
3299 /* If we have an automodification, check whether the final offset is OK. */
3300 if (automod_base && offset != (automod_offset < 0 ? 0 : automod_offset))
3303 /* Reject unprofitable cases. */
3304 if (len < first + (rclass == FP_REGS ? MIN_FMOVEM_REGS : MIN_MOVEM_REGS))
3310 /* Return the assembly code template for a movem or fmovem instruction
3311 whose pattern is given by PATTERN. Store the template's operands
3314 If the instruction uses post-increment or pre-decrement addressing,
3315 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3316 is true if this is a store instruction. */
3319 m68k_output_movem (rtx *operands, rtx pattern,
3320 HOST_WIDE_INT automod_offset, bool store_p)
3325 gcc_assert (GET_CODE (pattern) == PARALLEL);
3327 first = (automod_offset != 0);
3328 for (i = first; i < XVECLEN (pattern, 0); i++)
3330 /* When using movem with pre-decrement addressing, register X + D0_REG
3331 is controlled by bit 15 - X. For all other addressing modes,
3332 register X + D0_REG is controlled by bit X. Confusingly, the
3333 register mask for fmovem is in the opposite order to that for
3337 gcc_assert (MEM_P (XEXP (XVECEXP (pattern, 0, i), !store_p)));
3338 gcc_assert (REG_P (XEXP (XVECEXP (pattern, 0, i), store_p)));
3339 regno = REGNO (XEXP (XVECEXP (pattern, 0, i), store_p));
3340 if (automod_offset < 0)
3342 if (FP_REGNO_P (regno))
3343 mask |= 1 << (regno - FP0_REG);
3345 mask |= 1 << (15 - (regno - D0_REG));
3349 if (FP_REGNO_P (regno))
3350 mask |= 1 << (7 - (regno - FP0_REG));
3352 mask |= 1 << (regno - D0_REG);
3357 if (automod_offset == 0)
3358 operands[0] = XEXP (XEXP (XVECEXP (pattern, 0, first), !store_p), 0);
3359 else if (automod_offset < 0)
3360 operands[0] = gen_rtx_PRE_DEC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0)));
3362 operands[0] = gen_rtx_POST_INC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0)));
3363 operands[1] = GEN_INT (mask);
3364 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern, 0, first), store_p))))
3367 return "fmovem %1,%a0";
3369 return "fmovem %a0,%1";
3374 return "movem%.l %1,%a0";
3376 return "movem%.l %a0,%1";
3380 /* Return a REG that occurs in ADDR with coefficient 1.
3381 ADDR can be effectively incremented by incrementing REG. */
3384 find_addr_reg (rtx addr)
3386 while (GET_CODE (addr) == PLUS)
3388 if (GET_CODE (XEXP (addr, 0)) == REG)
3389 addr = XEXP (addr, 0);
3390 else if (GET_CODE (XEXP (addr, 1)) == REG)
3391 addr = XEXP (addr, 1);
3392 else if (CONSTANT_P (XEXP (addr, 0)))
3393 addr = XEXP (addr, 1);
3394 else if (CONSTANT_P (XEXP (addr, 1)))
3395 addr = XEXP (addr, 0);
3399 gcc_assert (GET_CODE (addr) == REG);
3403 /* Output assembler code to perform a 32-bit 3-operand add. */
3406 output_addsi3 (rtx *operands)
3408 if (! operands_match_p (operands[0], operands[1]))
3410 if (!ADDRESS_REG_P (operands[1]))
3412 rtx tmp = operands[1];
3414 operands[1] = operands[2];
3418 /* These insns can result from reloads to access
3419 stack slots over 64k from the frame pointer. */
3420 if (GET_CODE (operands[2]) == CONST_INT
3421 && (INTVAL (operands[2]) < -32768 || INTVAL (operands[2]) > 32767))
3422 return "move%.l %2,%0\n\tadd%.l %1,%0";
3423 if (GET_CODE (operands[2]) == REG)
3424 return MOTOROLA ? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
3425 return MOTOROLA ? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
3427 if (GET_CODE (operands[2]) == CONST_INT)
3429 if (INTVAL (operands[2]) > 0
3430 && INTVAL (operands[2]) <= 8)
3431 return "addq%.l %2,%0";
3432 if (INTVAL (operands[2]) < 0
3433 && INTVAL (operands[2]) >= -8)
3435 operands[2] = GEN_INT (- INTVAL (operands[2]));
3436 return "subq%.l %2,%0";
3438 /* On the CPU32 it is faster to use two addql instructions to
3439 add a small integer (8 < N <= 16) to a register.
3440 Likewise for subql. */
3441 if (TUNE_CPU32 && REG_P (operands[0]))
3443 if (INTVAL (operands[2]) > 8
3444 && INTVAL (operands[2]) <= 16)
3446 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
3447 return "addq%.l #8,%0\n\taddq%.l %2,%0";
3449 if (INTVAL (operands[2]) < -8
3450 && INTVAL (operands[2]) >= -16)
3452 operands[2] = GEN_INT (- INTVAL (operands[2]) - 8);
3453 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
3456 if (ADDRESS_REG_P (operands[0])
3457 && INTVAL (operands[2]) >= -0x8000
3458 && INTVAL (operands[2]) < 0x8000)
3461 return "add%.w %2,%0";
3463 return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
3466 return "add%.l %2,%0";
3469 /* Store in cc_status the expressions that the condition codes will
3470 describe after execution of an instruction whose pattern is EXP.
3471 Do not alter them if the instruction would not alter the cc's. */
3473 /* On the 68000, all the insns to store in an address register fail to
3474 set the cc's. However, in some cases these instructions can make it
3475 possibly invalid to use the saved cc's. In those cases we clear out
3476 some or all of the saved cc's so they won't be used. */
3479 notice_update_cc (rtx exp, rtx insn)
3481 if (GET_CODE (exp) == SET)
3483 if (GET_CODE (SET_SRC (exp)) == CALL)
3485 else if (ADDRESS_REG_P (SET_DEST (exp)))
3487 if (cc_status.value1 && modified_in_p (cc_status.value1, insn))
3488 cc_status.value1 = 0;
3489 if (cc_status.value2 && modified_in_p (cc_status.value2, insn))
3490 cc_status.value2 = 0;
3492 /* fmoves to memory or data registers do not set the condition
3493 codes. Normal moves _do_ set the condition codes, but not in
3494 a way that is appropriate for comparison with 0, because -0.0
3495 would be treated as a negative nonzero number. Note that it
3496 isn't appropriate to conditionalize this restriction on
3497 HONOR_SIGNED_ZEROS because that macro merely indicates whether
3498 we care about the difference between -0.0 and +0.0. */
3499 else if (!FP_REG_P (SET_DEST (exp))
3500 && SET_DEST (exp) != cc0_rtx
3501 && (FP_REG_P (SET_SRC (exp))
3502 || GET_CODE (SET_SRC (exp)) == FIX
3503 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp)))))
3505 /* A pair of move insns doesn't produce a useful overall cc. */
3506 else if (!FP_REG_P (SET_DEST (exp))
3507 && !FP_REG_P (SET_SRC (exp))
3508 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4
3509 && (GET_CODE (SET_SRC (exp)) == REG
3510 || GET_CODE (SET_SRC (exp)) == MEM
3511 || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE))
3513 else if (SET_DEST (exp) != pc_rtx)
3515 cc_status.flags = 0;
3516 cc_status.value1 = SET_DEST (exp);
3517 cc_status.value2 = SET_SRC (exp);
3520 else if (GET_CODE (exp) == PARALLEL
3521 && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
3523 rtx dest = SET_DEST (XVECEXP (exp, 0, 0));
3524 rtx src = SET_SRC (XVECEXP (exp, 0, 0));
3526 if (ADDRESS_REG_P (dest))
3528 else if (dest != pc_rtx)
3530 cc_status.flags = 0;
3531 cc_status.value1 = dest;
3532 cc_status.value2 = src;
3537 if (cc_status.value2 != 0
3538 && ADDRESS_REG_P (cc_status.value2)
3539 && GET_MODE (cc_status.value2) == QImode)
3541 if (cc_status.value2 != 0)
3542 switch (GET_CODE (cc_status.value2))
3544 case ASHIFT: case ASHIFTRT: case LSHIFTRT:
3545 case ROTATE: case ROTATERT:
3546 /* These instructions always clear the overflow bit, and set
3547 the carry to the bit shifted out. */
3548 /* ??? We don't currently have a way to signal carry not valid,
3549 nor do we check for it in the branch insns. */
3553 case PLUS: case MINUS: case MULT:
3554 case DIV: case UDIV: case MOD: case UMOD: case NEG:
3555 if (GET_MODE (cc_status.value2) != VOIDmode)
3556 cc_status.flags |= CC_NO_OVERFLOW;
3559 /* (SET r1 (ZERO_EXTEND r2)) on this machine
3560 ends with a move insn moving r2 in r2's mode.
3561 Thus, the cc's are set for r2.
3562 This can set N bit spuriously. */
3563 cc_status.flags |= CC_NOT_NEGATIVE;
3568 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG
3570 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
3571 cc_status.value2 = 0;
3572 if (((cc_status.value1 && FP_REG_P (cc_status.value1))
3573 || (cc_status.value2 && FP_REG_P (cc_status.value2))))
3574 cc_status.flags = CC_IN_68881;
3575 if (cc_status.value2 && GET_CODE (cc_status.value2) == COMPARE
3576 && GET_MODE_CLASS (GET_MODE (XEXP (cc_status.value2, 0))) == MODE_FLOAT)
3578 cc_status.flags = CC_IN_68881;
3579 if (!FP_REG_P (XEXP (cc_status.value2, 0)))
3580 cc_status.flags |= CC_REVERSED;
3585 output_move_const_double (rtx *operands)
3587 int code = standard_68881_constant_p (operands[1]);
3591 static char buf[40];
3593 sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff);
3596 return "fmove%.d %1,%0";
3600 output_move_const_single (rtx *operands)
3602 int code = standard_68881_constant_p (operands[1]);
3606 static char buf[40];
3608 sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff);
3611 return "fmove%.s %f1,%0";
3614 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
3615 from the "fmovecr" instruction.
3616 The value, anded with 0xff, gives the code to use in fmovecr
3617 to get the desired constant. */
3619 /* This code has been fixed for cross-compilation. */
3621 static int inited_68881_table = 0;
3623 static const char *const strings_68881[7] = {
3633 static const int codes_68881[7] = {
3643 REAL_VALUE_TYPE values_68881[7];
3645 /* Set up values_68881 array by converting the decimal values
3646 strings_68881 to binary. */
3649 init_68881_table (void)
3653 enum machine_mode mode;
3656 for (i = 0; i < 7; i++)
3660 r = REAL_VALUE_ATOF (strings_68881[i], mode);
3661 values_68881[i] = r;
3663 inited_68881_table = 1;
3667 standard_68881_constant_p (rtx x)
3672 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
3673 used at all on those chips. */
3677 if (! inited_68881_table)
3678 init_68881_table ();
3680 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3682 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
3684 for (i = 0; i < 6; i++)
3686 if (REAL_VALUES_IDENTICAL (r, values_68881[i]))
3687 return (codes_68881[i]);
3690 if (GET_MODE (x) == SFmode)
3693 if (REAL_VALUES_EQUAL (r, values_68881[6]))
3694 return (codes_68881[6]);
3696 /* larger powers of ten in the constants ram are not used
3697 because they are not equal to a `double' C constant. */
3701 /* If X is a floating-point constant, return the logarithm of X base 2,
3702 or 0 if X is not a power of 2. */
3705 floating_exact_log2 (rtx x)
3707 REAL_VALUE_TYPE r, r1;
3710 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3712 if (REAL_VALUES_LESS (r, dconst1))
3715 exp = real_exponent (&r);
3716 real_2expN (&r1, exp, DFmode);
3717 if (REAL_VALUES_EQUAL (r1, r))
3723 /* A C compound statement to output to stdio stream STREAM the
3724 assembler syntax for an instruction operand X. X is an RTL
3727 CODE is a value that can be used to specify one of several ways
3728 of printing the operand. It is used when identical operands
3729 must be printed differently depending on the context. CODE
3730 comes from the `%' specification that was used to request
3731 printing of the operand. If the specification was just `%DIGIT'
3732 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3733 is the ASCII code for LTR.
3735 If X is a register, this macro should print the register's name.
3736 The names can be found in an array `reg_names' whose type is
3737 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3739 When the machine description has a specification `%PUNCT' (a `%'
3740 followed by a punctuation character), this macro is called with
3741 a null pointer for X and the punctuation character for CODE.
3743 The m68k specific codes are:
3745 '.' for dot needed in Motorola-style opcode names.
3746 '-' for an operand pushing on the stack:
3747 sp@-, -(sp) or -(%sp) depending on the style of syntax.
3748 '+' for an operand pushing on the stack:
3749 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
3750 '@' for a reference to the top word on the stack:
3751 sp@, (sp) or (%sp) depending on the style of syntax.
3752 '#' for an immediate operand prefix (# in MIT and Motorola syntax
3753 but & in SGS syntax).
3754 '!' for the cc register (used in an `and to cc' insn).
3755 '$' for the letter `s' in an op code, but only on the 68040.
3756 '&' for the letter `d' in an op code, but only on the 68040.
3757 '/' for register prefix needed by longlong.h.
3758 '?' for m68k_library_id_string
3760 'b' for byte insn (no effect, on the Sun; this is for the ISI).
3761 'd' to force memory addressing to be absolute, not relative.
3762 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
3763 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
3764 or print pair of registers as rx:ry.
3765 'p' print an address with @PLTPC attached, but only if the operand
3766 is not locally-bound. */
3769 print_operand (FILE *file, rtx op, int letter)
3774 fprintf (file, ".");
3776 else if (letter == '#')
3777 asm_fprintf (file, "%I");
3778 else if (letter == '-')
3779 asm_fprintf (file, MOTOROLA ? "-(%Rsp)" : "%Rsp@-");
3780 else if (letter == '+')
3781 asm_fprintf (file, MOTOROLA ? "(%Rsp)+" : "%Rsp@+");
3782 else if (letter == '@')
3783 asm_fprintf (file, MOTOROLA ? "(%Rsp)" : "%Rsp@");
3784 else if (letter == '!')
3785 asm_fprintf (file, "%Rfpcr");
3786 else if (letter == '$')
3789 fprintf (file, "s");
3791 else if (letter == '&')
3794 fprintf (file, "d");
3796 else if (letter == '/')
3797 asm_fprintf (file, "%R");
3798 else if (letter == '?')
3799 asm_fprintf (file, m68k_library_id_string);
3800 else if (letter == 'p')
3802 output_addr_const (file, op);
3803 if (!(GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op)))
3804 fprintf (file, "@PLTPC");
3806 else if (GET_CODE (op) == REG)
3809 /* Print out the second register name of a register pair.
3810 I.e., R (6) => 7. */
3811 fputs (M68K_REGNAME(REGNO (op) + 1), file);
3813 fputs (M68K_REGNAME(REGNO (op)), file);
3815 else if (GET_CODE (op) == MEM)
3817 output_address (XEXP (op, 0));
3818 if (letter == 'd' && ! TARGET_68020
3819 && CONSTANT_ADDRESS_P (XEXP (op, 0))
3820 && !(GET_CODE (XEXP (op, 0)) == CONST_INT
3821 && INTVAL (XEXP (op, 0)) < 0x8000
3822 && INTVAL (XEXP (op, 0)) >= -0x8000))
3823 fprintf (file, MOTOROLA ? ".l" : ":l");
3825 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode)
3828 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
3829 ASM_OUTPUT_FLOAT_OPERAND (letter, file, r);
3831 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode)
3834 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
3835 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file, r);
3837 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode)
3840 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
3841 ASM_OUTPUT_DOUBLE_OPERAND (file, r);
3845 /* Use `print_operand_address' instead of `output_addr_const'
3846 to ensure that we print relevant PIC stuff. */
3847 asm_fprintf (file, "%I");
3849 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST))
3850 print_operand_address (file, op);
3852 output_addr_const (file, op);
3857 /* A C compound statement to output to stdio stream STREAM the
3858 assembler syntax for an instruction operand that is a memory
3859 reference whose address is ADDR. ADDR is an RTL expression.
3861 Note that this contains a kludge that knows that the only reason
3862 we have an address (plus (label_ref...) (reg...)) when not generating
3863 PIC code is in the insn before a tablejump, and we know that m68k.md
3864 generates a label LInnn: on such an insn.
3866 It is possible for PIC to generate a (plus (label_ref...) (reg...))
3867 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
3869 This routine is responsible for distinguishing between -fpic and -fPIC
3870 style relocations in an address. When generating -fpic code the
3871 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
3872 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
3875 print_operand_address (FILE *file, rtx addr)
3877 struct m68k_address address;
3879 if (!m68k_decompose_address (QImode, addr, true, &address))
3882 if (address.code == PRE_DEC)
3883 fprintf (file, MOTOROLA ? "-(%s)" : "%s@-",
3884 M68K_REGNAME (REGNO (address.base)));
3885 else if (address.code == POST_INC)
3886 fprintf (file, MOTOROLA ? "(%s)+" : "%s@+",
3887 M68K_REGNAME (REGNO (address.base)));
3888 else if (!address.base && !address.index)
3890 /* A constant address. */
3891 gcc_assert (address.offset == addr);
3892 if (GET_CODE (addr) == CONST_INT)
3894 /* (xxx).w or (xxx).l. */
3895 if (IN_RANGE (INTVAL (addr), -0x8000, 0x7fff))
3896 fprintf (file, MOTOROLA ? "%d.w" : "%d:w", (int) INTVAL (addr));
3898 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (addr));
3900 else if (TARGET_PCREL)
3902 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
3904 output_addr_const (file, addr);
3905 asm_fprintf (file, flag_pic == 1 ? ":w,%Rpc)" : ":l,%Rpc)");
3909 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
3910 name ends in `.<letter>', as the last 2 characters can be
3911 mistaken as a size suffix. Put the name in parentheses. */
3912 if (GET_CODE (addr) == SYMBOL_REF
3913 && strlen (XSTR (addr, 0)) > 2
3914 && XSTR (addr, 0)[strlen (XSTR (addr, 0)) - 2] == '.')
3917 output_addr_const (file, addr);
3921 output_addr_const (file, addr);
3928 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
3929 label being accessed, otherwise it is -1. */
3930 labelno = (address.offset
3932 && GET_CODE (address.offset) == LABEL_REF
3933 ? CODE_LABEL_NUMBER (XEXP (address.offset, 0))
3937 /* Print the "offset(base" component. */
3939 asm_fprintf (file, "%LL%d(%Rpc,", labelno);
3944 output_addr_const (file, address.offset);
3945 if (flag_pic && address.base == pic_offset_table_rtx)
3947 fprintf (file, "@GOT");
3948 if (flag_pic == 1 && TARGET_68020)
3949 fprintf (file, ".w");
3954 fputs (M68K_REGNAME (REGNO (address.base)), file);
3956 /* Print the ",index" component, if any. */
3961 fprintf (file, "%s.%c",
3962 M68K_REGNAME (REGNO (address.index)),
3963 GET_MODE (address.index) == HImode ? 'w' : 'l');
3964 if (address.scale != 1)
3965 fprintf (file, "*%d", address.scale);
3969 else /* !MOTOROLA */
3971 if (!address.offset && !address.index)
3972 fprintf (file, "%s@", M68K_REGNAME (REGNO (address.base)));
3975 /* Print the "base@(offset" component. */
3977 asm_fprintf (file, "%Rpc@(%LL%d", labelno);
3981 fputs (M68K_REGNAME (REGNO (address.base)), file);
3982 fprintf (file, "@(");
3985 output_addr_const (file, address.offset);
3986 if (address.base == pic_offset_table_rtx && TARGET_68020)
3990 fprintf (file, ":w"); break;
3992 fprintf (file, ":l"); break;
3998 /* Print the ",index" component, if any. */
4001 fprintf (file, ",%s:%c",
4002 M68K_REGNAME (REGNO (address.index)),
4003 GET_MODE (address.index) == HImode ? 'w' : 'l');
4004 if (address.scale != 1)
4005 fprintf (file, ":%d", address.scale);
4013 /* Check for cases where a clr insns can be omitted from code using
4014 strict_low_part sets. For example, the second clrl here is not needed:
4015 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
4017 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
4018 insn we are checking for redundancy. TARGET is the register set by the
4022 strict_low_part_peephole_ok (enum machine_mode mode, rtx first_insn,
4027 while ((p = PREV_INSN (p)))
4029 if (NOTE_INSN_BASIC_BLOCK_P (p))
4035 /* If it isn't an insn, then give up. */
4039 if (reg_set_p (target, p))
4041 rtx set = single_set (p);
4044 /* If it isn't an easy to recognize insn, then give up. */
4048 dest = SET_DEST (set);
4050 /* If this sets the entire target register to zero, then our
4051 first_insn is redundant. */
4052 if (rtx_equal_p (dest, target)
4053 && SET_SRC (set) == const0_rtx)
4055 else if (GET_CODE (dest) == STRICT_LOW_PART
4056 && GET_CODE (XEXP (dest, 0)) == REG
4057 && REGNO (XEXP (dest, 0)) == REGNO (target)
4058 && (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0)))
4059 <= GET_MODE_SIZE (mode)))
4060 /* This is a strict low part set which modifies less than
4061 we are using, so it is safe. */
4071 /* Operand predicates for implementing asymmetric pc-relative addressing
4072 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4073 when used as a source operand, but not as a destination operand.
4075 We model this by restricting the meaning of the basic predicates
4076 (general_operand, memory_operand, etc) to forbid the use of this
4077 addressing mode, and then define the following predicates that permit
4078 this addressing mode. These predicates can then be used for the
4079 source operands of the appropriate instructions.
4081 n.b. While it is theoretically possible to change all machine patterns
4082 to use this addressing more where permitted by the architecture,
4083 it has only been implemented for "common" cases: SImode, HImode, and
4084 QImode operands, and only for the principle operations that would
4085 require this addressing mode: data movement and simple integer operations.
4087 In parallel with these new predicates, two new constraint letters
4088 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4089 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4090 In the pcrel case 's' is only valid in combination with 'a' registers.
4091 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4092 of how these constraints are used.
4094 The use of these predicates is strictly optional, though patterns that
4095 don't will cause an extra reload register to be allocated where one
4098 lea (abc:w,%pc),%a0 ; need to reload address
4099 moveq &1,%d1 ; since write to pc-relative space
4100 movel %d1,%a0@ ; is not allowed
4102 lea (abc:w,%pc),%a1 ; no need to reload address here
4103 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4105 For more info, consult tiemann@cygnus.com.
4108 All of the ugliness with predicates and constraints is due to the
4109 simple fact that the m68k does not allow a pc-relative addressing
4110 mode as a destination. gcc does not distinguish between source and
4111 destination addresses. Hence, if we claim that pc-relative address
4112 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
4113 end up with invalid code. To get around this problem, we left
4114 pc-relative modes as invalid addresses, and then added special
4115 predicates and constraints to accept them.
4117 A cleaner way to handle this is to modify gcc to distinguish
4118 between source and destination addresses. We can then say that
4119 pc-relative is a valid source address but not a valid destination
4120 address, and hopefully avoid a lot of the predicate and constraint
4121 hackery. Unfortunately, this would be a pretty big change. It would
4122 be a useful change for a number of ports, but there aren't any current
4123 plans to undertake this.
4125 ***************************************************************************/
4129 output_andsi3 (rtx *operands)
4132 if (GET_CODE (operands[2]) == CONST_INT
4133 && (INTVAL (operands[2]) | 0xffff) == -1
4134 && (DATA_REG_P (operands[0])
4135 || offsettable_memref_p (operands[0]))
4136 && !TARGET_COLDFIRE)
4138 if (GET_CODE (operands[0]) != REG)
4139 operands[0] = adjust_address (operands[0], HImode, 2);
4140 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
4141 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4143 if (operands[2] == const0_rtx)
4145 return "and%.w %2,%0";
4147 if (GET_CODE (operands[2]) == CONST_INT
4148 && (logval = exact_log2 (~ INTVAL (operands[2]))) >= 0
4149 && (DATA_REG_P (operands[0])
4150 || offsettable_memref_p (operands[0])))
4152 if (DATA_REG_P (operands[0]))
4153 operands[1] = GEN_INT (logval);
4156 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
4157 operands[1] = GEN_INT (logval % 8);
4159 /* This does not set condition codes in a standard way. */
4161 return "bclr %1,%0";
4163 return "and%.l %2,%0";
4167 output_iorsi3 (rtx *operands)
4169 register int logval;
4170 if (GET_CODE (operands[2]) == CONST_INT
4171 && INTVAL (operands[2]) >> 16 == 0
4172 && (DATA_REG_P (operands[0])
4173 || offsettable_memref_p (operands[0]))
4174 && !TARGET_COLDFIRE)
4176 if (GET_CODE (operands[0]) != REG)
4177 operands[0] = adjust_address (operands[0], HImode, 2);
4178 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4180 if (INTVAL (operands[2]) == 0xffff)
4181 return "mov%.w %2,%0";
4182 return "or%.w %2,%0";
4184 if (GET_CODE (operands[2]) == CONST_INT
4185 && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
4186 && (DATA_REG_P (operands[0])
4187 || offsettable_memref_p (operands[0])))
4189 if (DATA_REG_P (operands[0]))
4190 operands[1] = GEN_INT (logval);
4193 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
4194 operands[1] = GEN_INT (logval % 8);
4197 return "bset %1,%0";
4199 return "or%.l %2,%0";
4203 output_xorsi3 (rtx *operands)
4205 register int logval;
4206 if (GET_CODE (operands[2]) == CONST_INT
4207 && INTVAL (operands[2]) >> 16 == 0
4208 && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0]))
4209 && !TARGET_COLDFIRE)
4211 if (! DATA_REG_P (operands[0]))
4212 operands[0] = adjust_address (operands[0], HImode, 2);
4213 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4215 if (INTVAL (operands[2]) == 0xffff)
4217 return "eor%.w %2,%0";
4219 if (GET_CODE (operands[2]) == CONST_INT
4220 && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
4221 && (DATA_REG_P (operands[0])
4222 || offsettable_memref_p (operands[0])))
4224 if (DATA_REG_P (operands[0]))
4225 operands[1] = GEN_INT (logval);
4228 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
4229 operands[1] = GEN_INT (logval % 8);
4232 return "bchg %1,%0";
4234 return "eor%.l %2,%0";
4237 /* Return the instruction that should be used for a call to address X,
4238 which is known to be in operand 0. */
4243 if (symbolic_operand (x, VOIDmode))
4244 return m68k_symbolic_call;
4249 /* Likewise sibling calls. */
4252 output_sibcall (rtx x)
4254 if (symbolic_operand (x, VOIDmode))
4255 return m68k_symbolic_jump;
4260 #ifdef M68K_TARGET_COFF
4262 /* Output assembly to switch to section NAME with attribute FLAGS. */
4265 m68k_coff_asm_named_section (const char *name, unsigned int flags,
4266 tree decl ATTRIBUTE_UNUSED)
4270 if (flags & SECTION_WRITE)
4275 fprintf (asm_out_file, "\t.section\t%s,\"%c\"\n", name, flagchar);
4278 #endif /* M68K_TARGET_COFF */
4281 m68k_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
4282 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
4285 rtx this_slot, offset, addr, mem, insn;
4287 /* Pretend to be a post-reload pass while generating rtl. */
4288 reload_completed = 1;
4290 /* The "this" pointer is stored at 4(%sp). */
4291 this_slot = gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, 4));
4293 /* Add DELTA to THIS. */
4296 /* Make the offset a legitimate operand for memory addition. */
4297 offset = GEN_INT (delta);
4298 if ((delta < -8 || delta > 8)
4299 && (TARGET_COLDFIRE || USE_MOVQ (delta)))
4301 emit_move_insn (gen_rtx_REG (Pmode, D0_REG), offset);
4302 offset = gen_rtx_REG (Pmode, D0_REG);
4304 emit_insn (gen_add3_insn (copy_rtx (this_slot),
4305 copy_rtx (this_slot), offset));
4308 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
4309 if (vcall_offset != 0)
4311 /* Set the static chain register to *THIS. */
4312 emit_move_insn (static_chain_rtx, this_slot);
4313 emit_move_insn (static_chain_rtx, gen_rtx_MEM (Pmode, static_chain_rtx));
4315 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
4316 addr = plus_constant (static_chain_rtx, vcall_offset);
4317 if (!m68k_legitimate_address_p (Pmode, addr, true))
4319 emit_insn (gen_rtx_SET (VOIDmode, static_chain_rtx, addr));
4320 addr = static_chain_rtx;
4323 /* Load the offset into %d0 and add it to THIS. */
4324 emit_move_insn (gen_rtx_REG (Pmode, D0_REG),
4325 gen_rtx_MEM (Pmode, addr));
4326 emit_insn (gen_add3_insn (copy_rtx (this_slot),
4327 copy_rtx (this_slot),
4328 gen_rtx_REG (Pmode, D0_REG)));
4331 /* Jump to the target function. Use a sibcall if direct jumps are
4332 allowed, otherwise load the address into a register first. */
4333 mem = DECL_RTL (function);
4334 if (!sibcall_operand (XEXP (mem, 0), VOIDmode))
4336 gcc_assert (flag_pic);
4338 if (!TARGET_SEP_DATA)
4340 /* Use the static chain register as a temporary (call-clobbered)
4341 GOT pointer for this function. We can use the static chain
4342 register because it isn't live on entry to the thunk. */
4343 SET_REGNO (pic_offset_table_rtx, STATIC_CHAIN_REGNUM);
4344 emit_insn (gen_load_got (pic_offset_table_rtx));
4346 legitimize_pic_address (XEXP (mem, 0), Pmode, static_chain_rtx);
4347 mem = replace_equiv_address (mem, static_chain_rtx);
4349 insn = emit_call_insn (gen_sibcall (mem, const0_rtx));
4350 SIBLING_CALL_P (insn) = 1;
4352 /* Run just enough of rest_of_compilation. */
4353 insn = get_insns ();
4354 split_all_insns_noflow ();
4355 final_start_function (insn, file, 1);
4356 final (insn, file, 1);
4357 final_end_function ();
4359 /* Clean up the vars set above. */
4360 reload_completed = 0;
4362 /* Restore the original PIC register. */
4364 SET_REGNO (pic_offset_table_rtx, PIC_REG);
4365 free_after_compilation (cfun);
4368 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
4371 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
4372 int incoming ATTRIBUTE_UNUSED)
4374 return gen_rtx_REG (Pmode, M68K_STRUCT_VALUE_REGNUM);
4377 /* Return nonzero if register old_reg can be renamed to register new_reg. */
4379 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
4380 unsigned int new_reg)
4383 /* Interrupt functions can only use registers that have already been
4384 saved by the prologue, even if they would normally be
4387 if ((m68k_get_function_kind (current_function_decl)
4388 == m68k_fk_interrupt_handler)
4389 && !df_regs_ever_live_p (new_reg))
4395 /* Value is true if hard register REGNO can hold a value of machine-mode
4396 MODE. On the 68000, we let the cpu registers can hold any mode, but
4397 restrict the 68881 registers to floating-point modes. */
4400 m68k_regno_mode_ok (int regno, enum machine_mode mode)
4402 if (DATA_REGNO_P (regno))
4404 /* Data Registers, can hold aggregate if fits in. */
4405 if (regno + GET_MODE_SIZE (mode) / 4 <= 8)
4408 else if (ADDRESS_REGNO_P (regno))
4410 if (regno + GET_MODE_SIZE (mode) / 4 <= 16)
4413 else if (FP_REGNO_P (regno))
4415 /* FPU registers, hold float or complex float of long double or
4417 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
4418 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4419 && GET_MODE_UNIT_SIZE (mode) <= TARGET_FP_REG_SIZE)
4425 /* Implement SECONDARY_RELOAD_CLASS. */
4428 m68k_secondary_reload_class (enum reg_class rclass,
4429 enum machine_mode mode, rtx x)
4433 regno = true_regnum (x);
4435 /* If one operand of a movqi is an address register, the other
4436 operand must be a general register or constant. Other types
4437 of operand must be reloaded through a data register. */
4438 if (GET_MODE_SIZE (mode) == 1
4439 && reg_classes_intersect_p (rclass, ADDR_REGS)
4440 && !(INT_REGNO_P (regno) || CONSTANT_P (x)))
4443 /* PC-relative addresses must be loaded into an address register first. */
4445 && !reg_class_subset_p (rclass, ADDR_REGS)
4446 && symbolic_operand (x, VOIDmode))
4452 /* Implement PREFERRED_RELOAD_CLASS. */
4455 m68k_preferred_reload_class (rtx x, enum reg_class rclass)
4457 enum reg_class secondary_class;
4459 /* If RCLASS might need a secondary reload, try restricting it to
4460 a class that doesn't. */
4461 secondary_class = m68k_secondary_reload_class (rclass, GET_MODE (x), x);
4462 if (secondary_class != NO_REGS
4463 && reg_class_subset_p (secondary_class, rclass))
4464 return secondary_class;
4466 /* Prefer to use moveq for in-range constants. */
4467 if (GET_CODE (x) == CONST_INT
4468 && reg_class_subset_p (DATA_REGS, rclass)
4469 && IN_RANGE (INTVAL (x), -0x80, 0x7f))
4472 /* ??? Do we really need this now? */
4473 if (GET_CODE (x) == CONST_DOUBLE
4474 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
4476 if (TARGET_HARD_FLOAT && reg_class_subset_p (FP_REGS, rclass))
4485 /* Return floating point values in a 68881 register. This makes 68881 code
4486 a little bit faster. It also makes -msoft-float code incompatible with
4487 hard-float code, so people have to be careful not to mix the two.
4488 For ColdFire it was decided the ABI incompatibility is undesirable.
4489 If there is need for a hard-float ABI it is probably worth doing it
4490 properly and also passing function arguments in FP registers. */
4492 m68k_libcall_value (enum machine_mode mode)
4499 return gen_rtx_REG (mode, FP0_REG);
4504 return gen_rtx_REG (mode, D0_REG);
4508 m68k_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED)
4510 enum machine_mode mode;
4512 mode = TYPE_MODE (valtype);
4518 return gen_rtx_REG (mode, FP0_REG);
4524 /* If the function returns a pointer, push that into %a0. */
4525 if (func && POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func))))
4526 /* For compatibility with the large body of existing code which
4527 does not always properly declare external functions returning
4528 pointer types, the m68k/SVR4 convention is to copy the value
4529 returned for pointer functions from a0 to d0 in the function
4530 epilogue, so that callers that have neglected to properly
4531 declare the callee can still find the correct return value in
4533 return gen_rtx_PARALLEL
4536 gen_rtx_EXPR_LIST (VOIDmode,
4537 gen_rtx_REG (mode, A0_REG),
4539 gen_rtx_EXPR_LIST (VOIDmode,
4540 gen_rtx_REG (mode, D0_REG),
4542 else if (POINTER_TYPE_P (valtype))
4543 return gen_rtx_REG (mode, A0_REG);
4545 return gen_rtx_REG (mode, D0_REG);
4548 /* Worker function for TARGET_RETURN_IN_MEMORY. */
4549 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
4551 m68k_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4553 enum machine_mode mode = TYPE_MODE (type);
4555 if (mode == BLKmode)
4558 /* If TYPE's known alignment is less than the alignment of MODE that
4559 would contain the structure, then return in memory. We need to
4560 do so to maintain the compatibility between code compiled with
4561 -mstrict-align and that compiled with -mno-strict-align. */
4562 if (AGGREGATE_TYPE_P (type)
4563 && TYPE_ALIGN (type) < GET_MODE_ALIGNMENT (mode))
4570 /* CPU to schedule the program for. */
4571 enum attr_cpu m68k_sched_cpu;
4573 /* MAC to schedule the program for. */
4574 enum attr_mac m68k_sched_mac;
4585 /* Implicit mem reference (e.g. stack). */
4588 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
4591 /* Memory with offset but without indexing. EA mode 5. */
4594 /* Memory with indexing. EA mode 6. */
4597 /* Memory referenced by absolute address. EA mode 7. */
4600 /* Immediate operand that doesn't require extension word. */
4603 /* Immediate 16 bit operand. */
4606 /* Immediate 32 bit operand. */
4610 /* True if current insn doesn't have complete pipeline description. */
4611 static bool sched_guess_p;
4613 /* Return type of memory ADDR_RTX refers to. */
4614 static enum attr_op_type
4615 sched_address_type (enum machine_mode mode, rtx addr_rtx)
4617 struct m68k_address address;
4619 if (!m68k_decompose_address (mode, addr_rtx,
4620 reload_completed, &address))
4622 gcc_assert (sched_guess_p);
4623 /* Reload will likely fix the address to be in the register. */
4624 return OP_TYPE_MEM234;
4627 if (address.scale != 0)
4628 return OP_TYPE_MEM6;
4630 if (address.base != NULL_RTX)
4632 if (address.offset == NULL_RTX)
4633 return OP_TYPE_MEM234;
4635 return OP_TYPE_MEM5;
4638 gcc_assert (address.offset != NULL_RTX);
4640 return OP_TYPE_MEM7;
4643 /* Return type of the operand OP.
4644 If ADDRESS_P is true, return type of memory location OP refers to. */
4645 static enum attr_op_type
4646 sched_operand_type (rtx op, bool address_p)
4648 gcc_assert (op != NULL_RTX);
4651 return sched_address_type (QImode, op);
4653 if (memory_operand (op, VOIDmode))
4654 return sched_address_type (GET_MODE (op), XEXP (op, 0));
4656 if (register_operand (op, VOIDmode))
4659 if (GET_CODE (op) == CONST_INT)
4661 /* ??? Below condition should probably check if the operation is
4662 signed or unsigned. */
4663 if (IN_RANGE (INTVAL (op), -0x8000, 0x7fff))
4664 return OP_TYPE_IMM_W;
4666 return OP_TYPE_IMM_L;
4669 if (GET_CODE (op) == CONST_DOUBLE)
4671 switch (GET_MODE (op))
4674 return OP_TYPE_IMM_W;
4678 return OP_TYPE_IMM_L;
4685 if (symbolic_operand (op, VOIDmode)
4688 switch (GET_MODE (op))
4691 return OP_TYPE_IMM_Q;
4694 return OP_TYPE_IMM_W;
4697 return OP_TYPE_IMM_L;
4700 if (GET_CODE (op) == SYMBOL_REF)
4701 /* ??? Just a guess. Probably we can guess better using length
4702 attribute of the instructions. */
4703 return OP_TYPE_IMM_W;
4705 return OP_TYPE_IMM_L;
4709 gcc_assert (sched_guess_p);
4714 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
4715 If ADDRESS_P is true, return type of memory location operand refers to. */
4716 static enum attr_op_type
4717 sched_attr_op_type (rtx insn, bool opx_p, bool address_p)
4721 extract_constrain_insn_cached (insn);
4724 i = get_attr_opx (insn);
4726 i = get_attr_opy (insn);
4728 if (i >= recog_data.n_operands)
4730 gcc_assert (sched_guess_p);
4734 return sched_operand_type (recog_data.operand[i], address_p);
4737 /* Implement opx_type attribute.
4738 Return type of INSN's operand X.
4739 If ADDRESS_P is true, return type of memory location operand refers to. */
4741 m68k_sched_attr_opx_type (rtx insn, int address_p)
4743 sched_guess_p = (get_attr_guess (insn) == GUESS_YES);
4745 switch (sched_attr_op_type (insn, true, address_p != 0))
4748 return OPX_TYPE_REG;
4751 return OPX_TYPE_MEM1;
4753 case OP_TYPE_MEM234:
4754 return OPX_TYPE_MEM234;
4757 return OPX_TYPE_MEM5;
4760 return OPX_TYPE_MEM6;
4763 return OPX_TYPE_MEM7;
4766 return OPX_TYPE_IMM_Q;
4769 return OPX_TYPE_IMM_W;
4772 return OPX_TYPE_IMM_L;
4780 /* Implement opy_type attribute.
4781 Return type of INSN's operand Y.
4782 If ADDRESS_P is true, return type of memory location operand refers to. */
4784 m68k_sched_attr_opy_type (rtx insn, int address_p)
4786 sched_guess_p = (get_attr_guess (insn) == GUESS_YES);
4788 switch (sched_attr_op_type (insn, false, address_p != 0))
4791 return OPY_TYPE_REG;
4794 return OPY_TYPE_MEM1;
4796 case OP_TYPE_MEM234:
4797 return OPY_TYPE_MEM234;
4800 return OPY_TYPE_MEM5;
4803 return OPY_TYPE_MEM6;
4806 return OPY_TYPE_MEM7;
4809 return OPY_TYPE_IMM_Q;
4812 return OPY_TYPE_IMM_W;
4815 return OPY_TYPE_IMM_L;
4823 /* Return the size of INSN. */
4825 m68k_sched_attr_size (rtx insn)
4829 sched_guess_p = (get_attr_guess (insn) == GUESS_YES);
4831 switch (get_attr_type1 (insn))
4842 switch (get_attr_opx_type (insn))
4847 case OPX_TYPE_MEM234:
4848 case OPY_TYPE_IMM_Q:
4853 /* Here we assume that most absolute references are short. */
4855 case OPY_TYPE_IMM_W:
4859 case OPY_TYPE_IMM_L:
4867 switch (get_attr_opy_type (insn))
4872 case OPY_TYPE_MEM234:
4873 case OPY_TYPE_IMM_Q:
4878 /* Here we assume that most absolute references are short. */
4880 case OPY_TYPE_IMM_W:
4884 case OPY_TYPE_IMM_L:
4894 gcc_assert (sched_guess_p);
4902 /* Implement op_mem attribute. */
4904 m68k_sched_attr_op_mem (rtx insn)
4906 enum attr_opy_mem opy;
4907 enum attr_opx_mem opx;
4909 sched_guess_p = (get_attr_guess (insn) == GUESS_YES);
4911 opy = get_attr_opy_mem (insn);
4912 opx = get_attr_opx_mem (insn);
4914 if (opy == OPY_MEM_R && opx == OPX_MEM_R)
4917 if (opy == OPY_MEM_R && opx == OPX_MEM_M)
4919 switch (get_attr_opx_access (insn))
4931 gcc_assert (sched_guess_p);
4932 return OP_MEM_UNKNOWN;
4936 if (opy == OPY_MEM_R && opx == OPX_MEM_I)
4938 switch (get_attr_opx_access (insn))
4950 gcc_assert (sched_guess_p);
4951 return OP_MEM_UNKNOWN;
4955 if (opy == OPY_MEM_M && opx == OPX_MEM_R)
4958 if (opy == OPY_MEM_M && opx == OPX_MEM_M)
4960 switch (get_attr_opx_access (insn))
4966 gcc_assert (sched_guess_p);
4967 return OP_MEM_UNKNOWN;
4971 if (opy == OPY_MEM_M && opx == OPX_MEM_I)
4973 switch (get_attr_opx_access (insn))
4979 gcc_assert (sched_guess_p);
4980 return OP_MEM_UNKNOWN;
4984 if (opy == OPY_MEM_I && opx == OPX_MEM_R)
4988 if (opy == OPY_MEM_I && opx == OPX_MEM_M)
4990 switch (get_attr_opx_access (insn))
4996 gcc_assert (sched_guess_p);
4997 return OP_MEM_UNKNOWN;
5001 gcc_assert (sched_guess_p);
5002 return OP_MEM_UNKNOWN;
5005 /* Jump instructions types. Indexed by INSN_UID.
5006 The same rtl insn can be expanded into different asm instructions
5007 depending on the cc0_status. To properly determine type of jump
5008 instructions we scan instruction stream and map jumps types to this
5010 static enum attr_type *sched_branch_type;
5012 /* Return the type of the jump insn. */
5014 m68k_sched_branch_type (rtx insn)
5016 enum attr_type type;
5018 type = sched_branch_type[INSN_UID (insn)];
5020 gcc_assert (type != 0);
5025 /* Implement type2 attribute. */
5027 m68k_sched_attr_type2 (rtx insn)
5029 switch (get_attr_type1 (insn))
5036 case TYPE1_ALU_REG1:
5037 case TYPE1_ALU_REGX:
5038 return TYPE2_ALU_REG;
5061 switch (m68k_sched_cpu)
5071 gcc_assert (get_attr_guess (insn) == GUESS_YES);
5072 return TYPE2_UNKNOWN;
5095 gcc_assert (get_attr_guess (insn) == GUESS_YES);
5096 return TYPE2_UNKNOWN;
5100 /* An empty state that is used in m68k_sched_adjust_cost. */
5101 static state_t sched_adjust_cost_state;
5103 /* Implement adjust_cost scheduler hook.
5104 Return adjusted COST of dependency LINK between DEF_INSN and INSN. */
5106 m68k_sched_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx def_insn,
5111 if (recog_memoized (def_insn) < 0
5112 || recog_memoized (insn) < 0)
5115 /* Don't try to issue INSN earlier than DFA permits.
5116 This is especially useful for instructions that write to memory,
5117 as their true dependence (default) latency is better to be set to 0
5118 to workaround alias analysis limitations.
5119 This is, in fact, a machine independent tweak, so, probably,
5120 it should be moved to haifa-sched.c: insn_cost (). */
5122 delay = min_insn_conflict_delay (sched_adjust_cost_state, def_insn, insn);
5129 /* Maximal length of instruction for current CPU.
5130 E.g. it is 3 for any ColdFire core. */
5131 static int max_insn_size;
5133 /* Data to model instruction buffer of CPU. */
5136 /* Size of the instruction buffer in words. */
5139 /* Number of filled words in the instruction buffer. */
5142 /* Additional information about instruction buffer for CPUs that have
5143 a buffer of instruction records, rather then a plain buffer
5144 of instruction words. */
5145 struct _sched_ib_records
5147 /* Size of buffer in records. */
5150 /* Array to hold data on adjustements made to the size of the buffer. */
5153 /* Index of the above array. */
5157 /* An insn that reserves (marks empty) one word in the instruction buffer. */
5161 static struct _sched_ib sched_ib;
5163 /* ID of memory unit. */
5164 static int sched_mem_unit_code;
5166 /* Implementation of the targetm.sched.variable_issue () hook.
5167 It is called after INSN was issued. It returns the number of insns
5168 that can possibly get scheduled on the current cycle.
5169 It is used here to determine the effect of INSN on the instruction
5172 m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED,
5173 int sched_verbose ATTRIBUTE_UNUSED,
5174 rtx insn, int can_issue_more)
5178 if (recog_memoized (insn) >= 0)
5180 switch (m68k_sched_cpu)
5184 insn_size = get_attr_size (insn);
5188 insn_size = get_attr_size (insn);
5190 /* ColdFire V3 and V4 cores have instruction buffers that can
5191 accumulate up to 8 instructions regardless of instructions'
5192 sizes. So we should take care not to "prefetch" 24 one-word
5193 or 12 two-words instructions.
5194 To model this behavior we temporarily decrease size of the
5195 buffer by (max_insn_size - insn_size) for next 7 instructions. */
5199 adjust = max_insn_size - insn_size;
5200 sched_ib.size -= adjust;
5202 if (sched_ib.filled > sched_ib.size)
5203 sched_ib.filled = sched_ib.size;
5205 sched_ib.records.adjust[sched_ib.records.adjust_index] = adjust;
5208 ++sched_ib.records.adjust_index;
5209 if (sched_ib.records.adjust_index == sched_ib.records.n_insns)
5210 sched_ib.records.adjust_index = 0;
5212 /* Undo adjustement we did 7 instructions ago. */
5214 += sched_ib.records.adjust[sched_ib.records.adjust_index];
5222 gcc_assert (insn_size <= sched_ib.filled);
5225 else if (GET_CODE (PATTERN (insn)) == ASM_INPUT
5226 || asm_noperands (PATTERN (insn)) >= 0)
5227 insn_size = sched_ib.filled;
5231 sched_ib.filled -= insn_size;
5233 return can_issue_more;
5236 /* Statistics gatherer. */
5240 /* Something needs to be done for this insn. */
5243 /* Support for this insn is complete. */
5246 /* This insn didn't require much effort to support it. */
5248 } sched_dump_class_def;
5250 /* Pointer to functions that classifies insns into 3 above classes. */
5251 typedef sched_dump_class_def (*sched_dump_class_func_t) (rtx);
5253 /* Return statistical type of INSN regarding splits. */
5254 static sched_dump_class_def
5255 sched_dump_split_class (rtx insn)
5259 i = recog_memoized (insn);
5260 gcc_assert (i >= 0);
5262 switch (get_attr_split (insn))
5265 return SCHED_DUMP_TODO;
5268 return SCHED_DUMP_DONE;
5271 return SCHED_DUMP_NOTHING;
5278 /* ID of the guess unit. */
5279 static int sched_dump_dfa_guess_unit_code;
5281 /* DFA state for use in sched_dump_dfa_class (). */
5282 static state_t sched_dump_dfa_state;
5284 /* Return statistical type of INSN regarding DFA reservations. */
5285 static sched_dump_class_def
5286 sched_dump_dfa_class (rtx insn)
5290 i = recog_memoized (insn);
5291 gcc_assert (i >= 0 && insn_has_dfa_reservation_p (insn));
5293 if (sched_dump_split_class (insn) == SCHED_DUMP_TODO)
5294 /* Insn is not yet ready for reservations. */
5295 return SCHED_DUMP_NOTHING;
5297 state_reset (sched_dump_dfa_state);
5299 if (state_transition (sched_dump_dfa_state, insn) >= 0)
5302 if (cpu_unit_reservation_p (sched_dump_dfa_state,
5303 sched_dump_dfa_guess_unit_code))
5304 return SCHED_DUMP_TODO;
5306 return SCHED_DUMP_DONE;
5309 /* Dump statistics on current function into file DUMP_FILENAME and prefix
5310 each entry with PREFIX.
5311 Instructions are classified with DUMP_CLASS. */
5313 m68k_sched_dump (sched_dump_class_func_t dump_class,
5314 const char *prefix, FILE *dump)
5322 gcc_assert (dump != NULL);
5324 present = sbitmap_alloc (CODE_FOR_nothing);
5325 sbitmap_zero (present);
5327 todos = xcalloc (CODE_FOR_nothing, sizeof (*todos));
5328 dones = xcalloc (CODE_FOR_nothing, sizeof (*dones));
5329 nothings = xcalloc (CODE_FOR_nothing, sizeof (*nothings));
5331 /* Gather statistics. */
5332 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
5334 if (INSN_P (insn) && recog_memoized (insn) >= 0)
5336 enum insn_code code;
5338 code = INSN_CODE (insn);
5339 gcc_assert (code < CODE_FOR_nothing);
5341 SET_BIT (present, code);
5343 switch (dump_class (insn))
5345 case SCHED_DUMP_TODO:
5349 case SCHED_DUMP_DONE:
5353 case SCHED_DUMP_NOTHING:
5360 /* Print statisctics. */
5363 sbitmap_iterator si;
5372 EXECUTE_IF_SET_IN_SBITMAP (present, 0, i, si)
5377 enum insn_code code;
5379 code = (enum insn_code) i;
5383 nothing = nothings[code];
5387 total_nothing += nothing;
5392 "%s: %3d: %d / %d / %d ;",
5393 prefix, code, todo, done, nothing);
5398 name = get_insn_name (code);
5401 fprintf (dump, " {%s}\n", name);
5403 fprintf (dump, " {unknown}\n");
5408 gcc_assert (CODE_FOR_nothing < 999);
5411 "%s: 999: %d / %d / %d ; {total}\n",
5412 prefix, total_todo, total_done, total_nothing);
5422 sbitmap_free (present);
5426 /* Implementation of targetm.sched.md_init_global () hook.
5427 It is invoked once per scheduling pass and is used here
5428 to initialize scheduler constants. */
5430 m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED,
5431 int sched_verbose ATTRIBUTE_UNUSED,
5432 int n_insns ATTRIBUTE_UNUSED)
5434 /* Init branch types. */
5438 sched_branch_type = xcalloc (get_max_uid () + 1,
5439 sizeof (*sched_branch_type));
5441 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
5444 /* !!! FIXME: Implement real scan here. */
5445 sched_branch_type[INSN_UID (insn)] = TYPE_BCC;
5449 if (reload_completed && sched_verbose >= 8)
5450 /* Dump statistics. */
5452 m68k_sched_dump (sched_dump_split_class, "m68k_sched_split",
5455 sched_dump_dfa_guess_unit_code = get_cpu_unit_code ("cf_guess");
5456 sched_dump_dfa_state = alloca (state_size ());
5458 m68k_sched_dump (sched_dump_dfa_class, "m68k_sched_dfa",
5461 sched_dump_dfa_state = NULL;
5462 sched_dump_dfa_guess_unit_code = 0;
5465 /* Setup target cpu. */
5466 switch (m68k_sched_cpu)
5471 sched_ib.records.n_insns = 0;
5472 sched_ib.records.adjust = NULL;
5477 sched_ib.records.n_insns = 8;
5478 sched_ib.records.adjust = xmalloc (sched_ib.records.n_insns
5479 * sizeof (*sched_ib.records.adjust));
5486 sched_mem_unit_code = get_cpu_unit_code ("cf_mem1");
5488 sched_adjust_cost_state = xmalloc (state_size ());
5489 state_reset (sched_adjust_cost_state);
5492 emit_insn (gen_ib ());
5493 sched_ib.insn = get_insns ();
5497 /* Scheduling pass is now finished. Free/reset static variables. */
5499 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
5500 int verbose ATTRIBUTE_UNUSED)
5502 sched_ib.insn = NULL;
5504 free (sched_adjust_cost_state);
5505 sched_adjust_cost_state = NULL;
5507 sched_mem_unit_code = 0;
5509 free (sched_ib.records.adjust);
5510 sched_ib.records.adjust = NULL;
5511 sched_ib.records.n_insns = 0;
5514 free (sched_branch_type);
5515 sched_branch_type = NULL;
5518 /* Implementation of targetm.sched.md_init () hook.
5519 It is invoked each time scheduler starts on the new block (basic block or
5520 extended basic block). */
5522 m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED,
5523 int sched_verbose ATTRIBUTE_UNUSED,
5524 int n_insns ATTRIBUTE_UNUSED)
5526 switch (m68k_sched_cpu)
5534 sched_ib.size = sched_ib.records.n_insns * max_insn_size;
5536 memset (sched_ib.records.adjust, 0,
5537 sched_ib.records.n_insns * sizeof (*sched_ib.records.adjust));
5538 sched_ib.records.adjust_index = 0;
5545 /* haifa-sched.c: schedule_block () calls advance_cycle () just before
5546 the first cycle. Workaround that. */
5547 sched_ib.filled = -2;
5550 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
5551 It is invoked just before current cycle finishes and is used here
5552 to track if instruction buffer got its two words this cycle. */
5554 m68k_sched_dfa_pre_advance_cycle (void)
5556 if (!cpu_unit_reservation_p (curr_state, sched_mem_unit_code))
5558 sched_ib.filled += 2;
5560 if (sched_ib.filled > sched_ib.size)
5561 sched_ib.filled = sched_ib.size;
5565 /* Implementation of targetm.sched.dfa_post_advance_cycle () hook.
5566 It is invoked just after new cycle begins and is used here
5567 to setup number of filled words in the instruction buffer so that
5568 instructions which won't have all their words prefetched would be
5569 stalled for a cycle. */
5571 m68k_sched_dfa_post_advance_cycle (void)
5575 /* Setup number of prefetched instruction words in the instruction
5577 i = max_insn_size - sched_ib.filled;
5581 if (state_transition (curr_state, sched_ib.insn) >= 0)