1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
36 #include "diagnostic-core.h"
42 #include "target-def.h"
46 /* ??? Need to add a dependency between m68k.o and sched-int.h. */
47 #include "sched-int.h"
48 #include "insn-codes.h"
51 enum reg_class regno_reg_class[] =
53 DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS,
54 DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS,
55 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
56 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
57 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
58 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
63 /* The minimum number of integer registers that we want to save with the
64 movem instruction. Using two movel instructions instead of a single
65 moveml is about 15% faster for the 68020 and 68030 at no expense in
67 #define MIN_MOVEM_REGS 3
69 /* The minimum number of floating point registers that we want to save
70 with the fmovem instruction. */
71 #define MIN_FMOVEM_REGS 1
73 /* Structure describing stack frame layout. */
76 /* Stack pointer to frame pointer offset. */
79 /* Offset of FPU registers. */
80 HOST_WIDE_INT foffset;
82 /* Frame size in bytes (rounded up). */
85 /* Data and address register. */
87 unsigned int reg_mask;
91 unsigned int fpu_mask;
93 /* Offsets relative to ARG_POINTER. */
94 HOST_WIDE_INT frame_pointer_offset;
95 HOST_WIDE_INT stack_pointer_offset;
97 /* Function which the above information refers to. */
101 /* Current frame information calculated by m68k_compute_frame_layout(). */
102 static struct m68k_frame current_frame;
104 /* Structure describing an m68k address.
106 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
107 with null fields evaluating to 0. Here:
109 - BASE satisfies m68k_legitimate_base_reg_p
110 - INDEX satisfies m68k_legitimate_index_reg_p
111 - OFFSET satisfies m68k_legitimate_constant_address_p
113 INDEX is either HImode or SImode. The other fields are SImode.
115 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
116 the address is (BASE)+. */
117 struct m68k_address {
125 static int m68k_sched_adjust_cost (rtx, rtx, rtx, int);
126 static int m68k_sched_issue_rate (void);
127 static int m68k_sched_variable_issue (FILE *, int, rtx, int);
128 static void m68k_sched_md_init_global (FILE *, int, int);
129 static void m68k_sched_md_finish_global (FILE *, int);
130 static void m68k_sched_md_init (FILE *, int, int);
131 static void m68k_sched_dfa_pre_advance_cycle (void);
132 static void m68k_sched_dfa_post_advance_cycle (void);
133 static int m68k_sched_first_cycle_multipass_dfa_lookahead (void);
135 static bool m68k_can_eliminate (const int, const int);
136 static bool m68k_legitimate_address_p (enum machine_mode, rtx, bool);
137 static bool m68k_handle_option (size_t, const char *, int);
138 static void m68k_option_override (void);
139 static rtx find_addr_reg (rtx);
140 static const char *singlemove_string (rtx *);
141 static void m68k_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
142 HOST_WIDE_INT, tree);
143 static rtx m68k_struct_value_rtx (tree, int);
144 static tree m68k_handle_fndecl_attribute (tree *node, tree name,
145 tree args, int flags,
147 static void m68k_compute_frame_layout (void);
148 static bool m68k_save_reg (unsigned int regno, bool interrupt_handler);
149 static bool m68k_ok_for_sibcall_p (tree, tree);
150 static bool m68k_tls_symbol_p (rtx);
151 static rtx m68k_legitimize_address (rtx, rtx, enum machine_mode);
152 static bool m68k_rtx_costs (rtx, int, int, int *, bool);
153 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
154 static bool m68k_return_in_memory (const_tree, const_tree);
156 static void m68k_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
157 static void m68k_trampoline_init (rtx, tree, rtx);
158 static int m68k_return_pops_args (tree, tree, int);
159 static rtx m68k_delegitimize_address (rtx);
162 /* Specify the identification number of the library being built */
163 const char *m68k_library_id_string = "_current_shared_library_a5_offset_";
165 /* Initialize the GCC target structure. */
167 #if INT_OP_GROUP == INT_OP_DOT_WORD
168 #undef TARGET_ASM_ALIGNED_HI_OP
169 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
172 #if INT_OP_GROUP == INT_OP_NO_DOT
173 #undef TARGET_ASM_BYTE_OP
174 #define TARGET_ASM_BYTE_OP "\tbyte\t"
175 #undef TARGET_ASM_ALIGNED_HI_OP
176 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
177 #undef TARGET_ASM_ALIGNED_SI_OP
178 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
181 #if INT_OP_GROUP == INT_OP_DC
182 #undef TARGET_ASM_BYTE_OP
183 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
184 #undef TARGET_ASM_ALIGNED_HI_OP
185 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
186 #undef TARGET_ASM_ALIGNED_SI_OP
187 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
190 #undef TARGET_ASM_UNALIGNED_HI_OP
191 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
192 #undef TARGET_ASM_UNALIGNED_SI_OP
193 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
195 #undef TARGET_ASM_OUTPUT_MI_THUNK
196 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
197 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
198 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
200 #undef TARGET_ASM_FILE_START_APP_OFF
201 #define TARGET_ASM_FILE_START_APP_OFF true
203 #undef TARGET_LEGITIMIZE_ADDRESS
204 #define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address
206 #undef TARGET_SCHED_ADJUST_COST
207 #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost
209 #undef TARGET_SCHED_ISSUE_RATE
210 #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate
212 #undef TARGET_SCHED_VARIABLE_ISSUE
213 #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue
215 #undef TARGET_SCHED_INIT_GLOBAL
216 #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global
218 #undef TARGET_SCHED_FINISH_GLOBAL
219 #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global
221 #undef TARGET_SCHED_INIT
222 #define TARGET_SCHED_INIT m68k_sched_md_init
224 #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE
225 #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle
227 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
228 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle
230 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
231 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
232 m68k_sched_first_cycle_multipass_dfa_lookahead
234 #undef TARGET_HANDLE_OPTION
235 #define TARGET_HANDLE_OPTION m68k_handle_option
237 #undef TARGET_OPTION_OVERRIDE
238 #define TARGET_OPTION_OVERRIDE m68k_option_override
240 #undef TARGET_RTX_COSTS
241 #define TARGET_RTX_COSTS m68k_rtx_costs
243 #undef TARGET_ATTRIBUTE_TABLE
244 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
246 #undef TARGET_PROMOTE_PROTOTYPES
247 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
249 #undef TARGET_STRUCT_VALUE_RTX
250 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
252 #undef TARGET_CANNOT_FORCE_CONST_MEM
253 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_illegitimate_symbolic_constant_p
255 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
256 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
258 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
259 #undef TARGET_RETURN_IN_MEMORY
260 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
264 #undef TARGET_HAVE_TLS
265 #define TARGET_HAVE_TLS (true)
267 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
268 #define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel
271 #undef TARGET_LEGITIMATE_ADDRESS_P
272 #define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p
274 #undef TARGET_CAN_ELIMINATE
275 #define TARGET_CAN_ELIMINATE m68k_can_eliminate
277 #undef TARGET_TRAMPOLINE_INIT
278 #define TARGET_TRAMPOLINE_INIT m68k_trampoline_init
280 #undef TARGET_RETURN_POPS_ARGS
281 #define TARGET_RETURN_POPS_ARGS m68k_return_pops_args
283 #undef TARGET_DELEGITIMIZE_ADDRESS
284 #define TARGET_DELEGITIMIZE_ADDRESS m68k_delegitimize_address
286 static const struct attribute_spec m68k_attribute_table[] =
288 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
289 { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute },
290 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute },
291 { "interrupt_thread", 0, 0, true, false, false, m68k_handle_fndecl_attribute },
292 { NULL, 0, 0, false, false, false, NULL }
295 struct gcc_target targetm = TARGET_INITIALIZER;
297 /* Base flags for 68k ISAs. */
298 #define FL_FOR_isa_00 FL_ISA_68000
299 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
300 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
301 generated 68881 code for 68020 and 68030 targets unless explicitly told
303 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
304 | FL_BITFIELD | FL_68881)
305 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
306 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
308 /* Base flags for ColdFire ISAs. */
309 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
310 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
311 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
312 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
313 /* ISA_C is not upwardly compatible with ISA_B. */
314 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
318 /* Traditional 68000 instruction sets. */
324 /* ColdFire instruction set variants. */
332 /* Information about one of the -march, -mcpu or -mtune arguments. */
333 struct m68k_target_selection
335 /* The argument being described. */
338 /* For -mcpu, this is the device selected by the option.
339 For -mtune and -march, it is a representative device
340 for the microarchitecture or ISA respectively. */
341 enum target_device device;
343 /* The M68K_DEVICE fields associated with DEVICE. See the comment
344 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
346 enum uarch_type microarch;
351 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
352 static const struct m68k_target_selection all_devices[] =
354 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
355 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
356 #include "m68k-devices.def"
358 { NULL, unk_device, NULL, unk_arch, isa_max, 0 }
361 /* A list of all ISAs, mapping each one to a representative device.
362 Used for -march selection. */
363 static const struct m68k_target_selection all_isas[] =
365 { "68000", m68000, NULL, u68000, isa_00, FL_FOR_isa_00 },
366 { "68010", m68010, NULL, u68010, isa_10, FL_FOR_isa_10 },
367 { "68020", m68020, NULL, u68020, isa_20, FL_FOR_isa_20 },
368 { "68030", m68030, NULL, u68030, isa_20, FL_FOR_isa_20 },
369 { "68040", m68040, NULL, u68040, isa_40, FL_FOR_isa_40 },
370 { "68060", m68060, NULL, u68060, isa_40, FL_FOR_isa_40 },
371 { "cpu32", cpu32, NULL, ucpu32, isa_20, FL_FOR_isa_cpu32 },
372 { "isaa", mcf5206e, NULL, ucfv2, isa_a, (FL_FOR_isa_a
374 { "isaaplus", mcf5271, NULL, ucfv2, isa_aplus, (FL_FOR_isa_aplus
376 { "isab", mcf5407, NULL, ucfv4, isa_b, FL_FOR_isa_b },
377 { "isac", unk_device, NULL, ucfv4, isa_c, (FL_FOR_isa_c
379 { NULL, unk_device, NULL, unk_arch, isa_max, 0 }
382 /* A list of all microarchitectures, mapping each one to a representative
383 device. Used for -mtune selection. */
384 static const struct m68k_target_selection all_microarchs[] =
386 { "68000", m68000, NULL, u68000, isa_00, FL_FOR_isa_00 },
387 { "68010", m68010, NULL, u68010, isa_10, FL_FOR_isa_10 },
388 { "68020", m68020, NULL, u68020, isa_20, FL_FOR_isa_20 },
389 { "68020-40", m68020, NULL, u68020_40, isa_20, FL_FOR_isa_20 },
390 { "68020-60", m68020, NULL, u68020_60, isa_20, FL_FOR_isa_20 },
391 { "68030", m68030, NULL, u68030, isa_20, FL_FOR_isa_20 },
392 { "68040", m68040, NULL, u68040, isa_40, FL_FOR_isa_40 },
393 { "68060", m68060, NULL, u68060, isa_40, FL_FOR_isa_40 },
394 { "cpu32", cpu32, NULL, ucpu32, isa_20, FL_FOR_isa_cpu32 },
395 { "cfv1", mcf51qe, NULL, ucfv1, isa_c, FL_FOR_isa_c },
396 { "cfv2", mcf5206, NULL, ucfv2, isa_a, FL_FOR_isa_a },
397 { "cfv3", mcf5307, NULL, ucfv3, isa_a, (FL_FOR_isa_a
399 { "cfv4", mcf5407, NULL, ucfv4, isa_b, FL_FOR_isa_b },
400 { "cfv4e", mcf547x, NULL, ucfv4e, isa_b, (FL_FOR_isa_b
404 { NULL, unk_device, NULL, unk_arch, isa_max, 0 }
407 /* The entries associated with the -mcpu, -march and -mtune settings,
408 or null for options that have not been used. */
409 const struct m68k_target_selection *m68k_cpu_entry;
410 const struct m68k_target_selection *m68k_arch_entry;
411 const struct m68k_target_selection *m68k_tune_entry;
413 /* Which CPU we are generating code for. */
414 enum target_device m68k_cpu;
416 /* Which microarchitecture to tune for. */
417 enum uarch_type m68k_tune;
419 /* Which FPU to use. */
420 enum fpu_type m68k_fpu;
422 /* The set of FL_* flags that apply to the target processor. */
423 unsigned int m68k_cpu_flags;
425 /* The set of FL_* flags that apply to the processor to be tuned for. */
426 unsigned int m68k_tune_flags;
428 /* Asm templates for calling or jumping to an arbitrary symbolic address,
429 or NULL if such calls or jumps are not supported. The address is held
431 const char *m68k_symbolic_call;
432 const char *m68k_symbolic_jump;
434 /* Enum variable that corresponds to m68k_symbolic_call values. */
435 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var;
438 /* See whether TABLE has an entry with name NAME. Return true and
439 store the entry in *ENTRY if so, otherwise return false and
440 leave *ENTRY alone. */
443 m68k_find_selection (const struct m68k_target_selection **entry,
444 const struct m68k_target_selection *table,
449 for (i = 0; table[i].name; i++)
450 if (strcmp (table[i].name, name) == 0)
458 /* Implement TARGET_HANDLE_OPTION. */
461 m68k_handle_option (size_t code, const char *arg, int value)
466 return m68k_find_selection (&m68k_arch_entry, all_isas, arg);
469 return m68k_find_selection (&m68k_cpu_entry, all_devices, arg);
472 return m68k_find_selection (&m68k_tune_entry, all_microarchs, arg);
475 return m68k_find_selection (&m68k_cpu_entry, all_devices, "5206");
478 return m68k_find_selection (&m68k_cpu_entry, all_devices, "5206e");
481 return m68k_find_selection (&m68k_cpu_entry, all_devices, "528x");
484 return m68k_find_selection (&m68k_cpu_entry, all_devices, "5307");
487 return m68k_find_selection (&m68k_cpu_entry, all_devices, "5407");
490 return m68k_find_selection (&m68k_cpu_entry, all_devices, "547x");
494 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68000");
497 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68010");
501 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68020");
504 return (m68k_find_selection (&m68k_tune_entry, all_microarchs,
506 && m68k_find_selection (&m68k_cpu_entry, all_devices, "68020"));
509 return (m68k_find_selection (&m68k_tune_entry, all_microarchs,
511 && m68k_find_selection (&m68k_cpu_entry, all_devices, "68020"));
514 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68030");
517 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68040");
520 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68060");
523 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68302");
527 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68332");
529 case OPT_mshared_library_id_:
530 if (value > MAX_LIBRARY_ID)
531 error ("-mshared-library-id=%s is not between 0 and %d",
532 arg, MAX_LIBRARY_ID);
536 asprintf (&tmp, "%d", (value * -4) - 4);
537 m68k_library_id_string = tmp;
546 /* Implement TARGET_OPTION_OVERRIDE. */
549 m68k_option_override (void)
551 const struct m68k_target_selection *entry;
552 unsigned long target_mask;
560 -march=ARCH should generate code that runs any processor
561 implementing architecture ARCH. -mcpu=CPU should override -march
562 and should generate code that runs on processor CPU, making free
563 use of any instructions that CPU understands. -mtune=UARCH applies
564 on top of -mcpu or -march and optimizes the code for UARCH. It does
565 not change the target architecture. */
568 /* Complain if the -march setting is for a different microarchitecture,
569 or includes flags that the -mcpu setting doesn't. */
571 && (m68k_arch_entry->microarch != m68k_cpu_entry->microarch
572 || (m68k_arch_entry->flags & ~m68k_cpu_entry->flags) != 0))
573 warning (0, "-mcpu=%s conflicts with -march=%s",
574 m68k_cpu_entry->name, m68k_arch_entry->name);
576 entry = m68k_cpu_entry;
579 entry = m68k_arch_entry;
582 entry = all_devices + TARGET_CPU_DEFAULT;
584 m68k_cpu_flags = entry->flags;
586 /* Use the architecture setting to derive default values for
590 /* ColdFire is lenient about alignment. */
591 if (!TARGET_COLDFIRE)
592 target_mask |= MASK_STRICT_ALIGNMENT;
594 if ((m68k_cpu_flags & FL_BITFIELD) != 0)
595 target_mask |= MASK_BITFIELD;
596 if ((m68k_cpu_flags & FL_CF_HWDIV) != 0)
597 target_mask |= MASK_CF_HWDIV;
598 if ((m68k_cpu_flags & (FL_68881 | FL_CF_FPU)) != 0)
599 target_mask |= MASK_HARD_FLOAT;
600 target_flags |= target_mask & ~target_flags_explicit;
602 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
603 m68k_cpu = entry->device;
606 m68k_tune = m68k_tune_entry->microarch;
607 m68k_tune_flags = m68k_tune_entry->flags;
609 #ifdef M68K_DEFAULT_TUNE
610 else if (!m68k_cpu_entry && !m68k_arch_entry)
612 enum target_device dev;
613 dev = all_microarchs[M68K_DEFAULT_TUNE].device;
614 m68k_tune_flags = all_devices[dev]->flags;
619 m68k_tune = entry->microarch;
620 m68k_tune_flags = entry->flags;
623 /* Set the type of FPU. */
624 m68k_fpu = (!TARGET_HARD_FLOAT ? FPUTYPE_NONE
625 : (m68k_cpu_flags & FL_COLDFIRE) != 0 ? FPUTYPE_COLDFIRE
628 /* Sanity check to ensure that msep-data and mid-sahred-library are not
629 * both specified together. Doing so simply doesn't make sense.
631 if (TARGET_SEP_DATA && TARGET_ID_SHARED_LIBRARY)
632 error ("cannot specify both -msep-data and -mid-shared-library");
634 /* If we're generating code for a separate A5 relative data segment,
635 * we've got to enable -fPIC as well. This might be relaxable to
636 * -fpic but it hasn't been tested properly.
638 if (TARGET_SEP_DATA || TARGET_ID_SHARED_LIBRARY)
641 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
642 error if the target does not support them. */
643 if (TARGET_PCREL && !TARGET_68020 && flag_pic == 2)
644 error ("-mpcrel -fPIC is not currently supported on selected cpu");
646 /* ??? A historic way of turning on pic, or is this intended to
647 be an embedded thing that doesn't have the same name binding
648 significance that it does on hosted ELF systems? */
649 if (TARGET_PCREL && flag_pic == 0)
654 m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_JSR;
656 m68k_symbolic_jump = "jra %a0";
658 else if (TARGET_ID_SHARED_LIBRARY)
659 /* All addresses must be loaded from the GOT. */
661 else if (TARGET_68020 || TARGET_ISAB || TARGET_ISAC)
664 m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_BSR_C;
666 m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_BSR_P;
669 /* No unconditional long branch */;
670 else if (TARGET_PCREL)
671 m68k_symbolic_jump = "bra%.l %c0";
673 m68k_symbolic_jump = "bra%.l %p0";
674 /* Turn off function cse if we are doing PIC. We always want
675 function call to be done as `bsr foo@PLTPC'. */
676 /* ??? It's traditional to do this for -mpcrel too, but it isn't
677 clear how intentional that is. */
678 flag_no_function_cse = 1;
681 switch (m68k_symbolic_call_var)
683 case M68K_SYMBOLIC_CALL_JSR:
684 m68k_symbolic_call = "jsr %a0";
687 case M68K_SYMBOLIC_CALL_BSR_C:
688 m68k_symbolic_call = "bsr%.l %c0";
691 case M68K_SYMBOLIC_CALL_BSR_P:
692 m68k_symbolic_call = "bsr%.l %p0";
695 case M68K_SYMBOLIC_CALL_NONE:
696 gcc_assert (m68k_symbolic_call == NULL);
703 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP
704 if (align_labels > 2)
706 warning (0, "-falign-labels=%d is not supported", align_labels);
711 warning (0, "-falign-loops=%d is not supported", align_loops);
716 SUBTARGET_OVERRIDE_OPTIONS;
718 /* Setup scheduling options. */
720 m68k_sched_cpu = CPU_CFV1;
722 m68k_sched_cpu = CPU_CFV2;
724 m68k_sched_cpu = CPU_CFV3;
726 m68k_sched_cpu = CPU_CFV4;
729 m68k_sched_cpu = CPU_UNKNOWN;
730 flag_schedule_insns = 0;
731 flag_schedule_insns_after_reload = 0;
732 flag_modulo_sched = 0;
735 if (m68k_sched_cpu != CPU_UNKNOWN)
737 if ((m68k_cpu_flags & (FL_CF_EMAC | FL_CF_EMAC_B)) != 0)
738 m68k_sched_mac = MAC_CF_EMAC;
739 else if ((m68k_cpu_flags & FL_CF_MAC) != 0)
740 m68k_sched_mac = MAC_CF_MAC;
742 m68k_sched_mac = MAC_NO;
746 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
747 given argument and NAME is the argument passed to -mcpu. Return NULL
748 if -mcpu was not passed. */
751 m68k_cpp_cpu_ident (const char *prefix)
755 return concat ("__m", prefix, "_cpu_", m68k_cpu_entry->name, NULL);
758 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
759 given argument and NAME is the name of the representative device for
760 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
763 m68k_cpp_cpu_family (const char *prefix)
767 return concat ("__m", prefix, "_family_", m68k_cpu_entry->family, NULL);
770 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
771 "interrupt_handler" attribute and interrupt_thread if FUNC has an
772 "interrupt_thread" attribute. Otherwise, return
773 m68k_fk_normal_function. */
775 enum m68k_function_kind
776 m68k_get_function_kind (tree func)
780 gcc_assert (TREE_CODE (func) == FUNCTION_DECL);
782 a = lookup_attribute ("interrupt", DECL_ATTRIBUTES (func));
784 return m68k_fk_interrupt_handler;
786 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
788 return m68k_fk_interrupt_handler;
790 a = lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func));
792 return m68k_fk_interrupt_thread;
794 return m68k_fk_normal_function;
797 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
798 struct attribute_spec.handler. */
800 m68k_handle_fndecl_attribute (tree *node, tree name,
801 tree args ATTRIBUTE_UNUSED,
802 int flags ATTRIBUTE_UNUSED,
805 if (TREE_CODE (*node) != FUNCTION_DECL)
807 warning (OPT_Wattributes, "%qE attribute only applies to functions",
809 *no_add_attrs = true;
812 if (m68k_get_function_kind (*node) != m68k_fk_normal_function)
814 error ("multiple interrupt attributes not allowed");
815 *no_add_attrs = true;
819 && !strcmp (IDENTIFIER_POINTER (name), "interrupt_thread"))
821 error ("interrupt_thread is available only on fido");
822 *no_add_attrs = true;
829 m68k_compute_frame_layout (void)
833 enum m68k_function_kind func_kind =
834 m68k_get_function_kind (current_function_decl);
835 bool interrupt_handler = func_kind == m68k_fk_interrupt_handler;
836 bool interrupt_thread = func_kind == m68k_fk_interrupt_thread;
838 /* Only compute the frame once per function.
839 Don't cache information until reload has been completed. */
840 if (current_frame.funcdef_no == current_function_funcdef_no
844 current_frame.size = (get_frame_size () + 3) & -4;
848 /* Interrupt thread does not need to save any register. */
849 if (!interrupt_thread)
850 for (regno = 0; regno < 16; regno++)
851 if (m68k_save_reg (regno, interrupt_handler))
853 mask |= 1 << (regno - D0_REG);
856 current_frame.offset = saved * 4;
857 current_frame.reg_no = saved;
858 current_frame.reg_mask = mask;
860 current_frame.foffset = 0;
862 if (TARGET_HARD_FLOAT)
864 /* Interrupt thread does not need to save any register. */
865 if (!interrupt_thread)
866 for (regno = 16; regno < 24; regno++)
867 if (m68k_save_reg (regno, interrupt_handler))
869 mask |= 1 << (regno - FP0_REG);
872 current_frame.foffset = saved * TARGET_FP_REG_SIZE;
873 current_frame.offset += current_frame.foffset;
875 current_frame.fpu_no = saved;
876 current_frame.fpu_mask = mask;
878 /* Remember what function this frame refers to. */
879 current_frame.funcdef_no = current_function_funcdef_no;
882 /* Worker function for TARGET_CAN_ELIMINATE. */
885 m68k_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
887 return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true);
891 m68k_initial_elimination_offset (int from, int to)
894 /* The arg pointer points 8 bytes before the start of the arguments,
895 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
896 frame pointer in most frames. */
897 argptr_offset = frame_pointer_needed ? 0 : UNITS_PER_WORD;
898 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
899 return argptr_offset;
901 m68k_compute_frame_layout ();
903 gcc_assert (to == STACK_POINTER_REGNUM);
906 case ARG_POINTER_REGNUM:
907 return current_frame.offset + current_frame.size - argptr_offset;
908 case FRAME_POINTER_REGNUM:
909 return current_frame.offset + current_frame.size;
915 /* Refer to the array `regs_ever_live' to determine which registers
916 to save; `regs_ever_live[I]' is nonzero if register number I
917 is ever used in the function. This function is responsible for
918 knowing which registers should not be saved even if used.
919 Return true if we need to save REGNO. */
922 m68k_save_reg (unsigned int regno, bool interrupt_handler)
924 if (flag_pic && regno == PIC_REG)
926 if (crtl->saves_all_registers)
928 if (crtl->uses_pic_offset_table)
930 /* Reload may introduce constant pool references into a function
931 that thitherto didn't need a PIC register. Note that the test
932 above will not catch that case because we will only set
933 crtl->uses_pic_offset_table when emitting
934 the address reloads. */
935 if (crtl->uses_const_pool)
939 if (crtl->calls_eh_return)
944 unsigned int test = EH_RETURN_DATA_REGNO (i);
945 if (test == INVALID_REGNUM)
952 /* Fixed regs we never touch. */
953 if (fixed_regs[regno])
956 /* The frame pointer (if it is such) is handled specially. */
957 if (regno == FRAME_POINTER_REGNUM && frame_pointer_needed)
960 /* Interrupt handlers must also save call_used_regs
961 if they are live or when calling nested functions. */
962 if (interrupt_handler)
964 if (df_regs_ever_live_p (regno))
967 if (!current_function_is_leaf && call_used_regs[regno])
971 /* Never need to save registers that aren't touched. */
972 if (!df_regs_ever_live_p (regno))
975 /* Otherwise save everything that isn't call-clobbered. */
976 return !call_used_regs[regno];
979 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
980 the lowest memory address. COUNT is the number of registers to be
981 moved, with register REGNO + I being moved if bit I of MASK is set.
982 STORE_P specifies the direction of the move and ADJUST_STACK_P says
983 whether or not this is pre-decrement (if STORE_P) or post-increment
984 (if !STORE_P) operation. */
987 m68k_emit_movem (rtx base, HOST_WIDE_INT offset,
988 unsigned int count, unsigned int regno,
989 unsigned int mask, bool store_p, bool adjust_stack_p)
992 rtx body, addr, src, operands[2];
993 enum machine_mode mode;
995 body = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (adjust_stack_p + count));
996 mode = reg_raw_mode[regno];
1001 src = plus_constant (base, (count
1002 * GET_MODE_SIZE (mode)
1003 * (HOST_WIDE_INT) (store_p ? -1 : 1)));
1004 XVECEXP (body, 0, i++) = gen_rtx_SET (VOIDmode, base, src);
1007 for (; mask != 0; mask >>= 1, regno++)
1010 addr = plus_constant (base, offset);
1011 operands[!store_p] = gen_frame_mem (mode, addr);
1012 operands[store_p] = gen_rtx_REG (mode, regno);
1013 XVECEXP (body, 0, i++)
1014 = gen_rtx_SET (VOIDmode, operands[0], operands[1]);
1015 offset += GET_MODE_SIZE (mode);
1017 gcc_assert (i == XVECLEN (body, 0));
1019 return emit_insn (body);
1022 /* Make INSN a frame-related instruction. */
1025 m68k_set_frame_related (rtx insn)
1030 RTX_FRAME_RELATED_P (insn) = 1;
1031 body = PATTERN (insn);
1032 if (GET_CODE (body) == PARALLEL)
1033 for (i = 0; i < XVECLEN (body, 0); i++)
1034 RTX_FRAME_RELATED_P (XVECEXP (body, 0, i)) = 1;
1037 /* Emit RTL for the "prologue" define_expand. */
1040 m68k_expand_prologue (void)
1042 HOST_WIDE_INT fsize_with_regs;
1043 rtx limit, src, dest;
1045 m68k_compute_frame_layout ();
1047 /* If the stack limit is a symbol, we can check it here,
1048 before actually allocating the space. */
1049 if (crtl->limit_stack
1050 && GET_CODE (stack_limit_rtx) == SYMBOL_REF)
1052 limit = plus_constant (stack_limit_rtx, current_frame.size + 4);
1053 if (!LEGITIMATE_CONSTANT_P (limit))
1055 emit_move_insn (gen_rtx_REG (Pmode, D0_REG), limit);
1056 limit = gen_rtx_REG (Pmode, D0_REG);
1058 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode,
1059 stack_pointer_rtx, limit),
1060 stack_pointer_rtx, limit,
1064 fsize_with_regs = current_frame.size;
1065 if (TARGET_COLDFIRE)
1067 /* ColdFire's move multiple instructions do not allow pre-decrement
1068 addressing. Add the size of movem saves to the initial stack
1069 allocation instead. */
1070 if (current_frame.reg_no >= MIN_MOVEM_REGS)
1071 fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode);
1072 if (current_frame.fpu_no >= MIN_FMOVEM_REGS)
1073 fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode);
1076 if (frame_pointer_needed)
1078 if (fsize_with_regs == 0 && TUNE_68040)
1080 /* On the 68040, two separate moves are faster than link.w 0. */
1081 dest = gen_frame_mem (Pmode,
1082 gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
1083 m68k_set_frame_related (emit_move_insn (dest, frame_pointer_rtx));
1084 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx,
1085 stack_pointer_rtx));
1087 else if (fsize_with_regs < 0x8000 || TARGET_68020)
1088 m68k_set_frame_related
1089 (emit_insn (gen_link (frame_pointer_rtx,
1090 GEN_INT (-4 - fsize_with_regs))));
1093 m68k_set_frame_related
1094 (emit_insn (gen_link (frame_pointer_rtx, GEN_INT (-4))));
1095 m68k_set_frame_related
1096 (emit_insn (gen_addsi3 (stack_pointer_rtx,
1098 GEN_INT (-fsize_with_regs))));
1101 /* If the frame pointer is needed, emit a special barrier that
1102 will prevent the scheduler from moving stores to the frame
1103 before the stack adjustment. */
1104 emit_insn (gen_stack_tie (stack_pointer_rtx, frame_pointer_rtx));
1106 else if (fsize_with_regs != 0)
1107 m68k_set_frame_related
1108 (emit_insn (gen_addsi3 (stack_pointer_rtx,
1110 GEN_INT (-fsize_with_regs))));
1112 if (current_frame.fpu_mask)
1114 gcc_assert (current_frame.fpu_no >= MIN_FMOVEM_REGS);
1116 m68k_set_frame_related
1117 (m68k_emit_movem (stack_pointer_rtx,
1118 current_frame.fpu_no * -GET_MODE_SIZE (XFmode),
1119 current_frame.fpu_no, FP0_REG,
1120 current_frame.fpu_mask, true, true));
1125 /* If we're using moveml to save the integer registers,
1126 the stack pointer will point to the bottom of the moveml
1127 save area. Find the stack offset of the first FP register. */
1128 if (current_frame.reg_no < MIN_MOVEM_REGS)
1131 offset = current_frame.reg_no * GET_MODE_SIZE (SImode);
1132 m68k_set_frame_related
1133 (m68k_emit_movem (stack_pointer_rtx, offset,
1134 current_frame.fpu_no, FP0_REG,
1135 current_frame.fpu_mask, true, false));
1139 /* If the stack limit is not a symbol, check it here.
1140 This has the disadvantage that it may be too late... */
1141 if (crtl->limit_stack)
1143 if (REG_P (stack_limit_rtx))
1144 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode, stack_pointer_rtx,
1146 stack_pointer_rtx, stack_limit_rtx,
1149 else if (GET_CODE (stack_limit_rtx) != SYMBOL_REF)
1150 warning (0, "stack limit expression is not supported");
1153 if (current_frame.reg_no < MIN_MOVEM_REGS)
1155 /* Store each register separately in the same order moveml does. */
1158 for (i = 16; i-- > 0; )
1159 if (current_frame.reg_mask & (1 << i))
1161 src = gen_rtx_REG (SImode, D0_REG + i);
1162 dest = gen_frame_mem (SImode,
1163 gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
1164 m68k_set_frame_related (emit_insn (gen_movsi (dest, src)));
1169 if (TARGET_COLDFIRE)
1170 /* The required register save space has already been allocated.
1171 The first register should be stored at (%sp). */
1172 m68k_set_frame_related
1173 (m68k_emit_movem (stack_pointer_rtx, 0,
1174 current_frame.reg_no, D0_REG,
1175 current_frame.reg_mask, true, false));
1177 m68k_set_frame_related
1178 (m68k_emit_movem (stack_pointer_rtx,
1179 current_frame.reg_no * -GET_MODE_SIZE (SImode),
1180 current_frame.reg_no, D0_REG,
1181 current_frame.reg_mask, true, true));
1184 if (!TARGET_SEP_DATA
1185 && crtl->uses_pic_offset_table)
1186 emit_insn (gen_load_got (pic_offset_table_rtx));
1189 /* Return true if a simple (return) instruction is sufficient for this
1190 instruction (i.e. if no epilogue is needed). */
1193 m68k_use_return_insn (void)
1195 if (!reload_completed || frame_pointer_needed || get_frame_size () != 0)
1198 m68k_compute_frame_layout ();
1199 return current_frame.offset == 0;
1202 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1203 SIBCALL_P says which.
1205 The function epilogue should not depend on the current stack pointer!
1206 It should use the frame pointer only, if there is a frame pointer.
1207 This is mandatory because of alloca; we also take advantage of it to
1208 omit stack adjustments before returning. */
1211 m68k_expand_epilogue (bool sibcall_p)
1213 HOST_WIDE_INT fsize, fsize_with_regs;
1214 bool big, restore_from_sp;
1216 m68k_compute_frame_layout ();
1218 fsize = current_frame.size;
1220 restore_from_sp = false;
1222 /* FIXME : current_function_is_leaf below is too strong.
1223 What we really need to know there is if there could be pending
1224 stack adjustment needed at that point. */
1225 restore_from_sp = (!frame_pointer_needed
1226 || (!cfun->calls_alloca
1227 && current_function_is_leaf));
1229 /* fsize_with_regs is the size we need to adjust the sp when
1230 popping the frame. */
1231 fsize_with_regs = fsize;
1232 if (TARGET_COLDFIRE && restore_from_sp)
1234 /* ColdFire's move multiple instructions do not allow post-increment
1235 addressing. Add the size of movem loads to the final deallocation
1237 if (current_frame.reg_no >= MIN_MOVEM_REGS)
1238 fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode);
1239 if (current_frame.fpu_no >= MIN_FMOVEM_REGS)
1240 fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode);
1243 if (current_frame.offset + fsize >= 0x8000
1245 && (current_frame.reg_mask || current_frame.fpu_mask))
1248 && (current_frame.reg_no >= MIN_MOVEM_REGS
1249 || current_frame.fpu_no >= MIN_FMOVEM_REGS))
1251 /* ColdFire's move multiple instructions do not support the
1252 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1253 stack-based restore. */
1254 emit_move_insn (gen_rtx_REG (Pmode, A1_REG),
1255 GEN_INT (-(current_frame.offset + fsize)));
1256 emit_insn (gen_addsi3 (stack_pointer_rtx,
1257 gen_rtx_REG (Pmode, A1_REG),
1258 frame_pointer_rtx));
1259 restore_from_sp = true;
1263 emit_move_insn (gen_rtx_REG (Pmode, A1_REG), GEN_INT (-fsize));
1269 if (current_frame.reg_no < MIN_MOVEM_REGS)
1271 /* Restore each register separately in the same order moveml does. */
1273 HOST_WIDE_INT offset;
1275 offset = current_frame.offset + fsize;
1276 for (i = 0; i < 16; i++)
1277 if (current_frame.reg_mask & (1 << i))
1283 /* Generate the address -OFFSET(%fp,%a1.l). */
1284 addr = gen_rtx_REG (Pmode, A1_REG);
1285 addr = gen_rtx_PLUS (Pmode, addr, frame_pointer_rtx);
1286 addr = plus_constant (addr, -offset);
1288 else if (restore_from_sp)
1289 addr = gen_rtx_POST_INC (Pmode, stack_pointer_rtx);
1291 addr = plus_constant (frame_pointer_rtx, -offset);
1292 emit_move_insn (gen_rtx_REG (SImode, D0_REG + i),
1293 gen_frame_mem (SImode, addr));
1294 offset -= GET_MODE_SIZE (SImode);
1297 else if (current_frame.reg_mask)
1300 m68k_emit_movem (gen_rtx_PLUS (Pmode,
1301 gen_rtx_REG (Pmode, A1_REG),
1303 -(current_frame.offset + fsize),
1304 current_frame.reg_no, D0_REG,
1305 current_frame.reg_mask, false, false);
1306 else if (restore_from_sp)
1307 m68k_emit_movem (stack_pointer_rtx, 0,
1308 current_frame.reg_no, D0_REG,
1309 current_frame.reg_mask, false,
1312 m68k_emit_movem (frame_pointer_rtx,
1313 -(current_frame.offset + fsize),
1314 current_frame.reg_no, D0_REG,
1315 current_frame.reg_mask, false, false);
1318 if (current_frame.fpu_no > 0)
1321 m68k_emit_movem (gen_rtx_PLUS (Pmode,
1322 gen_rtx_REG (Pmode, A1_REG),
1324 -(current_frame.foffset + fsize),
1325 current_frame.fpu_no, FP0_REG,
1326 current_frame.fpu_mask, false, false);
1327 else if (restore_from_sp)
1329 if (TARGET_COLDFIRE)
1333 /* If we used moveml to restore the integer registers, the
1334 stack pointer will still point to the bottom of the moveml
1335 save area. Find the stack offset of the first FP
1337 if (current_frame.reg_no < MIN_MOVEM_REGS)
1340 offset = current_frame.reg_no * GET_MODE_SIZE (SImode);
1341 m68k_emit_movem (stack_pointer_rtx, offset,
1342 current_frame.fpu_no, FP0_REG,
1343 current_frame.fpu_mask, false, false);
1346 m68k_emit_movem (stack_pointer_rtx, 0,
1347 current_frame.fpu_no, FP0_REG,
1348 current_frame.fpu_mask, false, true);
1351 m68k_emit_movem (frame_pointer_rtx,
1352 -(current_frame.foffset + fsize),
1353 current_frame.fpu_no, FP0_REG,
1354 current_frame.fpu_mask, false, false);
1357 if (frame_pointer_needed)
1358 emit_insn (gen_unlink (frame_pointer_rtx));
1359 else if (fsize_with_regs)
1360 emit_insn (gen_addsi3 (stack_pointer_rtx,
1362 GEN_INT (fsize_with_regs)));
1364 if (crtl->calls_eh_return)
1365 emit_insn (gen_addsi3 (stack_pointer_rtx,
1367 EH_RETURN_STACKADJ_RTX));
1370 emit_jump_insn (gen_rtx_RETURN (VOIDmode));
1373 /* Return true if X is a valid comparison operator for the dbcc
1376 Note it rejects floating point comparison operators.
1377 (In the future we could use Fdbcc).
1379 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1382 valid_dbcc_comparison_p_2 (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1384 switch (GET_CODE (x))
1386 case EQ: case NE: case GTU: case LTU:
1390 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1392 case GT: case LT: case GE: case LE:
1393 return ! (cc_prev_status.flags & CC_NO_OVERFLOW);
1399 /* Return nonzero if flags are currently in the 68881 flag register. */
1401 flags_in_68881 (void)
1403 /* We could add support for these in the future */
1404 return cc_status.flags & CC_IN_68881;
1407 /* Return true if PARALLEL contains register REGNO. */
1409 m68k_reg_present_p (const_rtx parallel, unsigned int regno)
1413 if (REG_P (parallel) && REGNO (parallel) == regno)
1416 if (GET_CODE (parallel) != PARALLEL)
1419 for (i = 0; i < XVECLEN (parallel, 0); ++i)
1423 x = XEXP (XVECEXP (parallel, 0, i), 0);
1424 if (REG_P (x) && REGNO (x) == regno)
1431 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1434 m68k_ok_for_sibcall_p (tree decl, tree exp)
1436 enum m68k_function_kind kind;
1438 /* We cannot use sibcalls for nested functions because we use the
1439 static chain register for indirect calls. */
1440 if (CALL_EXPR_STATIC_CHAIN (exp))
1443 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
1445 /* Check that the return value locations are the same. For
1446 example that we aren't returning a value from the sibling in
1447 a D0 register but then need to transfer it to a A0 register. */
1451 cfun_value = FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (cfun->decl)),
1453 call_value = FUNCTION_VALUE (TREE_TYPE (exp), decl);
1455 /* Check that the values are equal or that the result the callee
1456 function returns is superset of what the current function returns. */
1457 if (!(rtx_equal_p (cfun_value, call_value)
1458 || (REG_P (cfun_value)
1459 && m68k_reg_present_p (call_value, REGNO (cfun_value)))))
1463 kind = m68k_get_function_kind (current_function_decl);
1464 if (kind == m68k_fk_normal_function)
1465 /* We can always sibcall from a normal function, because it's
1466 undefined if it is calling an interrupt function. */
1469 /* Otherwise we can only sibcall if the function kind is known to be
1471 if (decl && m68k_get_function_kind (decl) == kind)
1477 /* Convert X to a legitimate function call memory reference and return the
1481 m68k_legitimize_call_address (rtx x)
1483 gcc_assert (MEM_P (x));
1484 if (call_operand (XEXP (x, 0), VOIDmode))
1486 return replace_equiv_address (x, force_reg (Pmode, XEXP (x, 0)));
1489 /* Likewise for sibling calls. */
1492 m68k_legitimize_sibcall_address (rtx x)
1494 gcc_assert (MEM_P (x));
1495 if (sibcall_operand (XEXP (x, 0), VOIDmode))
1498 emit_move_insn (gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM), XEXP (x, 0));
1499 return replace_equiv_address (x, gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM));
1502 /* Convert X to a legitimate address and return it if successful. Otherwise
1505 For the 68000, we handle X+REG by loading X into a register R and
1506 using R+REG. R will go in an address reg and indexing will be used.
1507 However, if REG is a broken-out memory address or multiplication,
1508 nothing needs to be done because REG can certainly go in an address reg. */
1511 m68k_legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
1513 if (m68k_tls_symbol_p (x))
1514 return m68k_legitimize_tls_address (x);
1516 if (GET_CODE (x) == PLUS)
1518 int ch = (x) != (oldx);
1521 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1523 if (GET_CODE (XEXP (x, 0)) == MULT)
1526 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
1528 if (GET_CODE (XEXP (x, 1)) == MULT)
1531 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
1535 if (GET_CODE (XEXP (x, 1)) == REG
1536 && GET_CODE (XEXP (x, 0)) == REG)
1538 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT)
1541 x = force_operand (x, 0);
1545 if (memory_address_p (mode, x))
1548 if (GET_CODE (XEXP (x, 0)) == REG
1549 || (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
1550 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
1551 && GET_MODE (XEXP (XEXP (x, 0), 0)) == HImode))
1553 rtx temp = gen_reg_rtx (Pmode);
1554 rtx val = force_operand (XEXP (x, 1), 0);
1555 emit_move_insn (temp, val);
1558 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT
1559 && GET_CODE (XEXP (x, 0)) == REG)
1560 x = force_operand (x, 0);
1562 else if (GET_CODE (XEXP (x, 1)) == REG
1563 || (GET_CODE (XEXP (x, 1)) == SIGN_EXTEND
1564 && GET_CODE (XEXP (XEXP (x, 1), 0)) == REG
1565 && GET_MODE (XEXP (XEXP (x, 1), 0)) == HImode))
1567 rtx temp = gen_reg_rtx (Pmode);
1568 rtx val = force_operand (XEXP (x, 0), 0);
1569 emit_move_insn (temp, val);
1572 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT
1573 && GET_CODE (XEXP (x, 1)) == REG)
1574 x = force_operand (x, 0);
1582 /* Output a dbCC; jCC sequence. Note we do not handle the
1583 floating point version of this sequence (Fdbcc). We also
1584 do not handle alternative conditions when CC_NO_OVERFLOW is
1585 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1586 kick those out before we get here. */
1589 output_dbcc_and_branch (rtx *operands)
1591 switch (GET_CODE (operands[3]))
1594 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands);
1598 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands);
1602 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands);
1606 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands);
1610 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands);
1614 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands);
1618 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands);
1622 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands);
1626 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands);
1630 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands);
1637 /* If the decrement is to be done in SImode, then we have
1638 to compensate for the fact that dbcc decrements in HImode. */
1639 switch (GET_MODE (operands[0]))
1642 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands);
1654 output_scc_di (rtx op, rtx operand1, rtx operand2, rtx dest)
1657 enum rtx_code op_code = GET_CODE (op);
1659 /* This does not produce a useful cc. */
1662 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1663 below. Swap the operands and change the op if these requirements
1664 are not fulfilled. */
1665 if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG)
1669 operand1 = operand2;
1671 op_code = swap_condition (op_code);
1673 loperands[0] = operand1;
1674 if (GET_CODE (operand1) == REG)
1675 loperands[1] = gen_rtx_REG (SImode, REGNO (operand1) + 1);
1677 loperands[1] = adjust_address (operand1, SImode, 4);
1678 if (operand2 != const0_rtx)
1680 loperands[2] = operand2;
1681 if (GET_CODE (operand2) == REG)
1682 loperands[3] = gen_rtx_REG (SImode, REGNO (operand2) + 1);
1684 loperands[3] = adjust_address (operand2, SImode, 4);
1686 loperands[4] = gen_label_rtx ();
1687 if (operand2 != const0_rtx)
1688 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands);
1691 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[0]))
1692 output_asm_insn ("tst%.l %0", loperands);
1694 output_asm_insn ("cmp%.w #0,%0", loperands);
1696 output_asm_insn ("jne %l4", loperands);
1698 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[1]))
1699 output_asm_insn ("tst%.l %1", loperands);
1701 output_asm_insn ("cmp%.w #0,%1", loperands);
1704 loperands[5] = dest;
1709 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1710 CODE_LABEL_NUMBER (loperands[4]));
1711 output_asm_insn ("seq %5", loperands);
1715 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1716 CODE_LABEL_NUMBER (loperands[4]));
1717 output_asm_insn ("sne %5", loperands);
1721 loperands[6] = gen_label_rtx ();
1722 output_asm_insn ("shi %5\n\tjra %l6", loperands);
1723 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1724 CODE_LABEL_NUMBER (loperands[4]));
1725 output_asm_insn ("sgt %5", loperands);
1726 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1727 CODE_LABEL_NUMBER (loperands[6]));
1731 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1732 CODE_LABEL_NUMBER (loperands[4]));
1733 output_asm_insn ("shi %5", loperands);
1737 loperands[6] = gen_label_rtx ();
1738 output_asm_insn ("scs %5\n\tjra %l6", loperands);
1739 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1740 CODE_LABEL_NUMBER (loperands[4]));
1741 output_asm_insn ("slt %5", loperands);
1742 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1743 CODE_LABEL_NUMBER (loperands[6]));
1747 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1748 CODE_LABEL_NUMBER (loperands[4]));
1749 output_asm_insn ("scs %5", loperands);
1753 loperands[6] = gen_label_rtx ();
1754 output_asm_insn ("scc %5\n\tjra %l6", loperands);
1755 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1756 CODE_LABEL_NUMBER (loperands[4]));
1757 output_asm_insn ("sge %5", loperands);
1758 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1759 CODE_LABEL_NUMBER (loperands[6]));
1763 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1764 CODE_LABEL_NUMBER (loperands[4]));
1765 output_asm_insn ("scc %5", loperands);
1769 loperands[6] = gen_label_rtx ();
1770 output_asm_insn ("sls %5\n\tjra %l6", loperands);
1771 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1772 CODE_LABEL_NUMBER (loperands[4]));
1773 output_asm_insn ("sle %5", loperands);
1774 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1775 CODE_LABEL_NUMBER (loperands[6]));
1779 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1780 CODE_LABEL_NUMBER (loperands[4]));
1781 output_asm_insn ("sls %5", loperands);
1791 output_btst (rtx *operands, rtx countop, rtx dataop, rtx insn, int signpos)
1793 operands[0] = countop;
1794 operands[1] = dataop;
1796 if (GET_CODE (countop) == CONST_INT)
1798 register int count = INTVAL (countop);
1799 /* If COUNT is bigger than size of storage unit in use,
1800 advance to the containing unit of same size. */
1801 if (count > signpos)
1803 int offset = (count & ~signpos) / 8;
1804 count = count & signpos;
1805 operands[1] = dataop = adjust_address (dataop, QImode, offset);
1807 if (count == signpos)
1808 cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N;
1810 cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N;
1812 /* These three statements used to use next_insns_test_no...
1813 but it appears that this should do the same job. */
1815 && next_insn_tests_no_inequality (insn))
1818 && next_insn_tests_no_inequality (insn))
1821 && next_insn_tests_no_inequality (insn))
1823 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1824 On some m68k variants unfortunately that's slower than btst.
1825 On 68000 and higher, that should also work for all HImode operands. */
1826 if (TUNE_CPU32 || TARGET_COLDFIRE || optimize_size)
1828 if (count == 3 && DATA_REG_P (operands[1])
1829 && next_insn_tests_no_inequality (insn))
1831 cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N | CC_NO_OVERFLOW;
1832 return "move%.w %1,%%ccr";
1834 if (count == 2 && DATA_REG_P (operands[1])
1835 && next_insn_tests_no_inequality (insn))
1837 cc_status.flags = CC_NOT_NEGATIVE | CC_INVERTED | CC_NO_OVERFLOW;
1838 return "move%.w %1,%%ccr";
1840 /* count == 1 followed by bvc/bvs and
1841 count == 0 followed by bcc/bcs are also possible, but need
1842 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1845 cc_status.flags = CC_NOT_NEGATIVE;
1847 return "btst %0,%1";
1850 /* Return true if X is a legitimate base register. STRICT_P says
1851 whether we need strict checking. */
1854 m68k_legitimate_base_reg_p (rtx x, bool strict_p)
1856 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1857 if (!strict_p && GET_CODE (x) == SUBREG)
1862 ? REGNO_OK_FOR_BASE_P (REGNO (x))
1863 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x))));
1866 /* Return true if X is a legitimate index register. STRICT_P says
1867 whether we need strict checking. */
1870 m68k_legitimate_index_reg_p (rtx x, bool strict_p)
1872 if (!strict_p && GET_CODE (x) == SUBREG)
1877 ? REGNO_OK_FOR_INDEX_P (REGNO (x))
1878 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x))));
1881 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1882 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1883 ADDRESS if so. STRICT_P says whether we need strict checking. */
1886 m68k_decompose_index (rtx x, bool strict_p, struct m68k_address *address)
1890 /* Check for a scale factor. */
1892 if ((TARGET_68020 || TARGET_COLDFIRE)
1893 && GET_CODE (x) == MULT
1894 && GET_CODE (XEXP (x, 1)) == CONST_INT
1895 && (INTVAL (XEXP (x, 1)) == 2
1896 || INTVAL (XEXP (x, 1)) == 4
1897 || (INTVAL (XEXP (x, 1)) == 8
1898 && (TARGET_COLDFIRE_FPU || !TARGET_COLDFIRE))))
1900 scale = INTVAL (XEXP (x, 1));
1904 /* Check for a word extension. */
1905 if (!TARGET_COLDFIRE
1906 && GET_CODE (x) == SIGN_EXTEND
1907 && GET_MODE (XEXP (x, 0)) == HImode)
1910 if (m68k_legitimate_index_reg_p (x, strict_p))
1912 address->scale = scale;
1920 /* Return true if X is an illegitimate symbolic constant. */
1923 m68k_illegitimate_symbolic_constant_p (rtx x)
1927 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P)
1929 split_const (x, &base, &offset);
1930 if (GET_CODE (base) == SYMBOL_REF
1931 && !offset_within_block_p (base, INTVAL (offset)))
1934 return m68k_tls_reference_p (x, false);
1937 /* Return true if X is a legitimate constant address that can reach
1938 bytes in the range [X, X + REACH). STRICT_P says whether we need
1942 m68k_legitimate_constant_address_p (rtx x, unsigned int reach, bool strict_p)
1946 if (!CONSTANT_ADDRESS_P (x))
1950 && !(strict_p && TARGET_PCREL)
1951 && symbolic_operand (x, VOIDmode))
1954 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P && reach > 1)
1956 split_const (x, &base, &offset);
1957 if (GET_CODE (base) == SYMBOL_REF
1958 && !offset_within_block_p (base, INTVAL (offset) + reach - 1))
1962 return !m68k_tls_reference_p (x, false);
1965 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1966 labels will become jump tables. */
1969 m68k_jump_table_ref_p (rtx x)
1971 if (GET_CODE (x) != LABEL_REF)
1975 if (!NEXT_INSN (x) && !PREV_INSN (x))
1978 x = next_nonnote_insn (x);
1979 return x && JUMP_TABLE_DATA_P (x);
1982 /* Return true if X is a legitimate address for values of mode MODE.
1983 STRICT_P says whether strict checking is needed. If the address
1984 is valid, describe its components in *ADDRESS. */
1987 m68k_decompose_address (enum machine_mode mode, rtx x,
1988 bool strict_p, struct m68k_address *address)
1992 memset (address, 0, sizeof (*address));
1994 if (mode == BLKmode)
1997 reach = GET_MODE_SIZE (mode);
1999 /* Check for (An) (mode 2). */
2000 if (m68k_legitimate_base_reg_p (x, strict_p))
2006 /* Check for -(An) and (An)+ (modes 3 and 4). */
2007 if ((GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC)
2008 && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p))
2010 address->code = GET_CODE (x);
2011 address->base = XEXP (x, 0);
2015 /* Check for (d16,An) (mode 5). */
2016 if (GET_CODE (x) == PLUS
2017 && GET_CODE (XEXP (x, 1)) == CONST_INT
2018 && IN_RANGE (INTVAL (XEXP (x, 1)), -0x8000, 0x8000 - reach)
2019 && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p))
2021 address->base = XEXP (x, 0);
2022 address->offset = XEXP (x, 1);
2026 /* Check for GOT loads. These are (bd,An,Xn) addresses if
2027 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
2029 if (GET_CODE (x) == PLUS
2030 && XEXP (x, 0) == pic_offset_table_rtx)
2032 /* As we are processing a PLUS, do not unwrap RELOC32 symbols --
2033 they are invalid in this context. */
2034 if (m68k_unwrap_symbol (XEXP (x, 1), false) != XEXP (x, 1))
2036 address->base = XEXP (x, 0);
2037 address->offset = XEXP (x, 1);
2042 /* The ColdFire FPU only accepts addressing modes 2-5. */
2043 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT)
2046 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
2047 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
2048 All these modes are variations of mode 7. */
2049 if (m68k_legitimate_constant_address_p (x, reach, strict_p))
2051 address->offset = x;
2055 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
2058 ??? do_tablejump creates these addresses before placing the target
2059 label, so we have to assume that unplaced labels are jump table
2060 references. It seems unlikely that we would ever generate indexed
2061 accesses to unplaced labels in other cases. */
2062 if (GET_CODE (x) == PLUS
2063 && m68k_jump_table_ref_p (XEXP (x, 1))
2064 && m68k_decompose_index (XEXP (x, 0), strict_p, address))
2066 address->offset = XEXP (x, 1);
2070 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
2071 (bd,An,Xn.SIZE*SCALE) addresses. */
2075 /* Check for a nonzero base displacement. */
2076 if (GET_CODE (x) == PLUS
2077 && m68k_legitimate_constant_address_p (XEXP (x, 1), reach, strict_p))
2079 address->offset = XEXP (x, 1);
2083 /* Check for a suppressed index register. */
2084 if (m68k_legitimate_base_reg_p (x, strict_p))
2090 /* Check for a suppressed base register. Do not allow this case
2091 for non-symbolic offsets as it effectively gives gcc freedom
2092 to treat data registers as base registers, which can generate
2095 && symbolic_operand (address->offset, VOIDmode)
2096 && m68k_decompose_index (x, strict_p, address))
2101 /* Check for a nonzero base displacement. */
2102 if (GET_CODE (x) == PLUS
2103 && GET_CODE (XEXP (x, 1)) == CONST_INT
2104 && IN_RANGE (INTVAL (XEXP (x, 1)), -0x80, 0x80 - reach))
2106 address->offset = XEXP (x, 1);
2111 /* We now expect the sum of a base and an index. */
2112 if (GET_CODE (x) == PLUS)
2114 if (m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p)
2115 && m68k_decompose_index (XEXP (x, 1), strict_p, address))
2117 address->base = XEXP (x, 0);
2121 if (m68k_legitimate_base_reg_p (XEXP (x, 1), strict_p)
2122 && m68k_decompose_index (XEXP (x, 0), strict_p, address))
2124 address->base = XEXP (x, 1);
2131 /* Return true if X is a legitimate address for values of mode MODE.
2132 STRICT_P says whether strict checking is needed. */
2135 m68k_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2137 struct m68k_address address;
2139 return m68k_decompose_address (mode, x, strict_p, &address);
2142 /* Return true if X is a memory, describing its address in ADDRESS if so.
2143 Apply strict checking if called during or after reload. */
2146 m68k_legitimate_mem_p (rtx x, struct m68k_address *address)
2149 && m68k_decompose_address (GET_MODE (x), XEXP (x, 0),
2150 reload_in_progress || reload_completed,
2154 /* Return true if X matches the 'Q' constraint. It must be a memory
2155 with a base address and no constant offset or index. */
2158 m68k_matches_q_p (rtx x)
2160 struct m68k_address address;
2162 return (m68k_legitimate_mem_p (x, &address)
2163 && address.code == UNKNOWN
2169 /* Return true if X matches the 'U' constraint. It must be a base address
2170 with a constant offset and no index. */
2173 m68k_matches_u_p (rtx x)
2175 struct m68k_address address;
2177 return (m68k_legitimate_mem_p (x, &address)
2178 && address.code == UNKNOWN
2184 /* Return GOT pointer. */
2189 if (pic_offset_table_rtx == NULL_RTX)
2190 pic_offset_table_rtx = gen_rtx_REG (Pmode, PIC_REG);
2192 crtl->uses_pic_offset_table = 1;
2194 return pic_offset_table_rtx;
2197 /* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC
2199 enum m68k_reloc { RELOC_GOT, RELOC_TLSGD, RELOC_TLSLDM, RELOC_TLSLDO,
2200 RELOC_TLSIE, RELOC_TLSLE };
2202 #define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT)
2204 /* Wrap symbol X into unspec representing relocation RELOC.
2205 BASE_REG - register that should be added to the result.
2206 TEMP_REG - if non-null, temporary register. */
2209 m68k_wrap_symbol (rtx x, enum m68k_reloc reloc, rtx base_reg, rtx temp_reg)
2213 use_x_p = (base_reg == pic_offset_table_rtx) ? TARGET_XGOT : TARGET_XTLS;
2215 if (TARGET_COLDFIRE && use_x_p)
2216 /* When compiling with -mx{got, tls} switch the code will look like this:
2218 move.l <X>@<RELOC>,<TEMP_REG>
2219 add.l <BASE_REG>,<TEMP_REG> */
2221 /* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra
2222 to put @RELOC after reference. */
2223 x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (reloc)),
2225 x = gen_rtx_CONST (Pmode, x);
2227 if (temp_reg == NULL)
2229 gcc_assert (can_create_pseudo_p ());
2230 temp_reg = gen_reg_rtx (Pmode);
2233 emit_move_insn (temp_reg, x);
2234 emit_insn (gen_addsi3 (temp_reg, temp_reg, base_reg));
2239 x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (reloc)),
2241 x = gen_rtx_CONST (Pmode, x);
2243 x = gen_rtx_PLUS (Pmode, base_reg, x);
2249 /* Helper for m68k_unwrap_symbol.
2250 Also, if unwrapping was successful (that is if (ORIG != <return value>)),
2251 sets *RELOC_PTR to relocation type for the symbol. */
2254 m68k_unwrap_symbol_1 (rtx orig, bool unwrap_reloc32_p,
2255 enum m68k_reloc *reloc_ptr)
2257 if (GET_CODE (orig) == CONST)
2260 enum m68k_reloc dummy;
2264 if (reloc_ptr == NULL)
2267 /* Handle an addend. */
2268 if ((GET_CODE (x) == PLUS || GET_CODE (x) == MINUS)
2269 && CONST_INT_P (XEXP (x, 1)))
2272 if (GET_CODE (x) == UNSPEC)
2274 switch (XINT (x, 1))
2276 case UNSPEC_RELOC16:
2277 orig = XVECEXP (x, 0, 0);
2278 *reloc_ptr = (enum m68k_reloc) INTVAL (XVECEXP (x, 0, 1));
2281 case UNSPEC_RELOC32:
2282 if (unwrap_reloc32_p)
2284 orig = XVECEXP (x, 0, 0);
2285 *reloc_ptr = (enum m68k_reloc) INTVAL (XVECEXP (x, 0, 1));
2298 /* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p,
2299 UNSPEC_RELOC32 wrappers. */
2302 m68k_unwrap_symbol (rtx orig, bool unwrap_reloc32_p)
2304 return m68k_unwrap_symbol_1 (orig, unwrap_reloc32_p, NULL);
2307 /* Helper for m68k_final_prescan_insn. */
2310 m68k_final_prescan_insn_1 (rtx *x_ptr, void *data ATTRIBUTE_UNUSED)
2314 if (m68k_unwrap_symbol (x, true) != x)
2315 /* For rationale of the below, see comment in m68k_final_prescan_insn. */
2319 gcc_assert (GET_CODE (x) == CONST);
2322 if (GET_CODE (plus) == PLUS || GET_CODE (plus) == MINUS)
2327 unspec = XEXP (plus, 0);
2328 gcc_assert (GET_CODE (unspec) == UNSPEC);
2329 addend = XEXP (plus, 1);
2330 gcc_assert (CONST_INT_P (addend));
2332 /* We now have all the pieces, rearrange them. */
2334 /* Move symbol to plus. */
2335 XEXP (plus, 0) = XVECEXP (unspec, 0, 0);
2337 /* Move plus inside unspec. */
2338 XVECEXP (unspec, 0, 0) = plus;
2340 /* Move unspec to top level of const. */
2341 XEXP (x, 0) = unspec;
2350 /* Prescan insn before outputing assembler for it. */
2353 m68k_final_prescan_insn (rtx insn ATTRIBUTE_UNUSED,
2354 rtx *operands, int n_operands)
2358 /* Combine and, possibly, other optimizations may do good job
2360 (const (unspec [(symbol)]))
2362 (const (plus (unspec [(symbol)])
2364 The problem with this is emitting @TLS or @GOT decorations.
2365 The decoration is emitted when processing (unspec), so the
2366 result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE".
2368 It seems that the easiest solution to this is to convert such
2370 (const (unspec [(plus (symbol)
2372 Note, that the top level of operand remains intact, so we don't have
2373 to patch up anything outside of the operand. */
2375 for (i = 0; i < n_operands; ++i)
2381 for_each_rtx (&op, m68k_final_prescan_insn_1, NULL);
2385 /* Move X to a register and add REG_EQUAL note pointing to ORIG.
2386 If REG is non-null, use it; generate new pseudo otherwise. */
2389 m68k_move_to_reg (rtx x, rtx orig, rtx reg)
2393 if (reg == NULL_RTX)
2395 gcc_assert (can_create_pseudo_p ());
2396 reg = gen_reg_rtx (Pmode);
2399 insn = emit_move_insn (reg, x);
2400 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2402 set_unique_reg_note (insn, REG_EQUAL, orig);
2407 /* Does the same as m68k_wrap_symbol, but returns a memory reference to
2411 m68k_wrap_symbol_into_got_ref (rtx x, enum m68k_reloc reloc, rtx temp_reg)
2413 x = m68k_wrap_symbol (x, reloc, m68k_get_gp (), temp_reg);
2415 x = gen_rtx_MEM (Pmode, x);
2416 MEM_READONLY_P (x) = 1;
2421 /* Legitimize PIC addresses. If the address is already
2422 position-independent, we return ORIG. Newly generated
2423 position-independent addresses go to REG. If we need more
2424 than one register, we lose.
2426 An address is legitimized by making an indirect reference
2427 through the Global Offset Table with the name of the symbol
2430 The assembler and linker are responsible for placing the
2431 address of the symbol in the GOT. The function prologue
2432 is responsible for initializing a5 to the starting address
2435 The assembler is also responsible for translating a symbol name
2436 into a constant displacement from the start of the GOT.
2438 A quick example may make things a little clearer:
2440 When not generating PIC code to store the value 12345 into _foo
2441 we would generate the following code:
2445 When generating PIC two transformations are made. First, the compiler
2446 loads the address of foo into a register. So the first transformation makes:
2451 The code in movsi will intercept the lea instruction and call this
2452 routine which will transform the instructions into:
2454 movel a5@(_foo:w), a0
2458 That (in a nutshell) is how *all* symbol and label references are
2462 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
2467 /* First handle a simple SYMBOL_REF or LABEL_REF */
2468 if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
2472 pic_ref = m68k_wrap_symbol_into_got_ref (orig, RELOC_GOT, reg);
2473 pic_ref = m68k_move_to_reg (pic_ref, orig, reg);
2475 else if (GET_CODE (orig) == CONST)
2479 /* Make sure this has not already been legitimized. */
2480 if (m68k_unwrap_symbol (orig, true) != orig)
2485 /* legitimize both operands of the PLUS */
2486 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
2488 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2489 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2490 base == reg ? 0 : reg);
2492 if (GET_CODE (orig) == CONST_INT)
2493 pic_ref = plus_constant (base, INTVAL (orig));
2495 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
2501 /* The __tls_get_addr symbol. */
2502 static GTY(()) rtx m68k_tls_get_addr;
2504 /* Return SYMBOL_REF for __tls_get_addr. */
2507 m68k_get_tls_get_addr (void)
2509 if (m68k_tls_get_addr == NULL_RTX)
2510 m68k_tls_get_addr = init_one_libfunc ("__tls_get_addr");
2512 return m68k_tls_get_addr;
2515 /* Return libcall result in A0 instead of usual D0. */
2516 static bool m68k_libcall_value_in_a0_p = false;
2518 /* Emit instruction sequence that calls __tls_get_addr. X is
2519 the TLS symbol we are referencing and RELOC is the symbol type to use
2520 (either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence
2521 emitted. A pseudo register with result of __tls_get_addr call is
2525 m68k_call_tls_get_addr (rtx x, rtx eqv, enum m68k_reloc reloc)
2531 /* Emit the call sequence. */
2534 /* FIXME: Unfortunately, emit_library_call_value does not
2535 consider (plus (%a5) (const (unspec))) to be a good enough
2536 operand for push, so it forces it into a register. The bad
2537 thing about this is that combiner, due to copy propagation and other
2538 optimizations, sometimes can not later fix this. As a consequence,
2539 additional register may be allocated resulting in a spill.
2540 For reference, see args processing loops in
2541 calls.c:emit_library_call_value_1.
2542 For testcase, see gcc.target/m68k/tls-{gd, ld}.c */
2543 x = m68k_wrap_symbol (x, reloc, m68k_get_gp (), NULL_RTX);
2545 /* __tls_get_addr() is not a libcall, but emitting a libcall_value
2546 is the simpliest way of generating a call. The difference between
2547 __tls_get_addr() and libcall is that the result is returned in D0
2548 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2549 which temporarily switches returning the result to A0. */
2551 m68k_libcall_value_in_a0_p = true;
2552 a0 = emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX, LCT_PURE,
2553 Pmode, 1, x, Pmode);
2554 m68k_libcall_value_in_a0_p = false;
2556 insns = get_insns ();
2559 gcc_assert (can_create_pseudo_p ());
2560 dest = gen_reg_rtx (Pmode);
2561 emit_libcall_block (insns, dest, a0, eqv);
2566 /* The __tls_get_addr symbol. */
2567 static GTY(()) rtx m68k_read_tp;
2569 /* Return SYMBOL_REF for __m68k_read_tp. */
2572 m68k_get_m68k_read_tp (void)
2574 if (m68k_read_tp == NULL_RTX)
2575 m68k_read_tp = init_one_libfunc ("__m68k_read_tp");
2577 return m68k_read_tp;
2580 /* Emit instruction sequence that calls __m68k_read_tp.
2581 A pseudo register with result of __m68k_read_tp call is returned. */
2584 m68k_call_m68k_read_tp (void)
2593 /* __m68k_read_tp() is not a libcall, but emitting a libcall_value
2594 is the simpliest way of generating a call. The difference between
2595 __m68k_read_tp() and libcall is that the result is returned in D0
2596 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2597 which temporarily switches returning the result to A0. */
2599 /* Emit the call sequence. */
2600 m68k_libcall_value_in_a0_p = true;
2601 a0 = emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX, LCT_PURE,
2603 m68k_libcall_value_in_a0_p = false;
2604 insns = get_insns ();
2607 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2608 share the m68k_read_tp result with other IE/LE model accesses. */
2609 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const1_rtx), UNSPEC_RELOC32);
2611 gcc_assert (can_create_pseudo_p ());
2612 dest = gen_reg_rtx (Pmode);
2613 emit_libcall_block (insns, dest, a0, eqv);
2618 /* Return a legitimized address for accessing TLS SYMBOL_REF X.
2619 For explanations on instructions sequences see TLS/NPTL ABI for m68k and
2623 m68k_legitimize_tls_address (rtx orig)
2625 switch (SYMBOL_REF_TLS_MODEL (orig))
2627 case TLS_MODEL_GLOBAL_DYNAMIC:
2628 orig = m68k_call_tls_get_addr (orig, orig, RELOC_TLSGD);
2631 case TLS_MODEL_LOCAL_DYNAMIC:
2637 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2638 share the LDM result with other LD model accesses. */
2639 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2642 a0 = m68k_call_tls_get_addr (orig, eqv, RELOC_TLSLDM);
2644 x = m68k_wrap_symbol (orig, RELOC_TLSLDO, a0, NULL_RTX);
2646 if (can_create_pseudo_p ())
2647 x = m68k_move_to_reg (x, orig, NULL_RTX);
2653 case TLS_MODEL_INITIAL_EXEC:
2658 a0 = m68k_call_m68k_read_tp ();
2660 x = m68k_wrap_symbol_into_got_ref (orig, RELOC_TLSIE, NULL_RTX);
2661 x = gen_rtx_PLUS (Pmode, x, a0);
2663 if (can_create_pseudo_p ())
2664 x = m68k_move_to_reg (x, orig, NULL_RTX);
2670 case TLS_MODEL_LOCAL_EXEC:
2675 a0 = m68k_call_m68k_read_tp ();
2677 x = m68k_wrap_symbol (orig, RELOC_TLSLE, a0, NULL_RTX);
2679 if (can_create_pseudo_p ())
2680 x = m68k_move_to_reg (x, orig, NULL_RTX);
2693 /* Return true if X is a TLS symbol. */
2696 m68k_tls_symbol_p (rtx x)
2698 if (!TARGET_HAVE_TLS)
2701 if (GET_CODE (x) != SYMBOL_REF)
2704 return SYMBOL_REF_TLS_MODEL (x) != 0;
2707 /* Helper for m68k_tls_referenced_p. */
2710 m68k_tls_reference_p_1 (rtx *x_ptr, void *data ATTRIBUTE_UNUSED)
2712 /* Note: this is not the same as m68k_tls_symbol_p. */
2713 if (GET_CODE (*x_ptr) == SYMBOL_REF)
2714 return SYMBOL_REF_TLS_MODEL (*x_ptr) != 0 ? 1 : 0;
2716 /* Don't recurse into legitimate TLS references. */
2717 if (m68k_tls_reference_p (*x_ptr, true))
2723 /* If !LEGITIMATE_P, return true if X is a TLS symbol reference,
2724 though illegitimate one.
2725 If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */
2728 m68k_tls_reference_p (rtx x, bool legitimate_p)
2730 if (!TARGET_HAVE_TLS)
2734 return for_each_rtx (&x, m68k_tls_reference_p_1, NULL) == 1 ? true : false;
2737 enum m68k_reloc reloc = RELOC_GOT;
2739 return (m68k_unwrap_symbol_1 (x, true, &reloc) != x
2740 && TLS_RELOC_P (reloc));
2746 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2748 /* Return the type of move that should be used for integer I. */
2751 m68k_const_method (HOST_WIDE_INT i)
2758 /* The ColdFire doesn't have byte or word operations. */
2759 /* FIXME: This may not be useful for the m68060 either. */
2760 if (!TARGET_COLDFIRE)
2762 /* if -256 < N < 256 but N is not in range for a moveq
2763 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2764 if (USE_MOVQ (i ^ 0xff))
2766 /* Likewise, try with not.w */
2767 if (USE_MOVQ (i ^ 0xffff))
2769 /* This is the only value where neg.w is useful */
2774 /* Try also with swap. */
2776 if (USE_MOVQ ((u >> 16) | (u << 16)))
2781 /* Try using MVZ/MVS with an immediate value to load constants. */
2782 if (i >= 0 && i <= 65535)
2784 if (i >= -32768 && i <= 32767)
2788 /* Otherwise, use move.l */
2792 /* Return the cost of moving constant I into a data register. */
2795 const_int_cost (HOST_WIDE_INT i)
2797 switch (m68k_const_method (i))
2800 /* Constants between -128 and 127 are cheap due to moveq. */
2808 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2818 m68k_rtx_costs (rtx x, int code, int outer_code, int *total,
2819 bool speed ATTRIBUTE_UNUSED)
2824 /* Constant zero is super cheap due to clr instruction. */
2825 if (x == const0_rtx)
2828 *total = const_int_cost (INTVAL (x));
2838 /* Make 0.0 cheaper than other floating constants to
2839 encourage creating tstsf and tstdf insns. */
2840 if (outer_code == COMPARE
2841 && (x == CONST0_RTX (SFmode) || x == CONST0_RTX (DFmode)))
2847 /* These are vaguely right for a 68020. */
2848 /* The costs for long multiply have been adjusted to work properly
2849 in synth_mult on the 68020, relative to an average of the time
2850 for add and the time for shift, taking away a little more because
2851 sometimes move insns are needed. */
2852 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2857 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2858 : (TUNE_CFV2 && TUNE_MAC) ? 4 \
2860 : TARGET_COLDFIRE ? 3 : 13)
2865 : TUNE_68000_10 ? 5 \
2866 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2867 : (TUNE_CFV2 && TUNE_MAC) ? 2 \
2869 : TARGET_COLDFIRE ? 2 : 8)
2872 (TARGET_CF_HWDIV ? 11 \
2873 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2876 /* An lea costs about three times as much as a simple add. */
2877 if (GET_MODE (x) == SImode
2878 && GET_CODE (XEXP (x, 1)) == REG
2879 && GET_CODE (XEXP (x, 0)) == MULT
2880 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
2881 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2882 && (INTVAL (XEXP (XEXP (x, 0), 1)) == 2
2883 || INTVAL (XEXP (XEXP (x, 0), 1)) == 4
2884 || INTVAL (XEXP (XEXP (x, 0), 1)) == 8))
2886 /* lea an@(dx:l:i),am */
2887 *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 2 : 3);
2897 *total = COSTS_N_INSNS(1);
2902 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2904 if (INTVAL (XEXP (x, 1)) < 16)
2905 *total = COSTS_N_INSNS (2) + INTVAL (XEXP (x, 1)) / 2;
2907 /* We're using clrw + swap for these cases. */
2908 *total = COSTS_N_INSNS (4) + (INTVAL (XEXP (x, 1)) - 16) / 2;
2911 *total = COSTS_N_INSNS (10); /* Worst case. */
2914 /* A shift by a big integer takes an extra instruction. */
2915 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2916 && (INTVAL (XEXP (x, 1)) == 16))
2918 *total = COSTS_N_INSNS (2); /* clrw;swap */
2921 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2922 && !(INTVAL (XEXP (x, 1)) > 0
2923 && INTVAL (XEXP (x, 1)) <= 8))
2925 *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 1 : 3); /* lsr #i,dn */
2931 if ((GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
2932 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
2933 && GET_MODE (x) == SImode)
2934 *total = COSTS_N_INSNS (MULW_COST);
2935 else if (GET_MODE (x) == QImode || GET_MODE (x) == HImode)
2936 *total = COSTS_N_INSNS (MULW_COST);
2938 *total = COSTS_N_INSNS (MULL_COST);
2945 if (GET_MODE (x) == QImode || GET_MODE (x) == HImode)
2946 *total = COSTS_N_INSNS (DIVW_COST); /* div.w */
2947 else if (TARGET_CF_HWDIV)
2948 *total = COSTS_N_INSNS (18);
2950 *total = COSTS_N_INSNS (43); /* div.l */
2954 if (outer_code == COMPARE)
2963 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2967 output_move_const_into_data_reg (rtx *operands)
2971 i = INTVAL (operands[1]);
2972 switch (m68k_const_method (i))
2975 return "mvzw %1,%0";
2977 return "mvsw %1,%0";
2979 return "moveq %1,%0";
2982 operands[1] = GEN_INT (i ^ 0xff);
2983 return "moveq %1,%0\n\tnot%.b %0";
2986 operands[1] = GEN_INT (i ^ 0xffff);
2987 return "moveq %1,%0\n\tnot%.w %0";
2990 return "moveq #-128,%0\n\tneg%.w %0";
2995 operands[1] = GEN_INT ((u << 16) | (u >> 16));
2996 return "moveq %1,%0\n\tswap %0";
2999 return "move%.l %1,%0";
3005 /* Return true if I can be handled by ISA B's mov3q instruction. */
3008 valid_mov3q_const (HOST_WIDE_INT i)
3010 return TARGET_ISAB && (i == -1 || IN_RANGE (i, 1, 7));
3013 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
3014 I is the value of OPERANDS[1]. */
3017 output_move_simode_const (rtx *operands)
3023 src = INTVAL (operands[1]);
3025 && (DATA_REG_P (dest) || MEM_P (dest))
3026 /* clr insns on 68000 read before writing. */
3027 && ((TARGET_68010 || TARGET_COLDFIRE)
3028 || !(MEM_P (dest) && MEM_VOLATILE_P (dest))))
3030 else if (GET_MODE (dest) == SImode && valid_mov3q_const (src))
3031 return "mov3q%.l %1,%0";
3032 else if (src == 0 && ADDRESS_REG_P (dest))
3033 return "sub%.l %0,%0";
3034 else if (DATA_REG_P (dest))
3035 return output_move_const_into_data_reg (operands);
3036 else if (ADDRESS_REG_P (dest) && IN_RANGE (src, -0x8000, 0x7fff))
3038 if (valid_mov3q_const (src))
3039 return "mov3q%.l %1,%0";
3040 return "move%.w %1,%0";
3042 else if (MEM_P (dest)
3043 && GET_CODE (XEXP (dest, 0)) == PRE_DEC
3044 && REGNO (XEXP (XEXP (dest, 0), 0)) == STACK_POINTER_REGNUM
3045 && IN_RANGE (src, -0x8000, 0x7fff))
3047 if (valid_mov3q_const (src))
3048 return "mov3q%.l %1,%-";
3051 return "move%.l %1,%0";
3055 output_move_simode (rtx *operands)
3057 if (GET_CODE (operands[1]) == CONST_INT)
3058 return output_move_simode_const (operands);
3059 else if ((GET_CODE (operands[1]) == SYMBOL_REF
3060 || GET_CODE (operands[1]) == CONST)
3061 && push_operand (operands[0], SImode))
3063 else if ((GET_CODE (operands[1]) == SYMBOL_REF
3064 || GET_CODE (operands[1]) == CONST)
3065 && ADDRESS_REG_P (operands[0]))
3066 return "lea %a1,%0";
3067 return "move%.l %1,%0";
3071 output_move_himode (rtx *operands)
3073 if (GET_CODE (operands[1]) == CONST_INT)
3075 if (operands[1] == const0_rtx
3076 && (DATA_REG_P (operands[0])
3077 || GET_CODE (operands[0]) == MEM)
3078 /* clr insns on 68000 read before writing. */
3079 && ((TARGET_68010 || TARGET_COLDFIRE)
3080 || !(GET_CODE (operands[0]) == MEM
3081 && MEM_VOLATILE_P (operands[0]))))
3083 else if (operands[1] == const0_rtx
3084 && ADDRESS_REG_P (operands[0]))
3085 return "sub%.l %0,%0";
3086 else if (DATA_REG_P (operands[0])
3087 && INTVAL (operands[1]) < 128
3088 && INTVAL (operands[1]) >= -128)
3089 return "moveq %1,%0";
3090 else if (INTVAL (operands[1]) < 0x8000
3091 && INTVAL (operands[1]) >= -0x8000)
3092 return "move%.w %1,%0";
3094 else if (CONSTANT_P (operands[1]))
3095 return "move%.l %1,%0";
3096 return "move%.w %1,%0";
3100 output_move_qimode (rtx *operands)
3102 /* 68k family always modifies the stack pointer by at least 2, even for
3103 byte pushes. The 5200 (ColdFire) does not do this. */
3105 /* This case is generated by pushqi1 pattern now. */
3106 gcc_assert (!(GET_CODE (operands[0]) == MEM
3107 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
3108 && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx
3109 && ! ADDRESS_REG_P (operands[1])
3110 && ! TARGET_COLDFIRE));
3112 /* clr and st insns on 68000 read before writing. */
3113 if (!ADDRESS_REG_P (operands[0])
3114 && ((TARGET_68010 || TARGET_COLDFIRE)
3115 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
3117 if (operands[1] == const0_rtx)
3119 if ((!TARGET_COLDFIRE || DATA_REG_P (operands[0]))
3120 && GET_CODE (operands[1]) == CONST_INT
3121 && (INTVAL (operands[1]) & 255) == 255)
3127 if (GET_CODE (operands[1]) == CONST_INT
3128 && DATA_REG_P (operands[0])
3129 && INTVAL (operands[1]) < 128
3130 && INTVAL (operands[1]) >= -128)
3131 return "moveq %1,%0";
3132 if (operands[1] == const0_rtx && ADDRESS_REG_P (operands[0]))
3133 return "sub%.l %0,%0";
3134 if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
3135 return "move%.l %1,%0";
3136 /* 68k family (including the 5200 ColdFire) does not support byte moves to
3137 from address registers. */
3138 if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
3139 return "move%.w %1,%0";
3140 return "move%.b %1,%0";
3144 output_move_stricthi (rtx *operands)
3146 if (operands[1] == const0_rtx
3147 /* clr insns on 68000 read before writing. */
3148 && ((TARGET_68010 || TARGET_COLDFIRE)
3149 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
3151 return "move%.w %1,%0";
3155 output_move_strictqi (rtx *operands)
3157 if (operands[1] == const0_rtx
3158 /* clr insns on 68000 read before writing. */
3159 && ((TARGET_68010 || TARGET_COLDFIRE)
3160 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
3162 return "move%.b %1,%0";
3165 /* Return the best assembler insn template
3166 for moving operands[1] into operands[0] as a fullword. */
3169 singlemove_string (rtx *operands)
3171 if (GET_CODE (operands[1]) == CONST_INT)
3172 return output_move_simode_const (operands);
3173 return "move%.l %1,%0";
3177 /* Output assembler or rtl code to perform a doubleword move insn
3178 with operands OPERANDS.
3179 Pointers to 3 helper functions should be specified:
3180 HANDLE_REG_ADJUST to adjust a register by a small value,
3181 HANDLE_COMPADR to compute an address and
3182 HANDLE_MOVSI to move 4 bytes. */
3185 handle_move_double (rtx operands[2],
3186 void (*handle_reg_adjust) (rtx, int),
3187 void (*handle_compadr) (rtx [2]),
3188 void (*handle_movsi) (rtx [2]))
3192 REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP
3197 rtx addreg0 = 0, addreg1 = 0;
3198 int dest_overlapped_low = 0;
3199 int size = GET_MODE_SIZE (GET_MODE (operands[0]));
3204 /* First classify both operands. */
3206 if (REG_P (operands[0]))
3208 else if (offsettable_memref_p (operands[0]))
3210 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
3212 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
3214 else if (GET_CODE (operands[0]) == MEM)
3219 if (REG_P (operands[1]))
3221 else if (CONSTANT_P (operands[1]))
3223 else if (offsettable_memref_p (operands[1]))
3225 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
3227 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
3229 else if (GET_CODE (operands[1]) == MEM)
3234 /* Check for the cases that the operand constraints are not supposed
3235 to allow to happen. Generating code for these cases is
3237 gcc_assert (optype0 != RNDOP && optype1 != RNDOP);
3239 /* If one operand is decrementing and one is incrementing
3240 decrement the former register explicitly
3241 and change that operand into ordinary indexing. */
3243 if (optype0 == PUSHOP && optype1 == POPOP)
3245 operands[0] = XEXP (XEXP (operands[0], 0), 0);
3247 handle_reg_adjust (operands[0], -size);
3249 if (GET_MODE (operands[1]) == XFmode)
3250 operands[0] = gen_rtx_MEM (XFmode, operands[0]);
3251 else if (GET_MODE (operands[0]) == DFmode)
3252 operands[0] = gen_rtx_MEM (DFmode, operands[0]);
3254 operands[0] = gen_rtx_MEM (DImode, operands[0]);
3257 if (optype0 == POPOP && optype1 == PUSHOP)
3259 operands[1] = XEXP (XEXP (operands[1], 0), 0);
3261 handle_reg_adjust (operands[1], -size);
3263 if (GET_MODE (operands[1]) == XFmode)
3264 operands[1] = gen_rtx_MEM (XFmode, operands[1]);
3265 else if (GET_MODE (operands[1]) == DFmode)
3266 operands[1] = gen_rtx_MEM (DFmode, operands[1]);
3268 operands[1] = gen_rtx_MEM (DImode, operands[1]);
3272 /* If an operand is an unoffsettable memory ref, find a register
3273 we can increment temporarily to make it refer to the second word. */
3275 if (optype0 == MEMOP)
3276 addreg0 = find_addr_reg (XEXP (operands[0], 0));
3278 if (optype1 == MEMOP)
3279 addreg1 = find_addr_reg (XEXP (operands[1], 0));
3281 /* Ok, we can do one word at a time.
3282 Normally we do the low-numbered word first,
3283 but if either operand is autodecrementing then we
3284 do the high-numbered word first.
3286 In either case, set up in LATEHALF the operands to use
3287 for the high-numbered word and in some cases alter the
3288 operands in OPERANDS to be suitable for the low-numbered word. */
3292 if (optype0 == REGOP)
3294 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2);
3295 middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3297 else if (optype0 == OFFSOP)
3299 middlehalf[0] = adjust_address (operands[0], SImode, 4);
3300 latehalf[0] = adjust_address (operands[0], SImode, size - 4);
3304 middlehalf[0] = adjust_address (operands[0], SImode, 0);
3305 latehalf[0] = adjust_address (operands[0], SImode, 0);
3308 if (optype1 == REGOP)
3310 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
3311 middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
3313 else if (optype1 == OFFSOP)
3315 middlehalf[1] = adjust_address (operands[1], SImode, 4);
3316 latehalf[1] = adjust_address (operands[1], SImode, size - 4);
3318 else if (optype1 == CNSTOP)
3320 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3325 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
3326 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
3327 operands[1] = GEN_INT (l[0]);
3328 middlehalf[1] = GEN_INT (l[1]);
3329 latehalf[1] = GEN_INT (l[2]);
3333 /* No non-CONST_DOUBLE constant should ever appear
3335 gcc_assert (!CONSTANT_P (operands[1]));
3340 middlehalf[1] = adjust_address (operands[1], SImode, 0);
3341 latehalf[1] = adjust_address (operands[1], SImode, 0);
3345 /* size is not 12: */
3347 if (optype0 == REGOP)
3348 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3349 else if (optype0 == OFFSOP)
3350 latehalf[0] = adjust_address (operands[0], SImode, size - 4);
3352 latehalf[0] = adjust_address (operands[0], SImode, 0);
3354 if (optype1 == REGOP)
3355 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
3356 else if (optype1 == OFFSOP)
3357 latehalf[1] = adjust_address (operands[1], SImode, size - 4);
3358 else if (optype1 == CNSTOP)
3359 split_double (operands[1], &operands[1], &latehalf[1]);
3361 latehalf[1] = adjust_address (operands[1], SImode, 0);
3364 /* If insn is effectively movd N(sp),-(sp) then we will do the
3365 high word first. We should use the adjusted operand 1 (which is N+4(sp))
3366 for the low word as well, to compensate for the first decrement of sp. */
3367 if (optype0 == PUSHOP
3368 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
3369 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
3370 operands[1] = middlehalf[1] = latehalf[1];
3372 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
3373 if the upper part of reg N does not appear in the MEM, arrange to
3374 emit the move late-half first. Otherwise, compute the MEM address
3375 into the upper part of N and use that as a pointer to the memory
3377 if (optype0 == REGOP
3378 && (optype1 == OFFSOP || optype1 == MEMOP))
3380 rtx testlow = gen_rtx_REG (SImode, REGNO (operands[0]));
3382 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
3383 && reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
3385 /* If both halves of dest are used in the src memory address,
3386 compute the address into latehalf of dest.
3387 Note that this can't happen if the dest is two data regs. */
3389 xops[0] = latehalf[0];
3390 xops[1] = XEXP (operands[1], 0);
3392 handle_compadr (xops);
3393 if (GET_MODE (operands[1]) == XFmode)
3395 operands[1] = gen_rtx_MEM (XFmode, latehalf[0]);
3396 middlehalf[1] = adjust_address (operands[1], DImode, size - 8);
3397 latehalf[1] = adjust_address (operands[1], DImode, size - 4);
3401 operands[1] = gen_rtx_MEM (DImode, latehalf[0]);
3402 latehalf[1] = adjust_address (operands[1], DImode, size - 4);
3406 && reg_overlap_mentioned_p (middlehalf[0],
3407 XEXP (operands[1], 0)))
3409 /* Check for two regs used by both source and dest.
3410 Note that this can't happen if the dest is all data regs.
3411 It can happen if the dest is d6, d7, a0.
3412 But in that case, latehalf is an addr reg, so
3413 the code at compadr does ok. */
3415 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
3416 || reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
3419 /* JRV says this can't happen: */
3420 gcc_assert (!addreg0 && !addreg1);
3422 /* Only the middle reg conflicts; simply put it last. */
3423 handle_movsi (operands);
3424 handle_movsi (latehalf);
3425 handle_movsi (middlehalf);
3429 else if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)))
3430 /* If the low half of dest is mentioned in the source memory
3431 address, the arrange to emit the move late half first. */
3432 dest_overlapped_low = 1;
3435 /* If one or both operands autodecrementing,
3436 do the two words, high-numbered first. */
3438 /* Likewise, the first move would clobber the source of the second one,
3439 do them in the other order. This happens only for registers;
3440 such overlap can't happen in memory unless the user explicitly
3441 sets it up, and that is an undefined circumstance. */
3443 if (optype0 == PUSHOP || optype1 == PUSHOP
3444 || (optype0 == REGOP && optype1 == REGOP
3445 && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1]))
3446 || REGNO (operands[0]) == REGNO (latehalf[1])))
3447 || dest_overlapped_low)
3449 /* Make any unoffsettable addresses point at high-numbered word. */
3451 handle_reg_adjust (addreg0, size - 4);
3453 handle_reg_adjust (addreg1, size - 4);
3456 handle_movsi (latehalf);
3458 /* Undo the adds we just did. */
3460 handle_reg_adjust (addreg0, -4);
3462 handle_reg_adjust (addreg1, -4);
3466 handle_movsi (middlehalf);
3469 handle_reg_adjust (addreg0, -4);
3471 handle_reg_adjust (addreg1, -4);
3474 /* Do low-numbered word. */
3476 handle_movsi (operands);
3480 /* Normal case: do the two words, low-numbered first. */
3482 handle_movsi (operands);
3484 /* Do the middle one of the three words for long double */
3488 handle_reg_adjust (addreg0, 4);
3490 handle_reg_adjust (addreg1, 4);
3492 handle_movsi (middlehalf);
3495 /* Make any unoffsettable addresses point at high-numbered word. */
3497 handle_reg_adjust (addreg0, 4);
3499 handle_reg_adjust (addreg1, 4);
3502 handle_movsi (latehalf);
3504 /* Undo the adds we just did. */
3506 handle_reg_adjust (addreg0, -(size - 4));
3508 handle_reg_adjust (addreg1, -(size - 4));
3513 /* Output assembler code to adjust REG by N. */
3515 output_reg_adjust (rtx reg, int n)
3519 gcc_assert (GET_MODE (reg) == SImode
3520 && -12 <= n && n != 0 && n <= 12);
3525 s = "add%.l #12,%0";
3529 s = "addq%.l #8,%0";
3533 s = "addq%.l #4,%0";
3537 s = "sub%.l #12,%0";
3541 s = "subq%.l #8,%0";
3545 s = "subq%.l #4,%0";
3553 output_asm_insn (s, ®);
3556 /* Emit rtl code to adjust REG by N. */
3558 emit_reg_adjust (rtx reg1, int n)
3562 gcc_assert (GET_MODE (reg1) == SImode
3563 && -12 <= n && n != 0 && n <= 12);
3565 reg1 = copy_rtx (reg1);
3566 reg2 = copy_rtx (reg1);
3569 emit_insn (gen_subsi3 (reg1, reg2, GEN_INT (-n)));
3571 emit_insn (gen_addsi3 (reg1, reg2, GEN_INT (n)));
3576 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
3578 output_compadr (rtx operands[2])
3580 output_asm_insn ("lea %a1,%0", operands);
3583 /* Output the best assembler insn for moving operands[1] into operands[0]
3586 output_movsi (rtx operands[2])
3588 output_asm_insn (singlemove_string (operands), operands);
3591 /* Copy OP and change its mode to MODE. */
3593 copy_operand (rtx op, enum machine_mode mode)
3595 /* ??? This looks really ugly. There must be a better way
3596 to change a mode on the operand. */
3597 if (GET_MODE (op) != VOIDmode)
3600 op = gen_rtx_REG (mode, REGNO (op));
3604 PUT_MODE (op, mode);
3611 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
3613 emit_movsi (rtx operands[2])
3615 operands[0] = copy_operand (operands[0], SImode);
3616 operands[1] = copy_operand (operands[1], SImode);
3618 emit_insn (gen_movsi (operands[0], operands[1]));
3621 /* Output assembler code to perform a doubleword move insn
3622 with operands OPERANDS. */
3624 output_move_double (rtx *operands)
3626 handle_move_double (operands,
3627 output_reg_adjust, output_compadr, output_movsi);
3632 /* Output rtl code to perform a doubleword move insn
3633 with operands OPERANDS. */
3635 m68k_emit_move_double (rtx operands[2])
3637 handle_move_double (operands, emit_reg_adjust, emit_movsi, emit_movsi);
3640 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
3641 new rtx with the correct mode. */
3644 force_mode (enum machine_mode mode, rtx orig)
3646 if (mode == GET_MODE (orig))
3649 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
3652 return gen_rtx_REG (mode, REGNO (orig));
3656 fp_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3658 return reg_renumber && FP_REG_P (op);
3661 /* Emit insns to move operands[1] into operands[0].
3663 Return 1 if we have written out everything that needs to be done to
3664 do the move. Otherwise, return 0 and the caller will emit the move
3667 Note SCRATCH_REG may not be in the proper mode depending on how it
3668 will be used. This routine is responsible for creating a new copy
3669 of SCRATCH_REG in the proper mode. */
3672 emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
3674 register rtx operand0 = operands[0];
3675 register rtx operand1 = operands[1];
3679 && reload_in_progress && GET_CODE (operand0) == REG
3680 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
3681 operand0 = reg_equiv_mem[REGNO (operand0)];
3682 else if (scratch_reg
3683 && reload_in_progress && GET_CODE (operand0) == SUBREG
3684 && GET_CODE (SUBREG_REG (operand0)) == REG
3685 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
3687 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3688 the code which tracks sets/uses for delete_output_reload. */
3689 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
3690 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
3691 SUBREG_BYTE (operand0));
3692 operand0 = alter_subreg (&temp);
3696 && reload_in_progress && GET_CODE (operand1) == REG
3697 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
3698 operand1 = reg_equiv_mem[REGNO (operand1)];
3699 else if (scratch_reg
3700 && reload_in_progress && GET_CODE (operand1) == SUBREG
3701 && GET_CODE (SUBREG_REG (operand1)) == REG
3702 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
3704 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3705 the code which tracks sets/uses for delete_output_reload. */
3706 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
3707 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
3708 SUBREG_BYTE (operand1));
3709 operand1 = alter_subreg (&temp);
3712 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
3713 && ((tem = find_replacement (&XEXP (operand0, 0)))
3714 != XEXP (operand0, 0)))
3715 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
3716 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
3717 && ((tem = find_replacement (&XEXP (operand1, 0)))
3718 != XEXP (operand1, 0)))
3719 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
3721 /* Handle secondary reloads for loads/stores of FP registers where
3722 the address is symbolic by using the scratch register */
3723 if (fp_reg_operand (operand0, mode)
3724 && ((GET_CODE (operand1) == MEM
3725 && ! memory_address_p (DFmode, XEXP (operand1, 0)))
3726 || ((GET_CODE (operand1) == SUBREG
3727 && GET_CODE (XEXP (operand1, 0)) == MEM
3728 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
3731 if (GET_CODE (operand1) == SUBREG)
3732 operand1 = XEXP (operand1, 0);
3734 /* SCRATCH_REG will hold an address. We want
3735 it in SImode regardless of what mode it was originally given
3737 scratch_reg = force_mode (SImode, scratch_reg);
3739 /* D might not fit in 14 bits either; for such cases load D into
3741 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
3743 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
3744 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
3746 XEXP (XEXP (operand1, 0), 0),
3750 emit_move_insn (scratch_reg, XEXP (operand1, 0));
3751 emit_insn (gen_rtx_SET (VOIDmode, operand0,
3752 gen_rtx_MEM (mode, scratch_reg)));
3755 else if (fp_reg_operand (operand1, mode)
3756 && ((GET_CODE (operand0) == MEM
3757 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
3758 || ((GET_CODE (operand0) == SUBREG)
3759 && GET_CODE (XEXP (operand0, 0)) == MEM
3760 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
3763 if (GET_CODE (operand0) == SUBREG)
3764 operand0 = XEXP (operand0, 0);
3766 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3767 it in SIMODE regardless of what mode it was originally given
3769 scratch_reg = force_mode (SImode, scratch_reg);
3771 /* D might not fit in 14 bits either; for such cases load D into
3773 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
3775 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
3776 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
3779 XEXP (XEXP (operand0, 0),
3784 emit_move_insn (scratch_reg, XEXP (operand0, 0));
3785 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
3789 /* Handle secondary reloads for loads of FP registers from constant
3790 expressions by forcing the constant into memory.
3792 use scratch_reg to hold the address of the memory location.
3794 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3795 NO_REGS when presented with a const_int and an register class
3796 containing only FP registers. Doing so unfortunately creates
3797 more problems than it solves. Fix this for 2.5. */
3798 else if (fp_reg_operand (operand0, mode)
3799 && CONSTANT_P (operand1)
3804 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3805 it in SIMODE regardless of what mode it was originally given
3807 scratch_reg = force_mode (SImode, scratch_reg);
3809 /* Force the constant into memory and put the address of the
3810 memory location into scratch_reg. */
3811 xoperands[0] = scratch_reg;
3812 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
3813 emit_insn (gen_rtx_SET (mode, scratch_reg, xoperands[1]));
3815 /* Now load the destination register. */
3816 emit_insn (gen_rtx_SET (mode, operand0,
3817 gen_rtx_MEM (mode, scratch_reg)));
3821 /* Now have insn-emit do whatever it normally does. */
3825 /* Split one or more DImode RTL references into pairs of SImode
3826 references. The RTL can be REG, offsettable MEM, integer constant, or
3827 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3828 split and "num" is its length. lo_half and hi_half are output arrays
3829 that parallel "operands". */
3832 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
3836 rtx op = operands[num];
3838 /* simplify_subreg refuses to split volatile memory addresses,
3839 but we still have to handle it. */
3840 if (GET_CODE (op) == MEM)
3842 lo_half[num] = adjust_address (op, SImode, 4);
3843 hi_half[num] = adjust_address (op, SImode, 0);
3847 lo_half[num] = simplify_gen_subreg (SImode, op,
3848 GET_MODE (op) == VOIDmode
3849 ? DImode : GET_MODE (op), 4);
3850 hi_half[num] = simplify_gen_subreg (SImode, op,
3851 GET_MODE (op) == VOIDmode
3852 ? DImode : GET_MODE (op), 0);
3857 /* Split X into a base and a constant offset, storing them in *BASE
3858 and *OFFSET respectively. */
3861 m68k_split_offset (rtx x, rtx *base, HOST_WIDE_INT *offset)
3864 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
3866 *offset += INTVAL (XEXP (x, 1));
3872 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3873 instruction. STORE_P says whether the move is a load or store.
3875 If the instruction uses post-increment or pre-decrement addressing,
3876 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3877 adjustment. This adjustment will be made by the first element of
3878 PARALLEL, with the loads or stores starting at element 1. If the
3879 instruction does not use post-increment or pre-decrement addressing,
3880 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3881 start at element 0. */
3884 m68k_movem_pattern_p (rtx pattern, rtx automod_base,
3885 HOST_WIDE_INT automod_offset, bool store_p)
3887 rtx base, mem_base, set, mem, reg, last_reg;
3888 HOST_WIDE_INT offset, mem_offset;
3890 enum reg_class rclass;
3892 len = XVECLEN (pattern, 0);
3893 first = (automod_base != NULL);
3897 /* Stores must be pre-decrement and loads must be post-increment. */
3898 if (store_p != (automod_offset < 0))
3901 /* Work out the base and offset for lowest memory location. */
3902 base = automod_base;
3903 offset = (automod_offset < 0 ? automod_offset : 0);
3907 /* Allow any valid base and offset in the first access. */
3914 for (i = first; i < len; i++)
3916 /* We need a plain SET. */
3917 set = XVECEXP (pattern, 0, i);
3918 if (GET_CODE (set) != SET)
3921 /* Check that we have a memory location... */
3922 mem = XEXP (set, !store_p);
3923 if (!MEM_P (mem) || !memory_operand (mem, VOIDmode))
3926 /* ...with the right address. */
3929 m68k_split_offset (XEXP (mem, 0), &base, &offset);
3930 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3931 There are no mode restrictions for 680x0 besides the
3932 automodification rules enforced above. */
3934 && !m68k_legitimate_base_reg_p (base, reload_completed))
3939 m68k_split_offset (XEXP (mem, 0), &mem_base, &mem_offset);
3940 if (!rtx_equal_p (base, mem_base) || offset != mem_offset)
3944 /* Check that we have a register of the required mode and class. */
3945 reg = XEXP (set, store_p);
3947 || !HARD_REGISTER_P (reg)
3948 || GET_MODE (reg) != reg_raw_mode[REGNO (reg)])
3953 /* The register must belong to RCLASS and have a higher number
3954 than the register in the previous SET. */
3955 if (!TEST_HARD_REG_BIT (reg_class_contents[rclass], REGNO (reg))
3956 || REGNO (last_reg) >= REGNO (reg))
3961 /* Work out which register class we need. */
3962 if (INT_REGNO_P (REGNO (reg)))
3963 rclass = GENERAL_REGS;
3964 else if (FP_REGNO_P (REGNO (reg)))
3971 offset += GET_MODE_SIZE (GET_MODE (reg));
3974 /* If we have an automodification, check whether the final offset is OK. */
3975 if (automod_base && offset != (automod_offset < 0 ? 0 : automod_offset))
3978 /* Reject unprofitable cases. */
3979 if (len < first + (rclass == FP_REGS ? MIN_FMOVEM_REGS : MIN_MOVEM_REGS))
3985 /* Return the assembly code template for a movem or fmovem instruction
3986 whose pattern is given by PATTERN. Store the template's operands
3989 If the instruction uses post-increment or pre-decrement addressing,
3990 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3991 is true if this is a store instruction. */
3994 m68k_output_movem (rtx *operands, rtx pattern,
3995 HOST_WIDE_INT automod_offset, bool store_p)
4000 gcc_assert (GET_CODE (pattern) == PARALLEL);
4002 first = (automod_offset != 0);
4003 for (i = first; i < XVECLEN (pattern, 0); i++)
4005 /* When using movem with pre-decrement addressing, register X + D0_REG
4006 is controlled by bit 15 - X. For all other addressing modes,
4007 register X + D0_REG is controlled by bit X. Confusingly, the
4008 register mask for fmovem is in the opposite order to that for
4012 gcc_assert (MEM_P (XEXP (XVECEXP (pattern, 0, i), !store_p)));
4013 gcc_assert (REG_P (XEXP (XVECEXP (pattern, 0, i), store_p)));
4014 regno = REGNO (XEXP (XVECEXP (pattern, 0, i), store_p));
4015 if (automod_offset < 0)
4017 if (FP_REGNO_P (regno))
4018 mask |= 1 << (regno - FP0_REG);
4020 mask |= 1 << (15 - (regno - D0_REG));
4024 if (FP_REGNO_P (regno))
4025 mask |= 1 << (7 - (regno - FP0_REG));
4027 mask |= 1 << (regno - D0_REG);
4032 if (automod_offset == 0)
4033 operands[0] = XEXP (XEXP (XVECEXP (pattern, 0, first), !store_p), 0);
4034 else if (automod_offset < 0)
4035 operands[0] = gen_rtx_PRE_DEC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0)));
4037 operands[0] = gen_rtx_POST_INC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0)));
4038 operands[1] = GEN_INT (mask);
4039 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern, 0, first), store_p))))
4042 return "fmovem %1,%a0";
4044 return "fmovem %a0,%1";
4049 return "movem%.l %1,%a0";
4051 return "movem%.l %a0,%1";
4055 /* Return a REG that occurs in ADDR with coefficient 1.
4056 ADDR can be effectively incremented by incrementing REG. */
4059 find_addr_reg (rtx addr)
4061 while (GET_CODE (addr) == PLUS)
4063 if (GET_CODE (XEXP (addr, 0)) == REG)
4064 addr = XEXP (addr, 0);
4065 else if (GET_CODE (XEXP (addr, 1)) == REG)
4066 addr = XEXP (addr, 1);
4067 else if (CONSTANT_P (XEXP (addr, 0)))
4068 addr = XEXP (addr, 1);
4069 else if (CONSTANT_P (XEXP (addr, 1)))
4070 addr = XEXP (addr, 0);
4074 gcc_assert (GET_CODE (addr) == REG);
4078 /* Output assembler code to perform a 32-bit 3-operand add. */
4081 output_addsi3 (rtx *operands)
4083 if (! operands_match_p (operands[0], operands[1]))
4085 if (!ADDRESS_REG_P (operands[1]))
4087 rtx tmp = operands[1];
4089 operands[1] = operands[2];
4093 /* These insns can result from reloads to access
4094 stack slots over 64k from the frame pointer. */
4095 if (GET_CODE (operands[2]) == CONST_INT
4096 && (INTVAL (operands[2]) < -32768 || INTVAL (operands[2]) > 32767))
4097 return "move%.l %2,%0\n\tadd%.l %1,%0";
4098 if (GET_CODE (operands[2]) == REG)
4099 return MOTOROLA ? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
4100 return MOTOROLA ? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
4102 if (GET_CODE (operands[2]) == CONST_INT)
4104 if (INTVAL (operands[2]) > 0
4105 && INTVAL (operands[2]) <= 8)
4106 return "addq%.l %2,%0";
4107 if (INTVAL (operands[2]) < 0
4108 && INTVAL (operands[2]) >= -8)
4110 operands[2] = GEN_INT (- INTVAL (operands[2]));
4111 return "subq%.l %2,%0";
4113 /* On the CPU32 it is faster to use two addql instructions to
4114 add a small integer (8 < N <= 16) to a register.
4115 Likewise for subql. */
4116 if (TUNE_CPU32 && REG_P (operands[0]))
4118 if (INTVAL (operands[2]) > 8
4119 && INTVAL (operands[2]) <= 16)
4121 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
4122 return "addq%.l #8,%0\n\taddq%.l %2,%0";
4124 if (INTVAL (operands[2]) < -8
4125 && INTVAL (operands[2]) >= -16)
4127 operands[2] = GEN_INT (- INTVAL (operands[2]) - 8);
4128 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
4131 if (ADDRESS_REG_P (operands[0])
4132 && INTVAL (operands[2]) >= -0x8000
4133 && INTVAL (operands[2]) < 0x8000)
4136 return "add%.w %2,%0";
4138 return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
4141 return "add%.l %2,%0";
4144 /* Store in cc_status the expressions that the condition codes will
4145 describe after execution of an instruction whose pattern is EXP.
4146 Do not alter them if the instruction would not alter the cc's. */
4148 /* On the 68000, all the insns to store in an address register fail to
4149 set the cc's. However, in some cases these instructions can make it
4150 possibly invalid to use the saved cc's. In those cases we clear out
4151 some or all of the saved cc's so they won't be used. */
4154 notice_update_cc (rtx exp, rtx insn)
4156 if (GET_CODE (exp) == SET)
4158 if (GET_CODE (SET_SRC (exp)) == CALL)
4160 else if (ADDRESS_REG_P (SET_DEST (exp)))
4162 if (cc_status.value1 && modified_in_p (cc_status.value1, insn))
4163 cc_status.value1 = 0;
4164 if (cc_status.value2 && modified_in_p (cc_status.value2, insn))
4165 cc_status.value2 = 0;
4167 /* fmoves to memory or data registers do not set the condition
4168 codes. Normal moves _do_ set the condition codes, but not in
4169 a way that is appropriate for comparison with 0, because -0.0
4170 would be treated as a negative nonzero number. Note that it
4171 isn't appropriate to conditionalize this restriction on
4172 HONOR_SIGNED_ZEROS because that macro merely indicates whether
4173 we care about the difference between -0.0 and +0.0. */
4174 else if (!FP_REG_P (SET_DEST (exp))
4175 && SET_DEST (exp) != cc0_rtx
4176 && (FP_REG_P (SET_SRC (exp))
4177 || GET_CODE (SET_SRC (exp)) == FIX
4178 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp)))))
4180 /* A pair of move insns doesn't produce a useful overall cc. */
4181 else if (!FP_REG_P (SET_DEST (exp))
4182 && !FP_REG_P (SET_SRC (exp))
4183 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4
4184 && (GET_CODE (SET_SRC (exp)) == REG
4185 || GET_CODE (SET_SRC (exp)) == MEM
4186 || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE))
4188 else if (SET_DEST (exp) != pc_rtx)
4190 cc_status.flags = 0;
4191 cc_status.value1 = SET_DEST (exp);
4192 cc_status.value2 = SET_SRC (exp);
4195 else if (GET_CODE (exp) == PARALLEL
4196 && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
4198 rtx dest = SET_DEST (XVECEXP (exp, 0, 0));
4199 rtx src = SET_SRC (XVECEXP (exp, 0, 0));
4201 if (ADDRESS_REG_P (dest))
4203 else if (dest != pc_rtx)
4205 cc_status.flags = 0;
4206 cc_status.value1 = dest;
4207 cc_status.value2 = src;
4212 if (cc_status.value2 != 0
4213 && ADDRESS_REG_P (cc_status.value2)
4214 && GET_MODE (cc_status.value2) == QImode)
4216 if (cc_status.value2 != 0)
4217 switch (GET_CODE (cc_status.value2))
4219 case ASHIFT: case ASHIFTRT: case LSHIFTRT:
4220 case ROTATE: case ROTATERT:
4221 /* These instructions always clear the overflow bit, and set
4222 the carry to the bit shifted out. */
4223 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
4226 case PLUS: case MINUS: case MULT:
4227 case DIV: case UDIV: case MOD: case UMOD: case NEG:
4228 if (GET_MODE (cc_status.value2) != VOIDmode)
4229 cc_status.flags |= CC_NO_OVERFLOW;
4232 /* (SET r1 (ZERO_EXTEND r2)) on this machine
4233 ends with a move insn moving r2 in r2's mode.
4234 Thus, the cc's are set for r2.
4235 This can set N bit spuriously. */
4236 cc_status.flags |= CC_NOT_NEGATIVE;
4241 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG
4243 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
4244 cc_status.value2 = 0;
4245 if (((cc_status.value1 && FP_REG_P (cc_status.value1))
4246 || (cc_status.value2 && FP_REG_P (cc_status.value2))))
4247 cc_status.flags = CC_IN_68881;
4248 if (cc_status.value2 && GET_CODE (cc_status.value2) == COMPARE
4249 && GET_MODE_CLASS (GET_MODE (XEXP (cc_status.value2, 0))) == MODE_FLOAT)
4251 cc_status.flags = CC_IN_68881;
4252 if (!FP_REG_P (XEXP (cc_status.value2, 0)))
4253 cc_status.flags |= CC_REVERSED;
4258 output_move_const_double (rtx *operands)
4260 int code = standard_68881_constant_p (operands[1]);
4264 static char buf[40];
4266 sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff);
4269 return "fmove%.d %1,%0";
4273 output_move_const_single (rtx *operands)
4275 int code = standard_68881_constant_p (operands[1]);
4279 static char buf[40];
4281 sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff);
4284 return "fmove%.s %f1,%0";
4287 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
4288 from the "fmovecr" instruction.
4289 The value, anded with 0xff, gives the code to use in fmovecr
4290 to get the desired constant. */
4292 /* This code has been fixed for cross-compilation. */
4294 static int inited_68881_table = 0;
4296 static const char *const strings_68881[7] = {
4306 static const int codes_68881[7] = {
4316 REAL_VALUE_TYPE values_68881[7];
4318 /* Set up values_68881 array by converting the decimal values
4319 strings_68881 to binary. */
4322 init_68881_table (void)
4326 enum machine_mode mode;
4329 for (i = 0; i < 7; i++)
4333 r = REAL_VALUE_ATOF (strings_68881[i], mode);
4334 values_68881[i] = r;
4336 inited_68881_table = 1;
4340 standard_68881_constant_p (rtx x)
4345 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
4346 used at all on those chips. */
4350 if (! inited_68881_table)
4351 init_68881_table ();
4353 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4355 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
4357 for (i = 0; i < 6; i++)
4359 if (REAL_VALUES_IDENTICAL (r, values_68881[i]))
4360 return (codes_68881[i]);
4363 if (GET_MODE (x) == SFmode)
4366 if (REAL_VALUES_EQUAL (r, values_68881[6]))
4367 return (codes_68881[6]);
4369 /* larger powers of ten in the constants ram are not used
4370 because they are not equal to a `double' C constant. */
4374 /* If X is a floating-point constant, return the logarithm of X base 2,
4375 or 0 if X is not a power of 2. */
4378 floating_exact_log2 (rtx x)
4380 REAL_VALUE_TYPE r, r1;
4383 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4385 if (REAL_VALUES_LESS (r, dconst1))
4388 exp = real_exponent (&r);
4389 real_2expN (&r1, exp, DFmode);
4390 if (REAL_VALUES_EQUAL (r1, r))
4396 /* A C compound statement to output to stdio stream STREAM the
4397 assembler syntax for an instruction operand X. X is an RTL
4400 CODE is a value that can be used to specify one of several ways
4401 of printing the operand. It is used when identical operands
4402 must be printed differently depending on the context. CODE
4403 comes from the `%' specification that was used to request
4404 printing of the operand. If the specification was just `%DIGIT'
4405 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4406 is the ASCII code for LTR.
4408 If X is a register, this macro should print the register's name.
4409 The names can be found in an array `reg_names' whose type is
4410 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4412 When the machine description has a specification `%PUNCT' (a `%'
4413 followed by a punctuation character), this macro is called with
4414 a null pointer for X and the punctuation character for CODE.
4416 The m68k specific codes are:
4418 '.' for dot needed in Motorola-style opcode names.
4419 '-' for an operand pushing on the stack:
4420 sp@-, -(sp) or -(%sp) depending on the style of syntax.
4421 '+' for an operand pushing on the stack:
4422 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
4423 '@' for a reference to the top word on the stack:
4424 sp@, (sp) or (%sp) depending on the style of syntax.
4425 '#' for an immediate operand prefix (# in MIT and Motorola syntax
4426 but & in SGS syntax).
4427 '!' for the cc register (used in an `and to cc' insn).
4428 '$' for the letter `s' in an op code, but only on the 68040.
4429 '&' for the letter `d' in an op code, but only on the 68040.
4430 '/' for register prefix needed by longlong.h.
4431 '?' for m68k_library_id_string
4433 'b' for byte insn (no effect, on the Sun; this is for the ISI).
4434 'd' to force memory addressing to be absolute, not relative.
4435 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
4436 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
4437 or print pair of registers as rx:ry.
4438 'p' print an address with @PLTPC attached, but only if the operand
4439 is not locally-bound. */
4442 print_operand (FILE *file, rtx op, int letter)
4447 fprintf (file, ".");
4449 else if (letter == '#')
4450 asm_fprintf (file, "%I");
4451 else if (letter == '-')
4452 asm_fprintf (file, MOTOROLA ? "-(%Rsp)" : "%Rsp@-");
4453 else if (letter == '+')
4454 asm_fprintf (file, MOTOROLA ? "(%Rsp)+" : "%Rsp@+");
4455 else if (letter == '@')
4456 asm_fprintf (file, MOTOROLA ? "(%Rsp)" : "%Rsp@");
4457 else if (letter == '!')
4458 asm_fprintf (file, "%Rfpcr");
4459 else if (letter == '$')
4462 fprintf (file, "s");
4464 else if (letter == '&')
4467 fprintf (file, "d");
4469 else if (letter == '/')
4470 asm_fprintf (file, "%R");
4471 else if (letter == '?')
4472 asm_fprintf (file, m68k_library_id_string);
4473 else if (letter == 'p')
4475 output_addr_const (file, op);
4476 if (!(GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op)))
4477 fprintf (file, "@PLTPC");
4479 else if (GET_CODE (op) == REG)
4482 /* Print out the second register name of a register pair.
4483 I.e., R (6) => 7. */
4484 fputs (M68K_REGNAME(REGNO (op) + 1), file);
4486 fputs (M68K_REGNAME(REGNO (op)), file);
4488 else if (GET_CODE (op) == MEM)
4490 output_address (XEXP (op, 0));
4491 if (letter == 'd' && ! TARGET_68020
4492 && CONSTANT_ADDRESS_P (XEXP (op, 0))
4493 && !(GET_CODE (XEXP (op, 0)) == CONST_INT
4494 && INTVAL (XEXP (op, 0)) < 0x8000
4495 && INTVAL (XEXP (op, 0)) >= -0x8000))
4496 fprintf (file, MOTOROLA ? ".l" : ":l");
4498 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode)
4502 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
4503 REAL_VALUE_TO_TARGET_SINGLE (r, l);
4504 asm_fprintf (file, "%I0x%lx", l & 0xFFFFFFFF);
4506 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode)
4510 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
4511 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
4512 asm_fprintf (file, "%I0x%lx%08lx%08lx", l[0] & 0xFFFFFFFF,
4513 l[1] & 0xFFFFFFFF, l[2] & 0xFFFFFFFF);
4515 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode)
4519 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
4520 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
4521 asm_fprintf (file, "%I0x%lx%08lx", l[0] & 0xFFFFFFFF, l[1] & 0xFFFFFFFF);
4525 /* Use `print_operand_address' instead of `output_addr_const'
4526 to ensure that we print relevant PIC stuff. */
4527 asm_fprintf (file, "%I");
4529 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST))
4530 print_operand_address (file, op);
4532 output_addr_const (file, op);
4536 /* Return string for TLS relocation RELOC. */
4539 m68k_get_reloc_decoration (enum m68k_reloc reloc)
4541 /* To my knowledge, !MOTOROLA assemblers don't support TLS. */
4542 gcc_assert (MOTOROLA || reloc == RELOC_GOT);
4549 if (flag_pic == 1 && TARGET_68020)
4590 /* m68k implementation of OUTPUT_ADDR_CONST_EXTRA. */
4593 m68k_output_addr_const_extra (FILE *file, rtx x)
4595 if (GET_CODE (x) == UNSPEC)
4597 switch (XINT (x, 1))
4599 case UNSPEC_RELOC16:
4600 case UNSPEC_RELOC32:
4601 output_addr_const (file, XVECEXP (x, 0, 0));
4602 fputs (m68k_get_reloc_decoration
4603 ((enum m68k_reloc) INTVAL (XVECEXP (x, 0, 1))), file);
4614 /* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
4617 m68k_output_dwarf_dtprel (FILE *file, int size, rtx x)
4619 gcc_assert (size == 4);
4620 fputs ("\t.long\t", file);
4621 output_addr_const (file, x);
4622 fputs ("@TLSLDO+0x8000", file);
4625 /* In the name of slightly smaller debug output, and to cater to
4626 general assembler lossage, recognize various UNSPEC sequences
4627 and turn them back into a direct symbol reference. */
4630 m68k_delegitimize_address (rtx orig_x)
4633 rtx addend = NULL_RTX;
4636 orig_x = delegitimize_mem_from_attrs (orig_x);
4637 if (! MEM_P (orig_x))
4640 x = XEXP (orig_x, 0);
4642 if (GET_CODE (x) == PLUS
4643 && GET_CODE (XEXP (x, 1)) == CONST
4644 && REG_P (XEXP (x, 0))
4645 && REGNO (XEXP (x, 0)) == PIC_REG)
4647 y = x = XEXP (XEXP (x, 1), 0);
4649 /* Handle an addend. */
4650 if ((GET_CODE (x) == PLUS || GET_CODE (x) == MINUS)
4651 && CONST_INT_P (XEXP (x, 1)))
4653 addend = XEXP (x, 1);
4657 if (GET_CODE (x) == UNSPEC
4658 && (XINT (x, 1) == UNSPEC_RELOC16
4659 || XINT (x, 1) == UNSPEC_RELOC32))
4661 result = XVECEXP (x, 0, 0);
4664 if (GET_CODE (y) == PLUS)
4665 result = gen_rtx_PLUS (Pmode, result, addend);
4667 result = gen_rtx_MINUS (Pmode, result, addend);
4668 result = gen_rtx_CONST (Pmode, result);
4678 /* A C compound statement to output to stdio stream STREAM the
4679 assembler syntax for an instruction operand that is a memory
4680 reference whose address is ADDR. ADDR is an RTL expression.
4682 Note that this contains a kludge that knows that the only reason
4683 we have an address (plus (label_ref...) (reg...)) when not generating
4684 PIC code is in the insn before a tablejump, and we know that m68k.md
4685 generates a label LInnn: on such an insn.
4687 It is possible for PIC to generate a (plus (label_ref...) (reg...))
4688 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
4690 This routine is responsible for distinguishing between -fpic and -fPIC
4691 style relocations in an address. When generating -fpic code the
4692 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
4693 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
4696 print_operand_address (FILE *file, rtx addr)
4698 struct m68k_address address;
4700 if (!m68k_decompose_address (QImode, addr, true, &address))
4703 if (address.code == PRE_DEC)
4704 fprintf (file, MOTOROLA ? "-(%s)" : "%s@-",
4705 M68K_REGNAME (REGNO (address.base)));
4706 else if (address.code == POST_INC)
4707 fprintf (file, MOTOROLA ? "(%s)+" : "%s@+",
4708 M68K_REGNAME (REGNO (address.base)));
4709 else if (!address.base && !address.index)
4711 /* A constant address. */
4712 gcc_assert (address.offset == addr);
4713 if (GET_CODE (addr) == CONST_INT)
4715 /* (xxx).w or (xxx).l. */
4716 if (IN_RANGE (INTVAL (addr), -0x8000, 0x7fff))
4717 fprintf (file, MOTOROLA ? "%d.w" : "%d:w", (int) INTVAL (addr));
4719 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (addr));
4721 else if (TARGET_PCREL)
4723 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
4725 output_addr_const (file, addr);
4726 asm_fprintf (file, flag_pic == 1 ? ":w,%Rpc)" : ":l,%Rpc)");
4730 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
4731 name ends in `.<letter>', as the last 2 characters can be
4732 mistaken as a size suffix. Put the name in parentheses. */
4733 if (GET_CODE (addr) == SYMBOL_REF
4734 && strlen (XSTR (addr, 0)) > 2
4735 && XSTR (addr, 0)[strlen (XSTR (addr, 0)) - 2] == '.')
4738 output_addr_const (file, addr);
4742 output_addr_const (file, addr);
4749 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
4750 label being accessed, otherwise it is -1. */
4751 labelno = (address.offset
4753 && GET_CODE (address.offset) == LABEL_REF
4754 ? CODE_LABEL_NUMBER (XEXP (address.offset, 0))
4758 /* Print the "offset(base" component. */
4760 asm_fprintf (file, "%LL%d(%Rpc,", labelno);
4764 output_addr_const (file, address.offset);
4768 fputs (M68K_REGNAME (REGNO (address.base)), file);
4770 /* Print the ",index" component, if any. */
4775 fprintf (file, "%s.%c",
4776 M68K_REGNAME (REGNO (address.index)),
4777 GET_MODE (address.index) == HImode ? 'w' : 'l');
4778 if (address.scale != 1)
4779 fprintf (file, "*%d", address.scale);
4783 else /* !MOTOROLA */
4785 if (!address.offset && !address.index)
4786 fprintf (file, "%s@", M68K_REGNAME (REGNO (address.base)));
4789 /* Print the "base@(offset" component. */
4791 asm_fprintf (file, "%Rpc@(%LL%d", labelno);
4795 fputs (M68K_REGNAME (REGNO (address.base)), file);
4796 fprintf (file, "@(");
4798 output_addr_const (file, address.offset);
4800 /* Print the ",index" component, if any. */
4803 fprintf (file, ",%s:%c",
4804 M68K_REGNAME (REGNO (address.index)),
4805 GET_MODE (address.index) == HImode ? 'w' : 'l');
4806 if (address.scale != 1)
4807 fprintf (file, ":%d", address.scale);
4815 /* Check for cases where a clr insns can be omitted from code using
4816 strict_low_part sets. For example, the second clrl here is not needed:
4817 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
4819 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
4820 insn we are checking for redundancy. TARGET is the register set by the
4824 strict_low_part_peephole_ok (enum machine_mode mode, rtx first_insn,
4829 while ((p = PREV_INSN (p)))
4831 if (NOTE_INSN_BASIC_BLOCK_P (p))
4837 /* If it isn't an insn, then give up. */
4841 if (reg_set_p (target, p))
4843 rtx set = single_set (p);
4846 /* If it isn't an easy to recognize insn, then give up. */
4850 dest = SET_DEST (set);
4852 /* If this sets the entire target register to zero, then our
4853 first_insn is redundant. */
4854 if (rtx_equal_p (dest, target)
4855 && SET_SRC (set) == const0_rtx)
4857 else if (GET_CODE (dest) == STRICT_LOW_PART
4858 && GET_CODE (XEXP (dest, 0)) == REG
4859 && REGNO (XEXP (dest, 0)) == REGNO (target)
4860 && (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0)))
4861 <= GET_MODE_SIZE (mode)))
4862 /* This is a strict low part set which modifies less than
4863 we are using, so it is safe. */
4873 /* Operand predicates for implementing asymmetric pc-relative addressing
4874 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4875 when used as a source operand, but not as a destination operand.
4877 We model this by restricting the meaning of the basic predicates
4878 (general_operand, memory_operand, etc) to forbid the use of this
4879 addressing mode, and then define the following predicates that permit
4880 this addressing mode. These predicates can then be used for the
4881 source operands of the appropriate instructions.
4883 n.b. While it is theoretically possible to change all machine patterns
4884 to use this addressing more where permitted by the architecture,
4885 it has only been implemented for "common" cases: SImode, HImode, and
4886 QImode operands, and only for the principle operations that would
4887 require this addressing mode: data movement and simple integer operations.
4889 In parallel with these new predicates, two new constraint letters
4890 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4891 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4892 In the pcrel case 's' is only valid in combination with 'a' registers.
4893 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4894 of how these constraints are used.
4896 The use of these predicates is strictly optional, though patterns that
4897 don't will cause an extra reload register to be allocated where one
4900 lea (abc:w,%pc),%a0 ; need to reload address
4901 moveq &1,%d1 ; since write to pc-relative space
4902 movel %d1,%a0@ ; is not allowed
4904 lea (abc:w,%pc),%a1 ; no need to reload address here
4905 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4907 For more info, consult tiemann@cygnus.com.
4910 All of the ugliness with predicates and constraints is due to the
4911 simple fact that the m68k does not allow a pc-relative addressing
4912 mode as a destination. gcc does not distinguish between source and
4913 destination addresses. Hence, if we claim that pc-relative address
4914 modes are valid, e.g. TARGET_LEGITIMATE_ADDRESS_P accepts them, then we
4915 end up with invalid code. To get around this problem, we left
4916 pc-relative modes as invalid addresses, and then added special
4917 predicates and constraints to accept them.
4919 A cleaner way to handle this is to modify gcc to distinguish
4920 between source and destination addresses. We can then say that
4921 pc-relative is a valid source address but not a valid destination
4922 address, and hopefully avoid a lot of the predicate and constraint
4923 hackery. Unfortunately, this would be a pretty big change. It would
4924 be a useful change for a number of ports, but there aren't any current
4925 plans to undertake this.
4927 ***************************************************************************/
4931 output_andsi3 (rtx *operands)
4934 if (GET_CODE (operands[2]) == CONST_INT
4935 && (INTVAL (operands[2]) | 0xffff) == -1
4936 && (DATA_REG_P (operands[0])
4937 || offsettable_memref_p (operands[0]))
4938 && !TARGET_COLDFIRE)
4940 if (GET_CODE (operands[0]) != REG)
4941 operands[0] = adjust_address (operands[0], HImode, 2);
4942 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
4943 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4945 if (operands[2] == const0_rtx)
4947 return "and%.w %2,%0";
4949 if (GET_CODE (operands[2]) == CONST_INT
4950 && (logval = exact_log2 (~ INTVAL (operands[2]) & 0xffffffff)) >= 0
4951 && (DATA_REG_P (operands[0])
4952 || offsettable_memref_p (operands[0])))
4954 if (DATA_REG_P (operands[0]))
4955 operands[1] = GEN_INT (logval);
4958 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
4959 operands[1] = GEN_INT (logval % 8);
4961 /* This does not set condition codes in a standard way. */
4963 return "bclr %1,%0";
4965 return "and%.l %2,%0";
4969 output_iorsi3 (rtx *operands)
4971 register int logval;
4972 if (GET_CODE (operands[2]) == CONST_INT
4973 && INTVAL (operands[2]) >> 16 == 0
4974 && (DATA_REG_P (operands[0])
4975 || offsettable_memref_p (operands[0]))
4976 && !TARGET_COLDFIRE)
4978 if (GET_CODE (operands[0]) != REG)
4979 operands[0] = adjust_address (operands[0], HImode, 2);
4980 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4982 if (INTVAL (operands[2]) == 0xffff)
4983 return "mov%.w %2,%0";
4984 return "or%.w %2,%0";
4986 if (GET_CODE (operands[2]) == CONST_INT
4987 && (logval = exact_log2 (INTVAL (operands[2]) & 0xffffffff)) >= 0
4988 && (DATA_REG_P (operands[0])
4989 || offsettable_memref_p (operands[0])))
4991 if (DATA_REG_P (operands[0]))
4992 operands[1] = GEN_INT (logval);
4995 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
4996 operands[1] = GEN_INT (logval % 8);
4999 return "bset %1,%0";
5001 return "or%.l %2,%0";
5005 output_xorsi3 (rtx *operands)
5007 register int logval;
5008 if (GET_CODE (operands[2]) == CONST_INT
5009 && INTVAL (operands[2]) >> 16 == 0
5010 && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0]))
5011 && !TARGET_COLDFIRE)
5013 if (! DATA_REG_P (operands[0]))
5014 operands[0] = adjust_address (operands[0], HImode, 2);
5015 /* Do not delete a following tstl %0 insn; that would be incorrect. */
5017 if (INTVAL (operands[2]) == 0xffff)
5019 return "eor%.w %2,%0";
5021 if (GET_CODE (operands[2]) == CONST_INT
5022 && (logval = exact_log2 (INTVAL (operands[2]) & 0xffffffff)) >= 0
5023 && (DATA_REG_P (operands[0])
5024 || offsettable_memref_p (operands[0])))
5026 if (DATA_REG_P (operands[0]))
5027 operands[1] = GEN_INT (logval);
5030 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
5031 operands[1] = GEN_INT (logval % 8);
5034 return "bchg %1,%0";
5036 return "eor%.l %2,%0";
5039 /* Return the instruction that should be used for a call to address X,
5040 which is known to be in operand 0. */
5045 if (symbolic_operand (x, VOIDmode))
5046 return m68k_symbolic_call;
5051 /* Likewise sibling calls. */
5054 output_sibcall (rtx x)
5056 if (symbolic_operand (x, VOIDmode))
5057 return m68k_symbolic_jump;
5063 m68k_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
5064 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
5067 rtx this_slot, offset, addr, mem, insn, tmp;
5069 /* Avoid clobbering the struct value reg by using the
5070 static chain reg as a temporary. */
5071 tmp = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
5073 /* Pretend to be a post-reload pass while generating rtl. */
5074 reload_completed = 1;
5076 /* The "this" pointer is stored at 4(%sp). */
5077 this_slot = gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, 4));
5079 /* Add DELTA to THIS. */
5082 /* Make the offset a legitimate operand for memory addition. */
5083 offset = GEN_INT (delta);
5084 if ((delta < -8 || delta > 8)
5085 && (TARGET_COLDFIRE || USE_MOVQ (delta)))
5087 emit_move_insn (gen_rtx_REG (Pmode, D0_REG), offset);
5088 offset = gen_rtx_REG (Pmode, D0_REG);
5090 emit_insn (gen_add3_insn (copy_rtx (this_slot),
5091 copy_rtx (this_slot), offset));
5094 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
5095 if (vcall_offset != 0)
5097 /* Set the static chain register to *THIS. */
5098 emit_move_insn (tmp, this_slot);
5099 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
5101 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
5102 addr = plus_constant (tmp, vcall_offset);
5103 if (!m68k_legitimate_address_p (Pmode, addr, true))
5105 emit_insn (gen_rtx_SET (VOIDmode, tmp, addr));
5109 /* Load the offset into %d0 and add it to THIS. */
5110 emit_move_insn (gen_rtx_REG (Pmode, D0_REG),
5111 gen_rtx_MEM (Pmode, addr));
5112 emit_insn (gen_add3_insn (copy_rtx (this_slot),
5113 copy_rtx (this_slot),
5114 gen_rtx_REG (Pmode, D0_REG)));
5117 /* Jump to the target function. Use a sibcall if direct jumps are
5118 allowed, otherwise load the address into a register first. */
5119 mem = DECL_RTL (function);
5120 if (!sibcall_operand (XEXP (mem, 0), VOIDmode))
5122 gcc_assert (flag_pic);
5124 if (!TARGET_SEP_DATA)
5126 /* Use the static chain register as a temporary (call-clobbered)
5127 GOT pointer for this function. We can use the static chain
5128 register because it isn't live on entry to the thunk. */
5129 SET_REGNO (pic_offset_table_rtx, STATIC_CHAIN_REGNUM);
5130 emit_insn (gen_load_got (pic_offset_table_rtx));
5132 legitimize_pic_address (XEXP (mem, 0), Pmode, tmp);
5133 mem = replace_equiv_address (mem, tmp);
5135 insn = emit_call_insn (gen_sibcall (mem, const0_rtx));
5136 SIBLING_CALL_P (insn) = 1;
5138 /* Run just enough of rest_of_compilation. */
5139 insn = get_insns ();
5140 split_all_insns_noflow ();
5141 final_start_function (insn, file, 1);
5142 final (insn, file, 1);
5143 final_end_function ();
5145 /* Clean up the vars set above. */
5146 reload_completed = 0;
5148 /* Restore the original PIC register. */
5150 SET_REGNO (pic_offset_table_rtx, PIC_REG);
5153 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
5156 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
5157 int incoming ATTRIBUTE_UNUSED)
5159 return gen_rtx_REG (Pmode, M68K_STRUCT_VALUE_REGNUM);
5162 /* Return nonzero if register old_reg can be renamed to register new_reg. */
5164 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
5165 unsigned int new_reg)
5168 /* Interrupt functions can only use registers that have already been
5169 saved by the prologue, even if they would normally be
5172 if ((m68k_get_function_kind (current_function_decl)
5173 == m68k_fk_interrupt_handler)
5174 && !df_regs_ever_live_p (new_reg))
5180 /* Value is true if hard register REGNO can hold a value of machine-mode
5181 MODE. On the 68000, we let the cpu registers can hold any mode, but
5182 restrict the 68881 registers to floating-point modes. */
5185 m68k_regno_mode_ok (int regno, enum machine_mode mode)
5187 if (DATA_REGNO_P (regno))
5189 /* Data Registers, can hold aggregate if fits in. */
5190 if (regno + GET_MODE_SIZE (mode) / 4 <= 8)
5193 else if (ADDRESS_REGNO_P (regno))
5195 if (regno + GET_MODE_SIZE (mode) / 4 <= 16)
5198 else if (FP_REGNO_P (regno))
5200 /* FPU registers, hold float or complex float of long double or
5202 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
5203 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5204 && GET_MODE_UNIT_SIZE (mode) <= TARGET_FP_REG_SIZE)
5210 /* Implement SECONDARY_RELOAD_CLASS. */
5213 m68k_secondary_reload_class (enum reg_class rclass,
5214 enum machine_mode mode, rtx x)
5218 regno = true_regnum (x);
5220 /* If one operand of a movqi is an address register, the other
5221 operand must be a general register or constant. Other types
5222 of operand must be reloaded through a data register. */
5223 if (GET_MODE_SIZE (mode) == 1
5224 && reg_classes_intersect_p (rclass, ADDR_REGS)
5225 && !(INT_REGNO_P (regno) || CONSTANT_P (x)))
5228 /* PC-relative addresses must be loaded into an address register first. */
5230 && !reg_class_subset_p (rclass, ADDR_REGS)
5231 && symbolic_operand (x, VOIDmode))
5237 /* Implement PREFERRED_RELOAD_CLASS. */
5240 m68k_preferred_reload_class (rtx x, enum reg_class rclass)
5242 enum reg_class secondary_class;
5244 /* If RCLASS might need a secondary reload, try restricting it to
5245 a class that doesn't. */
5246 secondary_class = m68k_secondary_reload_class (rclass, GET_MODE (x), x);
5247 if (secondary_class != NO_REGS
5248 && reg_class_subset_p (secondary_class, rclass))
5249 return secondary_class;
5251 /* Prefer to use moveq for in-range constants. */
5252 if (GET_CODE (x) == CONST_INT
5253 && reg_class_subset_p (DATA_REGS, rclass)
5254 && IN_RANGE (INTVAL (x), -0x80, 0x7f))
5257 /* ??? Do we really need this now? */
5258 if (GET_CODE (x) == CONST_DOUBLE
5259 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
5261 if (TARGET_HARD_FLOAT && reg_class_subset_p (FP_REGS, rclass))
5270 /* Return floating point values in a 68881 register. This makes 68881 code
5271 a little bit faster. It also makes -msoft-float code incompatible with
5272 hard-float code, so people have to be careful not to mix the two.
5273 For ColdFire it was decided the ABI incompatibility is undesirable.
5274 If there is need for a hard-float ABI it is probably worth doing it
5275 properly and also passing function arguments in FP registers. */
5277 m68k_libcall_value (enum machine_mode mode)
5284 return gen_rtx_REG (mode, FP0_REG);
5290 return gen_rtx_REG (mode, m68k_libcall_value_in_a0_p ? A0_REG : D0_REG);
5293 /* Location in which function value is returned.
5294 NOTE: Due to differences in ABIs, don't call this function directly,
5295 use FUNCTION_VALUE instead. */
5297 m68k_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED)
5299 enum machine_mode mode;
5301 mode = TYPE_MODE (valtype);
5307 return gen_rtx_REG (mode, FP0_REG);
5313 /* If the function returns a pointer, push that into %a0. */
5314 if (func && POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func))))
5315 /* For compatibility with the large body of existing code which
5316 does not always properly declare external functions returning
5317 pointer types, the m68k/SVR4 convention is to copy the value
5318 returned for pointer functions from a0 to d0 in the function
5319 epilogue, so that callers that have neglected to properly
5320 declare the callee can still find the correct return value in
5322 return gen_rtx_PARALLEL
5325 gen_rtx_EXPR_LIST (VOIDmode,
5326 gen_rtx_REG (mode, A0_REG),
5328 gen_rtx_EXPR_LIST (VOIDmode,
5329 gen_rtx_REG (mode, D0_REG),
5331 else if (POINTER_TYPE_P (valtype))
5332 return gen_rtx_REG (mode, A0_REG);
5334 return gen_rtx_REG (mode, D0_REG);
5337 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5338 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
5340 m68k_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
5342 enum machine_mode mode = TYPE_MODE (type);
5344 if (mode == BLKmode)
5347 /* If TYPE's known alignment is less than the alignment of MODE that
5348 would contain the structure, then return in memory. We need to
5349 do so to maintain the compatibility between code compiled with
5350 -mstrict-align and that compiled with -mno-strict-align. */
5351 if (AGGREGATE_TYPE_P (type)
5352 && TYPE_ALIGN (type) < GET_MODE_ALIGNMENT (mode))
5359 /* CPU to schedule the program for. */
5360 enum attr_cpu m68k_sched_cpu;
5362 /* MAC to schedule the program for. */
5363 enum attr_mac m68k_sched_mac;
5371 /* Integer register. */
5377 /* Implicit mem reference (e.g. stack). */
5380 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
5383 /* Memory with offset but without indexing. EA mode 5. */
5386 /* Memory with indexing. EA mode 6. */
5389 /* Memory referenced by absolute address. EA mode 7. */
5392 /* Immediate operand that doesn't require extension word. */
5395 /* Immediate 16 bit operand. */
5398 /* Immediate 32 bit operand. */
5402 /* Return type of memory ADDR_RTX refers to. */
5403 static enum attr_op_type
5404 sched_address_type (enum machine_mode mode, rtx addr_rtx)
5406 struct m68k_address address;
5408 if (symbolic_operand (addr_rtx, VOIDmode))
5409 return OP_TYPE_MEM7;
5411 if (!m68k_decompose_address (mode, addr_rtx,
5412 reload_completed, &address))
5414 gcc_assert (!reload_completed);
5415 /* Reload will likely fix the address to be in the register. */
5416 return OP_TYPE_MEM234;
5419 if (address.scale != 0)
5420 return OP_TYPE_MEM6;
5422 if (address.base != NULL_RTX)
5424 if (address.offset == NULL_RTX)
5425 return OP_TYPE_MEM234;
5427 return OP_TYPE_MEM5;
5430 gcc_assert (address.offset != NULL_RTX);
5432 return OP_TYPE_MEM7;
5435 /* Return X or Y (depending on OPX_P) operand of INSN. */
5437 sched_get_operand (rtx insn, bool opx_p)
5441 if (recog_memoized (insn) < 0)
5444 extract_constrain_insn_cached (insn);
5447 i = get_attr_opx (insn);
5449 i = get_attr_opy (insn);
5451 if (i >= recog_data.n_operands)
5454 return recog_data.operand[i];
5457 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
5458 If ADDRESS_P is true, return type of memory location operand refers to. */
5459 static enum attr_op_type
5460 sched_attr_op_type (rtx insn, bool opx_p, bool address_p)
5464 op = sched_get_operand (insn, opx_p);
5468 gcc_assert (!reload_completed);
5473 return sched_address_type (QImode, op);
5475 if (memory_operand (op, VOIDmode))
5476 return sched_address_type (GET_MODE (op), XEXP (op, 0));
5478 if (register_operand (op, VOIDmode))
5480 if ((!reload_completed && FLOAT_MODE_P (GET_MODE (op)))
5481 || (reload_completed && FP_REG_P (op)))
5487 if (GET_CODE (op) == CONST_INT)
5493 /* Check for quick constants. */
5494 switch (get_attr_type (insn))
5497 if (IN_RANGE (ival, 1, 8) || IN_RANGE (ival, -8, -1))
5498 return OP_TYPE_IMM_Q;
5500 gcc_assert (!reload_completed);
5504 if (USE_MOVQ (ival))
5505 return OP_TYPE_IMM_Q;
5507 gcc_assert (!reload_completed);
5511 if (valid_mov3q_const (ival))
5512 return OP_TYPE_IMM_Q;
5514 gcc_assert (!reload_completed);
5521 if (IN_RANGE (ival, -0x8000, 0x7fff))
5522 return OP_TYPE_IMM_W;
5524 return OP_TYPE_IMM_L;
5527 if (GET_CODE (op) == CONST_DOUBLE)
5529 switch (GET_MODE (op))
5532 return OP_TYPE_IMM_W;
5536 return OP_TYPE_IMM_L;
5543 if (GET_CODE (op) == CONST
5544 || symbolic_operand (op, VOIDmode)
5547 switch (GET_MODE (op))
5550 return OP_TYPE_IMM_Q;
5553 return OP_TYPE_IMM_W;
5556 return OP_TYPE_IMM_L;
5559 if (symbolic_operand (m68k_unwrap_symbol (op, false), VOIDmode))
5561 return OP_TYPE_IMM_W;
5563 return OP_TYPE_IMM_L;
5567 gcc_assert (!reload_completed);
5569 if (FLOAT_MODE_P (GET_MODE (op)))
5575 /* Implement opx_type attribute.
5576 Return type of INSN's operand X.
5577 If ADDRESS_P is true, return type of memory location operand refers to. */
5579 m68k_sched_attr_opx_type (rtx insn, int address_p)
5581 switch (sched_attr_op_type (insn, true, address_p != 0))
5587 return OPX_TYPE_FPN;
5590 return OPX_TYPE_MEM1;
5592 case OP_TYPE_MEM234:
5593 return OPX_TYPE_MEM234;
5596 return OPX_TYPE_MEM5;
5599 return OPX_TYPE_MEM6;
5602 return OPX_TYPE_MEM7;
5605 return OPX_TYPE_IMM_Q;
5608 return OPX_TYPE_IMM_W;
5611 return OPX_TYPE_IMM_L;
5618 /* Implement opy_type attribute.
5619 Return type of INSN's operand Y.
5620 If ADDRESS_P is true, return type of memory location operand refers to. */
5622 m68k_sched_attr_opy_type (rtx insn, int address_p)
5624 switch (sched_attr_op_type (insn, false, address_p != 0))
5630 return OPY_TYPE_FPN;
5633 return OPY_TYPE_MEM1;
5635 case OP_TYPE_MEM234:
5636 return OPY_TYPE_MEM234;
5639 return OPY_TYPE_MEM5;
5642 return OPY_TYPE_MEM6;
5645 return OPY_TYPE_MEM7;
5648 return OPY_TYPE_IMM_Q;
5651 return OPY_TYPE_IMM_W;
5654 return OPY_TYPE_IMM_L;
5661 /* Return size of INSN as int. */
5663 sched_get_attr_size_int (rtx insn)
5667 switch (get_attr_type (insn))
5670 /* There should be no references to m68k_sched_attr_size for 'ignore'
5684 switch (get_attr_opx_type (insn))
5690 case OPX_TYPE_MEM234:
5691 case OPY_TYPE_IMM_Q:
5696 /* Here we assume that most absolute references are short. */
5698 case OPY_TYPE_IMM_W:
5702 case OPY_TYPE_IMM_L:
5710 switch (get_attr_opy_type (insn))
5716 case OPY_TYPE_MEM234:
5717 case OPY_TYPE_IMM_Q:
5722 /* Here we assume that most absolute references are short. */
5724 case OPY_TYPE_IMM_W:
5728 case OPY_TYPE_IMM_L:
5738 gcc_assert (!reload_completed);
5746 /* Return size of INSN as attribute enum value. */
5748 m68k_sched_attr_size (rtx insn)
5750 switch (sched_get_attr_size_int (insn))
5766 /* Return operand X or Y (depending on OPX_P) of INSN,
5767 if it is a MEM, or NULL overwise. */
5768 static enum attr_op_type
5769 sched_get_opxy_mem_type (rtx insn, bool opx_p)
5773 switch (get_attr_opx_type (insn))
5778 case OPX_TYPE_IMM_Q:
5779 case OPX_TYPE_IMM_W:
5780 case OPX_TYPE_IMM_L:
5784 case OPX_TYPE_MEM234:
5787 return OP_TYPE_MEM1;
5790 return OP_TYPE_MEM6;
5798 switch (get_attr_opy_type (insn))
5803 case OPY_TYPE_IMM_Q:
5804 case OPY_TYPE_IMM_W:
5805 case OPY_TYPE_IMM_L:
5809 case OPY_TYPE_MEM234:
5812 return OP_TYPE_MEM1;
5815 return OP_TYPE_MEM6;
5823 /* Implement op_mem attribute. */
5825 m68k_sched_attr_op_mem (rtx insn)
5827 enum attr_op_type opx;
5828 enum attr_op_type opy;
5830 opx = sched_get_opxy_mem_type (insn, true);
5831 opy = sched_get_opxy_mem_type (insn, false);
5833 if (opy == OP_TYPE_RN && opx == OP_TYPE_RN)
5836 if (opy == OP_TYPE_RN && opx == OP_TYPE_MEM1)
5838 switch (get_attr_opx_access (insn))
5854 if (opy == OP_TYPE_RN && opx == OP_TYPE_MEM6)
5856 switch (get_attr_opx_access (insn))
5872 if (opy == OP_TYPE_MEM1 && opx == OP_TYPE_RN)
5875 if (opy == OP_TYPE_MEM1 && opx == OP_TYPE_MEM1)
5877 switch (get_attr_opx_access (insn))
5883 gcc_assert (!reload_completed);
5888 if (opy == OP_TYPE_MEM1 && opx == OP_TYPE_MEM6)
5890 switch (get_attr_opx_access (insn))
5896 gcc_assert (!reload_completed);
5901 if (opy == OP_TYPE_MEM6 && opx == OP_TYPE_RN)
5904 if (opy == OP_TYPE_MEM6 && opx == OP_TYPE_MEM1)
5906 switch (get_attr_opx_access (insn))
5912 gcc_assert (!reload_completed);
5917 gcc_assert (opy == OP_TYPE_MEM6 && opx == OP_TYPE_MEM6);
5918 gcc_assert (!reload_completed);
5922 /* Jump instructions types. Indexed by INSN_UID.
5923 The same rtl insn can be expanded into different asm instructions
5924 depending on the cc0_status. To properly determine type of jump
5925 instructions we scan instruction stream and map jumps types to this
5927 static enum attr_type *sched_branch_type;
5929 /* Return the type of the jump insn. */
5931 m68k_sched_branch_type (rtx insn)
5933 enum attr_type type;
5935 type = sched_branch_type[INSN_UID (insn)];
5937 gcc_assert (type != 0);
5942 /* Data for ColdFire V4 index bypass.
5943 Producer modifies register that is used as index in consumer with
5947 /* Producer instruction. */
5950 /* Consumer instruction. */
5953 /* Scale of indexed memory access within consumer.
5954 Or zero if bypass should not be effective at the moment. */
5956 } sched_cfv4_bypass_data;
5958 /* An empty state that is used in m68k_sched_adjust_cost. */
5959 static state_t sched_adjust_cost_state;
5961 /* Implement adjust_cost scheduler hook.
5962 Return adjusted COST of dependency LINK between DEF_INSN and INSN. */
5964 m68k_sched_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx def_insn,
5969 if (recog_memoized (def_insn) < 0
5970 || recog_memoized (insn) < 0)
5973 if (sched_cfv4_bypass_data.scale == 1)
5974 /* Handle ColdFire V4 bypass for indexed address with 1x scale. */
5976 /* haifa-sched.c: insn_cost () calls bypass_p () just before
5977 targetm.sched.adjust_cost (). Hence, we can be relatively sure
5978 that the data in sched_cfv4_bypass_data is up to date. */
5979 gcc_assert (sched_cfv4_bypass_data.pro == def_insn
5980 && sched_cfv4_bypass_data.con == insn);
5985 sched_cfv4_bypass_data.pro = NULL;
5986 sched_cfv4_bypass_data.con = NULL;
5987 sched_cfv4_bypass_data.scale = 0;
5990 gcc_assert (sched_cfv4_bypass_data.pro == NULL
5991 && sched_cfv4_bypass_data.con == NULL
5992 && sched_cfv4_bypass_data.scale == 0);
5994 /* Don't try to issue INSN earlier than DFA permits.
5995 This is especially useful for instructions that write to memory,
5996 as their true dependence (default) latency is better to be set to 0
5997 to workaround alias analysis limitations.
5998 This is, in fact, a machine independent tweak, so, probably,
5999 it should be moved to haifa-sched.c: insn_cost (). */
6000 delay = min_insn_conflict_delay (sched_adjust_cost_state, def_insn, insn);
6007 /* Return maximal number of insns that can be scheduled on a single cycle. */
6009 m68k_sched_issue_rate (void)
6011 switch (m68k_sched_cpu)
6027 /* Maximal length of instruction for current CPU.
6028 E.g. it is 3 for any ColdFire core. */
6029 static int max_insn_size;
6031 /* Data to model instruction buffer of CPU. */
6034 /* True if instruction buffer model is modeled for current CPU. */
6037 /* Size of the instruction buffer in words. */
6040 /* Number of filled words in the instruction buffer. */
6043 /* Additional information about instruction buffer for CPUs that have
6044 a buffer of instruction records, rather then a plain buffer
6045 of instruction words. */
6046 struct _sched_ib_records
6048 /* Size of buffer in records. */
6051 /* Array to hold data on adjustements made to the size of the buffer. */
6054 /* Index of the above array. */
6058 /* An insn that reserves (marks empty) one word in the instruction buffer. */
6062 static struct _sched_ib sched_ib;
6064 /* ID of memory unit. */
6065 static int sched_mem_unit_code;
6067 /* Implementation of the targetm.sched.variable_issue () hook.
6068 It is called after INSN was issued. It returns the number of insns
6069 that can possibly get scheduled on the current cycle.
6070 It is used here to determine the effect of INSN on the instruction
6073 m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED,
6074 int sched_verbose ATTRIBUTE_UNUSED,
6075 rtx insn, int can_issue_more)
6079 if (recog_memoized (insn) >= 0 && get_attr_type (insn) != TYPE_IGNORE)
6081 switch (m68k_sched_cpu)
6085 insn_size = sched_get_attr_size_int (insn);
6089 insn_size = sched_get_attr_size_int (insn);
6091 /* ColdFire V3 and V4 cores have instruction buffers that can
6092 accumulate up to 8 instructions regardless of instructions'
6093 sizes. So we should take care not to "prefetch" 24 one-word
6094 or 12 two-words instructions.
6095 To model this behavior we temporarily decrease size of the
6096 buffer by (max_insn_size - insn_size) for next 7 instructions. */
6100 adjust = max_insn_size - insn_size;
6101 sched_ib.size -= adjust;
6103 if (sched_ib.filled > sched_ib.size)
6104 sched_ib.filled = sched_ib.size;
6106 sched_ib.records.adjust[sched_ib.records.adjust_index] = adjust;
6109 ++sched_ib.records.adjust_index;
6110 if (sched_ib.records.adjust_index == sched_ib.records.n_insns)
6111 sched_ib.records.adjust_index = 0;
6113 /* Undo adjustement we did 7 instructions ago. */
6115 += sched_ib.records.adjust[sched_ib.records.adjust_index];
6120 gcc_assert (!sched_ib.enabled_p);
6128 gcc_assert (insn_size <= sched_ib.filled);
6131 else if (GET_CODE (PATTERN (insn)) == ASM_INPUT
6132 || asm_noperands (PATTERN (insn)) >= 0)
6133 insn_size = sched_ib.filled;
6137 sched_ib.filled -= insn_size;
6139 return can_issue_more;
6142 /* Return how many instructions should scheduler lookahead to choose the
6145 m68k_sched_first_cycle_multipass_dfa_lookahead (void)
6147 return m68k_sched_issue_rate () - 1;
6150 /* Implementation of targetm.sched.init_global () hook.
6151 It is invoked once per scheduling pass and is used here
6152 to initialize scheduler constants. */
6154 m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED,
6155 int sched_verbose ATTRIBUTE_UNUSED,
6156 int n_insns ATTRIBUTE_UNUSED)
6158 /* Init branch types. */
6162 sched_branch_type = XCNEWVEC (enum attr_type, get_max_uid () + 1);
6164 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
6167 /* !!! FIXME: Implement real scan here. */
6168 sched_branch_type[INSN_UID (insn)] = TYPE_BCC;
6172 #ifdef ENABLE_CHECKING
6173 /* Check that all instructions have DFA reservations and
6174 that all instructions can be issued from a clean state. */
6179 state = alloca (state_size ());
6181 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
6183 if (INSN_P (insn) && recog_memoized (insn) >= 0)
6185 gcc_assert (insn_has_dfa_reservation_p (insn));
6187 state_reset (state);
6188 if (state_transition (state, insn) >= 0)
6195 /* Setup target cpu. */
6197 /* ColdFire V4 has a set of features to keep its instruction buffer full
6198 (e.g., a separate memory bus for instructions) and, hence, we do not model
6199 buffer for this CPU. */
6200 sched_ib.enabled_p = (m68k_sched_cpu != CPU_CFV4);
6202 switch (m68k_sched_cpu)
6205 sched_ib.filled = 0;
6212 sched_ib.records.n_insns = 0;
6213 sched_ib.records.adjust = NULL;
6218 sched_ib.records.n_insns = 8;
6219 sched_ib.records.adjust = XNEWVEC (int, sched_ib.records.n_insns);
6226 sched_mem_unit_code = get_cpu_unit_code ("cf_mem1");
6228 sched_adjust_cost_state = xmalloc (state_size ());
6229 state_reset (sched_adjust_cost_state);
6232 emit_insn (gen_ib ());
6233 sched_ib.insn = get_insns ();
6237 /* Scheduling pass is now finished. Free/reset static variables. */
6239 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
6240 int verbose ATTRIBUTE_UNUSED)
6242 sched_ib.insn = NULL;
6244 free (sched_adjust_cost_state);
6245 sched_adjust_cost_state = NULL;
6247 sched_mem_unit_code = 0;
6249 free (sched_ib.records.adjust);
6250 sched_ib.records.adjust = NULL;
6251 sched_ib.records.n_insns = 0;
6254 free (sched_branch_type);
6255 sched_branch_type = NULL;
6258 /* Implementation of targetm.sched.init () hook.
6259 It is invoked each time scheduler starts on the new block (basic block or
6260 extended basic block). */
6262 m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED,
6263 int sched_verbose ATTRIBUTE_UNUSED,
6264 int n_insns ATTRIBUTE_UNUSED)
6266 switch (m68k_sched_cpu)
6274 sched_ib.size = sched_ib.records.n_insns * max_insn_size;
6276 memset (sched_ib.records.adjust, 0,
6277 sched_ib.records.n_insns * sizeof (*sched_ib.records.adjust));
6278 sched_ib.records.adjust_index = 0;
6282 gcc_assert (!sched_ib.enabled_p);
6290 if (sched_ib.enabled_p)
6291 /* haifa-sched.c: schedule_block () calls advance_cycle () just before
6292 the first cycle. Workaround that. */
6293 sched_ib.filled = -2;
6296 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
6297 It is invoked just before current cycle finishes and is used here
6298 to track if instruction buffer got its two words this cycle. */
6300 m68k_sched_dfa_pre_advance_cycle (void)
6302 if (!sched_ib.enabled_p)
6305 if (!cpu_unit_reservation_p (curr_state, sched_mem_unit_code))
6307 sched_ib.filled += 2;
6309 if (sched_ib.filled > sched_ib.size)
6310 sched_ib.filled = sched_ib.size;
6314 /* Implementation of targetm.sched.dfa_post_advance_cycle () hook.
6315 It is invoked just after new cycle begins and is used here
6316 to setup number of filled words in the instruction buffer so that
6317 instructions which won't have all their words prefetched would be
6318 stalled for a cycle. */
6320 m68k_sched_dfa_post_advance_cycle (void)
6324 if (!sched_ib.enabled_p)
6327 /* Setup number of prefetched instruction words in the instruction
6329 i = max_insn_size - sched_ib.filled;
6333 if (state_transition (curr_state, sched_ib.insn) >= 0)
6338 /* Return X or Y (depending on OPX_P) operand of INSN,
6339 if it is an integer register, or NULL overwise. */
6341 sched_get_reg_operand (rtx insn, bool opx_p)
6347 if (get_attr_opx_type (insn) == OPX_TYPE_RN)
6349 op = sched_get_operand (insn, true);
6350 gcc_assert (op != NULL);
6352 if (!reload_completed && !REG_P (op))
6358 if (get_attr_opy_type (insn) == OPY_TYPE_RN)
6360 op = sched_get_operand (insn, false);
6361 gcc_assert (op != NULL);
6363 if (!reload_completed && !REG_P (op))
6371 /* Return true, if X or Y (depending on OPX_P) operand of INSN
6374 sched_mem_operand_p (rtx insn, bool opx_p)
6376 switch (sched_get_opxy_mem_type (insn, opx_p))
6387 /* Return X or Y (depending on OPX_P) operand of INSN,
6388 if it is a MEM, or NULL overwise. */
6390 sched_get_mem_operand (rtx insn, bool must_read_p, bool must_write_p)
6410 if (opy_p && sched_mem_operand_p (insn, false))
6411 return sched_get_operand (insn, false);
6413 if (opx_p && sched_mem_operand_p (insn, true))
6414 return sched_get_operand (insn, true);
6420 /* Return non-zero if PRO modifies register used as part of
6423 m68k_sched_address_bypass_p (rtx pro, rtx con)
6428 pro_x = sched_get_reg_operand (pro, true);
6432 con_mem_read = sched_get_mem_operand (con, true, false);
6433 gcc_assert (con_mem_read != NULL);
6435 if (reg_mentioned_p (pro_x, con_mem_read))
6441 /* Helper function for m68k_sched_indexed_address_bypass_p.
6442 if PRO modifies register used as index in CON,
6443 return scale of indexed memory access in CON. Return zero overwise. */
6445 sched_get_indexed_address_scale (rtx pro, rtx con)
6449 struct m68k_address address;
6451 reg = sched_get_reg_operand (pro, true);
6455 mem = sched_get_mem_operand (con, true, false);
6456 gcc_assert (mem != NULL && MEM_P (mem));
6458 if (!m68k_decompose_address (GET_MODE (mem), XEXP (mem, 0), reload_completed,
6462 if (REGNO (reg) == REGNO (address.index))
6464 gcc_assert (address.scale != 0);
6465 return address.scale;
6471 /* Return non-zero if PRO modifies register used
6472 as index with scale 2 or 4 in CON. */
6474 m68k_sched_indexed_address_bypass_p (rtx pro, rtx con)
6476 gcc_assert (sched_cfv4_bypass_data.pro == NULL
6477 && sched_cfv4_bypass_data.con == NULL
6478 && sched_cfv4_bypass_data.scale == 0);
6480 switch (sched_get_indexed_address_scale (pro, con))
6483 /* We can't have a variable latency bypass, so
6484 remember to adjust the insn cost in adjust_cost hook. */
6485 sched_cfv4_bypass_data.pro = pro;
6486 sched_cfv4_bypass_data.con = con;
6487 sched_cfv4_bypass_data.scale = 1;
6499 /* We generate a two-instructions program at M_TRAMP :
6500 movea.l &CHAIN_VALUE,%a0
6502 where %a0 can be modified by changing STATIC_CHAIN_REGNUM. */
6505 m68k_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
6507 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
6510 gcc_assert (ADDRESS_REGNO_P (STATIC_CHAIN_REGNUM));
6512 mem = adjust_address (m_tramp, HImode, 0);
6513 emit_move_insn (mem, GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM-8) << 9)));
6514 mem = adjust_address (m_tramp, SImode, 2);
6515 emit_move_insn (mem, chain_value);
6517 mem = adjust_address (m_tramp, HImode, 6);
6518 emit_move_insn (mem, GEN_INT(0x4EF9));
6519 mem = adjust_address (m_tramp, SImode, 8);
6520 emit_move_insn (mem, fnaddr);
6522 FINALIZE_TRAMPOLINE (XEXP (m_tramp, 0));
6525 /* On the 68000, the RTS insn cannot pop anything.
6526 On the 68010, the RTD insn may be used to pop them if the number
6527 of args is fixed, but if the number is variable then the caller
6528 must pop them all. RTD can't be used for library calls now
6529 because the library is compiled with the Unix compiler.
6530 Use of RTD is a selectable option, since it is incompatible with
6531 standard Unix calling sequences. If the option is not selected,
6532 the caller must always pop the args. */
6535 m68k_return_pops_args (tree fundecl, tree funtype, int size)
6539 || TREE_CODE (fundecl) != IDENTIFIER_NODE)
6540 && (!stdarg_p (funtype)))
6544 #include "gt-m68k.h"