1 /* Definitions of target machine for GNU compiler.
2 Motorola 68HC11 and 68HC12.
3 Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Stephane Carrez (stcarrez@nerim.fr)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA.
24 A first 68HC11 port was made by Otto Lind (otto@coactive.com)
25 on gcc 2.6.3. I have used it as a starting point for this port.
26 However, this new port is a complete re-write. Its internal
27 design is completely different. The generated code is not
28 compatible with the gcc 2.6.3 port.
30 The gcc 2.6.3 port is available at:
32 ftp.unina.it/pub/electronics/motorola/68hc11/gcc/gcc-6811-fsf.tar.gz
36 /*****************************************************************************
38 ** Controlling the Compilation Driver, `gcc'
40 *****************************************************************************/
44 /* Compile and assemble for a 68hc11 unless there is a -m68hc12 option. */
47 "%{m68hc12:-m68hc12}" \
48 "%{m68hcs12:-m68hcs12}" \
49 "%{!m68hc12:%{!m68hcs12:-m68hc11}} " \
50 "%{mshort:-mshort}%{!mshort:-mlong} " \
51 "%{fshort-double:-mshort-double}%{!fshort-double:-mlong-double}"
54 /* We need to tell the linker the target elf format. Just pass an
55 emulation option. This can be overridden by -Wl option of gcc. */
58 "%{m68hc12:-m m68hc12elf}" \
59 "%{m68hcs12:-m m68hc12elf}" \
60 "%{!m68hc12:%{!m68hcs12:-m m68hc11elf}} " \
61 "%{!mnorelax:%{!m68hc12:%{!m68hcs12:-relax}}}"
74 "%{mshort:-D__HAVE_SHORT_INT__ -D__INT__=16}\
75 %{!mshort:-D__INT__=32}\
76 %{m68hc12:-Dmc6812 -DMC6812 -Dmc68hc12}\
77 %{m68hcs12:-Dmc6812 -DMC6812 -Dmc68hcs12}\
78 %{!m68hc12:%{!m68hcs12:-Dmc6811 -DMC6811 -Dmc68hc11}}\
79 %{fshort-double:-D__HAVE_SHORT_DOUBLE__}\
80 %{mlong-calls:-D__USE_RTC__}"
84 #define STARTFILE_SPEC "crt1%O%s"
86 /* Names to predefine in the preprocessor for this target machine. */
87 #define CPP_PREDEFINES "-Dmc68hc1x"
89 /* As an embedded target, we have no libc. */
92 /* Forward type declaration for prototypes definitions.
93 rtx_ptr is equivalent to rtx. Can't use the same name. */
95 typedef struct rtx_def *rtx_ptr;
98 typedef union tree_node *tree_ptr;
100 /* We can't declare enum machine_mode forward nor include 'machmode.h' here.
101 Prototypes defined here will use an int instead. It's better than no
103 typedef int enum_machine_mode;
105 /*****************************************************************************
107 ** Run-time Target Specification
109 *****************************************************************************/
111 /* Run-time compilation parameters selecting different hardware subsets. */
113 extern int target_flags;
115 extern short *reg_renumber; /* def in local_alloc.c */
117 /* Macros used in the machine description to test the flags. */
119 /* 6811 specific options
121 * For 68HC12, the auto inc/dec mode is disabled by default. The reason
122 * is that for most programs, the reload pass will fail because it needs
123 * more registers to save the value of the indexed register after the
124 * memory access. For simple programs, you can enable this
125 * with -mauto-incdec.
128 #define MASK_SHORT 0002 /* Compile with 16-bit `int' */
129 #define MASK_AUTO_INC_DEC 0004
130 #define MASK_M6811 0010
131 #define MASK_M68S12 0040
132 #define MASK_NO_DIRECT_MODE 0100
133 #define MASK_MIN_MAX 0200
134 #define MASK_LONG_CALLS 0400
136 #define TARGET_OP_TIME (optimize && optimize_size == 0)
137 #define TARGET_SHORT (target_flags & MASK_SHORT)
138 #define TARGET_M6811 (target_flags & MASK_M6811)
139 #define TARGET_M6812 (target_flags & MASK_M6812)
140 #define TARGET_M68S12 (target_flags & MASK_M68S12)
141 #define TARGET_AUTO_INC_DEC (target_flags & MASK_AUTO_INC_DEC)
142 #define TARGET_MIN_MAX (target_flags & MASK_MIN_MAX)
143 #define TARGET_NO_DIRECT_MODE (target_flags & MASK_NO_DIRECT_MODE)
144 #define TARGET_RELAX (TARGET_NO_DIRECT_MODE)
145 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
147 /* Default target_flags if no switches specified. */
148 #ifndef TARGET_DEFAULT
149 # define TARGET_DEFAULT (MASK_M6811)
152 /* Define this macro as a C expression for the initializer of an
153 array of string to tell the driver program which options are
154 defaults for this target and thus do not need to be handled
155 specially when using `MULTILIB_OPTIONS'. */
156 #ifndef MULTILIB_DEFAULTS
157 # if TARGET_DEFAULT & MASK_M6811
158 # define MULTILIB_DEFAULTS { "m68hc11" }
160 # define MULTILIB_DEFAULTS { "m68hc12" }
164 /* Macro to define tables used to set the flags. This is a list in braces of
165 pairs in braces, each pair being { "NAME", VALUE } where VALUE is the bits
166 to set or minus the bits to clear. An empty string NAME is used to
167 identify the default VALUE. */
169 #define TARGET_SWITCHES \
170 { { "short", MASK_SHORT, \
171 N_("Compile with 16-bit integer mode")}, \
172 { "noshort", - MASK_SHORT, \
173 N_("Compile with 32-bit integer mode")}, \
174 { "auto-incdec", MASK_AUTO_INC_DEC, \
175 N_("Auto pre/post decrement increment allowed")}, \
176 { "noauto-incdec", - MASK_AUTO_INC_DEC, \
177 N_("Auto pre/post decrement increment not allowed")}, \
178 { "inmax", MASK_MIN_MAX, \
179 N_("Min/max instructions allowed")}, \
180 { "nominmax", MASK_MIN_MAX, \
181 N_("Min/max instructions not allowed")}, \
182 { "long-calls", MASK_LONG_CALLS, \
183 N_("Use call and rtc for function calls and returns")}, \
184 { "nolong-calls", - MASK_LONG_CALLS, \
185 N_("Use jsr and rts for function calls and returns")}, \
186 { "relax", MASK_NO_DIRECT_MODE, \
187 N_("Do not use direct addressing mode for soft registers")},\
188 { "68hc11", MASK_M6811, \
189 N_("Compile for a 68HC11")}, \
190 { "68hc12", MASK_M6812, \
191 N_("Compile for a 68HC12")}, \
192 { "68hcs12", MASK_M6812 | MASK_M68S12, \
193 N_("Compile for a 68HCS12")}, \
194 { "6811", MASK_M6811, \
195 N_("Compile for a 68HC11")}, \
196 { "6812", MASK_M6812, \
197 N_("Compile for a 68HC12")}, \
198 { "68S12", MASK_M6812 | MASK_M68S12, \
199 N_("Compile for a 68HCS12")}, \
200 { "", TARGET_DEFAULT, 0 }}
202 /* This macro is similar to `TARGET_SWITCHES' but defines names of
203 command options that have values. Its definition is an
204 initializer with a subgrouping for each command option.
206 Each subgrouping contains a string constant, that defines the
207 fixed part of the option name, and the address of a variable. The
208 variable, type `char *', is set to the variable part of the given
209 option if the fixed part matches. The actual option name is made
210 by appending `-m' to the specified name. */
211 #define TARGET_OPTIONS \
212 { { "reg-alloc=", &m68hc11_reg_alloc_order, \
213 N_("Specify the register allocation order")}, \
214 { "soft-reg-count=", &m68hc11_soft_reg_count, \
215 N_("Indicate the number of soft registers available") }, \
219 /* These are meant to be redefined in the host dependent files */
220 #define SUBTARGET_SWITCHES
221 #define SUBTARGET_OPTIONS
223 extern const char *m68hc11_regparm_string;
224 extern const char *m68hc11_reg_alloc_order;
225 extern const char *m68hc11_soft_reg_count;
227 #ifndef TARGET_M68HC12
228 # define TARGET_M68HC11 1
231 /* Print subsidiary information on the compiler version in use. */
232 #define TARGET_VERSION fprintf (stderr, " (MC68HC11/MC68HC12/MC68HCS12)")
234 /* Sometimes certain combinations of command options do not make
235 sense on a particular target machine. You can define a macro
236 `OVERRIDE_OPTIONS' to take account of this. This macro, if
237 defined, is executed once just after all the command options have
240 Don't use this macro to turn on various extra optimizations for
241 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
243 #define OVERRIDE_OPTIONS m68hc11_override_options ();
246 /* Define cost parameters for a given processor variant. */
247 struct processor_costs {
248 const int add; /* cost of an add instruction */
249 const int logical; /* cost of a logical instruction */
251 const int shiftQI_const[8];
252 const int shiftHI_const[16];
261 /* Costs for the current processor. */
262 extern const struct processor_costs *m68hc11_cost;
265 /* target machine storage layout */
267 /* Define this if most significant byte of a word is the lowest numbered. */
268 #define BYTES_BIG_ENDIAN 1
270 /* Define this if most significant bit is lowest numbered
271 in instructions that operate on numbered bit-fields. */
272 #define BITS_BIG_ENDIAN 0
274 /* Define this if most significant word of a multiword number is numbered. */
275 #define WORDS_BIG_ENDIAN 1
277 /* Width of a word, in units (bytes). */
278 #define UNITS_PER_WORD 2
280 /* Definition of size_t. This is really an unsigned short as the
281 68hc11 only handles a 64K address space. */
282 #define SIZE_TYPE "short unsigned int"
284 /* A C expression for a string describing the name of the data type
285 to use for the result of subtracting two pointers. The typedef
286 name `ptrdiff_t' is defined using the contents of the string.
287 The 68hc11 only has a 64K address space. */
288 #define PTRDIFF_TYPE "short int"
290 /* Allocation boundary (bits) for storing pointers in memory. */
291 #define POINTER_BOUNDARY 8
293 /* Normal alignment required for function parameters on the stack, in bits.
294 This can't be less than BITS_PER_WORD */
295 #define PARM_BOUNDARY (BITS_PER_WORD)
297 /* Boundary (bits) on which stack pointer should be aligned. */
298 #define STACK_BOUNDARY 8
300 /* Allocation boundary (bits) for the code of a function. */
301 #define FUNCTION_BOUNDARY 8
303 #define BIGGEST_ALIGNMENT 8
305 /* Alignment of field after `int : 0' in a structure. */
306 #define EMPTY_FIELD_BOUNDARY 8
308 /* Every structure's size must be a multiple of this. */
309 #define STRUCTURE_SIZE_BOUNDARY 8
311 /* Define this if instructions will fail to work if given data not
312 on the nominal alignment. If instructions will merely go slower
313 in that case, do not define this macro. */
314 #define STRICT_ALIGNMENT 0
316 /* An integer expression for the size in bits of the largest integer
317 machine mode that should actually be used. All integer machine modes of
318 this size or smaller can be used for structures and unions with the
319 appropriate sizes. */
320 #define MAX_FIXED_MODE_SIZE 64
322 /* target machine storage layout */
324 /* Size (bits) of the type "int" on target machine
325 (If undefined, default is BITS_PER_WORD). */
326 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
328 /* Size (bits) of the type "short" on target machine */
329 #define SHORT_TYPE_SIZE 16
331 /* Size (bits) of the type "long" on target machine */
332 #define LONG_TYPE_SIZE 32
334 /* Size (bits) of the type "long long" on target machine */
335 #define LONG_LONG_TYPE_SIZE 64
337 /* A C expression for the size in bits of the type `float' on the
338 target machine. If you don't define this, the default is one word.
339 Don't use default: a word is only 16. */
340 #define FLOAT_TYPE_SIZE 32
342 /* A C expression for the size in bits of the type double on the target
343 machine. If you don't define this, the default is two words.
344 Be IEEE compliant. */
345 #define DOUBLE_TYPE_SIZE 64
347 #define LONG_DOUBLE_TYPE_SIZE 64
349 /* Define this as 1 if `char' should by default be signed; else as 0. */
350 #define DEFAULT_SIGNED_CHAR 0
352 /* Define these to avoid dependence on meaning of `int'.
353 Note that WCHAR_TYPE_SIZE is used in cexp.y,
354 where TARGET_SHORT is not available. */
355 #define WCHAR_TYPE "short int"
356 #define WCHAR_TYPE_SIZE 16
359 /* Standard register usage. */
361 #define HARD_REG_SIZE (UNITS_PER_WORD)
363 /* Assign names to real MC68HC11 registers.
364 A and B registers are not really used (A+B = D)
365 X register is first so that GCC allocates X+D for 32-bit integers and
366 the lowpart of that integer will be D. Having the lower part in D is
367 better for 32<->16bit conversions and for many arithmetic operations. */
368 #define HARD_X_REGNUM 0
369 #define HARD_D_REGNUM 1
370 #define HARD_Y_REGNUM 2
371 #define HARD_SP_REGNUM 3
372 #define HARD_PC_REGNUM 4
373 #define HARD_A_REGNUM 5
374 #define HARD_B_REGNUM 6
375 #define HARD_CCR_REGNUM 7
377 /* The Z register does not really exist in the 68HC11. This a fake register
378 for GCC. It is treated exactly as an index register (X or Y). It is only
379 in the A_REGS class, which is the BASE_REG_CLASS for GCC. Defining this
380 register helps the reload pass of GCC. Otherwise, the reload often aborts
381 with register spill failures.
383 The Z register is replaced by either X or Y during the machine specific
384 reorg (m68hc11_reorg). It is saved in the SOFT_Z_REGNUM soft-register
385 when this is necessary.
387 It's possible to tell GCC not to use this register with -ffixed-z. */
388 #define HARD_Z_REGNUM 8
390 /* The frame pointer is a soft-register. It's treated as such by GCC:
391 it is not and must not be part of the BASE_REG_CLASS. */
392 #define DEFAULT_HARD_FP_REGNUM (9)
393 #define HARD_FP_REGNUM (9)
394 #define HARD_AP_REGNUM (HARD_FP_REGNUM)
396 /* Temporary soft-register used in some cases when an operand came
397 up into a bad register class (D, X, Y, SP) and gcc failed to
398 recognize this. This register is never allocated by GCC. */
399 #define SOFT_TMP_REGNUM 10
401 /* The soft-register which is used to save the Z register
402 (see Z register replacement notes in m68hc11.c). */
403 #define SOFT_Z_REGNUM 11
405 /* The soft-register which is used to save either X or Y. */
406 #define SOFT_SAVED_XY_REGNUM 12
408 /* A fake clobber register for 68HC12 patterns. */
409 #define FAKE_CLOBBER_REGNUM (13)
411 /* Define 32 soft-registers of 16-bit each. By default,
412 only 12 of them are enabled and can be used by GCC. The
413 -msoft-reg-count=<n> option allows to control the number of valid
414 soft-registers. GCC can put 32-bit values in them
415 by allocating consecutive registers. The first 3 soft-registers
416 are never allocated by GCC. They are used in case the insn template needs
417 a temporary register, or for the Z register replacement. */
419 #define MAX_SOFT_REG_COUNT (32)
420 #define SOFT_REG_FIXED 0, 0, 0, 0, 0, 0, 0, 0, \
421 0, 0, 0, 0, 1, 1, 1, 1, \
422 1, 1, 1, 1, 1, 1, 1, 1, \
423 1, 1, 1, 1, 1, 1, 1, 1
424 #define SOFT_REG_USED 0, 0, 0, 0, 0, 0, 0, 0, \
425 0, 0, 0, 0, 1, 1, 1, 1, \
426 1, 1, 1, 1, 1, 1, 1, 1, \
427 1, 1, 1, 1, 1, 1, 1, 1
428 #define SOFT_REG_ORDER \
429 SOFT_REG_FIRST, SOFT_REG_FIRST+1,SOFT_REG_FIRST+2,SOFT_REG_FIRST+3,\
430 SOFT_REG_FIRST+4, SOFT_REG_FIRST+5,SOFT_REG_FIRST+6,SOFT_REG_FIRST+7,\
431 SOFT_REG_FIRST+8, SOFT_REG_FIRST+9,SOFT_REG_FIRST+10,SOFT_REG_FIRST+11,\
432 SOFT_REG_FIRST+12, SOFT_REG_FIRST+13,SOFT_REG_FIRST+14,SOFT_REG_FIRST+15,\
433 SOFT_REG_FIRST+16, SOFT_REG_FIRST+17,SOFT_REG_FIRST+18,SOFT_REG_FIRST+19,\
434 SOFT_REG_FIRST+20, SOFT_REG_FIRST+21,SOFT_REG_FIRST+22,SOFT_REG_FIRST+23,\
435 SOFT_REG_FIRST+24, SOFT_REG_FIRST+25,SOFT_REG_FIRST+26,SOFT_REG_FIRST+27,\
436 SOFT_REG_FIRST+28, SOFT_REG_FIRST+29,SOFT_REG_FIRST+30,SOFT_REG_FIRST+31
438 #define SOFT_REG_NAMES \
439 "*_.d1", "*_.d2", "*_.d3", "*_.d4", \
440 "*_.d5", "*_.d6", "*_.d7", "*_.d8", \
441 "*_.d9", "*_.d10", "*_.d11", "*_.d12", \
442 "*_.d13", "*_.d14", "*_.d15", "*_.d16", \
443 "*_.d17", "*_.d18", "*_.d19", "*_.d20", \
444 "*_.d21", "*_.d22", "*_.d23", "*_.d24", \
445 "*_.d25", "*_.d26", "*_.d27", "*_.d28", \
446 "*_.d29", "*_.d30", "*_.d31", "*_.d32"
448 /* First available soft-register for GCC. */
449 #define SOFT_REG_FIRST (SOFT_SAVED_XY_REGNUM+2)
451 /* Last available soft-register for GCC. */
452 #define SOFT_REG_LAST (SOFT_REG_FIRST+MAX_SOFT_REG_COUNT)
453 #define SOFT_FP_REGNUM (SOFT_REG_LAST)
454 #define SOFT_AP_REGNUM (SOFT_FP_REGNUM+1)
456 /* Number of actual hardware registers. The hardware registers are assigned
457 numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER.
458 All registers that the compiler knows about must be given numbers, even
459 those that are not normally considered general registers. */
460 #define FIRST_PSEUDO_REGISTER (SOFT_REG_LAST+2)
462 /* 1 for registers that have pervasive standard uses and are not available
463 for the register allocator. */
464 #define FIXED_REGISTERS \
465 {0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1,1, 1, SOFT_REG_FIXED, 1, 1}
466 /* X, D, Y, SP,PC,A, B, CCR, Z, FP,ZTMP,ZR,XYR, FK, D1 - D32, SOFT-FP, AP */
468 /* 1 for registers not available across function calls. For our pseudo
469 registers, all are available. */
470 #define CALL_USED_REGISTERS \
471 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1, 1, SOFT_REG_USED, 1, 1}
472 /* X, D, Y, SP,PC,A, B, CCR, Z, FP, ZTMP,ZR,XYR, D1 - 32, SOFT-FP, AP */
475 /* Define this macro to change register usage conditional on target flags.
477 The soft-registers are disabled or enabled according to the
478 -msoft-reg-count=<n> option. */
481 #define CONDITIONAL_REGISTER_USAGE (m68hc11_conditional_register_usage ())
483 /* List the order in which to allocate registers. Each register must be
484 listed once, even those in FIXED_REGISTERS. */
485 #define REG_ALLOC_ORDER \
486 { HARD_D_REGNUM, HARD_X_REGNUM, HARD_Y_REGNUM, \
487 SOFT_REG_ORDER, HARD_Z_REGNUM, HARD_PC_REGNUM, HARD_A_REGNUM, \
488 HARD_B_REGNUM, HARD_CCR_REGNUM, HARD_FP_REGNUM, SOFT_FP_REGNUM, \
489 HARD_SP_REGNUM, SOFT_TMP_REGNUM, SOFT_Z_REGNUM, SOFT_SAVED_XY_REGNUM, \
490 SOFT_AP_REGNUM, FAKE_CLOBBER_REGNUM }
492 /* A C expression for the number of consecutive hard registers,
493 starting at register number REGNO, required to hold a value of
495 #define HARD_REGNO_NREGS(REGNO, MODE) \
496 ((Q_REGNO_P (REGNO)) ? (GET_MODE_SIZE (MODE)) : \
497 ((GET_MODE_SIZE (MODE) + HARD_REG_SIZE - 1) / HARD_REG_SIZE))
499 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
500 - 8 bit values are stored anywhere (except the SP register).
501 - 16 bit values can be stored in any register whose mode is 16
502 - 32 bit values can be stored in D, X registers or in a soft register
503 (except the last one because we need 2 soft registers)
504 - Values whose size is > 32 bit are not stored in real hard
505 registers. They may be stored in soft registers if there are
507 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
508 hard_regno_mode_ok (REGNO,MODE)
510 /* Value is 1 if it is a good idea to tie two pseudo registers when one has
511 mode MODE1 and one has mode MODE2. If HARD_REGNO_MODE_OK could produce
512 different values for MODE1 and MODE2, for any hard reg, then this must be
513 0 for correct output.
515 All modes are tieable except QImode. */
516 #define MODES_TIEABLE_P(MODE1, MODE2) \
517 (((MODE1) == (MODE2)) \
518 || ((MODE1) != QImode && (MODE2) != QImode))
521 /* Define the classes of registers for register constraints in the
522 machine description. Also define ranges of constants.
524 One of the classes must always be named ALL_REGS and include all hard regs.
525 If there is more than one class, another class must be named NO_REGS
526 and contain no registers.
528 The name GENERAL_REGS must be the name of a class (or an alias for
529 another name such as ALL_REGS). This is the class of registers
530 that is allowed by "g" or "r" in a register constraint.
531 Also, registers outside this class are allocated only when
532 instructions express preferences for them.
534 The classes must be numbered in nondecreasing order; that is,
535 a larger-numbered class must never be contained completely
536 in a smaller-numbered class.
538 For any two classes, it is very desirable that there be another
539 class that represents their union. */
541 /* The M68hc11 has so fiew registers that it's not possible for GCC to
542 do any register allocation without breaking. We extend the processor
543 registers by having soft registers. These registers are treated as
544 hard registers by GCC but they are located in memory and accessed by page0
545 accesses (IND mode). */
549 D_REGS, /* 16-bit data register */
550 X_REGS, /* 16-bit X register */
551 Y_REGS, /* 16-bit Y register */
552 SP_REGS, /* 16 bit stack pointer */
553 DA_REGS, /* 8-bit A reg. */
554 DB_REGS, /* 8-bit B reg. */
555 Z_REGS, /* 16-bit fake Z register */
556 D8_REGS, /* 8-bit A or B reg. */
557 Q_REGS, /* 8-bit (byte (QI)) data (A, B or D) */
558 D_OR_X_REGS, /* D or X register */
559 D_OR_Y_REGS, /* D or Y register */
560 D_OR_SP_REGS, /* D or SP register */
561 X_OR_Y_REGS, /* IX or Y register */
562 A_REGS, /* 16-bit address register (X, Y, Z) */
563 X_OR_SP_REGS, /* X or SP register */
564 Y_OR_SP_REGS, /* Y or SP register */
565 X_OR_Y_OR_D_REGS, /* X, Y or D */
566 A_OR_D_REGS, /* X, Y, Z or D */
567 A_OR_SP_REGS, /* X, Y, Z or SP */
568 H_REGS, /* 16-bit hard register (D, X, Y, Z, SP) */
569 S_REGS, /* 16-bit soft register */
570 D_OR_S_REGS, /* 16-bit soft register or D register */
571 X_OR_S_REGS, /* 16-bit soft register or X register */
572 Y_OR_S_REGS, /* 16-bit soft register or Y register */
573 SP_OR_S_REGS, /* 16-bit soft register or SP register */
574 D_OR_X_OR_S_REGS, /* 16-bit soft register or D or X register */
575 D_OR_Y_OR_S_REGS, /* 16-bit soft register or D or Y register */
576 D_OR_SP_OR_S_REGS, /* 16-bit soft register or D or SP register */
577 A_OR_S_REGS, /* 16-bit soft register or X, Y registers */
578 D_OR_A_OR_S_REGS, /* 16-bit soft register or D, X, Y registers */
579 TMP_REGS, /* 16 bit fake scratch register */
580 D_OR_A_OR_TMP_REGS, /* General scratch register */
581 G_REGS, /* 16-bit general register
582 (H_REGS + soft registers) */
587 /* alias GENERAL_REGS to G_REGS. */
588 #define GENERAL_REGS G_REGS
590 #define N_REG_CLASSES (int) LIM_REG_CLASSES
592 /* Give names of register classes as strings for dump file. */
593 #define REG_CLASS_NAMES \
611 "X_OR_Y_OR_D_REGS", \
620 "D_OR_X_OR_S_REGS", \
621 "D_OR_Y_OR_S_REGS", \
622 "D_OR_SP_OR_S_REGS", \
624 "D_OR_A_OR_S_REGS", \
626 "D_OR_A_OR_TMP_REGS", \
630 /* An initializer containing the contents of the register classes,
631 as integers which are bit masks. The Nth integer specifies the
632 contents of class N. The way the integer MASK is interpreted is
633 that register R is in the class if `MASK & (1 << R)' is 1. */
635 /*--------------------------------------------------------------
650 Di 0xFFFFc000, 0x03FFF
651 SFRAME 0x00000000, 0x04000
652 AP 0x00000000, 0x08000
654 D_OR_X_REGS represents D+X. It is used for 32-bits numbers.
655 A_REGS represents a valid base register for indexing. It represents
656 X,Y and the Z register.
657 S_REGS represents the soft-registers. This includes the hard frame
658 and soft frame registers.
659 --------------------------------------------------------------*/
661 #define REG_CLASS_CONTENTS \
662 /* NO_REGS */ {{ 0x00000000, 0x00000000 }, \
663 /* D_REGS */ { 0x00000002, 0x00000000 }, /* D */ \
664 /* X_REGS */ { 0x00000001, 0x00000000 }, /* X */ \
665 /* Y_REGS */ { 0x00000004, 0x00000000 }, /* Y */ \
666 /* SP_REGS */ { 0x00000008, 0x00000000 }, /* SP */ \
667 /* DA_REGS */ { 0x00000020, 0x00000000 }, /* A */ \
668 /* DB_REGS */ { 0x00000040, 0x00000000 }, /* B */ \
669 /* Z_REGS */ { 0x00000100, 0x00000000 }, /* Z */ \
670 /* D8_REGS */ { 0x00000060, 0x00000000 }, /* A B */ \
671 /* Q_REGS */ { 0x00000062, 0x00000000 }, /* A B D */ \
672 /* D_OR_X_REGS */ { 0x00000003, 0x00000000 }, /* D X */ \
673 /* D_OR_Y_REGS */ { 0x00000006, 0x00000000 }, /* D Y */ \
674 /* D_OR_SP_REGS */ { 0x0000000A, 0x00000000 }, /* D SP */ \
675 /* X_OR_Y_REGS */ { 0x00000005, 0x00000000 }, /* X Y */ \
676 /* A_REGS */ { 0x00000105, 0x00000000 }, /* X Y Z */ \
677 /* X_OR_SP_REGS */ { 0x00000009, 0x00000000 }, /* X SP */ \
678 /* Y_OR_SP_REGS */ { 0x0000000C, 0x00000000 }, /* Y SP */ \
679 /* X_OR_Y_OR_D_REGS */ { 0x00000007, 0x00000000 }, /* D X Y */ \
680 /* A_OR_D_REGS */ { 0x00000107, 0x00000000 }, /* D X Y Z */ \
681 /* A_OR_SP_REGS */ { 0x0000010D, 0x00000000 }, /* X Y SP */ \
682 /* H_REGS */ { 0x0000010F, 0x00000000 }, /* D X Y SP */ \
683 /* S_REGS */ { 0xFFFFDE00, 0x00007FFF }, /* _.D,..,FP,Z* */ \
684 /* D_OR_S_REGS */ { 0xFFFFDE02, 0x00007FFF }, /* D _.D */ \
685 /* X_OR_S_REGS */ { 0xFFFFDE01, 0x00007FFF }, /* X _.D */ \
686 /* Y_OR_S_REGS */ { 0xFFFFDE04, 0x00007FFF }, /* Y _.D */ \
687 /* SP_OR_S_REGS */ { 0xFFFFDE08, 0x00007FFF }, /* SP _.D */ \
688 /* D_OR_X_OR_S_REGS */ { 0xFFFFDE03, 0x00007FFF }, /* D X _.D */ \
689 /* D_OR_Y_OR_S_REGS */ { 0xFFFFDE06, 0x00007FFF }, /* D Y _.D */ \
690 /* D_OR_SP_OR_S_REGS */ { 0xFFFFDE0A, 0x00007FFF }, /* D SP _.D */ \
691 /* A_OR_S_REGS */ { 0xFFFFDF05, 0x00007FFF }, /* X Y _.D */ \
692 /* D_OR_A_OR_S_REGS */ { 0xFFFFDF07, 0x00007FFF }, /* D X Y _.D */ \
693 /* TMP_REGS */ { 0x00002000, 0x00000000 }, /* FAKE */ \
694 /* D_OR_A_OR_TMP_REGS*/ { 0x00002107, 0x00000000 }, /* D X Y Z Fake */ \
695 /* G_REGS */ { 0xFFFFFF1F, 0x00007FFF }, /* ? _.D D X Y */ \
696 /* ALL_REGS*/ { 0xFFFFFFFF, 0x00007FFF }}
699 /* set up a C expression whose value is a register class containing hard
701 #define Q_REGNO_P(REGNO) ((REGNO) == HARD_A_REGNUM \
702 || (REGNO) == HARD_B_REGNUM)
703 #define Q_REG_P(X) (REG_P (X) && Q_REGNO_P (REGNO (X)))
705 #define D_REGNO_P(REGNO) ((REGNO) == HARD_D_REGNUM)
706 #define D_REG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X)))
708 #define DB_REGNO_P(REGNO) ((REGNO) == HARD_B_REGNUM)
709 #define DB_REG_P(X) (REG_P (X) && DB_REGNO_P (REGNO (X)))
710 #define DA_REGNO_P(REGNO) ((REGNO) == HARD_A_REGNUM)
711 #define DA_REG_P(X) (REG_P (X) && DA_REGNO_P (REGNO (X)))
713 #define X_REGNO_P(REGNO) ((REGNO) == HARD_X_REGNUM)
714 #define X_REG_P(X) (REG_P (X) && X_REGNO_P (REGNO (X)))
716 #define Y_REGNO_P(REGNO) ((REGNO) == HARD_Y_REGNUM)
717 #define Y_REG_P(X) (REG_P (X) && Y_REGNO_P (REGNO (X)))
719 #define Z_REGNO_P(REGNO) ((REGNO) == HARD_Z_REGNUM)
720 #define Z_REG_P(X) (REG_P (X) && Z_REGNO_P (REGNO (X)))
722 #define SP_REGNO_P(REGNO) ((REGNO) == HARD_SP_REGNUM)
723 #define SP_REG_P(X) (REG_P (X) && SP_REGNO_P (REGNO (X)))
725 /* Address register. */
726 #define A_REGNO_P(REGNO) ((REGNO) == HARD_X_REGNUM \
727 || (REGNO) == HARD_Y_REGNUM \
728 || (REGNO) == HARD_Z_REGNUM)
729 #define A_REG_P(X) (REG_P (X) && A_REGNO_P (REGNO (X)))
731 /* M68hc11 hard registers. */
732 #define H_REGNO_P(REGNO) (D_REGNO_P (REGNO) || A_REGNO_P (REGNO) \
733 || SP_REGNO_P (REGNO) || Q_REGNO_P (REGNO))
734 #define H_REG_P(X) (REG_P (X) && H_REGNO_P (REGNO (X)))
736 #define FAKE_REGNO_P(REGNO) ((REGNO) == FAKE_CLOBBER_REGNUM)
737 #define FAKE_REG_P(X) (REG_P (X) && FAKE_REGNO_P (REGNO (X)))
739 /* Soft registers (or register emulation for gcc). The temporary register
740 used by insn template must be part of the S_REGS class so that it
741 matches the 'u' constraint. */
742 #define S_REGNO_P(REGNO) ((REGNO) >= SOFT_TMP_REGNUM \
743 && (REGNO) <= SOFT_REG_LAST \
744 && (REGNO) != FAKE_CLOBBER_REGNUM)
745 #define S_REG_P(X) (REG_P (X) && S_REGNO_P (REGNO (X)))
747 #define Z_REGNO_P(REGNO) ((REGNO) == HARD_Z_REGNUM)
748 #define Z_REG_P(X) (REG_P (X) && Z_REGNO_P (REGNO (X)))
750 /* General register. */
751 #define G_REGNO_P(REGNO) (H_REGNO_P (REGNO) || S_REGNO_P (REGNO) \
752 || ((REGNO) == HARD_PC_REGNUM) \
753 || ((REGNO) == HARD_FP_REGNUM) \
754 || ((REGNO) == SOFT_FP_REGNUM) \
755 || ((REGNO) == FAKE_CLOBBER_REGNUM) \
756 || ((REGNO) == SOFT_AP_REGNUM))
758 #define G_REG_P(X) (REG_P (X) && G_REGNO_P (REGNO (X)))
760 #define REGNO_REG_CLASS(REGNO) \
761 (D_REGNO_P (REGNO) ? D_REGS : \
762 (X_REGNO_P (REGNO) ? X_REGS : \
763 (Y_REGNO_P (REGNO) ? Y_REGS : \
764 (SP_REGNO_P (REGNO) ? SP_REGS : \
765 (Z_REGNO_P (REGNO) ? Z_REGS : \
766 (H_REGNO_P (REGNO) ? H_REGS : \
767 (FAKE_REGNO_P (REGNO) ? TMP_REGS : \
768 (S_REGNO_P (REGNO) ? S_REGS : \
769 (DA_REGNO_P (REGNO) ? DA_REGS: \
770 (DB_REGNO_P (REGNO) ? DB_REGS: \
771 (G_REGNO_P (REGNO) ? G_REGS : ALL_REGS)))))))))))
774 /* Get reg_class from a letter in the machine description. */
776 extern enum reg_class m68hc11_tmp_regs_class;
777 #define REG_CLASS_FROM_LETTER(C) \
778 ((C) == 'a' ? DA_REGS : \
779 (C) == 'A' ? A_REGS : \
780 (C) == 'b' ? DB_REGS : \
781 (C) == 'B' ? X_OR_Y_REGS : \
782 (C) == 'd' ? D_REGS : \
783 (C) == 'D' ? D_OR_X_REGS : \
784 (C) == 'q' ? Q_REGS : \
785 (C) == 'h' ? H_REGS : \
786 (C) == 't' ? TMP_REGS : \
787 (C) == 'u' ? S_REGS : \
788 (C) == 'v' ? m68hc11_tmp_regs_class : \
789 (C) == 'w' ? SP_REGS : \
790 (C) == 'x' ? X_REGS : \
791 (C) == 'y' ? Y_REGS : \
792 (C) == 'z' ? Z_REGS : NO_REGS)
794 #define PREFERRED_RELOAD_CLASS(X,CLASS) preferred_reload_class(X,CLASS)
796 #define SMALL_REGISTER_CLASSES 1
798 /* A C expression whose value is nonzero if pseudos that have been
799 assigned to registers of class CLASS would likely be spilled
800 because registers of CLASS are needed for spill registers.
802 The default value of this macro returns 1 if CLASS has exactly one
803 register and zero otherwise. On most machines, this default
804 should be used. Only define this macro to some other expression
805 if pseudo allocated by `local-alloc.c' end up in memory because
806 their hard registers were needed for spill registers. If this
807 macro returns nonzero for those classes, those pseudos will only
808 be allocated by `global.c', which knows how to reallocate the
809 pseudo to another register. If there would not be another
810 register available for reallocation, you should not change the
811 definition of this macro since the only effect of such a
812 definition would be to slow down register allocation. */
814 #define CLASS_LIKELY_SPILLED_P(CLASS) \
815 (((CLASS) == D_REGS) \
816 || ((CLASS) == X_REGS) \
817 || ((CLASS) == Y_REGS) \
818 || ((CLASS) == A_REGS) \
819 || ((CLASS) == SP_REGS) \
820 || ((CLASS) == D_OR_X_REGS) \
821 || ((CLASS) == D_OR_Y_REGS) \
822 || ((CLASS) == X_OR_SP_REGS) \
823 || ((CLASS) == Y_OR_SP_REGS) \
824 || ((CLASS) == D_OR_SP_REGS))
826 /* Return the maximum number of consecutive registers needed to represent
827 mode MODE in a register of class CLASS. */
828 #define CLASS_MAX_NREGS(CLASS, MODE) \
829 (((CLASS) == DA_REGS || (CLASS) == DB_REGS \
830 || (CLASS) == D8_REGS || (CLASS) == Q_REGS) ? GET_MODE_SIZE (MODE) \
831 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
833 /* The letters I, J, K, L and M in a register constraint string
834 can be used to stand for particular ranges of immediate operands.
835 This macro defines what the ranges are.
836 C is the letter, and VALUE is a constant value.
837 Return 1 if VALUE is in the range specified by C.
840 `L' is for range -65536 to 65536
841 `M' is for values whose 16-bit low part is 0
843 'O' is for 16 (for rotate using swap).
844 'P' is for range -8 to 2 (used by addhi_sp)
846 'I', 'J' are not used. */
848 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
849 ((C) == 'K' ? (VALUE) == 0 : \
850 (C) == 'L' ? ((VALUE) >= -65536 && (VALUE) <= 65535) : \
851 (C) == 'M' ? ((VALUE) & 0x0ffffL) == 0 : \
852 (C) == 'N' ? ((VALUE) == 1 || (VALUE) == -1) : \
853 (C) == 'O' ? (VALUE) == 16 : \
854 (C) == 'P' ? ((VALUE) <= 2 && (VALUE) >= -8) : 0)
856 /* Similar, but for floating constants, and defining letters G and H.
859 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
860 ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \
861 && VALUE == CONST0_RTX (GET_MODE (VALUE))) : 0)
863 /* 'U' represents certain kind of memory indexed operand for 68HC12.
864 and any memory operand for 68HC11. */
865 #define EXTRA_CONSTRAINT(OP, C) \
866 ((C) == 'U' ? m68hc11_small_indexed_indirect_p (OP, GET_MODE (OP)) \
867 : (C) == 'Q' ? m68hc11_symbolic_p (OP, GET_MODE (OP)) \
868 : (C) == 'R' ? m68hc11_indirect_p (OP, GET_MODE (OP)) \
869 : (C) == 'S' ? (memory_operand (OP, GET_MODE (OP)) \
870 && non_push_operand (OP, GET_MODE (OP))) : 0)
873 /* Stack layout; function entry, exit and calling. */
875 /* Define this if pushing a word on the stack
876 makes the stack pointer a smaller address. */
877 #define STACK_GROWS_DOWNWARD
879 /* Define this if the nominal address of the stack frame
880 is at the high-address end of the local variables;
881 that is, each additional local variable allocated
882 goes at a more negative offset in the frame.
884 Don't define for 68HC11, the frame pointer is the bottom
885 of local variables. */
886 /* #define FRAME_GROWS_DOWNWARD */
888 /* Define this if successive arguments to a function occupy decreasing
889 addresses in the stack. */
890 /* #define ARGS_GROW_DOWNWARD */
892 /* Offset within stack frame to start allocating local variables at.
893 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
894 first local allocated. Otherwise, it is the offset to the BEGINNING
895 of the first local allocated. */
896 #define STARTING_FRAME_OFFSET 0
898 /* Offset of first parameter from the argument pointer register value. */
900 #define FIRST_PARM_OFFSET(FNDECL) 2
902 /* After the prologue, RA is at 0(AP) in the current frame. */
903 #define RETURN_ADDR_RTX(COUNT, FRAME) \
905 ? gen_rtx_MEM (Pmode, arg_pointer_rtx) \
908 /* Before the prologue, the top of the frame is at 2(sp). */
909 #define INCOMING_FRAME_SP_OFFSET 2
911 /* Define this if functions should assume that stack space has been
912 allocated for arguments even when their values are passed in
915 The value of this macro is the size, in bytes, of the area reserved for
916 arguments passed in registers.
918 This space can either be allocated by the caller or be a part of the
919 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE'
921 /* #define REG_PARM_STACK_SPACE(FNDECL) 2 */
923 /* Define this macro if REG_PARM_STACK_SPACE is defined but stack
924 parameters don't skip the area specified by REG_PARM_STACK_SPACE.
925 Normally, when a parameter is not passed in registers, it is placed on
926 the stack beyond the REG_PARM_STACK_SPACE area. Defining this macro
927 suppresses this behavior and causes the parameter to be passed on the
928 stack in its natural location. */
929 /* #define STACK_PARMS_IN_REG_PARM_AREA */
931 /* Register to use for pushing function arguments. */
932 #define STACK_POINTER_REGNUM HARD_SP_REGNUM
934 /* Base register for access to local variables of the function. */
935 #define FRAME_POINTER_REGNUM SOFT_FP_REGNUM
937 #define HARD_FRAME_POINTER_REGNUM HARD_FP_REGNUM
939 /* Base register for access to arguments of the function. */
940 #define ARG_POINTER_REGNUM SOFT_AP_REGNUM
942 /* Register in which static-chain is passed to a function. */
943 #define STATIC_CHAIN_REGNUM SOFT_Z_REGNUM
946 /* Definitions for register eliminations.
948 This is an array of structures. Each structure initializes one pair
949 of eliminable registers. The "from" register number is given first,
950 followed by "to". Eliminations of the same "from" register are listed
951 in order of preference.
953 We have two registers that are eliminated on the 6811. The psuedo arg
954 pointer and pseudo frame pointer registers can always be eliminated;
955 they are replaced with either the stack or the real frame pointer. */
957 #define ELIMINABLE_REGS \
958 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
959 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
960 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
961 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
963 /* Value should be nonzero if functions must have frame pointers.
964 Zero means the frame pointer need not be set up (and parms may be
965 accessed via the stack pointer) in functions that seem suitable.
966 This is computed in `reload', in reload1.c. */
967 #define FRAME_POINTER_REQUIRED 0
969 /* Given FROM and TO register numbers, say whether this elimination is allowed.
970 Frame pointer elimination is automatically handled.
972 All other eliminations are valid. */
974 #define CAN_ELIMINATE(FROM, TO) \
975 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
976 ? ! frame_pointer_needed \
980 /* Define the offset between two registers, one to be eliminated, and the other
981 its replacement, at the start of a routine. */
983 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
984 { OFFSET = m68hc11_initial_elimination_offset (FROM, TO); }
987 /* Passing Function Arguments on the Stack. */
989 /* When a prototype says `char' or `short', really pass an `int'. */
990 /* #define PROMOTE_PROTOTYPES */
992 /* If we generate an insn to push BYTES bytes, this says how many the
993 stack pointer really advances by. No rounding or alignment needed
995 #define PUSH_ROUNDING(BYTES) (BYTES)
997 /* Value is 1 if returning from a function call automatically pops the
998 arguments described by the number-of-args field in the call. FUNTYPE is
999 the data type of the function (as a tree), or for a library call it is
1000 an identifier node for the subroutine name.
1002 The standard MC6811 call, with arg count word, includes popping the
1003 args as part of the call template. */
1004 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1006 /* Nonzero if type TYPE should be returned in memory.
1007 Blocks and data types largers than 4 bytes cannot be returned
1008 in the register (D + X = 4). */
1009 #define RETURN_IN_MEMORY(TYPE) \
1010 ((TYPE_MODE (TYPE) == BLKmode) \
1011 ? (int_size_in_bytes (TYPE) > 4) \
1012 : (GET_MODE_SIZE (TYPE_MODE (TYPE)) > 4))
1015 /* Passing Arguments in Registers. */
1017 /* Define a data type for recording info about an argument list
1018 during the scan of that argument list. This data type should
1019 hold all necessary information about the function itself
1020 and about the args processed so far, enough to enable macros
1021 such as FUNCTION_ARG to determine where the next arg should go. */
1023 typedef struct m68hc11_args
1029 /* A C expression that indicates when an argument must be passed by reference.
1030 If nonzero for an argument, a copy of that argument is made in memory and a
1031 pointer to the argument is passed instead of the argument itself.
1032 The pointer is passed in whatever way is appropriate for passing a pointer
1035 64-bit numbers are passed by reference. */
1036 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1037 m68hc11_function_arg_pass_by_reference (& (CUM), (MODE), (TYPE), (NAMED))
1040 /* If defined, a C expression which determines whether, and in which direction,
1041 to pad out an argument with extra space. The value should be of type
1042 `enum direction': either `upward' to pad above the argument,
1043 `downward' to pad below, or `none' to inhibit padding.
1045 Structures are stored left shifted in their argument slot. */
1046 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1047 m68hc11_function_arg_padding ((MODE), (TYPE))
1049 /* A C expression that indicates when it is the called function's
1050 responsibility to make a copy of arguments passed by invisible
1051 reference. Normally, the caller makes a copy and passes the
1052 address of the copy to the routine being called. When
1053 FUNCTION_ARG_CALLEE_COPIES is defined and is nonzero, the caller
1054 does not make a copy. Instead, it passes a pointer to the "live"
1055 value. The called function must not modify this value. If it can
1056 be determined that the value won't be modified, it need not make a
1057 copy; otherwise a copy must be made. */
1058 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
1059 ((NAMED) && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
1061 /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a
1062 function whose data type is FNTYPE. For a library call, FNTYPE is 0. */
1063 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1064 (m68hc11_init_cumulative_args (&CUM, FNTYPE, LIBNAME))
1066 /* Update the data in CUM to advance over an argument of mode MODE and data
1067 type TYPE. (TYPE is null for libcalls where that information may not be
1069 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1070 (m68hc11_function_arg_advance (&CUM, MODE, TYPE, NAMED))
1072 /* Define where to put the arguments to a function.
1073 Value is zero to push the argument on the stack,
1074 or a hard register in which to store the argument.
1076 MODE is the argument's machine mode.
1077 TYPE is the data type of the argument (as a tree).
1078 This is null for libcalls where that information may
1080 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1081 the preceding args and about the function being called.
1082 NAMED is nonzero if this argument is a named parameter
1083 (otherwise it is an extra parameter matching an ellipsis). */
1084 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1085 (m68hc11_function_arg (&CUM, MODE, TYPE, NAMED))
1087 /* Define the profitability of saving registers around calls.
1089 Disable this because the saving instructions generated by
1090 caller-save need a reload and the way it is implemented,
1091 it forbids all spill registers at that point. Enabling
1092 caller saving results in spill failure. */
1093 #define CALLER_SAVE_PROFITABLE(REFS,CALLS) 0
1095 /* Implement `va_arg'. */
1096 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1097 m68hc11_va_arg (valist, type)
1099 /* For an arg passed partly in registers and partly in memory,
1100 this is the number of registers used.
1101 For args passed entirely in registers or entirely in memory, zero.
1103 Passing an arg partly in register and memory does not work at all.
1105 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) (0)
1107 /* 1 if N is a possible register number for function argument passing.
1108 D is for 16-bit values, X is for 32-bit (X+D). */
1109 #define FUNCTION_ARG_REGNO_P(N) \
1110 (((N) == HARD_D_REGNUM) || ((N) == HARD_X_REGNUM))
1112 /* All return values are in the D or X+D registers:
1113 - 8 and 16-bit values are returned in D.
1114 BLKmode are passed in D as pointer.
1115 - 32-bit values are returned in X + D.
1116 The high part is passed in X and the low part in D.
1117 For GCC, the register number must be HARD_X_REGNUM. */
1118 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1119 gen_rtx (REG, TYPE_MODE (VALTYPE), \
1120 ((TYPE_MODE (VALTYPE) == BLKmode \
1121 || GET_MODE_SIZE (TYPE_MODE (VALTYPE)) <= 2) \
1122 ? HARD_D_REGNUM : HARD_X_REGNUM))
1124 #define LIBCALL_VALUE(MODE) \
1125 gen_rtx (REG, MODE, \
1126 (((MODE) == BLKmode || GET_MODE_SIZE (MODE) <= 2) \
1127 ? HARD_D_REGNUM : HARD_X_REGNUM))
1129 /* 1 if N is a possible register number for a function value. */
1130 #define FUNCTION_VALUE_REGNO_P(N) \
1131 ((N) == HARD_D_REGNUM || (N) == HARD_X_REGNUM)
1133 /* Register in which address to store a structure value is passed to a
1135 #define STRUCT_VALUE_REGNUM HARD_D_REGNUM
1137 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1138 the stack pointer does not matter. The value is tested only in functions
1139 that have frame pointers. No definition is equivalent to always zero. */
1140 #define EXIT_IGNORE_STACK 0
1143 /* Generating Code for Profiling. */
1145 /* Output assembler code to FILE to increment profiler label # LABELNO
1146 for profiling a function entry. */
1147 #define FUNCTION_PROFILER(FILE, LABELNO) \
1148 fprintf (FILE, "\tldy\t.LP%d\n\tjsr mcount\n", (LABELNO))
1149 /* Length in units of the trampoline for entering a nested function. */
1150 #define TRAMPOLINE_SIZE (TARGET_M6811 ? 11 : 9)
1152 /* A C statement to initialize the variable parts of a trampoline.
1153 ADDR is an RTX for the address of the trampoline; FNADDR is an
1154 RTX for the address of the nested function; STATIC_CHAIN is an
1155 RTX for the static chain value that should be passed to the
1156 function when it is called. */
1157 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1158 m68hc11_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1161 /* `INIT_TARGET_OPTABS'
1162 Define this macro as a C statement that declares additional library
1163 routines renames existing ones. `init_optabs' calls this macro
1164 after initializing all the normal library routines.
1166 Overrides the memcpy */
1168 #define INIT_TARGET_OPTABS \
1171 memcpy_libfunc = gen_rtx_SYMBOL_REF (Pmode, "__memcpy"); \
1172 memcmp_libfunc = gen_rtx_SYMBOL_REF (Pmode, "__memcmp"); \
1173 memset_libfunc = gen_rtx_SYMBOL_REF (Pmode, "__memset"); \
1178 /* Addressing modes, and classification of registers for them. */
1180 /* The 68HC12 has all the post/pre increment/decrement modes. */
1181 #define HAVE_POST_INCREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC)
1182 #define HAVE_PRE_INCREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC)
1183 #define HAVE_POST_DECREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC)
1184 #define HAVE_PRE_DECREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC)
1186 /* The class value for base registers. This depends on the target:
1187 A_REGS for 68HC11 and A_OR_SP_REGS for 68HC12. The class value
1188 is stored at init time. */
1189 extern enum reg_class m68hc11_base_reg_class;
1190 #define BASE_REG_CLASS m68hc11_base_reg_class
1192 /* The class value for index registers. This is NO_REGS for 68HC11. */
1194 extern enum reg_class m68hc11_index_reg_class;
1195 #define INDEX_REG_CLASS m68hc11_index_reg_class
1197 /* These assume that REGNO is a hard or pseudo reg number. They give nonzero
1198 only if REGNO is a hard reg of the suitable class or a pseudo reg currently
1199 allocated to a suitable hard reg. Since they use reg_renumber, they are
1200 safe only once reg_renumber has been allocated, which happens in
1204 /* Internal macro, return 1 if REGNO is a valid base register. */
1205 #define REG_VALID_P(REGNO) (1) /* ? */
1207 extern unsigned char m68hc11_reg_valid_for_base[FIRST_PSEUDO_REGISTER];
1208 #define REG_VALID_FOR_BASE_P(REGNO) \
1209 (REG_VALID_P (REGNO) && (REGNO) < FIRST_PSEUDO_REGISTER \
1210 && m68hc11_reg_valid_for_base[REGNO])
1212 /* Internal macro, return 1 if REGNO is a valid index register. */
1213 extern unsigned char m68hc11_reg_valid_for_index[FIRST_PSEUDO_REGISTER];
1214 #define REG_VALID_FOR_INDEX_P(REGNO) \
1215 (REG_VALID_P (REGNO) >= 0 && (REGNO) < FIRST_PSEUDO_REGISTER \
1216 && m68hc11_reg_valid_for_index[REGNO])
1218 /* Internal macro, the nonstrict definition for REGNO_OK_FOR_BASE_P. */
1219 #define REGNO_OK_FOR_BASE_NONSTRICT_P(REGNO) \
1220 ((REGNO) >= FIRST_PSEUDO_REGISTER \
1221 || REG_VALID_FOR_BASE_P (REGNO) \
1222 || (REGNO) == FRAME_POINTER_REGNUM \
1223 || (REGNO) == HARD_FRAME_POINTER_REGNUM \
1224 || (REGNO) == ARG_POINTER_REGNUM \
1225 || (reg_renumber && REG_VALID_FOR_BASE_P (reg_renumber[REGNO])))
1227 /* Internal macro, the nonstrict definition for REGNO_OK_FOR_INDEX_P. */
1228 #define REGNO_OK_FOR_INDEX_NONSTRICT_P(REGNO) \
1230 && ((REGNO) >= FIRST_PSEUDO_REGISTER \
1231 || REG_VALID_FOR_INDEX_P (REGNO) \
1232 || (reg_renumber && REG_VALID_FOR_INDEX_P (reg_renumber[REGNO]))))
1234 /* Internal macro, the strict definition for REGNO_OK_FOR_BASE_P. */
1235 #define REGNO_OK_FOR_BASE_STRICT_P(REGNO) \
1236 ((REGNO) < FIRST_PSEUDO_REGISTER ? REG_VALID_FOR_BASE_P (REGNO) \
1237 : (reg_renumber && REG_VALID_FOR_BASE_P (reg_renumber[REGNO])))
1239 /* Internal macro, the strict definition for REGNO_OK_FOR_INDEX_P. */
1240 #define REGNO_OK_FOR_INDEX_STRICT_P(REGNO) \
1242 && ((REGNO) < FIRST_PSEUDO_REGISTER ? REG_VALID_FOR_INDEX_P (REGNO) \
1243 : (reg_renumber && REG_VALID_FOR_INDEX_P (reg_renumber[REGNO]))))
1245 #define REGNO_OK_FOR_BASE_P2(REGNO,STRICT) \
1246 ((STRICT) ? (REGNO_OK_FOR_BASE_STRICT_P (REGNO)) \
1247 : (REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO)))
1249 #define REGNO_OK_FOR_INDEX_P2(REGNO,STRICT) \
1250 ((STRICT) ? (REGNO_OK_FOR_INDEX_STRICT_P (REGNO)) \
1251 : (REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO)))
1253 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_BASE_STRICT_P (REGNO)
1254 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_INDEX_STRICT_P (REGNO)
1256 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_STRICT_P (REGNO (X))
1257 #define REG_OK_FOR_BASE_NONSTRICT_P(X) REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (X))
1258 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_STRICT_P (REGNO (X))
1259 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (X))
1261 /* see PUSH_POP_ADDRESS_P() below for an explanation of this. */
1262 #define IS_STACK_PUSH(operand) \
1263 ((GET_CODE (operand) == MEM) \
1264 && (GET_CODE (XEXP (operand, 0)) == PRE_DEC) \
1265 && (SP_REG_P (XEXP (XEXP (operand, 0), 0))))
1267 #define IS_STACK_POP(operand) \
1268 ((GET_CODE (operand) == MEM) \
1269 && (GET_CODE (XEXP (operand, 0)) == POST_INC) \
1270 && (SP_REG_P (XEXP (XEXP (operand, 0), 0))))
1272 /* 1 if X is an rtx for a constant that is a valid address. */
1273 #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X))
1275 /* Maximum number of registers that can appear in a valid memory address */
1276 #define MAX_REGS_PER_ADDRESS 2
1278 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a
1279 valid memory address for an instruction. The MODE argument is the
1280 machine mode for the MEM expression that wants to use this address. */
1282 /*--------------------------------------------------------------
1283 Valid addresses are either direct or indirect (MEM) versions
1284 of the following forms:
1288 --------------------------------------------------------------*/
1290 /* The range of index that is allowed by indirect addressing. */
1292 #define VALID_MIN_OFFSET m68hc11_min_offset
1293 #define VALID_MAX_OFFSET m68hc11_max_offset
1295 /* The offset values which are allowed by the n,x and n,y addressing modes.
1296 Take into account the size of the mode because we may have to add
1297 a mode offset to access the lowest part of the data.
1298 (For example, for an SImode, the last valid offset is 252.) */
1299 #define VALID_CONSTANT_OFFSET_P(X,MODE) \
1300 (((GET_CODE (X) == CONST_INT) && \
1301 ((INTVAL (X) >= VALID_MIN_OFFSET) \
1302 && ((INTVAL (X) <= VALID_MAX_OFFSET \
1303 - (HOST_WIDE_INT) (GET_MODE_SIZE (MODE) + 1))))) \
1305 && ((GET_CODE (X) == SYMBOL_REF) \
1306 || GET_CODE (X) == LABEL_REF \
1307 || GET_CODE (X) == CONST)))
1309 /* This is included to allow stack push/pop operations. Special hacks in the
1310 md and m6811.c files exist to support this. */
1311 #define PUSH_POP_ADDRESS_P(X) \
1312 (((GET_CODE (X) == PRE_DEC) || (GET_CODE (X) == POST_INC)) \
1313 && SP_REG_P (XEXP (X, 0)))
1315 /* Go to ADDR if X is a valid address. */
1316 #ifndef REG_OK_STRICT
1317 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1319 if (m68hc11_go_if_legitimate_address ((X), (MODE), 0)) goto ADDR; \
1322 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1324 if (m68hc11_go_if_legitimate_address ((X), (MODE), 1)) goto ADDR; \
1328 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check its
1329 validity for a certain class. We have two alternate definitions for each
1330 of them. The usual definition accepts all pseudo regs; the other rejects
1331 them unless they have been allocated suitable hard regs. The symbol
1332 REG_OK_STRICT causes the latter definition to be used.
1334 Most source files want to accept pseudo regs in the hope that they will
1335 get allocated to the class that the insn wants them to be in. Source files
1336 for reload pass need to be strict. After reload, it makes no difference,
1337 since pseudo regs have been eliminated by then. */
1339 #ifndef REG_OK_STRICT
1340 /* Nonzero if X is a hard reg that can be used as a base reg. */
1341 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X)
1343 /* Nonzero if X is a hard reg that can be used as an index. */
1344 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X)
1346 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X)
1347 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X)
1351 /* Try machine-dependent ways of modifying an illegitimate address
1352 to be legitimate. If we find one, return the new, valid address.
1353 This macro is used in only one place: `memory_address' in explow.c.
1355 OLDX is the address as it was before break_out_memory_refs was called.
1356 In some cases it is useful to look at this to decide what needs to be done.
1358 MODE and WIN are passed so that this macro can use
1359 GO_IF_LEGITIMATE_ADDRESS.
1361 It is always safe for this macro to do nothing.
1362 It exists to recognize opportunities to optimize the output. */
1364 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1365 { rtx operand = (X); \
1366 if (m68hc11_legitimize_address (&operand, (OLDX), (MODE))) \
1369 GO_IF_LEGITIMATE_ADDRESS (MODE,X,WIN); \
1373 /* Go to LABEL if ADDR (a legitimate address expression)
1374 has an effect that depends on the machine mode it is used for. */
1375 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1377 if (GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
1378 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
1382 /* Nonzero if the constant value X is a legitimate general operand.
1383 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1385 #define LEGITIMATE_CONSTANT_P(X) 1
1388 /* Tell final.c how to eliminate redundant test instructions. */
1390 #define NOTICE_UPDATE_CC(EXP, INSN) \
1391 m68hc11_notice_update_cc ((EXP), (INSN))
1393 /* Compute the cost of computing a constant rtl expression RTX whose rtx-code
1394 is CODE. The body of this macro is a portion of a switch statement. If
1395 the code is computed here, return it with a return statement. Otherwise,
1396 break from the switch.
1398 Constants are cheap. Moving them in registers must be avoided
1399 because most instructions do not handle two register operands. */
1400 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1402 /* Logical and arithmetic operations with a constant */ \
1403 /* operand are better because they are not supported */ \
1404 /* with two registers. */ \
1405 /* 'clr' is slow */ \
1406 if ((OUTER_CODE) == SET && (RTX) == const0_rtx) \
1407 /* After reload, the reload_cse pass checks the cost */ \
1408 /* to change a SET into a PLUS. Make const0 cheap. */ \
1409 return 1 - reload_completed; \
1415 if ((OUTER_CODE) == SET) \
1416 return 1 - reload_completed; \
1418 case CONST_DOUBLE: \
1421 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1441 case IF_THEN_ELSE: \
1442 return m68hc11_rtx_costs (X, CODE, OUTER_CODE);
1444 /* An expression giving the cost of an addressing mode that contains
1445 ADDRESS. If not defined, the cost is computed from the ADDRESS
1446 expression and the `CONST_COSTS' values. */
1448 #define ADDRESS_COST(RTX) m68hc11_address_cost (RTX)
1450 /* Move costs between classes of registers */
1451 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1452 (m68hc11_register_move_cost (MODE, CLASS1, CLASS2))
1454 /* Move cost between register and memory.
1455 - Move to a 16-bit register is reasonable,
1456 - Move to a soft register can be expensive. */
1457 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
1458 m68hc11_memory_move_cost ((MODE),(CLASS),(IN))
1460 /* A C expression for the cost of a branch instruction. A value of 1
1461 is the default; other values are interpreted relative to that.
1463 Pretend branches are cheap because GCC generates sub-optimal code
1464 for the default value. */
1465 #define BRANCH_COST 0
1467 /* Nonzero if access to memory by bytes is slow and undesirable. */
1468 #define SLOW_BYTE_ACCESS 0
1470 /* It is as good to call a constant function address as to call an address
1471 kept in a register. */
1472 #define NO_FUNCTION_CSE
1474 /* Try a machine-dependent way of reloading an illegitimate address
1475 operand. If we find one, push the reload and jump to WIN. This
1476 macro is used in only one place: `find_reloads_address' in reload.c.
1478 For M68HC11, we handle large displacements of a base register
1479 by splitting the addend accors an addhi3 insn.
1481 For M68HC12, the 64K offset range is available.
1484 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1486 /* We must recognize output that we have already generated ourselves. */ \
1487 if (GET_CODE (X) == PLUS \
1488 && GET_CODE (XEXP (X, 0)) == PLUS \
1489 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1490 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1491 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1493 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1494 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1498 if (GET_CODE (X) == PLUS \
1499 && GET_CODE (XEXP (X, 0)) == REG \
1500 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1501 && !VALID_CONSTANT_OFFSET_P (XEXP (X, 1), MODE)) \
1503 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1504 HOST_WIDE_INT low, high; \
1505 high = val & (~0x0FF); \
1506 low = val & 0x00FF; \
1507 if (low >= 256-15) { high += 16; low -= 16; } \
1508 /* Reload the high part into a base reg; leave the low part \
1509 in the mem directly. */ \
1511 X = gen_rtx_PLUS (Pmode, \
1512 gen_rtx_PLUS (Pmode, XEXP (X, 0), \
1516 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1517 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1524 /* Defining the Output Assembler Language. */
1526 /* A default list of other sections which we might be "in" at any given
1527 time. For targets that use additional sections (e.g. .tdesc) you
1528 should override this definition in the target-specific file which
1529 includes this file. */
1531 /* Output before read-only data. */
1532 #define TEXT_SECTION_ASM_OP ("\t.sect\t.text")
1534 /* Output before writable data. */
1535 #define DATA_SECTION_ASM_OP ("\t.sect\t.data")
1537 /* Output before uninitialized data. */
1538 #define BSS_SECTION_ASM_OP ("\t.sect\t.bss")
1540 /* Define the pseudo-ops used to switch to the .ctors and .dtors sections.
1542 Same as config/elfos.h but don't mark these section SHF_WRITE since
1543 there is no shared library problem. */
1544 #undef CTORS_SECTION_ASM_OP
1545 #define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"a\""
1547 #undef DTORS_SECTION_ASM_OP
1548 #define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"a\""
1550 #define TARGET_ASM_CONSTRUCTOR m68hc11_asm_out_constructor
1551 #define TARGET_ASM_DESTRUCTOR m68hc11_asm_out_destructor
1553 /* This is how to begin an assembly language file. Most svr4 assemblers want
1554 at least a .file directive to come first, and some want to see a .version
1555 directive come right after that. Here we just establish a default
1556 which generates only the .file directive. If you need a .version
1557 directive for any specific target, you should override this definition
1558 in the target-specific file which includes this one. */
1560 #undef ASM_FILE_START
1561 #define ASM_FILE_START(FILE) \
1562 m68hc11_asm_file_start ((FILE), main_input_filename)
1564 /* Comment character */
1565 #define ASM_COMMENT_START ";"
1567 /* Output to assembler file text saying following lines
1568 may contain character constants, extra white space, comments, etc. */
1569 #define ASM_APP_ON "; Begin inline assembler code\n#APP\n"
1571 /* Output to assembler file text saying following lines
1572 no longer contain unusual constructs. */
1573 #define ASM_APP_OFF "; End of inline assembler code\n#NO_APP\n"
1575 /* Write the extra assembler code needed to declare a function properly.
1576 Some svr4 assemblers need to also have something extra said about the
1577 function's return value. We allow for that here.
1579 For 68HC12 we mark functions that return with 'rtc'. The linker
1580 will ensure that a 'call' is really made (instead of 'jsr').
1581 The debugger needs this information to correctly compute the stack frame.
1583 For 68HC11/68HC12 we also mark interrupt handlers for gdb to
1584 compute the correct stack frame. */
1586 #undef ASM_DECLARE_FUNCTION_NAME
1587 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
1590 fprintf (FILE, "%s", TYPE_ASM_OP); \
1591 assemble_name (FILE, NAME); \
1593 fprintf (FILE, TYPE_OPERAND_FMT, "function"); \
1594 putc ('\n', FILE); \
1596 if (TARGET_M6812 && current_function_far) \
1598 fprintf (FILE, "\t.far\t"); \
1599 assemble_name (FILE, NAME); \
1600 putc ('\n', FILE); \
1602 else if (current_function_interrupt \
1603 || current_function_trap) \
1605 fprintf (FILE, "\t.interrupt\t"); \
1606 assemble_name (FILE, NAME); \
1607 putc ('\b', FILE); \
1609 ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \
1610 ASM_OUTPUT_LABEL(FILE, NAME); \
1614 /* Output #ident as a .ident. */
1616 /* output external reference */
1617 #define ASM_OUTPUT_EXTERNAL(FILE,DECL,NAME) \
1618 {fputs ("\t; extern\t", FILE); \
1619 assemble_name (FILE, NAME); \
1620 fputs ("\n", FILE);}
1622 /* How to refer to registers in assembler output. This sequence is indexed
1623 by compiler's hard-register-number (see above). */
1624 #define REGISTER_NAMES \
1625 { "x", "d", "y", "sp", "pc", "a", "b", "ccr", "z", \
1626 "*_.frame", "*_.tmp", "*_.z", "*_.xy", "*fake clobber", \
1627 SOFT_REG_NAMES, "*sframe", "*ap"}
1629 /* Print an instruction operand X on file FILE. CODE is the code from the
1630 %-spec for printing this operand. If `%z3' was used to print operand
1631 3, then CODE is 'z'. */
1633 #define PRINT_OPERAND(FILE, X, CODE) \
1634 print_operand (FILE, X, CODE)
1636 /* Print a memory operand whose address is X, on file FILE. */
1637 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1638 print_operand_address (FILE, ADDR)
1640 /* This is how to output an insn to push/pop a register on the stack.
1641 It need not be very fast code.
1643 Don't define because we don't know how to handle that with
1644 the STATIC_CHAIN_REGNUM (soft register). Saving the static
1645 chain must be made inside FUNCTION_PROFILER. */
1647 #undef ASM_OUTPUT_REG_PUSH
1648 #undef ASM_OUTPUT_REG_POP
1650 /* This is how to output an element of a case-vector that is relative. */
1652 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1653 fprintf (FILE, "\t%s\tL%d-L%d\n", integer_asm_op (2, TRUE), VALUE, REL)
1655 /* This is how to output an element of a case-vector that is absolute. */
1656 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1657 fprintf (FILE, "\t%s\t.L%d\n", integer_asm_op (2, TRUE), VALUE)
1659 /* This is how to output an assembler line that says to advance the
1660 location counter to a multiple of 2**LOG bytes. */
1661 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1664 fprintf ((FILE), "%s\n", ALIGN_ASM_OP); \
1668 /* Assembler Commands for Exception Regions. */
1670 /* Default values provided by GCC should be ok. Assumming that DWARF-2
1671 frame unwind info is ok for this platform. */
1673 #undef PREFERRED_DEBUGGING_TYPE
1674 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1676 /* The prefix for local labels. You should be able to define this as
1677 an empty string, or any arbitrary string (such as ".", ".L%", etc)
1678 without having to make any other changes to account for the specific
1679 definition. Note it is a string literal, not interpreted by printf
1681 #define LOCAL_LABEL_PREFIX "."
1683 /* The prefix for immediate operands. */
1684 #define IMMEDIATE_PREFIX "#"
1685 #define GLOBAL_ASM_OP "\t.globl\t"
1688 /* Miscellaneous Parameters. */
1690 /* Define the codes that are matched by predicates in m68hc11.c. */
1691 #define PREDICATE_CODES \
1692 {"stack_register_operand", {SUBREG, REG}}, \
1693 {"d_register_operand", {SUBREG, REG}}, \
1694 {"hard_addr_reg_operand", {SUBREG, REG}}, \
1695 {"hard_reg_operand", {SUBREG, REG}}, \
1696 {"m68hc11_logical_operator", {AND, IOR, XOR}}, \
1697 {"m68hc11_arith_operator", {AND, IOR, XOR, PLUS, MINUS, \
1698 ASHIFT, ASHIFTRT, LSHIFTRT, \
1699 ROTATE, ROTATERT }}, \
1700 {"m68hc11_non_shift_operator", {AND, IOR, XOR, PLUS, MINUS}}, \
1701 {"m68hc11_unary_operator", {NEG, NOT, SIGN_EXTEND, ZERO_EXTEND}}, \
1702 {"non_push_operand", {SUBREG, REG, MEM}}, \
1703 {"reg_or_some_mem_operand", {SUBREG, REG, MEM}}, \
1704 {"tst_operand", {SUBREG, REG, MEM}}, \
1705 {"cmp_operand", {SUBREG, REG, MEM, SYMBOL_REF, LABEL_REF, \
1706 CONST_INT, CONST_DOUBLE}},
1708 /* Specify the machine mode that this machine uses
1709 for the index in the tablejump instruction. */
1710 #define CASE_VECTOR_MODE Pmode
1712 /* This flag, if defined, says the same insns that convert to a signed fixnum
1713 also convert validly to an unsigned one. */
1714 #define FIXUNS_TRUNC_LIKE_FIX_TRUNC
1716 /* Max number of bytes we can move from memory to memory in one
1717 reasonably fast instruction. */
1720 /* MOVE_RATIO is the number of move instructions that is better than a
1721 block move. Make this small on 6811, since the code size grows very
1722 large with each move. */
1723 #define MOVE_RATIO 3
1725 /* Define if shifts truncate the shift count which implies one can omit
1726 a sign-extension or zero-extension of a shift count. */
1727 #define SHIFT_COUNT_TRUNCATED 1
1729 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1730 is done just by pretending it is already truncated. */
1731 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1733 /* Specify the machine mode that pointers have. After generation of rtl, the
1734 compiler makes no further distinction between pointers and any other
1735 objects of this machine mode. */
1736 #define Pmode HImode
1738 /* A function address in a call instruction is a byte address (for indexing
1739 purposes) so give the MEM rtx a byte's mode. */
1740 #define FUNCTION_MODE QImode
1742 /* Allow $ in identifiers */
1743 #define DOLLARS_IN_IDENTIFIERS 1
1745 /* Machine-dependent reorg pass.
1746 Specific optimizations are defined here:
1747 - this pass changes the Z register into either X or Y
1748 (it preserves X/Y previous values in a memory slot in page0).
1750 When this pass is finished, the global variable
1751 'z_replacement_completed' is set to 2. */
1752 #define MACHINE_DEPENDENT_REORG(X) m68hc11_reorg (X)
1754 extern int debug_m6811;
1755 extern int z_replacement_completed;
1756 extern int current_function_interrupt;
1757 extern int current_function_trap;
1758 extern int current_function_far;