1 /* Definitions of target machine for GNU compiler.
2 Motorola 68HC11 and 68HC12.
3 Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
4 Contributed by Stephane Carrez (stcarrez@worldnet.fr)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA.
24 A first 68HC11 port was made by Otto Lind (otto@coactive.com)
25 on gcc 2.6.3. I have used it as a starting point for this port.
26 However, this new port is a complete re-write. Its internal
27 design is completely different. The generated code is not
28 compatible with the gcc 2.6.3 port.
30 The gcc 2.6.3 port is available at:
32 ftp.unina.it/pub/electronics/motorola/68hc11/gcc/gcc-6811-fsf.tar.gz
36 /*****************************************************************************
38 ** Controlling the Compilation Driver, `gcc'
40 *****************************************************************************/
44 /* Compile and assemble for a 68hc11 unless there is a -m68hc12 option. */
46 #define ASM_SPEC "%{m68hc12:-m68hc12}%{!m68hc12:-m68hc11}"
49 /* We need to tell the linker the target elf format. Just pass an
50 emulation option. This can be overriden by -Wl option of gcc. */
52 #define LINK_SPEC "%{m68hc12:-m m68hc12elf}%{!m68hc12:-m m68hc11elf}"
65 "%{mshort:-D__HAVE_SHORT_INT__ -D__INT__=16 -D__INT_MAX__=32767}\
66 %{!mshort:-D__INT__=32 -D__INT_MAX__=2147483647}\
67 %{m68hc12:-Dmc6812 -DMC6812 -Dmc68hc12}\
68 %{!m68hc12:-Dmc6811 -DMC6811 -Dmc68hc11}\
69 %{fshort-double:-D__HAVE_SHORT_DOUBLE__}"
73 #define STARTFILE_SPEC "crt1%O%s"
75 /* Names to predefine in the preprocessor for this target machine. */
76 #define CPP_PREDEFINES "-Dmc68hc1x"
78 /* As an embedded target, we have no libc. */
81 /* Forward type declaration for prototypes definitions.
82 rtx_ptr is equivalent to rtx. Can't use the same name. */
84 typedef struct rtx_def *rtx_ptr;
87 typedef union tree_node *tree_ptr;
89 /* We can't declare enum machine_mode forward nor include 'machmode.h' here.
90 Prototypes defined here will use an int instead. It's better than no
92 typedef int enum_machine_mode;
94 /*****************************************************************************
96 ** Run-time Target Specification
98 *****************************************************************************/
100 /* Run-time compilation parameters selecting different hardware subsets. */
102 extern int target_flags;
104 extern short *reg_renumber; /* def in local_alloc.c */
106 /* Macros used in the machine description to test the flags. */
108 /* 6811 specific options
110 * For 68HC12, the auto inc/dec mode is disabled by default. The reason
111 * is that for most programs, the reload pass will fail because it needs
112 * more registers to save the value of the indexed register after the
113 * memory access. For simple programs, you can enable this
114 * with -mauto-incdec.
117 #define MASK_SHORT 0002 /* Compile with 16-bit `int' */
118 #define MASK_AUTO_INC_DEC 0004
119 #define MASK_M6811 0010
120 #define MASK_M6812 0020
122 #define TARGET_OP_TIME (optimize && optimize_size == 0)
123 #define TARGET_SHORT (target_flags & MASK_SHORT)
124 #define TARGET_M6811 (target_flags & MASK_M6811)
125 #define TARGET_M6812 (target_flags & MASK_M6812)
126 #define TARGET_AUTO_INC_DEC (target_flags & MASK_AUTO_INC_DEC)
128 /* Default target_flags if no switches specified. */
129 #ifndef TARGET_DEFAULT
130 # define TARGET_DEFAULT (MASK_M6811)
133 /* Define this macro as a C expression for the initializer of an
134 array of string to tell the driver program which options are
135 defaults for this target and thus do not need to be handled
136 specially when using `MULTILIB_OPTIONS'. */
137 #ifndef MULTILIB_DEFAULTS
138 # if TARGET_DEFAULT & MASK_M6811
139 # define MULTILIB_DEFAULTS { "m68hc11" }
141 # define MULTILIB_DEFAULTS { "m68hc12" }
145 /* Macro to define tables used to set the flags. This is a list in braces of
146 pairs in braces, each pair being { "NAME", VALUE } where VALUE is the bits
147 to set or minus the bits to clear. An empty string NAME is used to
148 identify the default VALUE. */
150 #define TARGET_SWITCHES \
151 { { "short", MASK_SHORT, \
152 N_("Compile with 16-bit integer mode")}, \
153 { "noshort", - MASK_SHORT, \
154 N_("Compile with 32-bit integer mode")}, \
155 { "auto-incdec", MASK_AUTO_INC_DEC, \
156 N_("Auto pre/post decrement increment allowed")}, \
157 { "noauto-incdec", - MASK_AUTO_INC_DEC, \
158 N_("Auto pre/post decrement increment not allowed")}, \
159 { "68hc11", MASK_M6811, \
160 N_("Compile for a 68HC11")}, \
161 { "68hc12", MASK_M6812, \
162 N_("Compile for a 68HC12")}, \
163 { "6811", MASK_M6811, \
164 N_("Compile for a 68HC11")}, \
165 { "6812", MASK_M6812, \
166 N_("Compile for a 68HC12")}, \
167 { "", TARGET_DEFAULT, 0 }}
169 /* This macro is similar to `TARGET_SWITCHES' but defines names of
170 command options that have values. Its definition is an
171 initializer with a subgrouping for each command option.
173 Each subgrouping contains a string constant, that defines the
174 fixed part of the option name, and the address of a variable. The
175 variable, type `char *', is set to the variable part of the given
176 option if the fixed part matches. The actual option name is made
177 by appending `-m' to the specified name. */
178 #define TARGET_OPTIONS \
179 { { "reg-alloc=", &m68hc11_reg_alloc_order, \
180 N_("Specify the register allocation order")}, \
181 { "soft-reg-count=", &m68hc11_soft_reg_count, \
182 N_("Indicate the number of soft registers available") }, \
186 /* These are meant to be redefined in the host dependent files */
187 #define SUBTARGET_SWITCHES
188 #define SUBTARGET_OPTIONS
190 extern const char *m68hc11_regparm_string;
191 extern const char *m68hc11_reg_alloc_order;
192 extern const char *m68hc11_soft_reg_count;
194 #ifndef TARGET_M68HC12
195 # define TARGET_M68HC11 1
198 /* Print subsidiary information on the compiler version in use. */
199 #define TARGET_VERSION fprintf (stderr, " (MC68HC11/MC68HC12)")
201 /* Sometimes certain combinations of command options do not make
202 sense on a particular target machine. You can define a macro
203 `OVERRIDE_OPTIONS' to take account of this. This macro, if
204 defined, is executed once just after all the command options have
207 Don't use this macro to turn on various extra optimizations for
208 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
210 #define OVERRIDE_OPTIONS m68hc11_override_options ();
213 /* Define cost parameters for a given processor variant. */
214 struct processor_costs {
215 int add; /* cost of an add instruction */
216 int logical; /* cost of a logical instruction */
218 int shiftQI_const[8];
219 int shiftHI_const[16];
228 /* Costs for the current processor. */
229 extern struct processor_costs *m68hc11_cost;
232 /* target machine storage layout */
234 /* Define this if most significant byte of a word is the lowest numbered. */
235 #define BYTES_BIG_ENDIAN 1
237 /* Define this if most significant bit is lowest numbered
238 in instructions that operate on numbered bit-fields. */
239 #define BITS_BIG_ENDIAN 0
241 /* Define this if most significant word of a multiword number is numbered. */
242 #define WORDS_BIG_ENDIAN 1
244 /* Number of bits in an addressible storage unit */
245 #define BITS_PER_UNIT 8
247 /* Number of bits in a word */
248 #define BITS_PER_WORD 16
250 /* Width of a word, in units (bytes). */
251 #define UNITS_PER_WORD (BITS_PER_WORD/8)
253 /* Define if you don't want extended real, but do want to use the
254 software floating point emulator for REAL_ARITHMETIC and
255 decimal <-> binary conversion. */
256 #define REAL_ARITHMETIC
258 /* Width in bits of a pointer. See also the macro `Pmode' defined below. */
259 #define POINTER_SIZE 16
261 /* Definition of size_t. This is really an unsigned short as the
262 68hc11 only handles a 64K address space. */
263 #define SIZE_TYPE "short unsigned int"
265 /* A C expression for a string describing the name of the data type
266 to use for the result of subtracting two pointers. The typedef
267 name `ptrdiff_t' is defined using the contents of the string.
268 The 68hc11 only has a 64K address space. */
269 #define PTRDIFF_TYPE "short int"
271 /* Allocation boundary (bits) for storing pointers in memory. */
272 #define POINTER_BOUNDARY 8
274 /* Normal alignment required for function parameters on the stack, in bits.
275 This can't be less than BITS_PER_WORD */
276 #define PARM_BOUNDARY (BITS_PER_WORD)
278 /* Boundary (bits) on which stack pointer should be aligned. */
279 #define STACK_BOUNDARY 8
281 /* Allocation boundary (bits) for the code of a function. */
282 #define FUNCTION_BOUNDARY 8
284 /* Biggest alignment that any data type can require on this machine,
286 #define BIGGEST_ALIGNMENT 8
288 /* Alignment of field after `int : 0' in a structure. */
289 #define EMPTY_FIELD_BOUNDARY 8
291 /* Every structure's size must be a multiple of this. */
292 #define STRUCTURE_SIZE_BOUNDARY 8
294 /* Define this if instructions will fail to work if given data not
295 on the nominal alignment. If instructions will merely go slower
296 in that case, do not define this macro. */
297 #define STRICT_ALIGNMENT 0
299 /* An integer expression for the size in bits of the largest integer
300 machine mode that should actually be used. All integer machine modes of
301 this size or smaller can be used for structures and unions with the
302 appropriate sizes. */
303 #define MAX_FIXED_MODE_SIZE 64
305 /* Floats are checked in a generic way. */
306 /* #define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) */
310 /* target machine storage layout */
312 /* Size (bits) of the type "int" on target machine
313 (If undefined, default is BITS_PER_WORD). */
314 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
316 /* Size (bits) of the type "short" on target machine */
317 #define SHORT_TYPE_SIZE 16
319 /* Size (bits) of the type "long" on target machine */
320 #define LONG_TYPE_SIZE 32
322 /* Size (bits) of the type "long long" on target machine */
323 #define LONG_LONG_TYPE_SIZE 64
325 /* Size (bits) of the type "char" on target machine */
326 #define CHAR_TYPE_SIZE 8
328 /* A C expression for the size in bits of the type `float' on the
329 target machine. If you don't define this, the default is one word.
330 Don't use default: a word is only 16. */
331 #define FLOAT_TYPE_SIZE 32
333 /* A C expression for the size in bits of the type double on the target
334 machine. If you don't define this, the default is two words.
335 Be IEEE compliant. */
336 #define DOUBLE_TYPE_SIZE 64
338 #define LONG_DOUBLE_TYPE_SIZE 64
340 /* Define this as 1 if `char' should by default be signed; else as 0. */
341 #define DEFAULT_SIGNED_CHAR 0
343 /* Define these to avoid dependence on meaning of `int'.
344 Note that WCHAR_TYPE_SIZE is used in cexp.y,
345 where TARGET_SHORT is not available. */
346 #define WCHAR_TYPE "short int"
347 #define WCHAR_TYPE_SIZE 16
350 /* Standard register usage. */
352 #define HARD_REG_SIZE (UNITS_PER_WORD)
354 /* Assign names to real MC68HC11 registers.
355 A and B registers are not really used (A+B = D)
356 X register is first so that GCC allocates X+D for 32-bit integers and
357 the lowpart of that integer will be D. Having the lower part in D is
358 better for 32<->16bit conversions and for many arithmetic operations. */
359 #define HARD_X_REGNUM 0
360 #define HARD_D_REGNUM 1
361 #define HARD_Y_REGNUM 2
362 #define HARD_SP_REGNUM 3
363 #define HARD_PC_REGNUM 4
364 #define HARD_A_REGNUM 5
365 #define HARD_B_REGNUM 6
366 #define HARD_CCR_REGNUM 7
368 /* The Z register does not really exist in the 68HC11. This a fake register
369 for GCC. It is treated exactly as an index register (X or Y). It is only
370 in the A_REGS class, which is the BASE_REG_CLASS for GCC. Defining this
371 register helps the reload pass of GCC. Otherwise, the reload often aborts
372 with register spill failures.
374 The Z register is replaced by either X or Y during the machine specific
375 reorg (m68hc11_reorg). It is saved in the SOFT_Z_REGNUM soft-register
376 when this is necessary.
378 It's possible to tell GCC not to use this register with -ffixed-z. */
379 #define HARD_Z_REGNUM 8
381 /* The frame pointer is a soft-register. It's treated as such by GCC:
382 it is not and must not be part of the BASE_REG_CLASS. */
383 #define DEFAULT_HARD_FP_REGNUM (9)
384 #define HARD_FP_REGNUM (9)
385 #define HARD_AP_REGNUM (HARD_FP_REGNUM)
387 /* Temporary soft-register used in some cases when an operand came
388 up into a bad register class (D, X, Y, SP) and gcc failed to
389 recognize this. This register is never allocated by GCC. */
390 #define SOFT_TMP_REGNUM 10
392 /* The soft-register which is used to save the Z register
393 (see Z register replacement notes in m68hc11.c). */
394 #define SOFT_Z_REGNUM 11
396 /* The soft-register which is used to save either X or Y. */
397 #define SOFT_SAVED_XY_REGNUM 12
399 /* A fake clobber register for 68HC12 patterns. */
400 #define FAKE_CLOBBER_REGNUM (13)
402 /* Define 32 soft-registers of 16-bit each. By default,
403 only 12 of them are enabled and can be used by GCC. The
404 -msoft-reg-count=<n> option allows to control the number of valid
405 soft-registers. GCC can put 32-bit values in them
406 by allocating consecutive registers. The first 3 soft-registers
407 are never allocated by GCC. They are used in case the insn template needs
408 a temporary register, or for the Z register replacement. */
410 #define MAX_SOFT_REG_COUNT (32)
411 #define SOFT_REG_FIXED 0, 0, 0, 0, 0, 0, 0, 0, \
412 0, 0, 0, 0, 1, 1, 1, 1, \
413 1, 1, 1, 1, 1, 1, 1, 1, \
414 1, 1, 1, 1, 1, 1, 1, 1
415 #define SOFT_REG_USED 0, 0, 0, 0, 0, 0, 0, 0, \
416 0, 0, 0, 0, 1, 1, 1, 1, \
417 1, 1, 1, 1, 1, 1, 1, 1, \
418 1, 1, 1, 1, 1, 1, 1, 1
419 #define SOFT_REG_ORDER \
420 SOFT_REG_FIRST, SOFT_REG_FIRST+1,SOFT_REG_FIRST+2,SOFT_REG_FIRST+3,\
421 SOFT_REG_FIRST+4, SOFT_REG_FIRST+5,SOFT_REG_FIRST+6,SOFT_REG_FIRST+7,\
422 SOFT_REG_FIRST+8, SOFT_REG_FIRST+9,SOFT_REG_FIRST+10,SOFT_REG_FIRST+11,\
423 SOFT_REG_FIRST+12, SOFT_REG_FIRST+13,SOFT_REG_FIRST+14,SOFT_REG_FIRST+15,\
424 SOFT_REG_FIRST+16, SOFT_REG_FIRST+17,SOFT_REG_FIRST+18,SOFT_REG_FIRST+19,\
425 SOFT_REG_FIRST+20, SOFT_REG_FIRST+21,SOFT_REG_FIRST+22,SOFT_REG_FIRST+23,\
426 SOFT_REG_FIRST+24, SOFT_REG_FIRST+25,SOFT_REG_FIRST+26,SOFT_REG_FIRST+27,\
427 SOFT_REG_FIRST+28, SOFT_REG_FIRST+29,SOFT_REG_FIRST+30,SOFT_REG_FIRST+31
429 #define SOFT_REG_NAMES \
430 "*_.d1", "*_.d2", "*_.d3", "*_.d4", \
431 "*_.d5", "*_.d6", "*_.d7", "*_.d8", \
432 "*_.d9", "*_.d10", "*_.d11", "*_.d12", \
433 "*_.d13", "*_.d14", "*_.d15", "*_.d16", \
434 "*_.d17", "*_.d18", "*_.d19", "*_.d20", \
435 "*_.d21", "*_.d22", "*_.d23", "*_.d24", \
436 "*_.d25", "*_.d26", "*_.d27", "*_.d28", \
437 "*_.d29", "*_.d30", "*_.d31", "*_.d32"
439 /* First available soft-register for GCC. */
440 #define SOFT_REG_FIRST (SOFT_SAVED_XY_REGNUM+2)
442 /* Last available soft-register for GCC. */
443 #define SOFT_REG_LAST (SOFT_REG_FIRST+MAX_SOFT_REG_COUNT)
444 #define SOFT_FP_REGNUM (SOFT_REG_LAST)
445 #define SOFT_AP_REGNUM (SOFT_FP_REGNUM+1)
447 /* Number of actual hardware registers. The hardware registers are assigned
448 numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER.
449 All registers that the compiler knows about must be given numbers, even
450 those that are not normally considered general registers. */
451 #define FIRST_PSEUDO_REGISTER (SOFT_REG_LAST+2)
453 /* 1 for registers that have pervasive standard uses and are not available
454 for the register allocator. */
455 #define FIXED_REGISTERS \
456 {0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1,1, 1, SOFT_REG_FIXED, 1, 1}
457 /* X, D, Y, SP,PC,A, B, CCR, Z, FP,ZTMP,ZR,XYR, FK, D1 - D32, SOFT-FP, AP */
459 /* 1 for registers not available across function calls. For our pseudo
460 registers, all are available. */
461 #define CALL_USED_REGISTERS \
462 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1, 1, SOFT_REG_USED, 1, 1}
463 /* X, D, Y, SP,PC,A, B, CCR, Z, FP, ZTMP,ZR,XYR, D1 - 32, SOFT-FP, AP */
466 /* Define this macro to change register usage conditional on target flags.
468 The soft-registers are disabled or enabled according to the
469 -msoft-reg-count=<n> option. */
472 #define CONDITIONAL_REGISTER_USAGE (m68hc11_conditional_register_usage ())
474 /* List the order in which to allocate registers. Each register must be
475 listed once, even those in FIXED_REGISTERS. */
476 #define REG_ALLOC_ORDER \
477 { HARD_D_REGNUM, HARD_X_REGNUM, HARD_Y_REGNUM, \
478 SOFT_REG_ORDER, HARD_Z_REGNUM, HARD_PC_REGNUM, HARD_A_REGNUM, \
479 HARD_B_REGNUM, HARD_CCR_REGNUM, HARD_FP_REGNUM, SOFT_FP_REGNUM, \
480 HARD_SP_REGNUM, SOFT_TMP_REGNUM, SOFT_Z_REGNUM, SOFT_SAVED_XY_REGNUM, \
481 SOFT_AP_REGNUM, FAKE_CLOBBER_REGNUM }
483 /* A C expression for the number of consecutive hard registers,
484 starting at register number REGNO, required to hold a value of
486 #define HARD_REGNO_NREGS(REGNO, MODE) \
487 ((Q_REGNO_P (REGNO)) ? (GET_MODE_SIZE (MODE)) : \
488 ((GET_MODE_SIZE (MODE) + HARD_REG_SIZE - 1) / HARD_REG_SIZE))
490 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
491 - 8 bit values are stored anywhere (except the SP register).
492 - 16 bit values can be stored in any register whose mode is 16
493 - 32 bit values can be stored in D, X registers or in a soft register
494 (except the last one because we need 2 soft registers)
495 - Values whose size is > 32 bit are not stored in real hard
496 registers. They may be stored in soft registers if there are
498 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
499 hard_regno_mode_ok (REGNO,MODE)
501 /* Value is 1 if it is a good idea to tie two pseudo registers when one has
502 mode MODE1 and one has mode MODE2. If HARD_REGNO_MODE_OK could produce
503 different values for MODE1 and MODE2, for any hard reg, then this must be
504 0 for correct output. */
505 #define MODES_TIEABLE_P(MODE1, MODE2) \
506 (((MODE1) == (MODE2)) \
507 || ((MODE1) == SImode && (MODE2) == HImode) \
508 || ((MODE1) == HImode && (MODE2) == SImode))
511 /* Define the classes of registers for register constraints in the
512 machine description. Also define ranges of constants.
514 One of the classes must always be named ALL_REGS and include all hard regs.
515 If there is more than one class, another class must be named NO_REGS
516 and contain no registers.
518 The name GENERAL_REGS must be the name of a class (or an alias for
519 another name such as ALL_REGS). This is the class of registers
520 that is allowed by "g" or "r" in a register constraint.
521 Also, registers outside this class are allocated only when
522 instructions express preferences for them.
524 The classes must be numbered in nondecreasing order; that is,
525 a larger-numbered class must never be contained completely
526 in a smaller-numbered class.
528 For any two classes, it is very desirable that there be another
529 class that represents their union. */
531 /* The M68hc11 has so fiew registers that it's not possible for GCC to
532 do any register allocation without breaking. We extend the processor
533 registers by having soft registers. These registers are treated as
534 hard registers by GCC but they are located in memory and accessed by page0
535 accesses (IND mode). */
539 D_REGS, /* 16-bit data register */
540 X_REGS, /* 16-bit X register */
541 Y_REGS, /* 16-bit Y register */
542 SP_REGS, /* 16 bit stack pointer */
543 DA_REGS, /* 8-bit A reg. */
544 DB_REGS, /* 8-bit B reg. */
545 Z_REGS, /* 16-bit fake Z register */
546 D8_REGS, /* 8-bit A or B reg. */
547 Q_REGS, /* 8-bit (byte (QI)) data (A, B or D) */
548 D_OR_X_REGS, /* D or X register */
549 D_OR_Y_REGS, /* D or Y register */
550 D_OR_SP_REGS, /* D or SP register */
551 X_OR_Y_REGS, /* IX or Y register */
552 A_REGS, /* 16-bit address register (X, Y, Z) */
553 X_OR_SP_REGS, /* X or SP register */
554 Y_OR_SP_REGS, /* Y or SP register */
555 X_OR_Y_OR_D_REGS, /* X, Y or D */
556 A_OR_D_REGS, /* X, Y, Z or D */
557 A_OR_SP_REGS, /* X, Y, Z or SP */
558 H_REGS, /* 16-bit hard register (D, X, Y, Z, SP) */
559 S_REGS, /* 16-bit soft register */
560 D_OR_S_REGS, /* 16-bit soft register or D register */
561 X_OR_S_REGS, /* 16-bit soft register or X register */
562 Y_OR_S_REGS, /* 16-bit soft register or Y register */
563 SP_OR_S_REGS, /* 16-bit soft register or SP register */
564 D_OR_X_OR_S_REGS, /* 16-bit soft register or D or X register */
565 D_OR_Y_OR_S_REGS, /* 16-bit soft register or D or Y register */
566 D_OR_SP_OR_S_REGS, /* 16-bit soft register or D or SP register */
567 A_OR_S_REGS, /* 16-bit soft register or X, Y registers */
568 D_OR_A_OR_S_REGS, /* 16-bit soft register or D, X, Y registers */
569 TMP_REGS, /* 16 bit fake scratch register */
570 D_OR_A_OR_TMP_REGS, /* General scratch register */
571 G_REGS, /* 16-bit general register
572 (H_REGS + soft registers) */
577 /* alias GENERAL_REGS to G_REGS. */
578 #define GENERAL_REGS G_REGS
580 #define N_REG_CLASSES (int) LIM_REG_CLASSES
582 /* Give names of register classes as strings for dump file. */
583 #define REG_CLASS_NAMES \
601 "X_OR_Y_OR_D_REGS", \
610 "D_OR_X_OR_S_REGS", \
611 "D_OR_Y_OR_S_REGS", \
612 "D_OR_SP_OR_S_REGS", \
614 "D_OR_A_OR_S_REGS", \
616 "D_OR_A_OR_TMP_REGS", \
620 /* An initializer containing the contents of the register classes,
621 as integers which are bit masks. The Nth integer specifies the
622 contents of class N. The way the integer MASK is interpreted is
623 that register R is in the class if `MASK & (1 << R)' is 1. */
625 /*--------------------------------------------------------------
640 Di 0xFFFFc000, 0x03FFF
641 SFRAME 0x00000000, 0x04000
642 AP 0x00000000, 0x08000
644 D_OR_X_REGS represents D+X. It is used for 32-bits numbers.
645 A_REGS represents a valid base register for indexing. It represents
646 X,Y and the Z register.
647 S_REGS represents the soft-registers. This includes the hard frame
648 and soft frame registers.
649 --------------------------------------------------------------*/
651 #define REG_CLASS_CONTENTS \
652 /* NO_REGS */ {{ 0x00000000, 0x00000000 }, \
653 /* D_REGS */ { 0x00000002, 0x00000000 }, /* D */ \
654 /* X_REGS */ { 0x00000001, 0x00000000 }, /* X */ \
655 /* Y_REGS */ { 0x00000004, 0x00000000 }, /* Y */ \
656 /* SP_REGS */ { 0x00000008, 0x00000000 }, /* SP */ \
657 /* DA_REGS */ { 0x00000020, 0x00000000 }, /* A */ \
658 /* DB_REGS */ { 0x00000040, 0x00000000 }, /* B */ \
659 /* D8_REGS */ { 0x00000060, 0x00000000 }, /* A B */ \
660 /* Z_REGS */ { 0x00000100, 0x00000000 }, /* Z */ \
661 /* Q_REGS */ { 0x00000062, 0x00000000 }, /* A B D */ \
662 /* D_OR_X_REGS */ { 0x00000003, 0x00000000 }, /* D X */ \
663 /* D_OR_Y_REGS */ { 0x00000006, 0x00000000 }, /* D Y */ \
664 /* D_OR_SP_REGS */ { 0x0000000A, 0x00000000 }, /* D SP */ \
665 /* X_OR_Y_REGS */ { 0x00000005, 0x00000000 }, /* X Y */ \
666 /* A_REGS */ { 0x00000105, 0x00000000 }, /* X Y Z */ \
667 /* X_OR_SP_REGS */ { 0x00000009, 0x00000000 }, /* X SP */ \
668 /* Y_OR_SP_REGS */ { 0x0000000C, 0x00000000 }, /* Y SP */ \
669 /* X_OR_Y_OR_D_REGS */ { 0x00000007, 0x00000000 }, /* D X Y */ \
670 /* A_OR_D_REGS */ { 0x00000107, 0x00000000 }, /* D X Y Z */ \
671 /* A_OR_SP_REGS */ { 0x0000010D, 0x00000000 }, /* X Y SP */ \
672 /* H_REGS */ { 0x0000010F, 0x00000000 }, /* D X Y SP */ \
673 /* S_REGS */ { 0xFFFFDE00, 0x00007FFF }, /* _.D,..,FP,Z* */ \
674 /* D_OR_S_REGS */ { 0xFFFFDE02, 0x00007FFF }, /* D _.D */ \
675 /* X_OR_S_REGS */ { 0xFFFFDE01, 0x00007FFF }, /* X _.D */ \
676 /* Y_OR_S_REGS */ { 0xFFFFDE04, 0x00007FFF }, /* Y _.D */ \
677 /* SP_OR_S_REGS */ { 0xFFFFDE08, 0x00007FFF }, /* SP _.D */ \
678 /* D_OR_X_OR_S_REGS */ { 0xFFFFDE03, 0x00007FFF }, /* D X _.D */ \
679 /* D_OR_Y_OR_S_REGS */ { 0xFFFFDE06, 0x00007FFF }, /* D Y _.D */ \
680 /* D_OR_SP_OR_S_REGS */ { 0xFFFFDE0A, 0x00007FFF }, /* D SP _.D */ \
681 /* A_OR_S_REGS */ { 0xFFFFDF05, 0x00007FFF }, /* X Y _.D */ \
682 /* D_OR_A_OR_S_REGS */ { 0xFFFFDF07, 0x00007FFF }, /* D X Y _.D */ \
683 /* TMP_REGS */ { 0x00002000, 0x00000000 }, /* FAKE */ \
684 /* D_OR_A_OR_TMP_REGS*/ { 0x00002107, 0x00000000 }, /* D X Y Z Fake */ \
685 /* G_REGS */ { 0xFFFFFF1F, 0x00007FFF }, /* ? _.D D X Y */ \
686 /* ALL_REGS*/ { 0xFFFFFFFF, 0x00007FFF }}
689 /* set up a C expression whose value is a register class containing hard
691 #define Q_REGNO_P(REGNO) ((REGNO) == HARD_A_REGNUM \
692 || (REGNO) == HARD_B_REGNUM)
693 #define Q_REG_P(X) (REG_P (X) && Q_REGNO_P (REGNO (X)))
695 #define D_REGNO_P(REGNO) ((REGNO) == HARD_D_REGNUM)
696 #define D_REG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X)))
698 #define DB_REGNO_P(REGNO) ((REGNO) == HARD_B_REGNUM)
699 #define DB_REG_P(X) (REG_P (X) && DB_REGNO_P (REGNO (X)))
700 #define DA_REGNO_P(REGNO) ((REGNO) == HARD_A_REGNUM)
701 #define DA_REG_P(X) (REG_P (X) && DA_REGNO_P (REGNO (X)))
703 #define X_REGNO_P(REGNO) ((REGNO) == HARD_X_REGNUM)
704 #define X_REG_P(X) (REG_P (X) && X_REGNO_P (REGNO (X)))
706 #define Y_REGNO_P(REGNO) ((REGNO) == HARD_Y_REGNUM)
707 #define Y_REG_P(X) (REG_P (X) && Y_REGNO_P (REGNO (X)))
709 #define Z_REGNO_P(REGNO) ((REGNO) == HARD_Z_REGNUM)
710 #define Z_REG_P(X) (REG_P (X) && Z_REGNO_P (REGNO (X)))
712 #define SP_REGNO_P(REGNO) ((REGNO) == HARD_SP_REGNUM)
713 #define SP_REG_P(X) (REG_P (X) && SP_REGNO_P (REGNO (X)))
715 /* Address register. */
716 #define A_REGNO_P(REGNO) ((REGNO) == HARD_X_REGNUM \
717 || (REGNO) == HARD_Y_REGNUM \
718 || (REGNO) == HARD_Z_REGNUM)
719 #define A_REG_P(X) (REG_P (X) && A_REGNO_P (REGNO (X)))
721 /* M68hc11 hard registers. */
722 #define H_REGNO_P(REGNO) (D_REGNO_P (REGNO) || A_REGNO_P (REGNO) \
723 || SP_REGNO_P (REGNO) || Q_REGNO_P (REGNO))
724 #define H_REG_P(X) (REG_P (X) && H_REGNO_P (REGNO (X)))
726 #define FAKE_REGNO_P(REGNO) ((REGNO) == FAKE_CLOBBER_REGNUM)
727 #define FAKE_REG_P(X) (REG_P (X) && FAKE_REGNO_P (REGNO (X)))
729 /* Soft registers (or register emulation for gcc). The temporary register
730 used by insn template must be part of the S_REGS class so that it
731 matches the 'u' constraint. */
732 #define S_REGNO_P(REGNO) ((REGNO) >= SOFT_TMP_REGNUM \
733 && (REGNO) <= SOFT_REG_LAST \
734 && (REGNO) != FAKE_CLOBBER_REGNUM)
735 #define S_REG_P(X) (REG_P (X) && S_REGNO_P (REGNO (X)))
737 #define Z_REGNO_P(REGNO) ((REGNO) == HARD_Z_REGNUM)
738 #define Z_REG_P(X) (REG_P (X) && Z_REGNO_P (REGNO (X)))
740 /* General register. */
741 #define G_REGNO_P(REGNO) (H_REGNO_P (REGNO) || S_REGNO_P (REGNO) \
742 || ((REGNO) == HARD_PC_REGNUM) \
743 || ((REGNO) == HARD_FP_REGNUM) \
744 || ((REGNO) == SOFT_FP_REGNUM) \
745 || ((REGNO) == FAKE_CLOBBER_REGNUM) \
746 || ((REGNO) == SOFT_AP_REGNUM))
748 #define G_REG_P(X) (REG_P (X) && G_REGNO_P (REGNO (X)))
750 #define REGNO_REG_CLASS(REGNO) \
751 (D_REGNO_P (REGNO) ? D_REGS : \
752 (X_REGNO_P (REGNO) ? X_REGS : \
753 (Y_REGNO_P (REGNO) ? Y_REGS : \
754 (SP_REGNO_P (REGNO) ? SP_REGS : \
755 (Z_REGNO_P (REGNO) ? Z_REGS : \
756 (H_REGNO_P (REGNO) ? H_REGS : \
757 (FAKE_REGNO_P (REGNO) ? TMP_REGS : \
758 (S_REGNO_P (REGNO) ? S_REGS : \
759 (DA_REGNO_P (REGNO) ? DA_REGS: \
760 (DB_REGNO_P (REGNO) ? DB_REGS: \
761 (G_REGNO_P (REGNO) ? G_REGS : ALL_REGS)))))))))))
764 /* Get reg_class from a letter in the machine description. */
766 extern enum reg_class m68hc11_tmp_regs_class;
767 #define REG_CLASS_FROM_LETTER(C) \
768 ((C) == 'a' ? DA_REGS : \
769 (C) == 'A' ? A_REGS : \
770 (C) == 'b' ? DB_REGS : \
771 (C) == 'B' ? X_OR_Y_REGS : \
772 (C) == 'd' ? D_REGS : \
773 (C) == 'D' ? D_OR_X_REGS : \
774 (C) == 'q' ? Q_REGS : \
775 (C) == 'h' ? H_REGS : \
776 (C) == 't' ? TMP_REGS : \
777 (C) == 'u' ? S_REGS : \
778 (C) == 'v' ? m68hc11_tmp_regs_class : \
779 (C) == 'w' ? SP_REGS : \
780 (C) == 'x' ? X_REGS : \
781 (C) == 'y' ? Y_REGS : \
782 (C) == 'z' ? Z_REGS : NO_REGS)
784 #define PREFERRED_RELOAD_CLASS(X,CLASS) preferred_reload_class(X,CLASS)
786 #define SMALL_REGISTER_CLASSES 1
788 /* A C expression whose value is nonzero if pseudos that have been
789 assigned to registers of class CLASS would likely be spilled
790 because registers of CLASS are needed for spill registers.
792 The default value of this macro returns 1 if CLASS has exactly one
793 register and zero otherwise. On most machines, this default
794 should be used. Only define this macro to some other expression
795 if pseudo allocated by `local-alloc.c' end up in memory because
796 their hard registers were needed for spill registers. If this
797 macro returns nonzero for those classes, those pseudos will only
798 be allocated by `global.c', which knows how to reallocate the
799 pseudo to another register. If there would not be another
800 register available for reallocation, you should not change the
801 definition of this macro since the only effect of such a
802 definition would be to slow down register allocation. */
804 #define CLASS_LIKELY_SPILLED_P(CLASS) \
805 (((CLASS) == D_REGS) \
806 || ((CLASS) == X_REGS) \
807 || ((CLASS) == Y_REGS) \
808 || ((CLASS) == A_REGS) \
809 || ((CLASS) == SP_REGS) \
810 || ((CLASS) == D_OR_X_REGS) \
811 || ((CLASS) == D_OR_Y_REGS) \
812 || ((CLASS) == X_OR_SP_REGS) \
813 || ((CLASS) == Y_OR_SP_REGS) \
814 || ((CLASS) == D_OR_SP_REGS))
816 /* Return the maximum number of consecutive registers needed to represent
817 mode MODE in a register of class CLASS. */
818 #define CLASS_MAX_NREGS(CLASS, MODE) \
819 (((CLASS) == DA_REGS || (CLASS) == DB_REGS \
820 || (CLASS) == D8_REGS || (CLASS) == Q_REGS) ? GET_MODE_SIZE (MODE) \
821 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
823 /* The letters I, J, K, L and M in a register constraint string
824 can be used to stand for particular ranges of immediate operands.
825 This macro defines what the ranges are.
826 C is the letter, and VALUE is a constant value.
827 Return 1 if VALUE is in the range specified by C.
829 `L' is for range -65536 to 65536
830 `M' is for values whose 16-bit low part is 0
832 'O' is for 16 (for rotate using swap).
833 'P' is for range -8 to 2 (used by addhi_sp)
835 'I', 'J', 'K' are not used. */
837 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
838 ((C) == 'L' ? (VALUE) >= -65536 && (VALUE) <= 65535 : \
839 (C) == 'M' ? ((VALUE) & 0x0ffffL) == 0 : \
840 (C) == 'N' ? ((VALUE) == 1 || (VALUE) == -1): \
841 (C) == 'O' ? (VALUE) == 16 : \
842 (C) == 'P' ? (VALUE) <= 2 && (VALUE) >= -8 : 0)
844 /* Similar, but for floating constants, and defining letters G and H.
845 No floating-point constants are valid on 68HC11. */
846 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0
848 /* 'U' represents certain kind of memory indexed operand for 68HC12.
849 and any memory operand for 68HC11. */
850 #define EXTRA_CONSTRAINT(OP, C) \
851 ((C) == 'U' ? m68hc11_small_indexed_indirect_p (OP, GET_MODE (OP)) : 0)
855 /* Stack layout; function entry, exit and calling. */
857 /* Define this if pushing a word on the stack
858 makes the stack pointer a smaller address. */
859 #define STACK_GROWS_DOWNWARD
861 /* Define this if the nominal address of the stack frame
862 is at the high-address end of the local variables;
863 that is, each additional local variable allocated
864 goes at a more negative offset in the frame.
866 Don't define for 68HC11, the frame pointer is the bottom
867 of local variables. */
868 /* #define FRAME_GROWS_DOWNWARD */
870 /* Define this if successive arguments to a function occupy decreasing
871 addresses in the stack. */
872 /* #define ARGS_GROW_DOWNWARD */
874 /* Offset within stack frame to start allocating local variables at.
875 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
876 first local allocated. Otherwise, it is the offset to the BEGINNING
877 of the first local allocated. */
878 #define STARTING_FRAME_OFFSET 0
880 /* Offset of first parameter from the argument pointer register value. */
882 #define FIRST_PARM_OFFSET(FNDECL) 2
884 /* A C expression whose value is RTL representing the location of the
885 incoming return address at the beginning of any function, before the
886 prologue. This RTL is either a REG, indicating that the return
887 value is saved in REG, or a MEM representing a location in
890 Before the prologue, RA is at 0(sp). */
891 #define INCOMING_RETURN_ADDR_RTX \
892 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
894 /* After the prologue, RA is at 0(AP) in the current frame. */
895 #define RETURN_ADDR_RTX(COUNT, FRAME) \
897 ? gen_rtx_MEM (Pmode, arg_pointer_rtx) \
900 /* Before the prologue, the top of the frame is at 2(sp). */
901 #define INCOMING_FRAME_SP_OFFSET 2
903 /* Define this if functions should assume that stack space has been
904 allocated for arguments even when their values are passed in
907 The value of this macro is the size, in bytes, of the area reserved for
908 arguments passed in registers.
910 This space can either be allocated by the caller or be a part of the
911 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE'
913 /* #define REG_PARM_STACK_SPACE(FNDECL) 2 */
915 /* Define this macro if REG_PARM_STACK_SPACE is defined but stack
916 parameters don't skip the area specified by REG_PARM_STACK_SPACE.
917 Normally, when a parameter is not passed in registers, it is placed on
918 the stack beyond the REG_PARM_STACK_SPACE area. Defining this macro
919 suppresses this behavior and causes the parameter to be passed on the
920 stack in its natural location. */
921 /* #define STACK_PARMS_IN_REG_PARM_AREA */
923 /* Register to use for pushing function arguments. */
924 #define STACK_POINTER_REGNUM HARD_SP_REGNUM
926 /* Base register for access to local variables of the function. */
927 #define FRAME_POINTER_REGNUM SOFT_FP_REGNUM
929 #define HARD_FRAME_POINTER_REGNUM HARD_FP_REGNUM
931 /* Base register for access to arguments of the function. */
932 #define ARG_POINTER_REGNUM SOFT_AP_REGNUM
934 /* Register in which static-chain is passed to a function. */
935 #define STATIC_CHAIN_REGNUM SOFT_Z_REGNUM
938 /* Definitions for register eliminations.
940 This is an array of structures. Each structure initializes one pair
941 of eliminable registers. The "from" register number is given first,
942 followed by "to". Eliminations of the same "from" register are listed
943 in order of preference.
945 We have two registers that are eliminated on the 6811. The psuedo arg
946 pointer and pseudo frame pointer registers can always be eliminated;
947 they are replaced with either the stack or the real frame pointer. */
949 #define ELIMINABLE_REGS \
950 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
951 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
952 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
953 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
955 /* Value should be nonzero if functions must have frame pointers.
956 Zero means the frame pointer need not be set up (and parms may be
957 accessed via the stack pointer) in functions that seem suitable.
958 This is computed in `reload', in reload1.c. */
959 #define FRAME_POINTER_REQUIRED 0
961 /* Given FROM and TO register numbers, say whether this elimination is allowed.
962 Frame pointer elimination is automatically handled.
964 All other eliminations are valid. */
966 #define CAN_ELIMINATE(FROM, TO) \
967 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
968 ? ! frame_pointer_needed \
972 /* Define the offset between two registers, one to be eliminated, and the other
973 its replacement, at the start of a routine. */
975 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
976 { OFFSET = m68hc11_initial_elimination_offset (FROM, TO); }
979 /* Passing Function Arguments on the Stack. */
981 /* When a prototype says `char' or `short', really pass an `int'. */
982 /* #define PROMOTE_PROTOTYPES */
984 /* If we generate an insn to push BYTES bytes, this says how many the
985 stack pointer really advances by. No rounding or alignment needed
987 #define PUSH_ROUNDING(BYTES) (BYTES)
989 /* Value is 1 if returning from a function call automatically pops the
990 arguments described by the number-of-args field in the call. FUNTYPE is
991 the data type of the function (as a tree), or for a library call it is
992 an identifier node for the subroutine name.
994 The standard MC6811 call, with arg count word, includes popping the
995 args as part of the call template. */
996 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
998 /* Nonzero if type TYPE should be returned in memory.
999 Blocks and data types largers than 4 bytes cannot be returned
1000 in the register (D + X = 4). */
1001 #define RETURN_IN_MEMORY(TYPE) \
1002 ((TYPE_MODE (TYPE) == BLKmode) \
1003 ? (int_size_in_bytes (TYPE) > 4) \
1004 : (GET_MODE_SIZE (TYPE_MODE (TYPE)) > 4))
1007 /* Passing Arguments in Registers. */
1009 /* Define a data type for recording info about an argument list
1010 during the scan of that argument list. This data type should
1011 hold all necessary information about the function itself
1012 and about the args processed so far, enough to enable macros
1013 such as FUNCTION_ARG to determine where the next arg should go. */
1015 typedef struct m68hc11_args
1021 /* A C expression that indicates when an argument must be passed by reference.
1022 If nonzero for an argument, a copy of that argument is made in memory and a
1023 pointer to the argument is passed instead of the argument itself.
1024 The pointer is passed in whatever way is appropriate for passing a pointer
1027 64-bit numbers are passed by reference. */
1028 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1029 m68hc11_function_arg_pass_by_reference (& (CUM), (MODE), (TYPE), (NAMED))
1032 /* If defined, a C expression which determines whether, and in which direction,
1033 to pad out an argument with extra space. The value should be of type
1034 `enum direction': either `upward' to pad above the argument,
1035 `downward' to pad below, or `none' to inhibit padding.
1037 Structures are stored left shifted in their argument slot. */
1038 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1039 m68hc11_function_arg_padding ((MODE), (TYPE))
1041 /* A C expression that indicates when it is the called function's
1042 responsibility to make a copy of arguments passed by invisible
1043 reference. Normally, the caller makes a copy and passes the
1044 address of the copy to the routine being called. When
1045 FUNCTION_ARG_CALLEE_COPIES is defined and is nonzero, the caller
1046 does not make a copy. Instead, it passes a pointer to the "live"
1047 value. The called function must not modify this value. If it can
1048 be determined that the value won't be modified, it need not make a
1049 copy; otherwise a copy must be made. */
1050 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
1051 ((NAMED) && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
1053 /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a
1054 function whose data type is FNTYPE. For a library call, FNTYPE is 0. */
1055 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1056 (m68hc11_init_cumulative_args (&CUM, FNTYPE, LIBNAME))
1058 /* Update the data in CUM to advance over an argument of mode MODE and data
1059 type TYPE. (TYPE is null for libcalls where that information may not be
1061 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1062 (m68hc11_function_arg_advance (&CUM, MODE, TYPE, NAMED))
1064 /* Define where to put the arguments to a function.
1065 Value is zero to push the argument on the stack,
1066 or a hard register in which to store the argument.
1068 MODE is the argument's machine mode.
1069 TYPE is the data type of the argument (as a tree).
1070 This is null for libcalls where that information may
1072 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1073 the preceding args and about the function being called.
1074 NAMED is nonzero if this argument is a named parameter
1075 (otherwise it is an extra parameter matching an ellipsis). */
1076 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1077 (m68hc11_function_arg (&CUM, MODE, TYPE, NAMED))
1079 /* Define the profitability of saving registers around calls.
1081 Disable this because the saving instructions generated by
1082 caller-save need a reload and the way it is implemented,
1083 it forbids all spill registers at that point. Enabling
1084 caller saving results in spill failure. */
1085 #define CALLER_SAVE_PROFITABLE(REFS,CALLS) 0
1087 /* Implement `va_arg'. */
1088 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1089 m68hc11_expand_builtin_va_start (stdarg, valist, nextarg)
1091 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1092 m68hc11_va_arg (valist, type)
1094 /* For an arg passed partly in registers and partly in memory,
1095 this is the number of registers used.
1096 For args passed entirely in registers or entirely in memory, zero.
1098 Passing an arg partly in register and memory does not work at all.
1100 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) (0)
1102 /* 1 if N is a possible register number for function argument passing.
1103 D is for 16-bit values, X is for 32-bit (X+D). */
1104 #define FUNCTION_ARG_REGNO_P(N) \
1105 (((N) == HARD_D_REGNUM) || ((N) == HARD_X_REGNUM))
1107 /* All return values are in the D or X+D registers:
1108 - 8 and 16-bit values are returned in D.
1109 BLKmode are passed in D as pointer.
1110 - 32-bit values are returned in X + D.
1111 The high part is passed in X and the low part in D.
1112 For GCC, the register number must be HARD_X_REGNUM. */
1113 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1114 gen_rtx (REG, TYPE_MODE (VALTYPE), \
1115 ((TYPE_MODE (VALTYPE) == BLKmode \
1116 || GET_MODE_SIZE (TYPE_MODE (VALTYPE)) <= 2) \
1117 ? HARD_D_REGNUM : HARD_X_REGNUM))
1119 #define LIBCALL_VALUE(MODE) \
1120 gen_rtx (REG, MODE, \
1121 (((MODE) == BLKmode || GET_MODE_SIZE (MODE) <= 2) \
1122 ? HARD_D_REGNUM : HARD_X_REGNUM))
1124 /* 1 if N is a possible register number for a function value. */
1125 #define FUNCTION_VALUE_REGNO_P(N) \
1126 ((N) == HARD_D_REGNUM || (N) == HARD_X_REGNUM)
1128 /* Register in which address to store a structure value is passed to a
1130 #define STRUCT_VALUE_REGNUM HARD_D_REGNUM
1132 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1133 the stack pointer does not matter. The value is tested only in functions
1134 that have frame pointers. No definition is equivalent to always zero. */
1135 #define EXIT_IGNORE_STACK 0
1138 /* Generating Code for Profiling. */
1140 /* Output assembler code to FILE to increment profiler label # LABELNO
1141 for profiling a function entry. */
1142 #define FUNCTION_PROFILER(FILE, LABELNO) \
1143 asm_fprintf (FILE, "\tldy LP%d\n\tjsr mcount\n", (LABELNO))
1145 /* Output assembler code to FILE to initialize this source file's
1146 basic block profiling info, if that has not already been done. */
1147 #define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL) \
1148 m68hc11_function_block_profiler(FILE, BLOCK_OR_LABEL)
1150 /* Output assembler code to FILE to increment the counter for
1151 the BLOCKNO'th basic block in this source file. */
1152 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1153 m68hc11_block_profiler(FILE, BLOCKNO)
1155 /* Output assembler code to FILE to indicate return from
1156 a function during basic block profiling. */
1157 #define FUNCTION_BLOCK_PROFILER_EXIT(FILE) \
1158 asm_fprintf (FILE, "\tjsr %U__bb_trace_ret\n");
1160 /* Save all registers which may be clobbered by a function call.
1161 MACHINE_STATE_SAVE and MACHINE_STATE_RESTORE are target-code macros,
1162 used in libgcc2.c. They may not refer to TARGET_* macros !!!
1164 We don't need to save the CCR nor the soft registers because
1165 they will be saved by gcc. */
1166 #define MACHINE_STATE_SAVE(id) \
1174 #define MACHINE_STATE_RESTORE(id) \
1182 /* Length in units of the trampoline for entering a nested function. */
1183 #define TRAMPOLINE_SIZE (TARGET_M6811 ? 11 : 9)
1185 /* A C statement to initialize the variable parts of a trampoline.
1186 ADDR is an RTX for the address of the trampoline; FNADDR is an
1187 RTX for the address of the nested function; STATIC_CHAIN is an
1188 RTX for the static chain value that should be passed to the
1189 function when it is called. */
1190 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1191 m68hc11_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1194 /* Define this macro if references to a symbol must be treated
1195 differently depending on something about the variable or function
1196 named by the symbol (such as what section it is in).
1198 For the 68HC11, we want to recognize trap handlers so that we
1199 handle calls to traps in a special manner (by issuing the trap).
1200 This information is stored in SYMBOL_REF_FLAG. */
1202 #define ENCODE_SECTION_INFO(DECL) m68hc11_encode_section_info (DECL)
1204 /* Override what GCC does for section info to let us recognize traps. */
1206 #define REDO_SECTION_INFO_P(DECL) 1
1208 /* `INIT_TARGET_OPTABS'
1209 Define this macro as a C statement that declares additional library
1210 routines renames existing ones. `init_optabs' calls this macro
1211 after initializing all the normal library routines.
1213 Overrides the memcpy */
1215 #define INIT_TARGET_OPTABS \
1218 memcpy_libfunc = gen_rtx_SYMBOL_REF (Pmode, "__memcpy"); \
1219 memcmp_libfunc = gen_rtx_SYMBOL_REF (Pmode, "__memcmp"); \
1220 memset_libfunc = gen_rtx_SYMBOL_REF (Pmode, "__memset"); \
1225 /* Addressing modes, and classification of registers for them. */
1227 /* The 68HC12 has all the post/pre increment/decrement modes. */
1228 #define HAVE_POST_INCREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC)
1229 #define HAVE_PRE_INCREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC)
1230 #define HAVE_POST_DECREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC)
1231 #define HAVE_PRE_DECREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC)
1233 /* The class value for base registers. This depends on the target:
1234 A_REGS for 68HC11 and A_OR_SP_REGS for 68HC12. The class value
1235 is stored at init time. */
1236 extern enum reg_class m68hc11_base_reg_class;
1237 #define BASE_REG_CLASS m68hc11_base_reg_class
1239 /* The class value for index registers. This is NO_REGS for 68HC11. */
1241 extern enum reg_class m68hc11_index_reg_class;
1242 #define INDEX_REG_CLASS m68hc11_index_reg_class
1244 /* These assume that REGNO is a hard or pseudo reg number. They give nonzero
1245 only if REGNO is a hard reg of the suitable class or a pseudo reg currently
1246 allocated to a suitable hard reg. Since they use reg_renumber, they are
1247 safe only once reg_renumber has been allocated, which happens in
1251 /* Internal macro, return 1 if REGNO is a valid base register. */
1252 #define REG_VALID_P(REGNO) (1) /* ? */
1254 extern unsigned char m68hc11_reg_valid_for_base[FIRST_PSEUDO_REGISTER];
1255 #define REG_VALID_FOR_BASE_P(REGNO) \
1256 (REG_VALID_P (REGNO) && (REGNO) < FIRST_PSEUDO_REGISTER \
1257 && m68hc11_reg_valid_for_base[REGNO])
1259 /* Internal macro, return 1 if REGNO is a valid index register. */
1260 extern unsigned char m68hc11_reg_valid_for_index[FIRST_PSEUDO_REGISTER];
1261 #define REG_VALID_FOR_INDEX_P(REGNO) \
1262 (REG_VALID_P (REGNO) >= 0 && (REGNO) < FIRST_PSEUDO_REGISTER \
1263 && m68hc11_reg_valid_for_index[REGNO])
1265 /* Internal macro, the nonstrict definition for REGNO_OK_FOR_BASE_P. */
1266 #define REGNO_OK_FOR_BASE_NONSTRICT_P(REGNO) \
1267 ((REGNO) >= FIRST_PSEUDO_REGISTER \
1268 || REG_VALID_FOR_BASE_P (REGNO) \
1269 || (REGNO) == FRAME_POINTER_REGNUM \
1270 || (REGNO) == HARD_FRAME_POINTER_REGNUM \
1271 || (REGNO) == ARG_POINTER_REGNUM \
1272 || (reg_renumber && REG_VALID_FOR_BASE_P (reg_renumber[REGNO])))
1274 /* Internal macro, the nonstrict definition for REGNO_OK_FOR_INDEX_P. */
1275 #define REGNO_OK_FOR_INDEX_NONSTRICT_P(REGNO) \
1277 && ((REGNO) >= FIRST_PSEUDO_REGISTER \
1278 || REG_VALID_FOR_INDEX_P (REGNO) \
1279 || (reg_renumber && REG_VALID_FOR_INDEX_P (reg_renumber[REGNO]))))
1281 /* Internal macro, the strict definition for REGNO_OK_FOR_BASE_P. */
1282 #define REGNO_OK_FOR_BASE_STRICT_P(REGNO) \
1283 ((REGNO) < FIRST_PSEUDO_REGISTER ? REG_VALID_FOR_BASE_P (REGNO) \
1284 : (reg_renumber && REG_VALID_FOR_BASE_P (reg_renumber[REGNO])))
1286 /* Internal macro, the strict definition for REGNO_OK_FOR_INDEX_P. */
1287 #define REGNO_OK_FOR_INDEX_STRICT_P(REGNO) \
1289 && ((REGNO) < FIRST_PSEUDO_REGISTER ? REG_VALID_FOR_INDEX_P (REGNO) \
1290 : (reg_renumber && REG_VALID_FOR_INDEX_P (reg_renumber[REGNO]))))
1292 #define REGNO_OK_FOR_BASE_P2(REGNO,STRICT) \
1293 ((STRICT) ? (REGNO_OK_FOR_BASE_STRICT_P (REGNO)) \
1294 : (REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO)))
1296 #define REGNO_OK_FOR_INDEX_P2(REGNO,STRICT) \
1297 ((STRICT) ? (REGNO_OK_FOR_INDEX_STRICT_P (REGNO)) \
1298 : (REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO)))
1300 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_BASE_STRICT_P (REGNO)
1301 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_INDEX_STRICT_P (REGNO)
1303 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_STRICT_P (REGNO (X))
1304 #define REG_OK_FOR_BASE_NONSTRICT_P(X) REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (X))
1305 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_STRICT_P (REGNO (X))
1306 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (X))
1308 /* see PUSH_POP_ADDRESS_P() below for an explanation of this. */
1309 #define IS_STACK_PUSH(operand) \
1310 ((GET_CODE (operand) == MEM) \
1311 && (GET_CODE (XEXP (operand, 0)) == PRE_DEC) \
1312 && (SP_REG_P (XEXP (XEXP (operand, 0), 0))))
1314 #define IS_STACK_POP(operand) \
1315 ((GET_CODE (operand) == MEM) \
1316 && (GET_CODE (XEXP (operand, 0)) == POST_INC) \
1317 && (SP_REG_P (XEXP (XEXP (operand, 0), 0))))
1319 /* 1 if X is an rtx for a constant that is a valid address. */
1320 #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X))
1322 /* Maximum number of registers that can appear in a valid memory address */
1323 #define MAX_REGS_PER_ADDRESS 2
1325 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a
1326 valid memory address for an instruction. The MODE argument is the
1327 machine mode for the MEM expression that wants to use this address. */
1329 /*--------------------------------------------------------------
1330 Valid addresses are either direct or indirect (MEM) versions
1331 of the following forms:
1335 --------------------------------------------------------------*/
1337 /* The range of index that is allowed by indirect addressing. */
1339 #define VALID_MIN_OFFSET m68hc11_min_offset
1340 #define VALID_MAX_OFFSET m68hc11_max_offset
1342 /* The offset values which are allowed by the n,x and n,y addressing modes.
1343 Take into account the size of the mode because we may have to add
1344 a mode offset to access the lowest part of the data.
1345 (For example, for an SImode, the last valid offset is 252.) */
1346 #define VALID_CONSTANT_OFFSET_P(X,MODE) \
1347 ((GET_CODE (X) == CONST_INT) && \
1348 ((INTVAL (X) >= VALID_MIN_OFFSET) \
1349 && ((INTVAL (X) <= VALID_MAX_OFFSET \
1350 - (HOST_WIDE_INT) (GET_MODE_SIZE (MODE) + 1)))))
1352 /* This is included to allow stack push/pop operations. Special hacks in the
1353 md and m6811.c files exist to support this. */
1354 #define PUSH_POP_ADDRESS_P(X) \
1355 (((GET_CODE (X) == PRE_DEC) || (GET_CODE (X) == POST_INC)) \
1356 && SP_REG_P (XEXP (X, 0)))
1358 /* Go to ADDR if X is a valid address. */
1359 #ifndef REG_OK_STRICT
1360 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1362 if (m68hc11_go_if_legitimate_address ((X), (MODE), 0)) goto ADDR; \
1365 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1367 if (m68hc11_go_if_legitimate_address ((X), (MODE), 1)) goto ADDR; \
1371 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check its
1372 validity for a certain class. We have two alternate definitions for each
1373 of them. The usual definition accepts all pseudo regs; the other rejects
1374 them unless they have been allocated suitable hard regs. The symbol
1375 REG_OK_STRICT causes the latter definition to be used.
1377 Most source files want to accept pseudo regs in the hope that they will
1378 get allocated to the class that the insn wants them to be in. Source files
1379 for reload pass need to be strict. After reload, it makes no difference,
1380 since pseudo regs have been eliminated by then. */
1382 #ifndef REG_OK_STRICT
1383 /* Nonzero if X is a hard reg that can be used as a base reg. */
1384 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X)
1386 /* Nonzero if X is a hard reg that can be used as an index. */
1387 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X)
1389 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X)
1390 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X)
1394 /* Try machine-dependent ways of modifying an illegitimate address
1395 to be legitimate. If we find one, return the new, valid address.
1396 This macro is used in only one place: `memory_address' in explow.c.
1398 OLDX is the address as it was before break_out_memory_refs was called.
1399 In some cases it is useful to look at this to decide what needs to be done.
1401 MODE and WIN are passed so that this macro can use
1402 GO_IF_LEGITIMATE_ADDRESS.
1404 It is always safe for this macro to do nothing.
1405 It exists to recognize opportunities to optimize the output. */
1407 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1408 { rtx operand = (X); \
1409 if (m68hc11_legitimize_address (&operand, (OLDX), (MODE))) \
1412 GO_IF_LEGITIMATE_ADDRESS (MODE,X,WIN); \
1416 /* Go to LABEL if ADDR (a legitimate address expression)
1417 has an effect that depends on the machine mode it is used for. */
1418 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1420 if (GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
1421 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
1425 /* Nonzero if the constant value X is a legitimate general operand.
1426 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1428 #define LEGITIMATE_CONSTANT_P(X) 1
1431 /* Tell final.c how to eliminate redundant test instructions. */
1433 #define NOTICE_UPDATE_CC(EXP, INSN) \
1434 m68hc11_notice_update_cc ((EXP), (INSN))
1436 /* Compute the cost of computing a constant rtl expression RTX whose rtx-code
1437 is CODE. The body of this macro is a portion of a switch statement. If
1438 the code is computed here, return it with a return statement. Otherwise,
1439 break from the switch.
1441 Constants are cheap. Moving them in registers must be avoided
1442 because most instructions do not handle two register operands. */
1443 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1445 /* Logical and arithmetic operations with a constant */ \
1446 /* operand are better because they are not supported */ \
1447 /* with two registers. */ \
1448 /* 'clr' is slow */ \
1449 if ((OUTER_CODE) == SET && (RTX) == const0_rtx) \
1450 /* After reload, the reload_cse pass checks the cost */ \
1451 /* to change a SET into a PLUS. Make const0 cheap. */ \
1452 return 1 - reload_completed; \
1458 if ((OUTER_CODE) == SET) \
1459 return 1 - reload_completed; \
1461 case CONST_DOUBLE: \
1464 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1484 case IF_THEN_ELSE: \
1485 return m68hc11_rtx_costs (X, CODE, OUTER_CODE);
1487 /* An expression giving the cost of an addressing mode that contains
1488 ADDRESS. If not defined, the cost is computed from the ADDRESS
1489 expression and the `CONST_COSTS' values. */
1491 #define ADDRESS_COST(RTX) m68hc11_address_cost (RTX)
1493 /* Move costs between classes of registers */
1494 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1495 (m68hc11_register_move_cost (CLASS1, CLASS2))
1497 /* Move cost between register and memory.
1498 - Move to a 16-bit register is reasonable,
1499 - Move to a soft register can be expensive. */
1500 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
1501 m68hc11_memory_move_cost ((MODE),(CLASS),(IN))
1503 /* A C expression for the cost of a branch instruction. A value of 1
1504 is the default; other values are interpreted relative to that.
1506 Pretend branches are cheap because GCC generates sub-optimal code
1507 for the default value. */
1508 #define BRANCH_COST 0
1510 /* Nonzero if access to memory by bytes is slow and undesirable. */
1511 #define SLOW_BYTE_ACCESS 0
1513 /* It is as good to call a constant function address as to call an address
1514 kept in a register. */
1515 #define NO_FUNCTION_CSE
1517 /* Try a machine-dependent way of reloading an illegitimate address
1518 operand. If we find one, push the reload and jump to WIN. This
1519 macro is used in only one place: `find_reloads_address' in reload.c.
1521 For M68HC11, we handle large displacements of a base register
1522 by splitting the addend accors an addhi3 insn.
1524 For M68HC12, the 64K offset range is available.
1527 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1529 /* We must recognize output that we have already generated ourselves. */ \
1530 if (GET_CODE (X) == PLUS \
1531 && GET_CODE (XEXP (X, 0)) == PLUS \
1532 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1533 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1534 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1536 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1537 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1541 if (GET_CODE (X) == PLUS \
1542 && GET_CODE (XEXP (X, 0)) == REG \
1543 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1544 && !VALID_CONSTANT_OFFSET_P (XEXP (X, 1), MODE)) \
1546 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1547 HOST_WIDE_INT low, high; \
1548 high = val & (~0x0FF); \
1549 low = val & 0x00FF; \
1550 if (low >= 256-15) { high += 16; low -= 16; } \
1551 /* Reload the high part into a base reg; leave the low part \
1552 in the mem directly. */ \
1554 X = gen_rtx_PLUS (Pmode, \
1555 gen_rtx_PLUS (Pmode, XEXP (X, 0), \
1559 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1560 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1567 /* Defining the Output Assembler Language. */
1569 /* A default list of other sections which we might be "in" at any given
1570 time. For targets that use additional sections (e.g. .tdesc) you
1571 should override this definition in the target-specific file which
1572 includes this file. */
1574 /* Output before read-only data. */
1575 #define TEXT_SECTION_ASM_OP ("\t.sect\t.text")
1577 /* Output before writable data. */
1578 #define DATA_SECTION_ASM_OP ("\t.sect\t.data")
1580 /* Output before uninitialized data. */
1581 #define BSS_SECTION_ASM_OP ("\t.sect\t.bss")
1583 /* This is how to begin an assembly language file. Most svr4 assemblers want
1584 at least a .file directive to come first, and some want to see a .version
1585 directive come right after that. Here we just establish a default
1586 which generates only the .file directive. If you need a .version
1587 directive for any specific target, you should override this definition
1588 in the target-specific file which includes this one. */
1590 #undef ASM_FILE_START
1591 #define ASM_FILE_START(FILE) \
1592 m68hc11_asm_file_start ((FILE), main_input_filename)
1594 /* Comment character */
1595 #define ASM_COMMENT_START ";"
1597 /* Output to assembler file text saying following lines
1598 may contain character constants, extra white space, comments, etc. */
1599 #define ASM_APP_ON "; Begin inline assembler code\n#APP\n"
1601 /* Output to assembler file text saying following lines
1602 no longer contain unusual constructs. */
1603 #define ASM_APP_OFF "; End of inline assembler code\n#NO_APP\n"
1605 /* Output #ident as a .ident. */
1607 /* This is how to output a `long double' extended real constant. */
1609 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
1610 ASM_OUTPUT_DOUBLE(FILE,VALUE)
1612 /* This is how to output an assembler line defining a `double' constant. */
1614 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1616 REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \
1617 fprintf (FILE, "\t%s\t0x%lx,0x%lx\n", ASM_LONG, l[0], l[1]); \
1620 /* This is how to output an assembler line defining a `float' constant. */
1622 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1624 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1625 fprintf ((FILE), "\t%s\t0x%lx\n", ASM_LONG, l); \
1628 /* This is how to output an assembler line defining a `long' constant. */
1629 #define ASM_OUTPUT_INT(FILE,VALUE) \
1630 ( fprintf (FILE, "\t%s\t", ASM_LONG), \
1631 output_addr_const (FILE, (VALUE)), \
1632 fprintf (FILE, "\n"))
1634 /* Likewise for `char' and `short' constants. */
1635 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1636 ( fprintf (FILE, "\t%s\t", ASM_SHORT), \
1637 output_addr_const (FILE, (VALUE)), \
1638 fprintf (FILE, "\n"))
1640 /* This is how to output an assembler line for a numeric constant byte. */
1641 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1642 ( fprintf (FILE, "%s", ASM_BYTE_OP), \
1643 output_addr_const (FILE, (VALUE)), \
1646 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1647 fprintf ((FILE), "%s0x%x\n", ASM_BYTE_OP, (VALUE))
1649 /* This is how to output the definition of a user-level label named NAME,
1650 such as the label on a static function or variable NAME. */
1652 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1653 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1656 /* This is how to output a command to make the user-level label named NAME
1657 defined for reference from other files. */
1659 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1660 do { fprintf (FILE, "%s", GLOBAL_ASM_OP); \
1661 assemble_name (FILE, NAME); \
1662 fputs ("\n", FILE);} while (0)
1664 /* output external reference */
1665 #define ASM_OUTPUT_EXTERNAL(FILE,DECL,NAME) \
1666 {fputs ("\t; extern\t", FILE); \
1667 assemble_name (FILE, NAME); \
1668 fputs ("\n", FILE);}
1672 /* Store in OUTPUT a string (made with alloca) containing
1673 an assembler-name for a local static variable named NAME.
1674 LABELNO is an integer which is different for each call. */
1676 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1677 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1678 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1680 /* How to refer to registers in assembler output. This sequence is indexed
1681 by compiler's hard-register-number (see above). */
1682 #define REGISTER_NAMES \
1683 { "x", "d", "y", "sp", "pc", "a", "b", "ccr", "z", \
1684 "*_.frame", "*_.tmp", "*_.z", "*_.xy", "*fake clobber", \
1685 SOFT_REG_NAMES, "*sframe", "*ap"}
1688 /* Output a float value (represented as a C double) as an immediate operand.
1689 This macro is a 68k-specific macro. */
1691 #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
1694 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1695 asm_fprintf ((FILE), "%I0x%lx", l); \
1698 /* Output a double value (represented as a C double) as an immediate operand.
1699 This macro is a 68k-specific macro. */
1700 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
1701 do { char dstr[30]; \
1702 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
1703 asm_fprintf (FILE, "%I0r%s", dstr); \
1706 /* Note, long double immediate operands are not actually
1707 generated by m68k.md. */
1708 #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \
1709 do { char dstr[30]; \
1710 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
1711 asm_fprintf (FILE, "%I0r%s", dstr); \
1714 /* Print an instruction operand X on file FILE. CODE is the code from the
1715 %-spec for printing this operand. If `%z3' was used to print operand
1716 3, then CODE is 'z'. */
1718 #define PRINT_OPERAND(FILE, X, CODE) \
1719 print_operand (FILE, X, CODE)
1721 /* Print a memory operand whose address is X, on file FILE. */
1722 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1723 print_operand_address (FILE, ADDR)
1725 /* This is how to output an insn to push/pop a register on the stack.
1726 It need not be very fast code.
1728 Don't define because we don't know how to handle that with
1729 the STATIC_CHAIN_REGNUM (soft register). Saving the static
1730 chain must be made inside FUNCTION_PROFILER. */
1732 #undef ASM_OUTPUT_REG_PUSH
1733 #undef ASM_OUTPUT_REG_POP
1735 /* This is how to output an element of a case-vector that is relative. */
1737 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1738 asm_fprintf (FILE, "\t%s\tL%d-L%d\n", ASM_SHORT, VALUE, REL)
1740 /* This is how to output an element of a case-vector that is absolute. */
1741 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1742 asm_fprintf (FILE, "\t%s\t.L%d\n", ASM_SHORT, VALUE)
1744 /* This is how to output an assembler line that says to advance the
1745 location counter to a multiple of 2**LOG bytes. */
1746 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1749 asm_fprintf ((FILE), "%s\n", ALIGN_ASM_OP); \
1753 /* Assembler Commands for Exception Regions. */
1755 /* Default values provided by GCC should be ok. Assumming that DWARF-2
1756 frame unwind info is ok for this platform. */
1758 /* How to renumber registers for dbx and gdb. */
1759 #define DBX_REGISTER_NUMBER(REGNO) \
1762 #undef PREFERRED_DEBUGGING_TYPE
1763 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1765 /* The prefix for local labels. You should be able to define this as
1766 an empty string, or any arbitrary string (such as ".", ".L%", etc)
1767 without having to make any other changes to account for the specific
1768 definition. Note it is a string literal, not interpreted by printf
1770 #define LOCAL_LABEL_PREFIX "."
1772 /* The prefix for immediate operands. */
1773 #define IMMEDIATE_PREFIX "#"
1774 #define GLOBAL_ASM_OP "\t.globl\t"
1775 #define ASM_LONG ".long"
1776 #define ASM_SHORT ".word"
1779 /* Miscellaneous Parameters. */
1781 /* Define the codes that are matched by predicates in m68hc11.c. */
1782 #define PREDICATE_CODES \
1783 {"stack_register_operand", {SUBREG, REG}}, \
1784 {"d_register_operand", {SUBREG, REG}}, \
1785 {"hard_addr_reg_operand", {SUBREG, REG}}, \
1786 {"hard_reg_operand", {SUBREG, REG}}, \
1787 {"m68hc11_logical_operator", {AND, IOR, XOR}}, \
1788 {"m68hc11_arith_operator", {AND, IOR, XOR, PLUS, MINUS, \
1789 ASHIFT, ASHIFTRT, LSHIFTRT, \
1790 ROTATE, ROTATERT }}, \
1791 {"m68hc11_non_shift_operator", {AND, IOR, XOR, PLUS, MINUS}}, \
1792 {"m68hc11_unary_operator", {NEG, NOT, SIGN_EXTEND, ZERO_EXTEND}}, \
1793 {"non_push_operand", {SUBREG, REG, MEM}}, \
1794 {"reg_or_some_mem_operand", {SUBREG, REG, MEM}}, \
1795 {"tst_operand", {SUBREG, REG, MEM}}, \
1796 {"cmp_operand", {SUBREG, REG, MEM, SYMBOL_REF, LABEL_REF, \
1797 CONST_INT, CONST_DOUBLE}},
1799 /* Specify the machine mode that this machine uses
1800 for the index in the tablejump instruction. */
1801 #define CASE_VECTOR_MODE Pmode
1803 /* Specify the tree operation to be used to convert reals to integers. */
1804 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1806 /* This flag, if defined, says the same insns that convert to a signed fixnum
1807 also convert validly to an unsigned one. */
1808 #define FIXUNS_TRUNC_LIKE_FIX_TRUNC
1810 /* This is the kind of divide that is easiest to do in the general case. */
1811 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1813 /* Max number of bytes we can move from memory to memory in one
1814 reasonably fast instruction. */
1817 /* MOVE_RATIO is the number of move instructions that is better than a
1818 block move. Make this small on 6811, since the code size grows very
1819 large with each move. */
1820 #define MOVE_RATIO 3
1822 /* Define if shifts truncate the shift count which implies one can omit
1823 a sign-extension or zero-extension of a shift count. */
1824 #define SHIFT_COUNT_TRUNCATED 1
1826 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1827 is done just by pretending it is already truncated. */
1828 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1830 /* Specify the machine mode that pointers have. After generation of rtl, the
1831 compiler makes no further distinction between pointers and any other
1832 objects of this machine mode. */
1833 #define Pmode HImode
1835 /* A function address in a call instruction is a byte address (for indexing
1836 purposes) so give the MEM rtx a byte's mode. */
1837 #define FUNCTION_MODE QImode
1839 /* define SCCS_DIRECTIVE if SCCS directives should be ignored */
1840 #define SCCS_DIRECTIVE 1
1842 /* Allow $ in identifiers */
1843 #define DOLLARS_IN_IDENTIFIERS 1
1845 /* Machine-dependent reorg pass.
1846 Specific optimizations are defined here:
1847 - this pass changes the Z register into either X or Y
1848 (it preserves X/Y previous values in a memory slot in page0).
1850 When this pass is finished, the global variable
1851 'z_replacement_completed' is set to 2. */
1852 #define MACHINE_DEPENDENT_REORG(X) m68hc11_reorg (X)
1854 extern int debug_m6811;
1855 extern int z_replacement_completed;
1856 extern int current_function_interrupt;
1857 extern int current_function_trap;
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