1 ;; Machine description of the Renesas M32R cpu for GNU C compiler
2 ;; Copyright (C) 1996, 1997, 1998, 1999, 2001, 2003, 2004, 2005,
3 ; 2007, 2008 Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 ;; UNSPEC_VOLATILE usage
26 (UNSPECV_FLUSH_ICACHE 1)])
30 [(UNSPEC_LOAD_SDA_BASE 2)
32 (UNSPEC_PIC_LOAD_ADDR 4)
37 ;; Insn type. Used to default other attribute values.
39 "int2,int4,load2,load4,load8,store2,store4,store8,shift2,shift4,mul2,div4,uncond_branch,branch,call,multi,misc"
40 (const_string "misc"))
43 (define_attr "length" ""
44 (cond [(eq_attr "type" "int2,load2,store2,shift2,mul2")
47 (eq_attr "type" "int4,load4,store4,shift4,div4")
50 (eq_attr "type" "multi")
53 (eq_attr "type" "uncond_branch,branch,call")
58 ;; The length here is the length of a single asm. Unfortunately it might be
59 ;; 2 or 4 so we must allow for 4. That's ok though.
60 (define_asm_attributes
61 [(set_attr "length" "4")
62 (set_attr "type" "multi")])
64 ;; Whether an instruction is short (16-bit) or long (32-bit).
65 (define_attr "insn_size" "short,long"
66 (if_then_else (eq_attr "type" "int2,load2,store2,shift2,mul2")
67 (const_string "short")
68 (const_string "long")))
70 ;; The target CPU we're compiling for.
71 (define_attr "cpu" "m32r,m32r2,m32rx"
72 (cond [(ne (symbol_ref "TARGET_M32RX") (const_int 0))
73 (const_string "m32rx")
74 (ne (symbol_ref "TARGET_M32R2") (const_int 0))
75 (const_string "m32r2")]
76 (const_string "m32r")))
78 ;; Defines the pipeline where an instruction can be executed on.
79 ;; For the M32R, a short instruction can execute one of the two pipes.
80 ;; For the M32Rx, the restrictions are modelled in the second
81 ;; condition of this attribute definition.
82 (define_attr "m32r_pipeline" "either,s,o,long"
83 (cond [(and (eq_attr "cpu" "m32r")
84 (eq_attr "insn_size" "short"))
85 (const_string "either")
86 (eq_attr "insn_size" "!short")
87 (const_string "long")]
88 (cond [(eq_attr "type" "int2")
89 (const_string "either")
90 (eq_attr "type" "load2,store2,shift2,uncond_branch,branch,call")
92 (eq_attr "type" "mul2")
94 (const_string "long"))))
96 ;; ::::::::::::::::::::
98 ;; :: Pipeline description
100 ;; ::::::::::::::::::::
102 ;; This model is based on Chapter 2, Appendix 3 and Appendix 4 of the
103 ;; "M32R-FPU Software Manual", Revision 1.01, plus additional information
104 ;; obtained by our best friend and mine, Google.
106 ;; The pipeline is modelled as a fetch unit, and a core with a memory unit,
107 ;; two execution units, where "fetch" models IF and D, "memory" for MEM1
108 ;; and MEM2, and "EXEC" for E, E1, E2, EM, and EA. Writeback and
109 ;; bypasses are not modelled.
110 (define_automaton "m32r")
112 ;; We pretend there are two short (16 bits) instruction fetchers. The
113 ;; "s" short fetcher cannot be reserved until the "o" short fetcher is
114 ;; reserved. Some instructions reserve both the left and right fetchers.
115 ;; These fetch units are a hack to get GCC to better pack the instructions
116 ;; for the M32Rx processor, which has two execution pipes.
118 ;; In reality there is only one decoder, which can decode either two 16-bit
119 ;; instructions, or a single 32-bit instruction.
121 ;; Note, "fetch" models both the IF and the D pipeline stages.
123 ;; The m32rx core has two execution pipes. We name them o_E and s_E.
124 ;; In addition, there's a memory unit.
126 (define_cpu_unit "o_IF,s_IF,o_E,s_E,memory" "m32r")
128 ;; Prevent the s pipe from being reserved before the o pipe.
129 (absence_set "s_IF" "o_IF")
130 (absence_set "s_E" "o_E")
132 ;; On the M32Rx, long instructions execute on both pipes, so reserve
133 ;; both fetch slots and both pipes.
134 (define_reservation "long_IF" "o_IF+s_IF")
135 (define_reservation "long_E" "o_E+s_E")
137 ;; ::::::::::::::::::::
139 ;; Simple instructions do 4 stages: IF D E WB. WB is not modelled.
140 ;; Hence, ready latency is 1.
141 (define_insn_reservation "short_left" 1
142 (and (eq_attr "m32r_pipeline" "o")
143 (and (eq_attr "insn_size" "short")
144 (eq_attr "type" "!load2")))
147 (define_insn_reservation "short_right" 1
148 (and (eq_attr "m32r_pipeline" "s")
149 (and (eq_attr "insn_size" "short")
150 (eq_attr "type" "!load2")))
153 (define_insn_reservation "short_either" 1
154 (and (eq_attr "m32r_pipeline" "either")
155 (and (eq_attr "insn_size" "short")
156 (eq_attr "type" "!load2")))
159 (define_insn_reservation "long_m32r" 1
160 (and (eq_attr "cpu" "m32r")
161 (and (eq_attr "insn_size" "long")
162 (eq_attr "type" "!load4,load8")))
165 (define_insn_reservation "long_m32rx" 2
166 (and (eq_attr "m32r_pipeline" "long")
167 (and (eq_attr "insn_size" "long")
168 (eq_attr "type" "!load4,load8")))
171 ;; Load/store instructions do 6 stages: IF D E MEM1 MEM2 WB.
172 ;; MEM1 may require more than one cycle depending on locality. We
173 ;; optimistically assume all memory is nearby, i.e. MEM1 takes only
174 ;; one cycle. Hence, ready latency is 3.
176 ;; The M32Rx can do short load/store only on the left pipe.
177 (define_insn_reservation "short_load_left" 3
178 (and (eq_attr "m32r_pipeline" "o")
179 (and (eq_attr "insn_size" "short")
180 (eq_attr "type" "load2")))
183 (define_insn_reservation "short_load" 3
184 (and (eq_attr "m32r_pipeline" "either")
185 (and (eq_attr "insn_size" "short")
186 (eq_attr "type" "load2")))
187 "s_IF|o_IF,s_E|o_E,memory*2")
189 (define_insn_reservation "long_load" 3
190 (and (eq_attr "cpu" "m32r")
191 (and (eq_attr "insn_size" "long")
192 (eq_attr "type" "load4,load8")))
193 "long_IF,long_E,memory*2")
195 (define_insn_reservation "long_load_m32rx" 3
196 (and (eq_attr "m32r_pipeline" "long")
197 (eq_attr "type" "load4,load8"))
198 "long_IF,long_E,memory*2")
201 (include "predicates.md")
202 (include "constraints.md")
204 ;; Expand prologue as RTL
205 (define_expand "prologue"
210 m32r_expand_prologue ();
214 ;; Expand epilogue as RTL
215 (define_expand "epilogue"
220 m32r_expand_epilogue ();
221 emit_jump_insn (gen_return_normal ());
225 ;; Move instructions.
227 ;; For QI and HI moves, the register must contain the full properly
228 ;; sign-extended value. nonzero_bits assumes this [otherwise
229 ;; SHORT_IMMEDIATES_SIGN_EXTEND must be used, but the comment for it
230 ;; says it's a kludge and the .md files should be fixed instead].
232 (define_expand "movqi"
233 [(set (match_operand:QI 0 "general_operand" "")
234 (match_operand:QI 1 "general_operand" ""))]
238 /* Fixup PIC cases. */
241 if (symbolic_operand (operands[1], QImode))
243 if (reload_in_progress || reload_completed)
244 operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);
246 operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);
250 /* Everything except mem = const or mem = mem can be done easily.
251 Objects in the small data area are handled too. */
253 if (MEM_P (operands[0]))
254 operands[1] = force_reg (QImode, operands[1]);
257 (define_insn "*movqi_insn"
258 [(set (match_operand:QI 0 "move_dest_operand" "=r,r,r,r,r,T,m")
259 (match_operand:QI 1 "move_src_operand" "r,I,JQR,T,m,r,r"))]
260 "register_operand (operands[0], QImode) || register_operand (operands[1], QImode)"
269 [(set_attr "type" "int2,int2,int4,load2,load4,store2,store4")
270 (set_attr "length" "2,2,4,2,4,2,4")])
272 (define_expand "movhi"
273 [(set (match_operand:HI 0 "general_operand" "")
274 (match_operand:HI 1 "general_operand" ""))]
278 /* Fixup PIC cases. */
281 if (symbolic_operand (operands[1], HImode))
283 if (reload_in_progress || reload_completed)
284 operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);
286 operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);
290 /* Everything except mem = const or mem = mem can be done easily. */
292 if (MEM_P (operands[0]))
293 operands[1] = force_reg (HImode, operands[1]);
296 (define_insn "*movhi_insn"
297 [(set (match_operand:HI 0 "move_dest_operand" "=r,r,r,r,r,r,T,m")
298 (match_operand:HI 1 "move_src_operand" "r,I,JQR,K,T,m,r,r"))]
299 "register_operand (operands[0], HImode) || register_operand (operands[1], HImode)"
309 [(set_attr "type" "int2,int2,int4,int4,load2,load4,store2,store4")
310 (set_attr "length" "2,2,4,4,2,4,2,4")])
312 (define_expand "movsi_push"
313 [(set (mem:SI (pre_dec:SI (match_operand:SI 0 "register_operand" "")))
314 (match_operand:SI 1 "register_operand" ""))]
318 (define_expand "movsi_pop"
319 [(set (match_operand:SI 0 "register_operand" "")
320 (mem:SI (post_inc:SI (match_operand:SI 1 "register_operand" ""))))]
324 (define_expand "movsi"
325 [(set (match_operand:SI 0 "general_operand" "")
326 (match_operand:SI 1 "general_operand" ""))]
330 /* Fixup PIC cases. */
333 if (symbolic_operand (operands[1], SImode))
335 if (reload_in_progress || reload_completed)
336 operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);
338 operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);
342 /* Everything except mem = const or mem = mem can be done easily. */
344 if (MEM_P (operands[0]))
345 operands[1] = force_reg (SImode, operands[1]);
347 /* Small Data Area reference? */
348 if (small_data_operand (operands[1], SImode))
350 emit_insn (gen_movsi_sda (operands[0], operands[1]));
354 /* If medium or large code model, symbols have to be loaded with
356 if (addr32_operand (operands[1], SImode))
358 emit_insn (gen_movsi_addr32 (operands[0], operands[1]));
363 ;; ??? Do we need a const_double constraint here for large unsigned values?
364 (define_insn "*movsi_insn"
365 [(set (match_operand:SI 0 "move_dest_operand" "=r,r,r,r,r,r,r,r,r,T,S,m")
366 (match_operand:SI 1 "move_src_operand" "r,I,J,MQ,L,n,T,U,m,r,r,r"))]
367 "register_operand (operands[0], SImode) || register_operand (operands[1], SImode)"
370 if (REG_P (operands[0]) || GET_CODE (operands[1]) == SUBREG)
372 switch (GET_CODE (operands[1]))
384 if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
385 && XEXP (XEXP (operands[1], 0), 0) == stack_pointer_rtx)
391 if (satisfies_constraint_J (operands[1]))
392 return \"ldi %0,%#%1\\t; %X1\";
394 if (satisfies_constraint_M (operands[1]))
395 return \"ld24 %0,%#%1\\t; %X1\";
397 if (satisfies_constraint_L (operands[1]))
398 return \"seth %0,%#%T1\\t; %X1\";
406 return \"ld24 %0,%#%1\";
412 else if (MEM_P (operands[0])
413 && (REG_P (operands[1]) || GET_CODE (operands[1]) == SUBREG))
415 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
416 && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx)
424 [(set_attr "type" "int2,int2,int4,int4,int4,multi,load2,load2,load4,store2,store2,store4")
425 (set_attr "length" "2,2,4,4,4,8,2,2,4,2,2,4")])
427 ; Try to use a four byte / two byte pair for constants not loadable with
431 [(set (match_operand:SI 0 "register_operand" "")
432 (match_operand:SI 1 "two_insn_const_operand" ""))]
434 [(set (match_dup 0) (match_dup 2))
435 (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 3)))]
438 unsigned HOST_WIDE_INT val = INTVAL (operands[1]);
439 unsigned HOST_WIDE_INT tmp;
442 /* In all cases we will emit two instructions. However we try to
443 use 2 byte instructions wherever possible. We can assume the
444 constant isn't loadable with any of ldi, ld24, or seth. */
446 /* See if we can load a 24-bit unsigned value and invert it. */
447 if (UINT24_P (~ val))
449 emit_insn (gen_movsi (operands[0], GEN_INT (~ val)));
450 emit_insn (gen_one_cmplsi2 (operands[0], operands[0]));
454 /* See if we can load a 24-bit unsigned value and shift it into place.
455 0x01fffffe is just beyond ld24's range. */
456 for (shift = 1, tmp = 0x01fffffe;
460 if ((val & ~tmp) == 0)
462 emit_insn (gen_movsi (operands[0], GEN_INT (val >> shift)));
463 emit_insn (gen_ashlsi3 (operands[0], operands[0], GEN_INT (shift)));
468 /* Can't use any two byte insn, fall back to seth/or3. Use ~0xffff instead
469 of 0xffff0000, since the later fails on a 64-bit host. */
470 operands[2] = GEN_INT ((val) & ~0xffff);
471 operands[3] = GEN_INT ((val) & 0xffff);
475 [(set (match_operand:SI 0 "register_operand" "")
476 (match_operand:SI 1 "seth_add3_operand" ""))]
479 (high:SI (match_dup 1)))
481 (lo_sum:SI (match_dup 0)
485 ;; Small data area support.
486 ;; The address of _SDA_BASE_ is loaded into a register and all objects in
487 ;; the small data area are indexed off that. This is done for each reference
488 ;; but cse will clean things up for us. We let the compiler choose the
489 ;; register to use so we needn't allocate (and maybe even fix) a special
490 ;; register to use. Since the load and store insns have a 16-bit offset the
491 ;; total size of the data area can be 64K. However, if the data area lives
492 ;; above 16M (24 bits), _SDA_BASE_ will have to be loaded with seth/add3 which
493 ;; would then yield 3 instructions to reference an object [though there would
494 ;; be no net loss if two or more objects were referenced]. The 3 insns can be
495 ;; reduced back to 2 if the size of the small data area were reduced to 32K
496 ;; [then seth + ld/st would work for any object in the area]. Doing this
497 ;; would require special handling of _SDA_BASE_ (its value would be
498 ;; (.sdata + 32K) & 0xffff0000) and reloc computations would be different
499 ;; [I think]. What to do about this is deferred until later and for now we
500 ;; require .sdata to be in the first 16M.
502 (define_expand "movsi_sda"
504 (unspec:SI [(const_int 0)] UNSPEC_LOAD_SDA_BASE))
505 (set (match_operand:SI 0 "register_operand" "")
506 (lo_sum:SI (match_dup 2)
507 (match_operand:SI 1 "small_data_operand" "")))]
511 if (reload_in_progress || reload_completed)
512 operands[2] = operands[0];
514 operands[2] = gen_reg_rtx (SImode);
517 (define_insn "*load_sda_base_32"
518 [(set (match_operand:SI 0 "register_operand" "=r")
519 (unspec:SI [(const_int 0)] UNSPEC_LOAD_SDA_BASE))]
521 "seth %0,%#shigh(_SDA_BASE_)\;add3 %0,%0,%#low(_SDA_BASE_)"
522 [(set_attr "type" "multi")
523 (set_attr "length" "8")])
525 (define_insn "*load_sda_base"
526 [(set (match_operand:SI 0 "register_operand" "=r")
527 (unspec:SI [(const_int 0)] UNSPEC_LOAD_SDA_BASE))]
529 "ld24 %0,#_SDA_BASE_"
530 [(set_attr "type" "int4")
531 (set_attr "length" "4")])
533 ;; 32-bit address support.
535 (define_expand "movsi_addr32"
537 ; addr32_operand isn't used because it's too restrictive,
538 ; seth_add3_operand is more general and thus safer.
539 (high:SI (match_operand:SI 1 "seth_add3_operand" "")))
540 (set (match_operand:SI 0 "register_operand" "")
541 (lo_sum:SI (match_dup 2) (match_dup 1)))]
545 if (reload_in_progress || reload_completed)
546 operands[2] = operands[0];
548 operands[2] = gen_reg_rtx (SImode);
551 (define_insn "set_hi_si"
552 [(set (match_operand:SI 0 "register_operand" "=r")
553 (high:SI (match_operand 1 "symbolic_operand" "")))]
555 "seth %0,%#shigh(%1)"
556 [(set_attr "type" "int4")
557 (set_attr "length" "4")])
559 (define_insn "lo_sum_si"
560 [(set (match_operand:SI 0 "register_operand" "=r")
561 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
562 (match_operand:SI 2 "immediate_operand" "in")))]
565 [(set_attr "type" "int4")
566 (set_attr "length" "4")])
568 (define_expand "movdi"
569 [(set (match_operand:DI 0 "general_operand" "")
570 (match_operand:DI 1 "general_operand" ""))]
574 /* Fixup PIC cases. */
577 if (symbolic_operand (operands[1], DImode))
579 if (reload_in_progress || reload_completed)
580 operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);
582 operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);
586 /* Everything except mem = const or mem = mem can be done easily. */
588 if (MEM_P (operands[0]))
589 operands[1] = force_reg (DImode, operands[1]);
592 (define_insn "*movdi_insn"
593 [(set (match_operand:DI 0 "move_dest_operand" "=r,r,r,r,m")
594 (match_operand:DI 1 "move_double_src_operand" "r,nG,F,m,r"))]
595 "register_operand (operands[0], DImode) || register_operand (operands[1], DImode)"
597 [(set_attr "type" "multi,multi,multi,load8,store8")
598 (set_attr "length" "4,4,16,6,6")])
601 [(set (match_operand:DI 0 "move_dest_operand" "")
602 (match_operand:DI 1 "move_double_src_operand" ""))]
605 "operands[2] = gen_split_move_double (operands);")
607 ;; Floating point move insns.
609 (define_expand "movsf"
610 [(set (match_operand:SF 0 "general_operand" "")
611 (match_operand:SF 1 "general_operand" ""))]
615 /* Fixup PIC cases. */
618 if (symbolic_operand (operands[1], SFmode))
620 if (reload_in_progress || reload_completed)
621 operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);
623 operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);
627 /* Everything except mem = const or mem = mem can be done easily. */
629 if (MEM_P (operands[0]))
630 operands[1] = force_reg (SFmode, operands[1]);
633 (define_insn "*movsf_insn"
634 [(set (match_operand:SF 0 "move_dest_operand" "=r,r,r,r,r,T,S,m")
635 (match_operand:SF 1 "move_src_operand" "r,F,U,S,m,r,r,r"))]
636 "register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode)"
646 ;; ??? Length of alternative 1 is either 2, 4 or 8.
647 [(set_attr "type" "int2,multi,load2,load2,load4,store2,store2,store4")
648 (set_attr "length" "2,8,2,2,4,2,2,4")])
651 [(set (match_operand:SF 0 "register_operand" "")
652 (match_operand:SF 1 "const_double_operand" ""))]
654 [(set (match_dup 2) (match_dup 3))]
657 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
658 operands[3] = operand_subword (operands[1], 0, 0, SFmode);
661 (define_expand "movdf"
662 [(set (match_operand:DF 0 "general_operand" "")
663 (match_operand:DF 1 "general_operand" ""))]
667 /* Fixup PIC cases. */
670 if (symbolic_operand (operands[1], DFmode))
672 if (reload_in_progress || reload_completed)
673 operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);
675 operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);
679 /* Everything except mem = const or mem = mem can be done easily. */
681 if (MEM_P (operands[0]))
682 operands[1] = force_reg (DFmode, operands[1]);
685 (define_insn "*movdf_insn"
686 [(set (match_operand:DF 0 "move_dest_operand" "=r,r,r,m")
687 (match_operand:DF 1 "move_double_src_operand" "r,F,m,r"))]
688 "register_operand (operands[0], DFmode) || register_operand (operands[1], DFmode)"
690 [(set_attr "type" "multi,multi,load8,store8")
691 (set_attr "length" "4,16,6,6")])
694 [(set (match_operand:DF 0 "move_dest_operand" "")
695 (match_operand:DF 1 "move_double_src_operand" ""))]
698 "operands[2] = gen_split_move_double (operands);")
700 ;; Zero extension instructions.
702 (define_insn "zero_extendqihi2"
703 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
704 (zero_extend:HI (match_operand:QI 1 "extend_operand" "r,T,m")))]
710 [(set_attr "type" "int4,load2,load4")
711 (set_attr "length" "4,2,4")])
713 (define_insn "zero_extendqisi2"
714 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
715 (zero_extend:SI (match_operand:QI 1 "extend_operand" "r,T,m")))]
721 [(set_attr "type" "int4,load2,load4")
722 (set_attr "length" "4,2,4")])
724 (define_insn "zero_extendhisi2"
725 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
726 (zero_extend:SI (match_operand:HI 1 "extend_operand" "r,T,m")))]
732 [(set_attr "type" "int4,load2,load4")
733 (set_attr "length" "4,2,4")])
735 ;; Signed conversions from a smaller integer to a larger integer
736 (define_insn "extendqihi2"
737 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
738 (sign_extend:HI (match_operand:QI 1 "extend_operand" "0,T,m")))]
744 [(set_attr "type" "multi,load2,load4")
745 (set_attr "length" "2,2,4")])
748 [(set (match_operand:HI 0 "register_operand" "")
749 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
755 rtx op0 = gen_lowpart (SImode, operands[0]);
756 rtx shift = GEN_INT (24);
758 operands[2] = gen_ashlsi3 (op0, op0, shift);
759 operands[3] = gen_ashrsi3 (op0, op0, shift);
762 (define_insn "extendqisi2"
763 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
764 (sign_extend:SI (match_operand:QI 1 "extend_operand" "0,T,m")))]
770 [(set_attr "type" "multi,load2,load4")
771 (set_attr "length" "4,2,4")])
774 [(set (match_operand:SI 0 "register_operand" "")
775 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
781 rtx shift = GEN_INT (24);
783 operands[2] = gen_ashlsi3 (operands[0], operands[0], shift);
784 operands[3] = gen_ashrsi3 (operands[0], operands[0], shift);
787 (define_insn "extendhisi2"
788 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
789 (sign_extend:SI (match_operand:HI 1 "extend_operand" "0,T,m")))]
795 [(set_attr "type" "multi,load2,load4")
796 (set_attr "length" "4,2,4")])
799 [(set (match_operand:SI 0 "register_operand" "")
800 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
806 rtx shift = GEN_INT (16);
808 operands[2] = gen_ashlsi3 (operands[0], operands[0], shift);
809 operands[3] = gen_ashrsi3 (operands[0], operands[0], shift);
812 ;; Arithmetic instructions.
814 ; ??? Adding an alternative to split add3 of small constants into two
815 ; insns yields better instruction packing but slower code. Adds of small
816 ; values is done a lot.
818 (define_insn "addsi3"
819 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
820 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,r")
821 (match_operand:SI 2 "nonmemory_operand" "r,I,J")))]
827 [(set_attr "type" "int2,int2,int4")
828 (set_attr "length" "2,2,4")])
831 ; [(set (match_operand:SI 0 "register_operand" "")
832 ; (plus:SI (match_operand:SI 1 "register_operand" "")
833 ; (match_operand:SI 2 "int8_operand" "")))]
835 ; && REGNO (operands[0]) != REGNO (operands[1])
836 ; && satisfies_constraint_I (operands[2])
837 ; && INTVAL (operands[2]) != 0"
838 ; [(set (match_dup 0) (match_dup 1))
839 ; (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
842 (define_insn "adddi3"
843 [(set (match_operand:DI 0 "register_operand" "=r")
844 (plus:DI (match_operand:DI 1 "register_operand" "%0")
845 (match_operand:DI 2 "register_operand" "r")))
846 (clobber (reg:CC 17))]
849 [(set_attr "type" "multi")
850 (set_attr "length" "6")])
852 ;; ??? The cmp clears the condition bit. Can we speed up somehow?
854 [(set (match_operand:DI 0 "register_operand" "")
855 (plus:DI (match_operand:DI 1 "register_operand" "")
856 (match_operand:DI 2 "register_operand" "")))
857 (clobber (reg:CC 17))]
859 [(parallel [(set (reg:CC 17)
861 (use (match_dup 4))])
862 (parallel [(set (match_dup 4)
863 (plus:SI (match_dup 4)
864 (plus:SI (match_dup 5)
865 (ne:SI (reg:CC 17) (const_int 0)))))
867 (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])
868 (parallel [(set (match_dup 6)
869 (plus:SI (match_dup 6)
870 (plus:SI (match_dup 7)
871 (ne:SI (reg:CC 17) (const_int 0)))))
873 (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])]
876 operands[4] = operand_subword (operands[0], (WORDS_BIG_ENDIAN != 0), 0, DImode);
877 operands[5] = operand_subword (operands[2], (WORDS_BIG_ENDIAN != 0), 0, DImode);
878 operands[6] = operand_subword (operands[0], (WORDS_BIG_ENDIAN == 0), 0, DImode);
879 operands[7] = operand_subword (operands[2], (WORDS_BIG_ENDIAN == 0), 0, DImode);
882 (define_insn "*clear_c"
885 (use (match_operand:SI 0 "register_operand" "r"))]
888 [(set_attr "type" "int2")
889 (set_attr "length" "2")])
891 (define_insn "*add_carry"
892 [(set (match_operand:SI 0 "register_operand" "=r")
893 (plus:SI (match_operand:SI 1 "register_operand" "%0")
894 (plus:SI (match_operand:SI 2 "register_operand" "r")
895 (ne:SI (reg:CC 17) (const_int 0)))))
897 (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))]
900 [(set_attr "type" "int2")
901 (set_attr "length" "2")])
903 (define_insn "subsi3"
904 [(set (match_operand:SI 0 "register_operand" "=r")
905 (minus:SI (match_operand:SI 1 "register_operand" "0")
906 (match_operand:SI 2 "register_operand" "r")))]
909 [(set_attr "type" "int2")
910 (set_attr "length" "2")])
912 (define_insn "subdi3"
913 [(set (match_operand:DI 0 "register_operand" "=r")
914 (minus:DI (match_operand:DI 1 "register_operand" "0")
915 (match_operand:DI 2 "register_operand" "r")))
916 (clobber (reg:CC 17))]
919 [(set_attr "type" "multi")
920 (set_attr "length" "6")])
922 ;; ??? The cmp clears the condition bit. Can we speed up somehow?
924 [(set (match_operand:DI 0 "register_operand" "")
925 (minus:DI (match_operand:DI 1 "register_operand" "")
926 (match_operand:DI 2 "register_operand" "")))
927 (clobber (reg:CC 17))]
929 [(parallel [(set (reg:CC 17)
931 (use (match_dup 4))])
932 (parallel [(set (match_dup 4)
933 (minus:SI (match_dup 4)
934 (minus:SI (match_dup 5)
935 (ne:SI (reg:CC 17) (const_int 0)))))
937 (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])
938 (parallel [(set (match_dup 6)
939 (minus:SI (match_dup 6)
940 (minus:SI (match_dup 7)
941 (ne:SI (reg:CC 17) (const_int 0)))))
943 (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])]
946 operands[4] = operand_subword (operands[0], (WORDS_BIG_ENDIAN != 0), 0, DImode);
947 operands[5] = operand_subword (operands[2], (WORDS_BIG_ENDIAN != 0), 0, DImode);
948 operands[6] = operand_subword (operands[0], (WORDS_BIG_ENDIAN == 0), 0, DImode);
949 operands[7] = operand_subword (operands[2], (WORDS_BIG_ENDIAN == 0), 0, DImode);
952 (define_insn "*sub_carry"
953 [(set (match_operand:SI 0 "register_operand" "=r")
954 (minus:SI (match_operand:SI 1 "register_operand" "%0")
955 (minus:SI (match_operand:SI 2 "register_operand" "r")
956 (ne:SI (reg:CC 17) (const_int 0)))))
958 (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))]
961 [(set_attr "type" "int2")
962 (set_attr "length" "2")])
964 ; Multiply/Divide instructions.
966 (define_insn "mulhisi3"
967 [(set (match_operand:SI 0 "register_operand" "=r")
968 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "r"))
969 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
971 "mullo %1,%2\;mvfacmi %0"
972 [(set_attr "type" "multi")
973 (set_attr "length" "4")])
975 (define_insn "mulsi3"
976 [(set (match_operand:SI 0 "register_operand" "=r")
977 (mult:SI (match_operand:SI 1 "register_operand" "%0")
978 (match_operand:SI 2 "register_operand" "r")))]
981 [(set_attr "type" "mul2")
982 (set_attr "length" "2")])
984 (define_insn "divsi3"
985 [(set (match_operand:SI 0 "register_operand" "=r")
986 (div:SI (match_operand:SI 1 "register_operand" "0")
987 (match_operand:SI 2 "register_operand" "r")))]
990 [(set_attr "type" "div4")
991 (set_attr "length" "4")])
993 (define_insn "udivsi3"
994 [(set (match_operand:SI 0 "register_operand" "=r")
995 (udiv:SI (match_operand:SI 1 "register_operand" "0")
996 (match_operand:SI 2 "register_operand" "r")))]
999 [(set_attr "type" "div4")
1000 (set_attr "length" "4")])
1002 (define_insn "modsi3"
1003 [(set (match_operand:SI 0 "register_operand" "=r")
1004 (mod:SI (match_operand:SI 1 "register_operand" "0")
1005 (match_operand:SI 2 "register_operand" "r")))]
1008 [(set_attr "type" "div4")
1009 (set_attr "length" "4")])
1011 (define_insn "umodsi3"
1012 [(set (match_operand:SI 0 "register_operand" "=r")
1013 (umod:SI (match_operand:SI 1 "register_operand" "0")
1014 (match_operand:SI 2 "register_operand" "r")))]
1017 [(set_attr "type" "div4")
1018 (set_attr "length" "4")])
1020 ;; Boolean instructions.
1022 ;; We don't define the DImode versions as expand_binop does a good enough job.
1023 ;; And if it doesn't it should be fixed.
1025 (define_insn "andsi3"
1026 [(set (match_operand:SI 0 "register_operand" "=r,r")
1027 (and:SI (match_operand:SI 1 "register_operand" "%0,r")
1028 (match_operand:SI 2 "reg_or_uint16_operand" "r,K")))]
1032 /* If we are worried about space, see if we can break this up into two
1033 short instructions, which might eliminate a NOP being inserted. */
1035 && m32r_not_same_reg (operands[0], operands[1])
1036 && satisfies_constraint_I (operands[2]))
1039 else if (CONST_INT_P (operands[2]))
1040 return \"and3 %0,%1,%#%X2\";
1042 return \"and %0,%2\";
1044 [(set_attr "type" "int2,int4")
1045 (set_attr "length" "2,4")])
1048 [(set (match_operand:SI 0 "register_operand" "")
1049 (and:SI (match_operand:SI 1 "register_operand" "")
1050 (match_operand:SI 2 "int8_operand" "")))]
1051 "optimize_size && m32r_not_same_reg (operands[0], operands[1])"
1052 [(set (match_dup 0) (match_dup 2))
1053 (set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))]
1056 (define_insn "iorsi3"
1057 [(set (match_operand:SI 0 "register_operand" "=r,r")
1058 (ior:SI (match_operand:SI 1 "register_operand" "%0,r")
1059 (match_operand:SI 2 "reg_or_uint16_operand" "r,K")))]
1063 /* If we are worried about space, see if we can break this up into two
1064 short instructions, which might eliminate a NOP being inserted. */
1066 && m32r_not_same_reg (operands[0], operands[1])
1067 && satisfies_constraint_I (operands[2]))
1070 else if (CONST_INT_P (operands[2]))
1071 return \"or3 %0,%1,%#%X2\";
1073 return \"or %0,%2\";
1075 [(set_attr "type" "int2,int4")
1076 (set_attr "length" "2,4")])
1079 [(set (match_operand:SI 0 "register_operand" "")
1080 (ior:SI (match_operand:SI 1 "register_operand" "")
1081 (match_operand:SI 2 "int8_operand" "")))]
1082 "optimize_size && m32r_not_same_reg (operands[0], operands[1])"
1083 [(set (match_dup 0) (match_dup 2))
1084 (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 1)))]
1087 (define_insn "xorsi3"
1088 [(set (match_operand:SI 0 "register_operand" "=r,r")
1089 (xor:SI (match_operand:SI 1 "register_operand" "%0,r")
1090 (match_operand:SI 2 "reg_or_uint16_operand" "r,K")))]
1094 /* If we are worried about space, see if we can break this up into two
1095 short instructions, which might eliminate a NOP being inserted. */
1097 && m32r_not_same_reg (operands[0], operands[1])
1098 && satisfies_constraint_I (operands[2]))
1101 else if (CONST_INT_P (operands[2]))
1102 return \"xor3 %0,%1,%#%X2\";
1104 return \"xor %0,%2\";
1106 [(set_attr "type" "int2,int4")
1107 (set_attr "length" "2,4")])
1110 [(set (match_operand:SI 0 "register_operand" "")
1111 (xor:SI (match_operand:SI 1 "register_operand" "")
1112 (match_operand:SI 2 "int8_operand" "")))]
1113 "optimize_size && m32r_not_same_reg (operands[0], operands[1])"
1114 [(set (match_dup 0) (match_dup 2))
1115 (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))]
1118 (define_insn "negsi2"
1119 [(set (match_operand:SI 0 "register_operand" "=r")
1120 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
1123 [(set_attr "type" "int2")
1124 (set_attr "length" "2")])
1126 (define_insn "one_cmplsi2"
1127 [(set (match_operand:SI 0 "register_operand" "=r")
1128 (not:SI (match_operand:SI 1 "register_operand" "r")))]
1131 [(set_attr "type" "int2")
1132 (set_attr "length" "2")])
1134 ;; Shift instructions.
1136 (define_insn "ashlsi3"
1137 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1138 (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r")
1139 (match_operand:SI 2 "reg_or_uint16_operand" "r,O,K")))]
1145 [(set_attr "type" "shift2,shift2,shift4")
1146 (set_attr "length" "2,2,4")])
1148 (define_insn "ashrsi3"
1149 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1150 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
1151 (match_operand:SI 2 "reg_or_uint16_operand" "r,O,K")))]
1157 [(set_attr "type" "shift2,shift2,shift4")
1158 (set_attr "length" "2,2,4")])
1160 (define_insn "lshrsi3"
1161 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1162 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
1163 (match_operand:SI 2 "reg_or_uint16_operand" "r,O,K")))]
1169 [(set_attr "type" "shift2,shift2,shift4")
1170 (set_attr "length" "2,2,4")])
1172 ;; Compare instructions.
1173 ;; This controls RTL generation and register allocation.
1175 ;; We generate RTL for comparisons and branches by having the cmpxx
1176 ;; patterns store away the operands. Then the bcc patterns
1177 ;; emit RTL for both the compare and the branch.
1179 ;; On the m32r it is more efficient to use the bxxz instructions and
1180 ;; thus merge the compare and branch into one instruction, so they are
1183 (define_insn "cmp_eqsi_zero_insn"
1185 (eq:CC (match_operand:SI 0 "register_operand" "r,r")
1186 (match_operand:SI 1 "reg_or_zero_operand" "r,P")))]
1187 "TARGET_M32RX || TARGET_M32R2"
1191 [(set_attr "type" "int4")
1192 (set_attr "length" "4")])
1194 ;; The cmp_xxx_insn patterns set the condition bit to the result of the
1195 ;; comparison. There isn't a "compare equal" instruction so cmp_eqsi_insn
1196 ;; is quite inefficient. However, it is rarely used.
1198 (define_insn "cmp_eqsi_insn"
1200 (eq:CC (match_operand:SI 0 "register_operand" "r,r")
1201 (match_operand:SI 1 "reg_or_cmp_int16_operand" "r,P")))
1202 (clobber (match_scratch:SI 2 "=&r,&r"))]
1206 if (which_alternative == 0)
1208 return \"mv %2,%0\;sub %2,%1\;cmpui %2,#1\";
1212 if (INTVAL (operands [1]) == 0)
1213 return \"cmpui %0, #1\";
1214 else if (REGNO (operands [2]) == REGNO (operands [0]))
1215 return \"addi %0,%#%N1\;cmpui %2,#1\";
1217 return \"add3 %2,%0,%#%N1\;cmpui %2,#1\";
1220 [(set_attr "type" "multi,multi")
1221 (set_attr "length" "8,8")])
1223 (define_insn "cmp_ltsi_insn"
1225 (lt:CC (match_operand:SI 0 "register_operand" "r,r")
1226 (match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
1231 [(set_attr "type" "int2,int4")
1232 (set_attr "length" "2,4")])
1234 (define_insn "cmp_ltusi_insn"
1236 (ltu:CC (match_operand:SI 0 "register_operand" "r,r")
1237 (match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
1242 [(set_attr "type" "int2,int4")
1243 (set_attr "length" "2,4")])
1245 ;; These control RTL generation for conditional jump insns.
1247 (define_expand "cbranchsi4"
1248 ; the comparison is emitted by gen_compare if needed.
1250 (if_then_else (match_operator 0 "ordered_comparison_operator"
1251 [(match_operand:SI 1 "register_operand" "")
1252 (match_operand:SI 2 "reg_or_cmp_int16_operand" "")])
1253 (label_ref (match_operand 3 "" ""))
1258 operands[0] = gen_compare (GET_CODE (operands[0]), operands[1], operands[2], FALSE);
1259 operands[1] = XEXP (operands[0], 0);
1260 operands[2] = XEXP (operands[0], 1);
1263 ;; Now match both normal and inverted jump.
1265 (define_insn "*branch_insn"
1267 (if_then_else (match_operator 1 "eqne_comparison_operator"
1268 [(reg 17) (const_int 0)])
1269 (label_ref (match_operand 0 "" ""))
1274 static char instruction[40];
1275 sprintf (instruction, \"%s%s %%l0\",
1276 (GET_CODE (operands[1]) == NE) ? \"bc\" : \"bnc\",
1277 (get_attr_length (insn) == 2) ? \".s\" : \"\");
1280 [(set_attr "type" "branch")
1282 ; We use 300/600 instead of 512,1024 to account for inaccurate insn
1283 ; lengths and insn alignments that are complex to track.
1284 ; It's not important that we be hyper-precise here. It may be more
1285 ; important blah blah blah when the chip supports parallel execution
1286 ; blah blah blah but until then blah blah blah this is simple and
1288 (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
1294 (define_insn "*rev_branch_insn"
1296 (if_then_else (match_operator 1 "eqne_comparison_operator"
1297 [(reg 17) (const_int 0)])
1299 (label_ref (match_operand 0 "" ""))))]
1300 ;"REVERSIBLE_CC_MODE (GET_MODE (XEXP (operands[1], 0)))"
1304 static char instruction[40];
1305 sprintf (instruction, \"%s%s %%l0\",
1306 (GET_CODE (operands[1]) == EQ) ? \"bc\" : \"bnc\",
1307 (get_attr_length (insn) == 2) ? \".s\" : \"\");
1310 [(set_attr "type" "branch")
1312 ; We use 300/600 instead of 512,1024 to account for inaccurate insn
1313 ; lengths and insn alignments that are complex to track.
1314 ; It's not important that we be hyper-precise here. It may be more
1315 ; important blah blah blah when the chip supports parallel execution
1316 ; blah blah blah but until then blah blah blah this is simple and
1318 (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
1324 ; reg/reg compare and branch insns
1326 (define_insn "*reg_branch_insn"
1328 (if_then_else (match_operator 1 "eqne_comparison_operator"
1329 [(match_operand:SI 2 "register_operand" "r")
1330 (match_operand:SI 3 "register_operand" "r")])
1331 (label_ref (match_operand 0 "" ""))
1336 /* Is branch target reachable with beq/bne? */
1337 if (get_attr_length (insn) == 4)
1339 if (GET_CODE (operands[1]) == EQ)
1340 return \"beq %2,%3,%l0\";
1342 return \"bne %2,%3,%l0\";
1346 if (GET_CODE (operands[1]) == EQ)
1347 return \"bne %2,%3,1f\;bra %l0\;1:\";
1349 return \"beq %2,%3,1f\;bra %l0\;1:\";
1352 [(set_attr "type" "branch")
1353 ; We use 25000/50000 instead of 32768/65536 to account for slot filling
1354 ; which is complex to track and inaccurate length specs.
1355 (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
1361 (define_insn "*rev_reg_branch_insn"
1363 (if_then_else (match_operator 1 "eqne_comparison_operator"
1364 [(match_operand:SI 2 "register_operand" "r")
1365 (match_operand:SI 3 "register_operand" "r")])
1367 (label_ref (match_operand 0 "" ""))))]
1371 /* Is branch target reachable with beq/bne? */
1372 if (get_attr_length (insn) == 4)
1374 if (GET_CODE (operands[1]) == NE)
1375 return \"beq %2,%3,%l0\";
1377 return \"bne %2,%3,%l0\";
1381 if (GET_CODE (operands[1]) == NE)
1382 return \"bne %2,%3,1f\;bra %l0\;1:\";
1384 return \"beq %2,%3,1f\;bra %l0\;1:\";
1387 [(set_attr "type" "branch")
1388 ; We use 25000/50000 instead of 32768/65536 to account for slot filling
1389 ; which is complex to track and inaccurate length specs.
1390 (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
1396 ; reg/zero compare and branch insns
1398 (define_insn "*zero_branch_insn"
1400 (if_then_else (match_operator 1 "signed_comparison_operator"
1401 [(match_operand:SI 2 "register_operand" "r")
1403 (label_ref (match_operand 0 "" ""))
1408 const char *br,*invbr;
1411 switch (GET_CODE (operands[1]))
1413 case EQ : br = \"eq\"; invbr = \"ne\"; break;
1414 case NE : br = \"ne\"; invbr = \"eq\"; break;
1415 case LE : br = \"le\"; invbr = \"gt\"; break;
1416 case GT : br = \"gt\"; invbr = \"le\"; break;
1417 case LT : br = \"lt\"; invbr = \"ge\"; break;
1418 case GE : br = \"ge\"; invbr = \"lt\"; break;
1420 default: gcc_unreachable ();
1423 /* Is branch target reachable with bxxz? */
1424 if (get_attr_length (insn) == 4)
1426 sprintf (asmtext, \"b%sz %%2,%%l0\", br);
1427 output_asm_insn (asmtext, operands);
1431 sprintf (asmtext, \"b%sz %%2,1f\;bra %%l0\;1:\", invbr);
1432 output_asm_insn (asmtext, operands);
1436 [(set_attr "type" "branch")
1437 ; We use 25000/50000 instead of 32768/65536 to account for slot filling
1438 ; which is complex to track and inaccurate length specs.
1439 (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
1445 (define_insn "*rev_zero_branch_insn"
1447 (if_then_else (match_operator 1 "eqne_comparison_operator"
1448 [(match_operand:SI 2 "register_operand" "r")
1451 (label_ref (match_operand 0 "" ""))))]
1455 const char *br,*invbr;
1458 switch (GET_CODE (operands[1]))
1460 case EQ : br = \"eq\"; invbr = \"ne\"; break;
1461 case NE : br = \"ne\"; invbr = \"eq\"; break;
1462 case LE : br = \"le\"; invbr = \"gt\"; break;
1463 case GT : br = \"gt\"; invbr = \"le\"; break;
1464 case LT : br = \"lt\"; invbr = \"ge\"; break;
1465 case GE : br = \"ge\"; invbr = \"lt\"; break;
1467 default: gcc_unreachable ();
1470 /* Is branch target reachable with bxxz? */
1471 if (get_attr_length (insn) == 4)
1473 sprintf (asmtext, \"b%sz %%2,%%l0\", invbr);
1474 output_asm_insn (asmtext, operands);
1478 sprintf (asmtext, \"b%sz %%2,1f\;bra %%l0\;1:\", br);
1479 output_asm_insn (asmtext, operands);
1483 [(set_attr "type" "branch")
1484 ; We use 25000/50000 instead of 32768/65536 to account for slot filling
1485 ; which is complex to track and inaccurate length specs.
1486 (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
1492 ;; S<cc> operations to set a register to 1/0 based on a comparison
1494 (define_expand "cstoresi4"
1495 [(match_operand:SI 0 "register_operand" "")
1496 (match_operator:SI 1 "ordered_comparison_operator"
1497 [(match_operand:SI 2 "register_operand" "")
1498 (match_operand:SI 3 "reg_or_cmp_int16_operand" "")])]
1502 if (GET_MODE (operands[0]) != SImode)
1505 if (!gen_cond_store (GET_CODE (operands[1]),
1506 operands[0], operands[2], operands[3]))
1512 (define_insn "seq_insn_m32rx"
1513 [(set (match_operand:SI 0 "register_operand" "=r")
1514 (eq:SI (match_operand:SI 1 "register_operand" "%r")
1515 (match_operand:SI 2 "reg_or_zero_operand" "rP")))
1516 (clobber (reg:CC 17))]
1517 "TARGET_M32RX || TARGET_M32R2"
1519 [(set_attr "type" "multi")
1520 (set_attr "length" "6")])
1523 [(set (match_operand:SI 0 "register_operand" "")
1524 (eq:SI (match_operand:SI 1 "register_operand" "")
1525 (match_operand:SI 2 "reg_or_zero_operand" "")))
1526 (clobber (reg:CC 17))]
1527 "TARGET_M32RX || TARGET_M32R2"
1529 (eq:CC (match_dup 1)
1532 (ne:SI (reg:CC 17) (const_int 0)))]
1535 (define_insn "seq_zero_insn"
1536 [(set (match_operand:SI 0 "register_operand" "=r")
1537 (eq:SI (match_operand:SI 1 "register_operand" "r")
1539 (clobber (reg:CC 17))]
1542 [(set_attr "type" "multi")
1543 (set_attr "length" "6")])
1546 [(set (match_operand:SI 0 "register_operand" "")
1547 (eq:SI (match_operand:SI 1 "register_operand" "")
1549 (clobber (reg:CC 17))]
1554 rtx op0 = operands[0];
1555 rtx op1 = operands[1];
1558 emit_insn (gen_cmp_ltusi_insn (op1, const1_rtx));
1559 emit_insn (gen_movcc_insn (op0));
1560 operands[3] = get_insns ();
1564 (define_insn "seq_insn"
1565 [(set (match_operand:SI 0 "register_operand" "=r,r,??r,r")
1566 (eq:SI (match_operand:SI 1 "register_operand" "r,r,r,r")
1567 (match_operand:SI 2 "reg_or_eq_int16_operand" "r,r,r,PK")))
1568 (clobber (reg:CC 17))
1569 (clobber (match_scratch:SI 3 "=1,2,&r,r"))]
1572 [(set_attr "type" "multi")
1573 (set_attr "length" "8,8,10,10")])
1576 [(set (match_operand:SI 0 "register_operand" "")
1577 (eq:SI (match_operand:SI 1 "register_operand" "")
1578 (match_operand:SI 2 "reg_or_eq_int16_operand" "")))
1579 (clobber (reg:CC 17))
1580 (clobber (match_scratch:SI 3 ""))]
1581 "TARGET_M32R && reload_completed"
1585 rtx op0 = operands[0];
1586 rtx op1 = operands[1];
1587 rtx op2 = operands[2];
1588 rtx op3 = operands[3];
1589 HOST_WIDE_INT value;
1591 if (REG_P (op2) && REG_P (op3)
1592 && REGNO (op2) == REGNO (op3))
1599 if (REG_P (op1) && REG_P (op3)
1600 && REGNO (op1) != REGNO (op3))
1602 emit_move_insn (op3, op1);
1606 if (satisfies_constraint_P (op2) && (value = INTVAL (op2)) != 0)
1607 emit_insn (gen_addsi3 (op3, op1, GEN_INT (-value)));
1609 emit_insn (gen_xorsi3 (op3, op1, op2));
1611 emit_insn (gen_cmp_ltusi_insn (op3, const1_rtx));
1612 emit_insn (gen_movcc_insn (op0));
1613 operands[4] = get_insns ();
1617 (define_insn "sne_zero_insn"
1618 [(set (match_operand:SI 0 "register_operand" "=r")
1619 (ne:SI (match_operand:SI 1 "register_operand" "r")
1621 (clobber (reg:CC 17))
1622 (clobber (match_scratch:SI 2 "=&r"))]
1625 [(set_attr "type" "multi")
1626 (set_attr "length" "6")])
1629 [(set (match_operand:SI 0 "register_operand" "")
1630 (ne:SI (match_operand:SI 1 "register_operand" "")
1632 (clobber (reg:CC 17))
1633 (clobber (match_scratch:SI 2 ""))]
1638 (ltu:CC (match_dup 2)
1641 (ne:SI (reg:CC 17) (const_int 0)))]
1644 (define_insn "slt_insn"
1645 [(set (match_operand:SI 0 "register_operand" "=r,r")
1646 (lt:SI (match_operand:SI 1 "register_operand" "r,r")
1647 (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
1648 (clobber (reg:CC 17))]
1651 [(set_attr "type" "multi")
1652 (set_attr "length" "4,6")])
1655 [(set (match_operand:SI 0 "register_operand" "")
1656 (lt:SI (match_operand:SI 1 "register_operand" "")
1657 (match_operand:SI 2 "reg_or_int16_operand" "")))
1658 (clobber (reg:CC 17))]
1661 (lt:CC (match_dup 1)
1664 (ne:SI (reg:CC 17) (const_int 0)))]
1667 (define_insn "sle_insn"
1668 [(set (match_operand:SI 0 "register_operand" "=r")
1669 (le:SI (match_operand:SI 1 "register_operand" "r")
1670 (match_operand:SI 2 "register_operand" "r")))
1671 (clobber (reg:CC 17))]
1674 [(set_attr "type" "multi")
1675 (set_attr "length" "8")])
1678 [(set (match_operand:SI 0 "register_operand" "")
1679 (le:SI (match_operand:SI 1 "register_operand" "")
1680 (match_operand:SI 2 "register_operand" "")))
1681 (clobber (reg:CC 17))]
1684 (lt:CC (match_dup 2)
1687 (ne:SI (reg:CC 17) (const_int 0)))
1689 (xor:SI (match_dup 0)
1693 ;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
1694 ;; xor reg,reg,1 which might eliminate a NOP being inserted.
1696 [(set (match_operand:SI 0 "register_operand" "")
1697 (le:SI (match_operand:SI 1 "register_operand" "")
1698 (match_operand:SI 2 "register_operand" "")))
1699 (clobber (reg:CC 17))]
1702 (lt:CC (match_dup 2)
1705 (ne:SI (reg:CC 17) (const_int 0)))
1707 (plus:SI (match_dup 0)
1710 (neg:SI (match_dup 0)))]
1713 (define_insn "sge_insn"
1714 [(set (match_operand:SI 0 "register_operand" "=r,r")
1715 (ge:SI (match_operand:SI 1 "register_operand" "r,r")
1716 (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
1717 (clobber (reg:CC 17))]
1720 [(set_attr "type" "multi")
1721 (set_attr "length" "8,10")])
1724 [(set (match_operand:SI 0 "register_operand" "")
1725 (ge:SI (match_operand:SI 1 "register_operand" "")
1726 (match_operand:SI 2 "reg_or_int16_operand" "")))
1727 (clobber (reg:CC 17))]
1730 (lt:CC (match_dup 1)
1733 (ne:SI (reg:CC 17) (const_int 0)))
1735 (xor:SI (match_dup 0)
1739 ;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
1740 ;; xor reg,reg,1 which might eliminate a NOP being inserted.
1742 [(set (match_operand:SI 0 "register_operand" "")
1743 (ge:SI (match_operand:SI 1 "register_operand" "")
1744 (match_operand:SI 2 "reg_or_int16_operand" "")))
1745 (clobber (reg:CC 17))]
1748 (lt:CC (match_dup 1)
1751 (ne:SI (reg:CC 17) (const_int 0)))
1753 (plus:SI (match_dup 0)
1756 (neg:SI (match_dup 0)))]
1759 (define_insn "sltu_insn"
1760 [(set (match_operand:SI 0 "register_operand" "=r,r")
1761 (ltu:SI (match_operand:SI 1 "register_operand" "r,r")
1762 (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
1763 (clobber (reg:CC 17))]
1766 [(set_attr "type" "multi")
1767 (set_attr "length" "6,8")])
1770 [(set (match_operand:SI 0 "register_operand" "")
1771 (ltu:SI (match_operand:SI 1 "register_operand" "")
1772 (match_operand:SI 2 "reg_or_int16_operand" "")))
1773 (clobber (reg:CC 17))]
1776 (ltu:CC (match_dup 1)
1779 (ne:SI (reg:CC 17) (const_int 0)))]
1782 (define_insn "sleu_insn"
1783 [(set (match_operand:SI 0 "register_operand" "=r")
1784 (leu:SI (match_operand:SI 1 "register_operand" "r")
1785 (match_operand:SI 2 "register_operand" "r")))
1786 (clobber (reg:CC 17))]
1789 [(set_attr "type" "multi")
1790 (set_attr "length" "8")])
1793 [(set (match_operand:SI 0 "register_operand" "")
1794 (leu:SI (match_operand:SI 1 "register_operand" "")
1795 (match_operand:SI 2 "register_operand" "")))
1796 (clobber (reg:CC 17))]
1799 (ltu:CC (match_dup 2)
1802 (ne:SI (reg:CC 17) (const_int 0)))
1804 (xor:SI (match_dup 0)
1808 ;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
1809 ;; xor reg,reg,1 which might eliminate a NOP being inserted.
1811 [(set (match_operand:SI 0 "register_operand" "")
1812 (leu:SI (match_operand:SI 1 "register_operand" "")
1813 (match_operand:SI 2 "register_operand" "")))
1814 (clobber (reg:CC 17))]
1817 (ltu:CC (match_dup 2)
1820 (ne:SI (reg:CC 17) (const_int 0)))
1822 (plus:SI (match_dup 0)
1825 (neg:SI (match_dup 0)))]
1828 (define_insn "sgeu_insn"
1829 [(set (match_operand:SI 0 "register_operand" "=r,r")
1830 (geu:SI (match_operand:SI 1 "register_operand" "r,r")
1831 (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
1832 (clobber (reg:CC 17))]
1835 [(set_attr "type" "multi")
1836 (set_attr "length" "8,10")])
1839 [(set (match_operand:SI 0 "register_operand" "")
1840 (geu:SI (match_operand:SI 1 "register_operand" "")
1841 (match_operand:SI 2 "reg_or_int16_operand" "")))
1842 (clobber (reg:CC 17))]
1845 (ltu:CC (match_dup 1)
1848 (ne:SI (reg:CC 17) (const_int 0)))
1850 (xor:SI (match_dup 0)
1854 ;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
1855 ;; xor reg,reg,1 which might eliminate a NOP being inserted.
1857 [(set (match_operand:SI 0 "register_operand" "")
1858 (geu:SI (match_operand:SI 1 "register_operand" "")
1859 (match_operand:SI 2 "reg_or_int16_operand" "")))
1860 (clobber (reg:CC 17))]
1863 (ltu:CC (match_dup 1)
1866 (ne:SI (reg:CC 17) (const_int 0)))
1868 (plus:SI (match_dup 0)
1871 (neg:SI (match_dup 0)))]
1874 (define_insn "movcc_insn"
1875 [(set (match_operand:SI 0 "register_operand" "=r")
1876 (ne:SI (reg:CC 17) (const_int 0)))]
1879 [(set_attr "type" "misc")
1880 (set_attr "length" "2")])
1883 ;; Unconditional and other jump instructions.
1886 [(set (pc) (label_ref (match_operand 0 "" "")))]
1889 [(set_attr "type" "uncond_branch")
1890 (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
1896 (define_insn "indirect_jump"
1897 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
1900 [(set_attr "type" "uncond_branch")
1901 (set_attr "length" "2")])
1903 (define_insn "return_lr"
1904 [(parallel [(return) (use (reg:SI 14))])]
1907 [(set_attr "type" "uncond_branch")
1908 (set_attr "length" "2")])
1910 (define_insn "return_rte"
1914 [(set_attr "type" "uncond_branch")
1915 (set_attr "length" "2")])
1917 (define_expand "return"
1922 emit_jump_insn (gen_return_lr ());
1926 (define_expand "return_normal"
1931 enum m32r_function_type fn_type;
1933 fn_type = m32r_compute_function_type (current_function_decl);
1934 if (M32R_INTERRUPT_P (fn_type))
1936 emit_jump_insn (gen_return_rte ());
1940 emit_jump_insn (gen_return_lr ());
1944 (define_expand "tablejump"
1945 [(parallel [(set (pc) (match_operand 0 "register_operand" "r"))
1946 (use (label_ref (match_operand 1 "" "")))])]
1950 /* In pic mode, our address differences are against the base of the
1951 table. Add that base value back in; CSE ought to be able to combine
1952 the two address loads. */
1957 tmp = gen_rtx_LABEL_REF (Pmode, operands[1]);
1959 tmp = gen_rtx_PLUS (Pmode, tmp2, tmp);
1960 operands[0] = memory_address (Pmode, tmp);
1964 (define_insn "*tablejump_insn"
1965 [(set (pc) (match_operand:SI 0 "address_operand" "p"))
1966 (use (label_ref (match_operand 1 "" "")))]
1969 [(set_attr "type" "uncond_branch")
1970 (set_attr "length" "2")])
1972 (define_expand "call"
1973 ;; operands[1] is stack_size_rtx
1974 ;; operands[2] is next_arg_register
1975 [(parallel [(call (match_operand:SI 0 "call_operand" "")
1976 (match_operand 1 "" ""))
1977 (clobber (reg:SI 14))])]
1982 crtl->uses_pic_offset_table = 1;
1985 (define_insn "*call_via_reg"
1986 [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
1987 (match_operand 1 "" ""))
1988 (clobber (reg:SI 14))]
1991 [(set_attr "type" "call")
1992 (set_attr "length" "2")])
1994 (define_insn "*call_via_label"
1995 [(call (mem:SI (match_operand:SI 0 "call_address_operand" ""))
1996 (match_operand 1 "" ""))
1997 (clobber (reg:SI 14))]
2001 int call26_p = call26_operand (operands[0], FUNCTION_MODE);
2005 /* We may not be able to reach with a `bl' insn so punt and leave it to
2007 We do this here, rather than doing a force_reg in the define_expand
2008 so these insns won't be separated, say by scheduling, thus simplifying
2010 return \"seth r14,%T0\;add3 r14,r14,%B0\;jl r14\";
2015 [(set_attr "type" "call")
2016 (set (attr "length")
2017 (if_then_else (eq (symbol_ref "call26_operand (operands[0], FUNCTION_MODE)")
2019 (const_int 12) ; 10 + 2 for nop filler
2020 ; The return address must be on a 4 byte boundary so
2021 ; there's no point in using a value of 2 here. A 2 byte
2022 ; insn may go in the left slot but we currently can't
2023 ; use such knowledge.
2026 (define_expand "call_value"
2027 ;; operand 2 is stack_size_rtx
2028 ;; operand 3 is next_arg_register
2029 [(parallel [(set (match_operand 0 "register_operand" "=r")
2030 (call (match_operand:SI 1 "call_operand" "")
2031 (match_operand 2 "" "")))
2032 (clobber (reg:SI 14))])]
2037 crtl->uses_pic_offset_table = 1;
2040 (define_insn "*call_value_via_reg"
2041 [(set (match_operand 0 "register_operand" "=r")
2042 (call (mem:SI (match_operand:SI 1 "register_operand" "r"))
2043 (match_operand 2 "" "")))
2044 (clobber (reg:SI 14))]
2047 [(set_attr "type" "call")
2048 (set_attr "length" "2")])
2050 (define_insn "*call_value_via_label"
2051 [(set (match_operand 0 "register_operand" "=r")
2052 (call (mem:SI (match_operand:SI 1 "call_address_operand" ""))
2053 (match_operand 2 "" "")))
2054 (clobber (reg:SI 14))]
2058 int call26_p = call26_operand (operands[1], FUNCTION_MODE);
2061 crtl->uses_pic_offset_table = 1;
2065 /* We may not be able to reach with a `bl' insn so punt and leave it to
2067 We do this here, rather than doing a force_reg in the define_expand
2068 so these insns won't be separated, say by scheduling, thus simplifying
2070 return \"seth r14,%T1\;add3 r14,r14,%B1\;jl r14\";
2075 [(set_attr "type" "call")
2076 (set (attr "length")
2077 (if_then_else (eq (symbol_ref "call26_operand (operands[1], FUNCTION_MODE)")
2079 (const_int 12) ; 10 + 2 for nop filler
2080 ; The return address must be on a 4 byte boundary so
2081 ; there's no point in using a value of 2 here. A 2 byte
2082 ; insn may go in the left slot but we currently can't
2083 ; use such knowledge.
2090 [(set_attr "type" "int2")
2091 (set_attr "length" "2")])
2093 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
2094 ;; all of memory. This blocks insns from being moved across this point.
2096 (define_insn "blockage"
2097 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
2101 ;; Special pattern to flush the icache.
2103 (define_insn "flush_icache"
2104 [(unspec_volatile [(match_operand 0 "memory_operand" "m")]
2105 UNSPECV_FLUSH_ICACHE)
2106 (match_operand 1 "" "")
2107 (clobber (reg:SI 17))]
2109 "* return \"trap %#%1 ; flush-icache\";"
2110 [(set_attr "type" "int4")
2111 (set_attr "length" "4")])
2113 ;; Speed up fabs and provide correct sign handling for -0
2115 (define_insn "absdf2"
2116 [(set (match_operand:DF 0 "register_operand" "=r")
2117 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
2120 [(set_attr "type" "multi")
2121 (set_attr "length" "4")])
2124 [(set (match_operand:DF 0 "register_operand" "")
2125 (abs:DF (match_operand:DF 1 "register_operand" "")))]
2128 (ashift:SI (match_dup 2)
2131 (lshiftrt:SI (match_dup 2)
2133 "operands[2] = gen_highpart (SImode, operands[0]);")
2135 (define_insn "abssf2"
2136 [(set (match_operand:SF 0 "register_operand" "=r")
2137 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
2140 [(set_attr "type" "multi")
2141 (set_attr "length" "4")])
2144 [(set (match_operand:SF 0 "register_operand" "")
2145 (abs:SF (match_operand:SF 1 "register_operand" "")))]
2148 (ashift:SI (match_dup 2)
2151 (lshiftrt:SI (match_dup 2)
2153 "operands[2] = gen_highpart (SImode, operands[0]);")
2155 ;; Conditional move instructions
2156 ;; Based on those done for the d10v
2158 (define_expand "movsicc"
2160 (set (match_operand:SI 0 "register_operand" "r")
2161 (if_then_else:SI (match_operand 1 "" "")
2162 (match_operand:SI 2 "conditional_move_operand" "O")
2163 (match_operand:SI 3 "conditional_move_operand" "O")
2170 if (! zero_and_one (operands [2], operands [3]))
2173 /* Generate the comparison that will set the carry flag. */
2174 operands[1] = gen_compare (GET_CODE (operands[1]), XEXP (operands[1], 0),
2175 XEXP (operands[1], 1), TRUE);
2177 /* See other movsicc pattern below for reason why. */
2178 emit_insn (gen_blockage ());
2181 ;; Generate the conditional instructions based on how the carry flag is examined.
2182 (define_insn "*movsicc_internal"
2183 [(set (match_operand:SI 0 "register_operand" "=r")
2184 (if_then_else:SI (match_operand 1 "carry_compare_operand" "")
2185 (match_operand:SI 2 "conditional_move_operand" "O")
2186 (match_operand:SI 3 "conditional_move_operand" "O")
2189 "zero_and_one (operands [2], operands[3])"
2190 "* return emit_cond_move (operands, insn);"
2191 [(set_attr "type" "multi")
2192 (set_attr "length" "8")
2197 ;; Block moves, see m32r.c for more details.
2198 ;; Argument 0 is the destination
2199 ;; Argument 1 is the source
2200 ;; Argument 2 is the length
2201 ;; Argument 3 is the alignment
2203 (define_expand "movmemsi"
2204 [(parallel [(set (match_operand:BLK 0 "general_operand" "")
2205 (match_operand:BLK 1 "general_operand" ""))
2206 (use (match_operand:SI 2 "immediate_operand" ""))
2207 (use (match_operand:SI 3 "immediate_operand" ""))])]
2211 if (operands[0]) /* Avoid unused code messages. */
2213 if (m32r_expand_block_move (operands))
2220 ;; Insn generated by block moves
2222 (define_insn "movmemsi_internal"
2223 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r")) ;; destination
2224 (mem:BLK (match_operand:SI 1 "register_operand" "r"))) ;; source
2225 (use (match_operand:SI 2 "m32r_block_immediate_operand" "J"));; # bytes to move
2226 (set (match_operand:SI 3 "register_operand" "=0")
2227 (plus:SI (minus (match_dup 2) (const_int 4))
2229 (set (match_operand:SI 4 "register_operand" "=1")
2230 (plus:SI (match_dup 1)
2232 (clobber (match_scratch:SI 5 "=&r")) ;; temp1
2233 (clobber (match_scratch:SI 6 "=&r"))] ;; temp2
2235 "* m32r_output_block_move (insn, operands); return \"\"; "
2236 [(set_attr "type" "store8")
2237 (set_attr "length" "72")]) ;; Maximum
2241 /* When generating pic, we need to load the symbol offset into a register.
2242 So that the optimizer does not confuse this with a normal symbol load
2243 we use an unspec. The offset will be loaded from a constant pool entry,
2244 since that is the only type of relocation we can use. */
2246 (define_insn "pic_load_addr"
2247 [(set (match_operand:SI 0 "register_operand" "=r")
2248 (unspec:SI [(match_operand 1 "" "")] UNSPEC_PIC_LOAD_ADDR))]
2251 [(set_attr "type" "int4")])
2253 (define_insn "gotoff_load_addr"
2254 [(set (match_operand:SI 0 "register_operand" "=r")
2255 (unspec:SI [(match_operand 1 "" "")] UNSPEC_GOTOFF))]
2257 "seth %0, %#shigh(%1@GOTOFF)\;add3 %0, %0, low(%1@GOTOFF)"
2258 [(set_attr "type" "int4")
2259 (set_attr "length" "8")])
2261 ;; Load program counter insns.
2263 (define_insn "get_pc"
2264 [(clobber (reg:SI 14))
2265 (set (match_operand 0 "register_operand" "=r,r")
2266 (unspec [(match_operand 1 "" "")] UNSPEC_GET_PC))
2267 (use (match_operand:SI 2 "immediate_operand" "W,i"))]
2270 bl.s .+4\;seth %0,%#shigh(%1)\;add3 %0,%0,%#low(%1+4)\;add %0,lr
2271 bl.s .+4\;ld24 %0,%#%1\;add %0,lr"
2272 [(set_attr "length" "12,8")])
2274 (define_expand "builtin_setjmp_receiver"
2275 [(label_ref (match_operand 0 "" ""))]
2279 m32r_load_pic_register ();