1 /* Definitions of target machine for GNU compiler, Renesas M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
3 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
28 #undef WCHAR_TYPE_SIZE
40 /* M32R/X overrides. */
41 /* Print subsidiary information on the compiler version in use. */
42 #define TARGET_VERSION fprintf (stderr, " (m32r/x/2)");
44 /* Additional flags for the preprocessor. */
45 #define CPP_CPU_SPEC "%{m32rx:-D__M32RX__ -D__m32rx__ -U__M32R2__ -U__m32r2__} \
46 %{m32r2:-D__M32R2__ -D__m32r2__ -U__M32RX__ -U__m32rx__} \
47 %{m32r:-U__M32RX__ -U__m32rx__ -U__M32R2__ -U__m32r2__} \
50 /* Assembler switches. */
51 #define ASM_CPU_SPEC \
52 "%{m32r} %{m32rx} %{m32r2} %{!O0: %{O*: -O}} --no-warn-explicit-parallel-conflicts"
54 /* Use m32rx specific crt0/crtinit/crtfini files. */
55 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} %{m32rx:m32rx/crtinit.o%s} %{!m32rx:crtinit.o%s}"
56 #define ENDFILE_CPU_SPEC "-lgloss %{m32rx:m32rx/crtfini.o%s} %{!m32rx:crtfini.o%s}"
58 /* Define this macro as a C expression for the initializer of an array of
59 strings to tell the driver program which options are defaults for this
60 target and thus do not need to be handled specially when using
61 `MULTILIB_OPTIONS'. */
62 #define SUBTARGET_MULTILIB_DEFAULTS , "m32r"
64 /* Number of additional registers the subtarget defines. */
65 #define SUBTARGET_NUM_REGISTERS 1
67 /* 1 for registers that cannot be allocated. */
68 #define SUBTARGET_FIXED_REGISTERS , 1
70 /* 1 for registers that are not available across function calls. */
71 #define SUBTARGET_CALL_USED_REGISTERS , 1
73 /* Order to allocate model specific registers. */
74 #define SUBTARGET_REG_ALLOC_ORDER , 19
76 /* Registers which are accumulators. */
77 #define SUBTARGET_REG_CLASS_ACCUM 0x80000
79 /* All registers added. */
80 #define SUBTARGET_REG_CLASS_ALL SUBTARGET_REG_CLASS_ACCUM
82 /* Additional accumulator registers. */
83 #define SUBTARGET_ACCUM_P(REGNO) ((REGNO) == 19)
85 /* Define additional register names. */
86 #define SUBTARGET_REGISTER_NAMES , "a1"
87 /* end M32R/X overrides. */
89 /* Print subsidiary information on the compiler version in use. */
90 #ifndef TARGET_VERSION
91 #define TARGET_VERSION fprintf (stderr, " (m32r)")
94 /* Names to predefine in the preprocessor for this target machine. */
95 /* __M32R__ is defined by the existing compiler so we use that. */
96 #define TARGET_CPU_CPP_BUILTINS() \
99 builtin_define ("__M32R__"); \
100 builtin_define ("__m32r__"); \
101 builtin_assert ("cpu=m32r"); \
102 builtin_assert ("machine=m32r"); \
103 builtin_define (TARGET_BIG_ENDIAN \
104 ? "__BIG_ENDIAN__" : "__LITTLE_ENDIAN__"); \
108 /* This macro defines names of additional specifications to put in the specs
109 that can be used in various specifications like CC1_SPEC. Its definition
110 is an initializer with a subgrouping for each command option.
112 Each subgrouping contains a string constant, that defines the
113 specification name, and a string constant that used by the GCC driver
116 Do not define this macro if it does not need to do anything. */
118 #ifndef SUBTARGET_EXTRA_SPECS
119 #define SUBTARGET_EXTRA_SPECS
123 #define ASM_CPU_SPEC ""
127 #define CPP_CPU_SPEC ""
131 #define CC1_CPU_SPEC ""
134 #ifndef LINK_CPU_SPEC
135 #define LINK_CPU_SPEC ""
138 #ifndef STARTFILE_CPU_SPEC
139 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} crtinit.o%s"
142 #ifndef ENDFILE_CPU_SPEC
143 #define ENDFILE_CPU_SPEC "-lgloss crtfini.o%s"
147 #if 0 /* Not supported yet. */
148 #define RELAX_SPEC "%{mrelax:-relax}"
150 #define RELAX_SPEC ""
154 #define EXTRA_SPECS \
155 { "asm_cpu", ASM_CPU_SPEC }, \
156 { "cpp_cpu", CPP_CPU_SPEC }, \
157 { "cc1_cpu", CC1_CPU_SPEC }, \
158 { "link_cpu", LINK_CPU_SPEC }, \
159 { "startfile_cpu", STARTFILE_CPU_SPEC }, \
160 { "endfile_cpu", ENDFILE_CPU_SPEC }, \
161 { "relax", RELAX_SPEC }, \
162 SUBTARGET_EXTRA_SPECS
164 #define CPP_SPEC "%(cpp_cpu)"
167 #define CC1_SPEC "%{G*} %(cc1_cpu)"
169 /* Options to pass on to the assembler. */
171 #define ASM_SPEC "%{v} %(asm_cpu) %(relax) %{fpic|fpie:-K PIC} %{fPIC|fPIE:-K PIC}"
173 #define LINK_SPEC "%{v} %(link_cpu) %(relax)"
175 #undef STARTFILE_SPEC
176 #define STARTFILE_SPEC "%(startfile_cpu)"
179 #define ENDFILE_SPEC "%(endfile_cpu)"
183 /* Run-time compilation parameters selecting different hardware subsets. */
185 #define TARGET_M32R (! TARGET_M32RX && ! TARGET_M32R2)
187 #ifndef TARGET_LITTLE_ENDIAN
188 #define TARGET_LITTLE_ENDIAN 0
190 #define TARGET_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN)
192 /* This defaults us to m32r. */
193 #ifndef TARGET_CPU_DEFAULT
194 #define TARGET_CPU_DEFAULT 0
199 Code models are used to select between two choices of two separate
200 possibilities (address space size, call insn to use):
202 small: addresses use 24 bits, use bl to make calls
203 medium: addresses use 32 bits, use bl to make calls (*1)
204 large: addresses use 32 bits, use seth/add3/jl to make calls (*2)
206 The fourth is "addresses use 24 bits, use seth/add3/jl to make calls" but
207 using this one doesn't make much sense.
209 (*1) The linker may eventually be able to relax seth/add3 -> ld24.
210 (*2) The linker may eventually be able to relax seth/add3/jl -> bl.
212 Internally these are recorded as TARGET_ADDR{24,32} and
215 The __model__ attribute can be used to select the code model to use when
216 accessing particular objects. */
218 enum m32r_model { M32R_MODEL_SMALL, M32R_MODEL_MEDIUM, M32R_MODEL_LARGE };
220 extern enum m32r_model m32r_model;
221 #define TARGET_MODEL_SMALL (m32r_model == M32R_MODEL_SMALL)
222 #define TARGET_MODEL_MEDIUM (m32r_model == M32R_MODEL_MEDIUM)
223 #define TARGET_MODEL_LARGE (m32r_model == M32R_MODEL_LARGE)
224 #define TARGET_ADDR24 (m32r_model == M32R_MODEL_SMALL)
225 #define TARGET_ADDR32 (! TARGET_ADDR24)
226 #define TARGET_CALL26 (! TARGET_CALL32)
227 #define TARGET_CALL32 (m32r_model == M32R_MODEL_LARGE)
229 /* The default is the small model. */
230 #ifndef M32R_MODEL_DEFAULT
231 #define M32R_MODEL_DEFAULT M32R_MODEL_SMALL
236 The SDA consists of sections .sdata, .sbss, and .scommon.
237 .scommon isn't a real section, symbols in it have their section index
238 set to SHN_M32R_SCOMMON, though support for it exists in the linker script.
240 Two switches control the SDA:
242 -G NNN - specifies the maximum size of variable to go in the SDA
244 -msdata=foo - specifies how such variables are handled
246 -msdata=none - small data area is disabled
248 -msdata=sdata - small data goes in the SDA, special code isn't
249 generated to use it, and special relocs aren't
252 -msdata=use - small data goes in the SDA, special code is generated
253 to use the SDA and special relocs are generated
255 The SDA is not multilib'd, it isn't necessary.
256 MULTILIB_EXTRA_OPTS is set in tmake_file to -msdata=sdata so multilib'd
257 libraries have small data in .sdata/SHN_M32R_SCOMMON so programs that use
258 -msdata=use will successfully link with them (references in header files
259 will cause the compiler to emit code that refers to library objects in
260 .data). ??? There can be a problem if the user passes a -G value greater
261 than the default and a library object in a header file is that size.
262 The default is 8 so this should be rare - if it occurs the user
263 is required to rebuild the libraries or use a smaller value for -G. */
265 /* Maximum size of variables that go in .sdata/.sbss.
266 The -msdata=foo switch also controls how small variables are handled. */
267 #ifndef SDATA_DEFAULT_SIZE
268 #define SDATA_DEFAULT_SIZE 8
271 enum m32r_sdata { M32R_SDATA_NONE, M32R_SDATA_SDATA, M32R_SDATA_USE };
273 extern enum m32r_sdata m32r_sdata;
274 #define TARGET_SDATA_NONE (m32r_sdata == M32R_SDATA_NONE)
275 #define TARGET_SDATA_SDATA (m32r_sdata == M32R_SDATA_SDATA)
276 #define TARGET_SDATA_USE (m32r_sdata == M32R_SDATA_USE)
278 /* Default is to disable the SDA
279 [for upward compatibility with previous toolchains]. */
280 #ifndef M32R_SDATA_DEFAULT
281 #define M32R_SDATA_DEFAULT M32R_SDATA_NONE
284 /* Define this macro as a C expression for the initializer of an array of
285 strings to tell the driver program which options are defaults for this
286 target and thus do not need to be handled specially when using
287 `MULTILIB_OPTIONS'. */
288 #ifndef SUBTARGET_MULTILIB_DEFAULTS
289 #define SUBTARGET_MULTILIB_DEFAULTS
292 #ifndef MULTILIB_DEFAULTS
293 #define MULTILIB_DEFAULTS { "mmodel=small" SUBTARGET_MULTILIB_DEFAULTS }
296 #ifndef SUBTARGET_OVERRIDE_OPTIONS
297 #define SUBTARGET_OVERRIDE_OPTIONS
300 /* Target machine storage layout. */
302 /* Define this if most significant bit is lowest numbered
303 in instructions that operate on numbered bit-fields. */
304 #define BITS_BIG_ENDIAN 1
306 /* Define this if most significant byte of a word is the lowest numbered. */
307 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
309 /* Define this if most significant word of a multiword number is the lowest
311 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
313 /* Width of a word, in units (bytes). */
314 #define UNITS_PER_WORD 4
316 /* Define this macro if it is advisable to hold scalars in registers
317 in a wider mode than that declared by the program. In such cases,
318 the value is constrained to be within the bounds of the declared
319 type, but kept valid in the wider mode. The signedness of the
320 extension may differ from that of the type. */
321 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
322 if (GET_MODE_CLASS (MODE) == MODE_INT \
323 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
328 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
329 #define PARM_BOUNDARY 32
331 /* Boundary (in *bits*) on which stack pointer should be aligned. */
332 #define STACK_BOUNDARY 32
334 /* ALIGN FRAMES on word boundaries */
335 #define M32R_STACK_ALIGN(LOC) (((LOC) + 3) & ~ 3)
337 /* Allocation boundary (in *bits*) for the code of a function. */
338 #define FUNCTION_BOUNDARY 32
340 /* Alignment of field after `int : 0' in a structure. */
341 #define EMPTY_FIELD_BOUNDARY 32
343 /* Every structure's size must be a multiple of this. */
344 #define STRUCTURE_SIZE_BOUNDARY 8
346 /* A bit-field declared as `int' forces `int' alignment for the struct. */
347 #define PCC_BITFIELD_TYPE_MATTERS 1
349 /* No data type wants to be aligned rounder than this. */
350 #define BIGGEST_ALIGNMENT 32
352 /* The best alignment to use in cases where we have a choice. */
353 #define FASTEST_ALIGNMENT 32
355 /* Make strings word-aligned so strcpy from constants will be faster. */
356 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
357 ((TREE_CODE (EXP) == STRING_CST \
358 && (ALIGN) < FASTEST_ALIGNMENT) \
359 ? FASTEST_ALIGNMENT : (ALIGN))
361 /* Make arrays of chars word-aligned for the same reasons. */
362 #define DATA_ALIGNMENT(TYPE, ALIGN) \
363 (TREE_CODE (TYPE) == ARRAY_TYPE \
364 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
365 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
367 /* Set this nonzero if move instructions will actually fail to work
368 when given unaligned data. */
369 #define STRICT_ALIGNMENT 1
371 /* Define LAVEL_ALIGN to calculate code length of PNOP at labels. */
372 #define LABEL_ALIGN(insn) 2
374 /* Layout of source language data types. */
376 #define SHORT_TYPE_SIZE 16
377 #define INT_TYPE_SIZE 32
378 #define LONG_TYPE_SIZE 32
379 #define LONG_LONG_TYPE_SIZE 64
380 #define FLOAT_TYPE_SIZE 32
381 #define DOUBLE_TYPE_SIZE 64
382 #define LONG_DOUBLE_TYPE_SIZE 64
384 /* Define this as 1 if `char' should by default be signed; else as 0. */
385 #define DEFAULT_SIGNED_CHAR 1
387 #define SIZE_TYPE "long unsigned int"
388 #define PTRDIFF_TYPE "long int"
389 #define WCHAR_TYPE "short unsigned int"
390 #define WCHAR_TYPE_SIZE 16
392 /* Standard register usage. */
394 /* Number of actual hardware registers.
395 The hardware registers are assigned numbers for the compiler
396 from 0 to just below FIRST_PSEUDO_REGISTER.
397 All registers that the compiler knows about must be given numbers,
398 even those that are not normally considered general registers. */
400 #define M32R_NUM_REGISTERS 19
402 #ifndef SUBTARGET_NUM_REGISTERS
403 #define SUBTARGET_NUM_REGISTERS 0
406 #define FIRST_PSEUDO_REGISTER (M32R_NUM_REGISTERS + SUBTARGET_NUM_REGISTERS)
408 /* 1 for registers that have pervasive standard uses
409 and are not available for the register allocator.
411 0-3 - arguments/results
412 4-5 - call used [4 is used as a tmp during prologue/epilogue generation]
414 7 - call used, static chain pointer
416 12 - call saved [reserved for global pointer]
418 14 - subroutine link register
423 19 - accumulator 1 in the m32r/x
424 By default, the extension registers are not available. */
426 #ifndef SUBTARGET_FIXED_REGISTERS
427 #define SUBTARGET_FIXED_REGISTERS
430 #define FIXED_REGISTERS \
432 0, 0, 0, 0, 0, 0, 0, 0, \
433 0, 0, 0, 0, 0, 0, 0, 1, \
435 SUBTARGET_FIXED_REGISTERS \
438 /* 1 for registers not available across function calls.
439 These must include the FIXED_REGISTERS and also any
440 registers that can be used without being saved.
441 The latter must include the registers where values are returned
442 and the register where structure-value addresses are passed.
443 Aside from that, you can include as many other registers as you like. */
445 #ifndef SUBTARGET_CALL_USED_REGISTERS
446 #define SUBTARGET_CALL_USED_REGISTERS
449 #define CALL_USED_REGISTERS \
451 1, 1, 1, 1, 1, 1, 1, 1, \
452 0, 0, 0, 0, 0, 0, 1, 1, \
454 SUBTARGET_CALL_USED_REGISTERS \
457 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
459 /* If defined, an initializer for a vector of integers, containing the
460 numbers of hard registers in the order in which GCC should
461 prefer to use them (from most preferred to least). */
463 #ifndef SUBTARGET_REG_ALLOC_ORDER
464 #define SUBTARGET_REG_ALLOC_ORDER
467 #if 1 /* Better for int code. */
468 #define REG_ALLOC_ORDER \
470 4, 5, 6, 7, 2, 3, 8, 9, 10, \
471 11, 12, 13, 14, 0, 1, 15, 16, 17, 18 \
472 SUBTARGET_REG_ALLOC_ORDER \
475 #else /* Better for fp code at expense of int code. */
476 #define REG_ALLOC_ORDER \
478 0, 1, 2, 3, 4, 5, 6, 7, 8, \
479 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 \
480 SUBTARGET_REG_ALLOC_ORDER \
484 /* Return number of consecutive hard regs needed starting at reg REGNO
485 to hold something of mode MODE.
486 This is ordinarily the length in words of a value of mode MODE
487 but can be less for certain modes in special long registers. */
488 #define HARD_REGNO_NREGS(REGNO, MODE) \
489 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
491 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
492 extern const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER];
493 extern unsigned int m32r_mode_class[];
494 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
495 ((m32r_hard_regno_mode_ok[REGNO] & m32r_mode_class[MODE]) != 0)
497 /* A C expression that is nonzero if it is desirable to choose
498 register allocation so as to avoid move instructions between a
499 value of mode MODE1 and a value of mode MODE2.
501 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
502 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
503 MODE2)' must be zero. */
505 /* Tie QI/HI/SI modes together. */
506 #define MODES_TIEABLE_P(MODE1, MODE2) \
507 ( GET_MODE_CLASS (MODE1) == MODE_INT \
508 && GET_MODE_CLASS (MODE2) == MODE_INT \
509 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
510 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD)
512 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
513 m32r_hard_regno_rename_ok (OLD_REG, NEW_REG)
515 /* Register classes and constants. */
517 /* Define the classes of registers for register constraints in the
518 machine description. Also define ranges of constants.
520 One of the classes must always be named ALL_REGS and include all hard regs.
521 If there is more than one class, another class must be named NO_REGS
522 and contain no registers.
524 The name GENERAL_REGS must be the name of a class (or an alias for
525 another name such as ALL_REGS). This is the class of registers
526 that is allowed by "g" or "r" in a register constraint.
527 Also, registers outside this class are allocated only when
528 instructions express preferences for them.
530 The classes must be numbered in nondecreasing order; that is,
531 a larger-numbered class must never be contained completely
532 in a smaller-numbered class.
534 For any two classes, it is very desirable that there be another
535 class that represents their union.
537 It is important that any condition codes have class NO_REGS.
538 See `register_operand'. */
542 NO_REGS, CARRY_REG, ACCUM_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
545 #define IRA_COVER_CLASSES \
547 ACCUM_REGS, GENERAL_REGS, LIM_REG_CLASSES \
550 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
552 /* Give names of register classes as strings for dump file. */
553 #define REG_CLASS_NAMES \
554 { "NO_REGS", "CARRY_REG", "ACCUM_REGS", "GENERAL_REGS", "ALL_REGS" }
556 /* Define which registers fit in which classes.
557 This is an initializer for a vector of HARD_REG_SET
558 of length N_REG_CLASSES. */
560 #ifndef SUBTARGET_REG_CLASS_CARRY
561 #define SUBTARGET_REG_CLASS_CARRY 0
564 #ifndef SUBTARGET_REG_CLASS_ACCUM
565 #define SUBTARGET_REG_CLASS_ACCUM 0
568 #ifndef SUBTARGET_REG_CLASS_GENERAL
569 #define SUBTARGET_REG_CLASS_GENERAL 0
572 #ifndef SUBTARGET_REG_CLASS_ALL
573 #define SUBTARGET_REG_CLASS_ALL 0
576 #define REG_CLASS_CONTENTS \
579 { 0x20000 | SUBTARGET_REG_CLASS_CARRY }, \
580 { 0x40000 | SUBTARGET_REG_CLASS_ACCUM }, \
581 { 0x1ffff | SUBTARGET_REG_CLASS_GENERAL }, \
582 { 0x7ffff | SUBTARGET_REG_CLASS_ALL }, \
585 /* The same information, inverted:
586 Return the class number of the smallest class containing
587 reg number REGNO. This could be a conditional expression
588 or could index an array. */
589 extern enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
590 #define REGNO_REG_CLASS(REGNO) (m32r_regno_reg_class[REGNO])
592 /* The class value for index registers, and the one for base regs. */
593 #define INDEX_REG_CLASS GENERAL_REGS
594 #define BASE_REG_CLASS GENERAL_REGS
596 /* These assume that REGNO is a hard or pseudo reg number.
597 They give nonzero only if REGNO is a hard reg of the suitable class
598 or a pseudo reg currently allocated to a suitable hard reg.
599 Since they use reg_renumber, they are safe only once reg_renumber
600 has been allocated, which happens in local-alloc.c. */
601 #define REGNO_OK_FOR_BASE_P(REGNO) \
602 ((REGNO) < FIRST_PSEUDO_REGISTER \
603 ? GPR_P (REGNO) || (REGNO) == ARG_POINTER_REGNUM \
604 : GPR_P (reg_renumber[REGNO]))
606 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
608 /* Return the maximum number of consecutive registers
609 needed to represent mode MODE in a register of class CLASS. */
610 #define CLASS_MAX_NREGS(CLASS, MODE) \
611 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
613 /* Return true if a value is inside a range. */
614 #define IN_RANGE_P(VALUE, LOW, HIGH) \
615 (((unsigned HOST_WIDE_INT)((VALUE) - (LOW))) \
616 <= ((unsigned HOST_WIDE_INT)((HIGH) - (LOW))))
618 /* Some range macros. */
619 #define INT16_P(X) ((X) >= - 0x8000 && (X) <= 0x7fff)
620 #define CMP_INT16_P(X) ((X) >= - 0x7fff && (X) <= 0x8000)
621 #define UINT16_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x0000ffff)
622 #define UINT24_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x00ffffff)
624 /* Stack layout and stack pointer usage. */
626 /* Define this macro if pushing a word onto the stack moves the stack
627 pointer to a smaller address. */
628 #define STACK_GROWS_DOWNWARD
630 /* Offset from frame pointer to start allocating local variables at.
631 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
632 first local allocated. Otherwise, it is the offset to the BEGINNING
633 of the first local allocated. */
634 /* The frame pointer points at the same place as the stack pointer, except if
635 alloca has been called. */
636 #define STARTING_FRAME_OFFSET \
637 M32R_STACK_ALIGN (crtl->outgoing_args_size)
639 /* Offset from the stack pointer register to the first location at which
640 outgoing arguments are placed. */
641 #define STACK_POINTER_OFFSET 0
643 /* Offset of first parameter from the argument pointer register value. */
644 #define FIRST_PARM_OFFSET(FNDECL) 0
646 /* Register to use for pushing function arguments. */
647 #define STACK_POINTER_REGNUM 15
649 /* Base register for access to local variables of the function. */
650 #define FRAME_POINTER_REGNUM 13
652 /* Base register for access to arguments of the function. */
653 #define ARG_POINTER_REGNUM 16
655 /* Register in which static-chain is passed to a function.
656 This must not be a register used by the prologue. */
657 #define STATIC_CHAIN_REGNUM 7
659 /* These aren't official macros. */
660 #define PROLOGUE_TMP_REGNUM 4
661 #define RETURN_ADDR_REGNUM 14
662 /* #define GP_REGNUM 12 */
663 #define CARRY_REGNUM 17
664 #define ACCUM_REGNUM 18
665 #define M32R_MAX_INT_REGS 16
667 #ifndef SUBTARGET_GPR_P
668 #define SUBTARGET_GPR_P(REGNO) 0
671 #ifndef SUBTARGET_ACCUM_P
672 #define SUBTARGET_ACCUM_P(REGNO) 0
675 #ifndef SUBTARGET_CARRY_P
676 #define SUBTARGET_CARRY_P(REGNO) 0
679 #define GPR_P(REGNO) (IN_RANGE_P ((REGNO), 0, 15) || SUBTARGET_GPR_P (REGNO))
680 #define ACCUM_P(REGNO) ((REGNO) == ACCUM_REGNUM || SUBTARGET_ACCUM_P (REGNO))
681 #define CARRY_P(REGNO) ((REGNO) == CARRY_REGNUM || SUBTARGET_CARRY_P (REGNO))
683 /* Eliminating the frame and arg pointers. */
686 /* C statement to store the difference between the frame pointer
687 and the stack pointer values immediately after the function prologue.
688 If `ELIMINABLE_REGS' is defined, this macro will be not be used and
689 need not be defined. */
690 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
691 ((VAR) = m32r_compute_frame_size (get_frame_size ()))
694 /* If defined, this macro specifies a table of register pairs used to
695 eliminate unneeded registers that point into the stack frame. If
696 it is not defined, the only elimination attempted by the compiler
697 is to replace references to the frame pointer with references to
700 Note that the elimination of the argument pointer with the stack
701 pointer is specified first since that is the preferred elimination. */
703 #define ELIMINABLE_REGS \
704 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
705 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
706 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }}
708 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
709 specifies the initial difference between the specified pair of
710 registers. This macro must be defined if `ELIMINABLE_REGS' is
713 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
716 int size = m32r_compute_frame_size (get_frame_size ()); \
718 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
720 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
721 (OFFSET) = size - crtl->args.pretend_args_size; \
722 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
723 (OFFSET) = size - crtl->args.pretend_args_size; \
725 gcc_unreachable (); \
729 /* Function argument passing. */
731 /* If defined, the maximum amount of space required for outgoing
732 arguments will be computed and placed into the variable
733 `crtl->outgoing_args_size'. No space will be pushed
734 onto the stack for each call; instead, the function prologue should
735 increase the stack frame size by this amount. */
736 #define ACCUMULATE_OUTGOING_ARGS 1
738 /* Define a data type for recording info about an argument list
739 during the scan of that argument list. This data type should
740 hold all necessary information about the function itself
741 and about the args processed so far, enough to enable macros
742 such as FUNCTION_ARG to determine where the next arg should go. */
743 #define CUMULATIVE_ARGS int
745 /* Initialize a variable CUM of type CUMULATIVE_ARGS
746 for a call to a function whose data type is FNTYPE.
747 For a library call, FNTYPE is 0. */
748 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
751 /* The number of registers used for parameter passing. Local to this file. */
752 #define M32R_MAX_PARM_REGS 4
754 /* 1 if N is a possible register number for function argument passing. */
755 #define FUNCTION_ARG_REGNO_P(N) \
756 ((unsigned) (N) < M32R_MAX_PARM_REGS)
759 /* Function results. */
761 /* Tell GCC to use TARGET_RETURN_IN_MEMORY. */
762 #define DEFAULT_PCC_STRUCT_RETURN 0
764 /* Function entry and exit. */
766 /* Initialize data used by insn expanders. This is called from
767 init_emit, once for each function, before code is generated. */
768 #define INIT_EXPANDERS m32r_init_expanders ()
770 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
771 the stack pointer does not matter. The value is tested only in
772 functions that have frame pointers.
773 No definition is equivalent to always zero. */
774 #define EXIT_IGNORE_STACK 1
776 /* Output assembler code to FILE to increment profiler label # LABELNO
777 for profiling a function entry. */
778 #undef FUNCTION_PROFILER
779 #define FUNCTION_PROFILER(FILE, LABELNO) \
784 fprintf (FILE, "\tld24 r14,#mcount\n"); \
785 fprintf (FILE, "\tadd r14,r12\n"); \
786 fprintf (FILE, "\tld r14,@r14\n"); \
787 fprintf (FILE, "\tjl r14\n"); \
792 fprintf (FILE, "\tbl mcount\n"); \
795 fprintf (FILE, "\tseth r14,#high(mcount)\n"); \
796 fprintf (FILE, "\tor3 r14,r14,#low(mcount)\n"); \
797 fprintf (FILE, "\tjl r14\n"); \
800 fprintf (FILE, "\taddi sp,#4\n"); \
806 /* On the M32R, the trampoline is:
808 mv r7, lr -> bl L1 ; 178e 7e01
809 L1: add3 r6, lr, #L2-L1 ; 86ae 000c (L2 - L1 = 12)
810 mv lr, r7 -> ld r7,@r6+ ; 1e87 27e6
811 ld r6, @r6 -> jmp r6 ; 26c6 1fc6
815 #ifndef CACHE_FLUSH_FUNC
816 #define CACHE_FLUSH_FUNC "_flush_cache"
818 #ifndef CACHE_FLUSH_TRAP
819 #define CACHE_FLUSH_TRAP 12
822 /* Length in bytes of the trampoline for entering a nested function. */
823 #define TRAMPOLINE_SIZE 24
826 #define RETURN_ADDR_RTX(COUNT, FRAME) m32r_return_addr (COUNT)
828 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)
830 /* Addressing modes, and classification of registers for them. */
832 /* Maximum number of registers that can appear in a valid memory address. */
833 #define MAX_REGS_PER_ADDRESS 1
835 /* We have post-inc load and pre-dec,pre-inc store,
836 but only for 4 byte vals. */
837 #define HAVE_PRE_DECREMENT 1
838 #define HAVE_PRE_INCREMENT 1
839 #define HAVE_POST_INCREMENT 1
841 /* Recognize any constant value that is a valid address. */
842 #define CONSTANT_ADDRESS_P(X) \
843 ( GET_CODE (X) == LABEL_REF \
844 || GET_CODE (X) == SYMBOL_REF \
846 || (GET_CODE (X) == CONST \
847 && ! (flag_pic && ! m32r_legitimate_pic_operand_p (X))))
849 /* Nonzero if the constant value X is a legitimate general operand.
850 We don't allow (plus symbol large-constant) as the relocations can't
851 describe it. INTVAL > 32767 handles both 16-bit and 24-bit relocations.
852 We allow all CONST_DOUBLE's as the md file patterns will force the
853 constant to memory if they can't handle them. */
855 #define LEGITIMATE_CONSTANT_P(X) \
856 (! (GET_CODE (X) == CONST \
857 && GET_CODE (XEXP (X, 0)) == PLUS \
858 && (GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF || GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF) \
859 && CONST_INT_P (XEXP (XEXP (X, 0), 1)) \
860 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (X, 0), 1)) > 32767))
862 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
863 and check its validity for a certain class.
864 We have two alternate definitions for each of them.
865 The usual definition accepts all pseudo regs; the other rejects
866 them unless they have been allocated suitable hard regs.
867 The symbol REG_OK_STRICT causes the latter definition to be used.
869 Most source files want to accept pseudo regs in the hope that
870 they will get allocated to the class that the insn wants them to be in.
871 Source files for reload pass need to be strict.
872 After reload, it makes no difference, since pseudo regs have
873 been eliminated by then. */
877 /* Nonzero if X is a hard reg that can be used as a base reg. */
878 #define REG_OK_FOR_BASE_P(X) GPR_P (REGNO (X))
879 /* Nonzero if X is a hard reg that can be used as an index. */
880 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
884 /* Nonzero if X is a hard reg that can be used as a base reg
885 or if it is a pseudo reg. */
886 #define REG_OK_FOR_BASE_P(X) \
888 || (REGNO (X)) == ARG_POINTER_REGNUM \
889 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
890 /* Nonzero if X is a hard reg that can be used as an index
891 or if it is a pseudo reg. */
892 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
896 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
897 that is a valid memory address for an instruction.
898 The MODE argument is the machine mode for the MEM expression
899 that wants to use this address. */
901 /* Local to this file. */
902 #define RTX_OK_FOR_BASE_P(X) (REG_P (X) && REG_OK_FOR_BASE_P (X))
904 /* Local to this file. */
905 #define RTX_OK_FOR_OFFSET_P(X) \
906 (CONST_INT_P (X) && INT16_P (INTVAL (X)))
908 /* Local to this file. */
909 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X) \
910 (GET_CODE (X) == PLUS \
911 && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \
912 && RTX_OK_FOR_OFFSET_P (XEXP (X, 1)))
914 /* Local to this file. */
915 /* For LO_SUM addresses, do not allow them if the MODE is > 1 word,
916 since more than one instruction will be required. */
917 #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X) \
918 (GET_CODE (X) == LO_SUM \
919 && (MODE != BLKmode && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)\
920 && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \
921 && CONSTANT_P (XEXP (X, 1)))
923 /* Local to this file. */
924 /* Is this a load and increment operation. */
925 #define LOAD_POSTINC_P(MODE, X) \
926 (((MODE) == SImode || (MODE) == SFmode) \
927 && GET_CODE (X) == POST_INC \
928 && REG_P (XEXP (X, 0)) \
929 && RTX_OK_FOR_BASE_P (XEXP (X, 0)))
931 /* Local to this file. */
932 /* Is this an increment/decrement and store operation. */
933 #define STORE_PREINC_PREDEC_P(MODE, X) \
934 (((MODE) == SImode || (MODE) == SFmode) \
935 && (GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC) \
936 && REG_P (XEXP (X, 0)) \
937 && RTX_OK_FOR_BASE_P (XEXP (X, 0)))
939 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
942 if (RTX_OK_FOR_BASE_P (X)) \
944 if (LEGITIMATE_OFFSET_ADDRESS_P ((MODE), (X))) \
946 if (LEGITIMATE_LO_SUM_ADDRESS_P ((MODE), (X))) \
948 if (LOAD_POSTINC_P ((MODE), (X))) \
950 if (STORE_PREINC_PREDEC_P ((MODE), (X))) \
955 /* Condition code usage. */
957 /* Return nonzero if SELECT_CC_MODE will never return MODE for a
958 floating point inequality comparison. */
959 #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/
963 /* The cost of a branch insn. */
964 /* A value of 2 here causes GCC to avoid using branches in comparisons like
965 while (a < N && a). Branches aren't that expensive on the M32R so
966 we define this as 1. Defining it as 2 had a heavy hit in fp-bit.c. */
967 #define BRANCH_COST(speed_p, predictable_p) ((TARGET_BRANCH_COST) ? 2 : 1)
969 /* Nonzero if access to memory by bytes is slow and undesirable.
970 For RISC chips, it means that access to memory by bytes is no
971 better than access by words when possible, so grab a whole word
972 and maybe make use of that. */
973 #define SLOW_BYTE_ACCESS 1
975 /* Define this macro if it is as good or better to call a constant
976 function address than to call an address kept in a register. */
977 #define NO_FUNCTION_CSE
979 /* Section selection. */
981 #define TEXT_SECTION_ASM_OP "\t.section .text"
982 #define DATA_SECTION_ASM_OP "\t.section .data"
983 #define BSS_SECTION_ASM_OP "\t.section .bss"
985 /* Define this macro if jump tables (for tablejump insns) should be
986 output in the text section, along with the assembler instructions.
987 Otherwise, the readonly data section is used.
988 This macro is irrelevant if there is no separate readonly data section. */
989 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
991 /* Position Independent Code. */
993 /* The register number of the register used to address a table of static
994 data addresses in memory. In some cases this register is defined by a
995 processor's ``application binary interface'' (ABI). When this macro
996 is defined, RTL is generated for this register once, as with the stack
997 pointer and frame pointer registers. If this macro is not defined, it
998 is up to the machine-dependent files to allocate such a register (if
1000 #define PIC_OFFSET_TABLE_REGNUM 12
1002 /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is
1003 clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM
1005 /* This register is call-saved on the M32R. */
1006 /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/
1008 /* A C expression that is nonzero if X is a legitimate immediate
1009 operand on the target machine when generating position independent code.
1010 You can assume that X satisfies CONSTANT_P, so you need not
1011 check this. You can also assume `flag_pic' is true, so you need not
1012 check it either. You need not define this macro if all constants
1013 (including SYMBOL_REF) can be immediate operands when generating
1014 position independent code. */
1015 #define LEGITIMATE_PIC_OPERAND_P(X) m32r_legitimate_pic_operand_p (X)
1017 /* Control the assembler format that we output. */
1019 /* A C string constant describing how to begin a comment in the target
1020 assembler language. The compiler assumes that the comment will
1021 end at the end of the line. */
1022 #define ASM_COMMENT_START ";"
1024 /* Output to assembler file text saying following lines
1025 may contain character constants, extra white space, comments, etc. */
1026 #define ASM_APP_ON ""
1028 /* Output to assembler file text saying following lines
1029 no longer contain unusual constructs. */
1030 #define ASM_APP_OFF ""
1032 /* Globalizing directive for a label. */
1033 #define GLOBAL_ASM_OP "\t.global\t"
1035 /* We do not use DBX_LINES_FUNCTION_RELATIVE or
1036 dbxout_stab_value_internal_label_diff here because
1037 we need to use .debugsym for the line label. */
1039 #define DBX_OUTPUT_SOURCE_LINE(file, line, counter) \
1042 const char * begin_label = \
1043 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); \
1045 ASM_GENERATE_INTERNAL_LABEL (label, "LM", counter); \
1047 dbxout_begin_stabn_sline (line); \
1048 assemble_name (file, label); \
1050 assemble_name (file, begin_label); \
1051 fputs ("\n\t.debugsym ", file); \
1052 assemble_name (file, label); \
1053 putc ('\n', file); \
1058 /* How to refer to registers in assembler output.
1059 This sequence is indexed by compiler's hard-register-number (see above). */
1060 #ifndef SUBTARGET_REGISTER_NAMES
1061 #define SUBTARGET_REGISTER_NAMES
1064 #define REGISTER_NAMES \
1066 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1067 "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", \
1068 "ap", "cbit", "a0" \
1069 SUBTARGET_REGISTER_NAMES \
1072 /* If defined, a C initializer for an array of structures containing
1073 a name and a register number. This macro defines additional names
1074 for hard registers, thus allowing the `asm' option in declarations
1075 to refer to registers using alternate names. */
1076 #ifndef SUBTARGET_ADDITIONAL_REGISTER_NAMES
1077 #define SUBTARGET_ADDITIONAL_REGISTER_NAMES
1080 #define ADDITIONAL_REGISTER_NAMES \
1082 /*{ "gp", GP_REGNUM },*/ \
1083 { "r13", FRAME_POINTER_REGNUM }, \
1084 { "r14", RETURN_ADDR_REGNUM }, \
1085 { "r15", STACK_POINTER_REGNUM }, \
1086 SUBTARGET_ADDITIONAL_REGISTER_NAMES \
1089 /* If defined, C string expressions to be used for the `%R', `%L',
1090 `%U', and `%I' options of `asm_fprintf' (see `final.c'). These
1091 are useful when a single `md' file must support multiple assembler
1092 formats. In that case, the various `tm.h' files can define these
1093 macros differently. */
1094 #define REGISTER_PREFIX ""
1095 #define LOCAL_LABEL_PREFIX ".L"
1096 #define USER_LABEL_PREFIX ""
1097 #define IMMEDIATE_PREFIX "#"
1099 /* This is how to output an element of a case-vector that is absolute. */
1100 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1104 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1105 fprintf (FILE, "\t.word\t"); \
1106 assemble_name (FILE, label); \
1107 fprintf (FILE, "\n"); \
1111 /* This is how to output an element of a case-vector that is relative. */
1112 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)\
1116 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1117 fprintf (FILE, "\t.word\t"); \
1118 assemble_name (FILE, label); \
1119 fprintf (FILE, "-"); \
1120 ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \
1121 assemble_name (FILE, label); \
1122 fprintf (FILE, "\n"); \
1126 /* The desired alignment for the location counter at the beginning
1128 /* On the M32R, align loops to 32 byte boundaries (cache line size)
1129 if -malign-loops. */
1130 #define LOOP_ALIGN(LABEL) (TARGET_ALIGN_LOOPS ? 5 : 0)
1132 /* Define this to be the maximum number of insns to move around when moving
1133 a loop test from the top of a loop to the bottom
1134 and seeing whether to duplicate it. The default is thirty.
1136 Loop unrolling currently doesn't like this optimization, so
1137 disable doing if we are unrolling loops and saving space. */
1138 #define LOOP_TEST_THRESHOLD (optimize_size \
1139 && !flag_unroll_loops \
1140 && !flag_unroll_all_loops ? 2 : 30)
1142 /* This is how to output an assembler line
1143 that says to advance the location counter
1144 to a multiple of 2**LOG bytes. */
1145 /* .balign is used to avoid confusion. */
1146 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1150 fprintf (FILE, "\t.balign %d\n", 1 << (LOG)); \
1154 /* Like `ASM_OUTPUT_COMMON' except takes the required alignment as a
1155 separate, explicit argument. If you define this macro, it is used in
1156 place of `ASM_OUTPUT_COMMON', and gives you more flexibility in
1157 handling the required alignment of the variable. The alignment is
1158 specified as the number of bits. */
1160 #define SCOMMON_ASM_OP "\t.scomm\t"
1162 #undef ASM_OUTPUT_ALIGNED_COMMON
1163 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
1166 if (! TARGET_SDATA_NONE \
1168 && (SIZE) <= (unsigned HOST_WIDE_INT) g_switch_value) \
1169 fprintf ((FILE), "%s", SCOMMON_ASM_OP); \
1171 fprintf ((FILE), "%s", COMMON_ASM_OP); \
1172 assemble_name ((FILE), (NAME)); \
1173 fprintf ((FILE), ",%u,%u\n", (int)(SIZE), (ALIGN) / BITS_PER_UNIT);\
1177 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1180 if (! TARGET_SDATA_NONE \
1182 && (SIZE) <= (unsigned HOST_WIDE_INT) g_switch_value) \
1183 switch_to_section (get_named_section (NULL, ".sbss", 0)); \
1185 switch_to_section (bss_section); \
1186 ASM_OUTPUT_ALIGN (FILE, floor_log2 (ALIGN / BITS_PER_UNIT)); \
1187 last_assemble_variable_decl = DECL; \
1188 ASM_DECLARE_OBJECT_NAME (FILE, NAME, DECL); \
1189 ASM_OUTPUT_SKIP (FILE, SIZE ? SIZE : 1); \
1193 /* Debugging information. */
1195 /* Generate DBX and DWARF debugging information. */
1196 #define DBX_DEBUGGING_INFO 1
1197 #define DWARF2_DEBUGGING_INFO 1
1199 /* Use DWARF2 debugging info by default. */
1200 #undef PREFERRED_DEBUGGING_TYPE
1201 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1203 /* Turn off splitting of long stabs. */
1204 #define DBX_CONTIN_LENGTH 0
1206 /* Miscellaneous. */
1208 /* Specify the machine mode that this machine uses
1209 for the index in the tablejump instruction. */
1210 #define CASE_VECTOR_MODE (flag_pic ? SImode : Pmode)
1212 /* Define if operations between registers always perform the operation
1213 on the full register even if a narrower mode is specified. */
1214 #define WORD_REGISTER_OPERATIONS
1216 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1217 will either zero-extend or sign-extend. The value of this macro should
1218 be the code that says which one of the two operations is implicitly
1219 done, UNKNOWN if none. */
1220 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1222 /* Max number of bytes we can move from memory
1223 to memory in one reasonably fast instruction. */
1226 /* Define this to be nonzero if shift instructions ignore all but the low-order
1228 #define SHIFT_COUNT_TRUNCATED 1
1230 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1231 is done just by pretending it is already truncated. */
1232 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1234 /* Specify the machine mode that pointers have.
1235 After generation of rtl, the compiler makes no further distinction
1236 between pointers and any other objects of this machine mode. */
1237 /* ??? The M32R doesn't have full 32-bit pointers, but making this PSImode has
1238 its own problems (you have to add extendpsisi2 and truncsipsi2).
1240 #define Pmode SImode
1242 /* A function address in a call instruction. */
1243 #define FUNCTION_MODE SImode
1245 /* M32R function types. */
1246 enum m32r_function_type
1248 M32R_FUNCTION_UNKNOWN, M32R_FUNCTION_NORMAL, M32R_FUNCTION_INTERRUPT
1251 #define M32R_INTERRUPT_P(TYPE) ((TYPE) == M32R_FUNCTION_INTERRUPT)
1253 /* The maximum number of bytes to copy using pairs of load/store instructions.
1254 If a block is larger than this then a loop will be generated to copy
1255 MAX_MOVE_BYTES chunks at a time. The value of 32 is a semi-arbitrary choice.
1256 A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte
1257 string copy in it. */
1258 #define MAX_MOVE_BYTES 32
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