1 /* Definitions of target machine for GNU compiler, Renesas M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
3 2005, 2006, 2007 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
25 #undef SWITCH_TAKES_ARG
26 #undef WORD_SWITCH_TAKES_ARG
27 #undef HANDLE_SYSV_PRAGMA
31 #undef WCHAR_TYPE_SIZE
43 /* M32R/X overrides. */
44 /* Print subsidiary information on the compiler version in use. */
45 #define TARGET_VERSION fprintf (stderr, " (m32r/x/2)");
47 /* Additional flags for the preprocessor. */
48 #define CPP_CPU_SPEC "%{m32rx:-D__M32RX__ -D__m32rx__ -U__M32R2__ -U__m32r2__} \
49 %{m32r2:-D__M32R2__ -D__m32r2__ -U__M32RX__ -U__m32rx__} \
50 %{m32r:-U__M32RX__ -U__m32rx__ -U__M32R2__ -U__m32r2__} \
53 /* Assembler switches. */
54 #define ASM_CPU_SPEC \
55 "%{m32r} %{m32rx} %{m32r2} %{!O0: %{O*: -O}} --no-warn-explicit-parallel-conflicts"
57 /* Use m32rx specific crt0/crtinit/crtfini files. */
58 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} %{m32rx:m32rx/crtinit.o%s} %{!m32rx:crtinit.o%s}"
59 #define ENDFILE_CPU_SPEC "-lgloss %{m32rx:m32rx/crtfini.o%s} %{!m32rx:crtfini.o%s}"
61 /* Define this macro as a C expression for the initializer of an array of
62 strings to tell the driver program which options are defaults for this
63 target and thus do not need to be handled specially when using
64 `MULTILIB_OPTIONS'. */
65 #define SUBTARGET_MULTILIB_DEFAULTS , "m32r"
67 /* Number of additional registers the subtarget defines. */
68 #define SUBTARGET_NUM_REGISTERS 1
70 /* 1 for registers that cannot be allocated. */
71 #define SUBTARGET_FIXED_REGISTERS , 1
73 /* 1 for registers that are not available across function calls. */
74 #define SUBTARGET_CALL_USED_REGISTERS , 1
76 /* Order to allocate model specific registers. */
77 #define SUBTARGET_REG_ALLOC_ORDER , 19
79 /* Registers which are accumulators. */
80 #define SUBTARGET_REG_CLASS_ACCUM 0x80000
82 /* All registers added. */
83 #define SUBTARGET_REG_CLASS_ALL SUBTARGET_REG_CLASS_ACCUM
85 /* Additional accumulator registers. */
86 #define SUBTARGET_ACCUM_P(REGNO) ((REGNO) == 19)
88 /* Define additional register names. */
89 #define SUBTARGET_REGISTER_NAMES , "a1"
90 /* end M32R/X overrides. */
92 /* Print subsidiary information on the compiler version in use. */
93 #ifndef TARGET_VERSION
94 #define TARGET_VERSION fprintf (stderr, " (m32r)")
97 /* Switch Recognition by gcc.c. Add -G xx support. */
99 #undef SWITCH_TAKES_ARG
100 #define SWITCH_TAKES_ARG(CHAR) \
101 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
103 /* Names to predefine in the preprocessor for this target machine. */
104 /* __M32R__ is defined by the existing compiler so we use that. */
105 #define TARGET_CPU_CPP_BUILTINS() \
108 builtin_define ("__M32R__"); \
109 builtin_define ("__m32r__"); \
110 builtin_assert ("cpu=m32r"); \
111 builtin_assert ("machine=m32r"); \
112 builtin_define (TARGET_BIG_ENDIAN \
113 ? "__BIG_ENDIAN__" : "__LITTLE_ENDIAN__"); \
117 /* This macro defines names of additional specifications to put in the specs
118 that can be used in various specifications like CC1_SPEC. Its definition
119 is an initializer with a subgrouping for each command option.
121 Each subgrouping contains a string constant, that defines the
122 specification name, and a string constant that used by the GCC driver
125 Do not define this macro if it does not need to do anything. */
127 #ifndef SUBTARGET_EXTRA_SPECS
128 #define SUBTARGET_EXTRA_SPECS
132 #define ASM_CPU_SPEC ""
136 #define CPP_CPU_SPEC ""
140 #define CC1_CPU_SPEC ""
143 #ifndef LINK_CPU_SPEC
144 #define LINK_CPU_SPEC ""
147 #ifndef STARTFILE_CPU_SPEC
148 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} crtinit.o%s"
151 #ifndef ENDFILE_CPU_SPEC
152 #define ENDFILE_CPU_SPEC "-lgloss crtfini.o%s"
156 #if 0 /* Not supported yet. */
157 #define RELAX_SPEC "%{mrelax:-relax}"
159 #define RELAX_SPEC ""
163 #define EXTRA_SPECS \
164 { "asm_cpu", ASM_CPU_SPEC }, \
165 { "cpp_cpu", CPP_CPU_SPEC }, \
166 { "cc1_cpu", CC1_CPU_SPEC }, \
167 { "link_cpu", LINK_CPU_SPEC }, \
168 { "startfile_cpu", STARTFILE_CPU_SPEC }, \
169 { "endfile_cpu", ENDFILE_CPU_SPEC }, \
170 { "relax", RELAX_SPEC }, \
171 SUBTARGET_EXTRA_SPECS
173 #define CPP_SPEC "%(cpp_cpu)"
176 #define CC1_SPEC "%{G*} %(cc1_cpu)"
178 /* Options to pass on to the assembler. */
180 #define ASM_SPEC "%{v} %(asm_cpu) %(relax) %{fpic|fpie:-K PIC} %{fPIC|fPIE:-K PIC}"
182 #define LINK_SPEC "%{v} %(link_cpu) %(relax)"
184 #undef STARTFILE_SPEC
185 #define STARTFILE_SPEC "%(startfile_cpu)"
188 #define ENDFILE_SPEC "%(endfile_cpu)"
192 /* Run-time compilation parameters selecting different hardware subsets. */
194 #define TARGET_M32R (! TARGET_M32RX && ! TARGET_M32R2)
196 #ifndef TARGET_LITTLE_ENDIAN
197 #define TARGET_LITTLE_ENDIAN 0
199 #define TARGET_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN)
201 /* This defaults us to m32r. */
202 #ifndef TARGET_CPU_DEFAULT
203 #define TARGET_CPU_DEFAULT 0
208 Code models are used to select between two choices of two separate
209 possibilities (address space size, call insn to use):
211 small: addresses use 24 bits, use bl to make calls
212 medium: addresses use 32 bits, use bl to make calls (*1)
213 large: addresses use 32 bits, use seth/add3/jl to make calls (*2)
215 The fourth is "addresses use 24 bits, use seth/add3/jl to make calls" but
216 using this one doesn't make much sense.
218 (*1) The linker may eventually be able to relax seth/add3 -> ld24.
219 (*2) The linker may eventually be able to relax seth/add3/jl -> bl.
221 Internally these are recorded as TARGET_ADDR{24,32} and
224 The __model__ attribute can be used to select the code model to use when
225 accessing particular objects. */
227 enum m32r_model { M32R_MODEL_SMALL, M32R_MODEL_MEDIUM, M32R_MODEL_LARGE };
229 extern enum m32r_model m32r_model;
230 #define TARGET_MODEL_SMALL (m32r_model == M32R_MODEL_SMALL)
231 #define TARGET_MODEL_MEDIUM (m32r_model == M32R_MODEL_MEDIUM)
232 #define TARGET_MODEL_LARGE (m32r_model == M32R_MODEL_LARGE)
233 #define TARGET_ADDR24 (m32r_model == M32R_MODEL_SMALL)
234 #define TARGET_ADDR32 (! TARGET_ADDR24)
235 #define TARGET_CALL26 (! TARGET_CALL32)
236 #define TARGET_CALL32 (m32r_model == M32R_MODEL_LARGE)
238 /* The default is the small model. */
239 #ifndef M32R_MODEL_DEFAULT
240 #define M32R_MODEL_DEFAULT M32R_MODEL_SMALL
245 The SDA consists of sections .sdata, .sbss, and .scommon.
246 .scommon isn't a real section, symbols in it have their section index
247 set to SHN_M32R_SCOMMON, though support for it exists in the linker script.
249 Two switches control the SDA:
251 -G NNN - specifies the maximum size of variable to go in the SDA
253 -msdata=foo - specifies how such variables are handled
255 -msdata=none - small data area is disabled
257 -msdata=sdata - small data goes in the SDA, special code isn't
258 generated to use it, and special relocs aren't
261 -msdata=use - small data goes in the SDA, special code is generated
262 to use the SDA and special relocs are generated
264 The SDA is not multilib'd, it isn't necessary.
265 MULTILIB_EXTRA_OPTS is set in tmake_file to -msdata=sdata so multilib'd
266 libraries have small data in .sdata/SHN_M32R_SCOMMON so programs that use
267 -msdata=use will successfully link with them (references in header files
268 will cause the compiler to emit code that refers to library objects in
269 .data). ??? There can be a problem if the user passes a -G value greater
270 than the default and a library object in a header file is that size.
271 The default is 8 so this should be rare - if it occurs the user
272 is required to rebuild the libraries or use a smaller value for -G. */
274 /* Maximum size of variables that go in .sdata/.sbss.
275 The -msdata=foo switch also controls how small variables are handled. */
276 #ifndef SDATA_DEFAULT_SIZE
277 #define SDATA_DEFAULT_SIZE 8
280 enum m32r_sdata { M32R_SDATA_NONE, M32R_SDATA_SDATA, M32R_SDATA_USE };
282 extern enum m32r_sdata m32r_sdata;
283 #define TARGET_SDATA_NONE (m32r_sdata == M32R_SDATA_NONE)
284 #define TARGET_SDATA_SDATA (m32r_sdata == M32R_SDATA_SDATA)
285 #define TARGET_SDATA_USE (m32r_sdata == M32R_SDATA_USE)
287 /* Default is to disable the SDA
288 [for upward compatibility with previous toolchains]. */
289 #ifndef M32R_SDATA_DEFAULT
290 #define M32R_SDATA_DEFAULT M32R_SDATA_NONE
293 /* Define this macro as a C expression for the initializer of an array of
294 strings to tell the driver program which options are defaults for this
295 target and thus do not need to be handled specially when using
296 `MULTILIB_OPTIONS'. */
297 #ifndef SUBTARGET_MULTILIB_DEFAULTS
298 #define SUBTARGET_MULTILIB_DEFAULTS
301 #ifndef MULTILIB_DEFAULTS
302 #define MULTILIB_DEFAULTS { "mmodel=small" SUBTARGET_MULTILIB_DEFAULTS }
305 /* Sometimes certain combinations of command options do not make
306 sense on a particular target machine. You can define a macro
307 `OVERRIDE_OPTIONS' to take account of this. This macro, if
308 defined, is executed once just after all the command options have
311 Don't use this macro to turn on various extra optimizations for
312 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
314 #ifndef SUBTARGET_OVERRIDE_OPTIONS
315 #define SUBTARGET_OVERRIDE_OPTIONS
318 #define OVERRIDE_OPTIONS \
321 /* These need to be done at start up. \
322 It's convenient to do them here. */ \
324 SUBTARGET_OVERRIDE_OPTIONS \
328 #ifndef SUBTARGET_OPTIMIZATION_OPTIONS
329 #define SUBTARGET_OPTIMIZATION_OPTIONS
332 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
336 flag_regmove = TRUE; \
340 flag_omit_frame_pointer = TRUE; \
343 SUBTARGET_OPTIMIZATION_OPTIONS \
347 /* Define this macro if debugging can be performed even without a
348 frame pointer. If this macro is defined, GCC will turn on the
349 `-fomit-frame-pointer' option whenever `-O' is specified. */
350 #define CAN_DEBUG_WITHOUT_FP
352 /* Target machine storage layout. */
354 /* Define this if most significant bit is lowest numbered
355 in instructions that operate on numbered bit-fields. */
356 #define BITS_BIG_ENDIAN 1
358 /* Define this if most significant byte of a word is the lowest numbered. */
359 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
361 /* Define this if most significant word of a multiword number is the lowest
363 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
365 /* Define this macro if WORDS_BIG_ENDIAN is not constant. This must
366 be a constant value with the same meaning as WORDS_BIG_ENDIAN,
367 which will be used only when compiling libgcc2.c. Typically the
368 value will be set based on preprocessor defines. */
369 /*#define LIBGCC2_WORDS_BIG_ENDIAN 1*/
371 /* Width of a word, in units (bytes). */
372 #define UNITS_PER_WORD 4
374 /* Define this macro if it is advisable to hold scalars in registers
375 in a wider mode than that declared by the program. In such cases,
376 the value is constrained to be within the bounds of the declared
377 type, but kept valid in the wider mode. The signedness of the
378 extension may differ from that of the type. */
379 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
380 if (GET_MODE_CLASS (MODE) == MODE_INT \
381 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
386 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
387 #define PARM_BOUNDARY 32
389 /* Boundary (in *bits*) on which stack pointer should be aligned. */
390 #define STACK_BOUNDARY 32
392 /* ALIGN FRAMES on word boundaries */
393 #define M32R_STACK_ALIGN(LOC) (((LOC) + 3) & ~ 3)
395 /* Allocation boundary (in *bits*) for the code of a function. */
396 #define FUNCTION_BOUNDARY 32
398 /* Alignment of field after `int : 0' in a structure. */
399 #define EMPTY_FIELD_BOUNDARY 32
401 /* Every structure's size must be a multiple of this. */
402 #define STRUCTURE_SIZE_BOUNDARY 8
404 /* A bit-field declared as `int' forces `int' alignment for the struct. */
405 #define PCC_BITFIELD_TYPE_MATTERS 1
407 /* No data type wants to be aligned rounder than this. */
408 #define BIGGEST_ALIGNMENT 32
410 /* The best alignment to use in cases where we have a choice. */
411 #define FASTEST_ALIGNMENT 32
413 /* Make strings word-aligned so strcpy from constants will be faster. */
414 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
415 ((TREE_CODE (EXP) == STRING_CST \
416 && (ALIGN) < FASTEST_ALIGNMENT) \
417 ? FASTEST_ALIGNMENT : (ALIGN))
419 /* Make arrays of chars word-aligned for the same reasons. */
420 #define DATA_ALIGNMENT(TYPE, ALIGN) \
421 (TREE_CODE (TYPE) == ARRAY_TYPE \
422 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
423 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
425 /* Set this nonzero if move instructions will actually fail to work
426 when given unaligned data. */
427 #define STRICT_ALIGNMENT 1
429 /* Define LAVEL_ALIGN to calculate code length of PNOP at labels. */
430 #define LABEL_ALIGN(insn) 2
432 /* Layout of source language data types. */
434 #define SHORT_TYPE_SIZE 16
435 #define INT_TYPE_SIZE 32
436 #define LONG_TYPE_SIZE 32
437 #define LONG_LONG_TYPE_SIZE 64
438 #define FLOAT_TYPE_SIZE 32
439 #define DOUBLE_TYPE_SIZE 64
440 #define LONG_DOUBLE_TYPE_SIZE 64
442 /* Define this as 1 if `char' should by default be signed; else as 0. */
443 #define DEFAULT_SIGNED_CHAR 1
445 #define SIZE_TYPE "long unsigned int"
446 #define PTRDIFF_TYPE "long int"
447 #define WCHAR_TYPE "short unsigned int"
448 #define WCHAR_TYPE_SIZE 16
450 /* Standard register usage. */
452 /* Number of actual hardware registers.
453 The hardware registers are assigned numbers for the compiler
454 from 0 to just below FIRST_PSEUDO_REGISTER.
455 All registers that the compiler knows about must be given numbers,
456 even those that are not normally considered general registers. */
458 #define M32R_NUM_REGISTERS 19
460 #ifndef SUBTARGET_NUM_REGISTERS
461 #define SUBTARGET_NUM_REGISTERS 0
464 #define FIRST_PSEUDO_REGISTER (M32R_NUM_REGISTERS + SUBTARGET_NUM_REGISTERS)
466 /* 1 for registers that have pervasive standard uses
467 and are not available for the register allocator.
469 0-3 - arguments/results
470 4-5 - call used [4 is used as a tmp during prologue/epilogue generation]
472 7 - call used, static chain pointer
474 12 - call saved [reserved for global pointer]
476 14 - subroutine link register
481 19 - accumulator 1 in the m32r/x
482 By default, the extension registers are not available. */
484 #ifndef SUBTARGET_FIXED_REGISTERS
485 #define SUBTARGET_FIXED_REGISTERS
488 #define FIXED_REGISTERS \
490 0, 0, 0, 0, 0, 0, 0, 0, \
491 0, 0, 0, 0, 0, 0, 0, 1, \
493 SUBTARGET_FIXED_REGISTERS \
496 /* 1 for registers not available across function calls.
497 These must include the FIXED_REGISTERS and also any
498 registers that can be used without being saved.
499 The latter must include the registers where values are returned
500 and the register where structure-value addresses are passed.
501 Aside from that, you can include as many other registers as you like. */
503 #ifndef SUBTARGET_CALL_USED_REGISTERS
504 #define SUBTARGET_CALL_USED_REGISTERS
507 #define CALL_USED_REGISTERS \
509 1, 1, 1, 1, 1, 1, 1, 1, \
510 0, 0, 0, 0, 0, 0, 1, 1, \
512 SUBTARGET_CALL_USED_REGISTERS \
515 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
517 /* Zero or more C statements that may conditionally modify two variables
518 `fixed_regs' and `call_used_regs' (both of type `char []') after they
519 have been initialized from the two preceding macros.
521 This is necessary in case the fixed or call-clobbered registers depend
524 You need not define this macro if it has no work to do. */
526 #ifdef SUBTARGET_CONDITIONAL_REGISTER_USAGE
527 #define CONDITIONAL_REGISTER_USAGE SUBTARGET_CONDITIONAL_REGISTER_USAGE
529 #define CONDITIONAL_REGISTER_USAGE \
534 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
535 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
541 /* If defined, an initializer for a vector of integers, containing the
542 numbers of hard registers in the order in which GCC should
543 prefer to use them (from most preferred to least). */
545 #ifndef SUBTARGET_REG_ALLOC_ORDER
546 #define SUBTARGET_REG_ALLOC_ORDER
549 #if 1 /* Better for int code. */
550 #define REG_ALLOC_ORDER \
552 4, 5, 6, 7, 2, 3, 8, 9, 10, \
553 11, 12, 13, 14, 0, 1, 15, 16, 17, 18 \
554 SUBTARGET_REG_ALLOC_ORDER \
557 #else /* Better for fp code at expense of int code. */
558 #define REG_ALLOC_ORDER \
560 0, 1, 2, 3, 4, 5, 6, 7, 8, \
561 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 \
562 SUBTARGET_REG_ALLOC_ORDER \
566 /* Return number of consecutive hard regs needed starting at reg REGNO
567 to hold something of mode MODE.
568 This is ordinarily the length in words of a value of mode MODE
569 but can be less for certain modes in special long registers. */
570 #define HARD_REGNO_NREGS(REGNO, MODE) \
571 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
573 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
574 extern const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER];
575 extern unsigned int m32r_mode_class[];
576 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
577 ((m32r_hard_regno_mode_ok[REGNO] & m32r_mode_class[MODE]) != 0)
579 /* A C expression that is nonzero if it is desirable to choose
580 register allocation so as to avoid move instructions between a
581 value of mode MODE1 and a value of mode MODE2.
583 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
584 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
585 MODE2)' must be zero. */
587 /* Tie QI/HI/SI modes together. */
588 #define MODES_TIEABLE_P(MODE1, MODE2) \
589 ( GET_MODE_CLASS (MODE1) == MODE_INT \
590 && GET_MODE_CLASS (MODE2) == MODE_INT \
591 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
592 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD)
594 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
595 m32r_hard_regno_rename_ok (OLD_REG, NEW_REG)
597 /* Register classes and constants. */
599 /* Define the classes of registers for register constraints in the
600 machine description. Also define ranges of constants.
602 One of the classes must always be named ALL_REGS and include all hard regs.
603 If there is more than one class, another class must be named NO_REGS
604 and contain no registers.
606 The name GENERAL_REGS must be the name of a class (or an alias for
607 another name such as ALL_REGS). This is the class of registers
608 that is allowed by "g" or "r" in a register constraint.
609 Also, registers outside this class are allocated only when
610 instructions express preferences for them.
612 The classes must be numbered in nondecreasing order; that is,
613 a larger-numbered class must never be contained completely
614 in a smaller-numbered class.
616 For any two classes, it is very desirable that there be another
617 class that represents their union.
619 It is important that any condition codes have class NO_REGS.
620 See `register_operand'. */
624 NO_REGS, CARRY_REG, ACCUM_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
627 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
629 /* Give names of register classes as strings for dump file. */
630 #define REG_CLASS_NAMES \
631 { "NO_REGS", "CARRY_REG", "ACCUM_REGS", "GENERAL_REGS", "ALL_REGS" }
633 /* Define which registers fit in which classes.
634 This is an initializer for a vector of HARD_REG_SET
635 of length N_REG_CLASSES. */
637 #ifndef SUBTARGET_REG_CLASS_CARRY
638 #define SUBTARGET_REG_CLASS_CARRY 0
641 #ifndef SUBTARGET_REG_CLASS_ACCUM
642 #define SUBTARGET_REG_CLASS_ACCUM 0
645 #ifndef SUBTARGET_REG_CLASS_GENERAL
646 #define SUBTARGET_REG_CLASS_GENERAL 0
649 #ifndef SUBTARGET_REG_CLASS_ALL
650 #define SUBTARGET_REG_CLASS_ALL 0
653 #define REG_CLASS_CONTENTS \
656 { 0x20000 | SUBTARGET_REG_CLASS_CARRY }, \
657 { 0x40000 | SUBTARGET_REG_CLASS_ACCUM }, \
658 { 0x1ffff | SUBTARGET_REG_CLASS_GENERAL }, \
659 { 0x7ffff | SUBTARGET_REG_CLASS_ALL }, \
662 /* The same information, inverted:
663 Return the class number of the smallest class containing
664 reg number REGNO. This could be a conditional expression
665 or could index an array. */
666 extern enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
667 #define REGNO_REG_CLASS(REGNO) (m32r_regno_reg_class[REGNO])
669 /* The class value for index registers, and the one for base regs. */
670 #define INDEX_REG_CLASS GENERAL_REGS
671 #define BASE_REG_CLASS GENERAL_REGS
673 /* These assume that REGNO is a hard or pseudo reg number.
674 They give nonzero only if REGNO is a hard reg of the suitable class
675 or a pseudo reg currently allocated to a suitable hard reg.
676 Since they use reg_renumber, they are safe only once reg_renumber
677 has been allocated, which happens in local-alloc.c. */
678 #define REGNO_OK_FOR_BASE_P(REGNO) \
679 ((REGNO) < FIRST_PSEUDO_REGISTER \
680 ? GPR_P (REGNO) || (REGNO) == ARG_POINTER_REGNUM \
681 : GPR_P (reg_renumber[REGNO]))
683 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
685 /* Given an rtx X being reloaded into a reg required to be
686 in class CLASS, return the class of reg to actually use.
687 In general this is just CLASS; but on some machines
688 in some cases it is preferable to use a more restrictive class. */
689 #define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
691 /* Return the maximum number of consecutive registers
692 needed to represent mode MODE in a register of class CLASS. */
693 #define CLASS_MAX_NREGS(CLASS, MODE) \
694 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
696 /* Return true if a value is inside a range. */
697 #define IN_RANGE_P(VALUE, LOW, HIGH) \
698 (((unsigned HOST_WIDE_INT)((VALUE) - (LOW))) \
699 <= ((unsigned HOST_WIDE_INT)((HIGH) - (LOW))))
701 /* Some range macros. */
702 #define INT16_P(X) ((X) >= - 0x8000 && (X) <= 0x7fff)
703 #define CMP_INT16_P(X) ((X) >= - 0x7fff && (X) <= 0x8000)
704 #define UINT16_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x0000ffff)
705 #define UINT24_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x00ffffff)
707 /* Stack layout and stack pointer usage. */
709 /* Define this macro if pushing a word onto the stack moves the stack
710 pointer to a smaller address. */
711 #define STACK_GROWS_DOWNWARD
713 /* Offset from frame pointer to start allocating local variables at.
714 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
715 first local allocated. Otherwise, it is the offset to the BEGINNING
716 of the first local allocated. */
717 /* The frame pointer points at the same place as the stack pointer, except if
718 alloca has been called. */
719 #define STARTING_FRAME_OFFSET \
720 M32R_STACK_ALIGN (crtl->outgoing_args_size)
722 /* Offset from the stack pointer register to the first location at which
723 outgoing arguments are placed. */
724 #define STACK_POINTER_OFFSET 0
726 /* Offset of first parameter from the argument pointer register value. */
727 #define FIRST_PARM_OFFSET(FNDECL) 0
729 /* Register to use for pushing function arguments. */
730 #define STACK_POINTER_REGNUM 15
732 /* Base register for access to local variables of the function. */
733 #define FRAME_POINTER_REGNUM 13
735 /* Base register for access to arguments of the function. */
736 #define ARG_POINTER_REGNUM 16
738 /* Register in which static-chain is passed to a function.
739 This must not be a register used by the prologue. */
740 #define STATIC_CHAIN_REGNUM 7
742 /* These aren't official macros. */
743 #define PROLOGUE_TMP_REGNUM 4
744 #define RETURN_ADDR_REGNUM 14
745 /* #define GP_REGNUM 12 */
746 #define CARRY_REGNUM 17
747 #define ACCUM_REGNUM 18
748 #define M32R_MAX_INT_REGS 16
750 #ifndef SUBTARGET_GPR_P
751 #define SUBTARGET_GPR_P(REGNO) 0
754 #ifndef SUBTARGET_ACCUM_P
755 #define SUBTARGET_ACCUM_P(REGNO) 0
758 #ifndef SUBTARGET_CARRY_P
759 #define SUBTARGET_CARRY_P(REGNO) 0
762 #define GPR_P(REGNO) (IN_RANGE_P ((REGNO), 0, 15) || SUBTARGET_GPR_P (REGNO))
763 #define ACCUM_P(REGNO) ((REGNO) == ACCUM_REGNUM || SUBTARGET_ACCUM_P (REGNO))
764 #define CARRY_P(REGNO) ((REGNO) == CARRY_REGNUM || SUBTARGET_CARRY_P (REGNO))
766 /* Eliminating the frame and arg pointers. */
768 /* A C expression which is nonzero if a function must have and use a
769 frame pointer. This expression is evaluated in the reload pass.
770 If its value is nonzero the function will have a frame pointer. */
771 #define FRAME_POINTER_REQUIRED current_function_calls_alloca
774 /* C statement to store the difference between the frame pointer
775 and the stack pointer values immediately after the function prologue.
776 If `ELIMINABLE_REGS' is defined, this macro will be not be used and
777 need not be defined. */
778 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
779 ((VAR) = m32r_compute_frame_size (get_frame_size ()))
782 /* If defined, this macro specifies a table of register pairs used to
783 eliminate unneeded registers that point into the stack frame. If
784 it is not defined, the only elimination attempted by the compiler
785 is to replace references to the frame pointer with references to
788 Note that the elimination of the argument pointer with the stack
789 pointer is specified first since that is the preferred elimination. */
791 #define ELIMINABLE_REGS \
792 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
793 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
794 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }}
796 /* A C expression that returns nonzero if the compiler is allowed to
797 try to replace register number FROM-REG with register number
798 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
799 defined, and will usually be the constant 1, since most of the
800 cases preventing register elimination are things that the compiler
801 already knows about. */
803 #define CAN_ELIMINATE(FROM, TO) \
804 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
805 ? ! frame_pointer_needed \
808 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
809 specifies the initial difference between the specified pair of
810 registers. This macro must be defined if `ELIMINABLE_REGS' is
813 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
816 int size = m32r_compute_frame_size (get_frame_size ()); \
818 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
820 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
821 (OFFSET) = size - crtl->args.pretend_args_size; \
822 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
823 (OFFSET) = size - crtl->args.pretend_args_size; \
825 gcc_unreachable (); \
829 /* Function argument passing. */
831 /* If defined, the maximum amount of space required for outgoing
832 arguments will be computed and placed into the variable
833 `crtl->outgoing_args_size'. No space will be pushed
834 onto the stack for each call; instead, the function prologue should
835 increase the stack frame size by this amount. */
836 #define ACCUMULATE_OUTGOING_ARGS 1
838 /* Value is the number of bytes of arguments automatically
839 popped when returning from a subroutine call.
840 FUNDECL is the declaration node of the function (as a tree),
841 FUNTYPE is the data type of the function (as a tree),
842 or for a library call it is an identifier node for the subroutine name.
843 SIZE is the number of bytes of arguments passed on the stack. */
844 #define RETURN_POPS_ARGS(DECL, FUNTYPE, SIZE) 0
846 /* Define a data type for recording info about an argument list
847 during the scan of that argument list. This data type should
848 hold all necessary information about the function itself
849 and about the args processed so far, enough to enable macros
850 such as FUNCTION_ARG to determine where the next arg should go. */
851 #define CUMULATIVE_ARGS int
853 /* Initialize a variable CUM of type CUMULATIVE_ARGS
854 for a call to a function whose data type is FNTYPE.
855 For a library call, FNTYPE is 0. */
856 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
859 /* The number of registers used for parameter passing. Local to this file. */
860 #define M32R_MAX_PARM_REGS 4
862 /* 1 if N is a possible register number for function argument passing. */
863 #define FUNCTION_ARG_REGNO_P(N) \
864 ((unsigned) (N) < M32R_MAX_PARM_REGS)
866 /* The ROUND_ADVANCE* macros are local to this file. */
867 /* Round SIZE up to a word boundary. */
868 #define ROUND_ADVANCE(SIZE) \
869 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
871 /* Round arg MODE/TYPE up to the next word boundary. */
872 #define ROUND_ADVANCE_ARG(MODE, TYPE) \
874 ? ROUND_ADVANCE ((unsigned int) int_size_in_bytes (TYPE)) \
875 : ROUND_ADVANCE ((unsigned int) GET_MODE_SIZE (MODE)))
877 /* Round CUM up to the necessary point for argument MODE/TYPE. */
878 #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) (CUM)
880 /* Return boolean indicating arg of type TYPE and mode MODE will be passed in
881 a reg. This includes arguments that have to be passed by reference as the
882 pointer to them is passed in a reg if one is available (and that is what
884 This macro is only used in this file. */
885 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
886 (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < M32R_MAX_PARM_REGS)
888 /* Determine where to put an argument to a function.
889 Value is zero to push the argument on the stack,
890 or a hard register in which to store the argument.
892 MODE is the argument's machine mode.
893 TYPE is the data type of the argument (as a tree).
894 This is null for libcalls where that information may
896 CUM is a variable of type CUMULATIVE_ARGS which gives info about
897 the preceding args and about the function being called.
898 NAMED is nonzero if this argument is a named parameter
899 (otherwise it is an extra parameter matching an ellipsis). */
900 /* On the M32R the first M32R_MAX_PARM_REGS args are normally in registers
901 and the rest are pushed. */
902 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
903 (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
904 ? gen_rtx_REG ((MODE), ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE))) \
907 /* Update the data in CUM to advance over an argument
908 of mode MODE and data type TYPE.
909 (TYPE is null for libcalls where that information may not be available.) */
910 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
911 ((CUM) = (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) \
912 + ROUND_ADVANCE_ARG ((MODE), (TYPE))))
914 /* If defined, a C expression that gives the alignment boundary, in bits,
915 of an argument with the specified mode and type. If it is not defined,
916 PARM_BOUNDARY is used for all arguments. */
918 /* We assume PARM_BOUNDARY == UNITS_PER_WORD here. */
919 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
920 (((TYPE) ? TYPE_ALIGN (TYPE) : GET_MODE_BITSIZE (MODE)) <= PARM_BOUNDARY \
921 ? PARM_BOUNDARY : 2 * PARM_BOUNDARY)
924 /* Function results. */
926 /* Define how to find the value returned by a function.
927 VALTYPE is the data type of the value (as a tree).
928 If the precise function being called is known, FUNC is its FUNCTION_DECL;
929 otherwise, FUNC is 0. */
930 #define FUNCTION_VALUE(VALTYPE, FUNC) gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
932 /* Define how to find the value returned by a library function
933 assuming the value has mode MODE. */
934 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
936 /* 1 if N is a possible register number for a function value
937 as seen by the caller. */
938 /* ??? What about r1 in DI/DF values. */
939 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
941 /* Tell GCC to use TARGET_RETURN_IN_MEMORY. */
942 #define DEFAULT_PCC_STRUCT_RETURN 0
944 /* Function entry and exit. */
946 /* Initialize data used by insn expanders. This is called from
947 init_emit, once for each function, before code is generated. */
948 #define INIT_EXPANDERS m32r_init_expanders ()
950 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
951 the stack pointer does not matter. The value is tested only in
952 functions that have frame pointers.
953 No definition is equivalent to always zero. */
954 #define EXIT_IGNORE_STACK 1
956 /* Output assembler code to FILE to increment profiler label # LABELNO
957 for profiling a function entry. */
958 #undef FUNCTION_PROFILER
959 #define FUNCTION_PROFILER(FILE, LABELNO) \
964 fprintf (FILE, "\tld24 r14,#mcount\n"); \
965 fprintf (FILE, "\tadd r14,r12\n"); \
966 fprintf (FILE, "\tld r14,@r14\n"); \
967 fprintf (FILE, "\tjl r14\n"); \
972 fprintf (FILE, "\tbl mcount\n"); \
975 fprintf (FILE, "\tseth r14,#high(mcount)\n"); \
976 fprintf (FILE, "\tor3 r14,r14,#low(mcount)\n"); \
977 fprintf (FILE, "\tjl r14\n"); \
980 fprintf (FILE, "\taddi sp,#4\n"); \
986 /* On the M32R, the trampoline is:
988 mv r7, lr -> bl L1 ; 178e 7e01
989 L1: add3 r6, lr, #L2-L1 ; 86ae 000c (L2 - L1 = 12)
990 mv lr, r7 -> ld r7,@r6+ ; 1e87 27e6
991 ld r6, @r6 -> jmp r6 ; 26c6 1fc6
995 #ifndef CACHE_FLUSH_FUNC
996 #define CACHE_FLUSH_FUNC "_flush_cache"
998 #ifndef CACHE_FLUSH_TRAP
999 #define CACHE_FLUSH_TRAP 12
1002 /* Length in bytes of the trampoline for entering a nested function. */
1003 #define TRAMPOLINE_SIZE 24
1005 /* Emit RTL insns to initialize the variable parts of a trampoline.
1006 FNADDR is an RTX for the address of the function's pure code.
1007 CXT is an RTX for the static chain value for the function. */
1008 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1011 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 0)), \
1012 gen_int_mode (TARGET_LITTLE_ENDIAN ? \
1013 0x017e8e17 : 0x178e7e01, SImode)); \
1014 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 4)), \
1015 gen_int_mode (TARGET_LITTLE_ENDIAN ? \
1016 0x0c00ae86 : 0x86ae000c, SImode)); \
1017 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), \
1018 gen_int_mode (TARGET_LITTLE_ENDIAN ? \
1019 0xe627871e : 0x1e8727e6, SImode)); \
1020 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 12)), \
1021 gen_int_mode (TARGET_LITTLE_ENDIAN ? \
1022 0xc616c626 : 0x26c61fc6, SImode)); \
1023 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 16)), \
1025 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 20)), \
1027 if (m32r_cache_flush_trap >= 0) \
1028 emit_insn (gen_flush_icache (validize_mem (gen_rtx_MEM (SImode, TRAMP)),\
1029 gen_int_mode (m32r_cache_flush_trap, SImode))); \
1030 else if (m32r_cache_flush_func && m32r_cache_flush_func[0]) \
1031 emit_library_call (m32r_function_symbol (m32r_cache_flush_func), \
1032 0, VOIDmode, 3, TRAMP, Pmode, \
1033 gen_int_mode (TRAMPOLINE_SIZE, SImode), SImode, \
1034 GEN_INT (3), SImode); \
1038 #define RETURN_ADDR_RTX(COUNT, FRAME) m32r_return_addr (COUNT)
1040 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)
1042 /* Addressing modes, and classification of registers for them. */
1044 /* Maximum number of registers that can appear in a valid memory address. */
1045 #define MAX_REGS_PER_ADDRESS 1
1047 /* We have post-inc load and pre-dec,pre-inc store,
1048 but only for 4 byte vals. */
1049 #define HAVE_PRE_DECREMENT 1
1050 #define HAVE_PRE_INCREMENT 1
1051 #define HAVE_POST_INCREMENT 1
1053 /* Recognize any constant value that is a valid address. */
1054 #define CONSTANT_ADDRESS_P(X) \
1055 ( GET_CODE (X) == LABEL_REF \
1056 || GET_CODE (X) == SYMBOL_REF \
1057 || GET_CODE (X) == CONST_INT \
1058 || (GET_CODE (X) == CONST \
1059 && ! (flag_pic && ! m32r_legitimate_pic_operand_p (X))))
1061 /* Nonzero if the constant value X is a legitimate general operand.
1062 We don't allow (plus symbol large-constant) as the relocations can't
1063 describe it. INTVAL > 32767 handles both 16-bit and 24-bit relocations.
1064 We allow all CONST_DOUBLE's as the md file patterns will force the
1065 constant to memory if they can't handle them. */
1067 #define LEGITIMATE_CONSTANT_P(X) \
1068 (! (GET_CODE (X) == CONST \
1069 && GET_CODE (XEXP (X, 0)) == PLUS \
1070 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
1071 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1072 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (X, 0), 1)) > 32767))
1074 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1075 and check its validity for a certain class.
1076 We have two alternate definitions for each of them.
1077 The usual definition accepts all pseudo regs; the other rejects
1078 them unless they have been allocated suitable hard regs.
1079 The symbol REG_OK_STRICT causes the latter definition to be used.
1081 Most source files want to accept pseudo regs in the hope that
1082 they will get allocated to the class that the insn wants them to be in.
1083 Source files for reload pass need to be strict.
1084 After reload, it makes no difference, since pseudo regs have
1085 been eliminated by then. */
1087 #ifdef REG_OK_STRICT
1089 /* Nonzero if X is a hard reg that can be used as a base reg. */
1090 #define REG_OK_FOR_BASE_P(X) GPR_P (REGNO (X))
1091 /* Nonzero if X is a hard reg that can be used as an index. */
1092 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1096 /* Nonzero if X is a hard reg that can be used as a base reg
1097 or if it is a pseudo reg. */
1098 #define REG_OK_FOR_BASE_P(X) \
1099 (GPR_P (REGNO (X)) \
1100 || (REGNO (X)) == ARG_POINTER_REGNUM \
1101 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1102 /* Nonzero if X is a hard reg that can be used as an index
1103 or if it is a pseudo reg. */
1104 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1108 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1109 that is a valid memory address for an instruction.
1110 The MODE argument is the machine mode for the MEM expression
1111 that wants to use this address. */
1113 /* Local to this file. */
1114 #define RTX_OK_FOR_BASE_P(X) (REG_P (X) && REG_OK_FOR_BASE_P (X))
1116 /* Local to this file. */
1117 #define RTX_OK_FOR_OFFSET_P(X) \
1118 (GET_CODE (X) == CONST_INT && INT16_P (INTVAL (X)))
1120 /* Local to this file. */
1121 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X) \
1122 (GET_CODE (X) == PLUS \
1123 && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \
1124 && RTX_OK_FOR_OFFSET_P (XEXP (X, 1)))
1126 /* Local to this file. */
1127 /* For LO_SUM addresses, do not allow them if the MODE is > 1 word,
1128 since more than one instruction will be required. */
1129 #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X) \
1130 (GET_CODE (X) == LO_SUM \
1131 && (MODE != BLKmode && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)\
1132 && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \
1133 && CONSTANT_P (XEXP (X, 1)))
1135 /* Local to this file. */
1136 /* Is this a load and increment operation. */
1137 #define LOAD_POSTINC_P(MODE, X) \
1138 (((MODE) == SImode || (MODE) == SFmode) \
1139 && GET_CODE (X) == POST_INC \
1140 && GET_CODE (XEXP (X, 0)) == REG \
1141 && RTX_OK_FOR_BASE_P (XEXP (X, 0)))
1143 /* Local to this file. */
1144 /* Is this an increment/decrement and store operation. */
1145 #define STORE_PREINC_PREDEC_P(MODE, X) \
1146 (((MODE) == SImode || (MODE) == SFmode) \
1147 && (GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC) \
1148 && GET_CODE (XEXP (X, 0)) == REG \
1149 && RTX_OK_FOR_BASE_P (XEXP (X, 0)))
1151 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1154 if (RTX_OK_FOR_BASE_P (X)) \
1156 if (LEGITIMATE_OFFSET_ADDRESS_P ((MODE), (X))) \
1158 if (LEGITIMATE_LO_SUM_ADDRESS_P ((MODE), (X))) \
1160 if (LOAD_POSTINC_P ((MODE), (X))) \
1162 if (STORE_PREINC_PREDEC_P ((MODE), (X))) \
1167 /* Try machine-dependent ways of modifying an illegitimate address
1168 to be legitimate. If we find one, return the new, valid address.
1169 This macro is used in only one place: `memory_address' in explow.c.
1171 OLDX is the address as it was before break_out_memory_refs was called.
1172 In some cases it is useful to look at this to decide what needs to be done.
1174 MODE and WIN are passed so that this macro can use
1175 GO_IF_LEGITIMATE_ADDRESS.
1177 It is always safe for this macro to do nothing. It exists to recognize
1178 opportunities to optimize the output. */
1180 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1184 (X) = m32r_legitimize_pic_address (X, NULL_RTX); \
1185 if (memory_address_p (MODE, X)) \
1190 /* Go to LABEL if ADDR (a legitimate address expression)
1191 has an effect that depends on the machine mode it is used for. */
1192 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1195 if (GET_CODE (ADDR) == LO_SUM) \
1200 /* Condition code usage. */
1202 /* Return nonzero if SELECT_CC_MODE will never return MODE for a
1203 floating point inequality comparison. */
1204 #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/
1208 /* Compute extra cost of moving data between one register class
1210 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) 2
1212 /* Compute the cost of moving data between registers and memory. */
1213 /* Memory is 3 times as expensive as registers.
1214 ??? Is that the right way to look at it? */
1215 #define MEMORY_MOVE_COST(MODE,CLASS,IN_P) \
1216 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12)
1218 /* The cost of a branch insn. */
1219 /* A value of 2 here causes GCC to avoid using branches in comparisons like
1220 while (a < N && a). Branches aren't that expensive on the M32R so
1221 we define this as 1. Defining it as 2 had a heavy hit in fp-bit.c. */
1222 #define BRANCH_COST ((TARGET_BRANCH_COST) ? 2 : 1)
1224 /* Nonzero if access to memory by bytes is slow and undesirable.
1225 For RISC chips, it means that access to memory by bytes is no
1226 better than access by words when possible, so grab a whole word
1227 and maybe make use of that. */
1228 #define SLOW_BYTE_ACCESS 1
1230 /* Define this macro if it is as good or better to call a constant
1231 function address than to call an address kept in a register. */
1232 #define NO_FUNCTION_CSE
1234 /* Section selection. */
1236 #define TEXT_SECTION_ASM_OP "\t.section .text"
1237 #define DATA_SECTION_ASM_OP "\t.section .data"
1238 #define BSS_SECTION_ASM_OP "\t.section .bss"
1240 /* Define this macro if jump tables (for tablejump insns) should be
1241 output in the text section, along with the assembler instructions.
1242 Otherwise, the readonly data section is used.
1243 This macro is irrelevant if there is no separate readonly data section. */
1244 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
1246 /* Position Independent Code. */
1248 /* The register number of the register used to address a table of static
1249 data addresses in memory. In some cases this register is defined by a
1250 processor's ``application binary interface'' (ABI). When this macro
1251 is defined, RTL is generated for this register once, as with the stack
1252 pointer and frame pointer registers. If this macro is not defined, it
1253 is up to the machine-dependent files to allocate such a register (if
1255 #define PIC_OFFSET_TABLE_REGNUM 12
1257 /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is
1258 clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM
1260 /* This register is call-saved on the M32R. */
1261 /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/
1263 /* A C expression that is nonzero if X is a legitimate immediate
1264 operand on the target machine when generating position independent code.
1265 You can assume that X satisfies CONSTANT_P, so you need not
1266 check this. You can also assume `flag_pic' is true, so you need not
1267 check it either. You need not define this macro if all constants
1268 (including SYMBOL_REF) can be immediate operands when generating
1269 position independent code. */
1270 #define LEGITIMATE_PIC_OPERAND_P(X) m32r_legitimate_pic_operand_p (X)
1272 /* Control the assembler format that we output. */
1274 /* A C string constant describing how to begin a comment in the target
1275 assembler language. The compiler assumes that the comment will
1276 end at the end of the line. */
1277 #define ASM_COMMENT_START ";"
1279 /* Output to assembler file text saying following lines
1280 may contain character constants, extra white space, comments, etc. */
1281 #define ASM_APP_ON ""
1283 /* Output to assembler file text saying following lines
1284 no longer contain unusual constructs. */
1285 #define ASM_APP_OFF ""
1287 /* Globalizing directive for a label. */
1288 #define GLOBAL_ASM_OP "\t.global\t"
1290 /* We do not use DBX_LINES_FUNCTION_RELATIVE or
1291 dbxout_stab_value_internal_label_diff here because
1292 we need to use .debugsym for the line label. */
1294 #define DBX_OUTPUT_SOURCE_LINE(file, line, counter) \
1297 const char * begin_label = \
1298 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); \
1300 ASM_GENERATE_INTERNAL_LABEL (label, "LM", counter); \
1302 dbxout_begin_stabn_sline (line); \
1303 assemble_name (file, label); \
1305 assemble_name (file, begin_label); \
1306 fputs ("\n\t.debugsym ", file); \
1307 assemble_name (file, label); \
1308 putc ('\n', file); \
1313 /* How to refer to registers in assembler output.
1314 This sequence is indexed by compiler's hard-register-number (see above). */
1315 #ifndef SUBTARGET_REGISTER_NAMES
1316 #define SUBTARGET_REGISTER_NAMES
1319 #define REGISTER_NAMES \
1321 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1322 "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", \
1323 "ap", "cbit", "a0" \
1324 SUBTARGET_REGISTER_NAMES \
1327 /* If defined, a C initializer for an array of structures containing
1328 a name and a register number. This macro defines additional names
1329 for hard registers, thus allowing the `asm' option in declarations
1330 to refer to registers using alternate names. */
1331 #ifndef SUBTARGET_ADDITIONAL_REGISTER_NAMES
1332 #define SUBTARGET_ADDITIONAL_REGISTER_NAMES
1335 #define ADDITIONAL_REGISTER_NAMES \
1337 /*{ "gp", GP_REGNUM },*/ \
1338 { "r13", FRAME_POINTER_REGNUM }, \
1339 { "r14", RETURN_ADDR_REGNUM }, \
1340 { "r15", STACK_POINTER_REGNUM }, \
1341 SUBTARGET_ADDITIONAL_REGISTER_NAMES \
1344 /* A C expression which evaluates to true if CODE is a valid
1345 punctuation character for use in the `PRINT_OPERAND' macro. */
1346 extern char m32r_punct_chars[256];
1347 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1348 m32r_punct_chars[(unsigned char) (CHAR)]
1350 /* Print operand X (an rtx) in assembler syntax to file FILE.
1351 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1352 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1353 #define PRINT_OPERAND(FILE, X, CODE) \
1354 m32r_print_operand (FILE, X, CODE)
1356 /* A C compound statement to output to stdio stream STREAM the
1357 assembler syntax for an instruction operand that is a memory
1358 reference whose address is ADDR. ADDR is an RTL expression. */
1359 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1360 m32r_print_operand_address (FILE, ADDR)
1362 /* If defined, C string expressions to be used for the `%R', `%L',
1363 `%U', and `%I' options of `asm_fprintf' (see `final.c'). These
1364 are useful when a single `md' file must support multiple assembler
1365 formats. In that case, the various `tm.h' files can define these
1366 macros differently. */
1367 #define REGISTER_PREFIX ""
1368 #define LOCAL_LABEL_PREFIX ".L"
1369 #define USER_LABEL_PREFIX ""
1370 #define IMMEDIATE_PREFIX "#"
1372 /* This is how to output an element of a case-vector that is absolute. */
1373 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1377 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1378 fprintf (FILE, "\t.word\t"); \
1379 assemble_name (FILE, label); \
1380 fprintf (FILE, "\n"); \
1384 /* This is how to output an element of a case-vector that is relative. */
1385 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)\
1389 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1390 fprintf (FILE, "\t.word\t"); \
1391 assemble_name (FILE, label); \
1392 fprintf (FILE, "-"); \
1393 ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \
1394 assemble_name (FILE, label); \
1395 fprintf (FILE, "\n"); \
1399 /* The desired alignment for the location counter at the beginning
1401 /* On the M32R, align loops to 32 byte boundaries (cache line size)
1402 if -malign-loops. */
1403 #define LOOP_ALIGN(LABEL) (TARGET_ALIGN_LOOPS ? 5 : 0)
1405 /* Define this to be the maximum number of insns to move around when moving
1406 a loop test from the top of a loop to the bottom
1407 and seeing whether to duplicate it. The default is thirty.
1409 Loop unrolling currently doesn't like this optimization, so
1410 disable doing if we are unrolling loops and saving space. */
1411 #define LOOP_TEST_THRESHOLD (optimize_size \
1412 && !flag_unroll_loops \
1413 && !flag_unroll_all_loops ? 2 : 30)
1415 /* This is how to output an assembler line
1416 that says to advance the location counter
1417 to a multiple of 2**LOG bytes. */
1418 /* .balign is used to avoid confusion. */
1419 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1423 fprintf (FILE, "\t.balign %d\n", 1 << (LOG)); \
1427 /* Like `ASM_OUTPUT_COMMON' except takes the required alignment as a
1428 separate, explicit argument. If you define this macro, it is used in
1429 place of `ASM_OUTPUT_COMMON', and gives you more flexibility in
1430 handling the required alignment of the variable. The alignment is
1431 specified as the number of bits. */
1433 #define SCOMMON_ASM_OP "\t.scomm\t"
1435 #undef ASM_OUTPUT_ALIGNED_COMMON
1436 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
1439 if (! TARGET_SDATA_NONE \
1440 && (SIZE) > 0 && (SIZE) <= g_switch_value) \
1441 fprintf ((FILE), "%s", SCOMMON_ASM_OP); \
1443 fprintf ((FILE), "%s", COMMON_ASM_OP); \
1444 assemble_name ((FILE), (NAME)); \
1445 fprintf ((FILE), ",%u,%u\n", (int)(SIZE), (ALIGN) / BITS_PER_UNIT);\
1449 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1452 if (! TARGET_SDATA_NONE \
1453 && (SIZE) > 0 && (SIZE) <= g_switch_value) \
1454 switch_to_section (get_named_section (NULL, ".sbss", 0)); \
1456 switch_to_section (bss_section); \
1457 ASM_OUTPUT_ALIGN (FILE, floor_log2 (ALIGN / BITS_PER_UNIT)); \
1458 last_assemble_variable_decl = DECL; \
1459 ASM_DECLARE_OBJECT_NAME (FILE, NAME, DECL); \
1460 ASM_OUTPUT_SKIP (FILE, SIZE ? SIZE : 1); \
1464 /* Debugging information. */
1466 /* Generate DBX and DWARF debugging information. */
1467 #define DBX_DEBUGGING_INFO 1
1468 #define DWARF2_DEBUGGING_INFO 1
1470 /* Use DWARF2 debugging info by default. */
1471 #undef PREFERRED_DEBUGGING_TYPE
1472 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1474 /* Turn off splitting of long stabs. */
1475 #define DBX_CONTIN_LENGTH 0
1477 /* Miscellaneous. */
1479 /* Specify the machine mode that this machine uses
1480 for the index in the tablejump instruction. */
1481 #define CASE_VECTOR_MODE (flag_pic ? SImode : Pmode)
1483 /* Define if operations between registers always perform the operation
1484 on the full register even if a narrower mode is specified. */
1485 #define WORD_REGISTER_OPERATIONS
1487 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1488 will either zero-extend or sign-extend. The value of this macro should
1489 be the code that says which one of the two operations is implicitly
1490 done, UNKNOWN if none. */
1491 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1493 /* Max number of bytes we can move from memory
1494 to memory in one reasonably fast instruction. */
1497 /* Define this to be nonzero if shift instructions ignore all but the low-order
1499 #define SHIFT_COUNT_TRUNCATED 1
1501 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1502 is done just by pretending it is already truncated. */
1503 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1505 /* Specify the machine mode that pointers have.
1506 After generation of rtl, the compiler makes no further distinction
1507 between pointers and any other objects of this machine mode. */
1508 /* ??? The M32R doesn't have full 32-bit pointers, but making this PSImode has
1509 its own problems (you have to add extendpsisi2 and truncsipsi2).
1511 #define Pmode SImode
1513 /* A function address in a call instruction. */
1514 #define FUNCTION_MODE SImode
1516 /* Define the information needed to generate branch and scc insns. This is
1517 stored from the compare operation. Note that we can't use "rtx" here
1518 since it hasn't been defined! */
1519 extern struct rtx_def * m32r_compare_op0;
1520 extern struct rtx_def * m32r_compare_op1;
1522 /* M32R function types. */
1523 enum m32r_function_type
1525 M32R_FUNCTION_UNKNOWN, M32R_FUNCTION_NORMAL, M32R_FUNCTION_INTERRUPT
1528 #define M32R_INTERRUPT_P(TYPE) ((TYPE) == M32R_FUNCTION_INTERRUPT)
1530 /* The maximum number of bytes to copy using pairs of load/store instructions.
1531 If a block is larger than this then a loop will be generated to copy
1532 MAX_MOVE_BYTES chunks at a time. The value of 32 is a semi-arbitrary choice.
1533 A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte
1534 string copy in it. */
1535 #define MAX_MOVE_BYTES 32
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