1 /* Definitions of target machine for GNU compiler, Renesas M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
3 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 2, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
26 #undef SWITCH_TAKES_ARG
27 #undef WORD_SWITCH_TAKES_ARG
28 #undef HANDLE_SYSV_PRAGMA
32 #undef WCHAR_TYPE_SIZE
44 /* M32R/X overrides. */
45 /* Print subsidiary information on the compiler version in use. */
46 #define TARGET_VERSION fprintf (stderr, " (m32r/x/2)");
48 /* Additional flags for the preprocessor. */
49 #define CPP_CPU_SPEC "%{m32rx:-D__M32RX__ -D__m32rx__ -U__M32R2__ -U__m32r2__} \
50 %{m32r2:-D__M32R2__ -D__m32r2__ -U__M32RX__ -U__m32rx__} \
51 %{m32r:-U__M32RX__ -U__m32rx__ -U__M32R2__ -U__m32r2__} \
54 /* Assembler switches. */
55 #define ASM_CPU_SPEC \
56 "%{m32r} %{m32rx} %{m32r2} %{!O0: %{O*: -O}} --no-warn-explicit-parallel-conflicts"
58 /* Use m32rx specific crt0/crtinit/crtfini files. */
59 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} %{m32rx:m32rx/crtinit.o%s} %{!m32rx:crtinit.o%s}"
60 #define ENDFILE_CPU_SPEC "-lgloss %{m32rx:m32rx/crtfini.o%s} %{!m32rx:crtfini.o%s}"
62 /* Define this macro as a C expression for the initializer of an array of
63 strings to tell the driver program which options are defaults for this
64 target and thus do not need to be handled specially when using
65 `MULTILIB_OPTIONS'. */
66 #define SUBTARGET_MULTILIB_DEFAULTS , "m32r"
68 /* Number of additional registers the subtarget defines. */
69 #define SUBTARGET_NUM_REGISTERS 1
71 /* 1 for registers that cannot be allocated. */
72 #define SUBTARGET_FIXED_REGISTERS , 1
74 /* 1 for registers that are not available across function calls. */
75 #define SUBTARGET_CALL_USED_REGISTERS , 1
77 /* Order to allocate model specific registers. */
78 #define SUBTARGET_REG_ALLOC_ORDER , 19
80 /* Registers which are accumulators. */
81 #define SUBTARGET_REG_CLASS_ACCUM 0x80000
83 /* All registers added. */
84 #define SUBTARGET_REG_CLASS_ALL SUBTARGET_REG_CLASS_ACCUM
86 /* Additional accumulator registers. */
87 #define SUBTARGET_ACCUM_P(REGNO) ((REGNO) == 19)
89 /* Define additional register names. */
90 #define SUBTARGET_REGISTER_NAMES , "a1"
91 /* end M32R/X overrides. */
93 /* Print subsidiary information on the compiler version in use. */
94 #ifndef TARGET_VERSION
95 #define TARGET_VERSION fprintf (stderr, " (m32r)")
98 /* Switch Recognition by gcc.c. Add -G xx support. */
100 #undef SWITCH_TAKES_ARG
101 #define SWITCH_TAKES_ARG(CHAR) \
102 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
104 /* Names to predefine in the preprocessor for this target machine. */
105 /* __M32R__ is defined by the existing compiler so we use that. */
106 #define TARGET_CPU_CPP_BUILTINS() \
109 builtin_define ("__M32R__"); \
110 builtin_define ("__m32r__"); \
111 builtin_assert ("cpu=m32r"); \
112 builtin_assert ("machine=m32r"); \
113 builtin_define (TARGET_BIG_ENDIAN \
114 ? "__BIG_ENDIAN__" : "__LITTLE_ENDIAN__"); \
118 /* This macro defines names of additional specifications to put in the specs
119 that can be used in various specifications like CC1_SPEC. Its definition
120 is an initializer with a subgrouping for each command option.
122 Each subgrouping contains a string constant, that defines the
123 specification name, and a string constant that used by the GCC driver
126 Do not define this macro if it does not need to do anything. */
128 #ifndef SUBTARGET_EXTRA_SPECS
129 #define SUBTARGET_EXTRA_SPECS
133 #define ASM_CPU_SPEC ""
137 #define CPP_CPU_SPEC ""
141 #define CC1_CPU_SPEC ""
144 #ifndef LINK_CPU_SPEC
145 #define LINK_CPU_SPEC ""
148 #ifndef STARTFILE_CPU_SPEC
149 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} crtinit.o%s"
152 #ifndef ENDFILE_CPU_SPEC
153 #define ENDFILE_CPU_SPEC "-lgloss crtfini.o%s"
157 #if 0 /* Not supported yet. */
158 #define RELAX_SPEC "%{mrelax:-relax}"
160 #define RELAX_SPEC ""
164 #define EXTRA_SPECS \
165 { "asm_cpu", ASM_CPU_SPEC }, \
166 { "cpp_cpu", CPP_CPU_SPEC }, \
167 { "cc1_cpu", CC1_CPU_SPEC }, \
168 { "link_cpu", LINK_CPU_SPEC }, \
169 { "startfile_cpu", STARTFILE_CPU_SPEC }, \
170 { "endfile_cpu", ENDFILE_CPU_SPEC }, \
171 { "relax", RELAX_SPEC }, \
172 SUBTARGET_EXTRA_SPECS
174 #define CPP_SPEC "%(cpp_cpu)"
177 #define CC1_SPEC "%{G*} %(cc1_cpu)"
179 /* Options to pass on to the assembler. */
181 #define ASM_SPEC "%{v} %(asm_cpu) %(relax) %{fpic|fpie:-K PIC} %{fPIC|fPIE:-K PIC}"
183 #define LINK_SPEC "%{v} %(link_cpu) %(relax)"
185 #undef STARTFILE_SPEC
186 #define STARTFILE_SPEC "%(startfile_cpu)"
189 #define ENDFILE_SPEC "%(endfile_cpu)"
193 /* Run-time compilation parameters selecting different hardware subsets. */
195 #define TARGET_M32R (! TARGET_M32RX && ! TARGET_M32R2)
197 #ifndef TARGET_LITTLE_ENDIAN
198 #define TARGET_LITTLE_ENDIAN 0
200 #define TARGET_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN)
202 /* This defaults us to m32r. */
203 #ifndef TARGET_CPU_DEFAULT
204 #define TARGET_CPU_DEFAULT 0
209 Code models are used to select between two choices of two separate
210 possibilities (address space size, call insn to use):
212 small: addresses use 24 bits, use bl to make calls
213 medium: addresses use 32 bits, use bl to make calls (*1)
214 large: addresses use 32 bits, use seth/add3/jl to make calls (*2)
216 The fourth is "addresses use 24 bits, use seth/add3/jl to make calls" but
217 using this one doesn't make much sense.
219 (*1) The linker may eventually be able to relax seth/add3 -> ld24.
220 (*2) The linker may eventually be able to relax seth/add3/jl -> bl.
222 Internally these are recorded as TARGET_ADDR{24,32} and
225 The __model__ attribute can be used to select the code model to use when
226 accessing particular objects. */
228 enum m32r_model { M32R_MODEL_SMALL, M32R_MODEL_MEDIUM, M32R_MODEL_LARGE };
230 extern enum m32r_model m32r_model;
231 #define TARGET_MODEL_SMALL (m32r_model == M32R_MODEL_SMALL)
232 #define TARGET_MODEL_MEDIUM (m32r_model == M32R_MODEL_MEDIUM)
233 #define TARGET_MODEL_LARGE (m32r_model == M32R_MODEL_LARGE)
234 #define TARGET_ADDR24 (m32r_model == M32R_MODEL_SMALL)
235 #define TARGET_ADDR32 (! TARGET_ADDR24)
236 #define TARGET_CALL26 (! TARGET_CALL32)
237 #define TARGET_CALL32 (m32r_model == M32R_MODEL_LARGE)
239 /* The default is the small model. */
240 #ifndef M32R_MODEL_DEFAULT
241 #define M32R_MODEL_DEFAULT M32R_MODEL_SMALL
246 The SDA consists of sections .sdata, .sbss, and .scommon.
247 .scommon isn't a real section, symbols in it have their section index
248 set to SHN_M32R_SCOMMON, though support for it exists in the linker script.
250 Two switches control the SDA:
252 -G NNN - specifies the maximum size of variable to go in the SDA
254 -msdata=foo - specifies how such variables are handled
256 -msdata=none - small data area is disabled
258 -msdata=sdata - small data goes in the SDA, special code isn't
259 generated to use it, and special relocs aren't
262 -msdata=use - small data goes in the SDA, special code is generated
263 to use the SDA and special relocs are generated
265 The SDA is not multilib'd, it isn't necessary.
266 MULTILIB_EXTRA_OPTS is set in tmake_file to -msdata=sdata so multilib'd
267 libraries have small data in .sdata/SHN_M32R_SCOMMON so programs that use
268 -msdata=use will successfully link with them (references in header files
269 will cause the compiler to emit code that refers to library objects in
270 .data). ??? There can be a problem if the user passes a -G value greater
271 than the default and a library object in a header file is that size.
272 The default is 8 so this should be rare - if it occurs the user
273 is required to rebuild the libraries or use a smaller value for -G. */
275 /* Maximum size of variables that go in .sdata/.sbss.
276 The -msdata=foo switch also controls how small variables are handled. */
277 #ifndef SDATA_DEFAULT_SIZE
278 #define SDATA_DEFAULT_SIZE 8
281 enum m32r_sdata { M32R_SDATA_NONE, M32R_SDATA_SDATA, M32R_SDATA_USE };
283 extern enum m32r_sdata m32r_sdata;
284 #define TARGET_SDATA_NONE (m32r_sdata == M32R_SDATA_NONE)
285 #define TARGET_SDATA_SDATA (m32r_sdata == M32R_SDATA_SDATA)
286 #define TARGET_SDATA_USE (m32r_sdata == M32R_SDATA_USE)
288 /* Default is to disable the SDA
289 [for upward compatibility with previous toolchains]. */
290 #ifndef M32R_SDATA_DEFAULT
291 #define M32R_SDATA_DEFAULT M32R_SDATA_NONE
294 /* Define this macro as a C expression for the initializer of an array of
295 strings to tell the driver program which options are defaults for this
296 target and thus do not need to be handled specially when using
297 `MULTILIB_OPTIONS'. */
298 #ifndef SUBTARGET_MULTILIB_DEFAULTS
299 #define SUBTARGET_MULTILIB_DEFAULTS
302 #ifndef MULTILIB_DEFAULTS
303 #define MULTILIB_DEFAULTS { "mmodel=small" SUBTARGET_MULTILIB_DEFAULTS }
306 /* Sometimes certain combinations of command options do not make
307 sense on a particular target machine. You can define a macro
308 `OVERRIDE_OPTIONS' to take account of this. This macro, if
309 defined, is executed once just after all the command options have
312 Don't use this macro to turn on various extra optimizations for
313 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
315 #ifndef SUBTARGET_OVERRIDE_OPTIONS
316 #define SUBTARGET_OVERRIDE_OPTIONS
319 #define OVERRIDE_OPTIONS \
322 /* These need to be done at start up. \
323 It's convenient to do them here. */ \
325 SUBTARGET_OVERRIDE_OPTIONS \
329 #ifndef SUBTARGET_OPTIMIZATION_OPTIONS
330 #define SUBTARGET_OPTIMIZATION_OPTIONS
333 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
337 flag_regmove = TRUE; \
341 flag_omit_frame_pointer = TRUE; \
342 flag_strength_reduce = FALSE; \
345 SUBTARGET_OPTIMIZATION_OPTIONS \
349 /* Define this macro if debugging can be performed even without a
350 frame pointer. If this macro is defined, GCC will turn on the
351 `-fomit-frame-pointer' option whenever `-O' is specified. */
352 #define CAN_DEBUG_WITHOUT_FP
354 /* Target machine storage layout. */
356 /* Define this if most significant bit is lowest numbered
357 in instructions that operate on numbered bit-fields. */
358 #define BITS_BIG_ENDIAN 1
360 /* Define this if most significant byte of a word is the lowest numbered. */
361 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
363 /* Define this if most significant word of a multiword number is the lowest
365 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
367 /* Define this macro if WORDS_BIG_ENDIAN is not constant. This must
368 be a constant value with the same meaning as WORDS_BIG_ENDIAN,
369 which will be used only when compiling libgcc2.c. Typically the
370 value will be set based on preprocessor defines. */
371 /*#define LIBGCC2_WORDS_BIG_ENDIAN 1*/
373 /* Width of a word, in units (bytes). */
374 #define UNITS_PER_WORD 4
376 /* Define this macro if it is advisable to hold scalars in registers
377 in a wider mode than that declared by the program. In such cases,
378 the value is constrained to be within the bounds of the declared
379 type, but kept valid in the wider mode. The signedness of the
380 extension may differ from that of the type. */
381 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
382 if (GET_MODE_CLASS (MODE) == MODE_INT \
383 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
388 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
389 #define PARM_BOUNDARY 32
391 /* Boundary (in *bits*) on which stack pointer should be aligned. */
392 #define STACK_BOUNDARY 32
394 /* ALIGN FRAMES on word boundaries */
395 #define M32R_STACK_ALIGN(LOC) (((LOC) + 3) & ~ 3)
397 /* Allocation boundary (in *bits*) for the code of a function. */
398 #define FUNCTION_BOUNDARY 32
400 /* Alignment of field after `int : 0' in a structure. */
401 #define EMPTY_FIELD_BOUNDARY 32
403 /* Every structure's size must be a multiple of this. */
404 #define STRUCTURE_SIZE_BOUNDARY 8
406 /* A bit-field declared as `int' forces `int' alignment for the struct. */
407 #define PCC_BITFIELD_TYPE_MATTERS 1
409 /* No data type wants to be aligned rounder than this. */
410 #define BIGGEST_ALIGNMENT 32
412 /* The best alignment to use in cases where we have a choice. */
413 #define FASTEST_ALIGNMENT 32
415 /* Make strings word-aligned so strcpy from constants will be faster. */
416 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
417 ((TREE_CODE (EXP) == STRING_CST \
418 && (ALIGN) < FASTEST_ALIGNMENT) \
419 ? FASTEST_ALIGNMENT : (ALIGN))
421 /* Make arrays of chars word-aligned for the same reasons. */
422 #define DATA_ALIGNMENT(TYPE, ALIGN) \
423 (TREE_CODE (TYPE) == ARRAY_TYPE \
424 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
425 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
427 /* Set this nonzero if move instructions will actually fail to work
428 when given unaligned data. */
429 #define STRICT_ALIGNMENT 1
431 /* Define LAVEL_ALIGN to calculate code length of PNOP at labels. */
432 #define LABEL_ALIGN(insn) 2
434 /* Layout of source language data types. */
436 #define SHORT_TYPE_SIZE 16
437 #define INT_TYPE_SIZE 32
438 #define LONG_TYPE_SIZE 32
439 #define LONG_LONG_TYPE_SIZE 64
440 #define FLOAT_TYPE_SIZE 32
441 #define DOUBLE_TYPE_SIZE 64
442 #define LONG_DOUBLE_TYPE_SIZE 64
444 /* Define this as 1 if `char' should by default be signed; else as 0. */
445 #define DEFAULT_SIGNED_CHAR 1
447 #define SIZE_TYPE "long unsigned int"
448 #define PTRDIFF_TYPE "long int"
449 #define WCHAR_TYPE "short unsigned int"
450 #define WCHAR_TYPE_SIZE 16
452 /* Standard register usage. */
454 /* Number of actual hardware registers.
455 The hardware registers are assigned numbers for the compiler
456 from 0 to just below FIRST_PSEUDO_REGISTER.
457 All registers that the compiler knows about must be given numbers,
458 even those that are not normally considered general registers. */
460 #define M32R_NUM_REGISTERS 19
462 #ifndef SUBTARGET_NUM_REGISTERS
463 #define SUBTARGET_NUM_REGISTERS 0
466 #define FIRST_PSEUDO_REGISTER (M32R_NUM_REGISTERS + SUBTARGET_NUM_REGISTERS)
468 /* 1 for registers that have pervasive standard uses
469 and are not available for the register allocator.
471 0-3 - arguments/results
472 4-5 - call used [4 is used as a tmp during prologue/epilogue generation]
474 7 - call used, static chain pointer
476 12 - call saved [reserved for global pointer]
478 14 - subroutine link register
483 19 - accumulator 1 in the m32r/x
484 By default, the extension registers are not available. */
486 #ifndef SUBTARGET_FIXED_REGISTERS
487 #define SUBTARGET_FIXED_REGISTERS
490 #define FIXED_REGISTERS \
492 0, 0, 0, 0, 0, 0, 0, 0, \
493 0, 0, 0, 0, 0, 0, 0, 1, \
495 SUBTARGET_FIXED_REGISTERS \
498 /* 1 for registers not available across function calls.
499 These must include the FIXED_REGISTERS and also any
500 registers that can be used without being saved.
501 The latter must include the registers where values are returned
502 and the register where structure-value addresses are passed.
503 Aside from that, you can include as many other registers as you like. */
505 #ifndef SUBTARGET_CALL_USED_REGISTERS
506 #define SUBTARGET_CALL_USED_REGISTERS
509 #define CALL_USED_REGISTERS \
511 1, 1, 1, 1, 1, 1, 1, 1, \
512 0, 0, 0, 0, 0, 0, 1, 1, \
514 SUBTARGET_CALL_USED_REGISTERS \
517 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
519 /* Zero or more C statements that may conditionally modify two variables
520 `fixed_regs' and `call_used_regs' (both of type `char []') after they
521 have been initialized from the two preceding macros.
523 This is necessary in case the fixed or call-clobbered registers depend
526 You need not define this macro if it has no work to do. */
528 #ifdef SUBTARGET_CONDITIONAL_REGISTER_USAGE
529 #define CONDITIONAL_REGISTER_USAGE SUBTARGET_CONDITIONAL_REGISTER_USAGE
531 #define CONDITIONAL_REGISTER_USAGE \
536 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
537 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
543 /* If defined, an initializer for a vector of integers, containing the
544 numbers of hard registers in the order in which GCC should
545 prefer to use them (from most preferred to least). */
547 #ifndef SUBTARGET_REG_ALLOC_ORDER
548 #define SUBTARGET_REG_ALLOC_ORDER
551 #if 1 /* Better for int code. */
552 #define REG_ALLOC_ORDER \
554 4, 5, 6, 7, 2, 3, 8, 9, 10, \
555 11, 12, 13, 14, 0, 1, 15, 16, 17, 18 \
556 SUBTARGET_REG_ALLOC_ORDER \
559 #else /* Better for fp code at expense of int code. */
560 #define REG_ALLOC_ORDER \
562 0, 1, 2, 3, 4, 5, 6, 7, 8, \
563 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 \
564 SUBTARGET_REG_ALLOC_ORDER \
568 /* Return number of consecutive hard regs needed starting at reg REGNO
569 to hold something of mode MODE.
570 This is ordinarily the length in words of a value of mode MODE
571 but can be less for certain modes in special long registers. */
572 #define HARD_REGNO_NREGS(REGNO, MODE) \
573 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
575 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
576 extern const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER];
577 extern unsigned int m32r_mode_class[];
578 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
579 ((m32r_hard_regno_mode_ok[REGNO] & m32r_mode_class[MODE]) != 0)
581 /* A C expression that is nonzero if it is desirable to choose
582 register allocation so as to avoid move instructions between a
583 value of mode MODE1 and a value of mode MODE2.
585 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
586 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
587 MODE2)' must be zero. */
589 /* Tie QI/HI/SI modes together. */
590 #define MODES_TIEABLE_P(MODE1, MODE2) \
591 ( GET_MODE_CLASS (MODE1) == MODE_INT \
592 && GET_MODE_CLASS (MODE2) == MODE_INT \
593 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
594 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD)
596 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
597 m32r_hard_regno_rename_ok (OLD_REG, NEW_REG)
599 /* Register classes and constants. */
601 /* Define the classes of registers for register constraints in the
602 machine description. Also define ranges of constants.
604 One of the classes must always be named ALL_REGS and include all hard regs.
605 If there is more than one class, another class must be named NO_REGS
606 and contain no registers.
608 The name GENERAL_REGS must be the name of a class (or an alias for
609 another name such as ALL_REGS). This is the class of registers
610 that is allowed by "g" or "r" in a register constraint.
611 Also, registers outside this class are allocated only when
612 instructions express preferences for them.
614 The classes must be numbered in nondecreasing order; that is,
615 a larger-numbered class must never be contained completely
616 in a smaller-numbered class.
618 For any two classes, it is very desirable that there be another
619 class that represents their union.
621 It is important that any condition codes have class NO_REGS.
622 See `register_operand'. */
626 NO_REGS, CARRY_REG, ACCUM_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
629 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
631 /* Give names of register classes as strings for dump file. */
632 #define REG_CLASS_NAMES \
633 { "NO_REGS", "CARRY_REG", "ACCUM_REGS", "GENERAL_REGS", "ALL_REGS" }
635 /* Define which registers fit in which classes.
636 This is an initializer for a vector of HARD_REG_SET
637 of length N_REG_CLASSES. */
639 #ifndef SUBTARGET_REG_CLASS_CARRY
640 #define SUBTARGET_REG_CLASS_CARRY 0
643 #ifndef SUBTARGET_REG_CLASS_ACCUM
644 #define SUBTARGET_REG_CLASS_ACCUM 0
647 #ifndef SUBTARGET_REG_CLASS_GENERAL
648 #define SUBTARGET_REG_CLASS_GENERAL 0
651 #ifndef SUBTARGET_REG_CLASS_ALL
652 #define SUBTARGET_REG_CLASS_ALL 0
655 #define REG_CLASS_CONTENTS \
658 { 0x20000 | SUBTARGET_REG_CLASS_CARRY }, \
659 { 0x40000 | SUBTARGET_REG_CLASS_ACCUM }, \
660 { 0x1ffff | SUBTARGET_REG_CLASS_GENERAL }, \
661 { 0x7ffff | SUBTARGET_REG_CLASS_ALL }, \
664 /* The same information, inverted:
665 Return the class number of the smallest class containing
666 reg number REGNO. This could be a conditional expression
667 or could index an array. */
668 extern enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
669 #define REGNO_REG_CLASS(REGNO) (m32r_regno_reg_class[REGNO])
671 /* The class value for index registers, and the one for base regs. */
672 #define INDEX_REG_CLASS GENERAL_REGS
673 #define BASE_REG_CLASS GENERAL_REGS
675 #define REG_CLASS_FROM_LETTER(C) \
676 ( (C) == 'c' ? CARRY_REG \
677 : (C) == 'a' ? ACCUM_REGS \
680 /* These assume that REGNO is a hard or pseudo reg number.
681 They give nonzero only if REGNO is a hard reg of the suitable class
682 or a pseudo reg currently allocated to a suitable hard reg.
683 Since they use reg_renumber, they are safe only once reg_renumber
684 has been allocated, which happens in local-alloc.c. */
685 #define REGNO_OK_FOR_BASE_P(REGNO) \
686 ((REGNO) < FIRST_PSEUDO_REGISTER \
687 ? GPR_P (REGNO) || (REGNO) == ARG_POINTER_REGNUM \
688 : GPR_P (reg_renumber[REGNO]))
690 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
692 /* Given an rtx X being reloaded into a reg required to be
693 in class CLASS, return the class of reg to actually use.
694 In general this is just CLASS; but on some machines
695 in some cases it is preferable to use a more restrictive class. */
696 #define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
698 /* Return the maximum number of consecutive registers
699 needed to represent mode MODE in a register of class CLASS. */
700 #define CLASS_MAX_NREGS(CLASS, MODE) \
701 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
703 /* The letters I, J, K, L, M, N, O, P in a register constraint string
704 can be used to stand for particular ranges of immediate operands.
705 This macro defines what the ranges are.
706 C is the letter, and VALUE is a constant value.
707 Return 1 if VALUE is in the range specified by C. */
708 /* 'I' is used for 8 bit signed immediates.
709 'J' is used for 16 bit signed immediates.
710 'K' is used for 16 bit unsigned immediates.
711 'L' is used for 16 bit immediates left shifted by 16 (sign ???).
712 'M' is used for 24 bit unsigned immediates.
713 'N' is used for any 32 bit non-symbolic value.
714 'O' is used for 5 bit unsigned immediates (shift count).
715 'P' is used for 16 bit signed immediates for compares
716 (values in the range -32767 to +32768). */
718 /* Return true if a value is inside a range. */
719 #define IN_RANGE_P(VALUE, LOW, HIGH) \
720 (((unsigned HOST_WIDE_INT)((VALUE) - (LOW))) \
721 <= ((unsigned HOST_WIDE_INT)((HIGH) - (LOW))))
723 /* Local to this file. */
724 #define INT8_P(X) ((X) >= - 0x80 && (X) <= 0x7f)
725 #define INT16_P(X) ((X) >= - 0x8000 && (X) <= 0x7fff)
726 #define CMP_INT16_P(X) ((X) >= - 0x7fff && (X) <= 0x8000)
727 #define UPPER16_P(X) (((X) & 0xffff) == 0 \
728 && ((X) >> 16) >= - 0x8000 \
729 && ((X) >> 16) <= 0x7fff)
730 #define UINT16_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x0000ffff)
731 #define UINT24_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x00ffffff)
732 #define UINT32_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0xffffffff)
733 #define UINT5_P(X) ((X) >= 0 && (X) < 32)
734 #define INVERTED_SIGNED_8BIT(VAL) ((VAL) >= -127 && (VAL) <= 128)
736 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
737 ( (C) == 'I' ? INT8_P (VALUE) \
738 : (C) == 'J' ? INT16_P (VALUE) \
739 : (C) == 'K' ? UINT16_P (VALUE) \
740 : (C) == 'L' ? UPPER16_P (VALUE) \
741 : (C) == 'M' ? UINT24_P (VALUE) \
742 : (C) == 'N' ? INVERTED_SIGNED_8BIT (VALUE) \
743 : (C) == 'O' ? UINT5_P (VALUE) \
744 : (C) == 'P' ? CMP_INT16_P (VALUE) \
747 /* Similar, but for floating constants, and defining letters G and H.
748 Here VALUE is the CONST_DOUBLE rtx itself.
749 For the m32r, handle a few constants inline.
750 ??? We needn't treat DI and DF modes differently, but for now we do. */
751 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
752 ( (C) == 'G' ? easy_di_const (VALUE) \
753 : (C) == 'H' ? easy_df_const (VALUE) \
756 /* A C expression that defines the optional machine-dependent constraint
757 letters that can be used to segregate specific types of operands,
758 usually memory references, for the target machine. It should return 1 if
759 VALUE corresponds to the operand type represented by the constraint letter
760 C. If C is not defined as an extra constraint, the value returned should
761 be 0 regardless of VALUE. */
762 /* Q is for symbolic addresses loadable with ld24.
763 R is for symbolic addresses when ld24 can't be used.
764 S is for stores with pre {inc,dec}rement
765 T is for indirect of a pointer.
766 U is for loads with post increment. */
768 #define EXTRA_CONSTRAINT(VALUE, C) \
769 ( (C) == 'Q' ? ((TARGET_ADDR24 && GET_CODE (VALUE) == LABEL_REF) \
770 || addr24_operand (VALUE, VOIDmode)) \
771 : (C) == 'R' ? ((TARGET_ADDR32 && GET_CODE (VALUE) == LABEL_REF) \
772 || addr32_operand (VALUE, VOIDmode)) \
773 : (C) == 'S' ? (GET_CODE (VALUE) == MEM \
774 && STORE_PREINC_PREDEC_P (GET_MODE (VALUE), \
776 : (C) == 'T' ? (GET_CODE (VALUE) == MEM \
777 && memreg_operand (VALUE, GET_MODE (VALUE))) \
778 : (C) == 'U' ? (GET_CODE (VALUE) == MEM \
779 && LOAD_POSTINC_P (GET_MODE (VALUE), \
783 /* Stack layout and stack pointer usage. */
785 /* Define this macro if pushing a word onto the stack moves the stack
786 pointer to a smaller address. */
787 #define STACK_GROWS_DOWNWARD
789 /* Offset from frame pointer to start allocating local variables at.
790 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
791 first local allocated. Otherwise, it is the offset to the BEGINNING
792 of the first local allocated. */
793 /* The frame pointer points at the same place as the stack pointer, except if
794 alloca has been called. */
795 #define STARTING_FRAME_OFFSET \
796 M32R_STACK_ALIGN (current_function_outgoing_args_size)
798 /* Offset from the stack pointer register to the first location at which
799 outgoing arguments are placed. */
800 #define STACK_POINTER_OFFSET 0
802 /* Offset of first parameter from the argument pointer register value. */
803 #define FIRST_PARM_OFFSET(FNDECL) 0
805 /* Register to use for pushing function arguments. */
806 #define STACK_POINTER_REGNUM 15
808 /* Base register for access to local variables of the function. */
809 #define FRAME_POINTER_REGNUM 13
811 /* Base register for access to arguments of the function. */
812 #define ARG_POINTER_REGNUM 16
814 /* Register in which static-chain is passed to a function.
815 This must not be a register used by the prologue. */
816 #define STATIC_CHAIN_REGNUM 7
818 /* These aren't official macros. */
819 #define PROLOGUE_TMP_REGNUM 4
820 #define RETURN_ADDR_REGNUM 14
821 /* #define GP_REGNUM 12 */
822 #define CARRY_REGNUM 17
823 #define ACCUM_REGNUM 18
824 #define M32R_MAX_INT_REGS 16
826 #ifndef SUBTARGET_GPR_P
827 #define SUBTARGET_GPR_P(REGNO) 0
830 #ifndef SUBTARGET_ACCUM_P
831 #define SUBTARGET_ACCUM_P(REGNO) 0
834 #ifndef SUBTARGET_CARRY_P
835 #define SUBTARGET_CARRY_P(REGNO) 0
838 #define GPR_P(REGNO) (IN_RANGE_P ((REGNO), 0, 15) || SUBTARGET_GPR_P (REGNO))
839 #define ACCUM_P(REGNO) ((REGNO) == ACCUM_REGNUM || SUBTARGET_ACCUM_P (REGNO))
840 #define CARRY_P(REGNO) ((REGNO) == CARRY_REGNUM || SUBTARGET_CARRY_P (REGNO))
842 /* Eliminating the frame and arg pointers. */
844 /* A C expression which is nonzero if a function must have and use a
845 frame pointer. This expression is evaluated in the reload pass.
846 If its value is nonzero the function will have a frame pointer. */
847 #define FRAME_POINTER_REQUIRED current_function_calls_alloca
850 /* C statement to store the difference between the frame pointer
851 and the stack pointer values immediately after the function prologue.
852 If `ELIMINABLE_REGS' is defined, this macro will be not be used and
853 need not be defined. */
854 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
855 ((VAR) = m32r_compute_frame_size (get_frame_size ()))
858 /* If defined, this macro specifies a table of register pairs used to
859 eliminate unneeded registers that point into the stack frame. If
860 it is not defined, the only elimination attempted by the compiler
861 is to replace references to the frame pointer with references to
864 Note that the elimination of the argument pointer with the stack
865 pointer is specified first since that is the preferred elimination. */
867 #define ELIMINABLE_REGS \
868 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
869 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
870 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }}
872 /* A C expression that returns nonzero if the compiler is allowed to
873 try to replace register number FROM-REG with register number
874 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
875 defined, and will usually be the constant 1, since most of the
876 cases preventing register elimination are things that the compiler
877 already knows about. */
879 #define CAN_ELIMINATE(FROM, TO) \
880 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
881 ? ! frame_pointer_needed \
884 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
885 specifies the initial difference between the specified pair of
886 registers. This macro must be defined if `ELIMINABLE_REGS' is
889 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
892 int size = m32r_compute_frame_size (get_frame_size ()); \
894 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
896 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
897 (OFFSET) = size - current_function_pretend_args_size; \
898 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
899 (OFFSET) = size - current_function_pretend_args_size; \
901 gcc_unreachable (); \
905 /* Function argument passing. */
907 /* If defined, the maximum amount of space required for outgoing
908 arguments will be computed and placed into the variable
909 `current_function_outgoing_args_size'. No space will be pushed
910 onto the stack for each call; instead, the function prologue should
911 increase the stack frame size by this amount. */
912 #define ACCUMULATE_OUTGOING_ARGS 1
914 /* Value is the number of bytes of arguments automatically
915 popped when returning from a subroutine call.
916 FUNDECL is the declaration node of the function (as a tree),
917 FUNTYPE is the data type of the function (as a tree),
918 or for a library call it is an identifier node for the subroutine name.
919 SIZE is the number of bytes of arguments passed on the stack. */
920 #define RETURN_POPS_ARGS(DECL, FUNTYPE, SIZE) 0
922 /* Define a data type for recording info about an argument list
923 during the scan of that argument list. This data type should
924 hold all necessary information about the function itself
925 and about the args processed so far, enough to enable macros
926 such as FUNCTION_ARG to determine where the next arg should go. */
927 #define CUMULATIVE_ARGS int
929 /* Initialize a variable CUM of type CUMULATIVE_ARGS
930 for a call to a function whose data type is FNTYPE.
931 For a library call, FNTYPE is 0. */
932 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
935 /* The number of registers used for parameter passing. Local to this file. */
936 #define M32R_MAX_PARM_REGS 4
938 /* 1 if N is a possible register number for function argument passing. */
939 #define FUNCTION_ARG_REGNO_P(N) \
940 ((unsigned) (N) < M32R_MAX_PARM_REGS)
942 /* The ROUND_ADVANCE* macros are local to this file. */
943 /* Round SIZE up to a word boundary. */
944 #define ROUND_ADVANCE(SIZE) \
945 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
947 /* Round arg MODE/TYPE up to the next word boundary. */
948 #define ROUND_ADVANCE_ARG(MODE, TYPE) \
950 ? ROUND_ADVANCE ((unsigned int) int_size_in_bytes (TYPE)) \
951 : ROUND_ADVANCE ((unsigned int) GET_MODE_SIZE (MODE)))
953 /* Round CUM up to the necessary point for argument MODE/TYPE. */
954 #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) (CUM)
956 /* Return boolean indicating arg of type TYPE and mode MODE will be passed in
957 a reg. This includes arguments that have to be passed by reference as the
958 pointer to them is passed in a reg if one is available (and that is what
960 This macro is only used in this file. */
961 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
962 (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < M32R_MAX_PARM_REGS)
964 /* Determine where to put an argument to a function.
965 Value is zero to push the argument on the stack,
966 or a hard register in which to store the argument.
968 MODE is the argument's machine mode.
969 TYPE is the data type of the argument (as a tree).
970 This is null for libcalls where that information may
972 CUM is a variable of type CUMULATIVE_ARGS which gives info about
973 the preceding args and about the function being called.
974 NAMED is nonzero if this argument is a named parameter
975 (otherwise it is an extra parameter matching an ellipsis). */
976 /* On the M32R the first M32R_MAX_PARM_REGS args are normally in registers
977 and the rest are pushed. */
978 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
979 (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
980 ? gen_rtx_REG ((MODE), ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE))) \
983 /* Update the data in CUM to advance over an argument
984 of mode MODE and data type TYPE.
985 (TYPE is null for libcalls where that information may not be available.) */
986 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
987 ((CUM) = (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) \
988 + ROUND_ADVANCE_ARG ((MODE), (TYPE))))
990 /* If defined, a C expression that gives the alignment boundary, in bits,
991 of an argument with the specified mode and type. If it is not defined,
992 PARM_BOUNDARY is used for all arguments. */
994 /* We assume PARM_BOUNDARY == UNITS_PER_WORD here. */
995 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
996 (((TYPE) ? TYPE_ALIGN (TYPE) : GET_MODE_BITSIZE (MODE)) <= PARM_BOUNDARY \
997 ? PARM_BOUNDARY : 2 * PARM_BOUNDARY)
1000 /* Function results. */
1002 /* Define how to find the value returned by a function.
1003 VALTYPE is the data type of the value (as a tree).
1004 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1005 otherwise, FUNC is 0. */
1006 #define FUNCTION_VALUE(VALTYPE, FUNC) gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
1008 /* Define how to find the value returned by a library function
1009 assuming the value has mode MODE. */
1010 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
1012 /* 1 if N is a possible register number for a function value
1013 as seen by the caller. */
1014 /* ??? What about r1 in DI/DF values. */
1015 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
1017 /* Tell GCC to use TARGET_RETURN_IN_MEMORY. */
1018 #define DEFAULT_PCC_STRUCT_RETURN 0
1020 /* Function entry and exit. */
1022 /* Initialize data used by insn expanders. This is called from
1023 init_emit, once for each function, before code is generated. */
1024 #define INIT_EXPANDERS m32r_init_expanders ()
1026 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1027 the stack pointer does not matter. The value is tested only in
1028 functions that have frame pointers.
1029 No definition is equivalent to always zero. */
1030 #define EXIT_IGNORE_STACK 1
1032 /* Output assembler code to FILE to increment profiler label # LABELNO
1033 for profiling a function entry. */
1034 #undef FUNCTION_PROFILER
1035 #define FUNCTION_PROFILER(FILE, LABELNO) \
1040 fprintf (FILE, "\tld24 r14,#mcount\n"); \
1041 fprintf (FILE, "\tadd r14,r12\n"); \
1042 fprintf (FILE, "\tld r14,@r14\n"); \
1043 fprintf (FILE, "\tjl r14\n"); \
1047 if (TARGET_ADDR24) \
1048 fprintf (FILE, "\tbl mcount\n"); \
1051 fprintf (FILE, "\tseth r14,#high(mcount)\n"); \
1052 fprintf (FILE, "\tor3 r14,r14,#low(mcount)\n"); \
1053 fprintf (FILE, "\tjl r14\n"); \
1056 fprintf (FILE, "\taddi sp,#4\n"); \
1062 /* On the M32R, the trampoline is:
1064 mv r7, lr -> bl L1 ; 178e 7e01
1065 L1: add3 r6, lr, #L2-L1 ; 86ae 000c (L2 - L1 = 12)
1066 mv lr, r7 -> ld r7,@r6+ ; 1e87 27e6
1067 ld r6, @r6 -> jmp r6 ; 26c6 1fc6
1071 #ifndef CACHE_FLUSH_FUNC
1072 #define CACHE_FLUSH_FUNC "_flush_cache"
1074 #ifndef CACHE_FLUSH_TRAP
1075 #define CACHE_FLUSH_TRAP 12
1078 /* Length in bytes of the trampoline for entering a nested function. */
1079 #define TRAMPOLINE_SIZE 24
1081 /* Emit RTL insns to initialize the variable parts of a trampoline.
1082 FNADDR is an RTX for the address of the function's pure code.
1083 CXT is an RTX for the static chain value for the function. */
1084 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1087 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 0)), \
1089 (TARGET_LITTLE_ENDIAN ? 0x017e8e17 : 0x178e7e01)); \
1090 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 4)), \
1092 (TARGET_LITTLE_ENDIAN ? 0x0c00ae86 : 0x86ae000c)); \
1093 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), \
1095 (TARGET_LITTLE_ENDIAN ? 0xe627871e : 0x1e8727e6)); \
1096 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 12)), \
1098 (TARGET_LITTLE_ENDIAN ? 0xc616c626 : 0x26c61fc6)); \
1099 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 16)), \
1101 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 20)), \
1103 if (m32r_cache_flush_trap >= 0) \
1104 emit_insn (gen_flush_icache (validize_mem (gen_rtx_MEM (SImode, TRAMP)),\
1105 GEN_INT (m32r_cache_flush_trap) )); \
1106 else if (m32r_cache_flush_func && m32r_cache_flush_func[0]) \
1107 emit_library_call (m32r_function_symbol (m32r_cache_flush_func), \
1108 0, VOIDmode, 3, TRAMP, Pmode, \
1109 GEN_INT (TRAMPOLINE_SIZE), SImode, \
1110 GEN_INT (3), SImode); \
1114 #define RETURN_ADDR_RTX(COUNT, FRAME) m32r_return_addr (COUNT)
1116 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)
1118 /* Addressing modes, and classification of registers for them. */
1120 /* Maximum number of registers that can appear in a valid memory address. */
1121 #define MAX_REGS_PER_ADDRESS 1
1123 /* We have post-inc load and pre-dec,pre-inc store,
1124 but only for 4 byte vals. */
1125 #define HAVE_PRE_DECREMENT 1
1126 #define HAVE_PRE_INCREMENT 1
1127 #define HAVE_POST_INCREMENT 1
1129 /* Recognize any constant value that is a valid address. */
1130 #define CONSTANT_ADDRESS_P(X) \
1131 ( GET_CODE (X) == LABEL_REF \
1132 || GET_CODE (X) == SYMBOL_REF \
1133 || GET_CODE (X) == CONST_INT \
1134 || (GET_CODE (X) == CONST \
1135 && ! (flag_pic && ! m32r_legitimate_pic_operand_p (X))))
1137 /* Nonzero if the constant value X is a legitimate general operand.
1138 We don't allow (plus symbol large-constant) as the relocations can't
1139 describe it. INTVAL > 32767 handles both 16 bit and 24 bit relocations.
1140 We allow all CONST_DOUBLE's as the md file patterns will force the
1141 constant to memory if they can't handle them. */
1143 #define LEGITIMATE_CONSTANT_P(X) \
1144 (! (GET_CODE (X) == CONST \
1145 && GET_CODE (XEXP (X, 0)) == PLUS \
1146 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
1147 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1148 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (X, 0), 1)) > 32767))
1150 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1151 and check its validity for a certain class.
1152 We have two alternate definitions for each of them.
1153 The usual definition accepts all pseudo regs; the other rejects
1154 them unless they have been allocated suitable hard regs.
1155 The symbol REG_OK_STRICT causes the latter definition to be used.
1157 Most source files want to accept pseudo regs in the hope that
1158 they will get allocated to the class that the insn wants them to be in.
1159 Source files for reload pass need to be strict.
1160 After reload, it makes no difference, since pseudo regs have
1161 been eliminated by then. */
1163 #ifdef REG_OK_STRICT
1165 /* Nonzero if X is a hard reg that can be used as a base reg. */
1166 #define REG_OK_FOR_BASE_P(X) GPR_P (REGNO (X))
1167 /* Nonzero if X is a hard reg that can be used as an index. */
1168 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1172 /* Nonzero if X is a hard reg that can be used as a base reg
1173 or if it is a pseudo reg. */
1174 #define REG_OK_FOR_BASE_P(X) \
1175 (GPR_P (REGNO (X)) \
1176 || (REGNO (X)) == ARG_POINTER_REGNUM \
1177 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1178 /* Nonzero if X is a hard reg that can be used as an index
1179 or if it is a pseudo reg. */
1180 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1184 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1185 that is a valid memory address for an instruction.
1186 The MODE argument is the machine mode for the MEM expression
1187 that wants to use this address. */
1189 /* Local to this file. */
1190 #define RTX_OK_FOR_BASE_P(X) (REG_P (X) && REG_OK_FOR_BASE_P (X))
1192 /* Local to this file. */
1193 #define RTX_OK_FOR_OFFSET_P(X) \
1194 (GET_CODE (X) == CONST_INT && INT16_P (INTVAL (X)))
1196 /* Local to this file. */
1197 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X) \
1198 (GET_CODE (X) == PLUS \
1199 && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \
1200 && RTX_OK_FOR_OFFSET_P (XEXP (X, 1)))
1202 /* Local to this file. */
1203 /* For LO_SUM addresses, do not allow them if the MODE is > 1 word,
1204 since more than one instruction will be required. */
1205 #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X) \
1206 (GET_CODE (X) == LO_SUM \
1207 && (MODE != BLKmode && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)\
1208 && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \
1209 && CONSTANT_P (XEXP (X, 1)))
1211 /* Local to this file. */
1212 /* Is this a load and increment operation. */
1213 #define LOAD_POSTINC_P(MODE, X) \
1214 (((MODE) == SImode || (MODE) == SFmode) \
1215 && GET_CODE (X) == POST_INC \
1216 && GET_CODE (XEXP (X, 0)) == REG \
1217 && RTX_OK_FOR_BASE_P (XEXP (X, 0)))
1219 /* Local to this file. */
1220 /* Is this an increment/decrement and store operation. */
1221 #define STORE_PREINC_PREDEC_P(MODE, X) \
1222 (((MODE) == SImode || (MODE) == SFmode) \
1223 && (GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC) \
1224 && GET_CODE (XEXP (X, 0)) == REG \
1225 && RTX_OK_FOR_BASE_P (XEXP (X, 0)))
1227 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1230 if (RTX_OK_FOR_BASE_P (X)) \
1232 if (LEGITIMATE_OFFSET_ADDRESS_P ((MODE), (X))) \
1234 if (LEGITIMATE_LO_SUM_ADDRESS_P ((MODE), (X))) \
1236 if (LOAD_POSTINC_P ((MODE), (X))) \
1238 if (STORE_PREINC_PREDEC_P ((MODE), (X))) \
1243 /* Try machine-dependent ways of modifying an illegitimate address
1244 to be legitimate. If we find one, return the new, valid address.
1245 This macro is used in only one place: `memory_address' in explow.c.
1247 OLDX is the address as it was before break_out_memory_refs was called.
1248 In some cases it is useful to look at this to decide what needs to be done.
1250 MODE and WIN are passed so that this macro can use
1251 GO_IF_LEGITIMATE_ADDRESS.
1253 It is always safe for this macro to do nothing. It exists to recognize
1254 opportunities to optimize the output. */
1256 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1260 (X) = m32r_legitimize_pic_address (X, NULL_RTX); \
1261 if (memory_address_p (MODE, X)) \
1266 /* Go to LABEL if ADDR (a legitimate address expression)
1267 has an effect that depends on the machine mode it is used for. */
1268 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1271 if ( GET_CODE (ADDR) == PRE_DEC \
1272 || GET_CODE (ADDR) == PRE_INC \
1273 || GET_CODE (ADDR) == POST_INC \
1274 || GET_CODE (ADDR) == LO_SUM) \
1279 /* Condition code usage. */
1281 /* Return nonzero if SELECT_CC_MODE will never return MODE for a
1282 floating point inequality comparison. */
1283 #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/
1287 /* Compute extra cost of moving data between one register class
1289 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) 2
1291 /* Compute the cost of moving data between registers and memory. */
1292 /* Memory is 3 times as expensive as registers.
1293 ??? Is that the right way to look at it? */
1294 #define MEMORY_MOVE_COST(MODE,CLASS,IN_P) \
1295 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12)
1297 /* The cost of a branch insn. */
1298 /* A value of 2 here causes GCC to avoid using branches in comparisons like
1299 while (a < N && a). Branches aren't that expensive on the M32R so
1300 we define this as 1. Defining it as 2 had a heavy hit in fp-bit.c. */
1301 #define BRANCH_COST ((TARGET_BRANCH_COST) ? 2 : 1)
1303 /* Nonzero if access to memory by bytes is slow and undesirable.
1304 For RISC chips, it means that access to memory by bytes is no
1305 better than access by words when possible, so grab a whole word
1306 and maybe make use of that. */
1307 #define SLOW_BYTE_ACCESS 1
1309 /* Define this macro if it is as good or better to call a constant
1310 function address than to call an address kept in a register. */
1311 #define NO_FUNCTION_CSE
1313 /* Section selection. */
1315 #define TEXT_SECTION_ASM_OP "\t.section .text"
1316 #define DATA_SECTION_ASM_OP "\t.section .data"
1317 #define BSS_SECTION_ASM_OP "\t.section .bss"
1319 /* Define this macro if jump tables (for tablejump insns) should be
1320 output in the text section, along with the assembler instructions.
1321 Otherwise, the readonly data section is used.
1322 This macro is irrelevant if there is no separate readonly data section. */
1323 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
1325 /* Position Independent Code. */
1327 /* The register number of the register used to address a table of static
1328 data addresses in memory. In some cases this register is defined by a
1329 processor's ``application binary interface'' (ABI). When this macro
1330 is defined, RTL is generated for this register once, as with the stack
1331 pointer and frame pointer registers. If this macro is not defined, it
1332 is up to the machine-dependent files to allocate such a register (if
1334 #define PIC_OFFSET_TABLE_REGNUM 12
1336 /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is
1337 clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM
1339 /* This register is call-saved on the M32R. */
1340 /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/
1342 /* A C expression that is nonzero if X is a legitimate immediate
1343 operand on the target machine when generating position independent code.
1344 You can assume that X satisfies CONSTANT_P, so you need not
1345 check this. You can also assume `flag_pic' is true, so you need not
1346 check it either. You need not define this macro if all constants
1347 (including SYMBOL_REF) can be immediate operands when generating
1348 position independent code. */
1349 #define LEGITIMATE_PIC_OPERAND_P(X) m32r_legitimate_pic_operand_p (X)
1351 /* Control the assembler format that we output. */
1353 /* A C string constant describing how to begin a comment in the target
1354 assembler language. The compiler assumes that the comment will
1355 end at the end of the line. */
1356 #define ASM_COMMENT_START ";"
1358 /* Output to assembler file text saying following lines
1359 may contain character constants, extra white space, comments, etc. */
1360 #define ASM_APP_ON ""
1362 /* Output to assembler file text saying following lines
1363 no longer contain unusual constructs. */
1364 #define ASM_APP_OFF ""
1366 /* Globalizing directive for a label. */
1367 #define GLOBAL_ASM_OP "\t.global\t"
1369 /* We do not use DBX_LINES_FUNCTION_RELATIVE or
1370 dbxout_stab_value_internal_label_diff here because
1371 we need to use .debugsym for the line label. */
1373 #define DBX_OUTPUT_SOURCE_LINE(file, line, counter) \
1376 rtx begin_label = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);\
1378 ASM_GENERATE_INTERNAL_LABEL (label, "LM", counter); \
1380 dbxout_begin_stabn_sline (line); \
1381 assemble_name (file, label); \
1383 assemble_name (file, begin_label); \
1384 fputs ("\n\t.debugsym ", file); \
1385 assemble_name (file, label); \
1386 putc ('\n', file); \
1391 /* How to refer to registers in assembler output.
1392 This sequence is indexed by compiler's hard-register-number (see above). */
1393 #ifndef SUBTARGET_REGISTER_NAMES
1394 #define SUBTARGET_REGISTER_NAMES
1397 #define REGISTER_NAMES \
1399 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1400 "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", \
1401 "ap", "cbit", "a0" \
1402 SUBTARGET_REGISTER_NAMES \
1405 /* If defined, a C initializer for an array of structures containing
1406 a name and a register number. This macro defines additional names
1407 for hard registers, thus allowing the `asm' option in declarations
1408 to refer to registers using alternate names. */
1409 #ifndef SUBTARGET_ADDITIONAL_REGISTER_NAMES
1410 #define SUBTARGET_ADDITIONAL_REGISTER_NAMES
1413 #define ADDITIONAL_REGISTER_NAMES \
1415 /*{ "gp", GP_REGNUM },*/ \
1416 { "r13", FRAME_POINTER_REGNUM }, \
1417 { "r14", RETURN_ADDR_REGNUM }, \
1418 { "r15", STACK_POINTER_REGNUM }, \
1419 SUBTARGET_ADDITIONAL_REGISTER_NAMES \
1422 /* A C expression which evaluates to true if CODE is a valid
1423 punctuation character for use in the `PRINT_OPERAND' macro. */
1424 extern char m32r_punct_chars[256];
1425 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1426 m32r_punct_chars[(unsigned char) (CHAR)]
1428 /* Print operand X (an rtx) in assembler syntax to file FILE.
1429 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1430 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1431 #define PRINT_OPERAND(FILE, X, CODE) \
1432 m32r_print_operand (FILE, X, CODE)
1434 /* A C compound statement to output to stdio stream STREAM the
1435 assembler syntax for an instruction operand that is a memory
1436 reference whose address is ADDR. ADDR is an RTL expression. */
1437 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1438 m32r_print_operand_address (FILE, ADDR)
1440 /* If defined, C string expressions to be used for the `%R', `%L',
1441 `%U', and `%I' options of `asm_fprintf' (see `final.c'). These
1442 are useful when a single `md' file must support multiple assembler
1443 formats. In that case, the various `tm.h' files can define these
1444 macros differently. */
1445 #define REGISTER_PREFIX ""
1446 #define LOCAL_LABEL_PREFIX ".L"
1447 #define USER_LABEL_PREFIX ""
1448 #define IMMEDIATE_PREFIX "#"
1450 /* This is how to output an element of a case-vector that is absolute. */
1451 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1455 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1456 fprintf (FILE, "\t.word\t"); \
1457 assemble_name (FILE, label); \
1458 fprintf (FILE, "\n"); \
1462 /* This is how to output an element of a case-vector that is relative. */
1463 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)\
1467 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1468 fprintf (FILE, "\t.word\t"); \
1469 assemble_name (FILE, label); \
1470 fprintf (FILE, "-"); \
1471 ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \
1472 assemble_name (FILE, label); \
1473 fprintf (FILE, "\n"); \
1477 /* The desired alignment for the location counter at the beginning
1479 /* On the M32R, align loops to 32 byte boundaries (cache line size)
1480 if -malign-loops. */
1481 #define LOOP_ALIGN(LABEL) (TARGET_ALIGN_LOOPS ? 5 : 0)
1483 /* Define this to be the maximum number of insns to move around when moving
1484 a loop test from the top of a loop to the bottom
1485 and seeing whether to duplicate it. The default is thirty.
1487 Loop unrolling currently doesn't like this optimization, so
1488 disable doing if we are unrolling loops and saving space. */
1489 #define LOOP_TEST_THRESHOLD (optimize_size \
1490 && !flag_unroll_loops \
1491 && !flag_unroll_all_loops ? 2 : 30)
1493 /* This is how to output an assembler line
1494 that says to advance the location counter
1495 to a multiple of 2**LOG bytes. */
1496 /* .balign is used to avoid confusion. */
1497 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1501 fprintf (FILE, "\t.balign %d\n", 1 << (LOG)); \
1505 /* Like `ASM_OUTPUT_COMMON' except takes the required alignment as a
1506 separate, explicit argument. If you define this macro, it is used in
1507 place of `ASM_OUTPUT_COMMON', and gives you more flexibility in
1508 handling the required alignment of the variable. The alignment is
1509 specified as the number of bits. */
1511 #define SCOMMON_ASM_OP "\t.scomm\t"
1513 #undef ASM_OUTPUT_ALIGNED_COMMON
1514 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
1517 if (! TARGET_SDATA_NONE \
1518 && (SIZE) > 0 && (SIZE) <= g_switch_value) \
1519 fprintf ((FILE), "%s", SCOMMON_ASM_OP); \
1521 fprintf ((FILE), "%s", COMMON_ASM_OP); \
1522 assemble_name ((FILE), (NAME)); \
1523 fprintf ((FILE), ",%u,%u\n", (int)(SIZE), (ALIGN) / BITS_PER_UNIT);\
1527 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1530 if (! TARGET_SDATA_NONE \
1531 && (SIZE) > 0 && (SIZE) <= g_switch_value) \
1532 named_section (0, ".sbss", 0); \
1535 ASM_OUTPUT_ALIGN (FILE, floor_log2 (ALIGN / BITS_PER_UNIT)); \
1536 last_assemble_variable_decl = DECL; \
1537 ASM_DECLARE_OBJECT_NAME (FILE, NAME, DECL); \
1538 ASM_OUTPUT_SKIP (FILE, SIZE ? SIZE : 1); \
1542 /* Debugging information. */
1544 /* Generate DBX and DWARF debugging information. */
1545 #define DBX_DEBUGGING_INFO 1
1546 #define DWARF2_DEBUGGING_INFO 1
1548 /* Use DWARF2 debugging info by default. */
1549 #undef PREFERRED_DEBUGGING_TYPE
1550 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1552 /* Turn off splitting of long stabs. */
1553 #define DBX_CONTIN_LENGTH 0
1555 /* Miscellaneous. */
1557 /* Specify the machine mode that this machine uses
1558 for the index in the tablejump instruction. */
1559 #define CASE_VECTOR_MODE (flag_pic ? SImode : Pmode)
1561 /* Define if operations between registers always perform the operation
1562 on the full register even if a narrower mode is specified. */
1563 #define WORD_REGISTER_OPERATIONS
1565 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1566 will either zero-extend or sign-extend. The value of this macro should
1567 be the code that says which one of the two operations is implicitly
1568 done, UNKNOWN if none. */
1569 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1571 /* Max number of bytes we can move from memory
1572 to memory in one reasonably fast instruction. */
1575 /* Define this to be nonzero if shift instructions ignore all but the low-order
1577 #define SHIFT_COUNT_TRUNCATED 1
1579 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1580 is done just by pretending it is already truncated. */
1581 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1583 /* Specify the machine mode that pointers have.
1584 After generation of rtl, the compiler makes no further distinction
1585 between pointers and any other objects of this machine mode. */
1586 /* ??? The M32R doesn't have full 32 bit pointers, but making this PSImode has
1587 its own problems (you have to add extendpsisi2 and truncsipsi2).
1589 #define Pmode SImode
1591 /* A function address in a call instruction. */
1592 #define FUNCTION_MODE SImode
1594 /* Define the information needed to generate branch and scc insns. This is
1595 stored from the compare operation. Note that we can't use "rtx" here
1596 since it hasn't been defined! */
1597 extern struct rtx_def * m32r_compare_op0;
1598 extern struct rtx_def * m32r_compare_op1;
1600 /* M32R function types. */
1601 enum m32r_function_type
1603 M32R_FUNCTION_UNKNOWN, M32R_FUNCTION_NORMAL, M32R_FUNCTION_INTERRUPT
1606 #define M32R_INTERRUPT_P(TYPE) ((TYPE) == M32R_FUNCTION_INTERRUPT)
1608 /* The maximum number of bytes to copy using pairs of load/store instructions.
1609 If a block is larger than this then a loop will be generated to copy
1610 MAX_MOVE_BYTES chunks at a time. The value of 32 is a semi-arbitrary choice.
1611 A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte
1612 string copy in it. */
1613 #define MAX_MOVE_BYTES 32
OSDN Git Service
