1 /* Definitions of target machine for GNU compiler, Renesas M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
3 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 2, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #undef SWITCH_TAKES_ARG
27 #undef WORD_SWITCH_TAKES_ARG
28 #undef HANDLE_SYSV_PRAGMA
32 #undef WCHAR_TYPE_SIZE
39 #undef SUBTARGET_SWITCHES
45 /* M32R/X overrides. */
46 /* Print subsidiary information on the compiler version in use. */
47 #define TARGET_VERSION fprintf (stderr, " (m32r/x/2)");
49 /* Additional flags for the preprocessor. */
50 #define CPP_CPU_SPEC "%{m32rx:-D__M32RX__ -D__m32rx__ -U__M32R2__ -U__m32r2__} \
51 %{m32r2:-D__M32R2__ -D__m32r2__ -U__M32RX__ -U__m32rx__} \
52 %{m32r:-U__M32RX__ -U__m32rx__ -U__M32R2__ -U__m32r2__} \
55 /* Assembler switches. */
56 #define ASM_CPU_SPEC \
57 "%{m32r} %{m32rx} %{m32r2} %{!O0: %{O*: -O}} --no-warn-explicit-parallel-conflicts"
59 /* Use m32rx specific crt0/crtinit/crtfini files. */
60 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} %{m32rx:m32rx/crtinit.o%s} %{!m32rx:crtinit.o%s}"
61 #define ENDFILE_CPU_SPEC "-lgloss %{m32rx:m32rx/crtfini.o%s} %{!m32rx:crtfini.o%s}"
63 /* Extra machine dependent switches. */
64 #define SUBTARGET_SWITCHES \
65 { "32rx", TARGET_M32RX_MASK, "Compile for the m32rx" }, \
66 { "32r2", TARGET_M32R2_MASK, "Compile for the m32r2" }, \
67 { "32r", -(TARGET_M32RX_MASK+TARGET_M32R2_MASK), "" },
69 /* Define this macro as a C expression for the initializer of an array of
70 strings to tell the driver program which options are defaults for this
71 target and thus do not need to be handled specially when using
72 `MULTILIB_OPTIONS'. */
73 #define SUBTARGET_MULTILIB_DEFAULTS , "m32r"
75 /* Number of additional registers the subtarget defines. */
76 #define SUBTARGET_NUM_REGISTERS 1
78 /* 1 for registers that cannot be allocated. */
79 #define SUBTARGET_FIXED_REGISTERS , 1
81 /* 1 for registers that are not available across function calls. */
82 #define SUBTARGET_CALL_USED_REGISTERS , 1
84 /* Order to allocate model specific registers. */
85 #define SUBTARGET_REG_ALLOC_ORDER , 19
87 /* Registers which are accumulators. */
88 #define SUBTARGET_REG_CLASS_ACCUM 0x80000
90 /* All registers added. */
91 #define SUBTARGET_REG_CLASS_ALL SUBTARGET_REG_CLASS_ACCUM
93 /* Additional accumulator registers. */
94 #define SUBTARGET_ACCUM_P(REGNO) ((REGNO) == 19)
96 /* Define additional register names. */
97 #define SUBTARGET_REGISTER_NAMES , "a1"
98 /* end M32R/X overrides. */
100 /* Print subsidiary information on the compiler version in use. */
101 #ifndef TARGET_VERSION
102 #define TARGET_VERSION fprintf (stderr, " (m32r)")
105 /* Switch Recognition by gcc.c. Add -G xx support. */
107 #undef SWITCH_TAKES_ARG
108 #define SWITCH_TAKES_ARG(CHAR) \
109 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
111 /* Names to predefine in the preprocessor for this target machine. */
112 /* __M32R__ is defined by the existing compiler so we use that. */
113 #define TARGET_CPU_CPP_BUILTINS() \
116 builtin_define ("__M32R__"); \
117 builtin_define ("__m32r__"); \
118 builtin_assert ("cpu=m32r"); \
119 builtin_assert ("machine=m32r"); \
120 builtin_define (TARGET_BIG_ENDIAN \
121 ? "__BIG_ENDIAN__" : "__LITTLE_ENDIAN__"); \
124 builtin_define ("__pic__"); \
125 builtin_define ("__PIC__"); \
130 /* This macro defines names of additional specifications to put in the specs
131 that can be used in various specifications like CC1_SPEC. Its definition
132 is an initializer with a subgrouping for each command option.
134 Each subgrouping contains a string constant, that defines the
135 specification name, and a string constant that used by the GCC driver
138 Do not define this macro if it does not need to do anything. */
140 #ifndef SUBTARGET_EXTRA_SPECS
141 #define SUBTARGET_EXTRA_SPECS
145 #define ASM_CPU_SPEC ""
149 #define CPP_CPU_SPEC ""
153 #define CC1_CPU_SPEC ""
156 #ifndef LINK_CPU_SPEC
157 #define LINK_CPU_SPEC ""
160 #ifndef STARTFILE_CPU_SPEC
161 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} crtinit.o%s"
164 #ifndef ENDFILE_CPU_SPEC
165 #define ENDFILE_CPU_SPEC "-lgloss crtfini.o%s"
169 #if 0 /* Not supported yet. */
170 #define RELAX_SPEC "%{mrelax:-relax}"
172 #define RELAX_SPEC ""
176 #define EXTRA_SPECS \
177 { "asm_cpu", ASM_CPU_SPEC }, \
178 { "cpp_cpu", CPP_CPU_SPEC }, \
179 { "cc1_cpu", CC1_CPU_SPEC }, \
180 { "link_cpu", LINK_CPU_SPEC }, \
181 { "startfile_cpu", STARTFILE_CPU_SPEC }, \
182 { "endfile_cpu", ENDFILE_CPU_SPEC }, \
183 { "relax", RELAX_SPEC }, \
184 SUBTARGET_EXTRA_SPECS
186 #define CPP_SPEC "%(cpp_cpu)"
189 #define CC1_SPEC "%{G*} %(cc1_cpu)"
191 /* Options to pass on to the assembler. */
193 #define ASM_SPEC "%{v} %(asm_cpu) %(relax) %{fpic:-K PIC} %{fPIC:-K PIC}"
195 #define LINK_SPEC "%{v} %(link_cpu) %(relax)"
197 #undef STARTFILE_SPEC
198 #define STARTFILE_SPEC "%(startfile_cpu)"
201 #define ENDFILE_SPEC "%(endfile_cpu)"
205 /* Run-time compilation parameters selecting different hardware subsets. */
207 extern int target_flags;
209 /* If nonzero, tell the linker to do relaxing.
210 We don't do anything with the option, other than recognize it.
211 LINK_SPEC handles passing -relax to the linker.
212 This can cause incorrect debugging information as line numbers may
213 turn out wrong. This shouldn't be specified unless accompanied with -O2
214 [where the user expects debugging information to be less accurate]. */
215 #define TARGET_RELAX_MASK (1 << 0)
217 /* For miscellaneous debugging purposes. */
218 #define TARGET_DEBUG_MASK (1 << 1)
219 #define TARGET_DEBUG (target_flags & TARGET_DEBUG_MASK)
221 /* Align loops to 32 byte boundaries (cache line size). */
222 /* ??? This option is experimental and is not documented. */
223 #define TARGET_ALIGN_LOOPS_MASK (1 << 2)
224 #define TARGET_ALIGN_LOOPS (target_flags & TARGET_ALIGN_LOOPS_MASK)
226 /* Change issue rate. */
227 #define TARGET_LOW_ISSUE_RATE_MASK (1 << 3)
228 #define TARGET_LOW_ISSUE_RATE (target_flags & TARGET_LOW_ISSUE_RATE_MASK)
230 /* Change branch cost */
231 #define TARGET_BRANCH_COST_MASK (1 << 4)
232 #define TARGET_BRANCH_COST (target_flags & TARGET_BRANCH_COST_MASK)
234 /* Target machine to compile for. */
235 #define TARGET_M32R 1
237 /* Support extended instruction set. */
238 #define TARGET_M32RX_MASK (1 << 5)
239 #define TARGET_M32RX (target_flags & TARGET_M32RX_MASK)
241 #define TARGET_M32R (! TARGET_M32RX)
243 /* Support extended instruction set of m32r2. */
244 #define TARGET_M32R2_MASK (1 << 6)
245 #define TARGET_M32R2 (target_flags & TARGET_M32R2_MASK)
247 #define TARGET_M32R (! TARGET_M32RX && ! TARGET_M32R2)
249 /* Little Endian Flag. */
250 #define LITTLE_ENDIAN_BIT (1 << 7)
251 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
252 #define TARGET_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN)
254 /* This defaults us to big-endian. */
255 #ifndef TARGET_ENDIAN_DEFAULT
256 #define TARGET_ENDIAN_DEFAULT 0
259 /* This defaults us to m32r. */
260 #ifndef TARGET_CPU_DEFAULT
261 #define TARGET_CPU_DEFAULT 0
264 /* Macro to define tables used to set the flags.
265 This is a list in braces of pairs in braces,
266 each pair being { "NAME", VALUE }
267 where VALUE is the bits to set or minus the bits to clear.
268 An empty string NAME is used to identify the default VALUE. */
270 #ifndef SUBTARGET_SWITCHES
271 #define SUBTARGET_SWITCHES
274 #ifndef TARGET_DEFAULT
275 #define TARGET_DEFAULT (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT)
278 #define TARGET_SWITCHES \
280 /* { "relax", TARGET_RELAX_MASK, "" }, \
281 { "no-relax", -TARGET_RELAX_MASK, "" },*/ \
282 { "debug", TARGET_DEBUG_MASK, \
283 N_("Display compile time statistics") }, \
284 { "align-loops", TARGET_ALIGN_LOOPS_MASK, \
285 N_("Align all loops to 32 byte boundary") }, \
286 { "no-align-loops", -TARGET_ALIGN_LOOPS_MASK, "" }, \
287 { "issue-rate=1", TARGET_LOW_ISSUE_RATE_MASK, \
288 N_("Only issue one instruction per cycle") }, \
289 { "issue-rate=2", -TARGET_LOW_ISSUE_RATE_MASK, "" }, \
290 { "branch-cost=1", TARGET_BRANCH_COST_MASK, \
291 N_("Prefer branches over conditional execution") }, \
292 { "branch-cost=2", -TARGET_BRANCH_COST_MASK, "" }, \
294 { "", TARGET_DEFAULT, "" } \
297 extern const char * m32r_model_string;
298 extern const char * m32r_sdata_string;
300 /* Cache-flush support. */
301 extern const char * m32r_cache_flush_func;
302 extern const char * m32r_cache_flush_trap_string;
303 extern int m32r_cache_flush_trap;
305 #ifndef SUBTARGET_OPTIONS
306 #define SUBTARGET_OPTIONS
309 #define TARGET_OPTIONS \
311 { "model=", & m32r_model_string, \
312 N_("Code size: small, medium or large"), 0}, \
313 { "sdata=", & m32r_sdata_string, \
314 N_("Small data area: none, sdata, use"), 0}, \
315 { "no-flush-func", & m32r_cache_flush_func, \
316 N_("Don't call any cache flush functions") }, \
317 { "flush-func=", & m32r_cache_flush_func, \
318 N_("Specify cache flush function") }, \
319 { "no-flush-trap", & m32r_cache_flush_trap_string, \
320 N_("Don't call any cache flush trap") }, \
321 { "flush-trap=", & m32r_cache_flush_trap_string, \
322 N_("Specify cache flush trap number") } \
328 Code models are used to select between two choices of two separate
329 possibilities (address space size, call insn to use):
331 small: addresses use 24 bits, use bl to make calls
332 medium: addresses use 32 bits, use bl to make calls (*1)
333 large: addresses use 32 bits, use seth/add3/jl to make calls (*2)
335 The fourth is "addresses use 24 bits, use seth/add3/jl to make calls" but
336 using this one doesn't make much sense.
338 (*1) The linker may eventually be able to relax seth/add3 -> ld24.
339 (*2) The linker may eventually be able to relax seth/add3/jl -> bl.
341 Internally these are recorded as TARGET_ADDR{24,32} and
344 The __model__ attribute can be used to select the code model to use when
345 accessing particular objects. */
347 enum m32r_model { M32R_MODEL_SMALL, M32R_MODEL_MEDIUM, M32R_MODEL_LARGE };
349 extern enum m32r_model m32r_model;
350 #define TARGET_MODEL_SMALL (m32r_model == M32R_MODEL_SMALL)
351 #define TARGET_MODEL_MEDIUM (m32r_model == M32R_MODEL_MEDIUM)
352 #define TARGET_MODEL_LARGE (m32r_model == M32R_MODEL_LARGE)
353 #define TARGET_ADDR24 (m32r_model == M32R_MODEL_SMALL)
354 #define TARGET_ADDR32 (! TARGET_ADDR24)
355 #define TARGET_CALL26 (! TARGET_CALL32)
356 #define TARGET_CALL32 (m32r_model == M32R_MODEL_LARGE)
358 /* The default is the small model. */
359 #ifndef M32R_MODEL_DEFAULT
360 #define M32R_MODEL_DEFAULT "small"
365 The SDA consists of sections .sdata, .sbss, and .scommon.
366 .scommon isn't a real section, symbols in it have their section index
367 set to SHN_M32R_SCOMMON, though support for it exists in the linker script.
369 Two switches control the SDA:
371 -G NNN - specifies the maximum size of variable to go in the SDA
373 -msdata=foo - specifies how such variables are handled
375 -msdata=none - small data area is disabled
377 -msdata=sdata - small data goes in the SDA, special code isn't
378 generated to use it, and special relocs aren't
381 -msdata=use - small data goes in the SDA, special code is generated
382 to use the SDA and special relocs are generated
384 The SDA is not multilib'd, it isn't necessary.
385 MULTILIB_EXTRA_OPTS is set in tmake_file to -msdata=sdata so multilib'd
386 libraries have small data in .sdata/SHN_M32R_SCOMMON so programs that use
387 -msdata=use will successfully link with them (references in header files
388 will cause the compiler to emit code that refers to library objects in
389 .data). ??? There can be a problem if the user passes a -G value greater
390 than the default and a library object in a header file is that size.
391 The default is 8 so this should be rare - if it occurs the user
392 is required to rebuild the libraries or use a smaller value for -G. */
394 /* Maximum size of variables that go in .sdata/.sbss.
395 The -msdata=foo switch also controls how small variables are handled. */
396 #ifndef SDATA_DEFAULT_SIZE
397 #define SDATA_DEFAULT_SIZE 8
400 enum m32r_sdata { M32R_SDATA_NONE, M32R_SDATA_SDATA, M32R_SDATA_USE };
402 extern enum m32r_sdata m32r_sdata;
403 #define TARGET_SDATA_NONE (m32r_sdata == M32R_SDATA_NONE)
404 #define TARGET_SDATA_SDATA (m32r_sdata == M32R_SDATA_SDATA)
405 #define TARGET_SDATA_USE (m32r_sdata == M32R_SDATA_USE)
407 /* Default is to disable the SDA
408 [for upward compatibility with previous toolchains]. */
409 #ifndef M32R_SDATA_DEFAULT
410 #define M32R_SDATA_DEFAULT "none"
413 /* Define this macro as a C expression for the initializer of an array of
414 strings to tell the driver program which options are defaults for this
415 target and thus do not need to be handled specially when using
416 `MULTILIB_OPTIONS'. */
417 #ifndef SUBTARGET_MULTILIB_DEFAULTS
418 #define SUBTARGET_MULTILIB_DEFAULTS
421 #ifndef MULTILIB_DEFAULTS
422 #define MULTILIB_DEFAULTS { "mmodel=small" SUBTARGET_MULTILIB_DEFAULTS }
425 /* Sometimes certain combinations of command options do not make
426 sense on a particular target machine. You can define a macro
427 `OVERRIDE_OPTIONS' to take account of this. This macro, if
428 defined, is executed once just after all the command options have
431 Don't use this macro to turn on various extra optimizations for
432 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
434 #ifndef SUBTARGET_OVERRIDE_OPTIONS
435 #define SUBTARGET_OVERRIDE_OPTIONS
438 #define OVERRIDE_OPTIONS \
441 /* These need to be done at start up. \
442 It's convenient to do them here. */ \
444 SUBTARGET_OVERRIDE_OPTIONS \
448 #ifndef SUBTARGET_OPTIMIZATION_OPTIONS
449 #define SUBTARGET_OPTIMIZATION_OPTIONS
452 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
456 flag_regmove = TRUE; \
460 flag_omit_frame_pointer = TRUE; \
461 flag_strength_reduce = FALSE; \
464 SUBTARGET_OPTIMIZATION_OPTIONS \
468 /* Define this macro if debugging can be performed even without a
469 frame pointer. If this macro is defined, GCC will turn on the
470 `-fomit-frame-pointer' option whenever `-O' is specified. */
471 #define CAN_DEBUG_WITHOUT_FP
473 /* Target machine storage layout. */
475 /* Define this if most significant bit is lowest numbered
476 in instructions that operate on numbered bit-fields. */
477 #define BITS_BIG_ENDIAN 1
479 /* Define this if most significant byte of a word is the lowest numbered. */
480 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
482 /* Define this if most significant word of a multiword number is the lowest
484 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
486 /* Define this macro if WORDS_BIG_ENDIAN is not constant. This must
487 be a constant value with the same meaning as WORDS_BIG_ENDIAN,
488 which will be used only when compiling libgcc2.c. Typically the
489 value will be set based on preprocessor defines. */
490 /*#define LIBGCC2_WORDS_BIG_ENDIAN 1*/
492 /* Width of a word, in units (bytes). */
493 #define UNITS_PER_WORD 4
495 /* Define this macro if it is advisable to hold scalars in registers
496 in a wider mode than that declared by the program. In such cases,
497 the value is constrained to be within the bounds of the declared
498 type, but kept valid in the wider mode. The signedness of the
499 extension may differ from that of the type. */
500 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
501 if (GET_MODE_CLASS (MODE) == MODE_INT \
502 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
507 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
508 #define PARM_BOUNDARY 32
510 /* Boundary (in *bits*) on which stack pointer should be aligned. */
511 #define STACK_BOUNDARY 32
513 /* ALIGN FRAMES on word boundaries */
514 #define M32R_STACK_ALIGN(LOC) (((LOC) + 3) & ~ 3)
516 /* Allocation boundary (in *bits*) for the code of a function. */
517 #define FUNCTION_BOUNDARY 32
519 /* Alignment of field after `int : 0' in a structure. */
520 #define EMPTY_FIELD_BOUNDARY 32
522 /* Every structure's size must be a multiple of this. */
523 #define STRUCTURE_SIZE_BOUNDARY 8
525 /* A bit-field declared as `int' forces `int' alignment for the struct. */
526 #define PCC_BITFIELD_TYPE_MATTERS 1
528 /* No data type wants to be aligned rounder than this. */
529 #define BIGGEST_ALIGNMENT 32
531 /* The best alignment to use in cases where we have a choice. */
532 #define FASTEST_ALIGNMENT 32
534 /* Make strings word-aligned so strcpy from constants will be faster. */
535 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
536 ((TREE_CODE (EXP) == STRING_CST \
537 && (ALIGN) < FASTEST_ALIGNMENT) \
538 ? FASTEST_ALIGNMENT : (ALIGN))
540 /* Make arrays of chars word-aligned for the same reasons. */
541 #define DATA_ALIGNMENT(TYPE, ALIGN) \
542 (TREE_CODE (TYPE) == ARRAY_TYPE \
543 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
544 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
546 /* Set this nonzero if move instructions will actually fail to work
547 when given unaligned data. */
548 #define STRICT_ALIGNMENT 1
550 /* Define LAVEL_ALIGN to calculate code length of PNOP at labels. */
551 #define LABEL_ALIGN(insn) 2
553 /* Layout of source language data types. */
555 #define SHORT_TYPE_SIZE 16
556 #define INT_TYPE_SIZE 32
557 #define LONG_TYPE_SIZE 32
558 #define LONG_LONG_TYPE_SIZE 64
559 #define FLOAT_TYPE_SIZE 32
560 #define DOUBLE_TYPE_SIZE 64
561 #define LONG_DOUBLE_TYPE_SIZE 64
563 /* Define this as 1 if `char' should by default be signed; else as 0. */
564 #define DEFAULT_SIGNED_CHAR 1
566 #define SIZE_TYPE "long unsigned int"
567 #define PTRDIFF_TYPE "long int"
568 #define WCHAR_TYPE "short unsigned int"
569 #define WCHAR_TYPE_SIZE 16
571 /* Standard register usage. */
573 /* Number of actual hardware registers.
574 The hardware registers are assigned numbers for the compiler
575 from 0 to just below FIRST_PSEUDO_REGISTER.
576 All registers that the compiler knows about must be given numbers,
577 even those that are not normally considered general registers. */
579 #define M32R_NUM_REGISTERS 19
581 #ifndef SUBTARGET_NUM_REGISTERS
582 #define SUBTARGET_NUM_REGISTERS 0
585 #define FIRST_PSEUDO_REGISTER (M32R_NUM_REGISTERS + SUBTARGET_NUM_REGISTERS)
587 /* 1 for registers that have pervasive standard uses
588 and are not available for the register allocator.
590 0-3 - arguments/results
591 4-5 - call used [4 is used as a tmp during prologue/epilogue generation]
593 7 - call used, static chain pointer
595 12 - call saved [reserved for global pointer]
597 14 - subroutine link register
602 19 - accumulator 1 in the m32r/x
603 By default, the extension registers are not available. */
605 #ifndef SUBTARGET_FIXED_REGISTERS
606 #define SUBTARGET_FIXED_REGISTERS
609 #define FIXED_REGISTERS \
611 0, 0, 0, 0, 0, 0, 0, 0, \
612 0, 0, 0, 0, 0, 0, 0, 1, \
614 SUBTARGET_FIXED_REGISTERS \
617 /* 1 for registers not available across function calls.
618 These must include the FIXED_REGISTERS and also any
619 registers that can be used without being saved.
620 The latter must include the registers where values are returned
621 and the register where structure-value addresses are passed.
622 Aside from that, you can include as many other registers as you like. */
624 #ifndef SUBTARGET_CALL_USED_REGISTERS
625 #define SUBTARGET_CALL_USED_REGISTERS
628 #define CALL_USED_REGISTERS \
630 1, 1, 1, 1, 1, 1, 1, 1, \
631 0, 0, 0, 0, 0, 0, 1, 1, \
633 SUBTARGET_CALL_USED_REGISTERS \
636 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
638 /* Zero or more C statements that may conditionally modify two variables
639 `fixed_regs' and `call_used_regs' (both of type `char []') after they
640 have been initialized from the two preceding macros.
642 This is necessary in case the fixed or call-clobbered registers depend
645 You need not define this macro if it has no work to do. */
647 #ifdef SUBTARGET_CONDITIONAL_REGISTER_USAGE
648 #define CONDITIONAL_REGISTER_USAGE SUBTARGET_CONDITIONAL_REGISTER_USAGE
650 #define CONDITIONAL_REGISTER_USAGE \
655 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
656 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
662 /* If defined, an initializer for a vector of integers, containing the
663 numbers of hard registers in the order in which GCC should
664 prefer to use them (from most preferred to least). */
666 #ifndef SUBTARGET_REG_ALLOC_ORDER
667 #define SUBTARGET_REG_ALLOC_ORDER
670 #if 1 /* Better for int code. */
671 #define REG_ALLOC_ORDER \
673 4, 5, 6, 7, 2, 3, 8, 9, 10, \
674 11, 12, 13, 14, 0, 1, 15, 16, 17, 18 \
675 SUBTARGET_REG_ALLOC_ORDER \
678 #else /* Better for fp code at expense of int code. */
679 #define REG_ALLOC_ORDER \
681 0, 1, 2, 3, 4, 5, 6, 7, 8, \
682 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 \
683 SUBTARGET_REG_ALLOC_ORDER \
687 /* Return number of consecutive hard regs needed starting at reg REGNO
688 to hold something of mode MODE.
689 This is ordinarily the length in words of a value of mode MODE
690 but can be less for certain modes in special long registers. */
691 #define HARD_REGNO_NREGS(REGNO, MODE) \
692 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
694 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
695 extern const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER];
696 extern unsigned int m32r_mode_class[];
697 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
698 ((m32r_hard_regno_mode_ok[REGNO] & m32r_mode_class[MODE]) != 0)
700 /* A C expression that is nonzero if it is desirable to choose
701 register allocation so as to avoid move instructions between a
702 value of mode MODE1 and a value of mode MODE2.
704 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
705 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
706 MODE2)' must be zero. */
708 /* Tie QI/HI/SI modes together. */
709 #define MODES_TIEABLE_P(MODE1, MODE2) \
710 ( GET_MODE_CLASS (MODE1) == MODE_INT \
711 && GET_MODE_CLASS (MODE2) == MODE_INT \
712 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
713 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD)
715 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
716 m32r_hard_regno_rename_ok (OLD_REG, NEW_REG)
718 /* Register classes and constants. */
720 /* Define the classes of registers for register constraints in the
721 machine description. Also define ranges of constants.
723 One of the classes must always be named ALL_REGS and include all hard regs.
724 If there is more than one class, another class must be named NO_REGS
725 and contain no registers.
727 The name GENERAL_REGS must be the name of a class (or an alias for
728 another name such as ALL_REGS). This is the class of registers
729 that is allowed by "g" or "r" in a register constraint.
730 Also, registers outside this class are allocated only when
731 instructions express preferences for them.
733 The classes must be numbered in nondecreasing order; that is,
734 a larger-numbered class must never be contained completely
735 in a smaller-numbered class.
737 For any two classes, it is very desirable that there be another
738 class that represents their union.
740 It is important that any condition codes have class NO_REGS.
741 See `register_operand'. */
745 NO_REGS, CARRY_REG, ACCUM_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
748 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
750 /* Give names of register classes as strings for dump file. */
751 #define REG_CLASS_NAMES \
752 { "NO_REGS", "CARRY_REG", "ACCUM_REGS", "GENERAL_REGS", "ALL_REGS" }
754 /* Define which registers fit in which classes.
755 This is an initializer for a vector of HARD_REG_SET
756 of length N_REG_CLASSES. */
758 #ifndef SUBTARGET_REG_CLASS_CARRY
759 #define SUBTARGET_REG_CLASS_CARRY 0
762 #ifndef SUBTARGET_REG_CLASS_ACCUM
763 #define SUBTARGET_REG_CLASS_ACCUM 0
766 #ifndef SUBTARGET_REG_CLASS_GENERAL
767 #define SUBTARGET_REG_CLASS_GENERAL 0
770 #ifndef SUBTARGET_REG_CLASS_ALL
771 #define SUBTARGET_REG_CLASS_ALL 0
774 #define REG_CLASS_CONTENTS \
777 { 0x20000 | SUBTARGET_REG_CLASS_CARRY }, \
778 { 0x40000 | SUBTARGET_REG_CLASS_ACCUM }, \
779 { 0x1ffff | SUBTARGET_REG_CLASS_GENERAL }, \
780 { 0x7ffff | SUBTARGET_REG_CLASS_ALL }, \
783 /* The same information, inverted:
784 Return the class number of the smallest class containing
785 reg number REGNO. This could be a conditional expression
786 or could index an array. */
787 extern enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
788 #define REGNO_REG_CLASS(REGNO) (m32r_regno_reg_class[REGNO])
790 /* The class value for index registers, and the one for base regs. */
791 #define INDEX_REG_CLASS GENERAL_REGS
792 #define BASE_REG_CLASS GENERAL_REGS
794 #define REG_CLASS_FROM_LETTER(C) \
795 ( (C) == 'c' ? CARRY_REG \
796 : (C) == 'a' ? ACCUM_REGS \
799 /* These assume that REGNO is a hard or pseudo reg number.
800 They give nonzero only if REGNO is a hard reg of the suitable class
801 or a pseudo reg currently allocated to a suitable hard reg.
802 Since they use reg_renumber, they are safe only once reg_renumber
803 has been allocated, which happens in local-alloc.c. */
804 #define REGNO_OK_FOR_BASE_P(REGNO) \
805 ((REGNO) < FIRST_PSEUDO_REGISTER \
806 ? GPR_P (REGNO) || (REGNO) == ARG_POINTER_REGNUM \
807 : GPR_P (reg_renumber[REGNO]))
809 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
811 /* Given an rtx X being reloaded into a reg required to be
812 in class CLASS, return the class of reg to actually use.
813 In general this is just CLASS; but on some machines
814 in some cases it is preferable to use a more restrictive class. */
815 #define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
817 /* Return the maximum number of consecutive registers
818 needed to represent mode MODE in a register of class CLASS. */
819 #define CLASS_MAX_NREGS(CLASS, MODE) \
820 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
822 /* The letters I, J, K, L, M, N, O, P in a register constraint string
823 can be used to stand for particular ranges of immediate operands.
824 This macro defines what the ranges are.
825 C is the letter, and VALUE is a constant value.
826 Return 1 if VALUE is in the range specified by C. */
827 /* 'I' is used for 8 bit signed immediates.
828 'J' is used for 16 bit signed immediates.
829 'K' is used for 16 bit unsigned immediates.
830 'L' is used for 16 bit immediates left shifted by 16 (sign ???).
831 'M' is used for 24 bit unsigned immediates.
832 'N' is used for any 32 bit non-symbolic value.
833 'O' is used for 5 bit unsigned immediates (shift count).
834 'P' is used for 16 bit signed immediates for compares
835 (values in the range -32767 to +32768). */
837 /* Return true if a value is inside a range. */
838 #define IN_RANGE_P(VALUE, LOW, HIGH) \
839 (((unsigned HOST_WIDE_INT)((VALUE) - (LOW))) \
840 <= ((unsigned HOST_WIDE_INT)((HIGH) - (LOW))))
842 /* Local to this file. */
843 #define INT8_P(X) ((X) >= - 0x80 && (X) <= 0x7f)
844 #define INT16_P(X) ((X) >= - 0x8000 && (X) <= 0x7fff)
845 #define CMP_INT16_P(X) ((X) >= - 0x7fff && (X) <= 0x8000)
846 #define UPPER16_P(X) (((X) & 0xffff) == 0 \
847 && ((X) >> 16) >= - 0x8000 \
848 && ((X) >> 16) <= 0x7fff)
849 #define UINT16_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x0000ffff)
850 #define UINT24_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x00ffffff)
851 #define UINT32_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0xffffffff)
852 #define UINT5_P(X) ((X) >= 0 && (X) < 32)
853 #define INVERTED_SIGNED_8BIT(VAL) ((VAL) >= -127 && (VAL) <= 128)
855 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
856 ( (C) == 'I' ? INT8_P (VALUE) \
857 : (C) == 'J' ? INT16_P (VALUE) \
858 : (C) == 'K' ? UINT16_P (VALUE) \
859 : (C) == 'L' ? UPPER16_P (VALUE) \
860 : (C) == 'M' ? UINT24_P (VALUE) \
861 : (C) == 'N' ? INVERTED_SIGNED_8BIT (VALUE) \
862 : (C) == 'O' ? UINT5_P (VALUE) \
863 : (C) == 'P' ? CMP_INT16_P (VALUE) \
866 /* Similar, but for floating constants, and defining letters G and H.
867 Here VALUE is the CONST_DOUBLE rtx itself.
868 For the m32r, handle a few constants inline.
869 ??? We needn't treat DI and DF modes differently, but for now we do. */
870 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
871 ( (C) == 'G' ? easy_di_const (VALUE) \
872 : (C) == 'H' ? easy_df_const (VALUE) \
875 /* A C expression that defines the optional machine-dependent constraint
876 letters that can be used to segregate specific types of operands,
877 usually memory references, for the target machine. It should return 1 if
878 VALUE corresponds to the operand type represented by the constraint letter
879 C. If C is not defined as an extra constraint, the value returned should
880 be 0 regardless of VALUE. */
881 /* Q is for symbolic addresses loadable with ld24.
882 R is for symbolic addresses when ld24 can't be used.
883 S is for stores with pre {inc,dec}rement
884 T is for indirect of a pointer.
885 U is for loads with post increment. */
887 #define EXTRA_CONSTRAINT(VALUE, C) \
888 ( (C) == 'Q' ? ((TARGET_ADDR24 && GET_CODE (VALUE) == LABEL_REF) \
889 || addr24_operand (VALUE, VOIDmode)) \
890 : (C) == 'R' ? ((TARGET_ADDR32 && GET_CODE (VALUE) == LABEL_REF) \
891 || addr32_operand (VALUE, VOIDmode)) \
892 : (C) == 'S' ? (GET_CODE (VALUE) == MEM \
893 && STORE_PREINC_PREDEC_P (GET_MODE (VALUE), \
895 : (C) == 'T' ? (GET_CODE (VALUE) == MEM \
896 && memreg_operand (VALUE, GET_MODE (VALUE))) \
897 : (C) == 'U' ? (GET_CODE (VALUE) == MEM \
898 && LOAD_POSTINC_P (GET_MODE (VALUE), \
902 /* Stack layout and stack pointer usage. */
904 /* Define this macro if pushing a word onto the stack moves the stack
905 pointer to a smaller address. */
906 #define STACK_GROWS_DOWNWARD
908 /* Offset from frame pointer to start allocating local variables at.
909 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
910 first local allocated. Otherwise, it is the offset to the BEGINNING
911 of the first local allocated. */
912 /* The frame pointer points at the same place as the stack pointer, except if
913 alloca has been called. */
914 #define STARTING_FRAME_OFFSET \
915 M32R_STACK_ALIGN (current_function_outgoing_args_size)
917 /* Offset from the stack pointer register to the first location at which
918 outgoing arguments are placed. */
919 #define STACK_POINTER_OFFSET 0
921 /* Offset of first parameter from the argument pointer register value. */
922 #define FIRST_PARM_OFFSET(FNDECL) 0
924 /* Register to use for pushing function arguments. */
925 #define STACK_POINTER_REGNUM 15
927 /* Base register for access to local variables of the function. */
928 #define FRAME_POINTER_REGNUM 13
930 /* Base register for access to arguments of the function. */
931 #define ARG_POINTER_REGNUM 16
933 /* Register in which static-chain is passed to a function.
934 This must not be a register used by the prologue. */
935 #define STATIC_CHAIN_REGNUM 7
937 /* These aren't official macros. */
938 #define PROLOGUE_TMP_REGNUM 4
939 #define RETURN_ADDR_REGNUM 14
940 /* #define GP_REGNUM 12 */
941 #define CARRY_REGNUM 17
942 #define ACCUM_REGNUM 18
943 #define M32R_MAX_INT_REGS 16
945 #ifndef SUBTARGET_GPR_P
946 #define SUBTARGET_GPR_P(REGNO) 0
949 #ifndef SUBTARGET_ACCUM_P
950 #define SUBTARGET_ACCUM_P(REGNO) 0
953 #ifndef SUBTARGET_CARRY_P
954 #define SUBTARGET_CARRY_P(REGNO) 0
957 #define GPR_P(REGNO) (IN_RANGE_P ((REGNO), 0, 15) || SUBTARGET_GPR_P (REGNO))
958 #define ACCUM_P(REGNO) ((REGNO) == ACCUM_REGNUM || SUBTARGET_ACCUM_P (REGNO))
959 #define CARRY_P(REGNO) ((REGNO) == CARRY_REGNUM || SUBTARGET_CARRY_P (REGNO))
961 /* Eliminating the frame and arg pointers. */
963 /* A C expression which is nonzero if a function must have and use a
964 frame pointer. This expression is evaluated in the reload pass.
965 If its value is nonzero the function will have a frame pointer. */
966 #define FRAME_POINTER_REQUIRED current_function_calls_alloca
969 /* C statement to store the difference between the frame pointer
970 and the stack pointer values immediately after the function prologue.
971 If `ELIMINABLE_REGS' is defined, this macro will be not be used and
972 need not be defined. */
973 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
974 ((VAR) = m32r_compute_frame_size (get_frame_size ()))
977 /* If defined, this macro specifies a table of register pairs used to
978 eliminate unneeded registers that point into the stack frame. If
979 it is not defined, the only elimination attempted by the compiler
980 is to replace references to the frame pointer with references to
983 Note that the elimination of the argument pointer with the stack
984 pointer is specified first since that is the preferred elimination. */
986 #define ELIMINABLE_REGS \
987 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
988 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
989 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }}
991 /* A C expression that returns nonzero if the compiler is allowed to
992 try to replace register number FROM-REG with register number
993 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
994 defined, and will usually be the constant 1, since most of the
995 cases preventing register elimination are things that the compiler
996 already knows about. */
998 #define CAN_ELIMINATE(FROM, TO) \
999 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1000 ? ! frame_pointer_needed \
1003 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
1004 specifies the initial difference between the specified pair of
1005 registers. This macro must be defined if `ELIMINABLE_REGS' is
1008 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1011 int size = m32r_compute_frame_size (get_frame_size ()); \
1013 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1015 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
1016 (OFFSET) = size - current_function_pretend_args_size; \
1017 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1018 (OFFSET) = size - current_function_pretend_args_size; \
1024 /* Function argument passing. */
1026 /* If defined, the maximum amount of space required for outgoing
1027 arguments will be computed and placed into the variable
1028 `current_function_outgoing_args_size'. No space will be pushed
1029 onto the stack for each call; instead, the function prologue should
1030 increase the stack frame size by this amount. */
1031 #define ACCUMULATE_OUTGOING_ARGS 1
1033 /* Value is the number of bytes of arguments automatically
1034 popped when returning from a subroutine call.
1035 FUNDECL is the declaration node of the function (as a tree),
1036 FUNTYPE is the data type of the function (as a tree),
1037 or for a library call it is an identifier node for the subroutine name.
1038 SIZE is the number of bytes of arguments passed on the stack. */
1039 #define RETURN_POPS_ARGS(DECL, FUNTYPE, SIZE) 0
1041 /* Define a data type for recording info about an argument list
1042 during the scan of that argument list. This data type should
1043 hold all necessary information about the function itself
1044 and about the args processed so far, enough to enable macros
1045 such as FUNCTION_ARG to determine where the next arg should go. */
1046 #define CUMULATIVE_ARGS int
1048 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1049 for a call to a function whose data type is FNTYPE.
1050 For a library call, FNTYPE is 0. */
1051 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1054 /* The number of registers used for parameter passing. Local to this file. */
1055 #define M32R_MAX_PARM_REGS 4
1057 /* 1 if N is a possible register number for function argument passing. */
1058 #define FUNCTION_ARG_REGNO_P(N) \
1059 ((unsigned) (N) < M32R_MAX_PARM_REGS)
1061 /* The ROUND_ADVANCE* macros are local to this file. */
1062 /* Round SIZE up to a word boundary. */
1063 #define ROUND_ADVANCE(SIZE) \
1064 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1066 /* Round arg MODE/TYPE up to the next word boundary. */
1067 #define ROUND_ADVANCE_ARG(MODE, TYPE) \
1068 ((MODE) == BLKmode \
1069 ? ROUND_ADVANCE ((unsigned int) int_size_in_bytes (TYPE)) \
1070 : ROUND_ADVANCE ((unsigned int) GET_MODE_SIZE (MODE)))
1072 /* Round CUM up to the necessary point for argument MODE/TYPE. */
1073 #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) (CUM)
1075 /* Return boolean indicating arg of type TYPE and mode MODE will be passed in
1076 a reg. This includes arguments that have to be passed by reference as the
1077 pointer to them is passed in a reg if one is available (and that is what
1079 This macro is only used in this file. */
1080 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1081 (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < M32R_MAX_PARM_REGS)
1083 /* Determine where to put an argument to a function.
1084 Value is zero to push the argument on the stack,
1085 or a hard register in which to store the argument.
1087 MODE is the argument's machine mode.
1088 TYPE is the data type of the argument (as a tree).
1089 This is null for libcalls where that information may
1091 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1092 the preceding args and about the function being called.
1093 NAMED is nonzero if this argument is a named parameter
1094 (otherwise it is an extra parameter matching an ellipsis). */
1095 /* On the M32R the first M32R_MAX_PARM_REGS args are normally in registers
1096 and the rest are pushed. */
1097 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1098 (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1099 ? gen_rtx_REG ((MODE), ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE))) \
1102 /* Update the data in CUM to advance over an argument
1103 of mode MODE and data type TYPE.
1104 (TYPE is null for libcalls where that information may not be available.) */
1105 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1106 ((CUM) = (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) \
1107 + ROUND_ADVANCE_ARG ((MODE), (TYPE))))
1109 /* If defined, a C expression that gives the alignment boundary, in bits,
1110 of an argument with the specified mode and type. If it is not defined,
1111 PARM_BOUNDARY is used for all arguments. */
1113 /* We assume PARM_BOUNDARY == UNITS_PER_WORD here. */
1114 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1115 (((TYPE) ? TYPE_ALIGN (TYPE) : GET_MODE_BITSIZE (MODE)) <= PARM_BOUNDARY \
1116 ? PARM_BOUNDARY : 2 * PARM_BOUNDARY)
1119 /* Function results. */
1121 /* Define how to find the value returned by a function.
1122 VALTYPE is the data type of the value (as a tree).
1123 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1124 otherwise, FUNC is 0. */
1125 #define FUNCTION_VALUE(VALTYPE, FUNC) gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
1127 /* Define how to find the value returned by a library function
1128 assuming the value has mode MODE. */
1129 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
1131 /* 1 if N is a possible register number for a function value
1132 as seen by the caller. */
1133 /* ??? What about r1 in DI/DF values. */
1134 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
1136 /* Tell GCC to use TARGET_RETURN_IN_MEMORY. */
1137 #define DEFAULT_PCC_STRUCT_RETURN 0
1139 /* Function entry and exit. */
1141 /* Initialize data used by insn expanders. This is called from
1142 init_emit, once for each function, before code is generated. */
1143 #define INIT_EXPANDERS m32r_init_expanders ()
1145 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1146 the stack pointer does not matter. The value is tested only in
1147 functions that have frame pointers.
1148 No definition is equivalent to always zero. */
1149 #define EXIT_IGNORE_STACK 1
1151 /* Output assembler code to FILE to increment profiler label # LABELNO
1152 for profiling a function entry. */
1153 #undef FUNCTION_PROFILER
1154 #define FUNCTION_PROFILER(FILE, LABELNO) \
1159 fprintf (FILE, "\tld24 r14,#mcount\n"); \
1160 fprintf (FILE, "\tadd r14,r12\n"); \
1161 fprintf (FILE, "\tld r14,@r14\n"); \
1162 fprintf (FILE, "\tjl r14\n"); \
1166 if (TARGET_ADDR24) \
1167 fprintf (FILE, "\tbl mcount\n"); \
1170 fprintf (FILE, "\tseth r14,#high(mcount)\n"); \
1171 fprintf (FILE, "\tor3 r14,r14,#low(mcount)\n"); \
1172 fprintf (FILE, "\tjl r14\n"); \
1175 fprintf (FILE, "\taddi sp,#4\n"); \
1181 /* On the M32R, the trampoline is:
1183 mv r7, lr -> bl L1 ; 178e 7e01
1184 L1: add3 r6, lr, #L2-L1 ; 86ae 000c (L2 - L1 = 12)
1185 mv lr, r7 -> ld r7,@r6+ ; 1e87 27e6
1186 ld r6, @r6 -> jmp r6 ; 26c6 1fc6
1190 #ifndef CACHE_FLUSH_FUNC
1191 #define CACHE_FLUSH_FUNC "_flush_cache"
1193 #ifndef CACHE_FLUSH_TRAP
1194 #define CACHE_FLUSH_TRAP "12"
1197 /* Length in bytes of the trampoline for entering a nested function. */
1198 #define TRAMPOLINE_SIZE 24
1200 /* Emit RTL insns to initialize the variable parts of a trampoline.
1201 FNADDR is an RTX for the address of the function's pure code.
1202 CXT is an RTX for the static chain value for the function. */
1203 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1206 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 0)), \
1208 (TARGET_LITTLE_ENDIAN ? 0x017e8e17 : 0x178e7e01)); \
1209 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 4)), \
1211 (TARGET_LITTLE_ENDIAN ? 0x0c00ae86 : 0x86ae000c)); \
1212 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), \
1214 (TARGET_LITTLE_ENDIAN ? 0xe627871e : 0x1e8727e6)); \
1215 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 12)), \
1217 (TARGET_LITTLE_ENDIAN ? 0xc616c626 : 0x26c61fc6)); \
1218 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 16)), \
1220 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 20)), \
1222 if (m32r_cache_flush_trap_string && m32r_cache_flush_trap_string[0]) \
1223 emit_insn (gen_flush_icache (validize_mem (gen_rtx_MEM (SImode, TRAMP)),\
1224 GEN_INT (m32r_cache_flush_trap) )); \
1225 else if (m32r_cache_flush_func && m32r_cache_flush_func[0]) \
1226 emit_library_call (m32r_function_symbol (m32r_cache_flush_func), \
1227 0, VOIDmode, 3, TRAMP, Pmode, \
1228 GEN_INT (TRAMPOLINE_SIZE), SImode, \
1229 GEN_INT (3), SImode); \
1233 #define RETURN_ADDR_RTX(COUNT, FRAME) m32r_return_addr (COUNT)
1235 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)
1237 /* Addressing modes, and classification of registers for them. */
1239 /* Maximum number of registers that can appear in a valid memory address. */
1240 #define MAX_REGS_PER_ADDRESS 1
1242 /* We have post-inc load and pre-dec,pre-inc store,
1243 but only for 4 byte vals. */
1244 #define HAVE_PRE_DECREMENT 1
1245 #define HAVE_PRE_INCREMENT 1
1246 #define HAVE_POST_INCREMENT 1
1248 /* Recognize any constant value that is a valid address. */
1249 #define CONSTANT_ADDRESS_P(X) \
1250 ( GET_CODE (X) == LABEL_REF \
1251 || GET_CODE (X) == SYMBOL_REF \
1252 || GET_CODE (X) == CONST_INT \
1253 || (GET_CODE (X) == CONST \
1254 && ! (flag_pic && ! m32r_legitimate_pic_operand_p (X))))
1256 /* Nonzero if the constant value X is a legitimate general operand.
1257 We don't allow (plus symbol large-constant) as the relocations can't
1258 describe it. INTVAL > 32767 handles both 16 bit and 24 bit relocations.
1259 We allow all CONST_DOUBLE's as the md file patterns will force the
1260 constant to memory if they can't handle them. */
1262 #define LEGITIMATE_CONSTANT_P(X) \
1263 (! (GET_CODE (X) == CONST \
1264 && GET_CODE (XEXP (X, 0)) == PLUS \
1265 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
1266 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1267 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (X, 0), 1)) > 32767))
1269 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1270 and check its validity for a certain class.
1271 We have two alternate definitions for each of them.
1272 The usual definition accepts all pseudo regs; the other rejects
1273 them unless they have been allocated suitable hard regs.
1274 The symbol REG_OK_STRICT causes the latter definition to be used.
1276 Most source files want to accept pseudo regs in the hope that
1277 they will get allocated to the class that the insn wants them to be in.
1278 Source files for reload pass need to be strict.
1279 After reload, it makes no difference, since pseudo regs have
1280 been eliminated by then. */
1282 #ifdef REG_OK_STRICT
1284 /* Nonzero if X is a hard reg that can be used as a base reg. */
1285 #define REG_OK_FOR_BASE_P(X) GPR_P (REGNO (X))
1286 /* Nonzero if X is a hard reg that can be used as an index. */
1287 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1291 /* Nonzero if X is a hard reg that can be used as a base reg
1292 or if it is a pseudo reg. */
1293 #define REG_OK_FOR_BASE_P(X) \
1294 (GPR_P (REGNO (X)) \
1295 || (REGNO (X)) == ARG_POINTER_REGNUM \
1296 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1297 /* Nonzero if X is a hard reg that can be used as an index
1298 or if it is a pseudo reg. */
1299 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1303 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1304 that is a valid memory address for an instruction.
1305 The MODE argument is the machine mode for the MEM expression
1306 that wants to use this address. */
1308 /* Local to this file. */
1309 #define RTX_OK_FOR_BASE_P(X) (REG_P (X) && REG_OK_FOR_BASE_P (X))
1311 /* Local to this file. */
1312 #define RTX_OK_FOR_OFFSET_P(X) \
1313 (GET_CODE (X) == CONST_INT && INT16_P (INTVAL (X)))
1315 /* Local to this file. */
1316 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X) \
1317 (GET_CODE (X) == PLUS \
1318 && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \
1319 && RTX_OK_FOR_OFFSET_P (XEXP (X, 1)))
1321 /* Local to this file. */
1322 /* For LO_SUM addresses, do not allow them if the MODE is > 1 word,
1323 since more than one instruction will be required. */
1324 #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X) \
1325 (GET_CODE (X) == LO_SUM \
1326 && (MODE != BLKmode && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)\
1327 && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \
1328 && CONSTANT_P (XEXP (X, 1)))
1330 /* Local to this file. */
1331 /* Is this a load and increment operation. */
1332 #define LOAD_POSTINC_P(MODE, X) \
1333 (((MODE) == SImode || (MODE) == SFmode) \
1334 && GET_CODE (X) == POST_INC \
1335 && GET_CODE (XEXP (X, 0)) == REG \
1336 && RTX_OK_FOR_BASE_P (XEXP (X, 0)))
1338 /* Local to this file. */
1339 /* Is this an increment/decrement and store operation. */
1340 #define STORE_PREINC_PREDEC_P(MODE, X) \
1341 (((MODE) == SImode || (MODE) == SFmode) \
1342 && (GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC) \
1343 && GET_CODE (XEXP (X, 0)) == REG \
1344 && RTX_OK_FOR_BASE_P (XEXP (X, 0)))
1346 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1349 if (RTX_OK_FOR_BASE_P (X)) \
1351 if (LEGITIMATE_OFFSET_ADDRESS_P ((MODE), (X))) \
1353 if (LEGITIMATE_LO_SUM_ADDRESS_P ((MODE), (X))) \
1355 if (LOAD_POSTINC_P ((MODE), (X))) \
1357 if (STORE_PREINC_PREDEC_P ((MODE), (X))) \
1362 /* Try machine-dependent ways of modifying an illegitimate address
1363 to be legitimate. If we find one, return the new, valid address.
1364 This macro is used in only one place: `memory_address' in explow.c.
1366 OLDX is the address as it was before break_out_memory_refs was called.
1367 In some cases it is useful to look at this to decide what needs to be done.
1369 MODE and WIN are passed so that this macro can use
1370 GO_IF_LEGITIMATE_ADDRESS.
1372 It is always safe for this macro to do nothing. It exists to recognize
1373 opportunities to optimize the output. */
1375 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1379 (X) = m32r_legitimize_pic_address (X, NULL_RTX); \
1380 if (memory_address_p (MODE, X)) \
1385 /* Go to LABEL if ADDR (a legitimate address expression)
1386 has an effect that depends on the machine mode it is used for. */
1387 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1390 if ( GET_CODE (ADDR) == PRE_DEC \
1391 || GET_CODE (ADDR) == PRE_INC \
1392 || GET_CODE (ADDR) == POST_INC \
1393 || GET_CODE (ADDR) == LO_SUM) \
1398 /* Condition code usage. */
1400 /* Return nonzero if SELECT_CC_MODE will never return MODE for a
1401 floating point inequality comparison. */
1402 #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/
1406 /* Compute extra cost of moving data between one register class
1408 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) 2
1410 /* Compute the cost of moving data between registers and memory. */
1411 /* Memory is 3 times as expensive as registers.
1412 ??? Is that the right way to look at it? */
1413 #define MEMORY_MOVE_COST(MODE,CLASS,IN_P) \
1414 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12)
1416 /* The cost of a branch insn. */
1417 /* A value of 2 here causes GCC to avoid using branches in comparisons like
1418 while (a < N && a). Branches aren't that expensive on the M32R so
1419 we define this as 1. Defining it as 2 had a heavy hit in fp-bit.c. */
1420 #define BRANCH_COST ((TARGET_BRANCH_COST) ? 2 : 1)
1422 /* Nonzero if access to memory by bytes is slow and undesirable.
1423 For RISC chips, it means that access to memory by bytes is no
1424 better than access by words when possible, so grab a whole word
1425 and maybe make use of that. */
1426 #define SLOW_BYTE_ACCESS 1
1428 /* Define this macro if it is as good or better to call a constant
1429 function address than to call an address kept in a register. */
1430 #define NO_FUNCTION_CSE
1432 /* Section selection. */
1434 #define TEXT_SECTION_ASM_OP "\t.section .text"
1435 #define DATA_SECTION_ASM_OP "\t.section .data"
1436 #define BSS_SECTION_ASM_OP "\t.section .bss"
1438 /* Define this macro if jump tables (for tablejump insns) should be
1439 output in the text section, along with the assembler instructions.
1440 Otherwise, the readonly data section is used.
1441 This macro is irrelevant if there is no separate readonly data section. */
1442 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
1444 /* Position Independent Code. */
1446 /* The register number of the register used to address a table of static
1447 data addresses in memory. In some cases this register is defined by a
1448 processor's ``application binary interface'' (ABI). When this macro
1449 is defined, RTL is generated for this register once, as with the stack
1450 pointer and frame pointer registers. If this macro is not defined, it
1451 is up to the machine-dependent files to allocate such a register (if
1453 #define PIC_OFFSET_TABLE_REGNUM 12
1455 /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is
1456 clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM
1458 /* This register is call-saved on the M32R. */
1459 /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/
1461 /* By generating position-independent code, when two different programs (A
1462 and B) share a common library (libC.a), the text of the library can be
1463 shared whether or not the library is linked at the same address for both
1464 programs. In some of these environments, position-independent code
1465 requires not only the use of different addressing modes, but also
1466 special code to enable the use of these addressing modes.
1468 The FINALIZE_PIC macro serves as a hook to emit these special
1469 codes once the function is being compiled into assembly code, but not
1470 before. (It is not done before, because in the case of compiling an
1471 inline function, it would lead to multiple PIC prologues being
1472 included in functions which used inline functions and were compiled to
1473 assembly language.) */
1475 #define FINALIZE_PIC m32r_finalize_pic ()
1477 /* A C expression that is nonzero if X is a legitimate immediate
1478 operand on the target machine when generating position independent code.
1479 You can assume that X satisfies CONSTANT_P, so you need not
1480 check this. You can also assume `flag_pic' is true, so you need not
1481 check it either. You need not define this macro if all constants
1482 (including SYMBOL_REF) can be immediate operands when generating
1483 position independent code. */
1484 #define LEGITIMATE_PIC_OPERAND_P(X) m32r_legitimate_pic_operand_p (X)
1486 /* Control the assembler format that we output. */
1488 /* A C string constant describing how to begin a comment in the target
1489 assembler language. The compiler assumes that the comment will
1490 end at the end of the line. */
1491 #define ASM_COMMENT_START ";"
1493 /* Output to assembler file text saying following lines
1494 may contain character constants, extra white space, comments, etc. */
1495 #define ASM_APP_ON ""
1497 /* Output to assembler file text saying following lines
1498 no longer contain unusual constructs. */
1499 #define ASM_APP_OFF ""
1501 /* Globalizing directive for a label. */
1502 #define GLOBAL_ASM_OP "\t.global\t"
1504 /* We do not use DBX_LINES_FUNCTION_RELATIVE or
1505 dbxout_stab_value_internal_label_diff here because
1506 we need to use .debugsym for the line label. */
1508 #define DBX_OUTPUT_SOURCE_LINE(file, line, counter) \
1511 rtx begin_label = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);\
1513 ASM_GENERATE_INTERNAL_LABEL (label, "LM", counter); \
1515 dbxout_begin_stabn_sline (line); \
1516 assemble_name (file, label); \
1518 assemble_name (file, begin_label); \
1519 fputs ("\n\t.debugsym ", file); \
1520 assemble_name (file, label); \
1521 putc ('\n', file); \
1526 /* How to refer to registers in assembler output.
1527 This sequence is indexed by compiler's hard-register-number (see above). */
1528 #ifndef SUBTARGET_REGISTER_NAMES
1529 #define SUBTARGET_REGISTER_NAMES
1532 #define REGISTER_NAMES \
1534 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1535 "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", \
1536 "ap", "cbit", "a0" \
1537 SUBTARGET_REGISTER_NAMES \
1540 /* If defined, a C initializer for an array of structures containing
1541 a name and a register number. This macro defines additional names
1542 for hard registers, thus allowing the `asm' option in declarations
1543 to refer to registers using alternate names. */
1544 #ifndef SUBTARGET_ADDITIONAL_REGISTER_NAMES
1545 #define SUBTARGET_ADDITIONAL_REGISTER_NAMES
1548 #define ADDITIONAL_REGISTER_NAMES \
1550 /*{ "gp", GP_REGNUM },*/ \
1551 { "r13", FRAME_POINTER_REGNUM }, \
1552 { "r14", RETURN_ADDR_REGNUM }, \
1553 { "r15", STACK_POINTER_REGNUM }, \
1554 SUBTARGET_ADDITIONAL_REGISTER_NAMES \
1557 /* A C expression which evaluates to true if CODE is a valid
1558 punctuation character for use in the `PRINT_OPERAND' macro. */
1559 extern char m32r_punct_chars[256];
1560 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1561 m32r_punct_chars[(unsigned char) (CHAR)]
1563 /* Print operand X (an rtx) in assembler syntax to file FILE.
1564 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1565 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1566 #define PRINT_OPERAND(FILE, X, CODE) \
1567 m32r_print_operand (FILE, X, CODE)
1569 /* A C compound statement to output to stdio stream STREAM the
1570 assembler syntax for an instruction operand that is a memory
1571 reference whose address is ADDR. ADDR is an RTL expression. */
1572 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1573 m32r_print_operand_address (FILE, ADDR)
1575 /* If defined, C string expressions to be used for the `%R', `%L',
1576 `%U', and `%I' options of `asm_fprintf' (see `final.c'). These
1577 are useful when a single `md' file must support multiple assembler
1578 formats. In that case, the various `tm.h' files can define these
1579 macros differently. */
1580 #define REGISTER_PREFIX ""
1581 #define LOCAL_LABEL_PREFIX ".L"
1582 #define USER_LABEL_PREFIX ""
1583 #define IMMEDIATE_PREFIX "#"
1585 /* This is how to output an element of a case-vector that is absolute. */
1586 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1590 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1591 fprintf (FILE, "\t.word\t"); \
1592 assemble_name (FILE, label); \
1593 fprintf (FILE, "\n"); \
1597 /* This is how to output an element of a case-vector that is relative. */
1598 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)\
1602 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1603 fprintf (FILE, "\t.word\t"); \
1604 assemble_name (FILE, label); \
1605 fprintf (FILE, "-"); \
1606 ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \
1607 assemble_name (FILE, label); \
1608 fprintf (FILE, "\n"); \
1612 /* The desired alignment for the location counter at the beginning
1614 /* On the M32R, align loops to 32 byte boundaries (cache line size)
1615 if -malign-loops. */
1616 #define LOOP_ALIGN(LABEL) (TARGET_ALIGN_LOOPS ? 5 : 0)
1618 /* Define this to be the maximum number of insns to move around when moving
1619 a loop test from the top of a loop to the bottom
1620 and seeing whether to duplicate it. The default is thirty.
1622 Loop unrolling currently doesn't like this optimization, so
1623 disable doing if we are unrolling loops and saving space. */
1624 #define LOOP_TEST_THRESHOLD (optimize_size \
1625 && !flag_unroll_loops \
1626 && !flag_unroll_all_loops ? 2 : 30)
1628 /* This is how to output an assembler line
1629 that says to advance the location counter
1630 to a multiple of 2**LOG bytes. */
1631 /* .balign is used to avoid confusion. */
1632 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1636 fprintf (FILE, "\t.balign %d\n", 1 << (LOG)); \
1640 /* Like `ASM_OUTPUT_COMMON' except takes the required alignment as a
1641 separate, explicit argument. If you define this macro, it is used in
1642 place of `ASM_OUTPUT_COMMON', and gives you more flexibility in
1643 handling the required alignment of the variable. The alignment is
1644 specified as the number of bits. */
1646 #define SCOMMON_ASM_OP "\t.scomm\t"
1648 #undef ASM_OUTPUT_ALIGNED_COMMON
1649 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
1652 if (! TARGET_SDATA_NONE \
1653 && (SIZE) > 0 && (SIZE) <= g_switch_value) \
1654 fprintf ((FILE), "%s", SCOMMON_ASM_OP); \
1656 fprintf ((FILE), "%s", COMMON_ASM_OP); \
1657 assemble_name ((FILE), (NAME)); \
1658 fprintf ((FILE), ",%u,%u\n", (int)(SIZE), (ALIGN) / BITS_PER_UNIT);\
1662 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1665 if (! TARGET_SDATA_NONE \
1666 && (SIZE) > 0 && (SIZE) <= g_switch_value) \
1667 named_section (0, ".sbss", 0); \
1670 ASM_OUTPUT_ALIGN (FILE, floor_log2 (ALIGN / BITS_PER_UNIT)); \
1671 last_assemble_variable_decl = DECL; \
1672 ASM_DECLARE_OBJECT_NAME (FILE, NAME, DECL); \
1673 ASM_OUTPUT_SKIP (FILE, SIZE ? SIZE : 1); \
1677 /* Debugging information. */
1679 /* Generate DBX and DWARF debugging information. */
1680 #define DBX_DEBUGGING_INFO 1
1681 #define DWARF2_DEBUGGING_INFO 1
1683 /* Use DWARF2 debugging info by default. */
1684 #undef PREFERRED_DEBUGGING_TYPE
1685 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1687 /* Turn off splitting of long stabs. */
1688 #define DBX_CONTIN_LENGTH 0
1690 /* Miscellaneous. */
1692 /* Specify the machine mode that this machine uses
1693 for the index in the tablejump instruction. */
1694 #define CASE_VECTOR_MODE (flag_pic ? SImode : Pmode)
1696 /* Define if operations between registers always perform the operation
1697 on the full register even if a narrower mode is specified. */
1698 #define WORD_REGISTER_OPERATIONS
1700 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1701 will either zero-extend or sign-extend. The value of this macro should
1702 be the code that says which one of the two operations is implicitly
1703 done, UNKNOWN if none. */
1704 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1706 /* Max number of bytes we can move from memory
1707 to memory in one reasonably fast instruction. */
1710 /* Define this to be nonzero if shift instructions ignore all but the low-order
1712 #define SHIFT_COUNT_TRUNCATED 1
1714 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1715 is done just by pretending it is already truncated. */
1716 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1718 /* Specify the machine mode that pointers have.
1719 After generation of rtl, the compiler makes no further distinction
1720 between pointers and any other objects of this machine mode. */
1721 /* ??? The M32R doesn't have full 32 bit pointers, but making this PSImode has
1722 it's own problems (you have to add extendpsisi2 and truncsipsi2).
1724 #define Pmode SImode
1726 /* A function address in a call instruction. */
1727 #define FUNCTION_MODE SImode
1729 /* Define the information needed to generate branch and scc insns. This is
1730 stored from the compare operation. Note that we can't use "rtx" here
1731 since it hasn't been defined! */
1732 extern struct rtx_def * m32r_compare_op0;
1733 extern struct rtx_def * m32r_compare_op1;
1735 /* M32R function types. */
1736 enum m32r_function_type
1738 M32R_FUNCTION_UNKNOWN, M32R_FUNCTION_NORMAL, M32R_FUNCTION_INTERRUPT
1741 #define M32R_INTERRUPT_P(TYPE) ((TYPE) == M32R_FUNCTION_INTERRUPT)
1743 /* Define this if you have defined special-purpose predicates in the
1744 file `MACHINE.c'. This macro is called within an initializer of an
1745 array of structures. The first field in the structure is the name
1746 of a predicate and the second field is an array of rtl codes. For
1747 each predicate, list all rtl codes that can be in expressions
1748 matched by the predicate. The list should have a trailing comma. */
1750 #define PREDICATE_CODES \
1751 { "reg_or_zero_operand", { REG, SUBREG, CONST_INT }}, \
1752 { "conditional_move_operand", { REG, SUBREG, CONST_INT }}, \
1753 { "carry_compare_operand", { EQ, NE }}, \
1754 { "eqne_comparison_operator", { EQ, NE }}, \
1755 { "signed_comparison_operator", { EQ, NE, LT, LE, GT, GE }}, \
1756 { "move_dest_operand", { REG, SUBREG, MEM }}, \
1757 { "move_src_operand", { REG, SUBREG, MEM, CONST_INT, \
1758 CONST_DOUBLE, LABEL_REF, CONST, \
1760 { "move_double_src_operand", { REG, SUBREG, MEM, CONST_INT, \
1762 { "two_insn_const_operand", { CONST_INT }}, \
1763 { "symbolic_operand", { SYMBOL_REF, LABEL_REF, CONST }}, \
1764 { "int8_operand", { CONST_INT }}, \
1765 { "uint16_operand", { CONST_INT }}, \
1766 { "reg_or_int16_operand", { REG, SUBREG, CONST_INT }}, \
1767 { "reg_or_uint16_operand", { REG, SUBREG, CONST_INT }}, \
1768 { "reg_or_cmp_int16_operand", { REG, SUBREG, CONST_INT }}, \
1769 { "reg_or_eq_int16_operand", { REG, SUBREG, CONST_INT }}, \
1770 { "cmp_int16_operand", { CONST_INT }}, \
1771 { "call_address_operand", { SYMBOL_REF, LABEL_REF, CONST }}, \
1772 { "extend_operand", { REG, SUBREG, MEM }}, \
1773 { "small_insn_p", { INSN, CALL_INSN, JUMP_INSN }}, \
1774 { "m32r_block_immediate_operand",{ CONST_INT }}, \
1775 { "large_insn_p", { INSN, CALL_INSN, JUMP_INSN }}, \
1776 { "seth_add3_operand", { SYMBOL_REF, LABEL_REF, CONST }},
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