1 /* Subroutines used for code generation on the Mitsubishi M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
31 #include "insn-attr.h"
38 #include "m32r-protos.h"
40 #include "target-def.h"
42 /* Save the operands last given to a compare for use when we
43 generate a scc or bcc insn. */
44 rtx m32r_compare_op0, m32r_compare_op1;
46 /* Array of valid operand punctuation characters. */
47 char m32r_punct_chars[256];
49 /* Selected code model. */
50 const char * m32r_model_string = M32R_MODEL_DEFAULT;
51 enum m32r_model m32r_model;
53 /* Selected SDA support. */
54 const char * m32r_sdata_string = M32R_SDATA_DEFAULT;
55 enum m32r_sdata m32r_sdata;
57 /* Scheduler support */
58 int m32r_sched_odd_word_p;
60 /* Forward declaration. */
61 static void init_reg_tables PARAMS ((void));
62 static void block_move_call PARAMS ((rtx, rtx, rtx));
63 static int m32r_is_insn PARAMS ((rtx));
64 static int m32r_valid_decl_attribute PARAMS ((tree, tree,
67 /* Initialize the GCC target structure. */
68 #undef TARGET_VALID_DECL_ATTRIBUTE
69 #define TARGET_VALID_DECL_ATTRIBUTE m32r_valid_decl_attribute
71 struct gcc_target target = TARGET_INITIALIZER;
73 /* Called by OVERRIDE_OPTIONS to initialize various things. */
80 /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */
81 memset (m32r_punct_chars, 0, sizeof (m32r_punct_chars));
82 m32r_punct_chars['#'] = 1;
83 m32r_punct_chars['@'] = 1; /* ??? no longer used */
85 /* Provide default value if not specified. */
87 g_switch_value = SDATA_DEFAULT_SIZE;
89 if (strcmp (m32r_model_string, "small") == 0)
90 m32r_model = M32R_MODEL_SMALL;
91 else if (strcmp (m32r_model_string, "medium") == 0)
92 m32r_model = M32R_MODEL_MEDIUM;
93 else if (strcmp (m32r_model_string, "large") == 0)
94 m32r_model = M32R_MODEL_LARGE;
96 error ("bad value (%s) for -mmodel switch", m32r_model_string);
98 if (strcmp (m32r_sdata_string, "none") == 0)
99 m32r_sdata = M32R_SDATA_NONE;
100 else if (strcmp (m32r_sdata_string, "sdata") == 0)
101 m32r_sdata = M32R_SDATA_SDATA;
102 else if (strcmp (m32r_sdata_string, "use") == 0)
103 m32r_sdata = M32R_SDATA_USE;
105 error ("bad value (%s) for -msdata switch", m32r_sdata_string);
108 /* Vectors to keep interesting information about registers where it can easily
109 be got. We use to use the actual mode value as the bit number, but there
110 is (or may be) more than 32 modes now. Instead we use two tables: one
111 indexed by hard register number, and one indexed by mode. */
113 /* The purpose of m32r_mode_class is to shrink the range of modes so that
114 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
115 mapped into one m32r_mode_class mode. */
120 S_MODE, D_MODE, T_MODE, O_MODE,
121 SF_MODE, DF_MODE, TF_MODE, OF_MODE, A_MODE
124 /* Modes for condition codes. */
125 #define C_MODES (1 << (int) C_MODE)
127 /* Modes for single-word and smaller quantities. */
128 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
130 /* Modes for double-word and smaller quantities. */
131 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
133 /* Modes for quad-word and smaller quantities. */
134 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
136 /* Modes for accumulators. */
137 #define A_MODES (1 << (int) A_MODE)
139 /* Value is 1 if register/mode pair is acceptable on arc. */
141 unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
143 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
144 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
145 S_MODES, C_MODES, A_MODES
148 unsigned int m32r_mode_class [NUM_MACHINE_MODES];
150 enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
157 for (i = 0; i < NUM_MACHINE_MODES; i++)
159 switch (GET_MODE_CLASS (i))
162 case MODE_PARTIAL_INT:
163 case MODE_COMPLEX_INT:
164 if (GET_MODE_SIZE (i) <= 4)
165 m32r_mode_class[i] = 1 << (int) S_MODE;
166 else if (GET_MODE_SIZE (i) == 8)
167 m32r_mode_class[i] = 1 << (int) D_MODE;
168 else if (GET_MODE_SIZE (i) == 16)
169 m32r_mode_class[i] = 1 << (int) T_MODE;
170 else if (GET_MODE_SIZE (i) == 32)
171 m32r_mode_class[i] = 1 << (int) O_MODE;
173 m32r_mode_class[i] = 0;
176 case MODE_COMPLEX_FLOAT:
177 if (GET_MODE_SIZE (i) <= 4)
178 m32r_mode_class[i] = 1 << (int) SF_MODE;
179 else if (GET_MODE_SIZE (i) == 8)
180 m32r_mode_class[i] = 1 << (int) DF_MODE;
181 else if (GET_MODE_SIZE (i) == 16)
182 m32r_mode_class[i] = 1 << (int) TF_MODE;
183 else if (GET_MODE_SIZE (i) == 32)
184 m32r_mode_class[i] = 1 << (int) OF_MODE;
186 m32r_mode_class[i] = 0;
190 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
191 we must explicitly check for them here. */
192 if (i == (int) CCmode)
193 m32r_mode_class[i] = 1 << (int) C_MODE;
195 m32r_mode_class[i] = 0;
200 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
203 m32r_regno_reg_class[i] = GENERAL_REGS;
204 else if (i == ARG_POINTER_REGNUM)
205 m32r_regno_reg_class[i] = GENERAL_REGS;
207 m32r_regno_reg_class[i] = NO_REGS;
211 /* M32R specific attribute support.
213 interrupt - for interrupt functions
215 model - select code model used to access object
217 small: addresses use 24 bits, use bl to make calls
218 medium: addresses use 32 bits, use bl to make calls
219 large: addresses use 32 bits, use seth/add3/jl to make calls
221 Grep for MODEL in m32r.h for more info.
224 static tree interrupt_ident1;
225 static tree interrupt_ident2;
226 static tree model_ident1;
227 static tree model_ident2;
228 static tree small_ident1;
229 static tree small_ident2;
230 static tree medium_ident1;
231 static tree medium_ident2;
232 static tree large_ident1;
233 static tree large_ident2;
236 init_idents PARAMS ((void))
238 if (interrupt_ident1 == 0)
240 interrupt_ident1 = get_identifier ("interrupt");
241 interrupt_ident2 = get_identifier ("__interrupt__");
242 model_ident1 = get_identifier ("model");
243 model_ident2 = get_identifier ("__model__");
244 small_ident1 = get_identifier ("small");
245 small_ident2 = get_identifier ("__small__");
246 medium_ident1 = get_identifier ("medium");
247 medium_ident2 = get_identifier ("__medium__");
248 large_ident1 = get_identifier ("large");
249 large_ident2 = get_identifier ("__large__");
253 /* Return nonzero if IDENTIFIER is a valid decl attribute. */
256 m32r_valid_decl_attribute (type, attributes, identifier, args)
257 tree type ATTRIBUTE_UNUSED;
258 tree attributes ATTRIBUTE_UNUSED;
264 if ((identifier == interrupt_ident1
265 || identifier == interrupt_ident2)
266 && list_length (args) == 0)
269 if ((identifier == model_ident1
270 || identifier == model_ident2)
271 && list_length (args) == 1
272 && (TREE_VALUE (args) == small_ident1
273 || TREE_VALUE (args) == small_ident2
274 || TREE_VALUE (args) == medium_ident1
275 || TREE_VALUE (args) == medium_ident2
276 || TREE_VALUE (args) == large_ident1
277 || TREE_VALUE (args) == large_ident2))
283 /* A C statement or statements to switch to the appropriate
284 section for output of DECL. DECL is either a `VAR_DECL' node
285 or a constant of some sort. RELOC indicates whether forming
286 the initial value of DECL requires link-time relocations. */
289 m32r_select_section (decl, reloc)
293 if (TREE_CODE (decl) == STRING_CST)
295 if (! flag_writable_strings)
300 else if (TREE_CODE (decl) == VAR_DECL)
302 if (SDATA_NAME_P (XSTR (XEXP (DECL_RTL (decl), 0), 0)))
304 else if ((flag_pic && reloc)
305 || !TREE_READONLY (decl)
306 || TREE_SIDE_EFFECTS (decl)
307 || !DECL_INITIAL (decl)
308 || (DECL_INITIAL (decl) != error_mark_node
309 && !TREE_CONSTANT (DECL_INITIAL (decl))))
318 /* Encode section information of DECL, which is either a VAR_DECL,
319 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
321 For the M32R we want to record:
323 - whether the object lives in .sdata/.sbss.
324 objects living in .sdata/.sbss are prefixed with SDATA_FLAG_CHAR
326 - what code model should be used to access the object
327 small: recorded with no flag - for space efficiency since they'll
329 medium: prefixed with MEDIUM_FLAG_CHAR
330 large: prefixed with LARGE_FLAG_CHAR
334 m32r_encode_section_info (decl)
340 switch (TREE_CODE (decl))
344 model = lookup_attribute ("model", DECL_MACHINE_ATTRIBUTES (decl));
348 /* ??? document all others that can appear here */
353 /* Only mark the object as being small data area addressable if
354 it hasn't been explicitly marked with a code model.
356 The user can explicitly put an object in the small data area with the
357 section attribute. If the object is in sdata/sbss and marked with a
358 code model do both [put the object in .sdata and mark it as being
359 addressed with a specific code model - don't mark it as being addressed
360 with an SDA reloc though]. This is ok and might be useful at times. If
361 the object doesn't fit the linker will give an error. */
365 if (TREE_CODE_CLASS (TREE_CODE (decl)) == 'd'
366 && DECL_SECTION_NAME (decl) != NULL_TREE)
368 char *name = (char *) TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
369 if (! strcmp (name, ".sdata") || ! strcmp (name, ".sbss"))
371 #if 0 /* ??? There's no reason to disallow this, is there? */
372 if (TREE_READONLY (decl))
373 error_with_decl (decl, "const objects cannot go in .sdata/.sbss");
375 prefix = SDATA_FLAG_CHAR;
380 if (TREE_CODE (decl) == VAR_DECL
381 && ! TREE_READONLY (decl)
382 && ! TARGET_SDATA_NONE)
384 int size = int_size_in_bytes (TREE_TYPE (decl));
386 if (size > 0 && size <= g_switch_value)
387 prefix = SDATA_FLAG_CHAR;
392 /* If data area not decided yet, check for a code model. */
401 id = TREE_VALUE (TREE_VALUE (model));
403 if (id == small_ident1 || id == small_ident2)
404 ; /* don't mark the symbol specially */
405 else if (id == medium_ident1 || id == medium_ident2)
406 prefix = MEDIUM_FLAG_CHAR;
407 else if (id == large_ident1 || id == large_ident2)
408 prefix = LARGE_FLAG_CHAR;
410 abort (); /* shouldn't happen */
414 if (TARGET_MODEL_SMALL)
415 ; /* don't mark the symbol specially */
416 else if (TARGET_MODEL_MEDIUM)
417 prefix = MEDIUM_FLAG_CHAR;
418 else if (TARGET_MODEL_LARGE)
419 prefix = LARGE_FLAG_CHAR;
421 abort (); /* shouldn't happen */
427 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd'
428 ? TREE_CST_RTL (decl) : DECL_RTL (decl));
429 const char *str = XSTR (XEXP (rtl, 0), 0);
430 int len = strlen (str);
431 char *newstr = ggc_alloc (len + 2);
433 strcpy (newstr + 1, str);
435 XSTR (XEXP (rtl, 0), 0) = newstr;
439 /* Do anything needed before RTL is emitted for each function. */
442 m32r_init_expanders ()
444 /* ??? At one point there was code here. The function is left in
445 to make it easy to experiment. */
448 /* Acceptable arguments to the call insn. */
451 call_address_operand (op, mode)
453 enum machine_mode mode;
455 return symbolic_operand (op, mode);
457 /* Constants and values in registers are not OK, because
458 the m32r BL instruction can only support PC relative branching. */
462 call_operand (op, mode)
464 enum machine_mode mode;
466 if (GET_CODE (op) != MEM)
469 return call_address_operand (op, mode);
472 /* Returns 1 if OP is a symbol reference. */
475 symbolic_operand (op, mode)
477 enum machine_mode mode ATTRIBUTE_UNUSED;
479 switch (GET_CODE (op))
491 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */
494 small_data_operand (op, mode)
496 enum machine_mode mode ATTRIBUTE_UNUSED;
498 if (! TARGET_SDATA_USE)
501 if (GET_CODE (op) == SYMBOL_REF)
502 return SDATA_NAME_P (XSTR (op, 0));
504 if (GET_CODE (op) == CONST
505 && GET_CODE (XEXP (op, 0)) == PLUS
506 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
507 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
508 && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
509 return SDATA_NAME_P (XSTR (XEXP (XEXP (op, 0), 0), 0));
514 /* Return 1 if OP is a symbol that can use 24 bit addressing. */
517 addr24_operand (op, mode)
519 enum machine_mode mode ATTRIBUTE_UNUSED;
521 if (GET_CODE (op) == LABEL_REF)
522 return TARGET_ADDR24;
524 if (GET_CODE (op) == SYMBOL_REF)
525 return (SMALL_NAME_P (XSTR (op, 0))
527 && (CONSTANT_POOL_ADDRESS_P (op)
528 || LIT_NAME_P (XSTR (op, 0)))));
530 if (GET_CODE (op) == CONST
531 && GET_CODE (XEXP (op, 0)) == PLUS
532 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
533 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
534 && UINT24_P (INTVAL (XEXP (XEXP (op, 0), 1))))
536 rtx sym = XEXP (XEXP (op, 0), 0);
537 return (SMALL_NAME_P (XSTR (sym, 0))
539 && (CONSTANT_POOL_ADDRESS_P (op)
540 || LIT_NAME_P (XSTR (op, 0)))));
546 /* Return 1 if OP is a symbol that needs 32 bit addressing. */
549 addr32_operand (op, mode)
551 enum machine_mode mode;
553 if (GET_CODE (op) == LABEL_REF)
554 return TARGET_ADDR32;
556 if (GET_CODE (op) == SYMBOL_REF)
557 return (! addr24_operand (op, mode)
558 && ! small_data_operand (op, mode));
560 if (GET_CODE (op) == CONST
561 && GET_CODE (XEXP (op, 0)) == PLUS
562 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
563 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
565 return (! addr24_operand (op, mode)
566 && ! small_data_operand (op, mode));
572 /* Return 1 if OP is a function that can be called with the `bl' insn. */
575 call26_operand (op, mode)
577 enum machine_mode mode ATTRIBUTE_UNUSED;
579 if (GET_CODE (op) == SYMBOL_REF)
580 return ! LARGE_NAME_P (XSTR (op, 0));
582 return TARGET_CALL26;
585 /* Returns 1 if OP is an acceptable operand for seth/add3. */
588 seth_add3_operand (op, mode)
590 enum machine_mode mode ATTRIBUTE_UNUSED;
592 if (GET_CODE (op) == SYMBOL_REF
593 || GET_CODE (op) == LABEL_REF)
596 if (GET_CODE (op) == CONST
597 && GET_CODE (XEXP (op, 0)) == PLUS
598 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
599 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
600 && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
606 /* Return true if OP is a signed 8 bit immediate value. */
609 int8_operand (op, mode)
611 enum machine_mode mode ATTRIBUTE_UNUSED;
613 if (GET_CODE (op) != CONST_INT)
615 return INT8_P (INTVAL (op));
618 /* Return true if OP is a signed 16 bit immediate value
619 useful in comparisons. */
622 cmp_int16_operand (op, mode)
624 enum machine_mode mode ATTRIBUTE_UNUSED;
626 if (GET_CODE (op) != CONST_INT)
628 return CMP_INT16_P (INTVAL (op));
631 /* Return true if OP is an unsigned 16 bit immediate value. */
634 uint16_operand (op, mode)
636 enum machine_mode mode ATTRIBUTE_UNUSED;
638 if (GET_CODE (op) != CONST_INT)
640 return UINT16_P (INTVAL (op));
643 /* Return true if OP is a register or signed 16 bit value. */
646 reg_or_int16_operand (op, mode)
648 enum machine_mode mode;
650 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
651 return register_operand (op, mode);
652 if (GET_CODE (op) != CONST_INT)
654 return INT16_P (INTVAL (op));
657 /* Return true if OP is a register or an unsigned 16 bit value. */
660 reg_or_uint16_operand (op, mode)
662 enum machine_mode mode;
664 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
665 return register_operand (op, mode);
666 if (GET_CODE (op) != CONST_INT)
668 return UINT16_P (INTVAL (op));
671 /* Return true if OP is a register or an integer value that can be
672 used is SEQ/SNE. We can use either XOR of the value or ADD of
673 the negative of the value for the constant. Don't allow 0,
674 because that is special cased. */
677 reg_or_eq_int16_operand (op, mode)
679 enum machine_mode mode;
683 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
684 return register_operand (op, mode);
686 if (GET_CODE (op) != CONST_INT)
690 return (value != 0) && (UINT16_P (value) || CMP_INT16_P (-value));
693 /* Return true if OP is a register or signed 16 bit value for compares. */
696 reg_or_cmp_int16_operand (op, mode)
698 enum machine_mode mode;
700 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
701 return register_operand (op, mode);
702 if (GET_CODE (op) != CONST_INT)
704 return CMP_INT16_P (INTVAL (op));
707 /* Return true if OP is a const_int requiring two instructions to load. */
710 two_insn_const_operand (op, mode)
712 enum machine_mode mode ATTRIBUTE_UNUSED;
714 if (GET_CODE (op) != CONST_INT)
716 if (INT16_P (INTVAL (op))
717 || UINT24_P (INTVAL (op))
718 || UPPER16_P (INTVAL (op)))
723 /* Return true if OP is an acceptable argument for a single word
727 move_src_operand (op, mode)
729 enum machine_mode mode;
731 switch (GET_CODE (op))
735 return addr24_operand (op, mode);
737 /* ??? We allow more cse opportunities if we only allow constants
738 loadable with one insn, and split the rest into two. The instances
739 where this would help should be rare and the current way is
741 return UINT32_P (INTVAL (op));
743 return TARGET_ADDR24;
747 else if (mode == SImode)
749 /* Large unsigned constants are represented as const_double's. */
750 unsigned HOST_WIDE_INT low, high;
752 low = CONST_DOUBLE_LOW (op);
753 high = CONST_DOUBLE_HIGH (op);
754 return high == 0 && low <= 0xffffffff;
759 return register_operand (op, mode);
761 /* (subreg (mem ...) ...) can occur here if the inner part was once a
762 pseudo-reg and is now a stack slot. */
763 if (GET_CODE (SUBREG_REG (op)) == MEM)
764 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
766 return register_operand (op, mode);
768 if (GET_CODE (XEXP (op, 0)) == PRE_INC
769 || GET_CODE (XEXP (op, 0)) == PRE_DEC)
770 return 0; /* loads can't do pre-{inc,dec} */
771 return address_operand (XEXP (op, 0), mode);
777 /* Return true if OP is an acceptable argument for a double word
781 move_double_src_operand (op, mode)
783 enum machine_mode mode;
785 switch (GET_CODE (op))
791 return register_operand (op, mode);
793 /* (subreg (mem ...) ...) can occur here if the inner part was once a
794 pseudo-reg and is now a stack slot. */
795 if (GET_CODE (SUBREG_REG (op)) == MEM)
796 return move_double_src_operand (SUBREG_REG (op), mode);
798 return register_operand (op, mode);
800 /* Disallow auto inc/dec for now. */
801 if (GET_CODE (XEXP (op, 0)) == PRE_DEC
802 || GET_CODE (XEXP (op, 0)) == PRE_INC)
804 return address_operand (XEXP (op, 0), mode);
810 /* Return true if OP is an acceptable argument for a move destination. */
813 move_dest_operand (op, mode)
815 enum machine_mode mode;
817 switch (GET_CODE (op))
820 return register_operand (op, mode);
822 /* (subreg (mem ...) ...) can occur here if the inner part was once a
823 pseudo-reg and is now a stack slot. */
824 if (GET_CODE (SUBREG_REG (op)) == MEM)
825 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
827 return register_operand (op, mode);
829 if (GET_CODE (XEXP (op, 0)) == POST_INC)
830 return 0; /* stores can't do post inc */
831 return address_operand (XEXP (op, 0), mode);
837 /* Return 1 if OP is a DImode const we want to handle inline.
838 This must match the code in the movdi pattern.
839 It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER. */
845 rtx high_rtx, low_rtx;
846 HOST_WIDE_INT high, low;
848 split_double (op, &high_rtx, &low_rtx);
849 high = INTVAL (high_rtx);
850 low = INTVAL (low_rtx);
851 /* Pick constants loadable with 2 16 bit `ldi' insns. */
852 if (high >= -128 && high <= 127
853 && low >= -128 && low <= 127)
858 /* Return 1 if OP is a DFmode const we want to handle inline.
859 This must match the code in the movdf pattern.
860 It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER. */
869 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
870 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
871 if (l[0] == 0 && l[1] == 0)
873 if ((l[0] & 0xffff) == 0 && l[1] == 0)
878 /* Return 1 if OP is an EQ or NE comparison operator. */
881 eqne_comparison_operator (op, mode)
883 enum machine_mode mode ATTRIBUTE_UNUSED;
885 enum rtx_code code = GET_CODE (op);
887 if (GET_RTX_CLASS (code) != '<')
889 return (code == EQ || code == NE);
892 /* Return 1 if OP is a signed comparison operator. */
895 signed_comparison_operator (op, mode)
897 enum machine_mode mode ATTRIBUTE_UNUSED;
899 enum rtx_code code = GET_CODE (op);
901 if (GET_RTX_CLASS (code) != '<')
903 return (code == EQ || code == NE
904 || code == LT || code == LE || code == GT || code == GE);
907 /* Return 1 if OP is (mem (reg ...)).
908 This is used in insn length calcs. */
911 memreg_operand (op, mode)
913 enum machine_mode mode ATTRIBUTE_UNUSED;
915 return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == REG;
918 /* Return true if OP is an acceptable input argument for a zero/sign extend
922 extend_operand (op, mode)
924 enum machine_mode mode;
928 switch (GET_CODE (op))
932 return register_operand (op, mode);
936 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
937 return 0; /* loads can't do pre inc/pre dec */
939 return address_operand (addr, mode);
946 /* Return non-zero if the operand is an insn that is a small insn.
947 Allow const_int 0 as well, which is a placeholder for NOP slots. */
950 small_insn_p (op, mode)
952 enum machine_mode mode ATTRIBUTE_UNUSED;
954 if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
960 return get_attr_length (op) == 2;
963 /* Return non-zero if the operand is an insn that is a large insn. */
966 large_insn_p (op, mode)
968 enum machine_mode mode ATTRIBUTE_UNUSED;
973 return get_attr_length (op) != 2;
979 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
980 return the mode to be used for the comparison. */
983 m32r_select_cc_mode (op, x, y)
984 int op ATTRIBUTE_UNUSED;
985 rtx x ATTRIBUTE_UNUSED;
986 rtx y ATTRIBUTE_UNUSED;
991 /* X and Y are two things to compare using CODE. Emit the compare insn and
992 return the rtx for compare [arg0 of the if_then_else].
993 If need_compare is true then the comparison insn must be generated, rather
994 than being susummed into the following branch instruction. */
997 gen_compare (code, x, y, need_compare)
1002 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
1003 enum rtx_code compare_code, branch_code;
1004 rtx cc_reg = gen_rtx_REG (mode, CARRY_REGNUM);
1009 case EQ: compare_code = EQ; branch_code = NE; break;
1010 case NE: compare_code = EQ; branch_code = EQ; break;
1011 case LT: compare_code = LT; branch_code = NE; break;
1012 case LE: compare_code = LT; branch_code = EQ; must_swap = 1; break;
1013 case GT: compare_code = LT; branch_code = NE; must_swap = 1; break;
1014 case GE: compare_code = LT; branch_code = EQ; break;
1015 case LTU: compare_code = LTU; branch_code = NE; break;
1016 case LEU: compare_code = LTU; branch_code = EQ; must_swap = 1; break;
1017 case GTU: compare_code = LTU; branch_code = NE; must_swap = 1; break;
1018 case GEU: compare_code = LTU; branch_code = EQ; break;
1026 switch (compare_code)
1029 if (GET_CODE (y) == CONST_INT
1030 && CMP_INT16_P (INTVAL (y)) /* reg equal to small const. */
1033 rtx tmp = gen_reg_rtx (SImode);
1035 emit_insn (gen_cmp_ne_small_const_insn (tmp, x, y));
1039 else if (CONSTANT_P (y)) /* reg equal to const. */
1041 rtx tmp = force_reg (GET_MODE (x), y);
1045 if (register_operand (y, SImode) /* reg equal to reg. */
1046 || y == const0_rtx) /* req equal to zero. */
1048 emit_insn (gen_cmp_eqsi_insn (x, y));
1050 return gen_rtx (code, mode, cc_reg, const0_rtx);
1055 if (register_operand (y, SImode)
1056 || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
1058 rtx tmp = gen_reg_rtx (SImode); /* reg compared to reg. */
1063 emit_insn (gen_cmp_ltsi_insn (x, y));
1067 if (y == const0_rtx)
1070 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1071 emit_insn (gen_cmp_ltsi_insn (x, tmp));
1075 if (GET_CODE (y) == CONST_INT)
1076 tmp = gen_rtx (PLUS, SImode, y, const1_rtx);
1078 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1079 emit_insn (gen_cmp_ltsi_insn (x, tmp));
1083 emit_insn (gen_cmp_ltsi_insn (x, y));
1090 return gen_rtx (code, mode, cc_reg, const0_rtx);
1095 if (register_operand (y, SImode)
1096 || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
1098 rtx tmp = gen_reg_rtx (SImode); /* reg (unsigned) compared to reg. */
1103 emit_insn (gen_cmp_ltusi_insn (x, y));
1107 if (y == const0_rtx)
1110 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1111 emit_insn (gen_cmp_ltusi_insn (x, tmp));
1115 if (GET_CODE (y) == CONST_INT)
1116 tmp = gen_rtx (PLUS, SImode, y, const1_rtx);
1118 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1119 emit_insn (gen_cmp_ltusi_insn (x, tmp));
1123 emit_insn (gen_cmp_ltusi_insn (x, y));
1130 return gen_rtx (code, mode, cc_reg, const0_rtx);
1140 /* reg/reg equal comparison */
1141 if (compare_code == EQ
1142 && register_operand (y, SImode))
1143 return gen_rtx (code, mode, x, y);
1145 /* reg/zero signed comparison */
1146 if ((compare_code == EQ || compare_code == LT)
1148 return gen_rtx (code, mode, x, y);
1150 /* reg/smallconst equal comparison */
1151 if (compare_code == EQ
1152 && GET_CODE (y) == CONST_INT
1153 && CMP_INT16_P (INTVAL (y)))
1155 rtx tmp = gen_reg_rtx (SImode);
1156 emit_insn (gen_cmp_ne_small_const_insn (tmp, x, y));
1157 return gen_rtx (code, mode, tmp, const0_rtx);
1160 /* reg/const equal comparison */
1161 if (compare_code == EQ
1164 rtx tmp = force_reg (GET_MODE (x), y);
1165 return gen_rtx (code, mode, x, tmp);
1172 y = force_reg (GET_MODE (x), y);
1176 (code == LTU || code == LEU || code == GTU || code == GEU)
1177 ? uint16_operand (y, GET_MODE (y))
1178 : reg_or_cmp_int16_operand (y, GET_MODE (y));
1181 y = force_reg (GET_MODE (x), y);
1185 switch (compare_code)
1188 emit_insn (gen_cmp_eqsi_insn (must_swap ? y : x, must_swap ? x : y));
1191 emit_insn (gen_cmp_ltsi_insn (must_swap ? y : x, must_swap ? x : y));
1194 emit_insn (gen_cmp_ltusi_insn (must_swap ? y : x, must_swap ? x : y));
1201 return gen_rtx (branch_code, VOIDmode, cc_reg, CONST0_RTX (mode));
1204 /* Split a 2 word move (DI or DF) into component parts. */
1207 gen_split_move_double (operands)
1210 enum machine_mode mode = GET_MODE (operands[0]);
1211 rtx dest = operands[0];
1212 rtx src = operands[1];
1215 /* We might have (SUBREG (MEM)) here, so just get rid of the
1216 subregs to make this code simpler. It is safe to call
1217 alter_subreg any time after reload. */
1218 if (GET_CODE (dest) == SUBREG)
1219 dest = alter_subreg (dest);
1220 if (GET_CODE (src) == SUBREG)
1221 src = alter_subreg (src);
1224 if (GET_CODE (dest) == REG)
1226 int dregno = REGNO (dest);
1229 if (GET_CODE (src) == REG)
1231 int sregno = REGNO (src);
1233 int reverse = (dregno == sregno + 1);
1235 /* We normally copy the low-numbered register first. However, if
1236 the first register operand 0 is the same as the second register of
1237 operand 1, we must copy in the opposite order. */
1238 emit_insn (gen_rtx_SET (VOIDmode,
1239 operand_subword (dest, reverse, TRUE, mode),
1240 operand_subword (src, reverse, TRUE, mode)));
1242 emit_insn (gen_rtx_SET (VOIDmode,
1243 operand_subword (dest, !reverse, TRUE, mode),
1244 operand_subword (src, !reverse, TRUE, mode)));
1247 /* reg = constant */
1248 else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE)
1251 split_double (src, &words[0], &words[1]);
1252 emit_insn (gen_rtx_SET (VOIDmode,
1253 operand_subword (dest, 0, TRUE, mode),
1256 emit_insn (gen_rtx_SET (VOIDmode,
1257 operand_subword (dest, 1, TRUE, mode),
1262 else if (GET_CODE (src) == MEM)
1264 /* If the high-address word is used in the address, we must load it
1265 last. Otherwise, load it first. */
1266 rtx addr = XEXP (src, 0);
1267 int reverse = (refers_to_regno_p (dregno, dregno+1, addr, 0) != 0);
1269 /* We used to optimize loads from single registers as
1273 if r3 were not used subsequently. However, the REG_NOTES aren't
1274 propigated correctly by the reload phase, and it can cause bad
1275 code to be generated. We could still try:
1277 ld r1,r3+; ld r2,r3; addi r3,-4
1279 which saves 2 bytes and doesn't force longword alignment. */
1280 emit_insn (gen_rtx_SET (VOIDmode,
1281 operand_subword (dest, reverse, TRUE, mode),
1282 change_address (src, SImode,
1283 plus_constant (addr,
1284 reverse * UNITS_PER_WORD))));
1286 emit_insn (gen_rtx_SET (VOIDmode,
1287 operand_subword (dest, !reverse, TRUE, mode),
1288 change_address (src, SImode,
1289 plus_constant (addr,
1290 (!reverse) * UNITS_PER_WORD))));
1298 /* We used to optimize loads from single registers as
1302 if r3 were not used subsequently. However, the REG_NOTES aren't
1303 propigated correctly by the reload phase, and it can cause bad
1304 code to be generated. We could still try:
1306 st r1,r3; st r2,+r3; addi r3,-4
1308 which saves 2 bytes and doesn't force longword alignment. */
1309 else if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
1311 rtx addr = XEXP (dest, 0);
1313 emit_insn (gen_rtx_SET (VOIDmode,
1314 change_address (dest, SImode, addr),
1315 operand_subword (src, 0, TRUE, mode)));
1317 emit_insn (gen_rtx_SET (VOIDmode,
1318 change_address (dest, SImode,
1319 plus_constant (addr, UNITS_PER_WORD)),
1320 operand_subword (src, 1, TRUE, mode)));
1326 val = gen_sequence ();
1332 /* Implements the FUNCTION_ARG_PARTIAL_NREGS macro. */
1335 function_arg_partial_nregs (cum, mode, type, named)
1336 CUMULATIVE_ARGS *cum;
1337 enum machine_mode mode;
1339 int named ATTRIBUTE_UNUSED;
1343 (((mode == BLKmode && type)
1344 ? (unsigned int) int_size_in_bytes (type)
1345 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
1348 if (*cum >= M32R_MAX_PARM_REGS)
1350 else if (*cum + size > M32R_MAX_PARM_REGS)
1351 ret = (*cum + size) - M32R_MAX_PARM_REGS;
1358 /* Do any needed setup for a variadic function. For the M32R, we must
1359 create a register parameter block, and then copy any anonymous arguments
1360 in registers to memory.
1362 CUM has not been updated for the last named argument which has type TYPE
1363 and mode MODE, and we rely on this fact. */
1366 m32r_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
1367 CUMULATIVE_ARGS *cum;
1368 enum machine_mode mode;
1378 /* All BLKmode values are passed by reference. */
1379 if (mode == BLKmode)
1382 /* We must treat `__builtin_va_alist' as an anonymous arg. */
1383 if (current_function_varargs)
1384 first_anon_arg = *cum;
1386 first_anon_arg = (ROUND_ADVANCE_CUM (*cum, mode, type)
1387 + ROUND_ADVANCE_ARG (mode, type));
1389 if (first_anon_arg < M32R_MAX_PARM_REGS)
1391 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1392 int first_reg_offset = first_anon_arg;
1393 /* Size in words to "pretend" allocate. */
1394 int size = M32R_MAX_PARM_REGS - first_reg_offset;
1397 regblock = gen_rtx_MEM (BLKmode,
1398 plus_constant (arg_pointer_rtx,
1399 FIRST_PARM_OFFSET (0)));
1400 MEM_ALIAS_SET (regblock) = get_varargs_alias_set ();
1401 move_block_from_reg (first_reg_offset, regblock,
1402 size, size * UNITS_PER_WORD);
1404 *pretend_size = (size * UNITS_PER_WORD);
1409 /* Implement `va_arg'. */
1412 m32r_va_arg (valist, type)
1415 HOST_WIDE_INT size, rsize;
1419 size = int_size_in_bytes (type);
1420 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
1424 tree type_ptr, type_ptr_ptr;
1426 /* Pass by reference. */
1428 type_ptr = build_pointer_type (type);
1429 type_ptr_ptr = build_pointer_type (type_ptr);
1431 t = build (POSTINCREMENT_EXPR, va_list_type_node, valist,
1432 build_int_2 (UNITS_PER_WORD, 0));
1433 TREE_SIDE_EFFECTS (t) = 1;
1434 t = build1 (NOP_EXPR, type_ptr_ptr, t);
1435 TREE_SIDE_EFFECTS (t) = 1;
1436 t = build1 (INDIRECT_REF, type_ptr, t);
1438 addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1442 /* Pass by value. */
1444 if (size < UNITS_PER_WORD)
1446 /* Care for bigendian correction on the aligned address. */
1447 t = build (PLUS_EXPR, ptr_type_node, valist,
1448 build_int_2 (rsize - size, 0));
1449 addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1450 addr_rtx = copy_to_reg (addr_rtx);
1453 t = build (PLUS_EXPR, va_list_type_node, valist,
1454 build_int_2 (rsize, 0));
1455 t = build (MODIFY_EXPR, va_list_type_node, valist, t);
1456 TREE_SIDE_EFFECTS (t) = 1;
1457 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
1461 t = build (POSTINCREMENT_EXPR, va_list_type_node, valist,
1462 build_int_2 (rsize, 0));
1463 TREE_SIDE_EFFECTS (t) = 1;
1464 addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1472 m32r_adjust_cost (insn, link, dep_insn, cost)
1473 rtx insn ATTRIBUTE_UNUSED;
1474 rtx link ATTRIBUTE_UNUSED;
1475 rtx dep_insn ATTRIBUTE_UNUSED;
1482 /* Return true if INSN is real instruction bearing insn. */
1488 return (INSN_P (insn)
1489 && GET_CODE (PATTERN (insn)) != USE
1490 && GET_CODE (PATTERN (insn)) != CLOBBER
1491 && GET_CODE (PATTERN (insn)) != ADDR_VEC);
1494 /* Increase the priority of long instructions so that the
1495 short instructions are scheduled ahead of the long ones. */
1498 m32r_adjust_priority (insn, priority)
1502 if (m32r_is_insn (insn)
1503 && get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1510 /* Initialize for scheduling a group of instructions. */
1513 m32r_sched_init (stream, verbose)
1514 FILE * stream ATTRIBUTE_UNUSED;
1515 int verbose ATTRIBUTE_UNUSED;
1517 m32r_sched_odd_word_p = FALSE;
1521 /* Reorder the schedulers priority list if needed */
1524 m32r_sched_reorder (stream, verbose, ready, n_ready)
1538 ";;\t\t::: Looking at %d insn(s) on ready list, boundary is %s word\n",
1540 (m32r_sched_odd_word_p) ? "odd" : "even");
1544 rtx * long_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1545 rtx * long_tail = long_head;
1546 rtx * short_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1547 rtx * short_tail = short_head;
1548 rtx * new_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1549 rtx * new_tail = new_head + (n_ready - 1);
1552 /* Loop through the instructions, classifing them as short/long. Try
1553 to keep 2 short together and/or 1 long. Note, the ready list is
1554 actually ordered backwards, so keep it in that manner. */
1555 for (i = n_ready-1; i >= 0; i--)
1557 rtx insn = ready[i];
1559 if (! m32r_is_insn (insn))
1561 /* Dump all current short/long insns just in case. */
1562 while (long_head != long_tail)
1563 *new_tail-- = *long_head++;
1565 while (short_head != short_tail)
1566 *new_tail-- = *short_head++;
1571 ";;\t\t::: Skipping non instruction %d\n",
1578 if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1579 *long_tail++ = insn;
1582 *short_tail++ = insn;
1586 /* If we are on an odd word, emit a single short instruction if
1588 if (m32r_sched_odd_word_p && short_head != short_tail)
1589 *new_tail-- = *short_head++;
1591 /* Now dump out all of the long instructions */
1592 while (long_head != long_tail)
1593 *new_tail-- = *long_head++;
1595 /* Now dump out all of the short instructions */
1596 while (short_head != short_tail)
1597 *new_tail-- = *short_head++;
1599 if (new_tail+1 != new_head)
1602 memcpy (ready, new_head, sizeof (rtx) * n_ready);
1606 fprintf (stream, ";;\t\t::: New ready list: ");
1607 debug_ready_list (ready, n_ready);
1610 for (i = 0; i < n_ready; i++)
1612 rtx insn = ready[i];
1614 fprintf (stream, " %d", INSN_UID (ready[i]));
1616 if (! m32r_is_insn (insn))
1617 fputs ("(?)", stream);
1619 else if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1620 fputs ("(l)", stream);
1623 fputs ("(s)", stream);
1626 fprintf (stream, "\n");
1633 /* If we have a machine that can issue a variable # of instructions
1634 per cycle, indicate how many more instructions can be issued
1635 after the current one. */
1637 m32r_sched_variable_issue (stream, verbose, insn, how_many)
1643 int orig_odd_word_p = m32r_sched_odd_word_p;
1644 int short_p = FALSE;
1647 if (how_many > 0 && !TARGET_DEBUG)
1649 if (! m32r_is_insn (insn))
1652 else if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1655 m32r_sched_odd_word_p = 0;
1659 m32r_sched_odd_word_p = !m32r_sched_odd_word_p;
1664 if (verbose > 7 && stream)
1666 ";;\t\t::: %s insn %d starts on an %s word, can emit %d more instruction(s)\n",
1667 short_p ? "short" : "long",
1669 orig_odd_word_p ? "odd" : "even",
1675 /* Cost functions. */
1677 /* Provide the costs of an addressing mode that contains ADDR.
1678 If ADDR is not a valid address, its cost is irrelevant.
1680 This function is trivial at the moment. This code doesn't live
1681 in m32r.h so it's easy to experiment. */
1684 m32r_address_cost (addr)
1685 rtx addr ATTRIBUTE_UNUSED;
1690 /* Type of function DECL.
1692 The result is cached. To reset the cache at the end of a function,
1693 call with DECL = NULL_TREE. */
1695 enum m32r_function_type
1696 m32r_compute_function_type (decl)
1700 static enum m32r_function_type fn_type = M32R_FUNCTION_UNKNOWN;
1701 /* Last function we were called for. */
1702 static tree last_fn = NULL_TREE;
1704 /* Resetting the cached value? */
1705 if (decl == NULL_TREE)
1707 fn_type = M32R_FUNCTION_UNKNOWN;
1708 last_fn = NULL_TREE;
1712 if (decl == last_fn && fn_type != M32R_FUNCTION_UNKNOWN)
1715 /* Compute function type. */
1716 fn_type = (lookup_attribute ("interrupt", DECL_MACHINE_ATTRIBUTES (current_function_decl)) != NULL_TREE
1717 ? M32R_FUNCTION_INTERRUPT
1718 : M32R_FUNCTION_NORMAL);
1723 \f/* Function prologue/epilogue handlers. */
1725 /* M32R stack frames look like:
1727 Before call After call
1728 +-----------------------+ +-----------------------+
1730 high | local variables, | | local variables, |
1731 mem | reg save area, etc. | | reg save area, etc. |
1733 +-----------------------+ +-----------------------+
1735 | arguments on stack. | | arguments on stack. |
1737 SP+0->+-----------------------+ +-----------------------+
1738 | reg parm save area, |
1739 | only created for |
1740 | variable argument |
1742 +-----------------------+
1743 | previous frame ptr |
1744 +-----------------------+
1746 | register save area |
1748 +-----------------------+
1750 +-----------------------+
1754 +-----------------------+
1756 | alloca allocations |
1758 +-----------------------+
1760 low | arguments on stack |
1762 SP+0->+-----------------------+
1765 1) The "reg parm save area" does not exist for non variable argument fns.
1766 2) The "reg parm save area" can be eliminated completely if we saved regs
1767 containing anonymous args separately but that complicates things too
1768 much (so it's not done).
1769 3) The return address is saved after the register save area so as to have as
1770 many insns as possible between the restoration of `lr' and the `jmp lr'.
1773 /* Structure to be filled in by m32r_compute_frame_size with register
1774 save masks, and offsets for the current function. */
1775 struct m32r_frame_info
1777 unsigned int total_size; /* # bytes that the entire frame takes up */
1778 unsigned int extra_size; /* # bytes of extra stuff */
1779 unsigned int pretend_size; /* # bytes we push and pretend caller did */
1780 unsigned int args_size; /* # bytes that outgoing arguments take up */
1781 unsigned int reg_size; /* # bytes needed to store regs */
1782 unsigned int var_size; /* # bytes that variables take up */
1783 unsigned int gmask; /* mask of saved gp registers */
1784 unsigned int save_fp; /* nonzero if fp must be saved */
1785 unsigned int save_lr; /* nonzero if lr (return addr) must be saved */
1786 int initialized; /* nonzero if frame size already calculated */
1789 /* Current frame information calculated by m32r_compute_frame_size. */
1790 static struct m32r_frame_info current_frame_info;
1792 /* Zero structure to initialize current_frame_info. */
1793 static struct m32r_frame_info zero_frame_info;
1795 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1796 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1798 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1799 The return address and frame pointer are treated separately.
1800 Don't consider them here. */
1801 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1802 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1803 && (regs_ever_live[regno] && (!call_used_regs[regno] || interrupt_p)))
1805 #define MUST_SAVE_FRAME_POINTER (regs_ever_live[FRAME_POINTER_REGNUM])
1806 #define MUST_SAVE_RETURN_ADDR (regs_ever_live[RETURN_ADDR_REGNUM] || profile_flag)
1808 #define SHORT_INSN_SIZE 2 /* size of small instructions */
1809 #define LONG_INSN_SIZE 4 /* size of long instructions */
1811 /* Return the bytes needed to compute the frame pointer from the current
1814 SIZE is the size needed for local variables. */
1817 m32r_compute_frame_size (size)
1818 int size; /* # of var. bytes allocated. */
1821 unsigned int total_size, var_size, args_size, pretend_size, extra_size;
1822 unsigned int reg_size, frame_size;
1824 enum m32r_function_type fn_type;
1827 var_size = M32R_STACK_ALIGN (size);
1828 args_size = M32R_STACK_ALIGN (current_function_outgoing_args_size);
1829 pretend_size = current_function_pretend_args_size;
1830 extra_size = FIRST_PARM_OFFSET (0);
1831 total_size = extra_size + pretend_size + args_size + var_size;
1835 /* See if this is an interrupt handler. Call used registers must be saved
1837 fn_type = m32r_compute_function_type (current_function_decl);
1838 interrupt_p = M32R_INTERRUPT_P (fn_type);
1840 /* Calculate space needed for registers. */
1842 for (regno = 0; regno < M32R_MAX_INT_REGS; regno++)
1844 if (MUST_SAVE_REGISTER (regno, interrupt_p))
1846 reg_size += UNITS_PER_WORD;
1847 gmask |= 1 << regno;
1851 current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER;
1852 current_frame_info.save_lr = MUST_SAVE_RETURN_ADDR;
1854 reg_size += ((current_frame_info.save_fp + current_frame_info.save_lr)
1856 total_size += reg_size;
1858 /* ??? Not sure this is necessary, and I don't think the epilogue
1859 handler will do the right thing if this changes total_size. */
1860 total_size = M32R_STACK_ALIGN (total_size);
1862 frame_size = total_size - (pretend_size + reg_size);
1864 /* Save computed information. */
1865 current_frame_info.total_size = total_size;
1866 current_frame_info.extra_size = extra_size;
1867 current_frame_info.pretend_size = pretend_size;
1868 current_frame_info.var_size = var_size;
1869 current_frame_info.args_size = args_size;
1870 current_frame_info.reg_size = reg_size;
1871 current_frame_info.gmask = gmask;
1872 current_frame_info.initialized = reload_completed;
1874 /* Ok, we're done. */
1878 /* When the `length' insn attribute is used, this macro specifies the
1879 value to be assigned to the address of the first insn in a
1880 function. If not specified, 0 is used. */
1883 m32r_first_insn_address ()
1885 if (! current_frame_info.initialized)
1886 m32r_compute_frame_size (get_frame_size ());
1891 /* Expand the m32r prologue as a series of insns. */
1894 m32r_expand_prologue ()
1900 if (! current_frame_info.initialized)
1901 m32r_compute_frame_size (get_frame_size ());
1903 gmask = current_frame_info.gmask;
1905 /* These cases shouldn't happen. Catch them now. */
1906 if (current_frame_info.total_size == 0 && gmask)
1909 /* Allocate space for register arguments if this is a variadic function. */
1910 if (current_frame_info.pretend_size != 0)
1912 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1913 the wrong result on a 64-bit host. */
1914 HOST_WIDE_INT pretend_size = current_frame_info.pretend_size;
1915 emit_insn (gen_addsi3 (stack_pointer_rtx,
1917 GEN_INT (-pretend_size)));
1920 /* Save any registers we need to and set up fp. */
1922 if (current_frame_info.save_fp)
1923 emit_insn (gen_movsi_push (stack_pointer_rtx, frame_pointer_rtx));
1925 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1927 /* Save any needed call-saved regs (and call-used if this is an
1928 interrupt handler). */
1929 for (regno = 0; regno <= M32R_MAX_INT_REGS; ++regno)
1931 if ((gmask & (1 << regno)) != 0)
1932 emit_insn (gen_movsi_push (stack_pointer_rtx,
1933 gen_rtx_REG (Pmode, regno)));
1936 if (current_frame_info.save_lr)
1937 emit_insn (gen_movsi_push (stack_pointer_rtx,
1938 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
1940 /* Allocate the stack frame. */
1941 frame_size = (current_frame_info.total_size
1942 - (current_frame_info.pretend_size
1943 + current_frame_info.reg_size));
1945 if (frame_size == 0)
1946 ; /* nothing to do */
1947 else if (frame_size <= 32768)
1948 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1949 GEN_INT (-frame_size)));
1952 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1953 emit_insn (gen_movsi (tmp, GEN_INT (frame_size)));
1954 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
1957 if (frame_pointer_needed)
1958 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
1960 if (profile_flag || profile_block_flag)
1961 emit_insn (gen_blockage ());
1965 /* Set up the stack and frame pointer (if desired) for the function.
1966 Note, if this is changed, you need to mirror the changes in
1967 m32r_compute_frame_size which calculates the prolog size. */
1970 m32r_output_function_prologue (file, size)
1974 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
1976 /* If this is an interrupt handler, mark it as such. */
1977 if (M32R_INTERRUPT_P (fn_type))
1979 fprintf (file, "\t%s interrupt handler\n",
1983 if (! current_frame_info.initialized)
1984 m32r_compute_frame_size (size);
1986 /* This is only for the human reader. */
1988 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
1990 current_frame_info.var_size,
1991 current_frame_info.reg_size / 4,
1992 current_frame_info.args_size,
1993 current_frame_info.extra_size);
1996 /* Do any necessary cleanup after a function to restore stack, frame,
2000 m32r_output_function_epilogue (file, size)
2002 int size ATTRIBUTE_UNUSED;
2005 int noepilogue = FALSE;
2007 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
2009 /* This is only for the human reader. */
2010 fprintf (file, "\t%s EPILOGUE\n", ASM_COMMENT_START);
2012 if (!current_frame_info.initialized)
2014 total_size = current_frame_info.total_size;
2016 if (total_size == 0)
2018 rtx insn = get_last_insn ();
2020 /* If the last insn was a BARRIER, we don't have to write any code
2021 because a jump (aka return) was put there. */
2022 if (GET_CODE (insn) == NOTE)
2023 insn = prev_nonnote_insn (insn);
2024 if (insn && GET_CODE (insn) == BARRIER)
2030 unsigned int var_size = current_frame_info.var_size;
2031 unsigned int args_size = current_frame_info.args_size;
2032 unsigned int gmask = current_frame_info.gmask;
2033 int can_trust_sp_p = !current_function_calls_alloca;
2034 const char * sp_str = reg_names[STACK_POINTER_REGNUM];
2035 const char * fp_str = reg_names[FRAME_POINTER_REGNUM];
2037 /* The first thing to do is point the sp at the bottom of the register
2041 unsigned int reg_offset = var_size + args_size;
2042 if (reg_offset == 0)
2043 ; /* nothing to do */
2044 else if (reg_offset < 128)
2045 fprintf (file, "\taddi %s,%s%d\n",
2046 sp_str, IMMEDIATE_PREFIX, reg_offset);
2047 else if (reg_offset < 32768)
2048 fprintf (file, "\tadd3 %s,%s,%s%d\n",
2049 sp_str, sp_str, IMMEDIATE_PREFIX, reg_offset);
2051 fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
2052 reg_names[PROLOGUE_TMP_REGNUM],
2053 IMMEDIATE_PREFIX, reg_offset,
2054 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
2056 else if (frame_pointer_needed)
2058 unsigned int reg_offset = var_size + args_size;
2059 if (reg_offset == 0)
2060 fprintf (file, "\tmv %s,%s\n", sp_str, fp_str);
2061 else if (reg_offset < 32768)
2062 fprintf (file, "\tadd3 %s,%s,%s%d\n",
2063 sp_str, fp_str, IMMEDIATE_PREFIX, reg_offset);
2065 fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
2066 reg_names[PROLOGUE_TMP_REGNUM],
2067 IMMEDIATE_PREFIX, reg_offset,
2068 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
2073 if (current_frame_info.save_lr)
2074 fprintf (file, "\tpop %s\n", reg_names[RETURN_ADDR_REGNUM]);
2076 /* Restore any saved registers, in reverse order of course. */
2077 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
2078 for (regno = M32R_MAX_INT_REGS - 1; regno >= 0; --regno)
2080 if ((gmask & (1L << regno)) != 0)
2081 fprintf (file, "\tpop %s\n", reg_names[regno]);
2084 if (current_frame_info.save_fp)
2085 fprintf (file, "\tpop %s\n", fp_str);
2087 /* Remove varargs area if present. */
2088 if (current_frame_info.pretend_size != 0)
2089 fprintf (file, "\taddi %s,%s%d\n",
2090 sp_str, IMMEDIATE_PREFIX, current_frame_info.pretend_size);
2092 /* Emit the return instruction. */
2093 if (M32R_INTERRUPT_P (fn_type))
2094 fprintf (file, "\trte\n");
2096 fprintf (file, "\tjmp %s\n", reg_names[RETURN_ADDR_REGNUM]);
2099 #if 0 /* no longer needed */
2100 /* Ensure the function cleanly ends on a 32 bit boundary. */
2101 fprintf (file, "\t.fillinsn\n");
2104 /* Reset state info for each function. */
2105 current_frame_info = zero_frame_info;
2106 m32r_compute_function_type (NULL_TREE);
2109 /* Return non-zero if this function is known to have a null or 1 instruction
2115 if (!reload_completed)
2118 if (! current_frame_info.initialized)
2119 m32r_compute_frame_size (get_frame_size ());
2121 return current_frame_info.total_size == 0;
2127 /* Emit special PIC prologues and epilogues. */
2130 m32r_finalize_pic ()
2135 /* Nested function support. */
2137 /* Emit RTL insns to initialize the variable parts of a trampoline.
2138 FNADDR is an RTX for the address of the function's pure code.
2139 CXT is an RTX for the static chain value for the function. */
2142 m32r_initialize_trampoline (tramp, fnaddr, cxt)
2143 rtx tramp ATTRIBUTE_UNUSED;
2144 rtx fnaddr ATTRIBUTE_UNUSED;
2145 rtx cxt ATTRIBUTE_UNUSED;
2149 /* Set the cpu type and print out other fancy things,
2150 at the top of the file. */
2153 m32r_asm_file_start (file)
2156 if (flag_verbose_asm)
2157 fprintf (file, "%s M32R/D special options: -G %d\n",
2158 ASM_COMMENT_START, g_switch_value);
2161 /* Print operand X (an rtx) in assembler syntax to file FILE.
2162 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2163 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2166 m32r_print_operand (file, x, code)
2175 /* The 's' and 'p' codes are used by output_block_move() to
2176 indicate post-increment 's'tores and 'p're-increment loads. */
2178 if (GET_CODE (x) == REG)
2179 fprintf (file, "@+%s", reg_names [REGNO (x)]);
2181 output_operand_lossage ("invalid operand to %s code");
2185 if (GET_CODE (x) == REG)
2186 fprintf (file, "@%s+", reg_names [REGNO (x)]);
2188 output_operand_lossage ("invalid operand to %p code");
2192 /* Write second word of DImode or DFmode reference,
2193 register or memory. */
2194 if (GET_CODE (x) == REG)
2195 fputs (reg_names[REGNO (x)+1], file);
2196 else if (GET_CODE (x) == MEM)
2198 fprintf (file, "@(");
2199 /* Handle possible auto-increment. Since it is pre-increment and
2200 we have already done it, we can just use an offset of four. */
2201 /* ??? This is taken from rs6000.c I think. I don't think it is
2202 currently necessary, but keep it around. */
2203 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2204 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2205 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
2207 output_address (plus_constant (XEXP (x, 0), 4));
2211 output_operand_lossage ("invalid operand to %R code");
2214 case 'H' : /* High word */
2215 case 'L' : /* Low word */
2216 if (GET_CODE (x) == REG)
2218 /* L = least significant word, H = most significant word */
2219 if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L'))
2220 fputs (reg_names[REGNO (x)], file);
2222 fputs (reg_names[REGNO (x)+1], file);
2224 else if (GET_CODE (x) == CONST_INT
2225 || GET_CODE (x) == CONST_DOUBLE)
2229 split_double (x, &first, &second);
2230 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2231 code == 'L' ? INTVAL (first) : INTVAL (second));
2234 output_operand_lossage ("invalid operand to %H/%L code");
2242 if (GET_CODE (x) != CONST_DOUBLE
2243 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
2244 fatal_insn ("Bad insn for 'A'", x);
2245 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
2246 REAL_VALUE_TO_DECIMAL (d, "%.20e", str);
2247 fprintf (file, "%s", str);
2251 case 'B' : /* Bottom half */
2252 case 'T' : /* Top half */
2253 /* Output the argument to a `seth' insn (sets the Top half-word).
2254 For constants output arguments to a seth/or3 pair to set Top and
2255 Bottom halves. For symbols output arguments to a seth/add3 pair to
2256 set Top and Bottom halves. The difference exists because for
2257 constants seth/or3 is more readable but for symbols we need to use
2258 the same scheme as `ld' and `st' insns (16 bit addend is signed). */
2259 switch (GET_CODE (x))
2266 split_double (x, &first, &second);
2267 x = WORDS_BIG_ENDIAN ? second : first;
2269 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
2275 ? INTVAL (x) & 0xffff
2276 : (INTVAL (x) >> 16) & 0xffff));
2282 && small_data_operand (x, VOIDmode))
2284 fputs ("sda(", file);
2285 output_addr_const (file, x);
2291 fputs (code == 'T' ? "shigh(" : "low(", file);
2292 output_addr_const (file, x);
2296 output_operand_lossage ("invalid operand to %T/%B code");
2303 /* Output a load/store with update indicator if appropriate. */
2304 if (GET_CODE (x) == MEM)
2306 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2307 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2311 output_operand_lossage ("invalid operand to %U code");
2315 /* Print a constant value negated. */
2316 if (GET_CODE (x) == CONST_INT)
2317 output_addr_const (file, GEN_INT (- INTVAL (x)));
2319 output_operand_lossage ("invalid operand to %N code");
2323 /* Print a const_int in hex. Used in comments. */
2324 if (GET_CODE (x) == CONST_INT)
2326 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
2335 fputs (IMMEDIATE_PREFIX, file);
2338 #if 0 /* ??? no longer used */
2340 fputs (reg_names[SDA_REGNUM], file);
2345 /* Do nothing special. */
2350 output_operand_lossage ("invalid operand output code");
2353 switch (GET_CODE (x))
2356 fputs (reg_names[REGNO (x)], file);
2361 if (GET_CODE (addr) == PRE_INC)
2363 if (GET_CODE (XEXP (addr, 0)) != REG)
2364 fatal_insn ("Pre-increment address is not a register", x);
2366 fprintf (file, "@+%s", reg_names[REGNO (XEXP (addr, 0))]);
2368 else if (GET_CODE (addr) == PRE_DEC)
2370 if (GET_CODE (XEXP (addr, 0)) != REG)
2371 fatal_insn ("Pre-decrement address is not a register", x);
2373 fprintf (file, "@-%s", reg_names[REGNO (XEXP (addr, 0))]);
2375 else if (GET_CODE (addr) == POST_INC)
2377 if (GET_CODE (XEXP (addr, 0)) != REG)
2378 fatal_insn ("Post-increment address is not a register", x);
2380 fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]);
2385 output_address (XEXP (x, 0));
2391 /* We handle SFmode constants here as output_addr_const doesn't. */
2392 if (GET_MODE (x) == SFmode)
2397 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
2398 REAL_VALUE_TO_TARGET_SINGLE (d, l);
2399 fprintf (file, "0x%08lx", l);
2403 /* Fall through. Let output_addr_const deal with it. */
2406 output_addr_const (file, x);
2411 /* Print a memory address as an operand to reference that memory location. */
2414 m32r_print_operand_address (file, addr)
2419 register rtx index = 0;
2422 switch (GET_CODE (addr))
2425 fputs (reg_names[REGNO (addr)], file);
2429 if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
2430 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
2431 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2432 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
2434 base = XEXP (addr, 0), index = XEXP (addr, 1);
2435 if (GET_CODE (base) == REG)
2437 /* Print the offset first (if present) to conform to the manual. */
2441 fprintf (file, "%d,", offset);
2442 fputs (reg_names[REGNO (base)], file);
2444 /* The chip doesn't support this, but left in for generality. */
2445 else if (GET_CODE (index) == REG)
2446 fprintf (file, "%s,%s",
2447 reg_names[REGNO (base)], reg_names[REGNO (index)]);
2448 /* Not sure this can happen, but leave in for now. */
2449 else if (GET_CODE (index) == SYMBOL_REF)
2451 output_addr_const (file, index);
2453 fputs (reg_names[REGNO (base)], file);
2456 fatal_insn ("Bad address", addr);
2458 else if (GET_CODE (base) == LO_SUM)
2461 || GET_CODE (XEXP (base, 0)) != REG)
2463 if (small_data_operand (XEXP (base, 1), VOIDmode))
2464 fputs ("sda(", file);
2466 fputs ("low(", file);
2467 output_addr_const (file, plus_constant (XEXP (base, 1), offset));
2469 fputs (reg_names[REGNO (XEXP (base, 0))], file);
2472 fatal_insn ("Bad address", addr);
2476 if (GET_CODE (XEXP (addr, 0)) != REG)
2477 fatal_insn ("Lo_sum not of register", addr);
2478 if (small_data_operand (XEXP (addr, 1), VOIDmode))
2479 fputs ("sda(", file);
2481 fputs ("low(", file);
2482 output_addr_const (file, XEXP (addr, 1));
2484 fputs (reg_names[REGNO (XEXP (addr, 0))], file);
2487 case PRE_INC : /* Assume SImode */
2488 fprintf (file, "+%s", reg_names[REGNO (XEXP (addr, 0))]);
2491 case PRE_DEC : /* Assume SImode */
2492 fprintf (file, "-%s", reg_names[REGNO (XEXP (addr, 0))]);
2495 case POST_INC : /* Assume SImode */
2496 fprintf (file, "%s+", reg_names[REGNO (XEXP (addr, 0))]);
2500 output_addr_const (file, addr);
2505 /* Return true if the operands are the constants 0 and 1. */
2507 zero_and_one (operand1, operand2)
2512 GET_CODE (operand1) == CONST_INT
2513 && GET_CODE (operand2) == CONST_INT
2514 && ( ((INTVAL (operand1) == 0) && (INTVAL (operand2) == 1))
2515 ||((INTVAL (operand1) == 1) && (INTVAL (operand2) == 0)));
2518 /* Return non-zero if the operand is suitable for use in a conditional move sequence. */
2520 conditional_move_operand (operand, mode)
2522 enum machine_mode mode;
2524 /* Only defined for simple integers so far... */
2525 if (mode != SImode && mode != HImode && mode != QImode)
2528 /* At the moment we can hanndle moving registers and loading constants. */
2529 /* To be added: Addition/subtraction/bitops/multiplication of registers. */
2531 switch (GET_CODE (operand))
2537 return INT8_P (INTVAL (operand));
2541 fprintf (stderr, "Test for cond move op of type: %s\n",
2542 GET_RTX_NAME (GET_CODE (operand)));
2548 /* Return true if the code is a test of the carry bit */
2550 carry_compare_operand (op, mode)
2552 enum machine_mode mode ATTRIBUTE_UNUSED;
2556 if (GET_MODE (op) != CCmode && GET_MODE (op) != VOIDmode)
2559 if (GET_CODE (op) != NE && GET_CODE (op) != EQ)
2563 if (GET_CODE (x) != REG || REGNO (x) != CARRY_REGNUM)
2567 if (GET_CODE (x) != CONST_INT || INTVAL (x) != 0)
2573 /* Generate the correct assembler code to handle the conditional loading of a
2574 value into a register. It is known that the operands satisfy the
2575 conditional_move_operand() function above. The destination is operand[0].
2576 The condition is operand [1]. The 'true' value is operand [2] and the
2577 'false' value is operand [3]. */
2579 emit_cond_move (operands, insn)
2581 rtx insn ATTRIBUTE_UNUSED;
2583 static char buffer [100];
2584 const char * dest = reg_names [REGNO (operands [0])];
2588 /* Destination must be a register. */
2589 if (GET_CODE (operands [0]) != REG)
2591 if (! conditional_move_operand (operands [2], SImode))
2593 if (! conditional_move_operand (operands [3], SImode))
2596 /* Check to see if the test is reversed. */
2597 if (GET_CODE (operands [1]) == NE)
2599 rtx tmp = operands [2];
2600 operands [2] = operands [3];
2604 sprintf (buffer, "mvfc %s, cbr", dest);
2606 /* If the true value was '0' then we need to invert the results of the move. */
2607 if (INTVAL (operands [2]) == 0)
2608 sprintf (buffer + strlen (buffer), "\n\txor3 %s, %s, #1",
2614 /* Returns true if the registers contained in the two
2615 rtl expressions are different. */
2617 m32r_not_same_reg (a, b)
2624 while (GET_CODE (a) == SUBREG)
2627 if (GET_CODE (a) == REG)
2630 while (GET_CODE (b) == SUBREG)
2633 if (GET_CODE (b) == REG)
2636 return reg_a != reg_b;
2640 /* Use a library function to move some bytes. */
2642 block_move_call (dest_reg, src_reg, bytes_rtx)
2647 /* We want to pass the size as Pmode, which will normally be SImode
2648 but will be DImode if we are using 64 bit longs and pointers. */
2649 if (GET_MODE (bytes_rtx) != VOIDmode
2650 && GET_MODE (bytes_rtx) != Pmode)
2651 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
2653 #ifdef TARGET_MEM_FUNCTIONS
2654 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0,
2655 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
2656 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
2657 TREE_UNSIGNED (sizetype)),
2658 TYPE_MODE (sizetype));
2660 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "bcopy"), 0,
2661 VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
2662 convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
2663 TREE_UNSIGNED (integer_type_node)),
2664 TYPE_MODE (integer_type_node));
2668 /* The maximum number of bytes to copy using pairs of load/store instructions.
2669 If a block is larger than this then a loop will be generated to copy
2670 MAX_MOVE_BYTES chunks at a time. The value of 32 is a semi-arbitary choice.
2671 A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte
2672 string copy in it. */
2673 #define MAX_MOVE_BYTES 32
2675 /* Expand string/block move operations.
2677 operands[0] is the pointer to the destination.
2678 operands[1] is the pointer to the source.
2679 operands[2] is the number of bytes to move.
2680 operands[3] is the alignment. */
2683 m32r_expand_block_move (operands)
2686 rtx orig_dst = operands[0];
2687 rtx orig_src = operands[1];
2688 rtx bytes_rtx = operands[2];
2689 rtx align_rtx = operands[3];
2690 int constp = GET_CODE (bytes_rtx) == CONST_INT;
2691 HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
2692 int align = INTVAL (align_rtx);
2697 if (constp && bytes <= 0)
2700 /* Move the address into scratch registers. */
2701 dst_reg = copy_addr_to_reg (XEXP (orig_dst, 0));
2702 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2704 if (align > UNITS_PER_WORD)
2705 align = UNITS_PER_WORD;
2707 /* If we prefer size over speed, always use a function call.
2708 If we do not know the size, use a function call.
2709 If the blocks are not word aligned, use a function call. */
2710 if (optimize_size || ! constp || align != UNITS_PER_WORD)
2712 block_move_call (dst_reg, src_reg, bytes_rtx);
2716 leftover = bytes % MAX_MOVE_BYTES;
2719 /* If necessary, generate a loop to handle the bulk of the copy. */
2724 rtx at_a_time = GEN_INT (MAX_MOVE_BYTES);
2725 rtx rounded_total = GEN_INT (bytes);
2727 /* If we are going to have to perform this loop more than
2728 once, then generate a label and compute the address the
2729 source register will contain upon completion of the final
2731 if (bytes > MAX_MOVE_BYTES)
2733 final_src = gen_reg_rtx (Pmode);
2736 emit_insn (gen_addsi3 (final_src, src_reg, rounded_total));
2739 emit_insn (gen_movsi (final_src, rounded_total));
2740 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
2743 label = gen_label_rtx ();
2747 /* It is known that output_block_move() will update src_reg to point
2748 to the word after the end of the source block, and dst_reg to point
2749 to the last word of the destination block, provided that the block
2750 is MAX_MOVE_BYTES long. */
2751 emit_insn (gen_movstrsi_internal (dst_reg, src_reg, at_a_time));
2752 emit_insn (gen_addsi3 (dst_reg, dst_reg, GEN_INT (4)));
2754 if (bytes > MAX_MOVE_BYTES)
2756 emit_insn (gen_cmpsi (src_reg, final_src));
2757 emit_jump_insn (gen_bne (label));
2762 emit_insn (gen_movstrsi_internal (dst_reg, src_reg, GEN_INT (leftover)));
2766 /* Emit load/stores for a small constant word aligned block_move.
2768 operands[0] is the memory address of the destination.
2769 operands[1] is the memory address of the source.
2770 operands[2] is the number of bytes to move.
2771 operands[3] is a temp register.
2772 operands[4] is a temp register. */
2775 m32r_output_block_move (insn, operands)
2776 rtx insn ATTRIBUTE_UNUSED;
2779 HOST_WIDE_INT bytes = INTVAL (operands[2]);
2783 if (bytes < 1 || bytes > MAX_MOVE_BYTES)
2786 /* We do not have a post-increment store available, so the first set of
2787 stores are done without any increment, then the remaining ones can use
2788 the pre-increment addressing mode.
2790 Note: expand_block_move() also relies upon this behaviour when building
2791 loops to copy large blocks. */
2800 output_asm_insn ("ld\t%3, %p1", operands);
2801 output_asm_insn ("ld\t%4, %p1", operands);
2802 output_asm_insn ("st\t%3, @%0", operands);
2803 output_asm_insn ("st\t%4, %s0", operands);
2807 output_asm_insn ("ld\t%3, %p1", operands);
2808 output_asm_insn ("ld\t%4, %p1", operands);
2809 output_asm_insn ("st\t%3, %s0", operands);
2810 output_asm_insn ("st\t%4, %s0", operands);
2815 else if (bytes >= 4)
2820 output_asm_insn ("ld\t%3, %p1", operands);
2823 output_asm_insn ("ld\t%4, %p1", operands);
2826 output_asm_insn ("st\t%3, @%0", operands);
2828 output_asm_insn ("st\t%3, %s0", operands);
2834 /* Get the entire next word, even though we do not want all of it.
2835 The saves us from doing several smaller loads, and we assume that
2836 we cannot cause a page fault when at least part of the word is in
2837 valid memory [since we don't get called if things aren't properly
2839 int dst_offset = first_time ? 0 : 4;
2843 /* If got_extra is true then we have already loaded
2844 the next word as part of loading and storing the previous word. */
2846 output_asm_insn ("ld\t%4, @%1", operands);
2852 output_asm_insn ("sra3\t%3, %4, #16", operands);
2853 my_operands[0] = operands[3];
2854 my_operands[1] = GEN_INT (dst_offset);
2855 my_operands[2] = operands[0];
2856 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands);
2858 /* If there is a byte left to store then increment the
2859 destination address and shift the contents of the source
2860 register down by 8 bits. We could not do the address
2861 increment in the store half word instruction, because it does
2862 not have an auto increment mode. */
2863 if (bytes > 0) /* assert (bytes == 1) */
2874 my_operands[0] = operands[4];
2875 my_operands[1] = GEN_INT (last_shift);
2876 output_asm_insn ("srai\t%0, #%1", my_operands);
2877 my_operands[0] = operands[4];
2878 my_operands[1] = GEN_INT (dst_offset);
2879 my_operands[2] = operands[0];
2880 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands);
2890 /* Return true if op is an integer constant, less than or equal to
2893 m32r_block_immediate_operand (op, mode)
2895 enum machine_mode mode ATTRIBUTE_UNUSED;
2897 if (GET_CODE (op) != CONST_INT
2898 || INTVAL (op) > MAX_MOVE_BYTES
2899 || INTVAL (op) <= 0)