1 /* Subroutines used for code generation on the Renesas M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
3 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 2, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
41 #include "integrate.h"
44 #include "target-def.h"
46 /* Save the operands last given to a compare for use when we
47 generate a scc or bcc insn. */
48 rtx m32r_compare_op0, m32r_compare_op1;
50 /* Array of valid operand punctuation characters. */
51 char m32r_punct_chars[256];
53 /* Selected code model. */
54 const char * m32r_model_string = M32R_MODEL_DEFAULT;
55 enum m32r_model m32r_model;
57 /* Selected SDA support. */
58 const char * m32r_sdata_string = M32R_SDATA_DEFAULT;
59 enum m32r_sdata m32r_sdata;
61 /* Machine-specific symbol_ref flags. */
62 #define SYMBOL_FLAG_MODEL_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT
63 #define SYMBOL_REF_MODEL(X) \
64 ((enum m32r_model) ((SYMBOL_REF_FLAGS (X) >> SYMBOL_FLAG_MODEL_SHIFT) & 3))
66 /* For string literals, etc. */
67 #define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.')
69 /* Cache-flush support. Cache-flush is used at trampoline.
70 Default cache-flush is "trap 12".
71 default cache-flush function is "_flush_cache" (CACHE_FLUSH_FUNC)
72 default cache-flush trap-interrupt number is "12". (CACHE_FLUSH_TRAP)
73 You can change how to generate code of cache-flush with following options.
74 -flush-func=FLUSH-FUNC-NAME
76 -fluch-trap=TRAP-NUMBER
78 const char *m32r_cache_flush_func = CACHE_FLUSH_FUNC;
79 const char *m32r_cache_flush_trap_string = CACHE_FLUSH_TRAP;
80 int m32r_cache_flush_trap = 12;
82 /* Forward declaration. */
83 static void init_reg_tables (void);
84 static void block_move_call (rtx, rtx, rtx);
85 static int m32r_is_insn (rtx);
86 const struct attribute_spec m32r_attribute_table[];
87 static tree m32r_handle_model_attribute (tree *, tree, tree, int, bool *);
88 static void m32r_output_function_prologue (FILE *, HOST_WIDE_INT);
89 static void m32r_output_function_epilogue (FILE *, HOST_WIDE_INT);
91 static void m32r_file_start (void);
93 static int m32r_adjust_priority (rtx, int);
94 static int m32r_issue_rate (void);
96 static void m32r_encode_section_info (tree, rtx, int);
97 static bool m32r_in_small_data_p (tree);
98 static bool m32r_return_in_memory (tree, tree);
99 static void m32r_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
101 static void init_idents (void);
102 static bool m32r_rtx_costs (rtx, int, int, int *);
103 static bool m32r_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
105 static int m32r_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
108 /* Initialize the GCC target structure. */
109 #undef TARGET_ATTRIBUTE_TABLE
110 #define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
112 #undef TARGET_ASM_ALIGNED_HI_OP
113 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
114 #undef TARGET_ASM_ALIGNED_SI_OP
115 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
117 #undef TARGET_ASM_FUNCTION_PROLOGUE
118 #define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue
119 #undef TARGET_ASM_FUNCTION_EPILOGUE
120 #define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
122 #undef TARGET_ASM_FILE_START
123 #define TARGET_ASM_FILE_START m32r_file_start
125 #undef TARGET_SCHED_ADJUST_PRIORITY
126 #define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
127 #undef TARGET_SCHED_ISSUE_RATE
128 #define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
130 #undef TARGET_ENCODE_SECTION_INFO
131 #define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info
132 #undef TARGET_IN_SMALL_DATA_P
133 #define TARGET_IN_SMALL_DATA_P m32r_in_small_data_p
135 #undef TARGET_RTX_COSTS
136 #define TARGET_RTX_COSTS m32r_rtx_costs
137 #undef TARGET_ADDRESS_COST
138 #define TARGET_ADDRESS_COST hook_int_rtx_0
140 #undef TARGET_PROMOTE_PROTOTYPES
141 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
142 #undef TARGET_RETURN_IN_MEMORY
143 #define TARGET_RETURN_IN_MEMORY m32r_return_in_memory
144 #undef TARGET_SETUP_INCOMING_VARARGS
145 #define TARGET_SETUP_INCOMING_VARARGS m32r_setup_incoming_varargs
146 #undef TARGET_MUST_PASS_IN_STACK
147 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
148 #undef TARGET_PASS_BY_REFERENCE
149 #define TARGET_PASS_BY_REFERENCE m32r_pass_by_reference
150 #undef TARGET_ARG_PARTIAL_BYTES
151 #define TARGET_ARG_PARTIAL_BYTES m32r_arg_partial_bytes
153 struct gcc_target targetm = TARGET_INITIALIZER;
155 /* Called by OVERRIDE_OPTIONS to initialize various things. */
162 /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */
163 memset (m32r_punct_chars, 0, sizeof (m32r_punct_chars));
164 m32r_punct_chars['#'] = 1;
165 m32r_punct_chars['@'] = 1; /* ??? no longer used */
167 /* Provide default value if not specified. */
169 g_switch_value = SDATA_DEFAULT_SIZE;
171 if (strcmp (m32r_model_string, "small") == 0)
172 m32r_model = M32R_MODEL_SMALL;
173 else if (strcmp (m32r_model_string, "medium") == 0)
174 m32r_model = M32R_MODEL_MEDIUM;
175 else if (strcmp (m32r_model_string, "large") == 0)
176 m32r_model = M32R_MODEL_LARGE;
178 error ("bad value (%s) for -mmodel switch", m32r_model_string);
180 if (strcmp (m32r_sdata_string, "none") == 0)
181 m32r_sdata = M32R_SDATA_NONE;
182 else if (strcmp (m32r_sdata_string, "sdata") == 0)
183 m32r_sdata = M32R_SDATA_SDATA;
184 else if (strcmp (m32r_sdata_string, "use") == 0)
185 m32r_sdata = M32R_SDATA_USE;
187 error ("bad value (%s) for -msdata switch", m32r_sdata_string);
189 if (m32r_cache_flush_trap_string)
191 /* Change trap-number (12) for cache-flush to the others (0 - 15). */
192 m32r_cache_flush_trap = atoi (m32r_cache_flush_trap_string);
193 if (m32r_cache_flush_trap < 0 || m32r_cache_flush_trap > 15)
194 error ("bad value (%s) for -flush-trap=n (0=<n<=15)",
195 m32r_cache_flush_trap_string);
199 /* Vectors to keep interesting information about registers where it can easily
200 be got. We use to use the actual mode value as the bit number, but there
201 is (or may be) more than 32 modes now. Instead we use two tables: one
202 indexed by hard register number, and one indexed by mode. */
204 /* The purpose of m32r_mode_class is to shrink the range of modes so that
205 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
206 mapped into one m32r_mode_class mode. */
211 S_MODE, D_MODE, T_MODE, O_MODE,
212 SF_MODE, DF_MODE, TF_MODE, OF_MODE, A_MODE
215 /* Modes for condition codes. */
216 #define C_MODES (1 << (int) C_MODE)
218 /* Modes for single-word and smaller quantities. */
219 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
221 /* Modes for double-word and smaller quantities. */
222 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
224 /* Modes for quad-word and smaller quantities. */
225 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
227 /* Modes for accumulators. */
228 #define A_MODES (1 << (int) A_MODE)
230 /* Value is 1 if register/mode pair is acceptable on arc. */
232 const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
234 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
235 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
236 S_MODES, C_MODES, A_MODES, A_MODES
239 unsigned int m32r_mode_class [NUM_MACHINE_MODES];
241 enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
244 init_reg_tables (void)
248 for (i = 0; i < NUM_MACHINE_MODES; i++)
250 switch (GET_MODE_CLASS (i))
253 case MODE_PARTIAL_INT:
254 case MODE_COMPLEX_INT:
255 if (GET_MODE_SIZE (i) <= 4)
256 m32r_mode_class[i] = 1 << (int) S_MODE;
257 else if (GET_MODE_SIZE (i) == 8)
258 m32r_mode_class[i] = 1 << (int) D_MODE;
259 else if (GET_MODE_SIZE (i) == 16)
260 m32r_mode_class[i] = 1 << (int) T_MODE;
261 else if (GET_MODE_SIZE (i) == 32)
262 m32r_mode_class[i] = 1 << (int) O_MODE;
264 m32r_mode_class[i] = 0;
267 case MODE_COMPLEX_FLOAT:
268 if (GET_MODE_SIZE (i) <= 4)
269 m32r_mode_class[i] = 1 << (int) SF_MODE;
270 else if (GET_MODE_SIZE (i) == 8)
271 m32r_mode_class[i] = 1 << (int) DF_MODE;
272 else if (GET_MODE_SIZE (i) == 16)
273 m32r_mode_class[i] = 1 << (int) TF_MODE;
274 else if (GET_MODE_SIZE (i) == 32)
275 m32r_mode_class[i] = 1 << (int) OF_MODE;
277 m32r_mode_class[i] = 0;
280 m32r_mode_class[i] = 1 << (int) C_MODE;
283 m32r_mode_class[i] = 0;
288 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
291 m32r_regno_reg_class[i] = GENERAL_REGS;
292 else if (i == ARG_POINTER_REGNUM)
293 m32r_regno_reg_class[i] = GENERAL_REGS;
295 m32r_regno_reg_class[i] = NO_REGS;
299 /* M32R specific attribute support.
301 interrupt - for interrupt functions
303 model - select code model used to access object
305 small: addresses use 24 bits, use bl to make calls
306 medium: addresses use 32 bits, use bl to make calls
307 large: addresses use 32 bits, use seth/add3/jl to make calls
309 Grep for MODEL in m32r.h for more info. */
311 static tree small_ident1;
312 static tree small_ident2;
313 static tree medium_ident1;
314 static tree medium_ident2;
315 static tree large_ident1;
316 static tree large_ident2;
321 if (small_ident1 == 0)
323 small_ident1 = get_identifier ("small");
324 small_ident2 = get_identifier ("__small__");
325 medium_ident1 = get_identifier ("medium");
326 medium_ident2 = get_identifier ("__medium__");
327 large_ident1 = get_identifier ("large");
328 large_ident2 = get_identifier ("__large__");
332 const struct attribute_spec m32r_attribute_table[] =
334 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
335 { "interrupt", 0, 0, true, false, false, NULL },
336 { "model", 1, 1, true, false, false, m32r_handle_model_attribute },
337 { NULL, 0, 0, false, false, false, NULL }
341 /* Handle an "model" attribute; arguments as in
342 struct attribute_spec.handler. */
344 m32r_handle_model_attribute (tree *node ATTRIBUTE_UNUSED, tree name,
345 tree args, int flags ATTRIBUTE_UNUSED,
351 arg = TREE_VALUE (args);
353 if (arg != small_ident1
354 && arg != small_ident2
355 && arg != medium_ident1
356 && arg != medium_ident2
357 && arg != large_ident1
358 && arg != large_ident2)
360 warning ("invalid argument of %qs attribute",
361 IDENTIFIER_POINTER (name));
362 *no_add_attrs = true;
368 /* Encode section information of DECL, which is either a VAR_DECL,
369 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
371 For the M32R we want to record:
373 - whether the object lives in .sdata/.sbss.
374 - what code model should be used to access the object
378 m32r_encode_section_info (tree decl, rtx rtl, int first)
382 enum m32r_model model;
384 default_encode_section_info (decl, rtl, first);
389 model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
396 id = TREE_VALUE (TREE_VALUE (model_attr));
398 if (id == small_ident1 || id == small_ident2)
399 model = M32R_MODEL_SMALL;
400 else if (id == medium_ident1 || id == medium_ident2)
401 model = M32R_MODEL_MEDIUM;
402 else if (id == large_ident1 || id == large_ident2)
403 model = M32R_MODEL_LARGE;
405 abort (); /* shouldn't happen */
409 if (TARGET_MODEL_SMALL)
410 model = M32R_MODEL_SMALL;
411 else if (TARGET_MODEL_MEDIUM)
412 model = M32R_MODEL_MEDIUM;
413 else if (TARGET_MODEL_LARGE)
414 model = M32R_MODEL_LARGE;
416 abort (); /* shouldn't happen */
418 extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT;
421 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
424 /* Only mark the object as being small data area addressable if
425 it hasn't been explicitly marked with a code model.
427 The user can explicitly put an object in the small data area with the
428 section attribute. If the object is in sdata/sbss and marked with a
429 code model do both [put the object in .sdata and mark it as being
430 addressed with a specific code model - don't mark it as being addressed
431 with an SDA reloc though]. This is ok and might be useful at times. If
432 the object doesn't fit the linker will give an error. */
435 m32r_in_small_data_p (tree decl)
439 if (TREE_CODE (decl) != VAR_DECL)
442 if (lookup_attribute ("model", DECL_ATTRIBUTES (decl)))
445 section = DECL_SECTION_NAME (decl);
448 char *name = (char *) TREE_STRING_POINTER (section);
449 if (strcmp (name, ".sdata") == 0 || strcmp (name, ".sbss") == 0)
454 if (! TREE_READONLY (decl) && ! TARGET_SDATA_NONE)
456 int size = int_size_in_bytes (TREE_TYPE (decl));
458 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
466 /* Do anything needed before RTL is emitted for each function. */
469 m32r_init_expanders (void)
471 /* ??? At one point there was code here. The function is left in
472 to make it easy to experiment. */
476 call_operand (rtx op, enum machine_mode mode)
478 if (GET_CODE (op) != MEM)
481 return call_address_operand (op, mode);
484 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */
487 small_data_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
489 if (! TARGET_SDATA_USE)
492 if (GET_CODE (op) == SYMBOL_REF)
493 return SYMBOL_REF_SMALL_P (op);
495 if (GET_CODE (op) == CONST
496 && GET_CODE (XEXP (op, 0)) == PLUS
497 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
498 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
499 && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
500 return SYMBOL_REF_SMALL_P (XEXP (XEXP (op, 0), 0));
505 /* Return 1 if OP is a symbol that can use 24 bit addressing. */
508 addr24_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
515 if (GET_CODE (op) == LABEL_REF)
516 return TARGET_ADDR24;
518 if (GET_CODE (op) == SYMBOL_REF)
520 else if (GET_CODE (op) == CONST
521 && GET_CODE (XEXP (op, 0)) == PLUS
522 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
523 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
524 && UINT24_P (INTVAL (XEXP (XEXP (op, 0), 1))))
525 sym = XEXP (XEXP (op, 0), 0);
529 if (SYMBOL_REF_MODEL (sym) == M32R_MODEL_SMALL)
533 && (CONSTANT_POOL_ADDRESS_P (sym)
534 || LIT_NAME_P (XSTR (sym, 0))))
540 /* Return 1 if OP is a symbol that needs 32 bit addressing. */
543 addr32_operand (rtx op, enum machine_mode mode)
547 if (GET_CODE (op) == LABEL_REF)
548 return TARGET_ADDR32;
550 if (GET_CODE (op) == SYMBOL_REF)
552 else if (GET_CODE (op) == CONST
553 && GET_CODE (XEXP (op, 0)) == PLUS
554 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
555 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
557 sym = XEXP (XEXP (op, 0), 0);
561 return (! addr24_operand (sym, mode)
562 && ! small_data_operand (sym, mode));
565 /* Return 1 if OP is a function that can be called with the `bl' insn. */
568 call26_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
573 if (GET_CODE (op) == SYMBOL_REF)
574 return SYMBOL_REF_MODEL (op) != M32R_MODEL_LARGE;
576 return TARGET_CALL26;
579 /* Return 1 if OP is a DImode const we want to handle inline.
580 This must match the code in the movdi pattern.
581 It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER. */
584 easy_di_const (rtx op)
586 rtx high_rtx, low_rtx;
587 HOST_WIDE_INT high, low;
589 split_double (op, &high_rtx, &low_rtx);
590 high = INTVAL (high_rtx);
591 low = INTVAL (low_rtx);
592 /* Pick constants loadable with 2 16 bit `ldi' insns. */
593 if (high >= -128 && high <= 127
594 && low >= -128 && low <= 127)
599 /* Return 1 if OP is a DFmode const we want to handle inline.
600 This must match the code in the movdf pattern.
601 It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER. */
604 easy_df_const (rtx op)
609 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
610 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
611 if (l[0] == 0 && l[1] == 0)
613 if ((l[0] & 0xffff) == 0 && l[1] == 0)
618 /* Return 1 if OP is (mem (reg ...)).
619 This is used in insn length calcs. */
622 memreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
624 return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == REG;
627 /* Return nonzero if TYPE must be passed by indirect reference. */
630 m32r_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
631 enum machine_mode mode, tree type,
632 bool named ATTRIBUTE_UNUSED)
637 size = int_size_in_bytes (type);
639 size = GET_MODE_SIZE (mode);
641 return (size < 0 || size > 8);
646 /* X and Y are two things to compare using CODE. Emit the compare insn and
647 return the rtx for compare [arg0 of the if_then_else].
648 If need_compare is true then the comparison insn must be generated, rather
649 than being subsumed into the following branch instruction. */
652 gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare)
654 enum rtx_code compare_code;
655 enum rtx_code branch_code;
656 rtx cc_reg = gen_rtx_REG (CCmode, CARRY_REGNUM);
661 case EQ: compare_code = EQ; branch_code = NE; break;
662 case NE: compare_code = EQ; branch_code = EQ; break;
663 case LT: compare_code = LT; branch_code = NE; break;
664 case LE: compare_code = LT; branch_code = EQ; must_swap = 1; break;
665 case GT: compare_code = LT; branch_code = NE; must_swap = 1; break;
666 case GE: compare_code = LT; branch_code = EQ; break;
667 case LTU: compare_code = LTU; branch_code = NE; break;
668 case LEU: compare_code = LTU; branch_code = EQ; must_swap = 1; break;
669 case GTU: compare_code = LTU; branch_code = NE; must_swap = 1; break;
670 case GEU: compare_code = LTU; branch_code = EQ; break;
678 switch (compare_code)
681 if (GET_CODE (y) == CONST_INT
682 && CMP_INT16_P (INTVAL (y)) /* Reg equal to small const. */
685 rtx tmp = gen_reg_rtx (SImode);
687 emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y))));
691 else if (CONSTANT_P (y)) /* Reg equal to const. */
693 rtx tmp = force_reg (GET_MODE (x), y);
697 if (register_operand (y, SImode) /* Reg equal to reg. */
698 || y == const0_rtx) /* Reg equal to zero. */
700 emit_insn (gen_cmp_eqsi_insn (x, y));
702 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
707 if (register_operand (y, SImode)
708 || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
710 rtx tmp = gen_reg_rtx (SImode); /* Reg compared to reg. */
715 emit_insn (gen_cmp_ltsi_insn (x, y));
722 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
723 emit_insn (gen_cmp_ltsi_insn (x, tmp));
727 if (GET_CODE (y) == CONST_INT)
728 tmp = gen_rtx_PLUS (SImode, y, const1_rtx);
730 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
731 emit_insn (gen_cmp_ltsi_insn (x, tmp));
735 emit_insn (gen_cmp_ltsi_insn (x, y));
742 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
747 if (register_operand (y, SImode)
748 || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
750 rtx tmp = gen_reg_rtx (SImode); /* Reg (unsigned) compared to reg. */
755 emit_insn (gen_cmp_ltusi_insn (x, y));
762 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
763 emit_insn (gen_cmp_ltusi_insn (x, tmp));
767 if (GET_CODE (y) == CONST_INT)
768 tmp = gen_rtx_PLUS (SImode, y, const1_rtx);
770 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
771 emit_insn (gen_cmp_ltusi_insn (x, tmp));
775 emit_insn (gen_cmp_ltusi_insn (x, y));
782 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
792 /* Reg/reg equal comparison. */
793 if (compare_code == EQ
794 && register_operand (y, SImode))
795 return gen_rtx_fmt_ee (code, CCmode, x, y);
797 /* Reg/zero signed comparison. */
798 if ((compare_code == EQ || compare_code == LT)
800 return gen_rtx_fmt_ee (code, CCmode, x, y);
802 /* Reg/smallconst equal comparison. */
803 if (compare_code == EQ
804 && GET_CODE (y) == CONST_INT
805 && CMP_INT16_P (INTVAL (y)))
807 rtx tmp = gen_reg_rtx (SImode);
809 emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y))));
810 return gen_rtx_fmt_ee (code, CCmode, tmp, const0_rtx);
813 /* Reg/const equal comparison. */
814 if (compare_code == EQ
817 rtx tmp = force_reg (GET_MODE (x), y);
819 return gen_rtx_fmt_ee (code, CCmode, x, tmp);
826 y = force_reg (GET_MODE (x), y);
829 int ok_const = reg_or_int16_operand (y, GET_MODE (y));
832 y = force_reg (GET_MODE (x), y);
836 switch (compare_code)
839 emit_insn (gen_cmp_eqsi_insn (must_swap ? y : x, must_swap ? x : y));
842 emit_insn (gen_cmp_ltsi_insn (must_swap ? y : x, must_swap ? x : y));
845 emit_insn (gen_cmp_ltusi_insn (must_swap ? y : x, must_swap ? x : y));
852 return gen_rtx_fmt_ee (branch_code, VOIDmode, cc_reg, CONST0_RTX (CCmode));
855 /* Split a 2 word move (DI or DF) into component parts. */
858 gen_split_move_double (rtx operands[])
860 enum machine_mode mode = GET_MODE (operands[0]);
861 rtx dest = operands[0];
862 rtx src = operands[1];
865 /* We might have (SUBREG (MEM)) here, so just get rid of the
866 subregs to make this code simpler. It is safe to call
867 alter_subreg any time after reload. */
868 if (GET_CODE (dest) == SUBREG)
869 alter_subreg (&dest);
870 if (GET_CODE (src) == SUBREG)
874 if (GET_CODE (dest) == REG)
876 int dregno = REGNO (dest);
879 if (GET_CODE (src) == REG)
881 int sregno = REGNO (src);
883 int reverse = (dregno == sregno + 1);
885 /* We normally copy the low-numbered register first. However, if
886 the first register operand 0 is the same as the second register of
887 operand 1, we must copy in the opposite order. */
888 emit_insn (gen_rtx_SET (VOIDmode,
889 operand_subword (dest, reverse, TRUE, mode),
890 operand_subword (src, reverse, TRUE, mode)));
892 emit_insn (gen_rtx_SET (VOIDmode,
893 operand_subword (dest, !reverse, TRUE, mode),
894 operand_subword (src, !reverse, TRUE, mode)));
897 /* Reg = constant. */
898 else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE)
901 split_double (src, &words[0], &words[1]);
902 emit_insn (gen_rtx_SET (VOIDmode,
903 operand_subword (dest, 0, TRUE, mode),
906 emit_insn (gen_rtx_SET (VOIDmode,
907 operand_subword (dest, 1, TRUE, mode),
912 else if (GET_CODE (src) == MEM)
914 /* If the high-address word is used in the address, we must load it
915 last. Otherwise, load it first. */
917 = (refers_to_regno_p (dregno, dregno + 1, XEXP (src, 0), 0) != 0);
919 /* We used to optimize loads from single registers as
923 if r3 were not used subsequently. However, the REG_NOTES aren't
924 propagated correctly by the reload phase, and it can cause bad
925 code to be generated. We could still try:
927 ld r1,r3+; ld r2,r3; addi r3,-4
929 which saves 2 bytes and doesn't force longword alignment. */
930 emit_insn (gen_rtx_SET (VOIDmode,
931 operand_subword (dest, reverse, TRUE, mode),
932 adjust_address (src, SImode,
933 reverse * UNITS_PER_WORD)));
935 emit_insn (gen_rtx_SET (VOIDmode,
936 operand_subword (dest, !reverse, TRUE, mode),
937 adjust_address (src, SImode,
938 !reverse * UNITS_PER_WORD)));
945 /* We used to optimize loads from single registers as
949 if r3 were not used subsequently. However, the REG_NOTES aren't
950 propagated correctly by the reload phase, and it can cause bad
951 code to be generated. We could still try:
953 st r1,r3; st r2,+r3; addi r3,-4
955 which saves 2 bytes and doesn't force longword alignment. */
956 else if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
958 emit_insn (gen_rtx_SET (VOIDmode,
959 adjust_address (dest, SImode, 0),
960 operand_subword (src, 0, TRUE, mode)));
962 emit_insn (gen_rtx_SET (VOIDmode,
963 adjust_address (dest, SImode, UNITS_PER_WORD),
964 operand_subword (src, 1, TRUE, mode)));
977 m32r_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
978 tree type, bool named ATTRIBUTE_UNUSED)
982 (((mode == BLKmode && type)
983 ? (unsigned int) int_size_in_bytes (type)
984 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
987 if (*cum >= M32R_MAX_PARM_REGS)
989 else if (*cum + size > M32R_MAX_PARM_REGS)
990 words = (*cum + size) - M32R_MAX_PARM_REGS;
994 return words * UNITS_PER_WORD;
997 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1000 m32r_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
1002 return m32r_pass_by_reference (NULL, TYPE_MODE (type), type, false);
1005 /* Do any needed setup for a variadic function. For the M32R, we must
1006 create a register parameter block, and then copy any anonymous arguments
1007 in registers to memory.
1009 CUM has not been updated for the last named argument which has type TYPE
1010 and mode MODE, and we rely on this fact. */
1013 m32r_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1014 tree type, int *pretend_size, int no_rtl)
1021 /* All BLKmode values are passed by reference. */
1022 if (mode == BLKmode)
1025 first_anon_arg = (ROUND_ADVANCE_CUM (*cum, mode, type)
1026 + ROUND_ADVANCE_ARG (mode, type));
1028 if (first_anon_arg < M32R_MAX_PARM_REGS)
1030 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1031 int first_reg_offset = first_anon_arg;
1032 /* Size in words to "pretend" allocate. */
1033 int size = M32R_MAX_PARM_REGS - first_reg_offset;
1036 regblock = gen_rtx_MEM (BLKmode,
1037 plus_constant (arg_pointer_rtx,
1038 FIRST_PARM_OFFSET (0)));
1039 set_mem_alias_set (regblock, get_varargs_alias_set ());
1040 move_block_from_reg (first_reg_offset, regblock, size);
1042 *pretend_size = (size * UNITS_PER_WORD);
1047 /* Return true if INSN is real instruction bearing insn. */
1050 m32r_is_insn (rtx insn)
1052 return (INSN_P (insn)
1053 && GET_CODE (PATTERN (insn)) != USE
1054 && GET_CODE (PATTERN (insn)) != CLOBBER
1055 && GET_CODE (PATTERN (insn)) != ADDR_VEC);
1058 /* Increase the priority of long instructions so that the
1059 short instructions are scheduled ahead of the long ones. */
1062 m32r_adjust_priority (rtx insn, int priority)
1064 if (m32r_is_insn (insn)
1065 && get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1072 /* Indicate how many instructions can be issued at the same time.
1073 This is sort of a lie. The m32r can issue only 1 long insn at
1074 once, but it can issue 2 short insns. The default therefore is
1075 set at 2, but this can be overridden by the command line option
1079 m32r_issue_rate (void)
1081 return ((TARGET_LOW_ISSUE_RATE) ? 1 : 2);
1084 /* Cost functions. */
1087 m32r_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, int *total)
1091 /* Small integers are as cheap as registers. 4 byte values can be
1092 fetched as immediate constants - let's give that the cost of an
1095 if (INT16_P (INTVAL (x)))
1105 *total = COSTS_N_INSNS (1);
1112 split_double (x, &high, &low);
1113 *total = COSTS_N_INSNS (!INT16_P (INTVAL (high))
1114 + !INT16_P (INTVAL (low)));
1119 *total = COSTS_N_INSNS (3);
1126 *total = COSTS_N_INSNS (10);
1134 /* Type of function DECL.
1136 The result is cached. To reset the cache at the end of a function,
1137 call with DECL = NULL_TREE. */
1139 enum m32r_function_type
1140 m32r_compute_function_type (tree decl)
1143 static enum m32r_function_type fn_type = M32R_FUNCTION_UNKNOWN;
1144 /* Last function we were called for. */
1145 static tree last_fn = NULL_TREE;
1147 /* Resetting the cached value? */
1148 if (decl == NULL_TREE)
1150 fn_type = M32R_FUNCTION_UNKNOWN;
1151 last_fn = NULL_TREE;
1155 if (decl == last_fn && fn_type != M32R_FUNCTION_UNKNOWN)
1158 /* Compute function type. */
1159 fn_type = (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE
1160 ? M32R_FUNCTION_INTERRUPT
1161 : M32R_FUNCTION_NORMAL);
1166 \f/* Function prologue/epilogue handlers. */
1168 /* M32R stack frames look like:
1170 Before call After call
1171 +-----------------------+ +-----------------------+
1173 high | local variables, | | local variables, |
1174 mem | reg save area, etc. | | reg save area, etc. |
1176 +-----------------------+ +-----------------------+
1178 | arguments on stack. | | arguments on stack. |
1180 SP+0->+-----------------------+ +-----------------------+
1181 | reg parm save area, |
1182 | only created for |
1183 | variable argument |
1185 +-----------------------+
1186 | previous frame ptr |
1187 +-----------------------+
1189 | register save area |
1191 +-----------------------+
1193 +-----------------------+
1197 +-----------------------+
1199 | alloca allocations |
1201 +-----------------------+
1203 low | arguments on stack |
1205 SP+0->+-----------------------+
1208 1) The "reg parm save area" does not exist for non variable argument fns.
1209 2) The "reg parm save area" can be eliminated completely if we saved regs
1210 containing anonymous args separately but that complicates things too
1211 much (so it's not done).
1212 3) The return address is saved after the register save area so as to have as
1213 many insns as possible between the restoration of `lr' and the `jmp lr'. */
1215 /* Structure to be filled in by m32r_compute_frame_size with register
1216 save masks, and offsets for the current function. */
1217 struct m32r_frame_info
1219 unsigned int total_size; /* # bytes that the entire frame takes up. */
1220 unsigned int extra_size; /* # bytes of extra stuff. */
1221 unsigned int pretend_size; /* # bytes we push and pretend caller did. */
1222 unsigned int args_size; /* # bytes that outgoing arguments take up. */
1223 unsigned int reg_size; /* # bytes needed to store regs. */
1224 unsigned int var_size; /* # bytes that variables take up. */
1225 unsigned int gmask; /* Mask of saved gp registers. */
1226 unsigned int save_fp; /* Nonzero if fp must be saved. */
1227 unsigned int save_lr; /* Nonzero if lr (return addr) must be saved. */
1228 int initialized; /* Nonzero if frame size already calculated. */
1231 /* Current frame information calculated by m32r_compute_frame_size. */
1232 static struct m32r_frame_info current_frame_info;
1234 /* Zero structure to initialize current_frame_info. */
1235 static struct m32r_frame_info zero_frame_info;
1237 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1238 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1240 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1241 The return address and frame pointer are treated separately.
1242 Don't consider them here. */
1243 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1244 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1245 && (regs_ever_live[regno] && (!call_really_used_regs[regno] || interrupt_p)))
1247 #define MUST_SAVE_FRAME_POINTER (regs_ever_live[FRAME_POINTER_REGNUM])
1248 #define MUST_SAVE_RETURN_ADDR (regs_ever_live[RETURN_ADDR_REGNUM] || current_function_profile)
1250 #define SHORT_INSN_SIZE 2 /* Size of small instructions. */
1251 #define LONG_INSN_SIZE 4 /* Size of long instructions. */
1253 /* Return the bytes needed to compute the frame pointer from the current
1256 SIZE is the size needed for local variables. */
1259 m32r_compute_frame_size (int size) /* # of var. bytes allocated. */
1262 unsigned int total_size, var_size, args_size, pretend_size, extra_size;
1263 unsigned int reg_size, frame_size;
1265 enum m32r_function_type fn_type;
1267 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table);
1269 var_size = M32R_STACK_ALIGN (size);
1270 args_size = M32R_STACK_ALIGN (current_function_outgoing_args_size);
1271 pretend_size = current_function_pretend_args_size;
1272 extra_size = FIRST_PARM_OFFSET (0);
1273 total_size = extra_size + pretend_size + args_size + var_size;
1277 /* See if this is an interrupt handler. Call used registers must be saved
1279 fn_type = m32r_compute_function_type (current_function_decl);
1280 interrupt_p = M32R_INTERRUPT_P (fn_type);
1282 /* Calculate space needed for registers. */
1283 for (regno = 0; regno < M32R_MAX_INT_REGS; regno++)
1285 if (MUST_SAVE_REGISTER (regno, interrupt_p)
1286 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
1288 reg_size += UNITS_PER_WORD;
1289 gmask |= 1 << regno;
1293 current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER;
1294 current_frame_info.save_lr = MUST_SAVE_RETURN_ADDR || pic_reg_used;
1296 reg_size += ((current_frame_info.save_fp + current_frame_info.save_lr)
1298 total_size += reg_size;
1300 /* ??? Not sure this is necessary, and I don't think the epilogue
1301 handler will do the right thing if this changes total_size. */
1302 total_size = M32R_STACK_ALIGN (total_size);
1304 frame_size = total_size - (pretend_size + reg_size);
1306 /* Save computed information. */
1307 current_frame_info.total_size = total_size;
1308 current_frame_info.extra_size = extra_size;
1309 current_frame_info.pretend_size = pretend_size;
1310 current_frame_info.var_size = var_size;
1311 current_frame_info.args_size = args_size;
1312 current_frame_info.reg_size = reg_size;
1313 current_frame_info.gmask = gmask;
1314 current_frame_info.initialized = reload_completed;
1316 /* Ok, we're done. */
1320 /* The table we use to reference PIC data. */
1321 static rtx global_offset_table;
1324 m32r_reload_lr (rtx sp, int size)
1326 rtx lr = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
1329 emit_insn (gen_movsi (lr, gen_rtx_MEM (Pmode, sp)));
1330 else if (size <= 32768)
1331 emit_insn (gen_movsi (lr, gen_rtx_MEM (Pmode,
1332 gen_rtx_PLUS (Pmode, sp,
1336 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1338 emit_insn (gen_movsi (tmp, GEN_INT (size)));
1339 emit_insn (gen_addsi3 (tmp, tmp, sp));
1340 emit_insn (gen_movsi (lr, gen_rtx_MEM (Pmode, tmp)));
1343 emit_insn (gen_rtx_USE (VOIDmode, lr));
1347 m32r_load_pic_register (void)
1349 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
1350 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
1351 GEN_INT (TARGET_MODEL_SMALL)));
1353 /* Need to emit this whether or not we obey regdecls,
1354 since setjmp/longjmp can cause life info to screw up. */
1355 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
1358 /* Expand the m32r prologue as a series of insns. */
1361 m32r_expand_prologue (void)
1366 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table);
1368 if (! current_frame_info.initialized)
1369 m32r_compute_frame_size (get_frame_size ());
1371 gmask = current_frame_info.gmask;
1373 /* These cases shouldn't happen. Catch them now. */
1374 if (current_frame_info.total_size == 0 && gmask)
1377 /* Allocate space for register arguments if this is a variadic function. */
1378 if (current_frame_info.pretend_size != 0)
1380 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1381 the wrong result on a 64-bit host. */
1382 HOST_WIDE_INT pretend_size = current_frame_info.pretend_size;
1383 emit_insn (gen_addsi3 (stack_pointer_rtx,
1385 GEN_INT (-pretend_size)));
1388 /* Save any registers we need to and set up fp. */
1389 if (current_frame_info.save_fp)
1390 emit_insn (gen_movsi_push (stack_pointer_rtx, frame_pointer_rtx));
1392 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1394 /* Save any needed call-saved regs (and call-used if this is an
1395 interrupt handler). */
1396 for (regno = 0; regno <= M32R_MAX_INT_REGS; ++regno)
1398 if ((gmask & (1 << regno)) != 0)
1399 emit_insn (gen_movsi_push (stack_pointer_rtx,
1400 gen_rtx_REG (Pmode, regno)));
1403 if (current_frame_info.save_lr)
1404 emit_insn (gen_movsi_push (stack_pointer_rtx,
1405 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
1407 /* Allocate the stack frame. */
1408 frame_size = (current_frame_info.total_size
1409 - (current_frame_info.pretend_size
1410 + current_frame_info.reg_size));
1412 if (frame_size == 0)
1413 ; /* Nothing to do. */
1414 else if (frame_size <= 32768)
1415 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1416 GEN_INT (-frame_size)));
1419 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1421 emit_insn (gen_movsi (tmp, GEN_INT (frame_size)));
1422 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
1425 if (frame_pointer_needed)
1426 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
1428 if (current_function_profile)
1429 /* Push lr for mcount (form_pc, x). */
1430 emit_insn (gen_movsi_push (stack_pointer_rtx,
1431 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
1435 m32r_load_pic_register ();
1436 m32r_reload_lr (stack_pointer_rtx,
1437 (current_function_profile ? 0 : frame_size));
1440 if (current_function_profile && !pic_reg_used)
1441 emit_insn (gen_blockage ());
1445 /* Set up the stack and frame pointer (if desired) for the function.
1446 Note, if this is changed, you need to mirror the changes in
1447 m32r_compute_frame_size which calculates the prolog size. */
1450 m32r_output_function_prologue (FILE * file, HOST_WIDE_INT size)
1452 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
1454 /* If this is an interrupt handler, mark it as such. */
1455 if (M32R_INTERRUPT_P (fn_type))
1456 fprintf (file, "\t%s interrupt handler\n", ASM_COMMENT_START);
1458 if (! current_frame_info.initialized)
1459 m32r_compute_frame_size (size);
1461 /* This is only for the human reader. */
1463 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
1465 current_frame_info.var_size,
1466 current_frame_info.reg_size / 4,
1467 current_frame_info.args_size,
1468 current_frame_info.extra_size);
1471 /* Do any necessary cleanup after a function to restore stack, frame,
1475 m32r_output_function_epilogue (FILE * file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1478 int noepilogue = FALSE;
1480 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
1482 /* This is only for the human reader. */
1483 fprintf (file, "\t%s EPILOGUE\n", ASM_COMMENT_START);
1485 if (!current_frame_info.initialized)
1487 total_size = current_frame_info.total_size;
1489 if (total_size == 0)
1491 rtx insn = get_last_insn ();
1493 /* If the last insn was a BARRIER, we don't have to write any code
1494 because a jump (aka return) was put there. */
1495 if (GET_CODE (insn) == NOTE)
1496 insn = prev_nonnote_insn (insn);
1497 if (insn && GET_CODE (insn) == BARRIER)
1503 unsigned int var_size = current_frame_info.var_size;
1504 unsigned int args_size = current_frame_info.args_size;
1505 unsigned int gmask = current_frame_info.gmask;
1506 int can_trust_sp_p = !current_function_calls_alloca;
1507 const char * sp_str = reg_names[STACK_POINTER_REGNUM];
1508 const char * fp_str = reg_names[FRAME_POINTER_REGNUM];
1510 /* The first thing to do is point the sp at the bottom of the register
1514 unsigned int reg_offset = var_size + args_size;
1515 if (reg_offset == 0)
1516 ; /* Nothing to do. */
1517 else if (reg_offset < 128)
1518 fprintf (file, "\taddi %s,%s%d\n",
1519 sp_str, IMMEDIATE_PREFIX, reg_offset);
1520 else if (reg_offset < 32768)
1521 fprintf (file, "\tadd3 %s,%s,%s%d\n",
1522 sp_str, sp_str, IMMEDIATE_PREFIX, reg_offset);
1524 fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
1525 reg_names[PROLOGUE_TMP_REGNUM],
1526 IMMEDIATE_PREFIX, reg_offset,
1527 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
1529 else if (frame_pointer_needed)
1531 unsigned int reg_offset = var_size + args_size;
1533 if (reg_offset == 0)
1534 fprintf (file, "\tmv %s,%s\n", sp_str, fp_str);
1535 else if (reg_offset < 32768)
1536 fprintf (file, "\tadd3 %s,%s,%s%d\n",
1537 sp_str, fp_str, IMMEDIATE_PREFIX, reg_offset);
1539 fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
1540 reg_names[PROLOGUE_TMP_REGNUM],
1541 IMMEDIATE_PREFIX, reg_offset,
1542 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
1547 if (current_frame_info.save_lr)
1548 fprintf (file, "\tpop %s\n", reg_names[RETURN_ADDR_REGNUM]);
1550 /* Restore any saved registers, in reverse order of course. */
1551 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1552 for (regno = M32R_MAX_INT_REGS - 1; regno >= 0; --regno)
1554 if ((gmask & (1L << regno)) != 0)
1555 fprintf (file, "\tpop %s\n", reg_names[regno]);
1558 if (current_frame_info.save_fp)
1559 fprintf (file, "\tpop %s\n", fp_str);
1561 /* Remove varargs area if present. */
1562 if (current_frame_info.pretend_size != 0)
1563 fprintf (file, "\taddi %s,%s%d\n",
1564 sp_str, IMMEDIATE_PREFIX, current_frame_info.pretend_size);
1566 /* Emit the return instruction. */
1567 if (M32R_INTERRUPT_P (fn_type))
1568 fprintf (file, "\trte\n");
1570 fprintf (file, "\tjmp %s\n", reg_names[RETURN_ADDR_REGNUM]);
1573 /* Reset state info for each function. */
1574 current_frame_info = zero_frame_info;
1575 m32r_compute_function_type (NULL_TREE);
1578 /* Return nonzero if this function is known to have a null or 1 instruction
1582 direct_return (void)
1584 if (!reload_completed)
1587 if (! current_frame_info.initialized)
1588 m32r_compute_frame_size (get_frame_size ());
1590 return current_frame_info.total_size == 0;
1597 m32r_legitimate_pic_operand_p (rtx x)
1599 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1602 if (GET_CODE (x) == CONST
1603 && GET_CODE (XEXP (x, 0)) == PLUS
1604 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
1605 || GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF)
1606 && (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
1613 m32r_legitimize_pic_address (rtx orig, rtx reg)
1616 printf("m32r_legitimize_pic_address()\n");
1619 if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
1621 rtx pic_ref, address;
1627 if (reload_in_progress || reload_completed)
1630 reg = gen_reg_rtx (Pmode);
1636 address = gen_reg_rtx (Pmode);
1640 current_function_uses_pic_offset_table = 1;
1642 if (GET_CODE (orig) == LABEL_REF
1643 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
1645 emit_insn (gen_gotoff_load_addr (reg, orig));
1646 emit_insn (gen_addsi3 (reg, reg, pic_offset_table_rtx));
1650 emit_insn (gen_pic_load_addr (address, orig));
1652 emit_insn (gen_addsi3 (address, address, pic_offset_table_rtx));
1653 pic_ref = gen_const_mem (Pmode, address);
1654 insn = emit_move_insn (reg, pic_ref);
1656 /* Put a REG_EQUAL note on this insn, so that it can be optimized
1658 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
1663 else if (GET_CODE (orig) == CONST)
1667 if (GET_CODE (XEXP (orig, 0)) == PLUS
1668 && XEXP (XEXP (orig, 0), 1) == pic_offset_table_rtx)
1673 if (reload_in_progress || reload_completed)
1676 reg = gen_reg_rtx (Pmode);
1679 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1681 base = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), reg);
1683 offset = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), NULL_RTX);
1685 offset = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), reg);
1690 if (GET_CODE (offset) == CONST_INT)
1692 if (INT16_P (INTVAL (offset)))
1693 return plus_constant (base, INTVAL (offset));
1694 else if (! reload_in_progress && ! reload_completed)
1695 offset = force_reg (Pmode, offset);
1697 /* If we reach here, then something is seriously wrong. */
1701 return gen_rtx_PLUS (Pmode, base, offset);
1707 /* Emit special PIC prologues and epilogues. */
1710 m32r_finalize_pic (void)
1712 current_function_uses_pic_offset_table |= current_function_profile;
1715 /* Nested function support. */
1717 /* Emit RTL insns to initialize the variable parts of a trampoline.
1718 FNADDR is an RTX for the address of the function's pure code.
1719 CXT is an RTX for the static chain value for the function. */
1722 m32r_initialize_trampoline (rtx tramp ATTRIBUTE_UNUSED,
1723 rtx fnaddr ATTRIBUTE_UNUSED,
1724 rtx cxt ATTRIBUTE_UNUSED)
1729 m32r_file_start (void)
1731 default_file_start ();
1733 if (flag_verbose_asm)
1734 fprintf (asm_out_file,
1735 "%s M32R/D special options: -G " HOST_WIDE_INT_PRINT_UNSIGNED "\n",
1736 ASM_COMMENT_START, g_switch_value);
1738 if (TARGET_LITTLE_ENDIAN)
1739 fprintf (asm_out_file, "\t.little\n");
1742 /* Print operand X (an rtx) in assembler syntax to file FILE.
1743 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1744 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1747 m32r_print_operand (FILE * file, rtx x, int code)
1753 /* The 's' and 'p' codes are used by output_block_move() to
1754 indicate post-increment 's'tores and 'p're-increment loads. */
1756 if (GET_CODE (x) == REG)
1757 fprintf (file, "@+%s", reg_names [REGNO (x)]);
1759 output_operand_lossage ("invalid operand to %%s code");
1763 if (GET_CODE (x) == REG)
1764 fprintf (file, "@%s+", reg_names [REGNO (x)]);
1766 output_operand_lossage ("invalid operand to %%p code");
1770 /* Write second word of DImode or DFmode reference,
1771 register or memory. */
1772 if (GET_CODE (x) == REG)
1773 fputs (reg_names[REGNO (x)+1], file);
1774 else if (GET_CODE (x) == MEM)
1776 fprintf (file, "@(");
1777 /* Handle possible auto-increment. Since it is pre-increment and
1778 we have already done it, we can just use an offset of four. */
1779 /* ??? This is taken from rs6000.c I think. I don't think it is
1780 currently necessary, but keep it around. */
1781 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1782 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1783 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
1785 output_address (plus_constant (XEXP (x, 0), 4));
1789 output_operand_lossage ("invalid operand to %%R code");
1792 case 'H' : /* High word. */
1793 case 'L' : /* Low word. */
1794 if (GET_CODE (x) == REG)
1796 /* L = least significant word, H = most significant word. */
1797 if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L'))
1798 fputs (reg_names[REGNO (x)], file);
1800 fputs (reg_names[REGNO (x)+1], file);
1802 else if (GET_CODE (x) == CONST_INT
1803 || GET_CODE (x) == CONST_DOUBLE)
1807 split_double (x, &first, &second);
1808 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
1809 code == 'L' ? INTVAL (first) : INTVAL (second));
1812 output_operand_lossage ("invalid operand to %%H/%%L code");
1819 if (GET_CODE (x) != CONST_DOUBLE
1820 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
1821 fatal_insn ("bad insn for 'A'", x);
1823 real_to_decimal (str, CONST_DOUBLE_REAL_VALUE (x), sizeof (str), 0, 1);
1824 fprintf (file, "%s", str);
1828 case 'B' : /* Bottom half. */
1829 case 'T' : /* Top half. */
1830 /* Output the argument to a `seth' insn (sets the Top half-word).
1831 For constants output arguments to a seth/or3 pair to set Top and
1832 Bottom halves. For symbols output arguments to a seth/add3 pair to
1833 set Top and Bottom halves. The difference exists because for
1834 constants seth/or3 is more readable but for symbols we need to use
1835 the same scheme as `ld' and `st' insns (16 bit addend is signed). */
1836 switch (GET_CODE (x))
1843 split_double (x, &first, &second);
1844 x = WORDS_BIG_ENDIAN ? second : first;
1845 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
1847 ? INTVAL (x) & 0xffff
1848 : (INTVAL (x) >> 16) & 0xffff));
1854 && small_data_operand (x, VOIDmode))
1856 fputs ("sda(", file);
1857 output_addr_const (file, x);
1863 fputs (code == 'T' ? "shigh(" : "low(", file);
1864 output_addr_const (file, x);
1868 output_operand_lossage ("invalid operand to %%T/%%B code");
1875 /* Output a load/store with update indicator if appropriate. */
1876 if (GET_CODE (x) == MEM)
1878 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1879 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1883 output_operand_lossage ("invalid operand to %%U code");
1887 /* Print a constant value negated. */
1888 if (GET_CODE (x) == CONST_INT)
1889 output_addr_const (file, GEN_INT (- INTVAL (x)));
1891 output_operand_lossage ("invalid operand to %%N code");
1895 /* Print a const_int in hex. Used in comments. */
1896 if (GET_CODE (x) == CONST_INT)
1897 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
1901 fputs (IMMEDIATE_PREFIX, file);
1905 /* Do nothing special. */
1910 output_operand_lossage ("invalid operand output code");
1913 switch (GET_CODE (x))
1916 fputs (reg_names[REGNO (x)], file);
1921 if (GET_CODE (addr) == PRE_INC)
1923 if (GET_CODE (XEXP (addr, 0)) != REG)
1924 fatal_insn ("pre-increment address is not a register", x);
1926 fprintf (file, "@+%s", reg_names[REGNO (XEXP (addr, 0))]);
1928 else if (GET_CODE (addr) == PRE_DEC)
1930 if (GET_CODE (XEXP (addr, 0)) != REG)
1931 fatal_insn ("pre-decrement address is not a register", x);
1933 fprintf (file, "@-%s", reg_names[REGNO (XEXP (addr, 0))]);
1935 else if (GET_CODE (addr) == POST_INC)
1937 if (GET_CODE (XEXP (addr, 0)) != REG)
1938 fatal_insn ("post-increment address is not a register", x);
1940 fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]);
1945 output_address (XEXP (x, 0));
1951 /* We handle SFmode constants here as output_addr_const doesn't. */
1952 if (GET_MODE (x) == SFmode)
1957 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
1958 REAL_VALUE_TO_TARGET_SINGLE (d, l);
1959 fprintf (file, "0x%08lx", l);
1963 /* Fall through. Let output_addr_const deal with it. */
1966 output_addr_const (file, x);
1971 /* Print a memory address as an operand to reference that memory location. */
1974 m32r_print_operand_address (FILE * file, rtx addr)
1980 switch (GET_CODE (addr))
1983 fputs (reg_names[REGNO (addr)], file);
1987 if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
1988 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
1989 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
1990 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
1992 base = XEXP (addr, 0), index = XEXP (addr, 1);
1993 if (GET_CODE (base) == REG)
1995 /* Print the offset first (if present) to conform to the manual. */
1999 fprintf (file, "%d,", offset);
2000 fputs (reg_names[REGNO (base)], file);
2002 /* The chip doesn't support this, but left in for generality. */
2003 else if (GET_CODE (index) == REG)
2004 fprintf (file, "%s,%s",
2005 reg_names[REGNO (base)], reg_names[REGNO (index)]);
2006 /* Not sure this can happen, but leave in for now. */
2007 else if (GET_CODE (index) == SYMBOL_REF)
2009 output_addr_const (file, index);
2011 fputs (reg_names[REGNO (base)], file);
2014 fatal_insn ("bad address", addr);
2016 else if (GET_CODE (base) == LO_SUM)
2019 || GET_CODE (XEXP (base, 0)) != REG)
2021 if (small_data_operand (XEXP (base, 1), VOIDmode))
2022 fputs ("sda(", file);
2024 fputs ("low(", file);
2025 output_addr_const (file, plus_constant (XEXP (base, 1), offset));
2027 fputs (reg_names[REGNO (XEXP (base, 0))], file);
2030 fatal_insn ("bad address", addr);
2034 if (GET_CODE (XEXP (addr, 0)) != REG)
2035 fatal_insn ("lo_sum not of register", addr);
2036 if (small_data_operand (XEXP (addr, 1), VOIDmode))
2037 fputs ("sda(", file);
2039 fputs ("low(", file);
2040 output_addr_const (file, XEXP (addr, 1));
2042 fputs (reg_names[REGNO (XEXP (addr, 0))], file);
2045 case PRE_INC : /* Assume SImode. */
2046 fprintf (file, "+%s", reg_names[REGNO (XEXP (addr, 0))]);
2049 case PRE_DEC : /* Assume SImode. */
2050 fprintf (file, "-%s", reg_names[REGNO (XEXP (addr, 0))]);
2053 case POST_INC : /* Assume SImode. */
2054 fprintf (file, "%s+", reg_names[REGNO (XEXP (addr, 0))]);
2058 output_addr_const (file, addr);
2063 /* Return true if the operands are the constants 0 and 1. */
2066 zero_and_one (rtx operand1, rtx operand2)
2069 GET_CODE (operand1) == CONST_INT
2070 && GET_CODE (operand2) == CONST_INT
2071 && ( ((INTVAL (operand1) == 0) && (INTVAL (operand2) == 1))
2072 ||((INTVAL (operand1) == 1) && (INTVAL (operand2) == 0)));
2075 /* Generate the correct assembler code to handle the conditional loading of a
2076 value into a register. It is known that the operands satisfy the
2077 conditional_move_operand() function above. The destination is operand[0].
2078 The condition is operand [1]. The 'true' value is operand [2] and the
2079 'false' value is operand [3]. */
2082 emit_cond_move (rtx * operands, rtx insn ATTRIBUTE_UNUSED)
2084 static char buffer [100];
2085 const char * dest = reg_names [REGNO (operands [0])];
2089 /* Destination must be a register. */
2090 if (GET_CODE (operands [0]) != REG)
2092 if (! conditional_move_operand (operands [2], SImode))
2094 if (! conditional_move_operand (operands [3], SImode))
2097 /* Check to see if the test is reversed. */
2098 if (GET_CODE (operands [1]) == NE)
2100 rtx tmp = operands [2];
2101 operands [2] = operands [3];
2105 sprintf (buffer, "mvfc %s, cbr", dest);
2107 /* If the true value was '0' then we need to invert the results of the move. */
2108 if (INTVAL (operands [2]) == 0)
2109 sprintf (buffer + strlen (buffer), "\n\txor3 %s, %s, #1",
2115 /* Returns true if the registers contained in the two
2116 rtl expressions are different. */
2119 m32r_not_same_reg (rtx a, rtx b)
2124 while (GET_CODE (a) == SUBREG)
2127 if (GET_CODE (a) == REG)
2130 while (GET_CODE (b) == SUBREG)
2133 if (GET_CODE (b) == REG)
2136 return reg_a != reg_b;
2141 m32r_function_symbol (const char *name)
2143 int extra_flags = 0;
2144 enum m32r_model model;
2145 rtx sym = gen_rtx_SYMBOL_REF (Pmode, name);
2147 if (TARGET_MODEL_SMALL)
2148 model = M32R_MODEL_SMALL;
2149 else if (TARGET_MODEL_MEDIUM)
2150 model = M32R_MODEL_MEDIUM;
2151 else if (TARGET_MODEL_LARGE)
2152 model = M32R_MODEL_LARGE;
2154 abort (); /* Shouldn't happen. */
2155 extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT;
2158 SYMBOL_REF_FLAGS (sym) |= extra_flags;
2163 /* Use a library function to move some bytes. */
2166 block_move_call (rtx dest_reg, rtx src_reg, rtx bytes_rtx)
2168 /* We want to pass the size as Pmode, which will normally be SImode
2169 but will be DImode if we are using 64 bit longs and pointers. */
2170 if (GET_MODE (bytes_rtx) != VOIDmode
2171 && GET_MODE (bytes_rtx) != Pmode)
2172 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
2174 emit_library_call (m32r_function_symbol ("memcpy"), 0,
2175 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
2176 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
2177 TYPE_UNSIGNED (sizetype)),
2178 TYPE_MODE (sizetype));
2181 /* Expand string/block move operations.
2183 operands[0] is the pointer to the destination.
2184 operands[1] is the pointer to the source.
2185 operands[2] is the number of bytes to move.
2186 operands[3] is the alignment. */
2189 m32r_expand_block_move (rtx operands[])
2191 rtx orig_dst = operands[0];
2192 rtx orig_src = operands[1];
2193 rtx bytes_rtx = operands[2];
2194 rtx align_rtx = operands[3];
2195 int constp = GET_CODE (bytes_rtx) == CONST_INT;
2196 HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
2197 int align = INTVAL (align_rtx);
2202 if (constp && bytes <= 0)
2205 /* Move the address into scratch registers. */
2206 dst_reg = copy_addr_to_reg (XEXP (orig_dst, 0));
2207 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2209 if (align > UNITS_PER_WORD)
2210 align = UNITS_PER_WORD;
2212 /* If we prefer size over speed, always use a function call.
2213 If we do not know the size, use a function call.
2214 If the blocks are not word aligned, use a function call. */
2215 if (optimize_size || ! constp || align != UNITS_PER_WORD)
2217 block_move_call (dst_reg, src_reg, bytes_rtx);
2221 leftover = bytes % MAX_MOVE_BYTES;
2224 /* If necessary, generate a loop to handle the bulk of the copy. */
2227 rtx label = NULL_RTX;
2228 rtx final_src = NULL_RTX;
2229 rtx at_a_time = GEN_INT (MAX_MOVE_BYTES);
2230 rtx rounded_total = GEN_INT (bytes);
2231 rtx new_dst_reg = gen_reg_rtx (SImode);
2232 rtx new_src_reg = gen_reg_rtx (SImode);
2234 /* If we are going to have to perform this loop more than
2235 once, then generate a label and compute the address the
2236 source register will contain upon completion of the final
2238 if (bytes > MAX_MOVE_BYTES)
2240 final_src = gen_reg_rtx (Pmode);
2243 emit_insn (gen_addsi3 (final_src, src_reg, rounded_total));
2246 emit_insn (gen_movsi (final_src, rounded_total));
2247 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
2250 label = gen_label_rtx ();
2254 /* It is known that output_block_move() will update src_reg to point
2255 to the word after the end of the source block, and dst_reg to point
2256 to the last word of the destination block, provided that the block
2257 is MAX_MOVE_BYTES long. */
2258 emit_insn (gen_movmemsi_internal (dst_reg, src_reg, at_a_time,
2259 new_dst_reg, new_src_reg));
2260 emit_move_insn (dst_reg, new_dst_reg);
2261 emit_move_insn (src_reg, new_src_reg);
2262 emit_insn (gen_addsi3 (dst_reg, dst_reg, GEN_INT (4)));
2264 if (bytes > MAX_MOVE_BYTES)
2266 emit_insn (gen_cmpsi (src_reg, final_src));
2267 emit_jump_insn (gen_bne (label));
2272 emit_insn (gen_movmemsi_internal (dst_reg, src_reg, GEN_INT (leftover),
2273 gen_reg_rtx (SImode),
2274 gen_reg_rtx (SImode)));
2278 /* Emit load/stores for a small constant word aligned block_move.
2280 operands[0] is the memory address of the destination.
2281 operands[1] is the memory address of the source.
2282 operands[2] is the number of bytes to move.
2283 operands[3] is a temp register.
2284 operands[4] is a temp register. */
2287 m32r_output_block_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[])
2289 HOST_WIDE_INT bytes = INTVAL (operands[2]);
2293 if (bytes < 1 || bytes > MAX_MOVE_BYTES)
2296 /* We do not have a post-increment store available, so the first set of
2297 stores are done without any increment, then the remaining ones can use
2298 the pre-increment addressing mode.
2300 Note: expand_block_move() also relies upon this behavior when building
2301 loops to copy large blocks. */
2310 output_asm_insn ("ld\t%5, %p1", operands);
2311 output_asm_insn ("ld\t%6, %p1", operands);
2312 output_asm_insn ("st\t%5, @%0", operands);
2313 output_asm_insn ("st\t%6, %s0", operands);
2317 output_asm_insn ("ld\t%5, %p1", operands);
2318 output_asm_insn ("ld\t%6, %p1", operands);
2319 output_asm_insn ("st\t%5, %s0", operands);
2320 output_asm_insn ("st\t%6, %s0", operands);
2325 else if (bytes >= 4)
2330 output_asm_insn ("ld\t%5, %p1", operands);
2333 output_asm_insn ("ld\t%6, %p1", operands);
2336 output_asm_insn ("st\t%5, @%0", operands);
2338 output_asm_insn ("st\t%5, %s0", operands);
2344 /* Get the entire next word, even though we do not want all of it.
2345 The saves us from doing several smaller loads, and we assume that
2346 we cannot cause a page fault when at least part of the word is in
2347 valid memory [since we don't get called if things aren't properly
2349 int dst_offset = first_time ? 0 : 4;
2350 /* The amount of increment we have to make to the
2351 destination pointer. */
2352 int dst_inc_amount = dst_offset + bytes - 4;
2353 /* The same for the source pointer. */
2354 int src_inc_amount = bytes;
2358 /* If got_extra is true then we have already loaded
2359 the next word as part of loading and storing the previous word. */
2361 output_asm_insn ("ld\t%6, @%1", operands);
2367 output_asm_insn ("sra3\t%5, %6, #16", operands);
2368 my_operands[0] = operands[5];
2369 my_operands[1] = GEN_INT (dst_offset);
2370 my_operands[2] = operands[0];
2371 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands);
2373 /* If there is a byte left to store then increment the
2374 destination address and shift the contents of the source
2375 register down by 8 bits. We could not do the address
2376 increment in the store half word instruction, because it does
2377 not have an auto increment mode. */
2378 if (bytes > 0) /* assert (bytes == 1) */
2389 my_operands[0] = operands[6];
2390 my_operands[1] = GEN_INT (last_shift);
2391 output_asm_insn ("srai\t%0, #%1", my_operands);
2392 my_operands[0] = operands[6];
2393 my_operands[1] = GEN_INT (dst_offset);
2394 my_operands[2] = operands[0];
2395 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands);
2398 /* Update the destination pointer if needed. We have to do
2399 this so that the patterns matches what we output in this
2402 && !find_reg_note (insn, REG_UNUSED, operands[0]))
2404 my_operands[0] = operands[0];
2405 my_operands[1] = GEN_INT (dst_inc_amount);
2406 output_asm_insn ("addi\t%0, #%1", my_operands);
2409 /* Update the source pointer if needed. We have to do this
2410 so that the patterns matches what we output in this
2413 && !find_reg_note (insn, REG_UNUSED, operands[1]))
2415 my_operands[0] = operands[1];
2416 my_operands[1] = GEN_INT (src_inc_amount);
2417 output_asm_insn ("addi\t%0, #%1", my_operands);
2427 /* Return true if using NEW_REG in place of OLD_REG is ok. */
2430 m32r_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
2431 unsigned int new_reg)
2433 /* Interrupt routines can't clobber any register that isn't already used. */
2434 if (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl))
2435 && !regs_ever_live[new_reg])
2438 /* We currently emit epilogues as text, not rtl, so the liveness
2439 of the return address register isn't visible. */
2440 if (current_function_is_leaf && new_reg == RETURN_ADDR_REGNUM)
2447 m32r_return_addr (int count)
2452 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);