1 /* Subroutines used for code generation on the Mitsubishi M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
32 #include "insn-attr.h"
39 #include "m32r-protos.h"
41 #include "target-def.h"
43 /* Save the operands last given to a compare for use when we
44 generate a scc or bcc insn. */
45 rtx m32r_compare_op0, m32r_compare_op1;
47 /* Array of valid operand punctuation characters. */
48 char m32r_punct_chars[256];
50 /* Selected code model. */
51 const char * m32r_model_string = M32R_MODEL_DEFAULT;
52 enum m32r_model m32r_model;
54 /* Selected SDA support. */
55 const char * m32r_sdata_string = M32R_SDATA_DEFAULT;
56 enum m32r_sdata m32r_sdata;
58 /* Scheduler support */
59 static int m32r_sched_odd_word_p;
61 /* Forward declaration. */
62 static void init_reg_tables PARAMS ((void));
63 static void block_move_call PARAMS ((rtx, rtx, rtx));
64 static int m32r_is_insn PARAMS ((rtx));
65 const struct attribute_spec m32r_attribute_table[];
66 static tree m32r_handle_model_attribute PARAMS ((tree *, tree, tree, int, bool *));
67 static void m32r_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
68 static void m32r_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
70 static int m32r_adjust_cost PARAMS ((rtx, rtx, rtx, int));
71 static int m32r_adjust_priority PARAMS ((rtx, int));
72 static void m32r_sched_init PARAMS ((FILE *, int, int));
73 static int m32r_sched_reorder PARAMS ((FILE *, int, rtx *, int *, int));
74 static int m32r_variable_issue PARAMS ((FILE *, int, rtx, int));
75 static int m32r_issue_rate PARAMS ((void));
78 /* Initialize the GCC target structure. */
79 #undef TARGET_ATTRIBUTE_TABLE
80 #define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
82 #undef TARGET_ASM_FUNCTION_PROLOGUE
83 #define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue
84 #undef TARGET_ASM_FUNCTION_EPILOGUE
85 #define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
87 #undef TARGET_SCHED_ADJUST_COST
88 #define TARGET_SCHED_ADJUST_COST m32r_adjust_cost
89 #undef TARGET_SCHED_ADJUST_PRIORITY
90 #define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
91 #undef TARGET_SCHED_ISSUE_RATE
92 #define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
93 #undef TARGET_SCHED_VARIABLE_ISSUE
94 #define TARGET_SCHED_VARIABLE_ISSUE m32r_variable_issue
95 #undef TARGET_SCHED_INIT
96 #define TARGET_SCHED_INIT m32r_sched_init
97 #undef TARGET_SCHED_REORDER
98 #define TARGET_SCHED_REORDER m32r_sched_reorder
100 struct gcc_target targetm = TARGET_INITIALIZER;
102 /* Called by OVERRIDE_OPTIONS to initialize various things. */
109 /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */
110 memset (m32r_punct_chars, 0, sizeof (m32r_punct_chars));
111 m32r_punct_chars['#'] = 1;
112 m32r_punct_chars['@'] = 1; /* ??? no longer used */
114 /* Provide default value if not specified. */
116 g_switch_value = SDATA_DEFAULT_SIZE;
118 if (strcmp (m32r_model_string, "small") == 0)
119 m32r_model = M32R_MODEL_SMALL;
120 else if (strcmp (m32r_model_string, "medium") == 0)
121 m32r_model = M32R_MODEL_MEDIUM;
122 else if (strcmp (m32r_model_string, "large") == 0)
123 m32r_model = M32R_MODEL_LARGE;
125 error ("bad value (%s) for -mmodel switch", m32r_model_string);
127 if (strcmp (m32r_sdata_string, "none") == 0)
128 m32r_sdata = M32R_SDATA_NONE;
129 else if (strcmp (m32r_sdata_string, "sdata") == 0)
130 m32r_sdata = M32R_SDATA_SDATA;
131 else if (strcmp (m32r_sdata_string, "use") == 0)
132 m32r_sdata = M32R_SDATA_USE;
134 error ("bad value (%s) for -msdata switch", m32r_sdata_string);
137 /* Vectors to keep interesting information about registers where it can easily
138 be got. We use to use the actual mode value as the bit number, but there
139 is (or may be) more than 32 modes now. Instead we use two tables: one
140 indexed by hard register number, and one indexed by mode. */
142 /* The purpose of m32r_mode_class is to shrink the range of modes so that
143 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
144 mapped into one m32r_mode_class mode. */
149 S_MODE, D_MODE, T_MODE, O_MODE,
150 SF_MODE, DF_MODE, TF_MODE, OF_MODE, A_MODE
153 /* Modes for condition codes. */
154 #define C_MODES (1 << (int) C_MODE)
156 /* Modes for single-word and smaller quantities. */
157 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
159 /* Modes for double-word and smaller quantities. */
160 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
162 /* Modes for quad-word and smaller quantities. */
163 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
165 /* Modes for accumulators. */
166 #define A_MODES (1 << (int) A_MODE)
168 /* Value is 1 if register/mode pair is acceptable on arc. */
170 unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
172 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
173 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
174 S_MODES, C_MODES, A_MODES, A_MODES
177 unsigned int m32r_mode_class [NUM_MACHINE_MODES];
179 enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
186 for (i = 0; i < NUM_MACHINE_MODES; i++)
188 switch (GET_MODE_CLASS (i))
191 case MODE_PARTIAL_INT:
192 case MODE_COMPLEX_INT:
193 if (GET_MODE_SIZE (i) <= 4)
194 m32r_mode_class[i] = 1 << (int) S_MODE;
195 else if (GET_MODE_SIZE (i) == 8)
196 m32r_mode_class[i] = 1 << (int) D_MODE;
197 else if (GET_MODE_SIZE (i) == 16)
198 m32r_mode_class[i] = 1 << (int) T_MODE;
199 else if (GET_MODE_SIZE (i) == 32)
200 m32r_mode_class[i] = 1 << (int) O_MODE;
202 m32r_mode_class[i] = 0;
205 case MODE_COMPLEX_FLOAT:
206 if (GET_MODE_SIZE (i) <= 4)
207 m32r_mode_class[i] = 1 << (int) SF_MODE;
208 else if (GET_MODE_SIZE (i) == 8)
209 m32r_mode_class[i] = 1 << (int) DF_MODE;
210 else if (GET_MODE_SIZE (i) == 16)
211 m32r_mode_class[i] = 1 << (int) TF_MODE;
212 else if (GET_MODE_SIZE (i) == 32)
213 m32r_mode_class[i] = 1 << (int) OF_MODE;
215 m32r_mode_class[i] = 0;
219 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
220 we must explicitly check for them here. */
221 if (i == (int) CCmode)
222 m32r_mode_class[i] = 1 << (int) C_MODE;
224 m32r_mode_class[i] = 0;
229 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
232 m32r_regno_reg_class[i] = GENERAL_REGS;
233 else if (i == ARG_POINTER_REGNUM)
234 m32r_regno_reg_class[i] = GENERAL_REGS;
236 m32r_regno_reg_class[i] = NO_REGS;
240 /* M32R specific attribute support.
242 interrupt - for interrupt functions
244 model - select code model used to access object
246 small: addresses use 24 bits, use bl to make calls
247 medium: addresses use 32 bits, use bl to make calls
248 large: addresses use 32 bits, use seth/add3/jl to make calls
250 Grep for MODEL in m32r.h for more info.
253 static tree small_ident1;
254 static tree small_ident2;
255 static tree medium_ident1;
256 static tree medium_ident2;
257 static tree large_ident1;
258 static tree large_ident2;
261 init_idents PARAMS ((void))
263 if (small_ident1 == 0)
265 small_ident1 = get_identifier ("small");
266 small_ident2 = get_identifier ("__small__");
267 medium_ident1 = get_identifier ("medium");
268 medium_ident2 = get_identifier ("__medium__");
269 large_ident1 = get_identifier ("large");
270 large_ident2 = get_identifier ("__large__");
274 const struct attribute_spec m32r_attribute_table[] =
276 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
277 { "interrupt", 0, 0, true, false, false, NULL },
278 { "model", 1, 1, true, false, false, m32r_handle_model_attribute },
279 { NULL, 0, 0, false, false, false, NULL }
283 /* Handle an "model" attribute; arguments as in
284 struct attribute_spec.handler. */
286 m32r_handle_model_attribute (node, name, args, flags, no_add_attrs)
287 tree *node ATTRIBUTE_UNUSED;
290 int flags ATTRIBUTE_UNUSED;
296 arg = TREE_VALUE (args);
298 if (arg != small_ident1
299 && arg != small_ident2
300 && arg != medium_ident1
301 && arg != medium_ident2
302 && arg != large_ident1
303 && arg != large_ident2)
305 warning ("invalid argument of `%s' attribute",
306 IDENTIFIER_POINTER (name));
307 *no_add_attrs = true;
313 /* A C statement or statements to switch to the appropriate
314 section for output of DECL. DECL is either a `VAR_DECL' node
315 or a constant of some sort. RELOC indicates whether forming
316 the initial value of DECL requires link-time relocations. */
319 m32r_select_section (decl, reloc)
323 if (TREE_CODE (decl) == STRING_CST)
325 if (! flag_writable_strings)
330 else if (TREE_CODE (decl) == VAR_DECL)
332 if (SDATA_NAME_P (XSTR (XEXP (DECL_RTL (decl), 0), 0)))
334 else if ((flag_pic && reloc)
335 || !TREE_READONLY (decl)
336 || TREE_SIDE_EFFECTS (decl)
337 || !DECL_INITIAL (decl)
338 || (DECL_INITIAL (decl) != error_mark_node
339 && !TREE_CONSTANT (DECL_INITIAL (decl))))
348 /* Encode section information of DECL, which is either a VAR_DECL,
349 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
351 For the M32R we want to record:
353 - whether the object lives in .sdata/.sbss.
354 objects living in .sdata/.sbss are prefixed with SDATA_FLAG_CHAR
356 - what code model should be used to access the object
357 small: recorded with no flag - for space efficiency since they'll
359 medium: prefixed with MEDIUM_FLAG_CHAR
360 large: prefixed with LARGE_FLAG_CHAR
364 m32r_encode_section_info (decl)
370 switch (TREE_CODE (decl))
374 model = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
378 /* ??? document all others that can appear here */
383 /* Only mark the object as being small data area addressable if
384 it hasn't been explicitly marked with a code model.
386 The user can explicitly put an object in the small data area with the
387 section attribute. If the object is in sdata/sbss and marked with a
388 code model do both [put the object in .sdata and mark it as being
389 addressed with a specific code model - don't mark it as being addressed
390 with an SDA reloc though]. This is ok and might be useful at times. If
391 the object doesn't fit the linker will give an error. */
395 if (TREE_CODE_CLASS (TREE_CODE (decl)) == 'd'
396 && DECL_SECTION_NAME (decl) != NULL_TREE)
398 char *name = (char *) TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
399 if (! strcmp (name, ".sdata") || ! strcmp (name, ".sbss"))
401 #if 0 /* ??? There's no reason to disallow this, is there? */
402 if (TREE_READONLY (decl))
403 error_with_decl (decl, "const objects cannot go in .sdata/.sbss");
405 prefix = SDATA_FLAG_CHAR;
410 if (TREE_CODE (decl) == VAR_DECL
411 && ! TREE_READONLY (decl)
412 && ! TARGET_SDATA_NONE)
414 int size = int_size_in_bytes (TREE_TYPE (decl));
416 if (size > 0 && size <= g_switch_value)
417 prefix = SDATA_FLAG_CHAR;
422 /* If data area not decided yet, check for a code model. */
431 id = TREE_VALUE (TREE_VALUE (model));
433 if (id == small_ident1 || id == small_ident2)
434 ; /* don't mark the symbol specially */
435 else if (id == medium_ident1 || id == medium_ident2)
436 prefix = MEDIUM_FLAG_CHAR;
437 else if (id == large_ident1 || id == large_ident2)
438 prefix = LARGE_FLAG_CHAR;
440 abort (); /* shouldn't happen */
444 if (TARGET_MODEL_SMALL)
445 ; /* don't mark the symbol specially */
446 else if (TARGET_MODEL_MEDIUM)
447 prefix = MEDIUM_FLAG_CHAR;
448 else if (TARGET_MODEL_LARGE)
449 prefix = LARGE_FLAG_CHAR;
451 abort (); /* shouldn't happen */
457 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd'
458 ? TREE_CST_RTL (decl) : DECL_RTL (decl));
459 const char *str = XSTR (XEXP (rtl, 0), 0);
460 int len = strlen (str);
461 char *newstr = ggc_alloc (len + 2);
463 strcpy (newstr + 1, str);
465 /* Note - we cannot leave the string in the ggc_alloc'ed space.
466 It must reside in the stringtable's domain. */
467 newstr = (char *) ggc_alloc_string (newstr, len + 2);
469 XSTR (XEXP (rtl, 0), 0) = newstr;
473 /* Do anything needed before RTL is emitted for each function. */
476 m32r_init_expanders ()
478 /* ??? At one point there was code here. The function is left in
479 to make it easy to experiment. */
482 /* Acceptable arguments to the call insn. */
485 call_address_operand (op, mode)
487 enum machine_mode mode;
489 return symbolic_operand (op, mode);
491 /* Constants and values in registers are not OK, because
492 the m32r BL instruction can only support PC relative branching. */
496 call_operand (op, mode)
498 enum machine_mode mode;
500 if (GET_CODE (op) != MEM)
503 return call_address_operand (op, mode);
506 /* Returns 1 if OP is a symbol reference. */
509 symbolic_operand (op, mode)
511 enum machine_mode mode ATTRIBUTE_UNUSED;
513 switch (GET_CODE (op))
525 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */
528 small_data_operand (op, mode)
530 enum machine_mode mode ATTRIBUTE_UNUSED;
532 if (! TARGET_SDATA_USE)
535 if (GET_CODE (op) == SYMBOL_REF)
536 return SDATA_NAME_P (XSTR (op, 0));
538 if (GET_CODE (op) == CONST
539 && GET_CODE (XEXP (op, 0)) == PLUS
540 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
541 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
542 && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
543 return SDATA_NAME_P (XSTR (XEXP (XEXP (op, 0), 0), 0));
548 /* Return 1 if OP is a symbol that can use 24 bit addressing. */
551 addr24_operand (op, mode)
553 enum machine_mode mode ATTRIBUTE_UNUSED;
555 if (GET_CODE (op) == LABEL_REF)
556 return TARGET_ADDR24;
558 if (GET_CODE (op) == SYMBOL_REF)
559 return (SMALL_NAME_P (XSTR (op, 0))
561 && (CONSTANT_POOL_ADDRESS_P (op)
562 || LIT_NAME_P (XSTR (op, 0)))));
564 if (GET_CODE (op) == CONST
565 && GET_CODE (XEXP (op, 0)) == PLUS
566 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
567 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
568 && UINT24_P (INTVAL (XEXP (XEXP (op, 0), 1))))
570 rtx sym = XEXP (XEXP (op, 0), 0);
571 return (SMALL_NAME_P (XSTR (sym, 0))
573 && (CONSTANT_POOL_ADDRESS_P (op)
574 || LIT_NAME_P (XSTR (op, 0)))));
580 /* Return 1 if OP is a symbol that needs 32 bit addressing. */
583 addr32_operand (op, mode)
585 enum machine_mode mode;
587 if (GET_CODE (op) == LABEL_REF)
588 return TARGET_ADDR32;
590 if (GET_CODE (op) == SYMBOL_REF)
591 return (! addr24_operand (op, mode)
592 && ! small_data_operand (op, mode));
594 if (GET_CODE (op) == CONST
595 && GET_CODE (XEXP (op, 0)) == PLUS
596 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
597 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
599 return (! addr24_operand (op, mode)
600 && ! small_data_operand (op, mode));
606 /* Return 1 if OP is a function that can be called with the `bl' insn. */
609 call26_operand (op, mode)
611 enum machine_mode mode ATTRIBUTE_UNUSED;
613 if (GET_CODE (op) == SYMBOL_REF)
614 return ! LARGE_NAME_P (XSTR (op, 0));
616 return TARGET_CALL26;
619 /* Returns 1 if OP is an acceptable operand for seth/add3. */
622 seth_add3_operand (op, mode)
624 enum machine_mode mode ATTRIBUTE_UNUSED;
626 if (GET_CODE (op) == SYMBOL_REF
627 || GET_CODE (op) == LABEL_REF)
630 if (GET_CODE (op) == CONST
631 && GET_CODE (XEXP (op, 0)) == PLUS
632 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
633 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
634 && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
640 /* Return true if OP is a signed 8 bit immediate value. */
643 int8_operand (op, mode)
645 enum machine_mode mode ATTRIBUTE_UNUSED;
647 if (GET_CODE (op) != CONST_INT)
649 return INT8_P (INTVAL (op));
652 /* Return true if OP is a signed 16 bit immediate value
653 useful in comparisons. */
656 cmp_int16_operand (op, mode)
658 enum machine_mode mode ATTRIBUTE_UNUSED;
660 if (GET_CODE (op) != CONST_INT)
662 return CMP_INT16_P (INTVAL (op));
665 /* Return true if OP is an unsigned 16 bit immediate value. */
668 uint16_operand (op, mode)
670 enum machine_mode mode ATTRIBUTE_UNUSED;
672 if (GET_CODE (op) != CONST_INT)
674 return UINT16_P (INTVAL (op));
677 /* Return true if OP is a register or signed 16 bit value. */
680 reg_or_int16_operand (op, mode)
682 enum machine_mode mode;
684 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
685 return register_operand (op, mode);
686 if (GET_CODE (op) != CONST_INT)
688 return INT16_P (INTVAL (op));
691 /* Return true if OP is a register or an unsigned 16 bit value. */
694 reg_or_uint16_operand (op, mode)
696 enum machine_mode mode;
698 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
699 return register_operand (op, mode);
700 if (GET_CODE (op) != CONST_INT)
702 return UINT16_P (INTVAL (op));
705 /* Return true if OP is a register or an integer value that can be
706 used is SEQ/SNE. We can use either XOR of the value or ADD of
707 the negative of the value for the constant. Don't allow 0,
708 because that is special cased. */
711 reg_or_eq_int16_operand (op, mode)
713 enum machine_mode mode;
717 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
718 return register_operand (op, mode);
720 if (GET_CODE (op) != CONST_INT)
724 return (value != 0) && (UINT16_P (value) || CMP_INT16_P (-value));
727 /* Return true if OP is a register or signed 16 bit value for compares. */
730 reg_or_cmp_int16_operand (op, mode)
732 enum machine_mode mode;
734 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
735 return register_operand (op, mode);
736 if (GET_CODE (op) != CONST_INT)
738 return CMP_INT16_P (INTVAL (op));
741 /* Return true if OP is a register or the constant 0. */
744 reg_or_zero_operand (op, mode)
746 enum machine_mode mode;
748 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
749 return register_operand (op, mode);
751 if (GET_CODE (op) != CONST_INT)
754 return INTVAL (op) == 0;
757 /* Return true if OP is a const_int requiring two instructions to load. */
760 two_insn_const_operand (op, mode)
762 enum machine_mode mode ATTRIBUTE_UNUSED;
764 if (GET_CODE (op) != CONST_INT)
766 if (INT16_P (INTVAL (op))
767 || UINT24_P (INTVAL (op))
768 || UPPER16_P (INTVAL (op)))
773 /* Return true if OP is an acceptable argument for a single word
777 move_src_operand (op, mode)
779 enum machine_mode mode;
781 switch (GET_CODE (op))
785 return addr24_operand (op, mode);
787 /* ??? We allow more cse opportunities if we only allow constants
788 loadable with one insn, and split the rest into two. The instances
789 where this would help should be rare and the current way is
791 return UINT32_P (INTVAL (op));
793 return TARGET_ADDR24;
797 else if (mode == SImode)
799 /* Large unsigned constants are represented as const_double's. */
800 unsigned HOST_WIDE_INT low, high;
802 low = CONST_DOUBLE_LOW (op);
803 high = CONST_DOUBLE_HIGH (op);
804 return high == 0 && low <= 0xffffffff;
809 return register_operand (op, mode);
811 /* (subreg (mem ...) ...) can occur here if the inner part was once a
812 pseudo-reg and is now a stack slot. */
813 if (GET_CODE (SUBREG_REG (op)) == MEM)
814 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
816 return register_operand (op, mode);
818 if (GET_CODE (XEXP (op, 0)) == PRE_INC
819 || GET_CODE (XEXP (op, 0)) == PRE_DEC)
820 return 0; /* loads can't do pre-{inc,dec} */
821 return address_operand (XEXP (op, 0), mode);
827 /* Return true if OP is an acceptable argument for a double word
831 move_double_src_operand (op, mode)
833 enum machine_mode mode;
835 switch (GET_CODE (op))
841 return register_operand (op, mode);
843 /* (subreg (mem ...) ...) can occur here if the inner part was once a
844 pseudo-reg and is now a stack slot. */
845 if (GET_CODE (SUBREG_REG (op)) == MEM)
846 return move_double_src_operand (SUBREG_REG (op), mode);
848 return register_operand (op, mode);
850 /* Disallow auto inc/dec for now. */
851 if (GET_CODE (XEXP (op, 0)) == PRE_DEC
852 || GET_CODE (XEXP (op, 0)) == PRE_INC)
854 return address_operand (XEXP (op, 0), mode);
860 /* Return true if OP is an acceptable argument for a move destination. */
863 move_dest_operand (op, mode)
865 enum machine_mode mode;
867 switch (GET_CODE (op))
870 return register_operand (op, mode);
872 /* (subreg (mem ...) ...) can occur here if the inner part was once a
873 pseudo-reg and is now a stack slot. */
874 if (GET_CODE (SUBREG_REG (op)) == MEM)
875 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
877 return register_operand (op, mode);
879 if (GET_CODE (XEXP (op, 0)) == POST_INC)
880 return 0; /* stores can't do post inc */
881 return address_operand (XEXP (op, 0), mode);
887 /* Return 1 if OP is a DImode const we want to handle inline.
888 This must match the code in the movdi pattern.
889 It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER. */
895 rtx high_rtx, low_rtx;
896 HOST_WIDE_INT high, low;
898 split_double (op, &high_rtx, &low_rtx);
899 high = INTVAL (high_rtx);
900 low = INTVAL (low_rtx);
901 /* Pick constants loadable with 2 16 bit `ldi' insns. */
902 if (high >= -128 && high <= 127
903 && low >= -128 && low <= 127)
908 /* Return 1 if OP is a DFmode const we want to handle inline.
909 This must match the code in the movdf pattern.
910 It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER. */
919 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
920 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
921 if (l[0] == 0 && l[1] == 0)
923 if ((l[0] & 0xffff) == 0 && l[1] == 0)
928 /* Return 1 if OP is an EQ or NE comparison operator. */
931 eqne_comparison_operator (op, mode)
933 enum machine_mode mode ATTRIBUTE_UNUSED;
935 enum rtx_code code = GET_CODE (op);
937 if (GET_RTX_CLASS (code) != '<')
939 return (code == EQ || code == NE);
942 /* Return 1 if OP is a signed comparison operator. */
945 signed_comparison_operator (op, mode)
947 enum machine_mode mode ATTRIBUTE_UNUSED;
949 enum rtx_code code = GET_CODE (op);
951 if (GET_RTX_CLASS (code) != '<')
953 return (code == EQ || code == NE
954 || code == LT || code == LE || code == GT || code == GE);
957 /* Return 1 if OP is (mem (reg ...)).
958 This is used in insn length calcs. */
961 memreg_operand (op, mode)
963 enum machine_mode mode ATTRIBUTE_UNUSED;
965 return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == REG;
968 /* Return true if OP is an acceptable input argument for a zero/sign extend
972 extend_operand (op, mode)
974 enum machine_mode mode;
978 switch (GET_CODE (op))
982 return register_operand (op, mode);
986 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
987 return 0; /* loads can't do pre inc/pre dec */
989 return address_operand (addr, mode);
996 /* Return non-zero if the operand is an insn that is a small insn.
997 Allow const_int 0 as well, which is a placeholder for NOP slots. */
1000 small_insn_p (op, mode)
1002 enum machine_mode mode ATTRIBUTE_UNUSED;
1004 if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
1010 return get_attr_length (op) == 2;
1013 /* Return non-zero if the operand is an insn that is a large insn. */
1016 large_insn_p (op, mode)
1018 enum machine_mode mode ATTRIBUTE_UNUSED;
1023 return get_attr_length (op) != 2;
1029 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1030 return the mode to be used for the comparison. */
1033 m32r_select_cc_mode (op, x, y)
1034 int op ATTRIBUTE_UNUSED;
1035 rtx x ATTRIBUTE_UNUSED;
1036 rtx y ATTRIBUTE_UNUSED;
1038 return (int) CCmode;
1041 /* X and Y are two things to compare using CODE. Emit the compare insn and
1042 return the rtx for compare [arg0 of the if_then_else].
1043 If need_compare is true then the comparison insn must be generated, rather
1044 than being susummed into the following branch instruction. */
1047 gen_compare (code, x, y, need_compare)
1052 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
1053 enum rtx_code compare_code, branch_code;
1054 rtx cc_reg = gen_rtx_REG (mode, CARRY_REGNUM);
1059 case EQ: compare_code = EQ; branch_code = NE; break;
1060 case NE: compare_code = EQ; branch_code = EQ; break;
1061 case LT: compare_code = LT; branch_code = NE; break;
1062 case LE: compare_code = LT; branch_code = EQ; must_swap = 1; break;
1063 case GT: compare_code = LT; branch_code = NE; must_swap = 1; break;
1064 case GE: compare_code = LT; branch_code = EQ; break;
1065 case LTU: compare_code = LTU; branch_code = NE; break;
1066 case LEU: compare_code = LTU; branch_code = EQ; must_swap = 1; break;
1067 case GTU: compare_code = LTU; branch_code = NE; must_swap = 1; break;
1068 case GEU: compare_code = LTU; branch_code = EQ; break;
1076 switch (compare_code)
1079 if (GET_CODE (y) == CONST_INT
1080 && CMP_INT16_P (INTVAL (y)) /* reg equal to small const. */
1083 rtx tmp = gen_reg_rtx (SImode);
1085 emit_insn (gen_cmp_ne_small_const_insn (tmp, x, y));
1089 else if (CONSTANT_P (y)) /* reg equal to const. */
1091 rtx tmp = force_reg (GET_MODE (x), y);
1095 if (register_operand (y, SImode) /* reg equal to reg. */
1096 || y == const0_rtx) /* req equal to zero. */
1098 emit_insn (gen_cmp_eqsi_insn (x, y));
1100 return gen_rtx (code, mode, cc_reg, const0_rtx);
1105 if (register_operand (y, SImode)
1106 || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
1108 rtx tmp = gen_reg_rtx (SImode); /* reg compared to reg. */
1113 emit_insn (gen_cmp_ltsi_insn (x, y));
1117 if (y == const0_rtx)
1120 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1121 emit_insn (gen_cmp_ltsi_insn (x, tmp));
1125 if (GET_CODE (y) == CONST_INT)
1126 tmp = gen_rtx (PLUS, SImode, y, const1_rtx);
1128 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1129 emit_insn (gen_cmp_ltsi_insn (x, tmp));
1133 emit_insn (gen_cmp_ltsi_insn (x, y));
1140 return gen_rtx (code, mode, cc_reg, const0_rtx);
1145 if (register_operand (y, SImode)
1146 || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
1148 rtx tmp = gen_reg_rtx (SImode); /* reg (unsigned) compared to reg. */
1153 emit_insn (gen_cmp_ltusi_insn (x, y));
1157 if (y == const0_rtx)
1160 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1161 emit_insn (gen_cmp_ltusi_insn (x, tmp));
1165 if (GET_CODE (y) == CONST_INT)
1166 tmp = gen_rtx (PLUS, SImode, y, const1_rtx);
1168 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1169 emit_insn (gen_cmp_ltusi_insn (x, tmp));
1173 emit_insn (gen_cmp_ltusi_insn (x, y));
1180 return gen_rtx (code, mode, cc_reg, const0_rtx);
1190 /* reg/reg equal comparison */
1191 if (compare_code == EQ
1192 && register_operand (y, SImode))
1193 return gen_rtx (code, mode, x, y);
1195 /* reg/zero signed comparison */
1196 if ((compare_code == EQ || compare_code == LT)
1198 return gen_rtx (code, mode, x, y);
1200 /* reg/smallconst equal comparison */
1201 if (compare_code == EQ
1202 && GET_CODE (y) == CONST_INT
1203 && CMP_INT16_P (INTVAL (y)))
1205 rtx tmp = gen_reg_rtx (SImode);
1206 emit_insn (gen_cmp_ne_small_const_insn (tmp, x, y));
1207 return gen_rtx (code, mode, tmp, const0_rtx);
1210 /* reg/const equal comparison */
1211 if (compare_code == EQ
1214 rtx tmp = force_reg (GET_MODE (x), y);
1215 return gen_rtx (code, mode, x, tmp);
1222 y = force_reg (GET_MODE (x), y);
1226 (code == LTU || code == LEU || code == GTU || code == GEU)
1227 ? uint16_operand (y, GET_MODE (y))
1228 : reg_or_cmp_int16_operand (y, GET_MODE (y));
1231 y = force_reg (GET_MODE (x), y);
1235 switch (compare_code)
1238 emit_insn (gen_cmp_eqsi_insn (must_swap ? y : x, must_swap ? x : y));
1241 emit_insn (gen_cmp_ltsi_insn (must_swap ? y : x, must_swap ? x : y));
1244 emit_insn (gen_cmp_ltusi_insn (must_swap ? y : x, must_swap ? x : y));
1251 return gen_rtx (branch_code, VOIDmode, cc_reg, CONST0_RTX (mode));
1254 /* Split a 2 word move (DI or DF) into component parts. */
1257 gen_split_move_double (operands)
1260 enum machine_mode mode = GET_MODE (operands[0]);
1261 rtx dest = operands[0];
1262 rtx src = operands[1];
1265 /* We might have (SUBREG (MEM)) here, so just get rid of the
1266 subregs to make this code simpler. It is safe to call
1267 alter_subreg any time after reload. */
1268 if (GET_CODE (dest) == SUBREG)
1269 dest = alter_subreg (dest);
1270 if (GET_CODE (src) == SUBREG)
1271 src = alter_subreg (src);
1274 if (GET_CODE (dest) == REG)
1276 int dregno = REGNO (dest);
1279 if (GET_CODE (src) == REG)
1281 int sregno = REGNO (src);
1283 int reverse = (dregno == sregno + 1);
1285 /* We normally copy the low-numbered register first. However, if
1286 the first register operand 0 is the same as the second register of
1287 operand 1, we must copy in the opposite order. */
1288 emit_insn (gen_rtx_SET (VOIDmode,
1289 operand_subword (dest, reverse, TRUE, mode),
1290 operand_subword (src, reverse, TRUE, mode)));
1292 emit_insn (gen_rtx_SET (VOIDmode,
1293 operand_subword (dest, !reverse, TRUE, mode),
1294 operand_subword (src, !reverse, TRUE, mode)));
1297 /* reg = constant */
1298 else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE)
1301 split_double (src, &words[0], &words[1]);
1302 emit_insn (gen_rtx_SET (VOIDmode,
1303 operand_subword (dest, 0, TRUE, mode),
1306 emit_insn (gen_rtx_SET (VOIDmode,
1307 operand_subword (dest, 1, TRUE, mode),
1312 else if (GET_CODE (src) == MEM)
1314 /* If the high-address word is used in the address, we must load it
1315 last. Otherwise, load it first. */
1317 = (refers_to_regno_p (dregno, dregno + 1, XEXP (src, 0), 0) != 0);
1319 /* We used to optimize loads from single registers as
1323 if r3 were not used subsequently. However, the REG_NOTES aren't
1324 propigated correctly by the reload phase, and it can cause bad
1325 code to be generated. We could still try:
1327 ld r1,r3+; ld r2,r3; addi r3,-4
1329 which saves 2 bytes and doesn't force longword alignment. */
1330 emit_insn (gen_rtx_SET (VOIDmode,
1331 operand_subword (dest, reverse, TRUE, mode),
1332 adjust_address (src, SImode,
1333 reverse * UNITS_PER_WORD)));
1335 emit_insn (gen_rtx_SET (VOIDmode,
1336 operand_subword (dest, !reverse, TRUE, mode),
1337 adjust_address (src, SImode,
1338 !reverse * UNITS_PER_WORD)));
1346 /* We used to optimize loads from single registers as
1350 if r3 were not used subsequently. However, the REG_NOTES aren't
1351 propigated correctly by the reload phase, and it can cause bad
1352 code to be generated. We could still try:
1354 st r1,r3; st r2,+r3; addi r3,-4
1356 which saves 2 bytes and doesn't force longword alignment. */
1357 else if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
1359 emit_insn (gen_rtx_SET (VOIDmode,
1360 adjust_address (dest, SImode, 0),
1361 operand_subword (src, 0, TRUE, mode)));
1363 emit_insn (gen_rtx_SET (VOIDmode,
1364 adjust_address (dest, SImode, UNITS_PER_WORD),
1365 operand_subword (src, 1, TRUE, mode)));
1371 val = gen_sequence ();
1377 /* Implements the FUNCTION_ARG_PARTIAL_NREGS macro. */
1380 function_arg_partial_nregs (cum, mode, type, named)
1381 CUMULATIVE_ARGS *cum;
1382 enum machine_mode mode;
1384 int named ATTRIBUTE_UNUSED;
1388 (((mode == BLKmode && type)
1389 ? (unsigned int) int_size_in_bytes (type)
1390 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
1393 if (*cum >= M32R_MAX_PARM_REGS)
1395 else if (*cum + size > M32R_MAX_PARM_REGS)
1396 ret = (*cum + size) - M32R_MAX_PARM_REGS;
1403 /* Do any needed setup for a variadic function. For the M32R, we must
1404 create a register parameter block, and then copy any anonymous arguments
1405 in registers to memory.
1407 CUM has not been updated for the last named argument which has type TYPE
1408 and mode MODE, and we rely on this fact. */
1411 m32r_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
1412 CUMULATIVE_ARGS *cum;
1413 enum machine_mode mode;
1423 /* All BLKmode values are passed by reference. */
1424 if (mode == BLKmode)
1427 /* We must treat `__builtin_va_alist' as an anonymous arg. */
1428 if (current_function_varargs)
1429 first_anon_arg = *cum;
1431 first_anon_arg = (ROUND_ADVANCE_CUM (*cum, mode, type)
1432 + ROUND_ADVANCE_ARG (mode, type));
1434 if (first_anon_arg < M32R_MAX_PARM_REGS)
1436 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1437 int first_reg_offset = first_anon_arg;
1438 /* Size in words to "pretend" allocate. */
1439 int size = M32R_MAX_PARM_REGS - first_reg_offset;
1442 regblock = gen_rtx_MEM (BLKmode,
1443 plus_constant (arg_pointer_rtx,
1444 FIRST_PARM_OFFSET (0)));
1445 set_mem_alias_set (regblock, get_varargs_alias_set ());
1446 move_block_from_reg (first_reg_offset, regblock,
1447 size, size * UNITS_PER_WORD);
1449 *pretend_size = (size * UNITS_PER_WORD);
1454 /* Implement `va_arg'. */
1457 m32r_va_arg (valist, type)
1460 HOST_WIDE_INT size, rsize;
1464 size = int_size_in_bytes (type);
1465 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
1469 tree type_ptr, type_ptr_ptr;
1471 /* Pass by reference. */
1473 type_ptr = build_pointer_type (type);
1474 type_ptr_ptr = build_pointer_type (type_ptr);
1476 t = build (POSTINCREMENT_EXPR, va_list_type_node, valist,
1477 build_int_2 (UNITS_PER_WORD, 0));
1478 TREE_SIDE_EFFECTS (t) = 1;
1479 t = build1 (NOP_EXPR, type_ptr_ptr, t);
1480 TREE_SIDE_EFFECTS (t) = 1;
1481 t = build1 (INDIRECT_REF, type_ptr, t);
1483 addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1487 /* Pass by value. */
1489 if (size < UNITS_PER_WORD)
1491 /* Care for bigendian correction on the aligned address. */
1492 t = build (PLUS_EXPR, ptr_type_node, valist,
1493 build_int_2 (rsize - size, 0));
1494 addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1495 addr_rtx = copy_to_reg (addr_rtx);
1498 t = build (PLUS_EXPR, va_list_type_node, valist,
1499 build_int_2 (rsize, 0));
1500 t = build (MODIFY_EXPR, va_list_type_node, valist, t);
1501 TREE_SIDE_EFFECTS (t) = 1;
1502 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
1506 t = build (POSTINCREMENT_EXPR, va_list_type_node, valist,
1507 build_int_2 (rsize, 0));
1508 TREE_SIDE_EFFECTS (t) = 1;
1509 addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1517 m32r_adjust_cost (insn, link, dep_insn, cost)
1518 rtx insn ATTRIBUTE_UNUSED;
1519 rtx link ATTRIBUTE_UNUSED;
1520 rtx dep_insn ATTRIBUTE_UNUSED;
1527 /* Return true if INSN is real instruction bearing insn. */
1533 return (INSN_P (insn)
1534 && GET_CODE (PATTERN (insn)) != USE
1535 && GET_CODE (PATTERN (insn)) != CLOBBER
1536 && GET_CODE (PATTERN (insn)) != ADDR_VEC);
1539 /* Increase the priority of long instructions so that the
1540 short instructions are scheduled ahead of the long ones. */
1543 m32r_adjust_priority (insn, priority)
1547 if (m32r_is_insn (insn)
1548 && get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1555 /* Initialize for scheduling a group of instructions. */
1558 m32r_sched_init (stream, verbose, max_ready)
1559 FILE * stream ATTRIBUTE_UNUSED;
1560 int verbose ATTRIBUTE_UNUSED;
1561 int max_ready ATTRIBUTE_UNUSED;
1563 m32r_sched_odd_word_p = FALSE;
1567 /* Reorder the schedulers priority list if needed */
1570 m32r_sched_reorder (stream, verbose, ready, n_readyp, clock)
1575 int clock ATTRIBUTE_UNUSED;
1577 int n_ready = *n_readyp;
1580 return m32r_issue_rate ();
1587 ";;\t\t::: Looking at %d insn(s) on ready list, boundary is %s word\n",
1589 (m32r_sched_odd_word_p) ? "odd" : "even");
1593 rtx * long_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1594 rtx * long_tail = long_head;
1595 rtx * short_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1596 rtx * short_tail = short_head;
1597 rtx * new_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1598 rtx * new_tail = new_head + (n_ready - 1);
1601 /* Loop through the instructions, classifing them as short/long. Try
1602 to keep 2 short together and/or 1 long. Note, the ready list is
1603 actually ordered backwards, so keep it in that manner. */
1604 for (i = n_ready-1; i >= 0; i--)
1606 rtx insn = ready[i];
1608 if (! m32r_is_insn (insn))
1610 /* Dump all current short/long insns just in case. */
1611 while (long_head != long_tail)
1612 *new_tail-- = *long_head++;
1614 while (short_head != short_tail)
1615 *new_tail-- = *short_head++;
1620 ";;\t\t::: Skipping non instruction %d\n",
1627 if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1628 *long_tail++ = insn;
1631 *short_tail++ = insn;
1635 /* If we are on an odd word, emit a single short instruction if
1637 if (m32r_sched_odd_word_p && short_head != short_tail)
1638 *new_tail-- = *short_head++;
1640 /* Now dump out all of the long instructions */
1641 while (long_head != long_tail)
1642 *new_tail-- = *long_head++;
1644 /* Now dump out all of the short instructions */
1645 while (short_head != short_tail)
1646 *new_tail-- = *short_head++;
1648 if (new_tail+1 != new_head)
1651 memcpy (ready, new_head, sizeof (rtx) * n_ready);
1655 fprintf (stream, ";;\t\t::: New ready list: ");
1656 for (i = 0; i < n_ready; i++)
1658 rtx insn = ready[i];
1660 fprintf (stream, " %d", INSN_UID (ready[i]));
1662 if (! m32r_is_insn (insn))
1663 fputs ("(?)", stream);
1665 else if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1666 fputs ("(l)", stream);
1669 fputs ("(s)", stream);
1672 fprintf (stream, "\n");
1675 return m32r_issue_rate ();
1678 /* Indicate how many instructions can be issued at the same time.
1679 This is sort of a lie. The m32r can issue only 1 long insn at
1680 once, but it can issue 2 short insns. The default therefore is
1681 set at 2, but this can be overridden by the command line option
1686 return ((TARGET_LOW_ISSUE_RATE) ? 1 : 2);
1689 /* If we have a machine that can issue a variable # of instructions
1690 per cycle, indicate how many more instructions can be issued
1691 after the current one. */
1693 m32r_variable_issue (stream, verbose, insn, how_many)
1699 int orig_odd_word_p = m32r_sched_odd_word_p;
1700 int short_p = FALSE;
1703 if (how_many > 0 && !TARGET_DEBUG)
1705 if (! m32r_is_insn (insn))
1708 else if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1711 m32r_sched_odd_word_p = 0;
1715 m32r_sched_odd_word_p = !m32r_sched_odd_word_p;
1720 if (verbose > 7 && stream)
1722 ";;\t\t::: %s insn %d starts on an %s word, can emit %d more instruction(s)\n",
1723 short_p ? "short" : "long",
1725 orig_odd_word_p ? "odd" : "even",
1731 /* Cost functions. */
1733 /* Provide the costs of an addressing mode that contains ADDR.
1734 If ADDR is not a valid address, its cost is irrelevant.
1736 This function is trivial at the moment. This code doesn't live
1737 in m32r.h so it's easy to experiment. */
1740 m32r_address_cost (addr)
1741 rtx addr ATTRIBUTE_UNUSED;
1746 /* Type of function DECL.
1748 The result is cached. To reset the cache at the end of a function,
1749 call with DECL = NULL_TREE. */
1751 enum m32r_function_type
1752 m32r_compute_function_type (decl)
1756 static enum m32r_function_type fn_type = M32R_FUNCTION_UNKNOWN;
1757 /* Last function we were called for. */
1758 static tree last_fn = NULL_TREE;
1760 /* Resetting the cached value? */
1761 if (decl == NULL_TREE)
1763 fn_type = M32R_FUNCTION_UNKNOWN;
1764 last_fn = NULL_TREE;
1768 if (decl == last_fn && fn_type != M32R_FUNCTION_UNKNOWN)
1771 /* Compute function type. */
1772 fn_type = (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE
1773 ? M32R_FUNCTION_INTERRUPT
1774 : M32R_FUNCTION_NORMAL);
1779 \f/* Function prologue/epilogue handlers. */
1781 /* M32R stack frames look like:
1783 Before call After call
1784 +-----------------------+ +-----------------------+
1786 high | local variables, | | local variables, |
1787 mem | reg save area, etc. | | reg save area, etc. |
1789 +-----------------------+ +-----------------------+
1791 | arguments on stack. | | arguments on stack. |
1793 SP+0->+-----------------------+ +-----------------------+
1794 | reg parm save area, |
1795 | only created for |
1796 | variable argument |
1798 +-----------------------+
1799 | previous frame ptr |
1800 +-----------------------+
1802 | register save area |
1804 +-----------------------+
1806 +-----------------------+
1810 +-----------------------+
1812 | alloca allocations |
1814 +-----------------------+
1816 low | arguments on stack |
1818 SP+0->+-----------------------+
1821 1) The "reg parm save area" does not exist for non variable argument fns.
1822 2) The "reg parm save area" can be eliminated completely if we saved regs
1823 containing anonymous args separately but that complicates things too
1824 much (so it's not done).
1825 3) The return address is saved after the register save area so as to have as
1826 many insns as possible between the restoration of `lr' and the `jmp lr'.
1829 /* Structure to be filled in by m32r_compute_frame_size with register
1830 save masks, and offsets for the current function. */
1831 struct m32r_frame_info
1833 unsigned int total_size; /* # bytes that the entire frame takes up */
1834 unsigned int extra_size; /* # bytes of extra stuff */
1835 unsigned int pretend_size; /* # bytes we push and pretend caller did */
1836 unsigned int args_size; /* # bytes that outgoing arguments take up */
1837 unsigned int reg_size; /* # bytes needed to store regs */
1838 unsigned int var_size; /* # bytes that variables take up */
1839 unsigned int gmask; /* mask of saved gp registers */
1840 unsigned int save_fp; /* nonzero if fp must be saved */
1841 unsigned int save_lr; /* nonzero if lr (return addr) must be saved */
1842 int initialized; /* nonzero if frame size already calculated */
1845 /* Current frame information calculated by m32r_compute_frame_size. */
1846 static struct m32r_frame_info current_frame_info;
1848 /* Zero structure to initialize current_frame_info. */
1849 static struct m32r_frame_info zero_frame_info;
1851 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1852 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1854 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1855 The return address and frame pointer are treated separately.
1856 Don't consider them here. */
1857 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1858 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1859 && (regs_ever_live[regno] && (!call_used_regs[regno] || interrupt_p)))
1861 #define MUST_SAVE_FRAME_POINTER (regs_ever_live[FRAME_POINTER_REGNUM])
1862 #define MUST_SAVE_RETURN_ADDR (regs_ever_live[RETURN_ADDR_REGNUM] || profile_flag)
1864 #define SHORT_INSN_SIZE 2 /* size of small instructions */
1865 #define LONG_INSN_SIZE 4 /* size of long instructions */
1867 /* Return the bytes needed to compute the frame pointer from the current
1870 SIZE is the size needed for local variables. */
1873 m32r_compute_frame_size (size)
1874 int size; /* # of var. bytes allocated. */
1877 unsigned int total_size, var_size, args_size, pretend_size, extra_size;
1878 unsigned int reg_size, frame_size;
1880 enum m32r_function_type fn_type;
1883 var_size = M32R_STACK_ALIGN (size);
1884 args_size = M32R_STACK_ALIGN (current_function_outgoing_args_size);
1885 pretend_size = current_function_pretend_args_size;
1886 extra_size = FIRST_PARM_OFFSET (0);
1887 total_size = extra_size + pretend_size + args_size + var_size;
1891 /* See if this is an interrupt handler. Call used registers must be saved
1893 fn_type = m32r_compute_function_type (current_function_decl);
1894 interrupt_p = M32R_INTERRUPT_P (fn_type);
1896 /* Calculate space needed for registers. */
1898 for (regno = 0; regno < M32R_MAX_INT_REGS; regno++)
1900 if (MUST_SAVE_REGISTER (regno, interrupt_p))
1902 reg_size += UNITS_PER_WORD;
1903 gmask |= 1 << regno;
1907 current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER;
1908 current_frame_info.save_lr = MUST_SAVE_RETURN_ADDR;
1910 reg_size += ((current_frame_info.save_fp + current_frame_info.save_lr)
1912 total_size += reg_size;
1914 /* ??? Not sure this is necessary, and I don't think the epilogue
1915 handler will do the right thing if this changes total_size. */
1916 total_size = M32R_STACK_ALIGN (total_size);
1918 frame_size = total_size - (pretend_size + reg_size);
1920 /* Save computed information. */
1921 current_frame_info.total_size = total_size;
1922 current_frame_info.extra_size = extra_size;
1923 current_frame_info.pretend_size = pretend_size;
1924 current_frame_info.var_size = var_size;
1925 current_frame_info.args_size = args_size;
1926 current_frame_info.reg_size = reg_size;
1927 current_frame_info.gmask = gmask;
1928 current_frame_info.initialized = reload_completed;
1930 /* Ok, we're done. */
1934 /* When the `length' insn attribute is used, this macro specifies the
1935 value to be assigned to the address of the first insn in a
1936 function. If not specified, 0 is used. */
1939 m32r_first_insn_address ()
1941 if (! current_frame_info.initialized)
1942 m32r_compute_frame_size (get_frame_size ());
1947 /* Expand the m32r prologue as a series of insns. */
1950 m32r_expand_prologue ()
1956 if (! current_frame_info.initialized)
1957 m32r_compute_frame_size (get_frame_size ());
1959 gmask = current_frame_info.gmask;
1961 /* These cases shouldn't happen. Catch them now. */
1962 if (current_frame_info.total_size == 0 && gmask)
1965 /* Allocate space for register arguments if this is a variadic function. */
1966 if (current_frame_info.pretend_size != 0)
1968 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1969 the wrong result on a 64-bit host. */
1970 HOST_WIDE_INT pretend_size = current_frame_info.pretend_size;
1971 emit_insn (gen_addsi3 (stack_pointer_rtx,
1973 GEN_INT (-pretend_size)));
1976 /* Save any registers we need to and set up fp. */
1978 if (current_frame_info.save_fp)
1979 emit_insn (gen_movsi_push (stack_pointer_rtx, frame_pointer_rtx));
1981 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1983 /* Save any needed call-saved regs (and call-used if this is an
1984 interrupt handler). */
1985 for (regno = 0; regno <= M32R_MAX_INT_REGS; ++regno)
1987 if ((gmask & (1 << regno)) != 0)
1988 emit_insn (gen_movsi_push (stack_pointer_rtx,
1989 gen_rtx_REG (Pmode, regno)));
1992 if (current_frame_info.save_lr)
1993 emit_insn (gen_movsi_push (stack_pointer_rtx,
1994 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
1996 /* Allocate the stack frame. */
1997 frame_size = (current_frame_info.total_size
1998 - (current_frame_info.pretend_size
1999 + current_frame_info.reg_size));
2001 if (frame_size == 0)
2002 ; /* nothing to do */
2003 else if (frame_size <= 32768)
2004 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
2005 GEN_INT (-frame_size)));
2008 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
2009 emit_insn (gen_movsi (tmp, GEN_INT (frame_size)));
2010 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
2013 if (frame_pointer_needed)
2014 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
2017 emit_insn (gen_blockage ());
2021 /* Set up the stack and frame pointer (if desired) for the function.
2022 Note, if this is changed, you need to mirror the changes in
2023 m32r_compute_frame_size which calculates the prolog size. */
2026 m32r_output_function_prologue (file, size)
2030 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
2032 /* If this is an interrupt handler, mark it as such. */
2033 if (M32R_INTERRUPT_P (fn_type))
2035 fprintf (file, "\t%s interrupt handler\n",
2039 if (! current_frame_info.initialized)
2040 m32r_compute_frame_size (size);
2042 /* This is only for the human reader. */
2044 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
2046 current_frame_info.var_size,
2047 current_frame_info.reg_size / 4,
2048 current_frame_info.args_size,
2049 current_frame_info.extra_size);
2052 /* Do any necessary cleanup after a function to restore stack, frame,
2056 m32r_output_function_epilogue (file, size)
2058 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
2061 int noepilogue = FALSE;
2063 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
2065 /* This is only for the human reader. */
2066 fprintf (file, "\t%s EPILOGUE\n", ASM_COMMENT_START);
2068 if (!current_frame_info.initialized)
2070 total_size = current_frame_info.total_size;
2072 if (total_size == 0)
2074 rtx insn = get_last_insn ();
2076 /* If the last insn was a BARRIER, we don't have to write any code
2077 because a jump (aka return) was put there. */
2078 if (GET_CODE (insn) == NOTE)
2079 insn = prev_nonnote_insn (insn);
2080 if (insn && GET_CODE (insn) == BARRIER)
2086 unsigned int var_size = current_frame_info.var_size;
2087 unsigned int args_size = current_frame_info.args_size;
2088 unsigned int gmask = current_frame_info.gmask;
2089 int can_trust_sp_p = !current_function_calls_alloca;
2090 const char * sp_str = reg_names[STACK_POINTER_REGNUM];
2091 const char * fp_str = reg_names[FRAME_POINTER_REGNUM];
2093 /* The first thing to do is point the sp at the bottom of the register
2097 unsigned int reg_offset = var_size + args_size;
2098 if (reg_offset == 0)
2099 ; /* nothing to do */
2100 else if (reg_offset < 128)
2101 fprintf (file, "\taddi %s,%s%d\n",
2102 sp_str, IMMEDIATE_PREFIX, reg_offset);
2103 else if (reg_offset < 32768)
2104 fprintf (file, "\tadd3 %s,%s,%s%d\n",
2105 sp_str, sp_str, IMMEDIATE_PREFIX, reg_offset);
2107 fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
2108 reg_names[PROLOGUE_TMP_REGNUM],
2109 IMMEDIATE_PREFIX, reg_offset,
2110 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
2112 else if (frame_pointer_needed)
2114 unsigned int reg_offset = var_size + args_size;
2115 if (reg_offset == 0)
2116 fprintf (file, "\tmv %s,%s\n", sp_str, fp_str);
2117 else if (reg_offset < 32768)
2118 fprintf (file, "\tadd3 %s,%s,%s%d\n",
2119 sp_str, fp_str, IMMEDIATE_PREFIX, reg_offset);
2121 fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
2122 reg_names[PROLOGUE_TMP_REGNUM],
2123 IMMEDIATE_PREFIX, reg_offset,
2124 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
2129 if (current_frame_info.save_lr)
2130 fprintf (file, "\tpop %s\n", reg_names[RETURN_ADDR_REGNUM]);
2132 /* Restore any saved registers, in reverse order of course. */
2133 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
2134 for (regno = M32R_MAX_INT_REGS - 1; regno >= 0; --regno)
2136 if ((gmask & (1L << regno)) != 0)
2137 fprintf (file, "\tpop %s\n", reg_names[regno]);
2140 if (current_frame_info.save_fp)
2141 fprintf (file, "\tpop %s\n", fp_str);
2143 /* Remove varargs area if present. */
2144 if (current_frame_info.pretend_size != 0)
2145 fprintf (file, "\taddi %s,%s%d\n",
2146 sp_str, IMMEDIATE_PREFIX, current_frame_info.pretend_size);
2148 /* Emit the return instruction. */
2149 if (M32R_INTERRUPT_P (fn_type))
2150 fprintf (file, "\trte\n");
2152 fprintf (file, "\tjmp %s\n", reg_names[RETURN_ADDR_REGNUM]);
2155 #if 0 /* no longer needed */
2156 /* Ensure the function cleanly ends on a 32 bit boundary. */
2157 fprintf (file, "\t.fillinsn\n");
2160 /* Reset state info for each function. */
2161 current_frame_info = zero_frame_info;
2162 m32r_compute_function_type (NULL_TREE);
2165 /* Return non-zero if this function is known to have a null or 1 instruction
2171 if (!reload_completed)
2174 if (! current_frame_info.initialized)
2175 m32r_compute_frame_size (get_frame_size ());
2177 return current_frame_info.total_size == 0;
2183 /* Emit special PIC prologues and epilogues. */
2186 m32r_finalize_pic ()
2191 /* Nested function support. */
2193 /* Emit RTL insns to initialize the variable parts of a trampoline.
2194 FNADDR is an RTX for the address of the function's pure code.
2195 CXT is an RTX for the static chain value for the function. */
2198 m32r_initialize_trampoline (tramp, fnaddr, cxt)
2199 rtx tramp ATTRIBUTE_UNUSED;
2200 rtx fnaddr ATTRIBUTE_UNUSED;
2201 rtx cxt ATTRIBUTE_UNUSED;
2205 /* Set the cpu type and print out other fancy things,
2206 at the top of the file. */
2209 m32r_asm_file_start (file)
2212 if (flag_verbose_asm)
2213 fprintf (file, "%s M32R/D special options: -G %d\n",
2214 ASM_COMMENT_START, g_switch_value);
2217 /* Print operand X (an rtx) in assembler syntax to file FILE.
2218 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2219 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2222 m32r_print_operand (file, x, code)
2231 /* The 's' and 'p' codes are used by output_block_move() to
2232 indicate post-increment 's'tores and 'p're-increment loads. */
2234 if (GET_CODE (x) == REG)
2235 fprintf (file, "@+%s", reg_names [REGNO (x)]);
2237 output_operand_lossage ("invalid operand to %s code");
2241 if (GET_CODE (x) == REG)
2242 fprintf (file, "@%s+", reg_names [REGNO (x)]);
2244 output_operand_lossage ("invalid operand to %p code");
2248 /* Write second word of DImode or DFmode reference,
2249 register or memory. */
2250 if (GET_CODE (x) == REG)
2251 fputs (reg_names[REGNO (x)+1], file);
2252 else if (GET_CODE (x) == MEM)
2254 fprintf (file, "@(");
2255 /* Handle possible auto-increment. Since it is pre-increment and
2256 we have already done it, we can just use an offset of four. */
2257 /* ??? This is taken from rs6000.c I think. I don't think it is
2258 currently necessary, but keep it around. */
2259 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2260 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2261 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
2263 output_address (plus_constant (XEXP (x, 0), 4));
2267 output_operand_lossage ("invalid operand to %R code");
2270 case 'H' : /* High word */
2271 case 'L' : /* Low word */
2272 if (GET_CODE (x) == REG)
2274 /* L = least significant word, H = most significant word */
2275 if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L'))
2276 fputs (reg_names[REGNO (x)], file);
2278 fputs (reg_names[REGNO (x)+1], file);
2280 else if (GET_CODE (x) == CONST_INT
2281 || GET_CODE (x) == CONST_DOUBLE)
2285 split_double (x, &first, &second);
2286 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2287 code == 'L' ? INTVAL (first) : INTVAL (second));
2290 output_operand_lossage ("invalid operand to %H/%L code");
2298 if (GET_CODE (x) != CONST_DOUBLE
2299 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
2300 fatal_insn ("bad insn for 'A'", x);
2301 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
2302 REAL_VALUE_TO_DECIMAL (d, "%.20e", str);
2303 fprintf (file, "%s", str);
2307 case 'B' : /* Bottom half */
2308 case 'T' : /* Top half */
2309 /* Output the argument to a `seth' insn (sets the Top half-word).
2310 For constants output arguments to a seth/or3 pair to set Top and
2311 Bottom halves. For symbols output arguments to a seth/add3 pair to
2312 set Top and Bottom halves. The difference exists because for
2313 constants seth/or3 is more readable but for symbols we need to use
2314 the same scheme as `ld' and `st' insns (16 bit addend is signed). */
2315 switch (GET_CODE (x))
2322 split_double (x, &first, &second);
2323 x = WORDS_BIG_ENDIAN ? second : first;
2325 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
2331 ? INTVAL (x) & 0xffff
2332 : (INTVAL (x) >> 16) & 0xffff));
2338 && small_data_operand (x, VOIDmode))
2340 fputs ("sda(", file);
2341 output_addr_const (file, x);
2347 fputs (code == 'T' ? "shigh(" : "low(", file);
2348 output_addr_const (file, x);
2352 output_operand_lossage ("invalid operand to %T/%B code");
2359 /* Output a load/store with update indicator if appropriate. */
2360 if (GET_CODE (x) == MEM)
2362 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2363 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2367 output_operand_lossage ("invalid operand to %U code");
2371 /* Print a constant value negated. */
2372 if (GET_CODE (x) == CONST_INT)
2373 output_addr_const (file, GEN_INT (- INTVAL (x)));
2375 output_operand_lossage ("invalid operand to %N code");
2379 /* Print a const_int in hex. Used in comments. */
2380 if (GET_CODE (x) == CONST_INT)
2382 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
2391 fputs (IMMEDIATE_PREFIX, file);
2394 #if 0 /* ??? no longer used */
2396 fputs (reg_names[SDA_REGNUM], file);
2401 /* Do nothing special. */
2406 output_operand_lossage ("invalid operand output code");
2409 switch (GET_CODE (x))
2412 fputs (reg_names[REGNO (x)], file);
2417 if (GET_CODE (addr) == PRE_INC)
2419 if (GET_CODE (XEXP (addr, 0)) != REG)
2420 fatal_insn ("pre-increment address is not a register", x);
2422 fprintf (file, "@+%s", reg_names[REGNO (XEXP (addr, 0))]);
2424 else if (GET_CODE (addr) == PRE_DEC)
2426 if (GET_CODE (XEXP (addr, 0)) != REG)
2427 fatal_insn ("pre-decrement address is not a register", x);
2429 fprintf (file, "@-%s", reg_names[REGNO (XEXP (addr, 0))]);
2431 else if (GET_CODE (addr) == POST_INC)
2433 if (GET_CODE (XEXP (addr, 0)) != REG)
2434 fatal_insn ("post-increment address is not a register", x);
2436 fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]);
2441 output_address (XEXP (x, 0));
2447 /* We handle SFmode constants here as output_addr_const doesn't. */
2448 if (GET_MODE (x) == SFmode)
2453 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
2454 REAL_VALUE_TO_TARGET_SINGLE (d, l);
2455 fprintf (file, "0x%08lx", l);
2459 /* Fall through. Let output_addr_const deal with it. */
2462 output_addr_const (file, x);
2467 /* Print a memory address as an operand to reference that memory location. */
2470 m32r_print_operand_address (file, addr)
2475 register rtx index = 0;
2478 switch (GET_CODE (addr))
2481 fputs (reg_names[REGNO (addr)], file);
2485 if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
2486 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
2487 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2488 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
2490 base = XEXP (addr, 0), index = XEXP (addr, 1);
2491 if (GET_CODE (base) == REG)
2493 /* Print the offset first (if present) to conform to the manual. */
2497 fprintf (file, "%d,", offset);
2498 fputs (reg_names[REGNO (base)], file);
2500 /* The chip doesn't support this, but left in for generality. */
2501 else if (GET_CODE (index) == REG)
2502 fprintf (file, "%s,%s",
2503 reg_names[REGNO (base)], reg_names[REGNO (index)]);
2504 /* Not sure this can happen, but leave in for now. */
2505 else if (GET_CODE (index) == SYMBOL_REF)
2507 output_addr_const (file, index);
2509 fputs (reg_names[REGNO (base)], file);
2512 fatal_insn ("bad address", addr);
2514 else if (GET_CODE (base) == LO_SUM)
2517 || GET_CODE (XEXP (base, 0)) != REG)
2519 if (small_data_operand (XEXP (base, 1), VOIDmode))
2520 fputs ("sda(", file);
2522 fputs ("low(", file);
2523 output_addr_const (file, plus_constant (XEXP (base, 1), offset));
2525 fputs (reg_names[REGNO (XEXP (base, 0))], file);
2528 fatal_insn ("bad address", addr);
2532 if (GET_CODE (XEXP (addr, 0)) != REG)
2533 fatal_insn ("lo_sum not of register", addr);
2534 if (small_data_operand (XEXP (addr, 1), VOIDmode))
2535 fputs ("sda(", file);
2537 fputs ("low(", file);
2538 output_addr_const (file, XEXP (addr, 1));
2540 fputs (reg_names[REGNO (XEXP (addr, 0))], file);
2543 case PRE_INC : /* Assume SImode */
2544 fprintf (file, "+%s", reg_names[REGNO (XEXP (addr, 0))]);
2547 case PRE_DEC : /* Assume SImode */
2548 fprintf (file, "-%s", reg_names[REGNO (XEXP (addr, 0))]);
2551 case POST_INC : /* Assume SImode */
2552 fprintf (file, "%s+", reg_names[REGNO (XEXP (addr, 0))]);
2556 output_addr_const (file, addr);
2561 /* Return true if the operands are the constants 0 and 1. */
2563 zero_and_one (operand1, operand2)
2568 GET_CODE (operand1) == CONST_INT
2569 && GET_CODE (operand2) == CONST_INT
2570 && ( ((INTVAL (operand1) == 0) && (INTVAL (operand2) == 1))
2571 ||((INTVAL (operand1) == 1) && (INTVAL (operand2) == 0)));
2574 /* Return non-zero if the operand is suitable for use in a conditional move sequence. */
2576 conditional_move_operand (operand, mode)
2578 enum machine_mode mode;
2580 /* Only defined for simple integers so far... */
2581 if (mode != SImode && mode != HImode && mode != QImode)
2584 /* At the moment we can hanndle moving registers and loading constants. */
2585 /* To be added: Addition/subtraction/bitops/multiplication of registers. */
2587 switch (GET_CODE (operand))
2593 return INT8_P (INTVAL (operand));
2597 fprintf (stderr, "Test for cond move op of type: %s\n",
2598 GET_RTX_NAME (GET_CODE (operand)));
2604 /* Return true if the code is a test of the carry bit */
2606 carry_compare_operand (op, mode)
2608 enum machine_mode mode ATTRIBUTE_UNUSED;
2612 if (GET_MODE (op) != CCmode && GET_MODE (op) != VOIDmode)
2615 if (GET_CODE (op) != NE && GET_CODE (op) != EQ)
2619 if (GET_CODE (x) != REG || REGNO (x) != CARRY_REGNUM)
2623 if (GET_CODE (x) != CONST_INT || INTVAL (x) != 0)
2629 /* Generate the correct assembler code to handle the conditional loading of a
2630 value into a register. It is known that the operands satisfy the
2631 conditional_move_operand() function above. The destination is operand[0].
2632 The condition is operand [1]. The 'true' value is operand [2] and the
2633 'false' value is operand [3]. */
2635 emit_cond_move (operands, insn)
2637 rtx insn ATTRIBUTE_UNUSED;
2639 static char buffer [100];
2640 const char * dest = reg_names [REGNO (operands [0])];
2644 /* Destination must be a register. */
2645 if (GET_CODE (operands [0]) != REG)
2647 if (! conditional_move_operand (operands [2], SImode))
2649 if (! conditional_move_operand (operands [3], SImode))
2652 /* Check to see if the test is reversed. */
2653 if (GET_CODE (operands [1]) == NE)
2655 rtx tmp = operands [2];
2656 operands [2] = operands [3];
2660 sprintf (buffer, "mvfc %s, cbr", dest);
2662 /* If the true value was '0' then we need to invert the results of the move. */
2663 if (INTVAL (operands [2]) == 0)
2664 sprintf (buffer + strlen (buffer), "\n\txor3 %s, %s, #1",
2670 /* Returns true if the registers contained in the two
2671 rtl expressions are different. */
2673 m32r_not_same_reg (a, b)
2680 while (GET_CODE (a) == SUBREG)
2683 if (GET_CODE (a) == REG)
2686 while (GET_CODE (b) == SUBREG)
2689 if (GET_CODE (b) == REG)
2692 return reg_a != reg_b;
2696 /* Use a library function to move some bytes. */
2698 block_move_call (dest_reg, src_reg, bytes_rtx)
2703 /* We want to pass the size as Pmode, which will normally be SImode
2704 but will be DImode if we are using 64 bit longs and pointers. */
2705 if (GET_MODE (bytes_rtx) != VOIDmode
2706 && GET_MODE (bytes_rtx) != Pmode)
2707 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
2709 #ifdef TARGET_MEM_FUNCTIONS
2710 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0,
2711 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
2712 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
2713 TREE_UNSIGNED (sizetype)),
2714 TYPE_MODE (sizetype));
2716 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "bcopy"), 0,
2717 VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
2718 convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
2719 TREE_UNSIGNED (integer_type_node)),
2720 TYPE_MODE (integer_type_node));
2724 /* The maximum number of bytes to copy using pairs of load/store instructions.
2725 If a block is larger than this then a loop will be generated to copy
2726 MAX_MOVE_BYTES chunks at a time. The value of 32 is a semi-arbitary choice.
2727 A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte
2728 string copy in it. */
2729 #define MAX_MOVE_BYTES 32
2731 /* Expand string/block move operations.
2733 operands[0] is the pointer to the destination.
2734 operands[1] is the pointer to the source.
2735 operands[2] is the number of bytes to move.
2736 operands[3] is the alignment. */
2739 m32r_expand_block_move (operands)
2742 rtx orig_dst = operands[0];
2743 rtx orig_src = operands[1];
2744 rtx bytes_rtx = operands[2];
2745 rtx align_rtx = operands[3];
2746 int constp = GET_CODE (bytes_rtx) == CONST_INT;
2747 HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
2748 int align = INTVAL (align_rtx);
2753 if (constp && bytes <= 0)
2756 /* Move the address into scratch registers. */
2757 dst_reg = copy_addr_to_reg (XEXP (orig_dst, 0));
2758 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2760 if (align > UNITS_PER_WORD)
2761 align = UNITS_PER_WORD;
2763 /* If we prefer size over speed, always use a function call.
2764 If we do not know the size, use a function call.
2765 If the blocks are not word aligned, use a function call. */
2766 if (optimize_size || ! constp || align != UNITS_PER_WORD)
2768 block_move_call (dst_reg, src_reg, bytes_rtx);
2772 leftover = bytes % MAX_MOVE_BYTES;
2775 /* If necessary, generate a loop to handle the bulk of the copy. */
2778 rtx label = NULL_RTX;
2779 rtx final_src = NULL_RTX;
2780 rtx at_a_time = GEN_INT (MAX_MOVE_BYTES);
2781 rtx rounded_total = GEN_INT (bytes);
2783 /* If we are going to have to perform this loop more than
2784 once, then generate a label and compute the address the
2785 source register will contain upon completion of the final
2787 if (bytes > MAX_MOVE_BYTES)
2789 final_src = gen_reg_rtx (Pmode);
2792 emit_insn (gen_addsi3 (final_src, src_reg, rounded_total));
2795 emit_insn (gen_movsi (final_src, rounded_total));
2796 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
2799 label = gen_label_rtx ();
2803 /* It is known that output_block_move() will update src_reg to point
2804 to the word after the end of the source block, and dst_reg to point
2805 to the last word of the destination block, provided that the block
2806 is MAX_MOVE_BYTES long. */
2807 emit_insn (gen_movstrsi_internal (dst_reg, src_reg, at_a_time));
2808 emit_insn (gen_addsi3 (dst_reg, dst_reg, GEN_INT (4)));
2810 if (bytes > MAX_MOVE_BYTES)
2812 emit_insn (gen_cmpsi (src_reg, final_src));
2813 emit_jump_insn (gen_bne (label));
2818 emit_insn (gen_movstrsi_internal (dst_reg, src_reg, GEN_INT (leftover)));
2822 /* Emit load/stores for a small constant word aligned block_move.
2824 operands[0] is the memory address of the destination.
2825 operands[1] is the memory address of the source.
2826 operands[2] is the number of bytes to move.
2827 operands[3] is a temp register.
2828 operands[4] is a temp register. */
2831 m32r_output_block_move (insn, operands)
2832 rtx insn ATTRIBUTE_UNUSED;
2835 HOST_WIDE_INT bytes = INTVAL (operands[2]);
2839 if (bytes < 1 || bytes > MAX_MOVE_BYTES)
2842 /* We do not have a post-increment store available, so the first set of
2843 stores are done without any increment, then the remaining ones can use
2844 the pre-increment addressing mode.
2846 Note: expand_block_move() also relies upon this behaviour when building
2847 loops to copy large blocks. */
2856 output_asm_insn ("ld\t%3, %p1", operands);
2857 output_asm_insn ("ld\t%4, %p1", operands);
2858 output_asm_insn ("st\t%3, @%0", operands);
2859 output_asm_insn ("st\t%4, %s0", operands);
2863 output_asm_insn ("ld\t%3, %p1", operands);
2864 output_asm_insn ("ld\t%4, %p1", operands);
2865 output_asm_insn ("st\t%3, %s0", operands);
2866 output_asm_insn ("st\t%4, %s0", operands);
2871 else if (bytes >= 4)
2876 output_asm_insn ("ld\t%3, %p1", operands);
2879 output_asm_insn ("ld\t%4, %p1", operands);
2882 output_asm_insn ("st\t%3, @%0", operands);
2884 output_asm_insn ("st\t%3, %s0", operands);
2890 /* Get the entire next word, even though we do not want all of it.
2891 The saves us from doing several smaller loads, and we assume that
2892 we cannot cause a page fault when at least part of the word is in
2893 valid memory [since we don't get called if things aren't properly
2895 int dst_offset = first_time ? 0 : 4;
2899 /* If got_extra is true then we have already loaded
2900 the next word as part of loading and storing the previous word. */
2902 output_asm_insn ("ld\t%4, @%1", operands);
2908 output_asm_insn ("sra3\t%3, %4, #16", operands);
2909 my_operands[0] = operands[3];
2910 my_operands[1] = GEN_INT (dst_offset);
2911 my_operands[2] = operands[0];
2912 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands);
2914 /* If there is a byte left to store then increment the
2915 destination address and shift the contents of the source
2916 register down by 8 bits. We could not do the address
2917 increment in the store half word instruction, because it does
2918 not have an auto increment mode. */
2919 if (bytes > 0) /* assert (bytes == 1) */
2930 my_operands[0] = operands[4];
2931 my_operands[1] = GEN_INT (last_shift);
2932 output_asm_insn ("srai\t%0, #%1", my_operands);
2933 my_operands[0] = operands[4];
2934 my_operands[1] = GEN_INT (dst_offset);
2935 my_operands[2] = operands[0];
2936 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands);
2946 /* Return true if op is an integer constant, less than or equal to
2949 m32r_block_immediate_operand (op, mode)
2951 enum machine_mode mode ATTRIBUTE_UNUSED;
2953 if (GET_CODE (op) != CONST_INT
2954 || INTVAL (op) > MAX_MOVE_BYTES
2955 || INTVAL (op) <= 0)