1 /* Subroutines used for code generation on the Mitsubishi M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
43 #include "target-def.h"
45 /* Save the operands last given to a compare for use when we
46 generate a scc or bcc insn. */
47 rtx m32r_compare_op0, m32r_compare_op1;
49 /* Array of valid operand punctuation characters. */
50 char m32r_punct_chars[256];
52 /* Selected code model. */
53 const char * m32r_model_string = M32R_MODEL_DEFAULT;
54 enum m32r_model m32r_model;
56 /* Selected SDA support. */
57 const char * m32r_sdata_string = M32R_SDATA_DEFAULT;
58 enum m32r_sdata m32r_sdata;
60 /* Scheduler support */
61 static int m32r_sched_odd_word_p;
63 /* Machine-specific symbol_ref flags. */
64 #define SYMBOL_FLAG_MODEL_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT
65 #define SYMBOL_REF_MODEL(X) \
66 ((enum m32r_model) ((SYMBOL_REF_FLAGS (X) >> SYMBOL_FLAG_MODEL_SHIFT) & 3))
68 /* For string literals, etc. */
69 #define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.')
71 /* Forward declaration. */
72 static void init_reg_tables PARAMS ((void));
73 static void block_move_call PARAMS ((rtx, rtx, rtx));
74 static int m32r_is_insn PARAMS ((rtx));
75 const struct attribute_spec m32r_attribute_table[];
76 static tree m32r_handle_model_attribute PARAMS ((tree *, tree, tree, int, bool *));
77 static void m32r_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
78 static void m32r_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
80 static void m32r_file_start PARAMS ((void));
82 static int m32r_adjust_cost PARAMS ((rtx, rtx, rtx, int));
83 static int m32r_adjust_priority PARAMS ((rtx, int));
84 static void m32r_sched_init PARAMS ((FILE *, int, int));
85 static int m32r_sched_reorder PARAMS ((FILE *, int, rtx *, int *, int));
86 static int m32r_variable_issue PARAMS ((FILE *, int, rtx, int));
87 static int m32r_issue_rate PARAMS ((void));
89 static void m32r_encode_section_info PARAMS ((tree, rtx, int));
90 static bool m32r_in_small_data_p PARAMS ((tree));
91 static void init_idents PARAMS ((void));
92 static bool m32r_rtx_costs PARAMS ((rtx, int, int, int *));
94 /* Initialize the GCC target structure. */
95 #undef TARGET_ATTRIBUTE_TABLE
96 #define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
98 #undef TARGET_ASM_ALIGNED_HI_OP
99 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
100 #undef TARGET_ASM_ALIGNED_SI_OP
101 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
103 #undef TARGET_ASM_FUNCTION_PROLOGUE
104 #define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue
105 #undef TARGET_ASM_FUNCTION_EPILOGUE
106 #define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
108 #undef TARGET_ASM_FILE_START
109 #define TARGET_ASM_FILE_START m32r_file_start
111 #undef TARGET_SCHED_ADJUST_COST
112 #define TARGET_SCHED_ADJUST_COST m32r_adjust_cost
113 #undef TARGET_SCHED_ADJUST_PRIORITY
114 #define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
115 #undef TARGET_SCHED_ISSUE_RATE
116 #define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
117 #undef TARGET_SCHED_VARIABLE_ISSUE
118 #define TARGET_SCHED_VARIABLE_ISSUE m32r_variable_issue
119 #undef TARGET_SCHED_INIT
120 #define TARGET_SCHED_INIT m32r_sched_init
121 #undef TARGET_SCHED_REORDER
122 #define TARGET_SCHED_REORDER m32r_sched_reorder
124 #undef TARGET_ENCODE_SECTION_INFO
125 #define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info
126 #undef TARGET_IN_SMALL_DATA_P
127 #define TARGET_IN_SMALL_DATA_P m32r_in_small_data_p
129 #undef TARGET_RTX_COSTS
130 #define TARGET_RTX_COSTS m32r_rtx_costs
131 #undef TARGET_ADDRESS_COST
132 #define TARGET_ADDRESS_COST hook_int_rtx_0
134 struct gcc_target targetm = TARGET_INITIALIZER;
136 /* Called by OVERRIDE_OPTIONS to initialize various things. */
143 /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */
144 memset (m32r_punct_chars, 0, sizeof (m32r_punct_chars));
145 m32r_punct_chars['#'] = 1;
146 m32r_punct_chars['@'] = 1; /* ??? no longer used */
148 /* Provide default value if not specified. */
150 g_switch_value = SDATA_DEFAULT_SIZE;
152 if (strcmp (m32r_model_string, "small") == 0)
153 m32r_model = M32R_MODEL_SMALL;
154 else if (strcmp (m32r_model_string, "medium") == 0)
155 m32r_model = M32R_MODEL_MEDIUM;
156 else if (strcmp (m32r_model_string, "large") == 0)
157 m32r_model = M32R_MODEL_LARGE;
159 error ("bad value (%s) for -mmodel switch", m32r_model_string);
161 if (strcmp (m32r_sdata_string, "none") == 0)
162 m32r_sdata = M32R_SDATA_NONE;
163 else if (strcmp (m32r_sdata_string, "sdata") == 0)
164 m32r_sdata = M32R_SDATA_SDATA;
165 else if (strcmp (m32r_sdata_string, "use") == 0)
166 m32r_sdata = M32R_SDATA_USE;
168 error ("bad value (%s) for -msdata switch", m32r_sdata_string);
171 /* Vectors to keep interesting information about registers where it can easily
172 be got. We use to use the actual mode value as the bit number, but there
173 is (or may be) more than 32 modes now. Instead we use two tables: one
174 indexed by hard register number, and one indexed by mode. */
176 /* The purpose of m32r_mode_class is to shrink the range of modes so that
177 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
178 mapped into one m32r_mode_class mode. */
183 S_MODE, D_MODE, T_MODE, O_MODE,
184 SF_MODE, DF_MODE, TF_MODE, OF_MODE, A_MODE
187 /* Modes for condition codes. */
188 #define C_MODES (1 << (int) C_MODE)
190 /* Modes for single-word and smaller quantities. */
191 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
193 /* Modes for double-word and smaller quantities. */
194 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
196 /* Modes for quad-word and smaller quantities. */
197 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
199 /* Modes for accumulators. */
200 #define A_MODES (1 << (int) A_MODE)
202 /* Value is 1 if register/mode pair is acceptable on arc. */
204 const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
206 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
207 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
208 S_MODES, C_MODES, A_MODES, A_MODES
211 unsigned int m32r_mode_class [NUM_MACHINE_MODES];
213 enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
220 for (i = 0; i < NUM_MACHINE_MODES; i++)
222 switch (GET_MODE_CLASS (i))
225 case MODE_PARTIAL_INT:
226 case MODE_COMPLEX_INT:
227 if (GET_MODE_SIZE (i) <= 4)
228 m32r_mode_class[i] = 1 << (int) S_MODE;
229 else if (GET_MODE_SIZE (i) == 8)
230 m32r_mode_class[i] = 1 << (int) D_MODE;
231 else if (GET_MODE_SIZE (i) == 16)
232 m32r_mode_class[i] = 1 << (int) T_MODE;
233 else if (GET_MODE_SIZE (i) == 32)
234 m32r_mode_class[i] = 1 << (int) O_MODE;
236 m32r_mode_class[i] = 0;
239 case MODE_COMPLEX_FLOAT:
240 if (GET_MODE_SIZE (i) <= 4)
241 m32r_mode_class[i] = 1 << (int) SF_MODE;
242 else if (GET_MODE_SIZE (i) == 8)
243 m32r_mode_class[i] = 1 << (int) DF_MODE;
244 else if (GET_MODE_SIZE (i) == 16)
245 m32r_mode_class[i] = 1 << (int) TF_MODE;
246 else if (GET_MODE_SIZE (i) == 32)
247 m32r_mode_class[i] = 1 << (int) OF_MODE;
249 m32r_mode_class[i] = 0;
252 m32r_mode_class[i] = 1 << (int) C_MODE;
255 m32r_mode_class[i] = 0;
260 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
263 m32r_regno_reg_class[i] = GENERAL_REGS;
264 else if (i == ARG_POINTER_REGNUM)
265 m32r_regno_reg_class[i] = GENERAL_REGS;
267 m32r_regno_reg_class[i] = NO_REGS;
271 /* M32R specific attribute support.
273 interrupt - for interrupt functions
275 model - select code model used to access object
277 small: addresses use 24 bits, use bl to make calls
278 medium: addresses use 32 bits, use bl to make calls
279 large: addresses use 32 bits, use seth/add3/jl to make calls
281 Grep for MODEL in m32r.h for more info.
284 static tree small_ident1;
285 static tree small_ident2;
286 static tree medium_ident1;
287 static tree medium_ident2;
288 static tree large_ident1;
289 static tree large_ident2;
294 if (small_ident1 == 0)
296 small_ident1 = get_identifier ("small");
297 small_ident2 = get_identifier ("__small__");
298 medium_ident1 = get_identifier ("medium");
299 medium_ident2 = get_identifier ("__medium__");
300 large_ident1 = get_identifier ("large");
301 large_ident2 = get_identifier ("__large__");
305 const struct attribute_spec m32r_attribute_table[] =
307 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
308 { "interrupt", 0, 0, true, false, false, NULL },
309 { "model", 1, 1, true, false, false, m32r_handle_model_attribute },
310 { NULL, 0, 0, false, false, false, NULL }
314 /* Handle an "model" attribute; arguments as in
315 struct attribute_spec.handler. */
317 m32r_handle_model_attribute (node, name, args, flags, no_add_attrs)
318 tree *node ATTRIBUTE_UNUSED;
321 int flags ATTRIBUTE_UNUSED;
327 arg = TREE_VALUE (args);
329 if (arg != small_ident1
330 && arg != small_ident2
331 && arg != medium_ident1
332 && arg != medium_ident2
333 && arg != large_ident1
334 && arg != large_ident2)
336 warning ("invalid argument of `%s' attribute",
337 IDENTIFIER_POINTER (name));
338 *no_add_attrs = true;
344 /* Encode section information of DECL, which is either a VAR_DECL,
345 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
347 For the M32R we want to record:
349 - whether the object lives in .sdata/.sbss.
350 - what code model should be used to access the object
354 m32r_encode_section_info (decl, rtl, first)
361 enum m32r_model model;
363 default_encode_section_info (decl, rtl, first);
368 model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
375 id = TREE_VALUE (TREE_VALUE (model_attr));
377 if (id == small_ident1 || id == small_ident2)
378 model = M32R_MODEL_SMALL;
379 else if (id == medium_ident1 || id == medium_ident2)
380 model = M32R_MODEL_MEDIUM;
381 else if (id == large_ident1 || id == large_ident2)
382 model = M32R_MODEL_LARGE;
384 abort (); /* shouldn't happen */
388 if (TARGET_MODEL_SMALL)
389 model = M32R_MODEL_SMALL;
390 else if (TARGET_MODEL_MEDIUM)
391 model = M32R_MODEL_MEDIUM;
392 else if (TARGET_MODEL_LARGE)
393 model = M32R_MODEL_LARGE;
395 abort (); /* shouldn't happen */
397 extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT;
400 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
403 /* Only mark the object as being small data area addressable if
404 it hasn't been explicitly marked with a code model.
406 The user can explicitly put an object in the small data area with the
407 section attribute. If the object is in sdata/sbss and marked with a
408 code model do both [put the object in .sdata and mark it as being
409 addressed with a specific code model - don't mark it as being addressed
410 with an SDA reloc though]. This is ok and might be useful at times. If
411 the object doesn't fit the linker will give an error. */
414 m32r_in_small_data_p (decl)
419 if (TREE_CODE (decl) != VAR_DECL)
422 if (lookup_attribute ("model", DECL_ATTRIBUTES (decl)))
425 section = DECL_SECTION_NAME (decl);
428 char *name = (char *) TREE_STRING_POINTER (section);
429 if (strcmp (name, ".sdata") == 0 || strcmp (name, ".sbss") == 0)
434 if (! TREE_READONLY (decl) && ! TARGET_SDATA_NONE)
436 int size = int_size_in_bytes (TREE_TYPE (decl));
438 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
446 /* Do anything needed before RTL is emitted for each function. */
449 m32r_init_expanders ()
451 /* ??? At one point there was code here. The function is left in
452 to make it easy to experiment. */
455 /* Acceptable arguments to the call insn. */
458 call_address_operand (op, mode)
460 enum machine_mode mode;
462 return symbolic_operand (op, mode);
464 /* Constants and values in registers are not OK, because
465 the m32r BL instruction can only support PC relative branching. */
469 call_operand (op, mode)
471 enum machine_mode mode;
473 if (GET_CODE (op) != MEM)
476 return call_address_operand (op, mode);
479 /* Returns 1 if OP is a symbol reference. */
482 symbolic_operand (op, mode)
484 enum machine_mode mode ATTRIBUTE_UNUSED;
486 switch (GET_CODE (op))
498 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */
501 small_data_operand (op, mode)
503 enum machine_mode mode ATTRIBUTE_UNUSED;
505 if (! TARGET_SDATA_USE)
508 if (GET_CODE (op) == SYMBOL_REF)
509 return SYMBOL_REF_SMALL_P (op);
511 if (GET_CODE (op) == CONST
512 && GET_CODE (XEXP (op, 0)) == PLUS
513 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
514 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
515 && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
516 return SYMBOL_REF_SMALL_P (XEXP (XEXP (op, 0), 0));
521 /* Return 1 if OP is a symbol that can use 24 bit addressing. */
524 addr24_operand (op, mode)
526 enum machine_mode mode ATTRIBUTE_UNUSED;
530 if (GET_CODE (op) == LABEL_REF)
531 return TARGET_ADDR24;
533 if (GET_CODE (op) == SYMBOL_REF)
535 else if (GET_CODE (op) == CONST
536 && GET_CODE (XEXP (op, 0)) == PLUS
537 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
538 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
539 && UINT24_P (INTVAL (XEXP (XEXP (op, 0), 1))))
540 sym = XEXP (XEXP (op, 0), 0);
544 if (SYMBOL_REF_MODEL (sym) == M32R_MODEL_SMALL)
548 && (CONSTANT_POOL_ADDRESS_P (sym)
549 || LIT_NAME_P (XSTR (sym, 0))))
555 /* Return 1 if OP is a symbol that needs 32 bit addressing. */
558 addr32_operand (op, mode)
560 enum machine_mode mode;
564 if (GET_CODE (op) == LABEL_REF)
565 return TARGET_ADDR32;
567 if (GET_CODE (op) == SYMBOL_REF)
569 else if (GET_CODE (op) == CONST
570 && GET_CODE (XEXP (op, 0)) == PLUS
571 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
572 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
573 sym = XEXP (XEXP (op, 0), 0);
577 return (! addr24_operand (sym, mode)
578 && ! small_data_operand (sym, mode));
581 /* Return 1 if OP is a function that can be called with the `bl' insn. */
584 call26_operand (op, mode)
586 enum machine_mode mode ATTRIBUTE_UNUSED;
588 if (GET_CODE (op) == SYMBOL_REF)
589 return SYMBOL_REF_MODEL (op) != M32R_MODEL_LARGE;
591 return TARGET_CALL26;
594 /* Returns 1 if OP is an acceptable operand for seth/add3. */
597 seth_add3_operand (op, mode)
599 enum machine_mode mode ATTRIBUTE_UNUSED;
601 if (GET_CODE (op) == SYMBOL_REF
602 || GET_CODE (op) == LABEL_REF)
605 if (GET_CODE (op) == CONST
606 && GET_CODE (XEXP (op, 0)) == PLUS
607 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
608 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
609 && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
615 /* Return true if OP is a signed 8 bit immediate value. */
618 int8_operand (op, mode)
620 enum machine_mode mode ATTRIBUTE_UNUSED;
622 if (GET_CODE (op) != CONST_INT)
624 return INT8_P (INTVAL (op));
627 /* Return true if OP is a signed 16 bit immediate value
628 useful in comparisons. */
631 cmp_int16_operand (op, mode)
633 enum machine_mode mode ATTRIBUTE_UNUSED;
635 if (GET_CODE (op) != CONST_INT)
637 return CMP_INT16_P (INTVAL (op));
640 /* Return true if OP is an unsigned 16 bit immediate value. */
643 uint16_operand (op, mode)
645 enum machine_mode mode ATTRIBUTE_UNUSED;
647 if (GET_CODE (op) != CONST_INT)
649 return UINT16_P (INTVAL (op));
652 /* Return true if OP is a register or signed 16 bit value. */
655 reg_or_int16_operand (op, mode)
657 enum machine_mode mode;
659 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
660 return register_operand (op, mode);
661 if (GET_CODE (op) != CONST_INT)
663 return INT16_P (INTVAL (op));
666 /* Return true if OP is a register or an unsigned 16 bit value. */
669 reg_or_uint16_operand (op, mode)
671 enum machine_mode mode;
673 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
674 return register_operand (op, mode);
675 if (GET_CODE (op) != CONST_INT)
677 return UINT16_P (INTVAL (op));
680 /* Return true if OP is a register or an integer value that can be
681 used is SEQ/SNE. We can use either XOR of the value or ADD of
682 the negative of the value for the constant. Don't allow 0,
683 because that is special cased. */
686 reg_or_eq_int16_operand (op, mode)
688 enum machine_mode mode;
692 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
693 return register_operand (op, mode);
695 if (GET_CODE (op) != CONST_INT)
699 return (value != 0) && (UINT16_P (value) || CMP_INT16_P (-value));
702 /* Return true if OP is a register or signed 16 bit value for compares. */
705 reg_or_cmp_int16_operand (op, mode)
707 enum machine_mode mode;
709 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
710 return register_operand (op, mode);
711 if (GET_CODE (op) != CONST_INT)
713 return CMP_INT16_P (INTVAL (op));
716 /* Return true if OP is a register or the constant 0. */
719 reg_or_zero_operand (op, mode)
721 enum machine_mode mode;
723 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
724 return register_operand (op, mode);
726 if (GET_CODE (op) != CONST_INT)
729 return INTVAL (op) == 0;
732 /* Return true if OP is a const_int requiring two instructions to load. */
735 two_insn_const_operand (op, mode)
737 enum machine_mode mode ATTRIBUTE_UNUSED;
739 if (GET_CODE (op) != CONST_INT)
741 if (INT16_P (INTVAL (op))
742 || UINT24_P (INTVAL (op))
743 || UPPER16_P (INTVAL (op)))
748 /* Return true if OP is an acceptable argument for a single word
752 move_src_operand (op, mode)
754 enum machine_mode mode;
756 switch (GET_CODE (op))
760 return addr24_operand (op, mode);
762 /* ??? We allow more cse opportunities if we only allow constants
763 loadable with one insn, and split the rest into two. The instances
764 where this would help should be rare and the current way is
766 if (HOST_BITS_PER_WIDE_INT > 32)
768 HOST_WIDE_INT rest = INTVAL (op) >> 31;
769 return (rest == 0 || rest == -1);
774 return TARGET_ADDR24;
778 else if (mode == SImode)
780 /* Large unsigned constants are represented as const_double's. */
781 unsigned HOST_WIDE_INT low, high;
783 low = CONST_DOUBLE_LOW (op);
784 high = CONST_DOUBLE_HIGH (op);
785 return high == 0 && low <= (unsigned) 0xffffffff;
790 return register_operand (op, mode);
792 /* (subreg (mem ...) ...) can occur here if the inner part was once a
793 pseudo-reg and is now a stack slot. */
794 if (GET_CODE (SUBREG_REG (op)) == MEM)
795 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
797 return register_operand (op, mode);
799 if (GET_CODE (XEXP (op, 0)) == PRE_INC
800 || GET_CODE (XEXP (op, 0)) == PRE_DEC)
801 return 0; /* loads can't do pre-{inc,dec} */
802 return address_operand (XEXP (op, 0), mode);
808 /* Return true if OP is an acceptable argument for a double word
812 move_double_src_operand (op, mode)
814 enum machine_mode mode;
816 switch (GET_CODE (op))
822 return register_operand (op, mode);
824 /* (subreg (mem ...) ...) can occur here if the inner part was once a
825 pseudo-reg and is now a stack slot. */
826 if (GET_CODE (SUBREG_REG (op)) == MEM)
827 return move_double_src_operand (SUBREG_REG (op), mode);
829 return register_operand (op, mode);
831 /* Disallow auto inc/dec for now. */
832 if (GET_CODE (XEXP (op, 0)) == PRE_DEC
833 || GET_CODE (XEXP (op, 0)) == PRE_INC)
835 return address_operand (XEXP (op, 0), mode);
841 /* Return true if OP is an acceptable argument for a move destination. */
844 move_dest_operand (op, mode)
846 enum machine_mode mode;
848 switch (GET_CODE (op))
851 return register_operand (op, mode);
853 /* (subreg (mem ...) ...) can occur here if the inner part was once a
854 pseudo-reg and is now a stack slot. */
855 if (GET_CODE (SUBREG_REG (op)) == MEM)
856 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
858 return register_operand (op, mode);
860 if (GET_CODE (XEXP (op, 0)) == POST_INC)
861 return 0; /* stores can't do post inc */
862 return address_operand (XEXP (op, 0), mode);
868 /* Return 1 if OP is a DImode const we want to handle inline.
869 This must match the code in the movdi pattern.
870 It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER. */
876 rtx high_rtx, low_rtx;
877 HOST_WIDE_INT high, low;
879 split_double (op, &high_rtx, &low_rtx);
880 high = INTVAL (high_rtx);
881 low = INTVAL (low_rtx);
882 /* Pick constants loadable with 2 16 bit `ldi' insns. */
883 if (high >= -128 && high <= 127
884 && low >= -128 && low <= 127)
889 /* Return 1 if OP is a DFmode const we want to handle inline.
890 This must match the code in the movdf pattern.
891 It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER. */
900 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
901 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
902 if (l[0] == 0 && l[1] == 0)
904 if ((l[0] & 0xffff) == 0 && l[1] == 0)
909 /* Return 1 if OP is an EQ or NE comparison operator. */
912 eqne_comparison_operator (op, mode)
914 enum machine_mode mode ATTRIBUTE_UNUSED;
916 enum rtx_code code = GET_CODE (op);
918 if (GET_RTX_CLASS (code) != '<')
920 return (code == EQ || code == NE);
923 /* Return 1 if OP is a signed comparison operator. */
926 signed_comparison_operator (op, mode)
928 enum machine_mode mode ATTRIBUTE_UNUSED;
930 enum rtx_code code = GET_CODE (op);
932 if (GET_RTX_CLASS (code) != '<')
934 return (code == EQ || code == NE
935 || code == LT || code == LE || code == GT || code == GE);
938 /* Return 1 if OP is (mem (reg ...)).
939 This is used in insn length calcs. */
942 memreg_operand (op, mode)
944 enum machine_mode mode ATTRIBUTE_UNUSED;
946 return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == REG;
949 /* Return true if OP is an acceptable input argument for a zero/sign extend
953 extend_operand (op, mode)
955 enum machine_mode mode;
959 switch (GET_CODE (op))
963 return register_operand (op, mode);
967 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
968 return 0; /* loads can't do pre inc/pre dec */
970 return address_operand (addr, mode);
977 /* Return nonzero if the operand is an insn that is a small insn.
978 Allow const_int 0 as well, which is a placeholder for NOP slots. */
981 small_insn_p (op, mode)
983 enum machine_mode mode ATTRIBUTE_UNUSED;
985 if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
991 return get_attr_length (op) == 2;
994 /* Return nonzero if the operand is an insn that is a large insn. */
997 large_insn_p (op, mode)
999 enum machine_mode mode ATTRIBUTE_UNUSED;
1004 return get_attr_length (op) != 2;
1007 /* Return nonzero if TYPE must be passed or returned in memory.
1008 The m32r treats both directions the same so we handle both directions
1009 in this function. */
1012 m32r_pass_by_reference (type)
1015 int size = int_size_in_bytes (type);
1017 if (size < 0 || size > 8)
1025 /* X and Y are two things to compare using CODE. Emit the compare insn and
1026 return the rtx for compare [arg0 of the if_then_else].
1027 If need_compare is true then the comparison insn must be generated, rather
1028 than being subsumed into the following branch instruction. */
1031 gen_compare (code, x, y, need_compare)
1036 enum rtx_code compare_code, branch_code;
1037 rtx cc_reg = gen_rtx_REG (CCmode, CARRY_REGNUM);
1042 case EQ: compare_code = EQ; branch_code = NE; break;
1043 case NE: compare_code = EQ; branch_code = EQ; break;
1044 case LT: compare_code = LT; branch_code = NE; break;
1045 case LE: compare_code = LT; branch_code = EQ; must_swap = 1; break;
1046 case GT: compare_code = LT; branch_code = NE; must_swap = 1; break;
1047 case GE: compare_code = LT; branch_code = EQ; break;
1048 case LTU: compare_code = LTU; branch_code = NE; break;
1049 case LEU: compare_code = LTU; branch_code = EQ; must_swap = 1; break;
1050 case GTU: compare_code = LTU; branch_code = NE; must_swap = 1; break;
1051 case GEU: compare_code = LTU; branch_code = EQ; break;
1059 switch (compare_code)
1062 if (GET_CODE (y) == CONST_INT
1063 && CMP_INT16_P (INTVAL (y)) /* reg equal to small const. */
1066 rtx tmp = gen_reg_rtx (SImode);
1068 emit_insn (gen_cmp_ne_small_const_insn (tmp, x, y));
1072 else if (CONSTANT_P (y)) /* reg equal to const. */
1074 rtx tmp = force_reg (GET_MODE (x), y);
1078 if (register_operand (y, SImode) /* reg equal to reg. */
1079 || y == const0_rtx) /* req equal to zero. */
1081 emit_insn (gen_cmp_eqsi_insn (x, y));
1083 return gen_rtx (code, CCmode, cc_reg, const0_rtx);
1088 if (register_operand (y, SImode)
1089 || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
1091 rtx tmp = gen_reg_rtx (SImode); /* reg compared to reg. */
1096 emit_insn (gen_cmp_ltsi_insn (x, y));
1100 if (y == const0_rtx)
1103 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1104 emit_insn (gen_cmp_ltsi_insn (x, tmp));
1108 if (GET_CODE (y) == CONST_INT)
1109 tmp = gen_rtx (PLUS, SImode, y, const1_rtx);
1111 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1112 emit_insn (gen_cmp_ltsi_insn (x, tmp));
1116 emit_insn (gen_cmp_ltsi_insn (x, y));
1123 return gen_rtx (code, CCmode, cc_reg, const0_rtx);
1128 if (register_operand (y, SImode)
1129 || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
1131 rtx tmp = gen_reg_rtx (SImode); /* reg (unsigned) compared to reg. */
1136 emit_insn (gen_cmp_ltusi_insn (x, y));
1140 if (y == const0_rtx)
1143 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1144 emit_insn (gen_cmp_ltusi_insn (x, tmp));
1148 if (GET_CODE (y) == CONST_INT)
1149 tmp = gen_rtx (PLUS, SImode, y, const1_rtx);
1151 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1152 emit_insn (gen_cmp_ltusi_insn (x, tmp));
1156 emit_insn (gen_cmp_ltusi_insn (x, y));
1163 return gen_rtx (code, CCmode, cc_reg, const0_rtx);
1173 /* reg/reg equal comparison */
1174 if (compare_code == EQ
1175 && register_operand (y, SImode))
1176 return gen_rtx (code, CCmode, x, y);
1178 /* reg/zero signed comparison */
1179 if ((compare_code == EQ || compare_code == LT)
1181 return gen_rtx (code, CCmode, x, y);
1183 /* reg/smallconst equal comparison */
1184 if (compare_code == EQ
1185 && GET_CODE (y) == CONST_INT
1186 && CMP_INT16_P (INTVAL (y)))
1188 rtx tmp = gen_reg_rtx (SImode);
1189 emit_insn (gen_cmp_ne_small_const_insn (tmp, x, y));
1190 return gen_rtx (code, CCmode, tmp, const0_rtx);
1193 /* reg/const equal comparison */
1194 if (compare_code == EQ
1197 rtx tmp = force_reg (GET_MODE (x), y);
1198 return gen_rtx (code, CCmode, x, tmp);
1205 y = force_reg (GET_MODE (x), y);
1209 (code == LTU || code == LEU || code == GTU || code == GEU)
1210 ? uint16_operand (y, GET_MODE (y))
1211 : reg_or_cmp_int16_operand (y, GET_MODE (y));
1214 y = force_reg (GET_MODE (x), y);
1218 switch (compare_code)
1221 emit_insn (gen_cmp_eqsi_insn (must_swap ? y : x, must_swap ? x : y));
1224 emit_insn (gen_cmp_ltsi_insn (must_swap ? y : x, must_swap ? x : y));
1227 emit_insn (gen_cmp_ltusi_insn (must_swap ? y : x, must_swap ? x : y));
1234 return gen_rtx (branch_code, VOIDmode, cc_reg, CONST0_RTX (CCmode));
1237 /* Split a 2 word move (DI or DF) into component parts. */
1240 gen_split_move_double (operands)
1243 enum machine_mode mode = GET_MODE (operands[0]);
1244 rtx dest = operands[0];
1245 rtx src = operands[1];
1248 /* We might have (SUBREG (MEM)) here, so just get rid of the
1249 subregs to make this code simpler. It is safe to call
1250 alter_subreg any time after reload. */
1251 if (GET_CODE (dest) == SUBREG)
1252 alter_subreg (&dest);
1253 if (GET_CODE (src) == SUBREG)
1254 alter_subreg (&src);
1257 if (GET_CODE (dest) == REG)
1259 int dregno = REGNO (dest);
1262 if (GET_CODE (src) == REG)
1264 int sregno = REGNO (src);
1266 int reverse = (dregno == sregno + 1);
1268 /* We normally copy the low-numbered register first. However, if
1269 the first register operand 0 is the same as the second register of
1270 operand 1, we must copy in the opposite order. */
1271 emit_insn (gen_rtx_SET (VOIDmode,
1272 operand_subword (dest, reverse, TRUE, mode),
1273 operand_subword (src, reverse, TRUE, mode)));
1275 emit_insn (gen_rtx_SET (VOIDmode,
1276 operand_subword (dest, !reverse, TRUE, mode),
1277 operand_subword (src, !reverse, TRUE, mode)));
1280 /* reg = constant */
1281 else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE)
1284 split_double (src, &words[0], &words[1]);
1285 emit_insn (gen_rtx_SET (VOIDmode,
1286 operand_subword (dest, 0, TRUE, mode),
1289 emit_insn (gen_rtx_SET (VOIDmode,
1290 operand_subword (dest, 1, TRUE, mode),
1295 else if (GET_CODE (src) == MEM)
1297 /* If the high-address word is used in the address, we must load it
1298 last. Otherwise, load it first. */
1300 = (refers_to_regno_p (dregno, dregno + 1, XEXP (src, 0), 0) != 0);
1302 /* We used to optimize loads from single registers as
1306 if r3 were not used subsequently. However, the REG_NOTES aren't
1307 propagated correctly by the reload phase, and it can cause bad
1308 code to be generated. We could still try:
1310 ld r1,r3+; ld r2,r3; addi r3,-4
1312 which saves 2 bytes and doesn't force longword alignment. */
1313 emit_insn (gen_rtx_SET (VOIDmode,
1314 operand_subword (dest, reverse, TRUE, mode),
1315 adjust_address (src, SImode,
1316 reverse * UNITS_PER_WORD)));
1318 emit_insn (gen_rtx_SET (VOIDmode,
1319 operand_subword (dest, !reverse, TRUE, mode),
1320 adjust_address (src, SImode,
1321 !reverse * UNITS_PER_WORD)));
1329 /* We used to optimize loads from single registers as
1333 if r3 were not used subsequently. However, the REG_NOTES aren't
1334 propagated correctly by the reload phase, and it can cause bad
1335 code to be generated. We could still try:
1337 st r1,r3; st r2,+r3; addi r3,-4
1339 which saves 2 bytes and doesn't force longword alignment. */
1340 else if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
1342 emit_insn (gen_rtx_SET (VOIDmode,
1343 adjust_address (dest, SImode, 0),
1344 operand_subword (src, 0, TRUE, mode)));
1346 emit_insn (gen_rtx_SET (VOIDmode,
1347 adjust_address (dest, SImode, UNITS_PER_WORD),
1348 operand_subword (src, 1, TRUE, mode)));
1360 /* Implements the FUNCTION_ARG_PARTIAL_NREGS macro. */
1363 function_arg_partial_nregs (cum, mode, type, named)
1364 CUMULATIVE_ARGS *cum;
1365 enum machine_mode mode;
1367 int named ATTRIBUTE_UNUSED;
1371 (((mode == BLKmode && type)
1372 ? (unsigned int) int_size_in_bytes (type)
1373 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
1376 if (*cum >= M32R_MAX_PARM_REGS)
1378 else if (*cum + size > M32R_MAX_PARM_REGS)
1379 ret = (*cum + size) - M32R_MAX_PARM_REGS;
1386 /* Do any needed setup for a variadic function. For the M32R, we must
1387 create a register parameter block, and then copy any anonymous arguments
1388 in registers to memory.
1390 CUM has not been updated for the last named argument which has type TYPE
1391 and mode MODE, and we rely on this fact. */
1394 m32r_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
1395 CUMULATIVE_ARGS *cum;
1396 enum machine_mode mode;
1406 /* All BLKmode values are passed by reference. */
1407 if (mode == BLKmode)
1410 first_anon_arg = (ROUND_ADVANCE_CUM (*cum, mode, type)
1411 + ROUND_ADVANCE_ARG (mode, type));
1413 if (first_anon_arg < M32R_MAX_PARM_REGS)
1415 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1416 int first_reg_offset = first_anon_arg;
1417 /* Size in words to "pretend" allocate. */
1418 int size = M32R_MAX_PARM_REGS - first_reg_offset;
1421 regblock = gen_rtx_MEM (BLKmode,
1422 plus_constant (arg_pointer_rtx,
1423 FIRST_PARM_OFFSET (0)));
1424 set_mem_alias_set (regblock, get_varargs_alias_set ());
1425 move_block_from_reg (first_reg_offset, regblock, size);
1427 *pretend_size = (size * UNITS_PER_WORD);
1432 /* Implement `va_arg'. */
1435 m32r_va_arg (valist, type)
1438 HOST_WIDE_INT size, rsize;
1442 size = int_size_in_bytes (type);
1443 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
1445 if (m32r_pass_by_reference (type))
1447 tree type_ptr, type_ptr_ptr;
1449 /* Pass by reference. */
1451 type_ptr = build_pointer_type (type);
1452 type_ptr_ptr = build_pointer_type (type_ptr);
1454 t = build (POSTINCREMENT_EXPR, va_list_type_node, valist,
1455 build_int_2 (UNITS_PER_WORD, 0));
1456 TREE_SIDE_EFFECTS (t) = 1;
1457 t = build1 (NOP_EXPR, type_ptr_ptr, t);
1458 TREE_SIDE_EFFECTS (t) = 1;
1459 t = build1 (INDIRECT_REF, type_ptr, t);
1461 addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1465 /* Pass by value. */
1467 if (size < UNITS_PER_WORD)
1469 /* Care for bigendian correction on the aligned address. */
1470 t = build (PLUS_EXPR, ptr_type_node, valist,
1471 build_int_2 (rsize - size, 0));
1472 addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1473 addr_rtx = copy_to_reg (addr_rtx);
1476 t = build (PLUS_EXPR, va_list_type_node, valist,
1477 build_int_2 (rsize, 0));
1478 t = build (MODIFY_EXPR, va_list_type_node, valist, t);
1479 TREE_SIDE_EFFECTS (t) = 1;
1480 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
1484 t = build (POSTINCREMENT_EXPR, va_list_type_node, valist,
1485 build_int_2 (rsize, 0));
1486 TREE_SIDE_EFFECTS (t) = 1;
1487 addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1495 m32r_adjust_cost (insn, link, dep_insn, cost)
1496 rtx insn ATTRIBUTE_UNUSED;
1497 rtx link ATTRIBUTE_UNUSED;
1498 rtx dep_insn ATTRIBUTE_UNUSED;
1505 /* Return true if INSN is real instruction bearing insn. */
1511 return (INSN_P (insn)
1512 && GET_CODE (PATTERN (insn)) != USE
1513 && GET_CODE (PATTERN (insn)) != CLOBBER
1514 && GET_CODE (PATTERN (insn)) != ADDR_VEC);
1517 /* Increase the priority of long instructions so that the
1518 short instructions are scheduled ahead of the long ones. */
1521 m32r_adjust_priority (insn, priority)
1525 if (m32r_is_insn (insn)
1526 && get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1533 /* Initialize for scheduling a group of instructions. */
1536 m32r_sched_init (stream, verbose, max_ready)
1537 FILE * stream ATTRIBUTE_UNUSED;
1538 int verbose ATTRIBUTE_UNUSED;
1539 int max_ready ATTRIBUTE_UNUSED;
1541 m32r_sched_odd_word_p = FALSE;
1545 /* Reorder the schedulers priority list if needed */
1548 m32r_sched_reorder (stream, verbose, ready, n_readyp, clock)
1553 int clock ATTRIBUTE_UNUSED;
1555 int n_ready = *n_readyp;
1558 return m32r_issue_rate ();
1565 ";;\t\t::: Looking at %d insn(s) on ready list, boundary is %s word\n",
1567 (m32r_sched_odd_word_p) ? "odd" : "even");
1571 rtx * long_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1572 rtx * long_tail = long_head;
1573 rtx * short_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1574 rtx * short_tail = short_head;
1575 rtx * new_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1576 rtx * new_tail = new_head + (n_ready - 1);
1579 /* Loop through the instructions, classifying them as short/long. Try
1580 to keep 2 short together and/or 1 long. Note, the ready list is
1581 actually ordered backwards, so keep it in that manner. */
1582 for (i = n_ready-1; i >= 0; i--)
1584 rtx insn = ready[i];
1586 if (! m32r_is_insn (insn))
1588 /* Dump all current short/long insns just in case. */
1589 while (long_head != long_tail)
1590 *new_tail-- = *long_head++;
1592 while (short_head != short_tail)
1593 *new_tail-- = *short_head++;
1598 ";;\t\t::: Skipping non instruction %d\n",
1605 if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1606 *long_tail++ = insn;
1609 *short_tail++ = insn;
1613 /* If we are on an odd word, emit a single short instruction if
1615 if (m32r_sched_odd_word_p && short_head != short_tail)
1616 *new_tail-- = *short_head++;
1618 /* Now dump out all of the long instructions */
1619 while (long_head != long_tail)
1620 *new_tail-- = *long_head++;
1622 /* Now dump out all of the short instructions */
1623 while (short_head != short_tail)
1624 *new_tail-- = *short_head++;
1626 if (new_tail+1 != new_head)
1629 memcpy (ready, new_head, sizeof (rtx) * n_ready);
1633 fprintf (stream, ";;\t\t::: New ready list: ");
1634 for (i = 0; i < n_ready; i++)
1636 rtx insn = ready[i];
1638 fprintf (stream, " %d", INSN_UID (ready[i]));
1640 if (! m32r_is_insn (insn))
1641 fputs ("(?)", stream);
1643 else if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1644 fputs ("(l)", stream);
1647 fputs ("(s)", stream);
1650 fprintf (stream, "\n");
1653 return m32r_issue_rate ();
1656 /* Indicate how many instructions can be issued at the same time.
1657 This is sort of a lie. The m32r can issue only 1 long insn at
1658 once, but it can issue 2 short insns. The default therefore is
1659 set at 2, but this can be overridden by the command line option
1664 return ((TARGET_LOW_ISSUE_RATE) ? 1 : 2);
1667 /* If we have a machine that can issue a variable # of instructions
1668 per cycle, indicate how many more instructions can be issued
1669 after the current one. */
1671 m32r_variable_issue (stream, verbose, insn, how_many)
1677 int orig_odd_word_p = m32r_sched_odd_word_p;
1678 int short_p = FALSE;
1681 if (how_many > 0 && !TARGET_DEBUG)
1683 if (! m32r_is_insn (insn))
1686 else if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1689 m32r_sched_odd_word_p = 0;
1693 m32r_sched_odd_word_p = !m32r_sched_odd_word_p;
1698 if (verbose > 7 && stream)
1700 ";;\t\t::: %s insn %d starts on an %s word, can emit %d more instruction(s)\n",
1701 short_p ? "short" : "long",
1703 orig_odd_word_p ? "odd" : "even",
1709 /* Cost functions. */
1712 m32r_rtx_costs (x, code, outer_code, total)
1714 int code, outer_code ATTRIBUTE_UNUSED;
1719 /* Small integers are as cheap as registers. 4 byte values can be
1720 fetched as immediate constants - let's give that the cost of an
1723 if (INT16_P (INTVAL (x)))
1733 *total = COSTS_N_INSNS (1);
1739 split_double (x, &high, &low);
1740 *total = COSTS_N_INSNS (!INT16_P (INTVAL (high))
1741 + !INT16_P (INTVAL (low)));
1746 *total = COSTS_N_INSNS (3);
1753 *total = COSTS_N_INSNS (10);
1761 /* Type of function DECL.
1763 The result is cached. To reset the cache at the end of a function,
1764 call with DECL = NULL_TREE. */
1766 enum m32r_function_type
1767 m32r_compute_function_type (decl)
1771 static enum m32r_function_type fn_type = M32R_FUNCTION_UNKNOWN;
1772 /* Last function we were called for. */
1773 static tree last_fn = NULL_TREE;
1775 /* Resetting the cached value? */
1776 if (decl == NULL_TREE)
1778 fn_type = M32R_FUNCTION_UNKNOWN;
1779 last_fn = NULL_TREE;
1783 if (decl == last_fn && fn_type != M32R_FUNCTION_UNKNOWN)
1786 /* Compute function type. */
1787 fn_type = (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE
1788 ? M32R_FUNCTION_INTERRUPT
1789 : M32R_FUNCTION_NORMAL);
1794 \f/* Function prologue/epilogue handlers. */
1796 /* M32R stack frames look like:
1798 Before call After call
1799 +-----------------------+ +-----------------------+
1801 high | local variables, | | local variables, |
1802 mem | reg save area, etc. | | reg save area, etc. |
1804 +-----------------------+ +-----------------------+
1806 | arguments on stack. | | arguments on stack. |
1808 SP+0->+-----------------------+ +-----------------------+
1809 | reg parm save area, |
1810 | only created for |
1811 | variable argument |
1813 +-----------------------+
1814 | previous frame ptr |
1815 +-----------------------+
1817 | register save area |
1819 +-----------------------+
1821 +-----------------------+
1825 +-----------------------+
1827 | alloca allocations |
1829 +-----------------------+
1831 low | arguments on stack |
1833 SP+0->+-----------------------+
1836 1) The "reg parm save area" does not exist for non variable argument fns.
1837 2) The "reg parm save area" can be eliminated completely if we saved regs
1838 containing anonymous args separately but that complicates things too
1839 much (so it's not done).
1840 3) The return address is saved after the register save area so as to have as
1841 many insns as possible between the restoration of `lr' and the `jmp lr'.
1844 /* Structure to be filled in by m32r_compute_frame_size with register
1845 save masks, and offsets for the current function. */
1846 struct m32r_frame_info
1848 unsigned int total_size; /* # bytes that the entire frame takes up */
1849 unsigned int extra_size; /* # bytes of extra stuff */
1850 unsigned int pretend_size; /* # bytes we push and pretend caller did */
1851 unsigned int args_size; /* # bytes that outgoing arguments take up */
1852 unsigned int reg_size; /* # bytes needed to store regs */
1853 unsigned int var_size; /* # bytes that variables take up */
1854 unsigned int gmask; /* mask of saved gp registers */
1855 unsigned int save_fp; /* nonzero if fp must be saved */
1856 unsigned int save_lr; /* nonzero if lr (return addr) must be saved */
1857 int initialized; /* nonzero if frame size already calculated */
1860 /* Current frame information calculated by m32r_compute_frame_size. */
1861 static struct m32r_frame_info current_frame_info;
1863 /* Zero structure to initialize current_frame_info. */
1864 static struct m32r_frame_info zero_frame_info;
1866 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1867 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1869 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1870 The return address and frame pointer are treated separately.
1871 Don't consider them here. */
1872 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1873 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1874 && (regs_ever_live[regno] && (!call_used_regs[regno] || interrupt_p)))
1876 #define MUST_SAVE_FRAME_POINTER (regs_ever_live[FRAME_POINTER_REGNUM])
1877 #define MUST_SAVE_RETURN_ADDR (regs_ever_live[RETURN_ADDR_REGNUM] || current_function_profile)
1879 #define SHORT_INSN_SIZE 2 /* size of small instructions */
1880 #define LONG_INSN_SIZE 4 /* size of long instructions */
1882 /* Return the bytes needed to compute the frame pointer from the current
1885 SIZE is the size needed for local variables. */
1888 m32r_compute_frame_size (size)
1889 int size; /* # of var. bytes allocated. */
1892 unsigned int total_size, var_size, args_size, pretend_size, extra_size;
1893 unsigned int reg_size, frame_size;
1895 enum m32r_function_type fn_type;
1898 var_size = M32R_STACK_ALIGN (size);
1899 args_size = M32R_STACK_ALIGN (current_function_outgoing_args_size);
1900 pretend_size = current_function_pretend_args_size;
1901 extra_size = FIRST_PARM_OFFSET (0);
1902 total_size = extra_size + pretend_size + args_size + var_size;
1906 /* See if this is an interrupt handler. Call used registers must be saved
1908 fn_type = m32r_compute_function_type (current_function_decl);
1909 interrupt_p = M32R_INTERRUPT_P (fn_type);
1911 /* Calculate space needed for registers. */
1913 for (regno = 0; regno < M32R_MAX_INT_REGS; regno++)
1915 if (MUST_SAVE_REGISTER (regno, interrupt_p))
1917 reg_size += UNITS_PER_WORD;
1918 gmask |= 1 << regno;
1922 current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER;
1923 current_frame_info.save_lr = MUST_SAVE_RETURN_ADDR;
1925 reg_size += ((current_frame_info.save_fp + current_frame_info.save_lr)
1927 total_size += reg_size;
1929 /* ??? Not sure this is necessary, and I don't think the epilogue
1930 handler will do the right thing if this changes total_size. */
1931 total_size = M32R_STACK_ALIGN (total_size);
1933 frame_size = total_size - (pretend_size + reg_size);
1935 /* Save computed information. */
1936 current_frame_info.total_size = total_size;
1937 current_frame_info.extra_size = extra_size;
1938 current_frame_info.pretend_size = pretend_size;
1939 current_frame_info.var_size = var_size;
1940 current_frame_info.args_size = args_size;
1941 current_frame_info.reg_size = reg_size;
1942 current_frame_info.gmask = gmask;
1943 current_frame_info.initialized = reload_completed;
1945 /* Ok, we're done. */
1949 /* When the `length' insn attribute is used, this macro specifies the
1950 value to be assigned to the address of the first insn in a
1951 function. If not specified, 0 is used. */
1954 m32r_first_insn_address ()
1956 if (! current_frame_info.initialized)
1957 m32r_compute_frame_size (get_frame_size ());
1962 /* Expand the m32r prologue as a series of insns. */
1965 m32r_expand_prologue ()
1971 if (! current_frame_info.initialized)
1972 m32r_compute_frame_size (get_frame_size ());
1974 gmask = current_frame_info.gmask;
1976 /* These cases shouldn't happen. Catch them now. */
1977 if (current_frame_info.total_size == 0 && gmask)
1980 /* Allocate space for register arguments if this is a variadic function. */
1981 if (current_frame_info.pretend_size != 0)
1983 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1984 the wrong result on a 64-bit host. */
1985 HOST_WIDE_INT pretend_size = current_frame_info.pretend_size;
1986 emit_insn (gen_addsi3 (stack_pointer_rtx,
1988 GEN_INT (-pretend_size)));
1991 /* Save any registers we need to and set up fp. */
1993 if (current_frame_info.save_fp)
1994 emit_insn (gen_movsi_push (stack_pointer_rtx, frame_pointer_rtx));
1996 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1998 /* Save any needed call-saved regs (and call-used if this is an
1999 interrupt handler). */
2000 for (regno = 0; regno <= M32R_MAX_INT_REGS; ++regno)
2002 if ((gmask & (1 << regno)) != 0)
2003 emit_insn (gen_movsi_push (stack_pointer_rtx,
2004 gen_rtx_REG (Pmode, regno)));
2007 if (current_frame_info.save_lr)
2008 emit_insn (gen_movsi_push (stack_pointer_rtx,
2009 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
2011 /* Allocate the stack frame. */
2012 frame_size = (current_frame_info.total_size
2013 - (current_frame_info.pretend_size
2014 + current_frame_info.reg_size));
2016 if (frame_size == 0)
2017 ; /* nothing to do */
2018 else if (frame_size <= 32768)
2019 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
2020 GEN_INT (-frame_size)));
2023 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
2024 emit_insn (gen_movsi (tmp, GEN_INT (frame_size)));
2025 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
2028 if (frame_pointer_needed)
2029 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
2031 if (current_function_profile)
2032 emit_insn (gen_blockage ());
2036 /* Set up the stack and frame pointer (if desired) for the function.
2037 Note, if this is changed, you need to mirror the changes in
2038 m32r_compute_frame_size which calculates the prolog size. */
2041 m32r_output_function_prologue (file, size)
2045 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
2047 /* If this is an interrupt handler, mark it as such. */
2048 if (M32R_INTERRUPT_P (fn_type))
2050 fprintf (file, "\t%s interrupt handler\n",
2054 if (! current_frame_info.initialized)
2055 m32r_compute_frame_size (size);
2057 /* This is only for the human reader. */
2059 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
2061 current_frame_info.var_size,
2062 current_frame_info.reg_size / 4,
2063 current_frame_info.args_size,
2064 current_frame_info.extra_size);
2067 /* Do any necessary cleanup after a function to restore stack, frame,
2071 m32r_output_function_epilogue (file, size)
2073 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
2076 int noepilogue = FALSE;
2078 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
2080 /* This is only for the human reader. */
2081 fprintf (file, "\t%s EPILOGUE\n", ASM_COMMENT_START);
2083 if (!current_frame_info.initialized)
2085 total_size = current_frame_info.total_size;
2087 if (total_size == 0)
2089 rtx insn = get_last_insn ();
2091 /* If the last insn was a BARRIER, we don't have to write any code
2092 because a jump (aka return) was put there. */
2093 if (GET_CODE (insn) == NOTE)
2094 insn = prev_nonnote_insn (insn);
2095 if (insn && GET_CODE (insn) == BARRIER)
2101 unsigned int var_size = current_frame_info.var_size;
2102 unsigned int args_size = current_frame_info.args_size;
2103 unsigned int gmask = current_frame_info.gmask;
2104 int can_trust_sp_p = !current_function_calls_alloca;
2105 const char * sp_str = reg_names[STACK_POINTER_REGNUM];
2106 const char * fp_str = reg_names[FRAME_POINTER_REGNUM];
2108 /* The first thing to do is point the sp at the bottom of the register
2112 unsigned int reg_offset = var_size + args_size;
2113 if (reg_offset == 0)
2114 ; /* nothing to do */
2115 else if (reg_offset < 128)
2116 fprintf (file, "\taddi %s,%s%d\n",
2117 sp_str, IMMEDIATE_PREFIX, reg_offset);
2118 else if (reg_offset < 32768)
2119 fprintf (file, "\tadd3 %s,%s,%s%d\n",
2120 sp_str, sp_str, IMMEDIATE_PREFIX, reg_offset);
2122 fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
2123 reg_names[PROLOGUE_TMP_REGNUM],
2124 IMMEDIATE_PREFIX, reg_offset,
2125 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
2127 else if (frame_pointer_needed)
2129 unsigned int reg_offset = var_size + args_size;
2130 if (reg_offset == 0)
2131 fprintf (file, "\tmv %s,%s\n", sp_str, fp_str);
2132 else if (reg_offset < 32768)
2133 fprintf (file, "\tadd3 %s,%s,%s%d\n",
2134 sp_str, fp_str, IMMEDIATE_PREFIX, reg_offset);
2136 fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
2137 reg_names[PROLOGUE_TMP_REGNUM],
2138 IMMEDIATE_PREFIX, reg_offset,
2139 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
2144 if (current_frame_info.save_lr)
2145 fprintf (file, "\tpop %s\n", reg_names[RETURN_ADDR_REGNUM]);
2147 /* Restore any saved registers, in reverse order of course. */
2148 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
2149 for (regno = M32R_MAX_INT_REGS - 1; regno >= 0; --regno)
2151 if ((gmask & (1L << regno)) != 0)
2152 fprintf (file, "\tpop %s\n", reg_names[regno]);
2155 if (current_frame_info.save_fp)
2156 fprintf (file, "\tpop %s\n", fp_str);
2158 /* Remove varargs area if present. */
2159 if (current_frame_info.pretend_size != 0)
2160 fprintf (file, "\taddi %s,%s%d\n",
2161 sp_str, IMMEDIATE_PREFIX, current_frame_info.pretend_size);
2163 /* Emit the return instruction. */
2164 if (M32R_INTERRUPT_P (fn_type))
2165 fprintf (file, "\trte\n");
2167 fprintf (file, "\tjmp %s\n", reg_names[RETURN_ADDR_REGNUM]);
2170 #if 0 /* no longer needed */
2171 /* Ensure the function cleanly ends on a 32 bit boundary. */
2172 fprintf (file, "\t.fillinsn\n");
2175 /* Reset state info for each function. */
2176 current_frame_info = zero_frame_info;
2177 m32r_compute_function_type (NULL_TREE);
2180 /* Return nonzero if this function is known to have a null or 1 instruction
2186 if (!reload_completed)
2189 if (! current_frame_info.initialized)
2190 m32r_compute_frame_size (get_frame_size ());
2192 return current_frame_info.total_size == 0;
2198 /* Emit special PIC prologues and epilogues. */
2201 m32r_finalize_pic ()
2206 /* Nested function support. */
2208 /* Emit RTL insns to initialize the variable parts of a trampoline.
2209 FNADDR is an RTX for the address of the function's pure code.
2210 CXT is an RTX for the static chain value for the function. */
2213 m32r_initialize_trampoline (tramp, fnaddr, cxt)
2214 rtx tramp ATTRIBUTE_UNUSED;
2215 rtx fnaddr ATTRIBUTE_UNUSED;
2216 rtx cxt ATTRIBUTE_UNUSED;
2223 default_file_start ();
2225 if (flag_verbose_asm)
2226 fprintf (asm_out_file,
2227 "%s M32R/D special options: -G " HOST_WIDE_INT_PRINT_UNSIGNED "\n",
2228 ASM_COMMENT_START, g_switch_value);
2231 /* Print operand X (an rtx) in assembler syntax to file FILE.
2232 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2233 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2236 m32r_print_operand (file, x, code)
2245 /* The 's' and 'p' codes are used by output_block_move() to
2246 indicate post-increment 's'tores and 'p're-increment loads. */
2248 if (GET_CODE (x) == REG)
2249 fprintf (file, "@+%s", reg_names [REGNO (x)]);
2251 output_operand_lossage ("invalid operand to %%s code");
2255 if (GET_CODE (x) == REG)
2256 fprintf (file, "@%s+", reg_names [REGNO (x)]);
2258 output_operand_lossage ("invalid operand to %%p code");
2262 /* Write second word of DImode or DFmode reference,
2263 register or memory. */
2264 if (GET_CODE (x) == REG)
2265 fputs (reg_names[REGNO (x)+1], file);
2266 else if (GET_CODE (x) == MEM)
2268 fprintf (file, "@(");
2269 /* Handle possible auto-increment. Since it is pre-increment and
2270 we have already done it, we can just use an offset of four. */
2271 /* ??? This is taken from rs6000.c I think. I don't think it is
2272 currently necessary, but keep it around. */
2273 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2274 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2275 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
2277 output_address (plus_constant (XEXP (x, 0), 4));
2281 output_operand_lossage ("invalid operand to %%R code");
2284 case 'H' : /* High word */
2285 case 'L' : /* Low word */
2286 if (GET_CODE (x) == REG)
2288 /* L = least significant word, H = most significant word */
2289 if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L'))
2290 fputs (reg_names[REGNO (x)], file);
2292 fputs (reg_names[REGNO (x)+1], file);
2294 else if (GET_CODE (x) == CONST_INT
2295 || GET_CODE (x) == CONST_DOUBLE)
2299 split_double (x, &first, &second);
2300 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2301 code == 'L' ? INTVAL (first) : INTVAL (second));
2304 output_operand_lossage ("invalid operand to %%H/%%L code");
2311 if (GET_CODE (x) != CONST_DOUBLE
2312 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
2313 fatal_insn ("bad insn for 'A'", x);
2315 real_to_decimal (str, CONST_DOUBLE_REAL_VALUE (x), sizeof (str), 0, 1);
2316 fprintf (file, "%s", str);
2320 case 'B' : /* Bottom half */
2321 case 'T' : /* Top half */
2322 /* Output the argument to a `seth' insn (sets the Top half-word).
2323 For constants output arguments to a seth/or3 pair to set Top and
2324 Bottom halves. For symbols output arguments to a seth/add3 pair to
2325 set Top and Bottom halves. The difference exists because for
2326 constants seth/or3 is more readable but for symbols we need to use
2327 the same scheme as `ld' and `st' insns (16 bit addend is signed). */
2328 switch (GET_CODE (x))
2335 split_double (x, &first, &second);
2336 x = WORDS_BIG_ENDIAN ? second : first;
2337 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2339 ? INTVAL (x) & 0xffff
2340 : (INTVAL (x) >> 16) & 0xffff));
2346 && small_data_operand (x, VOIDmode))
2348 fputs ("sda(", file);
2349 output_addr_const (file, x);
2355 fputs (code == 'T' ? "shigh(" : "low(", file);
2356 output_addr_const (file, x);
2360 output_operand_lossage ("invalid operand to %%T/%%B code");
2367 /* Output a load/store with update indicator if appropriate. */
2368 if (GET_CODE (x) == MEM)
2370 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2371 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2375 output_operand_lossage ("invalid operand to %%U code");
2379 /* Print a constant value negated. */
2380 if (GET_CODE (x) == CONST_INT)
2381 output_addr_const (file, GEN_INT (- INTVAL (x)));
2383 output_operand_lossage ("invalid operand to %%N code");
2387 /* Print a const_int in hex. Used in comments. */
2388 if (GET_CODE (x) == CONST_INT)
2389 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
2393 fputs (IMMEDIATE_PREFIX, file);
2396 #if 0 /* ??? no longer used */
2398 fputs (reg_names[SDA_REGNUM], file);
2403 /* Do nothing special. */
2408 output_operand_lossage ("invalid operand output code");
2411 switch (GET_CODE (x))
2414 fputs (reg_names[REGNO (x)], file);
2419 if (GET_CODE (addr) == PRE_INC)
2421 if (GET_CODE (XEXP (addr, 0)) != REG)
2422 fatal_insn ("pre-increment address is not a register", x);
2424 fprintf (file, "@+%s", reg_names[REGNO (XEXP (addr, 0))]);
2426 else if (GET_CODE (addr) == PRE_DEC)
2428 if (GET_CODE (XEXP (addr, 0)) != REG)
2429 fatal_insn ("pre-decrement address is not a register", x);
2431 fprintf (file, "@-%s", reg_names[REGNO (XEXP (addr, 0))]);
2433 else if (GET_CODE (addr) == POST_INC)
2435 if (GET_CODE (XEXP (addr, 0)) != REG)
2436 fatal_insn ("post-increment address is not a register", x);
2438 fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]);
2443 output_address (XEXP (x, 0));
2449 /* We handle SFmode constants here as output_addr_const doesn't. */
2450 if (GET_MODE (x) == SFmode)
2455 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
2456 REAL_VALUE_TO_TARGET_SINGLE (d, l);
2457 fprintf (file, "0x%08lx", l);
2461 /* Fall through. Let output_addr_const deal with it. */
2464 output_addr_const (file, x);
2469 /* Print a memory address as an operand to reference that memory location. */
2472 m32r_print_operand_address (file, addr)
2477 register rtx index = 0;
2480 switch (GET_CODE (addr))
2483 fputs (reg_names[REGNO (addr)], file);
2487 if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
2488 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
2489 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2490 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
2492 base = XEXP (addr, 0), index = XEXP (addr, 1);
2493 if (GET_CODE (base) == REG)
2495 /* Print the offset first (if present) to conform to the manual. */
2499 fprintf (file, "%d,", offset);
2500 fputs (reg_names[REGNO (base)], file);
2502 /* The chip doesn't support this, but left in for generality. */
2503 else if (GET_CODE (index) == REG)
2504 fprintf (file, "%s,%s",
2505 reg_names[REGNO (base)], reg_names[REGNO (index)]);
2506 /* Not sure this can happen, but leave in for now. */
2507 else if (GET_CODE (index) == SYMBOL_REF)
2509 output_addr_const (file, index);
2511 fputs (reg_names[REGNO (base)], file);
2514 fatal_insn ("bad address", addr);
2516 else if (GET_CODE (base) == LO_SUM)
2519 || GET_CODE (XEXP (base, 0)) != REG)
2521 if (small_data_operand (XEXP (base, 1), VOIDmode))
2522 fputs ("sda(", file);
2524 fputs ("low(", file);
2525 output_addr_const (file, plus_constant (XEXP (base, 1), offset));
2527 fputs (reg_names[REGNO (XEXP (base, 0))], file);
2530 fatal_insn ("bad address", addr);
2534 if (GET_CODE (XEXP (addr, 0)) != REG)
2535 fatal_insn ("lo_sum not of register", addr);
2536 if (small_data_operand (XEXP (addr, 1), VOIDmode))
2537 fputs ("sda(", file);
2539 fputs ("low(", file);
2540 output_addr_const (file, XEXP (addr, 1));
2542 fputs (reg_names[REGNO (XEXP (addr, 0))], file);
2545 case PRE_INC : /* Assume SImode */
2546 fprintf (file, "+%s", reg_names[REGNO (XEXP (addr, 0))]);
2549 case PRE_DEC : /* Assume SImode */
2550 fprintf (file, "-%s", reg_names[REGNO (XEXP (addr, 0))]);
2553 case POST_INC : /* Assume SImode */
2554 fprintf (file, "%s+", reg_names[REGNO (XEXP (addr, 0))]);
2558 output_addr_const (file, addr);
2563 /* Return true if the operands are the constants 0 and 1. */
2565 zero_and_one (operand1, operand2)
2570 GET_CODE (operand1) == CONST_INT
2571 && GET_CODE (operand2) == CONST_INT
2572 && ( ((INTVAL (operand1) == 0) && (INTVAL (operand2) == 1))
2573 ||((INTVAL (operand1) == 1) && (INTVAL (operand2) == 0)));
2576 /* Return nonzero if the operand is suitable for use in a conditional move sequence. */
2578 conditional_move_operand (operand, mode)
2580 enum machine_mode mode;
2582 /* Only defined for simple integers so far... */
2583 if (mode != SImode && mode != HImode && mode != QImode)
2586 /* At the moment we can handle moving registers and loading constants. */
2587 /* To be added: Addition/subtraction/bitops/multiplication of registers. */
2589 switch (GET_CODE (operand))
2595 return INT8_P (INTVAL (operand));
2599 fprintf (stderr, "Test for cond move op of type: %s\n",
2600 GET_RTX_NAME (GET_CODE (operand)));
2606 /* Return true if the code is a test of the carry bit */
2608 carry_compare_operand (op, mode)
2610 enum machine_mode mode ATTRIBUTE_UNUSED;
2614 if (GET_MODE (op) != CCmode && GET_MODE (op) != VOIDmode)
2617 if (GET_CODE (op) != NE && GET_CODE (op) != EQ)
2621 if (GET_CODE (x) != REG || REGNO (x) != CARRY_REGNUM)
2625 if (GET_CODE (x) != CONST_INT || INTVAL (x) != 0)
2631 /* Generate the correct assembler code to handle the conditional loading of a
2632 value into a register. It is known that the operands satisfy the
2633 conditional_move_operand() function above. The destination is operand[0].
2634 The condition is operand [1]. The 'true' value is operand [2] and the
2635 'false' value is operand [3]. */
2637 emit_cond_move (operands, insn)
2639 rtx insn ATTRIBUTE_UNUSED;
2641 static char buffer [100];
2642 const char * dest = reg_names [REGNO (operands [0])];
2646 /* Destination must be a register. */
2647 if (GET_CODE (operands [0]) != REG)
2649 if (! conditional_move_operand (operands [2], SImode))
2651 if (! conditional_move_operand (operands [3], SImode))
2654 /* Check to see if the test is reversed. */
2655 if (GET_CODE (operands [1]) == NE)
2657 rtx tmp = operands [2];
2658 operands [2] = operands [3];
2662 sprintf (buffer, "mvfc %s, cbr", dest);
2664 /* If the true value was '0' then we need to invert the results of the move. */
2665 if (INTVAL (operands [2]) == 0)
2666 sprintf (buffer + strlen (buffer), "\n\txor3 %s, %s, #1",
2672 /* Returns true if the registers contained in the two
2673 rtl expressions are different. */
2675 m32r_not_same_reg (a, b)
2682 while (GET_CODE (a) == SUBREG)
2685 if (GET_CODE (a) == REG)
2688 while (GET_CODE (b) == SUBREG)
2691 if (GET_CODE (b) == REG)
2694 return reg_a != reg_b;
2698 /* Use a library function to move some bytes. */
2700 block_move_call (dest_reg, src_reg, bytes_rtx)
2705 /* We want to pass the size as Pmode, which will normally be SImode
2706 but will be DImode if we are using 64 bit longs and pointers. */
2707 if (GET_MODE (bytes_rtx) != VOIDmode
2708 && GET_MODE (bytes_rtx) != Pmode)
2709 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
2711 #ifdef TARGET_MEM_FUNCTIONS
2712 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0,
2713 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
2714 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
2715 TREE_UNSIGNED (sizetype)),
2716 TYPE_MODE (sizetype));
2718 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "bcopy"), 0,
2719 VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
2720 convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
2721 TREE_UNSIGNED (integer_type_node)),
2722 TYPE_MODE (integer_type_node));
2726 /* The maximum number of bytes to copy using pairs of load/store instructions.
2727 If a block is larger than this then a loop will be generated to copy
2728 MAX_MOVE_BYTES chunks at a time. The value of 32 is a semi-arbitrary choice.
2729 A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte
2730 string copy in it. */
2731 #define MAX_MOVE_BYTES 32
2733 /* Expand string/block move operations.
2735 operands[0] is the pointer to the destination.
2736 operands[1] is the pointer to the source.
2737 operands[2] is the number of bytes to move.
2738 operands[3] is the alignment. */
2741 m32r_expand_block_move (operands)
2744 rtx orig_dst = operands[0];
2745 rtx orig_src = operands[1];
2746 rtx bytes_rtx = operands[2];
2747 rtx align_rtx = operands[3];
2748 int constp = GET_CODE (bytes_rtx) == CONST_INT;
2749 HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
2750 int align = INTVAL (align_rtx);
2755 if (constp && bytes <= 0)
2758 /* Move the address into scratch registers. */
2759 dst_reg = copy_addr_to_reg (XEXP (orig_dst, 0));
2760 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2762 if (align > UNITS_PER_WORD)
2763 align = UNITS_PER_WORD;
2765 /* If we prefer size over speed, always use a function call.
2766 If we do not know the size, use a function call.
2767 If the blocks are not word aligned, use a function call. */
2768 if (optimize_size || ! constp || align != UNITS_PER_WORD)
2770 block_move_call (dst_reg, src_reg, bytes_rtx);
2774 leftover = bytes % MAX_MOVE_BYTES;
2777 /* If necessary, generate a loop to handle the bulk of the copy. */
2780 rtx label = NULL_RTX;
2781 rtx final_src = NULL_RTX;
2782 rtx at_a_time = GEN_INT (MAX_MOVE_BYTES);
2783 rtx rounded_total = GEN_INT (bytes);
2785 /* If we are going to have to perform this loop more than
2786 once, then generate a label and compute the address the
2787 source register will contain upon completion of the final
2789 if (bytes > MAX_MOVE_BYTES)
2791 final_src = gen_reg_rtx (Pmode);
2794 emit_insn (gen_addsi3 (final_src, src_reg, rounded_total));
2797 emit_insn (gen_movsi (final_src, rounded_total));
2798 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
2801 label = gen_label_rtx ();
2805 /* It is known that output_block_move() will update src_reg to point
2806 to the word after the end of the source block, and dst_reg to point
2807 to the last word of the destination block, provided that the block
2808 is MAX_MOVE_BYTES long. */
2809 emit_insn (gen_movstrsi_internal (dst_reg, src_reg, at_a_time));
2810 emit_insn (gen_addsi3 (dst_reg, dst_reg, GEN_INT (4)));
2812 if (bytes > MAX_MOVE_BYTES)
2814 emit_insn (gen_cmpsi (src_reg, final_src));
2815 emit_jump_insn (gen_bne (label));
2820 emit_insn (gen_movstrsi_internal (dst_reg, src_reg, GEN_INT (leftover)));
2824 /* Emit load/stores for a small constant word aligned block_move.
2826 operands[0] is the memory address of the destination.
2827 operands[1] is the memory address of the source.
2828 operands[2] is the number of bytes to move.
2829 operands[3] is a temp register.
2830 operands[4] is a temp register. */
2833 m32r_output_block_move (insn, operands)
2834 rtx insn ATTRIBUTE_UNUSED;
2837 HOST_WIDE_INT bytes = INTVAL (operands[2]);
2841 if (bytes < 1 || bytes > MAX_MOVE_BYTES)
2844 /* We do not have a post-increment store available, so the first set of
2845 stores are done without any increment, then the remaining ones can use
2846 the pre-increment addressing mode.
2848 Note: expand_block_move() also relies upon this behavior when building
2849 loops to copy large blocks. */
2858 output_asm_insn ("ld\t%3, %p1", operands);
2859 output_asm_insn ("ld\t%4, %p1", operands);
2860 output_asm_insn ("st\t%3, @%0", operands);
2861 output_asm_insn ("st\t%4, %s0", operands);
2865 output_asm_insn ("ld\t%3, %p1", operands);
2866 output_asm_insn ("ld\t%4, %p1", operands);
2867 output_asm_insn ("st\t%3, %s0", operands);
2868 output_asm_insn ("st\t%4, %s0", operands);
2873 else if (bytes >= 4)
2878 output_asm_insn ("ld\t%3, %p1", operands);
2881 output_asm_insn ("ld\t%4, %p1", operands);
2884 output_asm_insn ("st\t%3, @%0", operands);
2886 output_asm_insn ("st\t%3, %s0", operands);
2892 /* Get the entire next word, even though we do not want all of it.
2893 The saves us from doing several smaller loads, and we assume that
2894 we cannot cause a page fault when at least part of the word is in
2895 valid memory [since we don't get called if things aren't properly
2897 int dst_offset = first_time ? 0 : 4;
2901 /* If got_extra is true then we have already loaded
2902 the next word as part of loading and storing the previous word. */
2904 output_asm_insn ("ld\t%4, @%1", operands);
2910 output_asm_insn ("sra3\t%3, %4, #16", operands);
2911 my_operands[0] = operands[3];
2912 my_operands[1] = GEN_INT (dst_offset);
2913 my_operands[2] = operands[0];
2914 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands);
2916 /* If there is a byte left to store then increment the
2917 destination address and shift the contents of the source
2918 register down by 8 bits. We could not do the address
2919 increment in the store half word instruction, because it does
2920 not have an auto increment mode. */
2921 if (bytes > 0) /* assert (bytes == 1) */
2932 my_operands[0] = operands[4];
2933 my_operands[1] = GEN_INT (last_shift);
2934 output_asm_insn ("srai\t%0, #%1", my_operands);
2935 my_operands[0] = operands[4];
2936 my_operands[1] = GEN_INT (dst_offset);
2937 my_operands[2] = operands[0];
2938 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands);
2948 /* Return true if op is an integer constant, less than or equal to
2951 m32r_block_immediate_operand (op, mode)
2953 enum machine_mode mode ATTRIBUTE_UNUSED;
2955 if (GET_CODE (op) != CONST_INT
2956 || INTVAL (op) > MAX_MOVE_BYTES
2957 || INTVAL (op) <= 0)
2963 /* Return true if using NEW_REG in place of OLD_REG is ok. */
2966 m32r_hard_regno_rename_ok (old_reg, new_reg)
2967 unsigned int old_reg ATTRIBUTE_UNUSED;
2968 unsigned int new_reg;
2970 /* Interrupt routines can't clobber any register that isn't already used. */
2971 if (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl))
2972 && !regs_ever_live[new_reg])
2975 /* We currently emit epilogues as text, not rtl, so the liveness
2976 of the return address register isn't visible. */
2977 if (current_function_is_leaf && new_reg == RETURN_ADDR_REGNUM)