1 /* Subroutines used for code generation on the Mitsubishi M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
32 #include "insn-attr.h"
39 #include "m32r-protos.h"
41 #include "target-def.h"
43 /* Save the operands last given to a compare for use when we
44 generate a scc or bcc insn. */
45 rtx m32r_compare_op0, m32r_compare_op1;
47 /* Array of valid operand punctuation characters. */
48 char m32r_punct_chars[256];
50 /* Selected code model. */
51 const char * m32r_model_string = M32R_MODEL_DEFAULT;
52 enum m32r_model m32r_model;
54 /* Selected SDA support. */
55 const char * m32r_sdata_string = M32R_SDATA_DEFAULT;
56 enum m32r_sdata m32r_sdata;
58 /* Scheduler support */
59 static int m32r_sched_odd_word_p;
61 /* Forward declaration. */
62 static void init_reg_tables PARAMS ((void));
63 static void block_move_call PARAMS ((rtx, rtx, rtx));
64 static int m32r_is_insn PARAMS ((rtx));
65 const struct attribute_spec m32r_attribute_table[];
66 static tree m32r_handle_model_attribute PARAMS ((tree *, tree, tree, int, bool *));
67 static void m32r_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
68 static void m32r_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
70 static int m32r_adjust_cost PARAMS ((rtx, rtx, rtx, int));
71 static int m32r_adjust_priority PARAMS ((rtx, int));
72 static void m32r_sched_init PARAMS ((FILE *, int, int));
73 static int m32r_sched_reorder PARAMS ((FILE *, int, rtx *, int *, int));
74 static int m32r_variable_issue PARAMS ((FILE *, int, rtx, int));
75 static int m32r_issue_rate PARAMS ((void));
77 static void m32r_select_section PARAMS ((tree, int, unsigned HOST_WIDE_INT));
80 /* Initialize the GCC target structure. */
81 #undef TARGET_ATTRIBUTE_TABLE
82 #define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
84 #undef TARGET_ASM_ALIGNED_HI_OP
85 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
86 #undef TARGET_ASM_ALIGNED_SI_OP
87 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
89 #undef TARGET_ASM_FUNCTION_PROLOGUE
90 #define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue
91 #undef TARGET_ASM_FUNCTION_EPILOGUE
92 #define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
94 #undef TARGET_SCHED_ADJUST_COST
95 #define TARGET_SCHED_ADJUST_COST m32r_adjust_cost
96 #undef TARGET_SCHED_ADJUST_PRIORITY
97 #define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
98 #undef TARGET_SCHED_ISSUE_RATE
99 #define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
100 #undef TARGET_SCHED_VARIABLE_ISSUE
101 #define TARGET_SCHED_VARIABLE_ISSUE m32r_variable_issue
102 #undef TARGET_SCHED_INIT
103 #define TARGET_SCHED_INIT m32r_sched_init
104 #undef TARGET_SCHED_REORDER
105 #define TARGET_SCHED_REORDER m32r_sched_reorder
107 struct gcc_target targetm = TARGET_INITIALIZER;
109 /* Called by OVERRIDE_OPTIONS to initialize various things. */
116 /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */
117 memset (m32r_punct_chars, 0, sizeof (m32r_punct_chars));
118 m32r_punct_chars['#'] = 1;
119 m32r_punct_chars['@'] = 1; /* ??? no longer used */
121 /* Provide default value if not specified. */
123 g_switch_value = SDATA_DEFAULT_SIZE;
125 if (strcmp (m32r_model_string, "small") == 0)
126 m32r_model = M32R_MODEL_SMALL;
127 else if (strcmp (m32r_model_string, "medium") == 0)
128 m32r_model = M32R_MODEL_MEDIUM;
129 else if (strcmp (m32r_model_string, "large") == 0)
130 m32r_model = M32R_MODEL_LARGE;
132 error ("bad value (%s) for -mmodel switch", m32r_model_string);
134 if (strcmp (m32r_sdata_string, "none") == 0)
135 m32r_sdata = M32R_SDATA_NONE;
136 else if (strcmp (m32r_sdata_string, "sdata") == 0)
137 m32r_sdata = M32R_SDATA_SDATA;
138 else if (strcmp (m32r_sdata_string, "use") == 0)
139 m32r_sdata = M32R_SDATA_USE;
141 error ("bad value (%s) for -msdata switch", m32r_sdata_string);
144 /* Vectors to keep interesting information about registers where it can easily
145 be got. We use to use the actual mode value as the bit number, but there
146 is (or may be) more than 32 modes now. Instead we use two tables: one
147 indexed by hard register number, and one indexed by mode. */
149 /* The purpose of m32r_mode_class is to shrink the range of modes so that
150 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
151 mapped into one m32r_mode_class mode. */
156 S_MODE, D_MODE, T_MODE, O_MODE,
157 SF_MODE, DF_MODE, TF_MODE, OF_MODE, A_MODE
160 /* Modes for condition codes. */
161 #define C_MODES (1 << (int) C_MODE)
163 /* Modes for single-word and smaller quantities. */
164 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
166 /* Modes for double-word and smaller quantities. */
167 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
169 /* Modes for quad-word and smaller quantities. */
170 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
172 /* Modes for accumulators. */
173 #define A_MODES (1 << (int) A_MODE)
175 /* Value is 1 if register/mode pair is acceptable on arc. */
177 const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
179 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
180 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
181 S_MODES, C_MODES, A_MODES, A_MODES
184 unsigned int m32r_mode_class [NUM_MACHINE_MODES];
186 enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
193 for (i = 0; i < NUM_MACHINE_MODES; i++)
195 switch (GET_MODE_CLASS (i))
198 case MODE_PARTIAL_INT:
199 case MODE_COMPLEX_INT:
200 if (GET_MODE_SIZE (i) <= 4)
201 m32r_mode_class[i] = 1 << (int) S_MODE;
202 else if (GET_MODE_SIZE (i) == 8)
203 m32r_mode_class[i] = 1 << (int) D_MODE;
204 else if (GET_MODE_SIZE (i) == 16)
205 m32r_mode_class[i] = 1 << (int) T_MODE;
206 else if (GET_MODE_SIZE (i) == 32)
207 m32r_mode_class[i] = 1 << (int) O_MODE;
209 m32r_mode_class[i] = 0;
212 case MODE_COMPLEX_FLOAT:
213 if (GET_MODE_SIZE (i) <= 4)
214 m32r_mode_class[i] = 1 << (int) SF_MODE;
215 else if (GET_MODE_SIZE (i) == 8)
216 m32r_mode_class[i] = 1 << (int) DF_MODE;
217 else if (GET_MODE_SIZE (i) == 16)
218 m32r_mode_class[i] = 1 << (int) TF_MODE;
219 else if (GET_MODE_SIZE (i) == 32)
220 m32r_mode_class[i] = 1 << (int) OF_MODE;
222 m32r_mode_class[i] = 0;
226 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
227 we must explicitly check for them here. */
228 if (i == (int) CCmode)
229 m32r_mode_class[i] = 1 << (int) C_MODE;
231 m32r_mode_class[i] = 0;
236 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
239 m32r_regno_reg_class[i] = GENERAL_REGS;
240 else if (i == ARG_POINTER_REGNUM)
241 m32r_regno_reg_class[i] = GENERAL_REGS;
243 m32r_regno_reg_class[i] = NO_REGS;
247 /* M32R specific attribute support.
249 interrupt - for interrupt functions
251 model - select code model used to access object
253 small: addresses use 24 bits, use bl to make calls
254 medium: addresses use 32 bits, use bl to make calls
255 large: addresses use 32 bits, use seth/add3/jl to make calls
257 Grep for MODEL in m32r.h for more info.
260 static tree small_ident1;
261 static tree small_ident2;
262 static tree medium_ident1;
263 static tree medium_ident2;
264 static tree large_ident1;
265 static tree large_ident2;
268 init_idents PARAMS ((void))
270 if (small_ident1 == 0)
272 small_ident1 = get_identifier ("small");
273 small_ident2 = get_identifier ("__small__");
274 medium_ident1 = get_identifier ("medium");
275 medium_ident2 = get_identifier ("__medium__");
276 large_ident1 = get_identifier ("large");
277 large_ident2 = get_identifier ("__large__");
281 const struct attribute_spec m32r_attribute_table[] =
283 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
284 { "interrupt", 0, 0, true, false, false, NULL },
285 { "model", 1, 1, true, false, false, m32r_handle_model_attribute },
286 { NULL, 0, 0, false, false, false, NULL }
290 /* Handle an "model" attribute; arguments as in
291 struct attribute_spec.handler. */
293 m32r_handle_model_attribute (node, name, args, flags, no_add_attrs)
294 tree *node ATTRIBUTE_UNUSED;
297 int flags ATTRIBUTE_UNUSED;
303 arg = TREE_VALUE (args);
305 if (arg != small_ident1
306 && arg != small_ident2
307 && arg != medium_ident1
308 && arg != medium_ident2
309 && arg != large_ident1
310 && arg != large_ident2)
312 warning ("invalid argument of `%s' attribute",
313 IDENTIFIER_POINTER (name));
314 *no_add_attrs = true;
320 /* A C statement or statements to switch to the appropriate
321 section for output of DECL. DECL is either a `VAR_DECL' node
322 or a constant of some sort. RELOC indicates whether forming
323 the initial value of DECL requires link-time relocations. */
326 m32r_select_section (decl, reloc, align)
329 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED;
331 if (TREE_CODE (decl) == STRING_CST)
333 if (! flag_writable_strings)
334 readonly_data_section ();
338 else if (TREE_CODE (decl) == VAR_DECL)
340 if (SDATA_NAME_P (XSTR (XEXP (DECL_RTL (decl), 0), 0)))
342 else if ((flag_pic && reloc)
343 || !TREE_READONLY (decl)
344 || TREE_SIDE_EFFECTS (decl)
345 || !DECL_INITIAL (decl)
346 || (DECL_INITIAL (decl) != error_mark_node
347 && !TREE_CONSTANT (DECL_INITIAL (decl))))
350 readonly_data_section ();
353 readonly_data_section ();
356 /* Encode section information of DECL, which is either a VAR_DECL,
357 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
359 For the M32R we want to record:
361 - whether the object lives in .sdata/.sbss.
362 objects living in .sdata/.sbss are prefixed with SDATA_FLAG_CHAR
364 - what code model should be used to access the object
365 small: recorded with no flag - for space efficiency since they'll
367 medium: prefixed with MEDIUM_FLAG_CHAR
368 large: prefixed with LARGE_FLAG_CHAR
372 m32r_encode_section_info (decl, first)
382 switch (TREE_CODE (decl))
386 model = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
390 /* ??? document all others that can appear here */
395 /* Only mark the object as being small data area addressable if
396 it hasn't been explicitly marked with a code model.
398 The user can explicitly put an object in the small data area with the
399 section attribute. If the object is in sdata/sbss and marked with a
400 code model do both [put the object in .sdata and mark it as being
401 addressed with a specific code model - don't mark it as being addressed
402 with an SDA reloc though]. This is ok and might be useful at times. If
403 the object doesn't fit the linker will give an error. */
407 if (TREE_CODE_CLASS (TREE_CODE (decl)) == 'd'
408 && DECL_SECTION_NAME (decl) != NULL_TREE)
410 char *name = (char *) TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
411 if (! strcmp (name, ".sdata") || ! strcmp (name, ".sbss"))
413 #if 0 /* ??? There's no reason to disallow this, is there? */
414 if (TREE_READONLY (decl))
415 error_with_decl (decl, "const objects cannot go in .sdata/.sbss");
417 prefix = SDATA_FLAG_CHAR;
422 if (TREE_CODE (decl) == VAR_DECL
423 && ! TREE_READONLY (decl)
424 && ! TARGET_SDATA_NONE)
426 int size = int_size_in_bytes (TREE_TYPE (decl));
428 if (size > 0 && size <= g_switch_value)
429 prefix = SDATA_FLAG_CHAR;
434 /* If data area not decided yet, check for a code model. */
443 id = TREE_VALUE (TREE_VALUE (model));
445 if (id == small_ident1 || id == small_ident2)
446 ; /* don't mark the symbol specially */
447 else if (id == medium_ident1 || id == medium_ident2)
448 prefix = MEDIUM_FLAG_CHAR;
449 else if (id == large_ident1 || id == large_ident2)
450 prefix = LARGE_FLAG_CHAR;
452 abort (); /* shouldn't happen */
456 if (TARGET_MODEL_SMALL)
457 ; /* don't mark the symbol specially */
458 else if (TARGET_MODEL_MEDIUM)
459 prefix = MEDIUM_FLAG_CHAR;
460 else if (TARGET_MODEL_LARGE)
461 prefix = LARGE_FLAG_CHAR;
463 abort (); /* shouldn't happen */
469 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd'
470 ? TREE_CST_RTL (decl) : DECL_RTL (decl));
471 const char *str = XSTR (XEXP (rtl, 0), 0);
472 int len = strlen (str);
473 char *newstr = ggc_alloc (len + 2);
475 strcpy (newstr + 1, str);
477 /* Note - we cannot leave the string in the ggc_alloc'ed space.
478 It must reside in the stringtable's domain. */
479 newstr = (char *) ggc_alloc_string (newstr, len + 2);
481 XSTR (XEXP (rtl, 0), 0) = newstr;
485 /* Do anything needed before RTL is emitted for each function. */
488 m32r_init_expanders ()
490 /* ??? At one point there was code here. The function is left in
491 to make it easy to experiment. */
494 /* Acceptable arguments to the call insn. */
497 call_address_operand (op, mode)
499 enum machine_mode mode;
501 return symbolic_operand (op, mode);
503 /* Constants and values in registers are not OK, because
504 the m32r BL instruction can only support PC relative branching. */
508 call_operand (op, mode)
510 enum machine_mode mode;
512 if (GET_CODE (op) != MEM)
515 return call_address_operand (op, mode);
518 /* Returns 1 if OP is a symbol reference. */
521 symbolic_operand (op, mode)
523 enum machine_mode mode ATTRIBUTE_UNUSED;
525 switch (GET_CODE (op))
537 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */
540 small_data_operand (op, mode)
542 enum machine_mode mode ATTRIBUTE_UNUSED;
544 if (! TARGET_SDATA_USE)
547 if (GET_CODE (op) == SYMBOL_REF)
548 return SDATA_NAME_P (XSTR (op, 0));
550 if (GET_CODE (op) == CONST
551 && GET_CODE (XEXP (op, 0)) == PLUS
552 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
553 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
554 && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
555 return SDATA_NAME_P (XSTR (XEXP (XEXP (op, 0), 0), 0));
560 /* Return 1 if OP is a symbol that can use 24 bit addressing. */
563 addr24_operand (op, mode)
565 enum machine_mode mode ATTRIBUTE_UNUSED;
567 if (GET_CODE (op) == LABEL_REF)
568 return TARGET_ADDR24;
570 if (GET_CODE (op) == SYMBOL_REF)
571 return (SMALL_NAME_P (XSTR (op, 0))
573 && (CONSTANT_POOL_ADDRESS_P (op)
574 || LIT_NAME_P (XSTR (op, 0)))));
576 if (GET_CODE (op) == CONST
577 && GET_CODE (XEXP (op, 0)) == PLUS
578 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
579 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
580 && UINT24_P (INTVAL (XEXP (XEXP (op, 0), 1))))
582 rtx sym = XEXP (XEXP (op, 0), 0);
583 return (SMALL_NAME_P (XSTR (sym, 0))
585 && (CONSTANT_POOL_ADDRESS_P (op)
586 || LIT_NAME_P (XSTR (op, 0)))));
592 /* Return 1 if OP is a symbol that needs 32 bit addressing. */
595 addr32_operand (op, mode)
597 enum machine_mode mode;
599 if (GET_CODE (op) == LABEL_REF)
600 return TARGET_ADDR32;
602 if (GET_CODE (op) == SYMBOL_REF)
603 return (! addr24_operand (op, mode)
604 && ! small_data_operand (op, mode));
606 if (GET_CODE (op) == CONST
607 && GET_CODE (XEXP (op, 0)) == PLUS
608 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
609 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
611 return (! addr24_operand (op, mode)
612 && ! small_data_operand (op, mode));
618 /* Return 1 if OP is a function that can be called with the `bl' insn. */
621 call26_operand (op, mode)
623 enum machine_mode mode ATTRIBUTE_UNUSED;
625 if (GET_CODE (op) == SYMBOL_REF)
626 return ! LARGE_NAME_P (XSTR (op, 0));
628 return TARGET_CALL26;
631 /* Returns 1 if OP is an acceptable operand for seth/add3. */
634 seth_add3_operand (op, mode)
636 enum machine_mode mode ATTRIBUTE_UNUSED;
638 if (GET_CODE (op) == SYMBOL_REF
639 || GET_CODE (op) == LABEL_REF)
642 if (GET_CODE (op) == CONST
643 && GET_CODE (XEXP (op, 0)) == PLUS
644 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
645 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
646 && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
652 /* Return true if OP is a signed 8 bit immediate value. */
655 int8_operand (op, mode)
657 enum machine_mode mode ATTRIBUTE_UNUSED;
659 if (GET_CODE (op) != CONST_INT)
661 return INT8_P (INTVAL (op));
664 /* Return true if OP is a signed 16 bit immediate value
665 useful in comparisons. */
668 cmp_int16_operand (op, mode)
670 enum machine_mode mode ATTRIBUTE_UNUSED;
672 if (GET_CODE (op) != CONST_INT)
674 return CMP_INT16_P (INTVAL (op));
677 /* Return true if OP is an unsigned 16 bit immediate value. */
680 uint16_operand (op, mode)
682 enum machine_mode mode ATTRIBUTE_UNUSED;
684 if (GET_CODE (op) != CONST_INT)
686 return UINT16_P (INTVAL (op));
689 /* Return true if OP is a register or signed 16 bit value. */
692 reg_or_int16_operand (op, mode)
694 enum machine_mode mode;
696 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
697 return register_operand (op, mode);
698 if (GET_CODE (op) != CONST_INT)
700 return INT16_P (INTVAL (op));
703 /* Return true if OP is a register or an unsigned 16 bit value. */
706 reg_or_uint16_operand (op, mode)
708 enum machine_mode mode;
710 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
711 return register_operand (op, mode);
712 if (GET_CODE (op) != CONST_INT)
714 return UINT16_P (INTVAL (op));
717 /* Return true if OP is a register or an integer value that can be
718 used is SEQ/SNE. We can use either XOR of the value or ADD of
719 the negative of the value for the constant. Don't allow 0,
720 because that is special cased. */
723 reg_or_eq_int16_operand (op, mode)
725 enum machine_mode mode;
729 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
730 return register_operand (op, mode);
732 if (GET_CODE (op) != CONST_INT)
736 return (value != 0) && (UINT16_P (value) || CMP_INT16_P (-value));
739 /* Return true if OP is a register or signed 16 bit value for compares. */
742 reg_or_cmp_int16_operand (op, mode)
744 enum machine_mode mode;
746 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
747 return register_operand (op, mode);
748 if (GET_CODE (op) != CONST_INT)
750 return CMP_INT16_P (INTVAL (op));
753 /* Return true if OP is a register or the constant 0. */
756 reg_or_zero_operand (op, mode)
758 enum machine_mode mode;
760 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
761 return register_operand (op, mode);
763 if (GET_CODE (op) != CONST_INT)
766 return INTVAL (op) == 0;
769 /* Return true if OP is a const_int requiring two instructions to load. */
772 two_insn_const_operand (op, mode)
774 enum machine_mode mode ATTRIBUTE_UNUSED;
776 if (GET_CODE (op) != CONST_INT)
778 if (INT16_P (INTVAL (op))
779 || UINT24_P (INTVAL (op))
780 || UPPER16_P (INTVAL (op)))
785 /* Return true if OP is an acceptable argument for a single word
789 move_src_operand (op, mode)
791 enum machine_mode mode;
793 switch (GET_CODE (op))
797 return addr24_operand (op, mode);
799 /* ??? We allow more cse opportunities if we only allow constants
800 loadable with one insn, and split the rest into two. The instances
801 where this would help should be rare and the current way is
803 if (HOST_BITS_PER_WIDE_INT > 32)
805 HOST_WIDE_INT rest = INTVAL (op) >> 31;
806 return (rest == 0 || rest == -1);
811 return TARGET_ADDR24;
815 else if (mode == SImode)
817 /* Large unsigned constants are represented as const_double's. */
818 unsigned HOST_WIDE_INT low, high;
820 low = CONST_DOUBLE_LOW (op);
821 high = CONST_DOUBLE_HIGH (op);
822 return high == 0 && low <= 0xffffffff;
827 return register_operand (op, mode);
829 /* (subreg (mem ...) ...) can occur here if the inner part was once a
830 pseudo-reg and is now a stack slot. */
831 if (GET_CODE (SUBREG_REG (op)) == MEM)
832 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
834 return register_operand (op, mode);
836 if (GET_CODE (XEXP (op, 0)) == PRE_INC
837 || GET_CODE (XEXP (op, 0)) == PRE_DEC)
838 return 0; /* loads can't do pre-{inc,dec} */
839 return address_operand (XEXP (op, 0), mode);
845 /* Return true if OP is an acceptable argument for a double word
849 move_double_src_operand (op, mode)
851 enum machine_mode mode;
853 switch (GET_CODE (op))
859 return register_operand (op, mode);
861 /* (subreg (mem ...) ...) can occur here if the inner part was once a
862 pseudo-reg and is now a stack slot. */
863 if (GET_CODE (SUBREG_REG (op)) == MEM)
864 return move_double_src_operand (SUBREG_REG (op), mode);
866 return register_operand (op, mode);
868 /* Disallow auto inc/dec for now. */
869 if (GET_CODE (XEXP (op, 0)) == PRE_DEC
870 || GET_CODE (XEXP (op, 0)) == PRE_INC)
872 return address_operand (XEXP (op, 0), mode);
878 /* Return true if OP is an acceptable argument for a move destination. */
881 move_dest_operand (op, mode)
883 enum machine_mode mode;
885 switch (GET_CODE (op))
888 return register_operand (op, mode);
890 /* (subreg (mem ...) ...) can occur here if the inner part was once a
891 pseudo-reg and is now a stack slot. */
892 if (GET_CODE (SUBREG_REG (op)) == MEM)
893 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
895 return register_operand (op, mode);
897 if (GET_CODE (XEXP (op, 0)) == POST_INC)
898 return 0; /* stores can't do post inc */
899 return address_operand (XEXP (op, 0), mode);
905 /* Return 1 if OP is a DImode const we want to handle inline.
906 This must match the code in the movdi pattern.
907 It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER. */
913 rtx high_rtx, low_rtx;
914 HOST_WIDE_INT high, low;
916 split_double (op, &high_rtx, &low_rtx);
917 high = INTVAL (high_rtx);
918 low = INTVAL (low_rtx);
919 /* Pick constants loadable with 2 16 bit `ldi' insns. */
920 if (high >= -128 && high <= 127
921 && low >= -128 && low <= 127)
926 /* Return 1 if OP is a DFmode const we want to handle inline.
927 This must match the code in the movdf pattern.
928 It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER. */
937 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
938 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
939 if (l[0] == 0 && l[1] == 0)
941 if ((l[0] & 0xffff) == 0 && l[1] == 0)
946 /* Return 1 if OP is an EQ or NE comparison operator. */
949 eqne_comparison_operator (op, mode)
951 enum machine_mode mode ATTRIBUTE_UNUSED;
953 enum rtx_code code = GET_CODE (op);
955 if (GET_RTX_CLASS (code) != '<')
957 return (code == EQ || code == NE);
960 /* Return 1 if OP is a signed comparison operator. */
963 signed_comparison_operator (op, mode)
965 enum machine_mode mode ATTRIBUTE_UNUSED;
967 enum rtx_code code = GET_CODE (op);
969 if (GET_RTX_CLASS (code) != '<')
971 return (code == EQ || code == NE
972 || code == LT || code == LE || code == GT || code == GE);
975 /* Return 1 if OP is (mem (reg ...)).
976 This is used in insn length calcs. */
979 memreg_operand (op, mode)
981 enum machine_mode mode ATTRIBUTE_UNUSED;
983 return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == REG;
986 /* Return true if OP is an acceptable input argument for a zero/sign extend
990 extend_operand (op, mode)
992 enum machine_mode mode;
996 switch (GET_CODE (op))
1000 return register_operand (op, mode);
1003 addr = XEXP (op, 0);
1004 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
1005 return 0; /* loads can't do pre inc/pre dec */
1007 return address_operand (addr, mode);
1014 /* Return non-zero if the operand is an insn that is a small insn.
1015 Allow const_int 0 as well, which is a placeholder for NOP slots. */
1018 small_insn_p (op, mode)
1020 enum machine_mode mode ATTRIBUTE_UNUSED;
1022 if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
1028 return get_attr_length (op) == 2;
1031 /* Return non-zero if the operand is an insn that is a large insn. */
1034 large_insn_p (op, mode)
1036 enum machine_mode mode ATTRIBUTE_UNUSED;
1041 return get_attr_length (op) != 2;
1047 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1048 return the mode to be used for the comparison. */
1051 m32r_select_cc_mode (op, x, y)
1052 int op ATTRIBUTE_UNUSED;
1053 rtx x ATTRIBUTE_UNUSED;
1054 rtx y ATTRIBUTE_UNUSED;
1056 return (int) CCmode;
1059 /* X and Y are two things to compare using CODE. Emit the compare insn and
1060 return the rtx for compare [arg0 of the if_then_else].
1061 If need_compare is true then the comparison insn must be generated, rather
1062 than being susummed into the following branch instruction. */
1065 gen_compare (code, x, y, need_compare)
1070 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
1071 enum rtx_code compare_code, branch_code;
1072 rtx cc_reg = gen_rtx_REG (mode, CARRY_REGNUM);
1077 case EQ: compare_code = EQ; branch_code = NE; break;
1078 case NE: compare_code = EQ; branch_code = EQ; break;
1079 case LT: compare_code = LT; branch_code = NE; break;
1080 case LE: compare_code = LT; branch_code = EQ; must_swap = 1; break;
1081 case GT: compare_code = LT; branch_code = NE; must_swap = 1; break;
1082 case GE: compare_code = LT; branch_code = EQ; break;
1083 case LTU: compare_code = LTU; branch_code = NE; break;
1084 case LEU: compare_code = LTU; branch_code = EQ; must_swap = 1; break;
1085 case GTU: compare_code = LTU; branch_code = NE; must_swap = 1; break;
1086 case GEU: compare_code = LTU; branch_code = EQ; break;
1094 switch (compare_code)
1097 if (GET_CODE (y) == CONST_INT
1098 && CMP_INT16_P (INTVAL (y)) /* reg equal to small const. */
1101 rtx tmp = gen_reg_rtx (SImode);
1103 emit_insn (gen_cmp_ne_small_const_insn (tmp, x, y));
1107 else if (CONSTANT_P (y)) /* reg equal to const. */
1109 rtx tmp = force_reg (GET_MODE (x), y);
1113 if (register_operand (y, SImode) /* reg equal to reg. */
1114 || y == const0_rtx) /* req equal to zero. */
1116 emit_insn (gen_cmp_eqsi_insn (x, y));
1118 return gen_rtx (code, mode, cc_reg, const0_rtx);
1123 if (register_operand (y, SImode)
1124 || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
1126 rtx tmp = gen_reg_rtx (SImode); /* reg compared to reg. */
1131 emit_insn (gen_cmp_ltsi_insn (x, y));
1135 if (y == const0_rtx)
1138 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1139 emit_insn (gen_cmp_ltsi_insn (x, tmp));
1143 if (GET_CODE (y) == CONST_INT)
1144 tmp = gen_rtx (PLUS, SImode, y, const1_rtx);
1146 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1147 emit_insn (gen_cmp_ltsi_insn (x, tmp));
1151 emit_insn (gen_cmp_ltsi_insn (x, y));
1158 return gen_rtx (code, mode, cc_reg, const0_rtx);
1163 if (register_operand (y, SImode)
1164 || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
1166 rtx tmp = gen_reg_rtx (SImode); /* reg (unsigned) compared to reg. */
1171 emit_insn (gen_cmp_ltusi_insn (x, y));
1175 if (y == const0_rtx)
1178 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1179 emit_insn (gen_cmp_ltusi_insn (x, tmp));
1183 if (GET_CODE (y) == CONST_INT)
1184 tmp = gen_rtx (PLUS, SImode, y, const1_rtx);
1186 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1187 emit_insn (gen_cmp_ltusi_insn (x, tmp));
1191 emit_insn (gen_cmp_ltusi_insn (x, y));
1198 return gen_rtx (code, mode, cc_reg, const0_rtx);
1208 /* reg/reg equal comparison */
1209 if (compare_code == EQ
1210 && register_operand (y, SImode))
1211 return gen_rtx (code, mode, x, y);
1213 /* reg/zero signed comparison */
1214 if ((compare_code == EQ || compare_code == LT)
1216 return gen_rtx (code, mode, x, y);
1218 /* reg/smallconst equal comparison */
1219 if (compare_code == EQ
1220 && GET_CODE (y) == CONST_INT
1221 && CMP_INT16_P (INTVAL (y)))
1223 rtx tmp = gen_reg_rtx (SImode);
1224 emit_insn (gen_cmp_ne_small_const_insn (tmp, x, y));
1225 return gen_rtx (code, mode, tmp, const0_rtx);
1228 /* reg/const equal comparison */
1229 if (compare_code == EQ
1232 rtx tmp = force_reg (GET_MODE (x), y);
1233 return gen_rtx (code, mode, x, tmp);
1240 y = force_reg (GET_MODE (x), y);
1244 (code == LTU || code == LEU || code == GTU || code == GEU)
1245 ? uint16_operand (y, GET_MODE (y))
1246 : reg_or_cmp_int16_operand (y, GET_MODE (y));
1249 y = force_reg (GET_MODE (x), y);
1253 switch (compare_code)
1256 emit_insn (gen_cmp_eqsi_insn (must_swap ? y : x, must_swap ? x : y));
1259 emit_insn (gen_cmp_ltsi_insn (must_swap ? y : x, must_swap ? x : y));
1262 emit_insn (gen_cmp_ltusi_insn (must_swap ? y : x, must_swap ? x : y));
1269 return gen_rtx (branch_code, VOIDmode, cc_reg, CONST0_RTX (mode));
1272 /* Split a 2 word move (DI or DF) into component parts. */
1275 gen_split_move_double (operands)
1278 enum machine_mode mode = GET_MODE (operands[0]);
1279 rtx dest = operands[0];
1280 rtx src = operands[1];
1283 /* We might have (SUBREG (MEM)) here, so just get rid of the
1284 subregs to make this code simpler. It is safe to call
1285 alter_subreg any time after reload. */
1286 if (GET_CODE (dest) == SUBREG)
1287 alter_subreg (&dest);
1288 if (GET_CODE (src) == SUBREG)
1289 alter_subreg (&src);
1292 if (GET_CODE (dest) == REG)
1294 int dregno = REGNO (dest);
1297 if (GET_CODE (src) == REG)
1299 int sregno = REGNO (src);
1301 int reverse = (dregno == sregno + 1);
1303 /* We normally copy the low-numbered register first. However, if
1304 the first register operand 0 is the same as the second register of
1305 operand 1, we must copy in the opposite order. */
1306 emit_insn (gen_rtx_SET (VOIDmode,
1307 operand_subword (dest, reverse, TRUE, mode),
1308 operand_subword (src, reverse, TRUE, mode)));
1310 emit_insn (gen_rtx_SET (VOIDmode,
1311 operand_subword (dest, !reverse, TRUE, mode),
1312 operand_subword (src, !reverse, TRUE, mode)));
1315 /* reg = constant */
1316 else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE)
1319 split_double (src, &words[0], &words[1]);
1320 emit_insn (gen_rtx_SET (VOIDmode,
1321 operand_subword (dest, 0, TRUE, mode),
1324 emit_insn (gen_rtx_SET (VOIDmode,
1325 operand_subword (dest, 1, TRUE, mode),
1330 else if (GET_CODE (src) == MEM)
1332 /* If the high-address word is used in the address, we must load it
1333 last. Otherwise, load it first. */
1335 = (refers_to_regno_p (dregno, dregno + 1, XEXP (src, 0), 0) != 0);
1337 /* We used to optimize loads from single registers as
1341 if r3 were not used subsequently. However, the REG_NOTES aren't
1342 propigated correctly by the reload phase, and it can cause bad
1343 code to be generated. We could still try:
1345 ld r1,r3+; ld r2,r3; addi r3,-4
1347 which saves 2 bytes and doesn't force longword alignment. */
1348 emit_insn (gen_rtx_SET (VOIDmode,
1349 operand_subword (dest, reverse, TRUE, mode),
1350 adjust_address (src, SImode,
1351 reverse * UNITS_PER_WORD)));
1353 emit_insn (gen_rtx_SET (VOIDmode,
1354 operand_subword (dest, !reverse, TRUE, mode),
1355 adjust_address (src, SImode,
1356 !reverse * UNITS_PER_WORD)));
1364 /* We used to optimize loads from single registers as
1368 if r3 were not used subsequently. However, the REG_NOTES aren't
1369 propigated correctly by the reload phase, and it can cause bad
1370 code to be generated. We could still try:
1372 st r1,r3; st r2,+r3; addi r3,-4
1374 which saves 2 bytes and doesn't force longword alignment. */
1375 else if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
1377 emit_insn (gen_rtx_SET (VOIDmode,
1378 adjust_address (dest, SImode, 0),
1379 operand_subword (src, 0, TRUE, mode)));
1381 emit_insn (gen_rtx_SET (VOIDmode,
1382 adjust_address (dest, SImode, UNITS_PER_WORD),
1383 operand_subword (src, 1, TRUE, mode)));
1389 val = gen_sequence ();
1395 /* Implements the FUNCTION_ARG_PARTIAL_NREGS macro. */
1398 function_arg_partial_nregs (cum, mode, type, named)
1399 CUMULATIVE_ARGS *cum;
1400 enum machine_mode mode;
1402 int named ATTRIBUTE_UNUSED;
1406 (((mode == BLKmode && type)
1407 ? (unsigned int) int_size_in_bytes (type)
1408 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
1411 if (*cum >= M32R_MAX_PARM_REGS)
1413 else if (*cum + size > M32R_MAX_PARM_REGS)
1414 ret = (*cum + size) - M32R_MAX_PARM_REGS;
1421 /* Do any needed setup for a variadic function. For the M32R, we must
1422 create a register parameter block, and then copy any anonymous arguments
1423 in registers to memory.
1425 CUM has not been updated for the last named argument which has type TYPE
1426 and mode MODE, and we rely on this fact. */
1429 m32r_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
1430 CUMULATIVE_ARGS *cum;
1431 enum machine_mode mode;
1441 /* All BLKmode values are passed by reference. */
1442 if (mode == BLKmode)
1445 /* We must treat `__builtin_va_alist' as an anonymous arg. */
1446 if (current_function_varargs)
1447 first_anon_arg = *cum;
1449 first_anon_arg = (ROUND_ADVANCE_CUM (*cum, mode, type)
1450 + ROUND_ADVANCE_ARG (mode, type));
1452 if (first_anon_arg < M32R_MAX_PARM_REGS)
1454 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1455 int first_reg_offset = first_anon_arg;
1456 /* Size in words to "pretend" allocate. */
1457 int size = M32R_MAX_PARM_REGS - first_reg_offset;
1460 regblock = gen_rtx_MEM (BLKmode,
1461 plus_constant (arg_pointer_rtx,
1462 FIRST_PARM_OFFSET (0)));
1463 set_mem_alias_set (regblock, get_varargs_alias_set ());
1464 move_block_from_reg (first_reg_offset, regblock,
1465 size, size * UNITS_PER_WORD);
1467 *pretend_size = (size * UNITS_PER_WORD);
1472 /* Implement `va_arg'. */
1475 m32r_va_arg (valist, type)
1478 HOST_WIDE_INT size, rsize;
1482 size = int_size_in_bytes (type);
1483 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
1487 tree type_ptr, type_ptr_ptr;
1489 /* Pass by reference. */
1491 type_ptr = build_pointer_type (type);
1492 type_ptr_ptr = build_pointer_type (type_ptr);
1494 t = build (POSTINCREMENT_EXPR, va_list_type_node, valist,
1495 build_int_2 (UNITS_PER_WORD, 0));
1496 TREE_SIDE_EFFECTS (t) = 1;
1497 t = build1 (NOP_EXPR, type_ptr_ptr, t);
1498 TREE_SIDE_EFFECTS (t) = 1;
1499 t = build1 (INDIRECT_REF, type_ptr, t);
1501 addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1505 /* Pass by value. */
1507 if (size < UNITS_PER_WORD)
1509 /* Care for bigendian correction on the aligned address. */
1510 t = build (PLUS_EXPR, ptr_type_node, valist,
1511 build_int_2 (rsize - size, 0));
1512 addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1513 addr_rtx = copy_to_reg (addr_rtx);
1516 t = build (PLUS_EXPR, va_list_type_node, valist,
1517 build_int_2 (rsize, 0));
1518 t = build (MODIFY_EXPR, va_list_type_node, valist, t);
1519 TREE_SIDE_EFFECTS (t) = 1;
1520 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
1524 t = build (POSTINCREMENT_EXPR, va_list_type_node, valist,
1525 build_int_2 (rsize, 0));
1526 TREE_SIDE_EFFECTS (t) = 1;
1527 addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1535 m32r_adjust_cost (insn, link, dep_insn, cost)
1536 rtx insn ATTRIBUTE_UNUSED;
1537 rtx link ATTRIBUTE_UNUSED;
1538 rtx dep_insn ATTRIBUTE_UNUSED;
1545 /* Return true if INSN is real instruction bearing insn. */
1551 return (INSN_P (insn)
1552 && GET_CODE (PATTERN (insn)) != USE
1553 && GET_CODE (PATTERN (insn)) != CLOBBER
1554 && GET_CODE (PATTERN (insn)) != ADDR_VEC);
1557 /* Increase the priority of long instructions so that the
1558 short instructions are scheduled ahead of the long ones. */
1561 m32r_adjust_priority (insn, priority)
1565 if (m32r_is_insn (insn)
1566 && get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1573 /* Initialize for scheduling a group of instructions. */
1576 m32r_sched_init (stream, verbose, max_ready)
1577 FILE * stream ATTRIBUTE_UNUSED;
1578 int verbose ATTRIBUTE_UNUSED;
1579 int max_ready ATTRIBUTE_UNUSED;
1581 m32r_sched_odd_word_p = FALSE;
1585 /* Reorder the schedulers priority list if needed */
1588 m32r_sched_reorder (stream, verbose, ready, n_readyp, clock)
1593 int clock ATTRIBUTE_UNUSED;
1595 int n_ready = *n_readyp;
1598 return m32r_issue_rate ();
1605 ";;\t\t::: Looking at %d insn(s) on ready list, boundary is %s word\n",
1607 (m32r_sched_odd_word_p) ? "odd" : "even");
1611 rtx * long_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1612 rtx * long_tail = long_head;
1613 rtx * short_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1614 rtx * short_tail = short_head;
1615 rtx * new_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1616 rtx * new_tail = new_head + (n_ready - 1);
1619 /* Loop through the instructions, classifing them as short/long. Try
1620 to keep 2 short together and/or 1 long. Note, the ready list is
1621 actually ordered backwards, so keep it in that manner. */
1622 for (i = n_ready-1; i >= 0; i--)
1624 rtx insn = ready[i];
1626 if (! m32r_is_insn (insn))
1628 /* Dump all current short/long insns just in case. */
1629 while (long_head != long_tail)
1630 *new_tail-- = *long_head++;
1632 while (short_head != short_tail)
1633 *new_tail-- = *short_head++;
1638 ";;\t\t::: Skipping non instruction %d\n",
1645 if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1646 *long_tail++ = insn;
1649 *short_tail++ = insn;
1653 /* If we are on an odd word, emit a single short instruction if
1655 if (m32r_sched_odd_word_p && short_head != short_tail)
1656 *new_tail-- = *short_head++;
1658 /* Now dump out all of the long instructions */
1659 while (long_head != long_tail)
1660 *new_tail-- = *long_head++;
1662 /* Now dump out all of the short instructions */
1663 while (short_head != short_tail)
1664 *new_tail-- = *short_head++;
1666 if (new_tail+1 != new_head)
1669 memcpy (ready, new_head, sizeof (rtx) * n_ready);
1673 fprintf (stream, ";;\t\t::: New ready list: ");
1674 for (i = 0; i < n_ready; i++)
1676 rtx insn = ready[i];
1678 fprintf (stream, " %d", INSN_UID (ready[i]));
1680 if (! m32r_is_insn (insn))
1681 fputs ("(?)", stream);
1683 else if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1684 fputs ("(l)", stream);
1687 fputs ("(s)", stream);
1690 fprintf (stream, "\n");
1693 return m32r_issue_rate ();
1696 /* Indicate how many instructions can be issued at the same time.
1697 This is sort of a lie. The m32r can issue only 1 long insn at
1698 once, but it can issue 2 short insns. The default therefore is
1699 set at 2, but this can be overridden by the command line option
1704 return ((TARGET_LOW_ISSUE_RATE) ? 1 : 2);
1707 /* If we have a machine that can issue a variable # of instructions
1708 per cycle, indicate how many more instructions can be issued
1709 after the current one. */
1711 m32r_variable_issue (stream, verbose, insn, how_many)
1717 int orig_odd_word_p = m32r_sched_odd_word_p;
1718 int short_p = FALSE;
1721 if (how_many > 0 && !TARGET_DEBUG)
1723 if (! m32r_is_insn (insn))
1726 else if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1729 m32r_sched_odd_word_p = 0;
1733 m32r_sched_odd_word_p = !m32r_sched_odd_word_p;
1738 if (verbose > 7 && stream)
1740 ";;\t\t::: %s insn %d starts on an %s word, can emit %d more instruction(s)\n",
1741 short_p ? "short" : "long",
1743 orig_odd_word_p ? "odd" : "even",
1749 /* Cost functions. */
1751 /* Provide the costs of an addressing mode that contains ADDR.
1752 If ADDR is not a valid address, its cost is irrelevant.
1754 This function is trivial at the moment. This code doesn't live
1755 in m32r.h so it's easy to experiment. */
1758 m32r_address_cost (addr)
1759 rtx addr ATTRIBUTE_UNUSED;
1764 /* Type of function DECL.
1766 The result is cached. To reset the cache at the end of a function,
1767 call with DECL = NULL_TREE. */
1769 enum m32r_function_type
1770 m32r_compute_function_type (decl)
1774 static enum m32r_function_type fn_type = M32R_FUNCTION_UNKNOWN;
1775 /* Last function we were called for. */
1776 static tree last_fn = NULL_TREE;
1778 /* Resetting the cached value? */
1779 if (decl == NULL_TREE)
1781 fn_type = M32R_FUNCTION_UNKNOWN;
1782 last_fn = NULL_TREE;
1786 if (decl == last_fn && fn_type != M32R_FUNCTION_UNKNOWN)
1789 /* Compute function type. */
1790 fn_type = (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE
1791 ? M32R_FUNCTION_INTERRUPT
1792 : M32R_FUNCTION_NORMAL);
1797 \f/* Function prologue/epilogue handlers. */
1799 /* M32R stack frames look like:
1801 Before call After call
1802 +-----------------------+ +-----------------------+
1804 high | local variables, | | local variables, |
1805 mem | reg save area, etc. | | reg save area, etc. |
1807 +-----------------------+ +-----------------------+
1809 | arguments on stack. | | arguments on stack. |
1811 SP+0->+-----------------------+ +-----------------------+
1812 | reg parm save area, |
1813 | only created for |
1814 | variable argument |
1816 +-----------------------+
1817 | previous frame ptr |
1818 +-----------------------+
1820 | register save area |
1822 +-----------------------+
1824 +-----------------------+
1828 +-----------------------+
1830 | alloca allocations |
1832 +-----------------------+
1834 low | arguments on stack |
1836 SP+0->+-----------------------+
1839 1) The "reg parm save area" does not exist for non variable argument fns.
1840 2) The "reg parm save area" can be eliminated completely if we saved regs
1841 containing anonymous args separately but that complicates things too
1842 much (so it's not done).
1843 3) The return address is saved after the register save area so as to have as
1844 many insns as possible between the restoration of `lr' and the `jmp lr'.
1847 /* Structure to be filled in by m32r_compute_frame_size with register
1848 save masks, and offsets for the current function. */
1849 struct m32r_frame_info
1851 unsigned int total_size; /* # bytes that the entire frame takes up */
1852 unsigned int extra_size; /* # bytes of extra stuff */
1853 unsigned int pretend_size; /* # bytes we push and pretend caller did */
1854 unsigned int args_size; /* # bytes that outgoing arguments take up */
1855 unsigned int reg_size; /* # bytes needed to store regs */
1856 unsigned int var_size; /* # bytes that variables take up */
1857 unsigned int gmask; /* mask of saved gp registers */
1858 unsigned int save_fp; /* nonzero if fp must be saved */
1859 unsigned int save_lr; /* nonzero if lr (return addr) must be saved */
1860 int initialized; /* nonzero if frame size already calculated */
1863 /* Current frame information calculated by m32r_compute_frame_size. */
1864 static struct m32r_frame_info current_frame_info;
1866 /* Zero structure to initialize current_frame_info. */
1867 static struct m32r_frame_info zero_frame_info;
1869 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1870 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1872 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1873 The return address and frame pointer are treated separately.
1874 Don't consider them here. */
1875 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1876 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1877 && (regs_ever_live[regno] && (!call_used_regs[regno] || interrupt_p)))
1879 #define MUST_SAVE_FRAME_POINTER (regs_ever_live[FRAME_POINTER_REGNUM])
1880 #define MUST_SAVE_RETURN_ADDR (regs_ever_live[RETURN_ADDR_REGNUM] || current_function_profile)
1882 #define SHORT_INSN_SIZE 2 /* size of small instructions */
1883 #define LONG_INSN_SIZE 4 /* size of long instructions */
1885 /* Return the bytes needed to compute the frame pointer from the current
1888 SIZE is the size needed for local variables. */
1891 m32r_compute_frame_size (size)
1892 int size; /* # of var. bytes allocated. */
1895 unsigned int total_size, var_size, args_size, pretend_size, extra_size;
1896 unsigned int reg_size, frame_size;
1898 enum m32r_function_type fn_type;
1901 var_size = M32R_STACK_ALIGN (size);
1902 args_size = M32R_STACK_ALIGN (current_function_outgoing_args_size);
1903 pretend_size = current_function_pretend_args_size;
1904 extra_size = FIRST_PARM_OFFSET (0);
1905 total_size = extra_size + pretend_size + args_size + var_size;
1909 /* See if this is an interrupt handler. Call used registers must be saved
1911 fn_type = m32r_compute_function_type (current_function_decl);
1912 interrupt_p = M32R_INTERRUPT_P (fn_type);
1914 /* Calculate space needed for registers. */
1916 for (regno = 0; regno < M32R_MAX_INT_REGS; regno++)
1918 if (MUST_SAVE_REGISTER (regno, interrupt_p))
1920 reg_size += UNITS_PER_WORD;
1921 gmask |= 1 << regno;
1925 current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER;
1926 current_frame_info.save_lr = MUST_SAVE_RETURN_ADDR;
1928 reg_size += ((current_frame_info.save_fp + current_frame_info.save_lr)
1930 total_size += reg_size;
1932 /* ??? Not sure this is necessary, and I don't think the epilogue
1933 handler will do the right thing if this changes total_size. */
1934 total_size = M32R_STACK_ALIGN (total_size);
1936 frame_size = total_size - (pretend_size + reg_size);
1938 /* Save computed information. */
1939 current_frame_info.total_size = total_size;
1940 current_frame_info.extra_size = extra_size;
1941 current_frame_info.pretend_size = pretend_size;
1942 current_frame_info.var_size = var_size;
1943 current_frame_info.args_size = args_size;
1944 current_frame_info.reg_size = reg_size;
1945 current_frame_info.gmask = gmask;
1946 current_frame_info.initialized = reload_completed;
1948 /* Ok, we're done. */
1952 /* When the `length' insn attribute is used, this macro specifies the
1953 value to be assigned to the address of the first insn in a
1954 function. If not specified, 0 is used. */
1957 m32r_first_insn_address ()
1959 if (! current_frame_info.initialized)
1960 m32r_compute_frame_size (get_frame_size ());
1965 /* Expand the m32r prologue as a series of insns. */
1968 m32r_expand_prologue ()
1974 if (! current_frame_info.initialized)
1975 m32r_compute_frame_size (get_frame_size ());
1977 gmask = current_frame_info.gmask;
1979 /* These cases shouldn't happen. Catch them now. */
1980 if (current_frame_info.total_size == 0 && gmask)
1983 /* Allocate space for register arguments if this is a variadic function. */
1984 if (current_frame_info.pretend_size != 0)
1986 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1987 the wrong result on a 64-bit host. */
1988 HOST_WIDE_INT pretend_size = current_frame_info.pretend_size;
1989 emit_insn (gen_addsi3 (stack_pointer_rtx,
1991 GEN_INT (-pretend_size)));
1994 /* Save any registers we need to and set up fp. */
1996 if (current_frame_info.save_fp)
1997 emit_insn (gen_movsi_push (stack_pointer_rtx, frame_pointer_rtx));
1999 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
2001 /* Save any needed call-saved regs (and call-used if this is an
2002 interrupt handler). */
2003 for (regno = 0; regno <= M32R_MAX_INT_REGS; ++regno)
2005 if ((gmask & (1 << regno)) != 0)
2006 emit_insn (gen_movsi_push (stack_pointer_rtx,
2007 gen_rtx_REG (Pmode, regno)));
2010 if (current_frame_info.save_lr)
2011 emit_insn (gen_movsi_push (stack_pointer_rtx,
2012 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
2014 /* Allocate the stack frame. */
2015 frame_size = (current_frame_info.total_size
2016 - (current_frame_info.pretend_size
2017 + current_frame_info.reg_size));
2019 if (frame_size == 0)
2020 ; /* nothing to do */
2021 else if (frame_size <= 32768)
2022 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
2023 GEN_INT (-frame_size)));
2026 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
2027 emit_insn (gen_movsi (tmp, GEN_INT (frame_size)));
2028 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
2031 if (frame_pointer_needed)
2032 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
2034 if (current_function_profile)
2035 emit_insn (gen_blockage ());
2039 /* Set up the stack and frame pointer (if desired) for the function.
2040 Note, if this is changed, you need to mirror the changes in
2041 m32r_compute_frame_size which calculates the prolog size. */
2044 m32r_output_function_prologue (file, size)
2048 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
2050 /* If this is an interrupt handler, mark it as such. */
2051 if (M32R_INTERRUPT_P (fn_type))
2053 fprintf (file, "\t%s interrupt handler\n",
2057 if (! current_frame_info.initialized)
2058 m32r_compute_frame_size (size);
2060 /* This is only for the human reader. */
2062 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
2064 current_frame_info.var_size,
2065 current_frame_info.reg_size / 4,
2066 current_frame_info.args_size,
2067 current_frame_info.extra_size);
2070 /* Do any necessary cleanup after a function to restore stack, frame,
2074 m32r_output_function_epilogue (file, size)
2076 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
2079 int noepilogue = FALSE;
2081 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
2083 /* This is only for the human reader. */
2084 fprintf (file, "\t%s EPILOGUE\n", ASM_COMMENT_START);
2086 if (!current_frame_info.initialized)
2088 total_size = current_frame_info.total_size;
2090 if (total_size == 0)
2092 rtx insn = get_last_insn ();
2094 /* If the last insn was a BARRIER, we don't have to write any code
2095 because a jump (aka return) was put there. */
2096 if (GET_CODE (insn) == NOTE)
2097 insn = prev_nonnote_insn (insn);
2098 if (insn && GET_CODE (insn) == BARRIER)
2104 unsigned int var_size = current_frame_info.var_size;
2105 unsigned int args_size = current_frame_info.args_size;
2106 unsigned int gmask = current_frame_info.gmask;
2107 int can_trust_sp_p = !current_function_calls_alloca;
2108 const char * sp_str = reg_names[STACK_POINTER_REGNUM];
2109 const char * fp_str = reg_names[FRAME_POINTER_REGNUM];
2111 /* The first thing to do is point the sp at the bottom of the register
2115 unsigned int reg_offset = var_size + args_size;
2116 if (reg_offset == 0)
2117 ; /* nothing to do */
2118 else if (reg_offset < 128)
2119 fprintf (file, "\taddi %s,%s%d\n",
2120 sp_str, IMMEDIATE_PREFIX, reg_offset);
2121 else if (reg_offset < 32768)
2122 fprintf (file, "\tadd3 %s,%s,%s%d\n",
2123 sp_str, sp_str, IMMEDIATE_PREFIX, reg_offset);
2125 fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
2126 reg_names[PROLOGUE_TMP_REGNUM],
2127 IMMEDIATE_PREFIX, reg_offset,
2128 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
2130 else if (frame_pointer_needed)
2132 unsigned int reg_offset = var_size + args_size;
2133 if (reg_offset == 0)
2134 fprintf (file, "\tmv %s,%s\n", sp_str, fp_str);
2135 else if (reg_offset < 32768)
2136 fprintf (file, "\tadd3 %s,%s,%s%d\n",
2137 sp_str, fp_str, IMMEDIATE_PREFIX, reg_offset);
2139 fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
2140 reg_names[PROLOGUE_TMP_REGNUM],
2141 IMMEDIATE_PREFIX, reg_offset,
2142 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
2147 if (current_frame_info.save_lr)
2148 fprintf (file, "\tpop %s\n", reg_names[RETURN_ADDR_REGNUM]);
2150 /* Restore any saved registers, in reverse order of course. */
2151 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
2152 for (regno = M32R_MAX_INT_REGS - 1; regno >= 0; --regno)
2154 if ((gmask & (1L << regno)) != 0)
2155 fprintf (file, "\tpop %s\n", reg_names[regno]);
2158 if (current_frame_info.save_fp)
2159 fprintf (file, "\tpop %s\n", fp_str);
2161 /* Remove varargs area if present. */
2162 if (current_frame_info.pretend_size != 0)
2163 fprintf (file, "\taddi %s,%s%d\n",
2164 sp_str, IMMEDIATE_PREFIX, current_frame_info.pretend_size);
2166 /* Emit the return instruction. */
2167 if (M32R_INTERRUPT_P (fn_type))
2168 fprintf (file, "\trte\n");
2170 fprintf (file, "\tjmp %s\n", reg_names[RETURN_ADDR_REGNUM]);
2173 #if 0 /* no longer needed */
2174 /* Ensure the function cleanly ends on a 32 bit boundary. */
2175 fprintf (file, "\t.fillinsn\n");
2178 /* Reset state info for each function. */
2179 current_frame_info = zero_frame_info;
2180 m32r_compute_function_type (NULL_TREE);
2183 /* Return non-zero if this function is known to have a null or 1 instruction
2189 if (!reload_completed)
2192 if (! current_frame_info.initialized)
2193 m32r_compute_frame_size (get_frame_size ());
2195 return current_frame_info.total_size == 0;
2201 /* Emit special PIC prologues and epilogues. */
2204 m32r_finalize_pic ()
2209 /* Nested function support. */
2211 /* Emit RTL insns to initialize the variable parts of a trampoline.
2212 FNADDR is an RTX for the address of the function's pure code.
2213 CXT is an RTX for the static chain value for the function. */
2216 m32r_initialize_trampoline (tramp, fnaddr, cxt)
2217 rtx tramp ATTRIBUTE_UNUSED;
2218 rtx fnaddr ATTRIBUTE_UNUSED;
2219 rtx cxt ATTRIBUTE_UNUSED;
2223 /* Set the cpu type and print out other fancy things,
2224 at the top of the file. */
2227 m32r_asm_file_start (file)
2230 if (flag_verbose_asm)
2231 fprintf (file, "%s M32R/D special options: -G %d\n",
2232 ASM_COMMENT_START, g_switch_value);
2235 /* Print operand X (an rtx) in assembler syntax to file FILE.
2236 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2237 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2240 m32r_print_operand (file, x, code)
2249 /* The 's' and 'p' codes are used by output_block_move() to
2250 indicate post-increment 's'tores and 'p're-increment loads. */
2252 if (GET_CODE (x) == REG)
2253 fprintf (file, "@+%s", reg_names [REGNO (x)]);
2255 output_operand_lossage ("invalid operand to %%s code");
2259 if (GET_CODE (x) == REG)
2260 fprintf (file, "@%s+", reg_names [REGNO (x)]);
2262 output_operand_lossage ("invalid operand to %%p code");
2266 /* Write second word of DImode or DFmode reference,
2267 register or memory. */
2268 if (GET_CODE (x) == REG)
2269 fputs (reg_names[REGNO (x)+1], file);
2270 else if (GET_CODE (x) == MEM)
2272 fprintf (file, "@(");
2273 /* Handle possible auto-increment. Since it is pre-increment and
2274 we have already done it, we can just use an offset of four. */
2275 /* ??? This is taken from rs6000.c I think. I don't think it is
2276 currently necessary, but keep it around. */
2277 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2278 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2279 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
2281 output_address (plus_constant (XEXP (x, 0), 4));
2285 output_operand_lossage ("invalid operand to %%R code");
2288 case 'H' : /* High word */
2289 case 'L' : /* Low word */
2290 if (GET_CODE (x) == REG)
2292 /* L = least significant word, H = most significant word */
2293 if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L'))
2294 fputs (reg_names[REGNO (x)], file);
2296 fputs (reg_names[REGNO (x)+1], file);
2298 else if (GET_CODE (x) == CONST_INT
2299 || GET_CODE (x) == CONST_DOUBLE)
2303 split_double (x, &first, &second);
2304 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2305 code == 'L' ? INTVAL (first) : INTVAL (second));
2308 output_operand_lossage ("invalid operand to %%H/%%L code");
2316 if (GET_CODE (x) != CONST_DOUBLE
2317 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
2318 fatal_insn ("bad insn for 'A'", x);
2319 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
2320 REAL_VALUE_TO_DECIMAL (d, "%.20e", str);
2321 fprintf (file, "%s", str);
2325 case 'B' : /* Bottom half */
2326 case 'T' : /* Top half */
2327 /* Output the argument to a `seth' insn (sets the Top half-word).
2328 For constants output arguments to a seth/or3 pair to set Top and
2329 Bottom halves. For symbols output arguments to a seth/add3 pair to
2330 set Top and Bottom halves. The difference exists because for
2331 constants seth/or3 is more readable but for symbols we need to use
2332 the same scheme as `ld' and `st' insns (16 bit addend is signed). */
2333 switch (GET_CODE (x))
2340 split_double (x, &first, &second);
2341 x = WORDS_BIG_ENDIAN ? second : first;
2343 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
2349 ? INTVAL (x) & 0xffff
2350 : (INTVAL (x) >> 16) & 0xffff));
2356 && small_data_operand (x, VOIDmode))
2358 fputs ("sda(", file);
2359 output_addr_const (file, x);
2365 fputs (code == 'T' ? "shigh(" : "low(", file);
2366 output_addr_const (file, x);
2370 output_operand_lossage ("invalid operand to %%T/%%B code");
2377 /* Output a load/store with update indicator if appropriate. */
2378 if (GET_CODE (x) == MEM)
2380 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2381 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2385 output_operand_lossage ("invalid operand to %%U code");
2389 /* Print a constant value negated. */
2390 if (GET_CODE (x) == CONST_INT)
2391 output_addr_const (file, GEN_INT (- INTVAL (x)));
2393 output_operand_lossage ("invalid operand to %%N code");
2397 /* Print a const_int in hex. Used in comments. */
2398 if (GET_CODE (x) == CONST_INT)
2400 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
2409 fputs (IMMEDIATE_PREFIX, file);
2412 #if 0 /* ??? no longer used */
2414 fputs (reg_names[SDA_REGNUM], file);
2419 /* Do nothing special. */
2424 output_operand_lossage ("invalid operand output code");
2427 switch (GET_CODE (x))
2430 fputs (reg_names[REGNO (x)], file);
2435 if (GET_CODE (addr) == PRE_INC)
2437 if (GET_CODE (XEXP (addr, 0)) != REG)
2438 fatal_insn ("pre-increment address is not a register", x);
2440 fprintf (file, "@+%s", reg_names[REGNO (XEXP (addr, 0))]);
2442 else if (GET_CODE (addr) == PRE_DEC)
2444 if (GET_CODE (XEXP (addr, 0)) != REG)
2445 fatal_insn ("pre-decrement address is not a register", x);
2447 fprintf (file, "@-%s", reg_names[REGNO (XEXP (addr, 0))]);
2449 else if (GET_CODE (addr) == POST_INC)
2451 if (GET_CODE (XEXP (addr, 0)) != REG)
2452 fatal_insn ("post-increment address is not a register", x);
2454 fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]);
2459 output_address (XEXP (x, 0));
2465 /* We handle SFmode constants here as output_addr_const doesn't. */
2466 if (GET_MODE (x) == SFmode)
2471 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
2472 REAL_VALUE_TO_TARGET_SINGLE (d, l);
2473 fprintf (file, "0x%08lx", l);
2477 /* Fall through. Let output_addr_const deal with it. */
2480 output_addr_const (file, x);
2485 /* Print a memory address as an operand to reference that memory location. */
2488 m32r_print_operand_address (file, addr)
2493 register rtx index = 0;
2496 switch (GET_CODE (addr))
2499 fputs (reg_names[REGNO (addr)], file);
2503 if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
2504 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
2505 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2506 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
2508 base = XEXP (addr, 0), index = XEXP (addr, 1);
2509 if (GET_CODE (base) == REG)
2511 /* Print the offset first (if present) to conform to the manual. */
2515 fprintf (file, "%d,", offset);
2516 fputs (reg_names[REGNO (base)], file);
2518 /* The chip doesn't support this, but left in for generality. */
2519 else if (GET_CODE (index) == REG)
2520 fprintf (file, "%s,%s",
2521 reg_names[REGNO (base)], reg_names[REGNO (index)]);
2522 /* Not sure this can happen, but leave in for now. */
2523 else if (GET_CODE (index) == SYMBOL_REF)
2525 output_addr_const (file, index);
2527 fputs (reg_names[REGNO (base)], file);
2530 fatal_insn ("bad address", addr);
2532 else if (GET_CODE (base) == LO_SUM)
2535 || GET_CODE (XEXP (base, 0)) != REG)
2537 if (small_data_operand (XEXP (base, 1), VOIDmode))
2538 fputs ("sda(", file);
2540 fputs ("low(", file);
2541 output_addr_const (file, plus_constant (XEXP (base, 1), offset));
2543 fputs (reg_names[REGNO (XEXP (base, 0))], file);
2546 fatal_insn ("bad address", addr);
2550 if (GET_CODE (XEXP (addr, 0)) != REG)
2551 fatal_insn ("lo_sum not of register", addr);
2552 if (small_data_operand (XEXP (addr, 1), VOIDmode))
2553 fputs ("sda(", file);
2555 fputs ("low(", file);
2556 output_addr_const (file, XEXP (addr, 1));
2558 fputs (reg_names[REGNO (XEXP (addr, 0))], file);
2561 case PRE_INC : /* Assume SImode */
2562 fprintf (file, "+%s", reg_names[REGNO (XEXP (addr, 0))]);
2565 case PRE_DEC : /* Assume SImode */
2566 fprintf (file, "-%s", reg_names[REGNO (XEXP (addr, 0))]);
2569 case POST_INC : /* Assume SImode */
2570 fprintf (file, "%s+", reg_names[REGNO (XEXP (addr, 0))]);
2574 output_addr_const (file, addr);
2579 /* Return true if the operands are the constants 0 and 1. */
2581 zero_and_one (operand1, operand2)
2586 GET_CODE (operand1) == CONST_INT
2587 && GET_CODE (operand2) == CONST_INT
2588 && ( ((INTVAL (operand1) == 0) && (INTVAL (operand2) == 1))
2589 ||((INTVAL (operand1) == 1) && (INTVAL (operand2) == 0)));
2592 /* Return non-zero if the operand is suitable for use in a conditional move sequence. */
2594 conditional_move_operand (operand, mode)
2596 enum machine_mode mode;
2598 /* Only defined for simple integers so far... */
2599 if (mode != SImode && mode != HImode && mode != QImode)
2602 /* At the moment we can hanndle moving registers and loading constants. */
2603 /* To be added: Addition/subtraction/bitops/multiplication of registers. */
2605 switch (GET_CODE (operand))
2611 return INT8_P (INTVAL (operand));
2615 fprintf (stderr, "Test for cond move op of type: %s\n",
2616 GET_RTX_NAME (GET_CODE (operand)));
2622 /* Return true if the code is a test of the carry bit */
2624 carry_compare_operand (op, mode)
2626 enum machine_mode mode ATTRIBUTE_UNUSED;
2630 if (GET_MODE (op) != CCmode && GET_MODE (op) != VOIDmode)
2633 if (GET_CODE (op) != NE && GET_CODE (op) != EQ)
2637 if (GET_CODE (x) != REG || REGNO (x) != CARRY_REGNUM)
2641 if (GET_CODE (x) != CONST_INT || INTVAL (x) != 0)
2647 /* Generate the correct assembler code to handle the conditional loading of a
2648 value into a register. It is known that the operands satisfy the
2649 conditional_move_operand() function above. The destination is operand[0].
2650 The condition is operand [1]. The 'true' value is operand [2] and the
2651 'false' value is operand [3]. */
2653 emit_cond_move (operands, insn)
2655 rtx insn ATTRIBUTE_UNUSED;
2657 static char buffer [100];
2658 const char * dest = reg_names [REGNO (operands [0])];
2662 /* Destination must be a register. */
2663 if (GET_CODE (operands [0]) != REG)
2665 if (! conditional_move_operand (operands [2], SImode))
2667 if (! conditional_move_operand (operands [3], SImode))
2670 /* Check to see if the test is reversed. */
2671 if (GET_CODE (operands [1]) == NE)
2673 rtx tmp = operands [2];
2674 operands [2] = operands [3];
2678 sprintf (buffer, "mvfc %s, cbr", dest);
2680 /* If the true value was '0' then we need to invert the results of the move. */
2681 if (INTVAL (operands [2]) == 0)
2682 sprintf (buffer + strlen (buffer), "\n\txor3 %s, %s, #1",
2688 /* Returns true if the registers contained in the two
2689 rtl expressions are different. */
2691 m32r_not_same_reg (a, b)
2698 while (GET_CODE (a) == SUBREG)
2701 if (GET_CODE (a) == REG)
2704 while (GET_CODE (b) == SUBREG)
2707 if (GET_CODE (b) == REG)
2710 return reg_a != reg_b;
2714 /* Use a library function to move some bytes. */
2716 block_move_call (dest_reg, src_reg, bytes_rtx)
2721 /* We want to pass the size as Pmode, which will normally be SImode
2722 but will be DImode if we are using 64 bit longs and pointers. */
2723 if (GET_MODE (bytes_rtx) != VOIDmode
2724 && GET_MODE (bytes_rtx) != Pmode)
2725 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
2727 #ifdef TARGET_MEM_FUNCTIONS
2728 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0,
2729 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
2730 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
2731 TREE_UNSIGNED (sizetype)),
2732 TYPE_MODE (sizetype));
2734 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "bcopy"), 0,
2735 VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
2736 convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
2737 TREE_UNSIGNED (integer_type_node)),
2738 TYPE_MODE (integer_type_node));
2742 /* The maximum number of bytes to copy using pairs of load/store instructions.
2743 If a block is larger than this then a loop will be generated to copy
2744 MAX_MOVE_BYTES chunks at a time. The value of 32 is a semi-arbitary choice.
2745 A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte
2746 string copy in it. */
2747 #define MAX_MOVE_BYTES 32
2749 /* Expand string/block move operations.
2751 operands[0] is the pointer to the destination.
2752 operands[1] is the pointer to the source.
2753 operands[2] is the number of bytes to move.
2754 operands[3] is the alignment. */
2757 m32r_expand_block_move (operands)
2760 rtx orig_dst = operands[0];
2761 rtx orig_src = operands[1];
2762 rtx bytes_rtx = operands[2];
2763 rtx align_rtx = operands[3];
2764 int constp = GET_CODE (bytes_rtx) == CONST_INT;
2765 HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
2766 int align = INTVAL (align_rtx);
2771 if (constp && bytes <= 0)
2774 /* Move the address into scratch registers. */
2775 dst_reg = copy_addr_to_reg (XEXP (orig_dst, 0));
2776 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2778 if (align > UNITS_PER_WORD)
2779 align = UNITS_PER_WORD;
2781 /* If we prefer size over speed, always use a function call.
2782 If we do not know the size, use a function call.
2783 If the blocks are not word aligned, use a function call. */
2784 if (optimize_size || ! constp || align != UNITS_PER_WORD)
2786 block_move_call (dst_reg, src_reg, bytes_rtx);
2790 leftover = bytes % MAX_MOVE_BYTES;
2793 /* If necessary, generate a loop to handle the bulk of the copy. */
2796 rtx label = NULL_RTX;
2797 rtx final_src = NULL_RTX;
2798 rtx at_a_time = GEN_INT (MAX_MOVE_BYTES);
2799 rtx rounded_total = GEN_INT (bytes);
2801 /* If we are going to have to perform this loop more than
2802 once, then generate a label and compute the address the
2803 source register will contain upon completion of the final
2805 if (bytes > MAX_MOVE_BYTES)
2807 final_src = gen_reg_rtx (Pmode);
2810 emit_insn (gen_addsi3 (final_src, src_reg, rounded_total));
2813 emit_insn (gen_movsi (final_src, rounded_total));
2814 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
2817 label = gen_label_rtx ();
2821 /* It is known that output_block_move() will update src_reg to point
2822 to the word after the end of the source block, and dst_reg to point
2823 to the last word of the destination block, provided that the block
2824 is MAX_MOVE_BYTES long. */
2825 emit_insn (gen_movstrsi_internal (dst_reg, src_reg, at_a_time));
2826 emit_insn (gen_addsi3 (dst_reg, dst_reg, GEN_INT (4)));
2828 if (bytes > MAX_MOVE_BYTES)
2830 emit_insn (gen_cmpsi (src_reg, final_src));
2831 emit_jump_insn (gen_bne (label));
2836 emit_insn (gen_movstrsi_internal (dst_reg, src_reg, GEN_INT (leftover)));
2840 /* Emit load/stores for a small constant word aligned block_move.
2842 operands[0] is the memory address of the destination.
2843 operands[1] is the memory address of the source.
2844 operands[2] is the number of bytes to move.
2845 operands[3] is a temp register.
2846 operands[4] is a temp register. */
2849 m32r_output_block_move (insn, operands)
2850 rtx insn ATTRIBUTE_UNUSED;
2853 HOST_WIDE_INT bytes = INTVAL (operands[2]);
2857 if (bytes < 1 || bytes > MAX_MOVE_BYTES)
2860 /* We do not have a post-increment store available, so the first set of
2861 stores are done without any increment, then the remaining ones can use
2862 the pre-increment addressing mode.
2864 Note: expand_block_move() also relies upon this behaviour when building
2865 loops to copy large blocks. */
2874 output_asm_insn ("ld\t%3, %p1", operands);
2875 output_asm_insn ("ld\t%4, %p1", operands);
2876 output_asm_insn ("st\t%3, @%0", operands);
2877 output_asm_insn ("st\t%4, %s0", operands);
2881 output_asm_insn ("ld\t%3, %p1", operands);
2882 output_asm_insn ("ld\t%4, %p1", operands);
2883 output_asm_insn ("st\t%3, %s0", operands);
2884 output_asm_insn ("st\t%4, %s0", operands);
2889 else if (bytes >= 4)
2894 output_asm_insn ("ld\t%3, %p1", operands);
2897 output_asm_insn ("ld\t%4, %p1", operands);
2900 output_asm_insn ("st\t%3, @%0", operands);
2902 output_asm_insn ("st\t%3, %s0", operands);
2908 /* Get the entire next word, even though we do not want all of it.
2909 The saves us from doing several smaller loads, and we assume that
2910 we cannot cause a page fault when at least part of the word is in
2911 valid memory [since we don't get called if things aren't properly
2913 int dst_offset = first_time ? 0 : 4;
2917 /* If got_extra is true then we have already loaded
2918 the next word as part of loading and storing the previous word. */
2920 output_asm_insn ("ld\t%4, @%1", operands);
2926 output_asm_insn ("sra3\t%3, %4, #16", operands);
2927 my_operands[0] = operands[3];
2928 my_operands[1] = GEN_INT (dst_offset);
2929 my_operands[2] = operands[0];
2930 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands);
2932 /* If there is a byte left to store then increment the
2933 destination address and shift the contents of the source
2934 register down by 8 bits. We could not do the address
2935 increment in the store half word instruction, because it does
2936 not have an auto increment mode. */
2937 if (bytes > 0) /* assert (bytes == 1) */
2948 my_operands[0] = operands[4];
2949 my_operands[1] = GEN_INT (last_shift);
2950 output_asm_insn ("srai\t%0, #%1", my_operands);
2951 my_operands[0] = operands[4];
2952 my_operands[1] = GEN_INT (dst_offset);
2953 my_operands[2] = operands[0];
2954 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands);
2964 /* Return true if op is an integer constant, less than or equal to
2967 m32r_block_immediate_operand (op, mode)
2969 enum machine_mode mode ATTRIBUTE_UNUSED;
2971 if (GET_CODE (op) != CONST_INT
2972 || INTVAL (op) > MAX_MOVE_BYTES
2973 || INTVAL (op) <= 0)