1 /* Subroutines used for code generation on the Renesas M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
3 2005, 2007, 2008 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
33 #include "insn-attr.h"
40 #include "integrate.h"
43 #include "target-def.h"
44 #include "tm-constrs.h"
46 /* Array of valid operand punctuation characters. */
47 char m32r_punct_chars[256];
49 /* Selected code model. */
50 enum m32r_model m32r_model = M32R_MODEL_DEFAULT;
52 /* Selected SDA support. */
53 enum m32r_sdata m32r_sdata = M32R_SDATA_DEFAULT;
55 /* Machine-specific symbol_ref flags. */
56 #define SYMBOL_FLAG_MODEL_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT
57 #define SYMBOL_REF_MODEL(X) \
58 ((enum m32r_model) ((SYMBOL_REF_FLAGS (X) >> SYMBOL_FLAG_MODEL_SHIFT) & 3))
60 /* For string literals, etc. */
61 #define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.')
63 /* Forward declaration. */
64 static bool m32r_handle_option (size_t, const char *, int);
65 static void init_reg_tables (void);
66 static void block_move_call (rtx, rtx, rtx);
67 static int m32r_is_insn (rtx);
68 const struct attribute_spec m32r_attribute_table[];
69 static rtx m32r_legitimize_address (rtx, rtx, enum machine_mode);
70 static tree m32r_handle_model_attribute (tree *, tree, tree, int, bool *);
71 static void m32r_output_function_prologue (FILE *, HOST_WIDE_INT);
72 static void m32r_output_function_epilogue (FILE *, HOST_WIDE_INT);
74 static void m32r_file_start (void);
76 static int m32r_adjust_priority (rtx, int);
77 static int m32r_issue_rate (void);
79 static void m32r_encode_section_info (tree, rtx, int);
80 static bool m32r_in_small_data_p (const_tree);
81 static bool m32r_return_in_memory (const_tree, const_tree);
82 static void m32r_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
84 static void init_idents (void);
85 static bool m32r_rtx_costs (rtx, int, int, int *, bool speed);
86 static bool m32r_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
88 static int m32r_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
91 /* Initialize the GCC target structure. */
92 #undef TARGET_ATTRIBUTE_TABLE
93 #define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
95 #undef TARGET_LEGITIMIZE_ADDRESS
96 #define TARGET_LEGITIMIZE_ADDRESS m32r_legitimize_address
98 #undef TARGET_ASM_ALIGNED_HI_OP
99 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
100 #undef TARGET_ASM_ALIGNED_SI_OP
101 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
103 #undef TARGET_ASM_FUNCTION_PROLOGUE
104 #define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue
105 #undef TARGET_ASM_FUNCTION_EPILOGUE
106 #define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
108 #undef TARGET_ASM_FILE_START
109 #define TARGET_ASM_FILE_START m32r_file_start
111 #undef TARGET_SCHED_ADJUST_PRIORITY
112 #define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
113 #undef TARGET_SCHED_ISSUE_RATE
114 #define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
116 #undef TARGET_DEFAULT_TARGET_FLAGS
117 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_CPU_DEFAULT
118 #undef TARGET_HANDLE_OPTION
119 #define TARGET_HANDLE_OPTION m32r_handle_option
121 #undef TARGET_ENCODE_SECTION_INFO
122 #define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info
123 #undef TARGET_IN_SMALL_DATA_P
124 #define TARGET_IN_SMALL_DATA_P m32r_in_small_data_p
126 #undef TARGET_RTX_COSTS
127 #define TARGET_RTX_COSTS m32r_rtx_costs
128 #undef TARGET_ADDRESS_COST
129 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
131 #undef TARGET_PROMOTE_PROTOTYPES
132 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
133 #undef TARGET_RETURN_IN_MEMORY
134 #define TARGET_RETURN_IN_MEMORY m32r_return_in_memory
135 #undef TARGET_SETUP_INCOMING_VARARGS
136 #define TARGET_SETUP_INCOMING_VARARGS m32r_setup_incoming_varargs
137 #undef TARGET_MUST_PASS_IN_STACK
138 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
139 #undef TARGET_PASS_BY_REFERENCE
140 #define TARGET_PASS_BY_REFERENCE m32r_pass_by_reference
141 #undef TARGET_ARG_PARTIAL_BYTES
142 #define TARGET_ARG_PARTIAL_BYTES m32r_arg_partial_bytes
144 struct gcc_target targetm = TARGET_INITIALIZER;
146 /* Implement TARGET_HANDLE_OPTION. */
149 m32r_handle_option (size_t code, const char *arg, int value)
154 target_flags &= ~(MASK_M32R2 | MASK_M32RX);
158 if (strcmp (arg, "small") == 0)
159 m32r_model = M32R_MODEL_SMALL;
160 else if (strcmp (arg, "medium") == 0)
161 m32r_model = M32R_MODEL_MEDIUM;
162 else if (strcmp (arg, "large") == 0)
163 m32r_model = M32R_MODEL_LARGE;
169 if (strcmp (arg, "none") == 0)
170 m32r_sdata = M32R_SDATA_NONE;
171 else if (strcmp (arg, "sdata") == 0)
172 m32r_sdata = M32R_SDATA_SDATA;
173 else if (strcmp (arg, "use") == 0)
174 m32r_sdata = M32R_SDATA_USE;
179 case OPT_mno_flush_func:
180 m32r_cache_flush_func = NULL;
183 case OPT_mflush_trap_:
186 case OPT_mno_flush_trap:
187 m32r_cache_flush_trap = -1;
195 /* Called by OVERRIDE_OPTIONS to initialize various things. */
202 /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */
203 memset (m32r_punct_chars, 0, sizeof (m32r_punct_chars));
204 m32r_punct_chars['#'] = 1;
205 m32r_punct_chars['@'] = 1; /* ??? no longer used */
207 /* Provide default value if not specified. */
209 g_switch_value = SDATA_DEFAULT_SIZE;
212 /* Vectors to keep interesting information about registers where it can easily
213 be got. We use to use the actual mode value as the bit number, but there
214 is (or may be) more than 32 modes now. Instead we use two tables: one
215 indexed by hard register number, and one indexed by mode. */
217 /* The purpose of m32r_mode_class is to shrink the range of modes so that
218 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
219 mapped into one m32r_mode_class mode. */
224 S_MODE, D_MODE, T_MODE, O_MODE,
225 SF_MODE, DF_MODE, TF_MODE, OF_MODE, A_MODE
228 /* Modes for condition codes. */
229 #define C_MODES (1 << (int) C_MODE)
231 /* Modes for single-word and smaller quantities. */
232 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
234 /* Modes for double-word and smaller quantities. */
235 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
237 /* Modes for quad-word and smaller quantities. */
238 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
240 /* Modes for accumulators. */
241 #define A_MODES (1 << (int) A_MODE)
243 /* Value is 1 if register/mode pair is acceptable on arc. */
245 const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
247 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
248 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
249 S_MODES, C_MODES, A_MODES, A_MODES
252 unsigned int m32r_mode_class [NUM_MACHINE_MODES];
254 enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
257 init_reg_tables (void)
261 for (i = 0; i < NUM_MACHINE_MODES; i++)
263 switch (GET_MODE_CLASS (i))
266 case MODE_PARTIAL_INT:
267 case MODE_COMPLEX_INT:
268 if (GET_MODE_SIZE (i) <= 4)
269 m32r_mode_class[i] = 1 << (int) S_MODE;
270 else if (GET_MODE_SIZE (i) == 8)
271 m32r_mode_class[i] = 1 << (int) D_MODE;
272 else if (GET_MODE_SIZE (i) == 16)
273 m32r_mode_class[i] = 1 << (int) T_MODE;
274 else if (GET_MODE_SIZE (i) == 32)
275 m32r_mode_class[i] = 1 << (int) O_MODE;
277 m32r_mode_class[i] = 0;
280 case MODE_COMPLEX_FLOAT:
281 if (GET_MODE_SIZE (i) <= 4)
282 m32r_mode_class[i] = 1 << (int) SF_MODE;
283 else if (GET_MODE_SIZE (i) == 8)
284 m32r_mode_class[i] = 1 << (int) DF_MODE;
285 else if (GET_MODE_SIZE (i) == 16)
286 m32r_mode_class[i] = 1 << (int) TF_MODE;
287 else if (GET_MODE_SIZE (i) == 32)
288 m32r_mode_class[i] = 1 << (int) OF_MODE;
290 m32r_mode_class[i] = 0;
293 m32r_mode_class[i] = 1 << (int) C_MODE;
296 m32r_mode_class[i] = 0;
301 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
304 m32r_regno_reg_class[i] = GENERAL_REGS;
305 else if (i == ARG_POINTER_REGNUM)
306 m32r_regno_reg_class[i] = GENERAL_REGS;
308 m32r_regno_reg_class[i] = NO_REGS;
312 /* M32R specific attribute support.
314 interrupt - for interrupt functions
316 model - select code model used to access object
318 small: addresses use 24 bits, use bl to make calls
319 medium: addresses use 32 bits, use bl to make calls
320 large: addresses use 32 bits, use seth/add3/jl to make calls
322 Grep for MODEL in m32r.h for more info. */
324 static tree small_ident1;
325 static tree small_ident2;
326 static tree medium_ident1;
327 static tree medium_ident2;
328 static tree large_ident1;
329 static tree large_ident2;
334 if (small_ident1 == 0)
336 small_ident1 = get_identifier ("small");
337 small_ident2 = get_identifier ("__small__");
338 medium_ident1 = get_identifier ("medium");
339 medium_ident2 = get_identifier ("__medium__");
340 large_ident1 = get_identifier ("large");
341 large_ident2 = get_identifier ("__large__");
345 const struct attribute_spec m32r_attribute_table[] =
347 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
348 { "interrupt", 0, 0, true, false, false, NULL },
349 { "model", 1, 1, true, false, false, m32r_handle_model_attribute },
350 { NULL, 0, 0, false, false, false, NULL }
354 /* Handle an "model" attribute; arguments as in
355 struct attribute_spec.handler. */
357 m32r_handle_model_attribute (tree *node ATTRIBUTE_UNUSED, tree name,
358 tree args, int flags ATTRIBUTE_UNUSED,
364 arg = TREE_VALUE (args);
366 if (arg != small_ident1
367 && arg != small_ident2
368 && arg != medium_ident1
369 && arg != medium_ident2
370 && arg != large_ident1
371 && arg != large_ident2)
373 warning (OPT_Wattributes, "invalid argument of %qs attribute",
374 IDENTIFIER_POINTER (name));
375 *no_add_attrs = true;
381 /* Encode section information of DECL, which is either a VAR_DECL,
382 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
384 For the M32R we want to record:
386 - whether the object lives in .sdata/.sbss.
387 - what code model should be used to access the object
391 m32r_encode_section_info (tree decl, rtx rtl, int first)
395 enum m32r_model model;
397 default_encode_section_info (decl, rtl, first);
402 model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
409 id = TREE_VALUE (TREE_VALUE (model_attr));
411 if (id == small_ident1 || id == small_ident2)
412 model = M32R_MODEL_SMALL;
413 else if (id == medium_ident1 || id == medium_ident2)
414 model = M32R_MODEL_MEDIUM;
415 else if (id == large_ident1 || id == large_ident2)
416 model = M32R_MODEL_LARGE;
418 gcc_unreachable (); /* shouldn't happen */
422 if (TARGET_MODEL_SMALL)
423 model = M32R_MODEL_SMALL;
424 else if (TARGET_MODEL_MEDIUM)
425 model = M32R_MODEL_MEDIUM;
426 else if (TARGET_MODEL_LARGE)
427 model = M32R_MODEL_LARGE;
429 gcc_unreachable (); /* shouldn't happen */
431 extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT;
434 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
437 /* Only mark the object as being small data area addressable if
438 it hasn't been explicitly marked with a code model.
440 The user can explicitly put an object in the small data area with the
441 section attribute. If the object is in sdata/sbss and marked with a
442 code model do both [put the object in .sdata and mark it as being
443 addressed with a specific code model - don't mark it as being addressed
444 with an SDA reloc though]. This is ok and might be useful at times. If
445 the object doesn't fit the linker will give an error. */
448 m32r_in_small_data_p (const_tree decl)
452 if (TREE_CODE (decl) != VAR_DECL)
455 if (lookup_attribute ("model", DECL_ATTRIBUTES (decl)))
458 section = DECL_SECTION_NAME (decl);
461 const char *const name = TREE_STRING_POINTER (section);
462 if (strcmp (name, ".sdata") == 0 || strcmp (name, ".sbss") == 0)
467 if (! TREE_READONLY (decl) && ! TARGET_SDATA_NONE)
469 int size = int_size_in_bytes (TREE_TYPE (decl));
471 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
479 /* Do anything needed before RTL is emitted for each function. */
482 m32r_init_expanders (void)
484 /* ??? At one point there was code here. The function is left in
485 to make it easy to experiment. */
489 call_operand (rtx op, enum machine_mode mode)
494 return call_address_operand (op, mode);
497 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */
500 small_data_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
502 if (! TARGET_SDATA_USE)
505 if (GET_CODE (op) == SYMBOL_REF)
506 return SYMBOL_REF_SMALL_P (op);
508 if (GET_CODE (op) == CONST
509 && GET_CODE (XEXP (op, 0)) == PLUS
510 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
511 && satisfies_constraint_J (XEXP (XEXP (op, 0), 1)))
512 return SYMBOL_REF_SMALL_P (XEXP (XEXP (op, 0), 0));
517 /* Return 1 if OP is a symbol that can use 24-bit addressing. */
520 addr24_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
527 if (GET_CODE (op) == LABEL_REF)
528 return TARGET_ADDR24;
530 if (GET_CODE (op) == SYMBOL_REF)
532 else if (GET_CODE (op) == CONST
533 && GET_CODE (XEXP (op, 0)) == PLUS
534 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
535 && satisfies_constraint_M (XEXP (XEXP (op, 0), 1)))
536 sym = XEXP (XEXP (op, 0), 0);
540 if (SYMBOL_REF_MODEL (sym) == M32R_MODEL_SMALL)
544 && (CONSTANT_POOL_ADDRESS_P (sym)
545 || LIT_NAME_P (XSTR (sym, 0))))
551 /* Return 1 if OP is a symbol that needs 32-bit addressing. */
554 addr32_operand (rtx op, enum machine_mode mode)
558 if (GET_CODE (op) == LABEL_REF)
559 return TARGET_ADDR32;
561 if (GET_CODE (op) == SYMBOL_REF)
563 else if (GET_CODE (op) == CONST
564 && GET_CODE (XEXP (op, 0)) == PLUS
565 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
566 && CONST_INT_P (XEXP (XEXP (op, 0), 1))
568 sym = XEXP (XEXP (op, 0), 0);
572 return (! addr24_operand (sym, mode)
573 && ! small_data_operand (sym, mode));
576 /* Return 1 if OP is a function that can be called with the `bl' insn. */
579 call26_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
584 if (GET_CODE (op) == SYMBOL_REF)
585 return SYMBOL_REF_MODEL (op) != M32R_MODEL_LARGE;
587 return TARGET_CALL26;
590 /* Return 1 if OP is a DImode const we want to handle inline.
591 This must match the code in the movdi pattern.
592 It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER. */
595 easy_di_const (rtx op)
597 rtx high_rtx, low_rtx;
598 HOST_WIDE_INT high, low;
600 split_double (op, &high_rtx, &low_rtx);
601 high = INTVAL (high_rtx);
602 low = INTVAL (low_rtx);
603 /* Pick constants loadable with 2 16-bit `ldi' insns. */
604 if (high >= -128 && high <= 127
605 && low >= -128 && low <= 127)
610 /* Return 1 if OP is a DFmode const we want to handle inline.
611 This must match the code in the movdf pattern.
612 It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER. */
615 easy_df_const (rtx op)
620 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
621 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
622 if (l[0] == 0 && l[1] == 0)
624 if ((l[0] & 0xffff) == 0 && l[1] == 0)
629 /* Return 1 if OP is (mem (reg ...)).
630 This is used in insn length calcs. */
633 memreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
635 return REG_P (op) && MEM_P (XEXP (op, 0));
638 /* Return nonzero if TYPE must be passed by indirect reference. */
641 m32r_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
642 enum machine_mode mode, const_tree type,
643 bool named ATTRIBUTE_UNUSED)
648 size = int_size_in_bytes (type);
650 size = GET_MODE_SIZE (mode);
652 return (size < 0 || size > 8);
657 /* X and Y are two things to compare using CODE. Emit the compare insn and
658 return the rtx for compare [arg0 of the if_then_else].
659 If need_compare is true then the comparison insn must be generated, rather
660 than being subsumed into the following branch instruction. */
663 gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare)
665 enum rtx_code compare_code;
666 enum rtx_code branch_code;
667 rtx cc_reg = gen_rtx_REG (CCmode, CARRY_REGNUM);
672 case EQ: compare_code = EQ; branch_code = NE; break;
673 case NE: compare_code = EQ; branch_code = EQ; break;
674 case LT: compare_code = LT; branch_code = NE; break;
675 case LE: compare_code = LT; branch_code = EQ; must_swap = 1; break;
676 case GT: compare_code = LT; branch_code = NE; must_swap = 1; break;
677 case GE: compare_code = LT; branch_code = EQ; break;
678 case LTU: compare_code = LTU; branch_code = NE; break;
679 case LEU: compare_code = LTU; branch_code = EQ; must_swap = 1; break;
680 case GTU: compare_code = LTU; branch_code = NE; must_swap = 1; break;
681 case GEU: compare_code = LTU; branch_code = EQ; break;
689 switch (compare_code)
692 if (satisfies_constraint_P (y) /* Reg equal to small const. */
695 rtx tmp = gen_reg_rtx (SImode);
697 emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y))));
701 else if (CONSTANT_P (y)) /* Reg equal to const. */
703 rtx tmp = force_reg (GET_MODE (x), y);
707 if (register_operand (y, SImode) /* Reg equal to reg. */
708 || y == const0_rtx) /* Reg equal to zero. */
710 emit_insn (gen_cmp_eqsi_insn (x, y));
712 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
717 if (register_operand (y, SImode)
718 || satisfies_constraint_P (y))
720 rtx tmp = gen_reg_rtx (SImode); /* Reg compared to reg. */
725 emit_insn (gen_cmp_ltsi_insn (x, y));
732 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
733 emit_insn (gen_cmp_ltsi_insn (x, tmp));
738 tmp = gen_rtx_PLUS (SImode, y, const1_rtx);
740 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
741 emit_insn (gen_cmp_ltsi_insn (x, tmp));
745 emit_insn (gen_cmp_ltsi_insn (x, y));
752 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
757 if (register_operand (y, SImode)
758 || satisfies_constraint_P (y))
760 rtx tmp = gen_reg_rtx (SImode); /* Reg (unsigned) compared to reg. */
765 emit_insn (gen_cmp_ltusi_insn (x, y));
772 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
773 emit_insn (gen_cmp_ltusi_insn (x, tmp));
778 tmp = gen_rtx_PLUS (SImode, y, const1_rtx);
780 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
781 emit_insn (gen_cmp_ltusi_insn (x, tmp));
785 emit_insn (gen_cmp_ltusi_insn (x, y));
792 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
802 /* Reg/reg equal comparison. */
803 if (compare_code == EQ
804 && register_operand (y, SImode))
805 return gen_rtx_fmt_ee (code, CCmode, x, y);
807 /* Reg/zero signed comparison. */
808 if ((compare_code == EQ || compare_code == LT)
810 return gen_rtx_fmt_ee (code, CCmode, x, y);
812 /* Reg/smallconst equal comparison. */
813 if (compare_code == EQ
814 && satisfies_constraint_P (y))
816 rtx tmp = gen_reg_rtx (SImode);
818 emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y))));
819 return gen_rtx_fmt_ee (code, CCmode, tmp, const0_rtx);
822 /* Reg/const equal comparison. */
823 if (compare_code == EQ
826 rtx tmp = force_reg (GET_MODE (x), y);
828 return gen_rtx_fmt_ee (code, CCmode, x, tmp);
835 y = force_reg (GET_MODE (x), y);
838 int ok_const = reg_or_int16_operand (y, GET_MODE (y));
841 y = force_reg (GET_MODE (x), y);
845 switch (compare_code)
848 emit_insn (gen_cmp_eqsi_insn (must_swap ? y : x, must_swap ? x : y));
851 emit_insn (gen_cmp_ltsi_insn (must_swap ? y : x, must_swap ? x : y));
854 emit_insn (gen_cmp_ltusi_insn (must_swap ? y : x, must_swap ? x : y));
861 return gen_rtx_fmt_ee (branch_code, VOIDmode, cc_reg, CONST0_RTX (CCmode));
865 gen_cond_store (enum rtx_code code, rtx op0, rtx op1, rtx op2)
867 enum machine_mode mode = GET_MODE (op0);
869 gcc_assert (mode == SImode);
873 if (!register_operand (op1, mode))
874 op1 = force_reg (mode, op1);
876 if (TARGET_M32RX || TARGET_M32R2)
878 if (!reg_or_zero_operand (op2, mode))
879 op2 = force_reg (mode, op2);
881 emit_insn (gen_seq_insn_m32rx (op0, op1, op2));
884 if (CONST_INT_P (op2) && INTVAL (op2) == 0)
886 emit_insn (gen_seq_zero_insn (op0, op1));
890 if (!reg_or_eq_int16_operand (op2, mode))
891 op2 = force_reg (mode, op2);
893 emit_insn (gen_seq_insn (op0, op1, op2));
897 if (!CONST_INT_P (op2)
898 || (INTVAL (op2) != 0 && satisfies_constraint_K (op2)))
902 if (reload_completed || reload_in_progress)
905 reg = gen_reg_rtx (SImode);
906 emit_insn (gen_xorsi3 (reg, op1, op2));
909 if (!register_operand (op1, mode))
910 op1 = force_reg (mode, op1);
912 emit_insn (gen_sne_zero_insn (op0, op1));
927 if (!register_operand (op1, mode))
928 op1 = force_reg (mode, op1);
930 if (!reg_or_int16_operand (op2, mode))
931 op2 = force_reg (mode, op2);
933 emit_insn (gen_slt_insn (op0, op1, op2));
946 if (!register_operand (op1, mode))
947 op1 = force_reg (mode, op1);
949 if (!reg_or_int16_operand (op2, mode))
950 op2 = force_reg (mode, op2);
952 emit_insn (gen_sltu_insn (op0, op1, op2));
957 if (!register_operand (op1, mode))
958 op1 = force_reg (mode, op1);
960 if (!reg_or_int16_operand (op2, mode))
961 op2 = force_reg (mode, op2);
964 emit_insn (gen_sge_insn (op0, op1, op2));
966 emit_insn (gen_sgeu_insn (op0, op1, op2));
971 if (!register_operand (op1, mode))
972 op1 = force_reg (mode, op1);
974 if (CONST_INT_P (op2))
976 HOST_WIDE_INT value = INTVAL (op2);
977 if (value >= 2147483647)
979 emit_move_insn (op0, const1_rtx);
983 op2 = GEN_INT (value + 1);
984 if (value < -32768 || value >= 32767)
985 op2 = force_reg (mode, op2);
988 emit_insn (gen_sltu_insn (op0, op1, op2));
990 emit_insn (gen_slt_insn (op0, op1, op2));
994 if (!register_operand (op2, mode))
995 op2 = force_reg (mode, op2);
998 emit_insn (gen_sleu_insn (op0, op1, op2));
1000 emit_insn (gen_sle_insn (op0, op1, op2));
1009 /* Split a 2 word move (DI or DF) into component parts. */
1012 gen_split_move_double (rtx operands[])
1014 enum machine_mode mode = GET_MODE (operands[0]);
1015 rtx dest = operands[0];
1016 rtx src = operands[1];
1019 /* We might have (SUBREG (MEM)) here, so just get rid of the
1020 subregs to make this code simpler. It is safe to call
1021 alter_subreg any time after reload. */
1022 if (GET_CODE (dest) == SUBREG)
1023 alter_subreg (&dest);
1024 if (GET_CODE (src) == SUBREG)
1025 alter_subreg (&src);
1030 int dregno = REGNO (dest);
1035 int sregno = REGNO (src);
1037 int reverse = (dregno == sregno + 1);
1039 /* We normally copy the low-numbered register first. However, if
1040 the first register operand 0 is the same as the second register of
1041 operand 1, we must copy in the opposite order. */
1042 emit_insn (gen_rtx_SET (VOIDmode,
1043 operand_subword (dest, reverse, TRUE, mode),
1044 operand_subword (src, reverse, TRUE, mode)));
1046 emit_insn (gen_rtx_SET (VOIDmode,
1047 operand_subword (dest, !reverse, TRUE, mode),
1048 operand_subword (src, !reverse, TRUE, mode)));
1051 /* Reg = constant. */
1052 else if (CONST_INT_P (src) || GET_CODE (src) == CONST_DOUBLE)
1055 split_double (src, &words[0], &words[1]);
1056 emit_insn (gen_rtx_SET (VOIDmode,
1057 operand_subword (dest, 0, TRUE, mode),
1060 emit_insn (gen_rtx_SET (VOIDmode,
1061 operand_subword (dest, 1, TRUE, mode),
1066 else if (MEM_P (src))
1068 /* If the high-address word is used in the address, we must load it
1069 last. Otherwise, load it first. */
1071 = (refers_to_regno_p (dregno, dregno + 1, XEXP (src, 0), 0) != 0);
1073 /* We used to optimize loads from single registers as
1077 if r3 were not used subsequently. However, the REG_NOTES aren't
1078 propagated correctly by the reload phase, and it can cause bad
1079 code to be generated. We could still try:
1081 ld r1,r3+; ld r2,r3; addi r3,-4
1083 which saves 2 bytes and doesn't force longword alignment. */
1084 emit_insn (gen_rtx_SET (VOIDmode,
1085 operand_subword (dest, reverse, TRUE, mode),
1086 adjust_address (src, SImode,
1087 reverse * UNITS_PER_WORD)));
1089 emit_insn (gen_rtx_SET (VOIDmode,
1090 operand_subword (dest, !reverse, TRUE, mode),
1091 adjust_address (src, SImode,
1092 !reverse * UNITS_PER_WORD)));
1099 /* We used to optimize loads from single registers as
1103 if r3 were not used subsequently. However, the REG_NOTES aren't
1104 propagated correctly by the reload phase, and it can cause bad
1105 code to be generated. We could still try:
1107 st r1,r3; st r2,+r3; addi r3,-4
1109 which saves 2 bytes and doesn't force longword alignment. */
1110 else if (REG_P (dest) && MEM_P (src))
1112 emit_insn (gen_rtx_SET (VOIDmode,
1113 adjust_address (dest, SImode, 0),
1114 operand_subword (src, 0, TRUE, mode)));
1116 emit_insn (gen_rtx_SET (VOIDmode,
1117 adjust_address (dest, SImode, UNITS_PER_WORD),
1118 operand_subword (src, 1, TRUE, mode)));
1131 m32r_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1132 tree type, bool named ATTRIBUTE_UNUSED)
1136 (((mode == BLKmode && type)
1137 ? (unsigned int) int_size_in_bytes (type)
1138 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
1141 if (*cum >= M32R_MAX_PARM_REGS)
1143 else if (*cum + size > M32R_MAX_PARM_REGS)
1144 words = (*cum + size) - M32R_MAX_PARM_REGS;
1148 return words * UNITS_PER_WORD;
1151 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1154 m32r_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
1156 return m32r_pass_by_reference (NULL, TYPE_MODE (type), type, false);
1159 /* Do any needed setup for a variadic function. For the M32R, we must
1160 create a register parameter block, and then copy any anonymous arguments
1161 in registers to memory.
1163 CUM has not been updated for the last named argument which has type TYPE
1164 and mode MODE, and we rely on this fact. */
1167 m32r_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1168 tree type, int *pretend_size, int no_rtl)
1175 /* All BLKmode values are passed by reference. */
1176 gcc_assert (mode != BLKmode);
1178 first_anon_arg = (ROUND_ADVANCE_CUM (*cum, mode, type)
1179 + ROUND_ADVANCE_ARG (mode, type));
1181 if (first_anon_arg < M32R_MAX_PARM_REGS)
1183 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1184 int first_reg_offset = first_anon_arg;
1185 /* Size in words to "pretend" allocate. */
1186 int size = M32R_MAX_PARM_REGS - first_reg_offset;
1189 regblock = gen_frame_mem (BLKmode,
1190 plus_constant (arg_pointer_rtx,
1191 FIRST_PARM_OFFSET (0)));
1192 set_mem_alias_set (regblock, get_varargs_alias_set ());
1193 move_block_from_reg (first_reg_offset, regblock, size);
1195 *pretend_size = (size * UNITS_PER_WORD);
1200 /* Return true if INSN is real instruction bearing insn. */
1203 m32r_is_insn (rtx insn)
1205 return (INSN_P (insn)
1206 && GET_CODE (PATTERN (insn)) != USE
1207 && GET_CODE (PATTERN (insn)) != CLOBBER
1208 && GET_CODE (PATTERN (insn)) != ADDR_VEC);
1211 /* Increase the priority of long instructions so that the
1212 short instructions are scheduled ahead of the long ones. */
1215 m32r_adjust_priority (rtx insn, int priority)
1217 if (m32r_is_insn (insn)
1218 && get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1225 /* Indicate how many instructions can be issued at the same time.
1226 This is sort of a lie. The m32r can issue only 1 long insn at
1227 once, but it can issue 2 short insns. The default therefore is
1228 set at 2, but this can be overridden by the command line option
1232 m32r_issue_rate (void)
1234 return ((TARGET_LOW_ISSUE_RATE) ? 1 : 2);
1237 /* Cost functions. */
1240 m32r_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, int *total,
1241 bool speed ATTRIBUTE_UNUSED)
1245 /* Small integers are as cheap as registers. 4 byte values can be
1246 fetched as immediate constants - let's give that the cost of an
1249 if (INT16_P (INTVAL (x)))
1259 *total = COSTS_N_INSNS (1);
1266 split_double (x, &high, &low);
1267 *total = COSTS_N_INSNS (!INT16_P (INTVAL (high))
1268 + !INT16_P (INTVAL (low)));
1273 *total = COSTS_N_INSNS (3);
1280 *total = COSTS_N_INSNS (10);
1288 /* Type of function DECL.
1290 The result is cached. To reset the cache at the end of a function,
1291 call with DECL = NULL_TREE. */
1293 enum m32r_function_type
1294 m32r_compute_function_type (tree decl)
1297 static enum m32r_function_type fn_type = M32R_FUNCTION_UNKNOWN;
1298 /* Last function we were called for. */
1299 static tree last_fn = NULL_TREE;
1301 /* Resetting the cached value? */
1302 if (decl == NULL_TREE)
1304 fn_type = M32R_FUNCTION_UNKNOWN;
1305 last_fn = NULL_TREE;
1309 if (decl == last_fn && fn_type != M32R_FUNCTION_UNKNOWN)
1312 /* Compute function type. */
1313 fn_type = (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE
1314 ? M32R_FUNCTION_INTERRUPT
1315 : M32R_FUNCTION_NORMAL);
1320 \f/* Function prologue/epilogue handlers. */
1322 /* M32R stack frames look like:
1324 Before call After call
1325 +-----------------------+ +-----------------------+
1327 high | local variables, | | local variables, |
1328 mem | reg save area, etc. | | reg save area, etc. |
1330 +-----------------------+ +-----------------------+
1332 | arguments on stack. | | arguments on stack. |
1334 SP+0->+-----------------------+ +-----------------------+
1335 | reg parm save area, |
1336 | only created for |
1337 | variable argument |
1339 +-----------------------+
1340 | previous frame ptr |
1341 +-----------------------+
1343 | register save area |
1345 +-----------------------+
1347 +-----------------------+
1351 +-----------------------+
1353 | alloca allocations |
1355 +-----------------------+
1357 low | arguments on stack |
1359 SP+0->+-----------------------+
1362 1) The "reg parm save area" does not exist for non variable argument fns.
1363 2) The "reg parm save area" can be eliminated completely if we saved regs
1364 containing anonymous args separately but that complicates things too
1365 much (so it's not done).
1366 3) The return address is saved after the register save area so as to have as
1367 many insns as possible between the restoration of `lr' and the `jmp lr'. */
1369 /* Structure to be filled in by m32r_compute_frame_size with register
1370 save masks, and offsets for the current function. */
1371 struct m32r_frame_info
1373 unsigned int total_size; /* # bytes that the entire frame takes up. */
1374 unsigned int extra_size; /* # bytes of extra stuff. */
1375 unsigned int pretend_size; /* # bytes we push and pretend caller did. */
1376 unsigned int args_size; /* # bytes that outgoing arguments take up. */
1377 unsigned int reg_size; /* # bytes needed to store regs. */
1378 unsigned int var_size; /* # bytes that variables take up. */
1379 unsigned int gmask; /* Mask of saved gp registers. */
1380 unsigned int save_fp; /* Nonzero if fp must be saved. */
1381 unsigned int save_lr; /* Nonzero if lr (return addr) must be saved. */
1382 int initialized; /* Nonzero if frame size already calculated. */
1385 /* Current frame information calculated by m32r_compute_frame_size. */
1386 static struct m32r_frame_info current_frame_info;
1388 /* Zero structure to initialize current_frame_info. */
1389 static struct m32r_frame_info zero_frame_info;
1391 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1392 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1394 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1395 The return address and frame pointer are treated separately.
1396 Don't consider them here. */
1397 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1398 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1399 && (df_regs_ever_live_p (regno) && (!call_really_used_regs[regno] || interrupt_p)))
1401 #define MUST_SAVE_FRAME_POINTER (df_regs_ever_live_p (FRAME_POINTER_REGNUM))
1402 #define MUST_SAVE_RETURN_ADDR (df_regs_ever_live_p (RETURN_ADDR_REGNUM) || crtl->profile)
1404 #define SHORT_INSN_SIZE 2 /* Size of small instructions. */
1405 #define LONG_INSN_SIZE 4 /* Size of long instructions. */
1407 /* Return the bytes needed to compute the frame pointer from the current
1410 SIZE is the size needed for local variables. */
1413 m32r_compute_frame_size (int size) /* # of var. bytes allocated. */
1416 unsigned int total_size, var_size, args_size, pretend_size, extra_size;
1417 unsigned int reg_size, frame_size;
1419 enum m32r_function_type fn_type;
1421 int pic_reg_used = flag_pic && (crtl->uses_pic_offset_table
1424 var_size = M32R_STACK_ALIGN (size);
1425 args_size = M32R_STACK_ALIGN (crtl->outgoing_args_size);
1426 pretend_size = crtl->args.pretend_args_size;
1427 extra_size = FIRST_PARM_OFFSET (0);
1428 total_size = extra_size + pretend_size + args_size + var_size;
1432 /* See if this is an interrupt handler. Call used registers must be saved
1434 fn_type = m32r_compute_function_type (current_function_decl);
1435 interrupt_p = M32R_INTERRUPT_P (fn_type);
1437 /* Calculate space needed for registers. */
1438 for (regno = 0; regno < M32R_MAX_INT_REGS; regno++)
1440 if (MUST_SAVE_REGISTER (regno, interrupt_p)
1441 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
1443 reg_size += UNITS_PER_WORD;
1444 gmask |= 1 << regno;
1448 current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER;
1449 current_frame_info.save_lr = MUST_SAVE_RETURN_ADDR || pic_reg_used;
1451 reg_size += ((current_frame_info.save_fp + current_frame_info.save_lr)
1453 total_size += reg_size;
1455 /* ??? Not sure this is necessary, and I don't think the epilogue
1456 handler will do the right thing if this changes total_size. */
1457 total_size = M32R_STACK_ALIGN (total_size);
1459 frame_size = total_size - (pretend_size + reg_size);
1461 /* Save computed information. */
1462 current_frame_info.total_size = total_size;
1463 current_frame_info.extra_size = extra_size;
1464 current_frame_info.pretend_size = pretend_size;
1465 current_frame_info.var_size = var_size;
1466 current_frame_info.args_size = args_size;
1467 current_frame_info.reg_size = reg_size;
1468 current_frame_info.gmask = gmask;
1469 current_frame_info.initialized = reload_completed;
1471 /* Ok, we're done. */
1475 /* The table we use to reference PIC data. */
1476 static rtx global_offset_table;
1479 m32r_reload_lr (rtx sp, int size)
1481 rtx lr = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
1484 emit_insn (gen_movsi (lr, gen_frame_mem (Pmode, sp)));
1485 else if (size < 32768)
1486 emit_insn (gen_movsi (lr, gen_frame_mem (Pmode,
1487 gen_rtx_PLUS (Pmode, sp,
1491 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1493 emit_insn (gen_movsi (tmp, GEN_INT (size)));
1494 emit_insn (gen_addsi3 (tmp, tmp, sp));
1495 emit_insn (gen_movsi (lr, gen_frame_mem (Pmode, tmp)));
1502 m32r_load_pic_register (void)
1504 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
1505 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
1506 GEN_INT (TARGET_MODEL_SMALL)));
1508 /* Need to emit this whether or not we obey regdecls,
1509 since setjmp/longjmp can cause life info to screw up. */
1510 emit_use (pic_offset_table_rtx);
1513 /* Expand the m32r prologue as a series of insns. */
1516 m32r_expand_prologue (void)
1521 int pic_reg_used = flag_pic && (crtl->uses_pic_offset_table
1524 if (! current_frame_info.initialized)
1525 m32r_compute_frame_size (get_frame_size ());
1527 gmask = current_frame_info.gmask;
1529 /* These cases shouldn't happen. Catch them now. */
1530 gcc_assert (current_frame_info.total_size || !gmask);
1532 /* Allocate space for register arguments if this is a variadic function. */
1533 if (current_frame_info.pretend_size != 0)
1535 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1536 the wrong result on a 64-bit host. */
1537 HOST_WIDE_INT pretend_size = current_frame_info.pretend_size;
1538 emit_insn (gen_addsi3 (stack_pointer_rtx,
1540 GEN_INT (-pretend_size)));
1543 /* Save any registers we need to and set up fp. */
1544 if (current_frame_info.save_fp)
1545 emit_insn (gen_movsi_push (stack_pointer_rtx, frame_pointer_rtx));
1547 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1549 /* Save any needed call-saved regs (and call-used if this is an
1550 interrupt handler). */
1551 for (regno = 0; regno <= M32R_MAX_INT_REGS; ++regno)
1553 if ((gmask & (1 << regno)) != 0)
1554 emit_insn (gen_movsi_push (stack_pointer_rtx,
1555 gen_rtx_REG (Pmode, regno)));
1558 if (current_frame_info.save_lr)
1559 emit_insn (gen_movsi_push (stack_pointer_rtx,
1560 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
1562 /* Allocate the stack frame. */
1563 frame_size = (current_frame_info.total_size
1564 - (current_frame_info.pretend_size
1565 + current_frame_info.reg_size));
1567 if (frame_size == 0)
1568 ; /* Nothing to do. */
1569 else if (frame_size <= 32768)
1570 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1571 GEN_INT (-frame_size)));
1574 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1576 emit_insn (gen_movsi (tmp, GEN_INT (frame_size)));
1577 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
1580 if (frame_pointer_needed)
1581 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
1584 /* Push lr for mcount (form_pc, x). */
1585 emit_insn (gen_movsi_push (stack_pointer_rtx,
1586 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
1590 m32r_load_pic_register ();
1591 m32r_reload_lr (stack_pointer_rtx,
1592 (crtl->profile ? 0 : frame_size));
1595 if (crtl->profile && !pic_reg_used)
1596 emit_insn (gen_blockage ());
1600 /* Set up the stack and frame pointer (if desired) for the function.
1601 Note, if this is changed, you need to mirror the changes in
1602 m32r_compute_frame_size which calculates the prolog size. */
1605 m32r_output_function_prologue (FILE * file, HOST_WIDE_INT size)
1607 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
1609 /* If this is an interrupt handler, mark it as such. */
1610 if (M32R_INTERRUPT_P (fn_type))
1611 fprintf (file, "\t%s interrupt handler\n", ASM_COMMENT_START);
1613 if (! current_frame_info.initialized)
1614 m32r_compute_frame_size (size);
1616 /* This is only for the human reader. */
1618 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
1620 current_frame_info.var_size,
1621 current_frame_info.reg_size / 4,
1622 current_frame_info.args_size,
1623 current_frame_info.extra_size);
1626 /* Output RTL to pop register REGNO from the stack. */
1633 x = emit_insn (gen_movsi_pop (gen_rtx_REG (Pmode, regno),
1634 stack_pointer_rtx));
1636 = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
1639 /* Expand the m32r epilogue as a series of insns. */
1642 m32r_expand_epilogue (void)
1645 int noepilogue = FALSE;
1648 gcc_assert (current_frame_info.initialized);
1649 total_size = current_frame_info.total_size;
1651 if (total_size == 0)
1653 rtx insn = get_last_insn ();
1655 /* If the last insn was a BARRIER, we don't have to write any code
1656 because a jump (aka return) was put there. */
1657 if (insn && NOTE_P (insn))
1658 insn = prev_nonnote_insn (insn);
1659 if (insn && BARRIER_P (insn))
1665 unsigned int var_size = current_frame_info.var_size;
1666 unsigned int args_size = current_frame_info.args_size;
1667 unsigned int gmask = current_frame_info.gmask;
1668 int can_trust_sp_p = !cfun->calls_alloca;
1670 if (flag_exceptions)
1671 emit_insn (gen_blockage ());
1673 /* The first thing to do is point the sp at the bottom of the register
1677 unsigned int reg_offset = var_size + args_size;
1679 if (reg_offset == 0)
1680 ; /* Nothing to do. */
1681 else if (reg_offset < 32768)
1682 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1683 GEN_INT (reg_offset)));
1686 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1688 emit_insn (gen_movsi (tmp, GEN_INT (reg_offset)));
1689 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1693 else if (frame_pointer_needed)
1695 unsigned int reg_offset = var_size + args_size;
1697 if (reg_offset == 0)
1698 emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx));
1699 else if (reg_offset < 32768)
1700 emit_insn (gen_addsi3 (stack_pointer_rtx, frame_pointer_rtx,
1701 GEN_INT (reg_offset)));
1704 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1706 emit_insn (gen_movsi (tmp, GEN_INT (reg_offset)));
1707 emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx));
1708 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1715 if (current_frame_info.save_lr)
1716 pop (RETURN_ADDR_REGNUM);
1718 /* Restore any saved registers, in reverse order of course. */
1719 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1720 for (regno = M32R_MAX_INT_REGS - 1; regno >= 0; --regno)
1722 if ((gmask & (1L << regno)) != 0)
1726 if (current_frame_info.save_fp)
1727 pop (FRAME_POINTER_REGNUM);
1729 /* Remove varargs area if present. */
1730 if (current_frame_info.pretend_size != 0)
1731 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1732 GEN_INT (current_frame_info.pretend_size)));
1734 emit_insn (gen_blockage ());
1738 /* Do any necessary cleanup after a function to restore stack, frame,
1742 m32r_output_function_epilogue (FILE * file ATTRIBUTE_UNUSED,
1743 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1745 /* Reset state info for each function. */
1746 current_frame_info = zero_frame_info;
1747 m32r_compute_function_type (NULL_TREE);
1750 /* Return nonzero if this function is known to have a null or 1 instruction
1754 direct_return (void)
1756 if (!reload_completed)
1759 if (M32R_INTERRUPT_P (m32r_compute_function_type (current_function_decl)))
1762 if (! current_frame_info.initialized)
1763 m32r_compute_frame_size (get_frame_size ());
1765 return current_frame_info.total_size == 0;
1772 m32r_legitimate_pic_operand_p (rtx x)
1774 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1777 if (GET_CODE (x) == CONST
1778 && GET_CODE (XEXP (x, 0)) == PLUS
1779 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
1780 || GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF)
1781 && (CONST_INT_P (XEXP (XEXP (x, 0), 1))))
1788 m32r_legitimize_pic_address (rtx orig, rtx reg)
1791 printf("m32r_legitimize_pic_address()\n");
1794 if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
1796 rtx pic_ref, address;
1802 gcc_assert (!reload_in_progress && !reload_completed);
1803 reg = gen_reg_rtx (Pmode);
1809 address = gen_reg_rtx (Pmode);
1813 crtl->uses_pic_offset_table = 1;
1815 if (GET_CODE (orig) == LABEL_REF
1816 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
1818 emit_insn (gen_gotoff_load_addr (reg, orig));
1819 emit_insn (gen_addsi3 (reg, reg, pic_offset_table_rtx));
1823 emit_insn (gen_pic_load_addr (address, orig));
1825 emit_insn (gen_addsi3 (address, address, pic_offset_table_rtx));
1826 pic_ref = gen_const_mem (Pmode, address);
1827 insn = emit_move_insn (reg, pic_ref);
1829 /* Put a REG_EQUAL note on this insn, so that it can be optimized
1831 set_unique_reg_note (insn, REG_EQUAL, orig);
1835 else if (GET_CODE (orig) == CONST)
1839 if (GET_CODE (XEXP (orig, 0)) == PLUS
1840 && XEXP (XEXP (orig, 0), 1) == pic_offset_table_rtx)
1845 gcc_assert (!reload_in_progress && !reload_completed);
1846 reg = gen_reg_rtx (Pmode);
1849 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1851 base = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), reg);
1853 offset = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), NULL_RTX);
1855 offset = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), reg);
1860 if (CONST_INT_P (offset))
1862 if (INT16_P (INTVAL (offset)))
1863 return plus_constant (base, INTVAL (offset));
1866 gcc_assert (! reload_in_progress && ! reload_completed);
1867 offset = force_reg (Pmode, offset);
1871 return gen_rtx_PLUS (Pmode, base, offset);
1878 m32r_legitimize_address (rtx x, rtx orig_x ATTRIBUTE_UNUSED,
1879 enum machine_mode mode ATTRIBUTE_UNUSED)
1882 return m32r_legitimize_pic_address (x, NULL_RTX);
1887 /* Nested function support. */
1889 /* Emit RTL insns to initialize the variable parts of a trampoline.
1890 FNADDR is an RTX for the address of the function's pure code.
1891 CXT is an RTX for the static chain value for the function. */
1894 m32r_initialize_trampoline (rtx tramp ATTRIBUTE_UNUSED,
1895 rtx fnaddr ATTRIBUTE_UNUSED,
1896 rtx cxt ATTRIBUTE_UNUSED)
1901 m32r_file_start (void)
1903 default_file_start ();
1905 if (flag_verbose_asm)
1906 fprintf (asm_out_file,
1907 "%s M32R/D special options: -G " HOST_WIDE_INT_PRINT_UNSIGNED "\n",
1908 ASM_COMMENT_START, g_switch_value);
1910 if (TARGET_LITTLE_ENDIAN)
1911 fprintf (asm_out_file, "\t.little\n");
1914 /* Print operand X (an rtx) in assembler syntax to file FILE.
1915 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1916 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1919 m32r_print_operand (FILE * file, rtx x, int code)
1925 /* The 's' and 'p' codes are used by output_block_move() to
1926 indicate post-increment 's'tores and 'p're-increment loads. */
1929 fprintf (file, "@+%s", reg_names [REGNO (x)]);
1931 output_operand_lossage ("invalid operand to %%s code");
1936 fprintf (file, "@%s+", reg_names [REGNO (x)]);
1938 output_operand_lossage ("invalid operand to %%p code");
1942 /* Write second word of DImode or DFmode reference,
1943 register or memory. */
1945 fputs (reg_names[REGNO (x)+1], file);
1948 fprintf (file, "@(");
1949 /* Handle possible auto-increment. Since it is pre-increment and
1950 we have already done it, we can just use an offset of four. */
1951 /* ??? This is taken from rs6000.c I think. I don't think it is
1952 currently necessary, but keep it around. */
1953 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1954 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1955 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
1957 output_address (plus_constant (XEXP (x, 0), 4));
1961 output_operand_lossage ("invalid operand to %%R code");
1964 case 'H' : /* High word. */
1965 case 'L' : /* Low word. */
1968 /* L = least significant word, H = most significant word. */
1969 if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L'))
1970 fputs (reg_names[REGNO (x)], file);
1972 fputs (reg_names[REGNO (x)+1], file);
1974 else if (CONST_INT_P (x)
1975 || GET_CODE (x) == CONST_DOUBLE)
1979 split_double (x, &first, &second);
1980 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
1981 code == 'L' ? INTVAL (first) : INTVAL (second));
1984 output_operand_lossage ("invalid operand to %%H/%%L code");
1991 if (GET_CODE (x) != CONST_DOUBLE
1992 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
1993 fatal_insn ("bad insn for 'A'", x);
1995 real_to_decimal (str, CONST_DOUBLE_REAL_VALUE (x), sizeof (str), 0, 1);
1996 fprintf (file, "%s", str);
2000 case 'B' : /* Bottom half. */
2001 case 'T' : /* Top half. */
2002 /* Output the argument to a `seth' insn (sets the Top half-word).
2003 For constants output arguments to a seth/or3 pair to set Top and
2004 Bottom halves. For symbols output arguments to a seth/add3 pair to
2005 set Top and Bottom halves. The difference exists because for
2006 constants seth/or3 is more readable but for symbols we need to use
2007 the same scheme as `ld' and `st' insns (16-bit addend is signed). */
2008 switch (GET_CODE (x))
2015 split_double (x, &first, &second);
2016 x = WORDS_BIG_ENDIAN ? second : first;
2017 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2019 ? INTVAL (x) & 0xffff
2020 : (INTVAL (x) >> 16) & 0xffff));
2026 && small_data_operand (x, VOIDmode))
2028 fputs ("sda(", file);
2029 output_addr_const (file, x);
2035 fputs (code == 'T' ? "shigh(" : "low(", file);
2036 output_addr_const (file, x);
2040 output_operand_lossage ("invalid operand to %%T/%%B code");
2047 /* Output a load/store with update indicator if appropriate. */
2050 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2051 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2055 output_operand_lossage ("invalid operand to %%U code");
2059 /* Print a constant value negated. */
2060 if (CONST_INT_P (x))
2061 output_addr_const (file, GEN_INT (- INTVAL (x)));
2063 output_operand_lossage ("invalid operand to %%N code");
2067 /* Print a const_int in hex. Used in comments. */
2068 if (CONST_INT_P (x))
2069 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
2073 fputs (IMMEDIATE_PREFIX, file);
2077 /* Do nothing special. */
2082 output_operand_lossage ("invalid operand output code");
2085 switch (GET_CODE (x))
2088 fputs (reg_names[REGNO (x)], file);
2093 if (GET_CODE (addr) == PRE_INC)
2095 if (!REG_P (XEXP (addr, 0)))
2096 fatal_insn ("pre-increment address is not a register", x);
2098 fprintf (file, "@+%s", reg_names[REGNO (XEXP (addr, 0))]);
2100 else if (GET_CODE (addr) == PRE_DEC)
2102 if (!REG_P (XEXP (addr, 0)))
2103 fatal_insn ("pre-decrement address is not a register", x);
2105 fprintf (file, "@-%s", reg_names[REGNO (XEXP (addr, 0))]);
2107 else if (GET_CODE (addr) == POST_INC)
2109 if (!REG_P (XEXP (addr, 0)))
2110 fatal_insn ("post-increment address is not a register", x);
2112 fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]);
2117 output_address (XEXP (x, 0));
2123 /* We handle SFmode constants here as output_addr_const doesn't. */
2124 if (GET_MODE (x) == SFmode)
2129 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
2130 REAL_VALUE_TO_TARGET_SINGLE (d, l);
2131 fprintf (file, "0x%08lx", l);
2135 /* Fall through. Let output_addr_const deal with it. */
2138 output_addr_const (file, x);
2143 /* Print a memory address as an operand to reference that memory location. */
2146 m32r_print_operand_address (FILE * file, rtx addr)
2152 switch (GET_CODE (addr))
2155 fputs (reg_names[REGNO (addr)], file);
2159 if (CONST_INT_P (XEXP (addr, 0)))
2160 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
2161 else if (CONST_INT_P (XEXP (addr, 1)))
2162 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
2164 base = XEXP (addr, 0), index = XEXP (addr, 1);
2167 /* Print the offset first (if present) to conform to the manual. */
2171 fprintf (file, "%d,", offset);
2172 fputs (reg_names[REGNO (base)], file);
2174 /* The chip doesn't support this, but left in for generality. */
2175 else if (REG_P (index))
2176 fprintf (file, "%s,%s",
2177 reg_names[REGNO (base)], reg_names[REGNO (index)]);
2178 /* Not sure this can happen, but leave in for now. */
2179 else if (GET_CODE (index) == SYMBOL_REF)
2181 output_addr_const (file, index);
2183 fputs (reg_names[REGNO (base)], file);
2186 fatal_insn ("bad address", addr);
2188 else if (GET_CODE (base) == LO_SUM)
2190 gcc_assert (!index && REG_P (XEXP (base, 0)));
2191 if (small_data_operand (XEXP (base, 1), VOIDmode))
2192 fputs ("sda(", file);
2194 fputs ("low(", file);
2195 output_addr_const (file, plus_constant (XEXP (base, 1), offset));
2197 fputs (reg_names[REGNO (XEXP (base, 0))], file);
2200 fatal_insn ("bad address", addr);
2204 if (!REG_P (XEXP (addr, 0)))
2205 fatal_insn ("lo_sum not of register", addr);
2206 if (small_data_operand (XEXP (addr, 1), VOIDmode))
2207 fputs ("sda(", file);
2209 fputs ("low(", file);
2210 output_addr_const (file, XEXP (addr, 1));
2212 fputs (reg_names[REGNO (XEXP (addr, 0))], file);
2215 case PRE_INC : /* Assume SImode. */
2216 fprintf (file, "+%s", reg_names[REGNO (XEXP (addr, 0))]);
2219 case PRE_DEC : /* Assume SImode. */
2220 fprintf (file, "-%s", reg_names[REGNO (XEXP (addr, 0))]);
2223 case POST_INC : /* Assume SImode. */
2224 fprintf (file, "%s+", reg_names[REGNO (XEXP (addr, 0))]);
2228 output_addr_const (file, addr);
2233 /* Return true if the operands are the constants 0 and 1. */
2236 zero_and_one (rtx operand1, rtx operand2)
2239 CONST_INT_P (operand1)
2240 && CONST_INT_P (operand2)
2241 && ( ((INTVAL (operand1) == 0) && (INTVAL (operand2) == 1))
2242 ||((INTVAL (operand1) == 1) && (INTVAL (operand2) == 0)));
2245 /* Generate the correct assembler code to handle the conditional loading of a
2246 value into a register. It is known that the operands satisfy the
2247 conditional_move_operand() function above. The destination is operand[0].
2248 The condition is operand [1]. The 'true' value is operand [2] and the
2249 'false' value is operand [3]. */
2252 emit_cond_move (rtx * operands, rtx insn ATTRIBUTE_UNUSED)
2254 static char buffer [100];
2255 const char * dest = reg_names [REGNO (operands [0])];
2259 /* Destination must be a register. */
2260 gcc_assert (REG_P (operands [0]));
2261 gcc_assert (conditional_move_operand (operands [2], SImode));
2262 gcc_assert (conditional_move_operand (operands [3], SImode));
2264 /* Check to see if the test is reversed. */
2265 if (GET_CODE (operands [1]) == NE)
2267 rtx tmp = operands [2];
2268 operands [2] = operands [3];
2272 sprintf (buffer, "mvfc %s, cbr", dest);
2274 /* If the true value was '0' then we need to invert the results of the move. */
2275 if (INTVAL (operands [2]) == 0)
2276 sprintf (buffer + strlen (buffer), "\n\txor3 %s, %s, #1",
2282 /* Returns true if the registers contained in the two
2283 rtl expressions are different. */
2286 m32r_not_same_reg (rtx a, rtx b)
2291 while (GET_CODE (a) == SUBREG)
2297 while (GET_CODE (b) == SUBREG)
2303 return reg_a != reg_b;
2308 m32r_function_symbol (const char *name)
2310 int extra_flags = 0;
2311 enum m32r_model model;
2312 rtx sym = gen_rtx_SYMBOL_REF (Pmode, name);
2314 if (TARGET_MODEL_SMALL)
2315 model = M32R_MODEL_SMALL;
2316 else if (TARGET_MODEL_MEDIUM)
2317 model = M32R_MODEL_MEDIUM;
2318 else if (TARGET_MODEL_LARGE)
2319 model = M32R_MODEL_LARGE;
2321 gcc_unreachable (); /* Shouldn't happen. */
2322 extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT;
2325 SYMBOL_REF_FLAGS (sym) |= extra_flags;
2330 /* Use a library function to move some bytes. */
2333 block_move_call (rtx dest_reg, rtx src_reg, rtx bytes_rtx)
2335 /* We want to pass the size as Pmode, which will normally be SImode
2336 but will be DImode if we are using 64-bit longs and pointers. */
2337 if (GET_MODE (bytes_rtx) != VOIDmode
2338 && GET_MODE (bytes_rtx) != Pmode)
2339 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
2341 emit_library_call (m32r_function_symbol ("memcpy"), 0,
2342 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
2343 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
2344 TYPE_UNSIGNED (sizetype)),
2345 TYPE_MODE (sizetype));
2348 /* Expand string/block move operations.
2350 operands[0] is the pointer to the destination.
2351 operands[1] is the pointer to the source.
2352 operands[2] is the number of bytes to move.
2353 operands[3] is the alignment.
2355 Returns 1 upon success, 0 otherwise. */
2358 m32r_expand_block_move (rtx operands[])
2360 rtx orig_dst = operands[0];
2361 rtx orig_src = operands[1];
2362 rtx bytes_rtx = operands[2];
2363 rtx align_rtx = operands[3];
2364 int constp = CONST_INT_P (bytes_rtx);
2365 HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
2366 int align = INTVAL (align_rtx);
2371 if (constp && bytes <= 0)
2374 /* Move the address into scratch registers. */
2375 dst_reg = copy_addr_to_reg (XEXP (orig_dst, 0));
2376 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2378 if (align > UNITS_PER_WORD)
2379 align = UNITS_PER_WORD;
2381 /* If we prefer size over speed, always use a function call.
2382 If we do not know the size, use a function call.
2383 If the blocks are not word aligned, use a function call. */
2384 if (optimize_size || ! constp || align != UNITS_PER_WORD)
2386 block_move_call (dst_reg, src_reg, bytes_rtx);
2390 leftover = bytes % MAX_MOVE_BYTES;
2393 /* If necessary, generate a loop to handle the bulk of the copy. */
2396 rtx label = NULL_RTX;
2397 rtx final_src = NULL_RTX;
2398 rtx at_a_time = GEN_INT (MAX_MOVE_BYTES);
2399 rtx rounded_total = GEN_INT (bytes);
2400 rtx new_dst_reg = gen_reg_rtx (SImode);
2401 rtx new_src_reg = gen_reg_rtx (SImode);
2403 /* If we are going to have to perform this loop more than
2404 once, then generate a label and compute the address the
2405 source register will contain upon completion of the final
2407 if (bytes > MAX_MOVE_BYTES)
2409 final_src = gen_reg_rtx (Pmode);
2412 emit_insn (gen_addsi3 (final_src, src_reg, rounded_total));
2415 emit_insn (gen_movsi (final_src, rounded_total));
2416 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
2419 label = gen_label_rtx ();
2423 /* It is known that output_block_move() will update src_reg to point
2424 to the word after the end of the source block, and dst_reg to point
2425 to the last word of the destination block, provided that the block
2426 is MAX_MOVE_BYTES long. */
2427 emit_insn (gen_movmemsi_internal (dst_reg, src_reg, at_a_time,
2428 new_dst_reg, new_src_reg));
2429 emit_move_insn (dst_reg, new_dst_reg);
2430 emit_move_insn (src_reg, new_src_reg);
2431 emit_insn (gen_addsi3 (dst_reg, dst_reg, GEN_INT (4)));
2433 if (bytes > MAX_MOVE_BYTES)
2435 rtx test = gen_rtx_NE (VOIDmode, src_reg, final_src);
2436 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
2441 emit_insn (gen_movmemsi_internal (dst_reg, src_reg, GEN_INT (leftover),
2442 gen_reg_rtx (SImode),
2443 gen_reg_rtx (SImode)));
2448 /* Emit load/stores for a small constant word aligned block_move.
2450 operands[0] is the memory address of the destination.
2451 operands[1] is the memory address of the source.
2452 operands[2] is the number of bytes to move.
2453 operands[3] is a temp register.
2454 operands[4] is a temp register. */
2457 m32r_output_block_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[])
2459 HOST_WIDE_INT bytes = INTVAL (operands[2]);
2463 gcc_assert (bytes >= 1 && bytes <= MAX_MOVE_BYTES);
2465 /* We do not have a post-increment store available, so the first set of
2466 stores are done without any increment, then the remaining ones can use
2467 the pre-increment addressing mode.
2469 Note: expand_block_move() also relies upon this behavior when building
2470 loops to copy large blocks. */
2479 output_asm_insn ("ld\t%5, %p1", operands);
2480 output_asm_insn ("ld\t%6, %p1", operands);
2481 output_asm_insn ("st\t%5, @%0", operands);
2482 output_asm_insn ("st\t%6, %s0", operands);
2486 output_asm_insn ("ld\t%5, %p1", operands);
2487 output_asm_insn ("ld\t%6, %p1", operands);
2488 output_asm_insn ("st\t%5, %s0", operands);
2489 output_asm_insn ("st\t%6, %s0", operands);
2494 else if (bytes >= 4)
2499 output_asm_insn ("ld\t%5, %p1", operands);
2502 output_asm_insn ("ld\t%6, %p1", operands);
2505 output_asm_insn ("st\t%5, @%0", operands);
2507 output_asm_insn ("st\t%5, %s0", operands);
2513 /* Get the entire next word, even though we do not want all of it.
2514 The saves us from doing several smaller loads, and we assume that
2515 we cannot cause a page fault when at least part of the word is in
2516 valid memory [since we don't get called if things aren't properly
2518 int dst_offset = first_time ? 0 : 4;
2519 /* The amount of increment we have to make to the
2520 destination pointer. */
2521 int dst_inc_amount = dst_offset + bytes - 4;
2522 /* The same for the source pointer. */
2523 int src_inc_amount = bytes;
2527 /* If got_extra is true then we have already loaded
2528 the next word as part of loading and storing the previous word. */
2530 output_asm_insn ("ld\t%6, @%1", operands);
2536 output_asm_insn ("sra3\t%5, %6, #16", operands);
2537 my_operands[0] = operands[5];
2538 my_operands[1] = GEN_INT (dst_offset);
2539 my_operands[2] = operands[0];
2540 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands);
2542 /* If there is a byte left to store then increment the
2543 destination address and shift the contents of the source
2544 register down by 8 bits. We could not do the address
2545 increment in the store half word instruction, because it does
2546 not have an auto increment mode. */
2547 if (bytes > 0) /* assert (bytes == 1) */
2558 my_operands[0] = operands[6];
2559 my_operands[1] = GEN_INT (last_shift);
2560 output_asm_insn ("srai\t%0, #%1", my_operands);
2561 my_operands[0] = operands[6];
2562 my_operands[1] = GEN_INT (dst_offset);
2563 my_operands[2] = operands[0];
2564 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands);
2567 /* Update the destination pointer if needed. We have to do
2568 this so that the patterns matches what we output in this
2571 && !find_reg_note (insn, REG_UNUSED, operands[0]))
2573 my_operands[0] = operands[0];
2574 my_operands[1] = GEN_INT (dst_inc_amount);
2575 output_asm_insn ("addi\t%0, #%1", my_operands);
2578 /* Update the source pointer if needed. We have to do this
2579 so that the patterns matches what we output in this
2582 && !find_reg_note (insn, REG_UNUSED, operands[1]))
2584 my_operands[0] = operands[1];
2585 my_operands[1] = GEN_INT (src_inc_amount);
2586 output_asm_insn ("addi\t%0, #%1", my_operands);
2596 /* Return true if using NEW_REG in place of OLD_REG is ok. */
2599 m32r_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
2600 unsigned int new_reg)
2602 /* Interrupt routines can't clobber any register that isn't already used. */
2603 if (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl))
2604 && !df_regs_ever_live_p (new_reg))
2611 m32r_return_addr (int count)
2616 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);