1 /* Subroutines used for code generation on the Renesas M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
3 2005, 2007, 2008 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
33 #include "insn-attr.h"
40 #include "integrate.h"
43 #include "target-def.h"
44 #include "tm-constrs.h"
46 /* Save the operands last given to a compare for use when we
47 generate a scc or bcc insn. */
48 rtx m32r_compare_op0, m32r_compare_op1;
50 /* Array of valid operand punctuation characters. */
51 char m32r_punct_chars[256];
53 /* Selected code model. */
54 enum m32r_model m32r_model = M32R_MODEL_DEFAULT;
56 /* Selected SDA support. */
57 enum m32r_sdata m32r_sdata = M32R_SDATA_DEFAULT;
59 /* Machine-specific symbol_ref flags. */
60 #define SYMBOL_FLAG_MODEL_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT
61 #define SYMBOL_REF_MODEL(X) \
62 ((enum m32r_model) ((SYMBOL_REF_FLAGS (X) >> SYMBOL_FLAG_MODEL_SHIFT) & 3))
64 /* For string literals, etc. */
65 #define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.')
67 /* Forward declaration. */
68 static bool m32r_handle_option (size_t, const char *, int);
69 static void init_reg_tables (void);
70 static void block_move_call (rtx, rtx, rtx);
71 static int m32r_is_insn (rtx);
72 const struct attribute_spec m32r_attribute_table[];
73 static rtx m32r_legitimize_address (rtx, rtx, enum machine_mode);
74 static tree m32r_handle_model_attribute (tree *, tree, tree, int, bool *);
75 static void m32r_output_function_prologue (FILE *, HOST_WIDE_INT);
76 static void m32r_output_function_epilogue (FILE *, HOST_WIDE_INT);
78 static void m32r_file_start (void);
80 static int m32r_adjust_priority (rtx, int);
81 static int m32r_issue_rate (void);
83 static void m32r_encode_section_info (tree, rtx, int);
84 static bool m32r_in_small_data_p (const_tree);
85 static bool m32r_return_in_memory (const_tree, const_tree);
86 static void m32r_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
88 static void init_idents (void);
89 static bool m32r_rtx_costs (rtx, int, int, int *, bool speed);
90 static bool m32r_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
92 static int m32r_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
95 /* Initialize the GCC target structure. */
96 #undef TARGET_ATTRIBUTE_TABLE
97 #define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
99 #undef TARGET_LEGITIMIZE_ADDRESS
100 #define TARGET_LEGITIMIZE_ADDRESS m32r_legitimize_address
102 #undef TARGET_ASM_ALIGNED_HI_OP
103 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
104 #undef TARGET_ASM_ALIGNED_SI_OP
105 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
107 #undef TARGET_ASM_FUNCTION_PROLOGUE
108 #define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue
109 #undef TARGET_ASM_FUNCTION_EPILOGUE
110 #define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
112 #undef TARGET_ASM_FILE_START
113 #define TARGET_ASM_FILE_START m32r_file_start
115 #undef TARGET_SCHED_ADJUST_PRIORITY
116 #define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
117 #undef TARGET_SCHED_ISSUE_RATE
118 #define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
120 #undef TARGET_DEFAULT_TARGET_FLAGS
121 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_CPU_DEFAULT
122 #undef TARGET_HANDLE_OPTION
123 #define TARGET_HANDLE_OPTION m32r_handle_option
125 #undef TARGET_ENCODE_SECTION_INFO
126 #define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info
127 #undef TARGET_IN_SMALL_DATA_P
128 #define TARGET_IN_SMALL_DATA_P m32r_in_small_data_p
130 #undef TARGET_RTX_COSTS
131 #define TARGET_RTX_COSTS m32r_rtx_costs
132 #undef TARGET_ADDRESS_COST
133 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
135 #undef TARGET_PROMOTE_PROTOTYPES
136 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
137 #undef TARGET_RETURN_IN_MEMORY
138 #define TARGET_RETURN_IN_MEMORY m32r_return_in_memory
139 #undef TARGET_SETUP_INCOMING_VARARGS
140 #define TARGET_SETUP_INCOMING_VARARGS m32r_setup_incoming_varargs
141 #undef TARGET_MUST_PASS_IN_STACK
142 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
143 #undef TARGET_PASS_BY_REFERENCE
144 #define TARGET_PASS_BY_REFERENCE m32r_pass_by_reference
145 #undef TARGET_ARG_PARTIAL_BYTES
146 #define TARGET_ARG_PARTIAL_BYTES m32r_arg_partial_bytes
148 struct gcc_target targetm = TARGET_INITIALIZER;
150 /* Implement TARGET_HANDLE_OPTION. */
153 m32r_handle_option (size_t code, const char *arg, int value)
158 target_flags &= ~(MASK_M32R2 | MASK_M32RX);
162 if (strcmp (arg, "small") == 0)
163 m32r_model = M32R_MODEL_SMALL;
164 else if (strcmp (arg, "medium") == 0)
165 m32r_model = M32R_MODEL_MEDIUM;
166 else if (strcmp (arg, "large") == 0)
167 m32r_model = M32R_MODEL_LARGE;
173 if (strcmp (arg, "none") == 0)
174 m32r_sdata = M32R_SDATA_NONE;
175 else if (strcmp (arg, "sdata") == 0)
176 m32r_sdata = M32R_SDATA_SDATA;
177 else if (strcmp (arg, "use") == 0)
178 m32r_sdata = M32R_SDATA_USE;
183 case OPT_mno_flush_func:
184 m32r_cache_flush_func = NULL;
187 case OPT_mflush_trap_:
190 case OPT_mno_flush_trap:
191 m32r_cache_flush_trap = -1;
199 /* Called by OVERRIDE_OPTIONS to initialize various things. */
206 /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */
207 memset (m32r_punct_chars, 0, sizeof (m32r_punct_chars));
208 m32r_punct_chars['#'] = 1;
209 m32r_punct_chars['@'] = 1; /* ??? no longer used */
211 /* Provide default value if not specified. */
213 g_switch_value = SDATA_DEFAULT_SIZE;
216 /* Vectors to keep interesting information about registers where it can easily
217 be got. We use to use the actual mode value as the bit number, but there
218 is (or may be) more than 32 modes now. Instead we use two tables: one
219 indexed by hard register number, and one indexed by mode. */
221 /* The purpose of m32r_mode_class is to shrink the range of modes so that
222 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
223 mapped into one m32r_mode_class mode. */
228 S_MODE, D_MODE, T_MODE, O_MODE,
229 SF_MODE, DF_MODE, TF_MODE, OF_MODE, A_MODE
232 /* Modes for condition codes. */
233 #define C_MODES (1 << (int) C_MODE)
235 /* Modes for single-word and smaller quantities. */
236 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
238 /* Modes for double-word and smaller quantities. */
239 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
241 /* Modes for quad-word and smaller quantities. */
242 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
244 /* Modes for accumulators. */
245 #define A_MODES (1 << (int) A_MODE)
247 /* Value is 1 if register/mode pair is acceptable on arc. */
249 const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
251 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
252 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
253 S_MODES, C_MODES, A_MODES, A_MODES
256 unsigned int m32r_mode_class [NUM_MACHINE_MODES];
258 enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
261 init_reg_tables (void)
265 for (i = 0; i < NUM_MACHINE_MODES; i++)
267 switch (GET_MODE_CLASS (i))
270 case MODE_PARTIAL_INT:
271 case MODE_COMPLEX_INT:
272 if (GET_MODE_SIZE (i) <= 4)
273 m32r_mode_class[i] = 1 << (int) S_MODE;
274 else if (GET_MODE_SIZE (i) == 8)
275 m32r_mode_class[i] = 1 << (int) D_MODE;
276 else if (GET_MODE_SIZE (i) == 16)
277 m32r_mode_class[i] = 1 << (int) T_MODE;
278 else if (GET_MODE_SIZE (i) == 32)
279 m32r_mode_class[i] = 1 << (int) O_MODE;
281 m32r_mode_class[i] = 0;
284 case MODE_COMPLEX_FLOAT:
285 if (GET_MODE_SIZE (i) <= 4)
286 m32r_mode_class[i] = 1 << (int) SF_MODE;
287 else if (GET_MODE_SIZE (i) == 8)
288 m32r_mode_class[i] = 1 << (int) DF_MODE;
289 else if (GET_MODE_SIZE (i) == 16)
290 m32r_mode_class[i] = 1 << (int) TF_MODE;
291 else if (GET_MODE_SIZE (i) == 32)
292 m32r_mode_class[i] = 1 << (int) OF_MODE;
294 m32r_mode_class[i] = 0;
297 m32r_mode_class[i] = 1 << (int) C_MODE;
300 m32r_mode_class[i] = 0;
305 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
308 m32r_regno_reg_class[i] = GENERAL_REGS;
309 else if (i == ARG_POINTER_REGNUM)
310 m32r_regno_reg_class[i] = GENERAL_REGS;
312 m32r_regno_reg_class[i] = NO_REGS;
316 /* M32R specific attribute support.
318 interrupt - for interrupt functions
320 model - select code model used to access object
322 small: addresses use 24 bits, use bl to make calls
323 medium: addresses use 32 bits, use bl to make calls
324 large: addresses use 32 bits, use seth/add3/jl to make calls
326 Grep for MODEL in m32r.h for more info. */
328 static tree small_ident1;
329 static tree small_ident2;
330 static tree medium_ident1;
331 static tree medium_ident2;
332 static tree large_ident1;
333 static tree large_ident2;
338 if (small_ident1 == 0)
340 small_ident1 = get_identifier ("small");
341 small_ident2 = get_identifier ("__small__");
342 medium_ident1 = get_identifier ("medium");
343 medium_ident2 = get_identifier ("__medium__");
344 large_ident1 = get_identifier ("large");
345 large_ident2 = get_identifier ("__large__");
349 const struct attribute_spec m32r_attribute_table[] =
351 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
352 { "interrupt", 0, 0, true, false, false, NULL },
353 { "model", 1, 1, true, false, false, m32r_handle_model_attribute },
354 { NULL, 0, 0, false, false, false, NULL }
358 /* Handle an "model" attribute; arguments as in
359 struct attribute_spec.handler. */
361 m32r_handle_model_attribute (tree *node ATTRIBUTE_UNUSED, tree name,
362 tree args, int flags ATTRIBUTE_UNUSED,
368 arg = TREE_VALUE (args);
370 if (arg != small_ident1
371 && arg != small_ident2
372 && arg != medium_ident1
373 && arg != medium_ident2
374 && arg != large_ident1
375 && arg != large_ident2)
377 warning (OPT_Wattributes, "invalid argument of %qs attribute",
378 IDENTIFIER_POINTER (name));
379 *no_add_attrs = true;
385 /* Encode section information of DECL, which is either a VAR_DECL,
386 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
388 For the M32R we want to record:
390 - whether the object lives in .sdata/.sbss.
391 - what code model should be used to access the object
395 m32r_encode_section_info (tree decl, rtx rtl, int first)
399 enum m32r_model model;
401 default_encode_section_info (decl, rtl, first);
406 model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
413 id = TREE_VALUE (TREE_VALUE (model_attr));
415 if (id == small_ident1 || id == small_ident2)
416 model = M32R_MODEL_SMALL;
417 else if (id == medium_ident1 || id == medium_ident2)
418 model = M32R_MODEL_MEDIUM;
419 else if (id == large_ident1 || id == large_ident2)
420 model = M32R_MODEL_LARGE;
422 gcc_unreachable (); /* shouldn't happen */
426 if (TARGET_MODEL_SMALL)
427 model = M32R_MODEL_SMALL;
428 else if (TARGET_MODEL_MEDIUM)
429 model = M32R_MODEL_MEDIUM;
430 else if (TARGET_MODEL_LARGE)
431 model = M32R_MODEL_LARGE;
433 gcc_unreachable (); /* shouldn't happen */
435 extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT;
438 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
441 /* Only mark the object as being small data area addressable if
442 it hasn't been explicitly marked with a code model.
444 The user can explicitly put an object in the small data area with the
445 section attribute. If the object is in sdata/sbss and marked with a
446 code model do both [put the object in .sdata and mark it as being
447 addressed with a specific code model - don't mark it as being addressed
448 with an SDA reloc though]. This is ok and might be useful at times. If
449 the object doesn't fit the linker will give an error. */
452 m32r_in_small_data_p (const_tree decl)
456 if (TREE_CODE (decl) != VAR_DECL)
459 if (lookup_attribute ("model", DECL_ATTRIBUTES (decl)))
462 section = DECL_SECTION_NAME (decl);
465 const char *const name = TREE_STRING_POINTER (section);
466 if (strcmp (name, ".sdata") == 0 || strcmp (name, ".sbss") == 0)
471 if (! TREE_READONLY (decl) && ! TARGET_SDATA_NONE)
473 int size = int_size_in_bytes (TREE_TYPE (decl));
475 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
483 /* Do anything needed before RTL is emitted for each function. */
486 m32r_init_expanders (void)
488 /* ??? At one point there was code here. The function is left in
489 to make it easy to experiment. */
493 call_operand (rtx op, enum machine_mode mode)
495 if (GET_CODE (op) != MEM)
498 return call_address_operand (op, mode);
501 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */
504 small_data_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
506 if (! TARGET_SDATA_USE)
509 if (GET_CODE (op) == SYMBOL_REF)
510 return SYMBOL_REF_SMALL_P (op);
512 if (GET_CODE (op) == CONST
513 && GET_CODE (XEXP (op, 0)) == PLUS
514 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
515 && satisfies_constraint_J (XEXP (XEXP (op, 0), 1)))
516 return SYMBOL_REF_SMALL_P (XEXP (XEXP (op, 0), 0));
521 /* Return 1 if OP is a symbol that can use 24-bit addressing. */
524 addr24_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
531 if (GET_CODE (op) == LABEL_REF)
532 return TARGET_ADDR24;
534 if (GET_CODE (op) == SYMBOL_REF)
536 else if (GET_CODE (op) == CONST
537 && GET_CODE (XEXP (op, 0)) == PLUS
538 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
539 && satisfies_constraint_M (XEXP (XEXP (op, 0), 1)))
540 sym = XEXP (XEXP (op, 0), 0);
544 if (SYMBOL_REF_MODEL (sym) == M32R_MODEL_SMALL)
548 && (CONSTANT_POOL_ADDRESS_P (sym)
549 || LIT_NAME_P (XSTR (sym, 0))))
555 /* Return 1 if OP is a symbol that needs 32-bit addressing. */
558 addr32_operand (rtx op, enum machine_mode mode)
562 if (GET_CODE (op) == LABEL_REF)
563 return TARGET_ADDR32;
565 if (GET_CODE (op) == SYMBOL_REF)
567 else if (GET_CODE (op) == CONST
568 && GET_CODE (XEXP (op, 0)) == PLUS
569 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
570 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
572 sym = XEXP (XEXP (op, 0), 0);
576 return (! addr24_operand (sym, mode)
577 && ! small_data_operand (sym, mode));
580 /* Return 1 if OP is a function that can be called with the `bl' insn. */
583 call26_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
588 if (GET_CODE (op) == SYMBOL_REF)
589 return SYMBOL_REF_MODEL (op) != M32R_MODEL_LARGE;
591 return TARGET_CALL26;
594 /* Return 1 if OP is a DImode const we want to handle inline.
595 This must match the code in the movdi pattern.
596 It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER. */
599 easy_di_const (rtx op)
601 rtx high_rtx, low_rtx;
602 HOST_WIDE_INT high, low;
604 split_double (op, &high_rtx, &low_rtx);
605 high = INTVAL (high_rtx);
606 low = INTVAL (low_rtx);
607 /* Pick constants loadable with 2 16-bit `ldi' insns. */
608 if (high >= -128 && high <= 127
609 && low >= -128 && low <= 127)
614 /* Return 1 if OP is a DFmode const we want to handle inline.
615 This must match the code in the movdf pattern.
616 It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER. */
619 easy_df_const (rtx op)
624 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
625 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
626 if (l[0] == 0 && l[1] == 0)
628 if ((l[0] & 0xffff) == 0 && l[1] == 0)
633 /* Return 1 if OP is (mem (reg ...)).
634 This is used in insn length calcs. */
637 memreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
639 return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == REG;
642 /* Return nonzero if TYPE must be passed by indirect reference. */
645 m32r_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
646 enum machine_mode mode, const_tree type,
647 bool named ATTRIBUTE_UNUSED)
652 size = int_size_in_bytes (type);
654 size = GET_MODE_SIZE (mode);
656 return (size < 0 || size > 8);
661 /* X and Y are two things to compare using CODE. Emit the compare insn and
662 return the rtx for compare [arg0 of the if_then_else].
663 If need_compare is true then the comparison insn must be generated, rather
664 than being subsumed into the following branch instruction. */
667 gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare)
669 enum rtx_code compare_code;
670 enum rtx_code branch_code;
671 rtx cc_reg = gen_rtx_REG (CCmode, CARRY_REGNUM);
676 case EQ: compare_code = EQ; branch_code = NE; break;
677 case NE: compare_code = EQ; branch_code = EQ; break;
678 case LT: compare_code = LT; branch_code = NE; break;
679 case LE: compare_code = LT; branch_code = EQ; must_swap = 1; break;
680 case GT: compare_code = LT; branch_code = NE; must_swap = 1; break;
681 case GE: compare_code = LT; branch_code = EQ; break;
682 case LTU: compare_code = LTU; branch_code = NE; break;
683 case LEU: compare_code = LTU; branch_code = EQ; must_swap = 1; break;
684 case GTU: compare_code = LTU; branch_code = NE; must_swap = 1; break;
685 case GEU: compare_code = LTU; branch_code = EQ; break;
693 switch (compare_code)
696 if (satisfies_constraint_P (y) /* Reg equal to small const. */
699 rtx tmp = gen_reg_rtx (SImode);
701 emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y))));
705 else if (CONSTANT_P (y)) /* Reg equal to const. */
707 rtx tmp = force_reg (GET_MODE (x), y);
711 if (register_operand (y, SImode) /* Reg equal to reg. */
712 || y == const0_rtx) /* Reg equal to zero. */
714 emit_insn (gen_cmp_eqsi_insn (x, y));
716 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
721 if (register_operand (y, SImode)
722 || satisfies_constraint_P (y))
724 rtx tmp = gen_reg_rtx (SImode); /* Reg compared to reg. */
729 emit_insn (gen_cmp_ltsi_insn (x, y));
736 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
737 emit_insn (gen_cmp_ltsi_insn (x, tmp));
741 if (GET_CODE (y) == CONST_INT)
742 tmp = gen_rtx_PLUS (SImode, y, const1_rtx);
744 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
745 emit_insn (gen_cmp_ltsi_insn (x, tmp));
749 emit_insn (gen_cmp_ltsi_insn (x, y));
756 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
761 if (register_operand (y, SImode)
762 || satisfies_constraint_P (y))
764 rtx tmp = gen_reg_rtx (SImode); /* Reg (unsigned) compared to reg. */
769 emit_insn (gen_cmp_ltusi_insn (x, y));
776 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
777 emit_insn (gen_cmp_ltusi_insn (x, tmp));
781 if (GET_CODE (y) == CONST_INT)
782 tmp = gen_rtx_PLUS (SImode, y, const1_rtx);
784 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
785 emit_insn (gen_cmp_ltusi_insn (x, tmp));
789 emit_insn (gen_cmp_ltusi_insn (x, y));
796 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
806 /* Reg/reg equal comparison. */
807 if (compare_code == EQ
808 && register_operand (y, SImode))
809 return gen_rtx_fmt_ee (code, CCmode, x, y);
811 /* Reg/zero signed comparison. */
812 if ((compare_code == EQ || compare_code == LT)
814 return gen_rtx_fmt_ee (code, CCmode, x, y);
816 /* Reg/smallconst equal comparison. */
817 if (compare_code == EQ
818 && satisfies_constraint_P (y))
820 rtx tmp = gen_reg_rtx (SImode);
822 emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y))));
823 return gen_rtx_fmt_ee (code, CCmode, tmp, const0_rtx);
826 /* Reg/const equal comparison. */
827 if (compare_code == EQ
830 rtx tmp = force_reg (GET_MODE (x), y);
832 return gen_rtx_fmt_ee (code, CCmode, x, tmp);
839 y = force_reg (GET_MODE (x), y);
842 int ok_const = reg_or_int16_operand (y, GET_MODE (y));
845 y = force_reg (GET_MODE (x), y);
849 switch (compare_code)
852 emit_insn (gen_cmp_eqsi_insn (must_swap ? y : x, must_swap ? x : y));
855 emit_insn (gen_cmp_ltsi_insn (must_swap ? y : x, must_swap ? x : y));
858 emit_insn (gen_cmp_ltusi_insn (must_swap ? y : x, must_swap ? x : y));
865 return gen_rtx_fmt_ee (branch_code, VOIDmode, cc_reg, CONST0_RTX (CCmode));
868 /* Split a 2 word move (DI or DF) into component parts. */
871 gen_split_move_double (rtx operands[])
873 enum machine_mode mode = GET_MODE (operands[0]);
874 rtx dest = operands[0];
875 rtx src = operands[1];
878 /* We might have (SUBREG (MEM)) here, so just get rid of the
879 subregs to make this code simpler. It is safe to call
880 alter_subreg any time after reload. */
881 if (GET_CODE (dest) == SUBREG)
882 alter_subreg (&dest);
883 if (GET_CODE (src) == SUBREG)
887 if (GET_CODE (dest) == REG)
889 int dregno = REGNO (dest);
892 if (GET_CODE (src) == REG)
894 int sregno = REGNO (src);
896 int reverse = (dregno == sregno + 1);
898 /* We normally copy the low-numbered register first. However, if
899 the first register operand 0 is the same as the second register of
900 operand 1, we must copy in the opposite order. */
901 emit_insn (gen_rtx_SET (VOIDmode,
902 operand_subword (dest, reverse, TRUE, mode),
903 operand_subword (src, reverse, TRUE, mode)));
905 emit_insn (gen_rtx_SET (VOIDmode,
906 operand_subword (dest, !reverse, TRUE, mode),
907 operand_subword (src, !reverse, TRUE, mode)));
910 /* Reg = constant. */
911 else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE)
914 split_double (src, &words[0], &words[1]);
915 emit_insn (gen_rtx_SET (VOIDmode,
916 operand_subword (dest, 0, TRUE, mode),
919 emit_insn (gen_rtx_SET (VOIDmode,
920 operand_subword (dest, 1, TRUE, mode),
925 else if (GET_CODE (src) == MEM)
927 /* If the high-address word is used in the address, we must load it
928 last. Otherwise, load it first. */
930 = (refers_to_regno_p (dregno, dregno + 1, XEXP (src, 0), 0) != 0);
932 /* We used to optimize loads from single registers as
936 if r3 were not used subsequently. However, the REG_NOTES aren't
937 propagated correctly by the reload phase, and it can cause bad
938 code to be generated. We could still try:
940 ld r1,r3+; ld r2,r3; addi r3,-4
942 which saves 2 bytes and doesn't force longword alignment. */
943 emit_insn (gen_rtx_SET (VOIDmode,
944 operand_subword (dest, reverse, TRUE, mode),
945 adjust_address (src, SImode,
946 reverse * UNITS_PER_WORD)));
948 emit_insn (gen_rtx_SET (VOIDmode,
949 operand_subword (dest, !reverse, TRUE, mode),
950 adjust_address (src, SImode,
951 !reverse * UNITS_PER_WORD)));
958 /* We used to optimize loads from single registers as
962 if r3 were not used subsequently. However, the REG_NOTES aren't
963 propagated correctly by the reload phase, and it can cause bad
964 code to be generated. We could still try:
966 st r1,r3; st r2,+r3; addi r3,-4
968 which saves 2 bytes and doesn't force longword alignment. */
969 else if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
971 emit_insn (gen_rtx_SET (VOIDmode,
972 adjust_address (dest, SImode, 0),
973 operand_subword (src, 0, TRUE, mode)));
975 emit_insn (gen_rtx_SET (VOIDmode,
976 adjust_address (dest, SImode, UNITS_PER_WORD),
977 operand_subword (src, 1, TRUE, mode)));
990 m32r_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
991 tree type, bool named ATTRIBUTE_UNUSED)
995 (((mode == BLKmode && type)
996 ? (unsigned int) int_size_in_bytes (type)
997 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
1000 if (*cum >= M32R_MAX_PARM_REGS)
1002 else if (*cum + size > M32R_MAX_PARM_REGS)
1003 words = (*cum + size) - M32R_MAX_PARM_REGS;
1007 return words * UNITS_PER_WORD;
1010 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1013 m32r_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
1015 return m32r_pass_by_reference (NULL, TYPE_MODE (type), type, false);
1018 /* Do any needed setup for a variadic function. For the M32R, we must
1019 create a register parameter block, and then copy any anonymous arguments
1020 in registers to memory.
1022 CUM has not been updated for the last named argument which has type TYPE
1023 and mode MODE, and we rely on this fact. */
1026 m32r_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1027 tree type, int *pretend_size, int no_rtl)
1034 /* All BLKmode values are passed by reference. */
1035 gcc_assert (mode != BLKmode);
1037 first_anon_arg = (ROUND_ADVANCE_CUM (*cum, mode, type)
1038 + ROUND_ADVANCE_ARG (mode, type));
1040 if (first_anon_arg < M32R_MAX_PARM_REGS)
1042 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1043 int first_reg_offset = first_anon_arg;
1044 /* Size in words to "pretend" allocate. */
1045 int size = M32R_MAX_PARM_REGS - first_reg_offset;
1048 regblock = gen_frame_mem (BLKmode,
1049 plus_constant (arg_pointer_rtx,
1050 FIRST_PARM_OFFSET (0)));
1051 set_mem_alias_set (regblock, get_varargs_alias_set ());
1052 move_block_from_reg (first_reg_offset, regblock, size);
1054 *pretend_size = (size * UNITS_PER_WORD);
1059 /* Return true if INSN is real instruction bearing insn. */
1062 m32r_is_insn (rtx insn)
1064 return (INSN_P (insn)
1065 && GET_CODE (PATTERN (insn)) != USE
1066 && GET_CODE (PATTERN (insn)) != CLOBBER
1067 && GET_CODE (PATTERN (insn)) != ADDR_VEC);
1070 /* Increase the priority of long instructions so that the
1071 short instructions are scheduled ahead of the long ones. */
1074 m32r_adjust_priority (rtx insn, int priority)
1076 if (m32r_is_insn (insn)
1077 && get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1084 /* Indicate how many instructions can be issued at the same time.
1085 This is sort of a lie. The m32r can issue only 1 long insn at
1086 once, but it can issue 2 short insns. The default therefore is
1087 set at 2, but this can be overridden by the command line option
1091 m32r_issue_rate (void)
1093 return ((TARGET_LOW_ISSUE_RATE) ? 1 : 2);
1096 /* Cost functions. */
1099 m32r_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, int *total,
1100 bool speed ATTRIBUTE_UNUSED)
1104 /* Small integers are as cheap as registers. 4 byte values can be
1105 fetched as immediate constants - let's give that the cost of an
1108 if (INT16_P (INTVAL (x)))
1118 *total = COSTS_N_INSNS (1);
1125 split_double (x, &high, &low);
1126 *total = COSTS_N_INSNS (!INT16_P (INTVAL (high))
1127 + !INT16_P (INTVAL (low)));
1132 *total = COSTS_N_INSNS (3);
1139 *total = COSTS_N_INSNS (10);
1147 /* Type of function DECL.
1149 The result is cached. To reset the cache at the end of a function,
1150 call with DECL = NULL_TREE. */
1152 enum m32r_function_type
1153 m32r_compute_function_type (tree decl)
1156 static enum m32r_function_type fn_type = M32R_FUNCTION_UNKNOWN;
1157 /* Last function we were called for. */
1158 static tree last_fn = NULL_TREE;
1160 /* Resetting the cached value? */
1161 if (decl == NULL_TREE)
1163 fn_type = M32R_FUNCTION_UNKNOWN;
1164 last_fn = NULL_TREE;
1168 if (decl == last_fn && fn_type != M32R_FUNCTION_UNKNOWN)
1171 /* Compute function type. */
1172 fn_type = (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE
1173 ? M32R_FUNCTION_INTERRUPT
1174 : M32R_FUNCTION_NORMAL);
1179 \f/* Function prologue/epilogue handlers. */
1181 /* M32R stack frames look like:
1183 Before call After call
1184 +-----------------------+ +-----------------------+
1186 high | local variables, | | local variables, |
1187 mem | reg save area, etc. | | reg save area, etc. |
1189 +-----------------------+ +-----------------------+
1191 | arguments on stack. | | arguments on stack. |
1193 SP+0->+-----------------------+ +-----------------------+
1194 | reg parm save area, |
1195 | only created for |
1196 | variable argument |
1198 +-----------------------+
1199 | previous frame ptr |
1200 +-----------------------+
1202 | register save area |
1204 +-----------------------+
1206 +-----------------------+
1210 +-----------------------+
1212 | alloca allocations |
1214 +-----------------------+
1216 low | arguments on stack |
1218 SP+0->+-----------------------+
1221 1) The "reg parm save area" does not exist for non variable argument fns.
1222 2) The "reg parm save area" can be eliminated completely if we saved regs
1223 containing anonymous args separately but that complicates things too
1224 much (so it's not done).
1225 3) The return address is saved after the register save area so as to have as
1226 many insns as possible between the restoration of `lr' and the `jmp lr'. */
1228 /* Structure to be filled in by m32r_compute_frame_size with register
1229 save masks, and offsets for the current function. */
1230 struct m32r_frame_info
1232 unsigned int total_size; /* # bytes that the entire frame takes up. */
1233 unsigned int extra_size; /* # bytes of extra stuff. */
1234 unsigned int pretend_size; /* # bytes we push and pretend caller did. */
1235 unsigned int args_size; /* # bytes that outgoing arguments take up. */
1236 unsigned int reg_size; /* # bytes needed to store regs. */
1237 unsigned int var_size; /* # bytes that variables take up. */
1238 unsigned int gmask; /* Mask of saved gp registers. */
1239 unsigned int save_fp; /* Nonzero if fp must be saved. */
1240 unsigned int save_lr; /* Nonzero if lr (return addr) must be saved. */
1241 int initialized; /* Nonzero if frame size already calculated. */
1244 /* Current frame information calculated by m32r_compute_frame_size. */
1245 static struct m32r_frame_info current_frame_info;
1247 /* Zero structure to initialize current_frame_info. */
1248 static struct m32r_frame_info zero_frame_info;
1250 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1251 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1253 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1254 The return address and frame pointer are treated separately.
1255 Don't consider them here. */
1256 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1257 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1258 && (df_regs_ever_live_p (regno) && (!call_really_used_regs[regno] || interrupt_p)))
1260 #define MUST_SAVE_FRAME_POINTER (df_regs_ever_live_p (FRAME_POINTER_REGNUM))
1261 #define MUST_SAVE_RETURN_ADDR (df_regs_ever_live_p (RETURN_ADDR_REGNUM) || crtl->profile)
1263 #define SHORT_INSN_SIZE 2 /* Size of small instructions. */
1264 #define LONG_INSN_SIZE 4 /* Size of long instructions. */
1266 /* Return the bytes needed to compute the frame pointer from the current
1269 SIZE is the size needed for local variables. */
1272 m32r_compute_frame_size (int size) /* # of var. bytes allocated. */
1275 unsigned int total_size, var_size, args_size, pretend_size, extra_size;
1276 unsigned int reg_size, frame_size;
1278 enum m32r_function_type fn_type;
1280 int pic_reg_used = flag_pic && (crtl->uses_pic_offset_table
1283 var_size = M32R_STACK_ALIGN (size);
1284 args_size = M32R_STACK_ALIGN (crtl->outgoing_args_size);
1285 pretend_size = crtl->args.pretend_args_size;
1286 extra_size = FIRST_PARM_OFFSET (0);
1287 total_size = extra_size + pretend_size + args_size + var_size;
1291 /* See if this is an interrupt handler. Call used registers must be saved
1293 fn_type = m32r_compute_function_type (current_function_decl);
1294 interrupt_p = M32R_INTERRUPT_P (fn_type);
1296 /* Calculate space needed for registers. */
1297 for (regno = 0; regno < M32R_MAX_INT_REGS; regno++)
1299 if (MUST_SAVE_REGISTER (regno, interrupt_p)
1300 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
1302 reg_size += UNITS_PER_WORD;
1303 gmask |= 1 << regno;
1307 current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER;
1308 current_frame_info.save_lr = MUST_SAVE_RETURN_ADDR || pic_reg_used;
1310 reg_size += ((current_frame_info.save_fp + current_frame_info.save_lr)
1312 total_size += reg_size;
1314 /* ??? Not sure this is necessary, and I don't think the epilogue
1315 handler will do the right thing if this changes total_size. */
1316 total_size = M32R_STACK_ALIGN (total_size);
1318 frame_size = total_size - (pretend_size + reg_size);
1320 /* Save computed information. */
1321 current_frame_info.total_size = total_size;
1322 current_frame_info.extra_size = extra_size;
1323 current_frame_info.pretend_size = pretend_size;
1324 current_frame_info.var_size = var_size;
1325 current_frame_info.args_size = args_size;
1326 current_frame_info.reg_size = reg_size;
1327 current_frame_info.gmask = gmask;
1328 current_frame_info.initialized = reload_completed;
1330 /* Ok, we're done. */
1334 /* The table we use to reference PIC data. */
1335 static rtx global_offset_table;
1338 m32r_reload_lr (rtx sp, int size)
1340 rtx lr = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
1343 emit_insn (gen_movsi (lr, gen_frame_mem (Pmode, sp)));
1344 else if (size < 32768)
1345 emit_insn (gen_movsi (lr, gen_frame_mem (Pmode,
1346 gen_rtx_PLUS (Pmode, sp,
1350 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1352 emit_insn (gen_movsi (tmp, GEN_INT (size)));
1353 emit_insn (gen_addsi3 (tmp, tmp, sp));
1354 emit_insn (gen_movsi (lr, gen_frame_mem (Pmode, tmp)));
1361 m32r_load_pic_register (void)
1363 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
1364 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
1365 GEN_INT (TARGET_MODEL_SMALL)));
1367 /* Need to emit this whether or not we obey regdecls,
1368 since setjmp/longjmp can cause life info to screw up. */
1369 emit_use (pic_offset_table_rtx);
1372 /* Expand the m32r prologue as a series of insns. */
1375 m32r_expand_prologue (void)
1380 int pic_reg_used = flag_pic && (crtl->uses_pic_offset_table
1383 if (! current_frame_info.initialized)
1384 m32r_compute_frame_size (get_frame_size ());
1386 gmask = current_frame_info.gmask;
1388 /* These cases shouldn't happen. Catch them now. */
1389 gcc_assert (current_frame_info.total_size || !gmask);
1391 /* Allocate space for register arguments if this is a variadic function. */
1392 if (current_frame_info.pretend_size != 0)
1394 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1395 the wrong result on a 64-bit host. */
1396 HOST_WIDE_INT pretend_size = current_frame_info.pretend_size;
1397 emit_insn (gen_addsi3 (stack_pointer_rtx,
1399 GEN_INT (-pretend_size)));
1402 /* Save any registers we need to and set up fp. */
1403 if (current_frame_info.save_fp)
1404 emit_insn (gen_movsi_push (stack_pointer_rtx, frame_pointer_rtx));
1406 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1408 /* Save any needed call-saved regs (and call-used if this is an
1409 interrupt handler). */
1410 for (regno = 0; regno <= M32R_MAX_INT_REGS; ++regno)
1412 if ((gmask & (1 << regno)) != 0)
1413 emit_insn (gen_movsi_push (stack_pointer_rtx,
1414 gen_rtx_REG (Pmode, regno)));
1417 if (current_frame_info.save_lr)
1418 emit_insn (gen_movsi_push (stack_pointer_rtx,
1419 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
1421 /* Allocate the stack frame. */
1422 frame_size = (current_frame_info.total_size
1423 - (current_frame_info.pretend_size
1424 + current_frame_info.reg_size));
1426 if (frame_size == 0)
1427 ; /* Nothing to do. */
1428 else if (frame_size <= 32768)
1429 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1430 GEN_INT (-frame_size)));
1433 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1435 emit_insn (gen_movsi (tmp, GEN_INT (frame_size)));
1436 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
1439 if (frame_pointer_needed)
1440 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
1443 /* Push lr for mcount (form_pc, x). */
1444 emit_insn (gen_movsi_push (stack_pointer_rtx,
1445 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
1449 m32r_load_pic_register ();
1450 m32r_reload_lr (stack_pointer_rtx,
1451 (crtl->profile ? 0 : frame_size));
1454 if (crtl->profile && !pic_reg_used)
1455 emit_insn (gen_blockage ());
1459 /* Set up the stack and frame pointer (if desired) for the function.
1460 Note, if this is changed, you need to mirror the changes in
1461 m32r_compute_frame_size which calculates the prolog size. */
1464 m32r_output_function_prologue (FILE * file, HOST_WIDE_INT size)
1466 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
1468 /* If this is an interrupt handler, mark it as such. */
1469 if (M32R_INTERRUPT_P (fn_type))
1470 fprintf (file, "\t%s interrupt handler\n", ASM_COMMENT_START);
1472 if (! current_frame_info.initialized)
1473 m32r_compute_frame_size (size);
1475 /* This is only for the human reader. */
1477 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
1479 current_frame_info.var_size,
1480 current_frame_info.reg_size / 4,
1481 current_frame_info.args_size,
1482 current_frame_info.extra_size);
1485 /* Output RTL to pop register REGNO from the stack. */
1492 x = emit_insn (gen_movsi_pop (gen_rtx_REG (Pmode, regno),
1493 stack_pointer_rtx));
1495 = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
1498 /* Expand the m32r epilogue as a series of insns. */
1501 m32r_expand_epilogue (void)
1504 int noepilogue = FALSE;
1507 gcc_assert (current_frame_info.initialized);
1508 total_size = current_frame_info.total_size;
1510 if (total_size == 0)
1512 rtx insn = get_last_insn ();
1514 /* If the last insn was a BARRIER, we don't have to write any code
1515 because a jump (aka return) was put there. */
1516 if (insn && GET_CODE (insn) == NOTE)
1517 insn = prev_nonnote_insn (insn);
1518 if (insn && GET_CODE (insn) == BARRIER)
1524 unsigned int var_size = current_frame_info.var_size;
1525 unsigned int args_size = current_frame_info.args_size;
1526 unsigned int gmask = current_frame_info.gmask;
1527 int can_trust_sp_p = !cfun->calls_alloca;
1529 if (flag_exceptions)
1530 emit_insn (gen_blockage ());
1532 /* The first thing to do is point the sp at the bottom of the register
1536 unsigned int reg_offset = var_size + args_size;
1538 if (reg_offset == 0)
1539 ; /* Nothing to do. */
1540 else if (reg_offset < 32768)
1541 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1542 GEN_INT (reg_offset)));
1545 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1547 emit_insn (gen_movsi (tmp, GEN_INT (reg_offset)));
1548 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1552 else if (frame_pointer_needed)
1554 unsigned int reg_offset = var_size + args_size;
1556 if (reg_offset == 0)
1557 emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx));
1558 else if (reg_offset < 32768)
1559 emit_insn (gen_addsi3 (stack_pointer_rtx, frame_pointer_rtx,
1560 GEN_INT (reg_offset)));
1563 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1565 emit_insn (gen_movsi (tmp, GEN_INT (reg_offset)));
1566 emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx));
1567 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1574 if (current_frame_info.save_lr)
1575 pop (RETURN_ADDR_REGNUM);
1577 /* Restore any saved registers, in reverse order of course. */
1578 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1579 for (regno = M32R_MAX_INT_REGS - 1; regno >= 0; --regno)
1581 if ((gmask & (1L << regno)) != 0)
1585 if (current_frame_info.save_fp)
1586 pop (FRAME_POINTER_REGNUM);
1588 /* Remove varargs area if present. */
1589 if (current_frame_info.pretend_size != 0)
1590 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1591 GEN_INT (current_frame_info.pretend_size)));
1593 emit_insn (gen_blockage ());
1597 /* Do any necessary cleanup after a function to restore stack, frame,
1601 m32r_output_function_epilogue (FILE * file ATTRIBUTE_UNUSED,
1602 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1604 /* Reset state info for each function. */
1605 current_frame_info = zero_frame_info;
1606 m32r_compute_function_type (NULL_TREE);
1609 /* Return nonzero if this function is known to have a null or 1 instruction
1613 direct_return (void)
1615 if (!reload_completed)
1618 if (M32R_INTERRUPT_P (m32r_compute_function_type (current_function_decl)))
1621 if (! current_frame_info.initialized)
1622 m32r_compute_frame_size (get_frame_size ());
1624 return current_frame_info.total_size == 0;
1631 m32r_legitimate_pic_operand_p (rtx x)
1633 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1636 if (GET_CODE (x) == CONST
1637 && GET_CODE (XEXP (x, 0)) == PLUS
1638 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
1639 || GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF)
1640 && (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
1647 m32r_legitimize_pic_address (rtx orig, rtx reg)
1650 printf("m32r_legitimize_pic_address()\n");
1653 if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
1655 rtx pic_ref, address;
1661 gcc_assert (!reload_in_progress && !reload_completed);
1662 reg = gen_reg_rtx (Pmode);
1668 address = gen_reg_rtx (Pmode);
1672 crtl->uses_pic_offset_table = 1;
1674 if (GET_CODE (orig) == LABEL_REF
1675 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
1677 emit_insn (gen_gotoff_load_addr (reg, orig));
1678 emit_insn (gen_addsi3 (reg, reg, pic_offset_table_rtx));
1682 emit_insn (gen_pic_load_addr (address, orig));
1684 emit_insn (gen_addsi3 (address, address, pic_offset_table_rtx));
1685 pic_ref = gen_const_mem (Pmode, address);
1686 insn = emit_move_insn (reg, pic_ref);
1688 /* Put a REG_EQUAL note on this insn, so that it can be optimized
1690 set_unique_reg_note (insn, REG_EQUAL, orig);
1694 else if (GET_CODE (orig) == CONST)
1698 if (GET_CODE (XEXP (orig, 0)) == PLUS
1699 && XEXP (XEXP (orig, 0), 1) == pic_offset_table_rtx)
1704 gcc_assert (!reload_in_progress && !reload_completed);
1705 reg = gen_reg_rtx (Pmode);
1708 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1710 base = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), reg);
1712 offset = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), NULL_RTX);
1714 offset = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), reg);
1719 if (GET_CODE (offset) == CONST_INT)
1721 if (INT16_P (INTVAL (offset)))
1722 return plus_constant (base, INTVAL (offset));
1725 gcc_assert (! reload_in_progress && ! reload_completed);
1726 offset = force_reg (Pmode, offset);
1730 return gen_rtx_PLUS (Pmode, base, offset);
1737 m32r_legitimize_address (rtx x, rtx orig_x ATTRIBUTE_UNUSED,
1738 enum machine_mode mode ATTRIBUTE_UNUSED)
1741 return m32r_legitimize_pic_address (x, NULL_RTX);
1746 /* Nested function support. */
1748 /* Emit RTL insns to initialize the variable parts of a trampoline.
1749 FNADDR is an RTX for the address of the function's pure code.
1750 CXT is an RTX for the static chain value for the function. */
1753 m32r_initialize_trampoline (rtx tramp ATTRIBUTE_UNUSED,
1754 rtx fnaddr ATTRIBUTE_UNUSED,
1755 rtx cxt ATTRIBUTE_UNUSED)
1760 m32r_file_start (void)
1762 default_file_start ();
1764 if (flag_verbose_asm)
1765 fprintf (asm_out_file,
1766 "%s M32R/D special options: -G " HOST_WIDE_INT_PRINT_UNSIGNED "\n",
1767 ASM_COMMENT_START, g_switch_value);
1769 if (TARGET_LITTLE_ENDIAN)
1770 fprintf (asm_out_file, "\t.little\n");
1773 /* Print operand X (an rtx) in assembler syntax to file FILE.
1774 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1775 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1778 m32r_print_operand (FILE * file, rtx x, int code)
1784 /* The 's' and 'p' codes are used by output_block_move() to
1785 indicate post-increment 's'tores and 'p're-increment loads. */
1787 if (GET_CODE (x) == REG)
1788 fprintf (file, "@+%s", reg_names [REGNO (x)]);
1790 output_operand_lossage ("invalid operand to %%s code");
1794 if (GET_CODE (x) == REG)
1795 fprintf (file, "@%s+", reg_names [REGNO (x)]);
1797 output_operand_lossage ("invalid operand to %%p code");
1801 /* Write second word of DImode or DFmode reference,
1802 register or memory. */
1803 if (GET_CODE (x) == REG)
1804 fputs (reg_names[REGNO (x)+1], file);
1805 else if (GET_CODE (x) == MEM)
1807 fprintf (file, "@(");
1808 /* Handle possible auto-increment. Since it is pre-increment and
1809 we have already done it, we can just use an offset of four. */
1810 /* ??? This is taken from rs6000.c I think. I don't think it is
1811 currently necessary, but keep it around. */
1812 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1813 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1814 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
1816 output_address (plus_constant (XEXP (x, 0), 4));
1820 output_operand_lossage ("invalid operand to %%R code");
1823 case 'H' : /* High word. */
1824 case 'L' : /* Low word. */
1825 if (GET_CODE (x) == REG)
1827 /* L = least significant word, H = most significant word. */
1828 if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L'))
1829 fputs (reg_names[REGNO (x)], file);
1831 fputs (reg_names[REGNO (x)+1], file);
1833 else if (GET_CODE (x) == CONST_INT
1834 || GET_CODE (x) == CONST_DOUBLE)
1838 split_double (x, &first, &second);
1839 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
1840 code == 'L' ? INTVAL (first) : INTVAL (second));
1843 output_operand_lossage ("invalid operand to %%H/%%L code");
1850 if (GET_CODE (x) != CONST_DOUBLE
1851 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
1852 fatal_insn ("bad insn for 'A'", x);
1854 real_to_decimal (str, CONST_DOUBLE_REAL_VALUE (x), sizeof (str), 0, 1);
1855 fprintf (file, "%s", str);
1859 case 'B' : /* Bottom half. */
1860 case 'T' : /* Top half. */
1861 /* Output the argument to a `seth' insn (sets the Top half-word).
1862 For constants output arguments to a seth/or3 pair to set Top and
1863 Bottom halves. For symbols output arguments to a seth/add3 pair to
1864 set Top and Bottom halves. The difference exists because for
1865 constants seth/or3 is more readable but for symbols we need to use
1866 the same scheme as `ld' and `st' insns (16-bit addend is signed). */
1867 switch (GET_CODE (x))
1874 split_double (x, &first, &second);
1875 x = WORDS_BIG_ENDIAN ? second : first;
1876 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
1878 ? INTVAL (x) & 0xffff
1879 : (INTVAL (x) >> 16) & 0xffff));
1885 && small_data_operand (x, VOIDmode))
1887 fputs ("sda(", file);
1888 output_addr_const (file, x);
1894 fputs (code == 'T' ? "shigh(" : "low(", file);
1895 output_addr_const (file, x);
1899 output_operand_lossage ("invalid operand to %%T/%%B code");
1906 /* Output a load/store with update indicator if appropriate. */
1907 if (GET_CODE (x) == MEM)
1909 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1910 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1914 output_operand_lossage ("invalid operand to %%U code");
1918 /* Print a constant value negated. */
1919 if (GET_CODE (x) == CONST_INT)
1920 output_addr_const (file, GEN_INT (- INTVAL (x)));
1922 output_operand_lossage ("invalid operand to %%N code");
1926 /* Print a const_int in hex. Used in comments. */
1927 if (GET_CODE (x) == CONST_INT)
1928 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
1932 fputs (IMMEDIATE_PREFIX, file);
1936 /* Do nothing special. */
1941 output_operand_lossage ("invalid operand output code");
1944 switch (GET_CODE (x))
1947 fputs (reg_names[REGNO (x)], file);
1952 if (GET_CODE (addr) == PRE_INC)
1954 if (GET_CODE (XEXP (addr, 0)) != REG)
1955 fatal_insn ("pre-increment address is not a register", x);
1957 fprintf (file, "@+%s", reg_names[REGNO (XEXP (addr, 0))]);
1959 else if (GET_CODE (addr) == PRE_DEC)
1961 if (GET_CODE (XEXP (addr, 0)) != REG)
1962 fatal_insn ("pre-decrement address is not a register", x);
1964 fprintf (file, "@-%s", reg_names[REGNO (XEXP (addr, 0))]);
1966 else if (GET_CODE (addr) == POST_INC)
1968 if (GET_CODE (XEXP (addr, 0)) != REG)
1969 fatal_insn ("post-increment address is not a register", x);
1971 fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]);
1976 output_address (XEXP (x, 0));
1982 /* We handle SFmode constants here as output_addr_const doesn't. */
1983 if (GET_MODE (x) == SFmode)
1988 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
1989 REAL_VALUE_TO_TARGET_SINGLE (d, l);
1990 fprintf (file, "0x%08lx", l);
1994 /* Fall through. Let output_addr_const deal with it. */
1997 output_addr_const (file, x);
2002 /* Print a memory address as an operand to reference that memory location. */
2005 m32r_print_operand_address (FILE * file, rtx addr)
2011 switch (GET_CODE (addr))
2014 fputs (reg_names[REGNO (addr)], file);
2018 if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
2019 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
2020 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2021 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
2023 base = XEXP (addr, 0), index = XEXP (addr, 1);
2024 if (GET_CODE (base) == REG)
2026 /* Print the offset first (if present) to conform to the manual. */
2030 fprintf (file, "%d,", offset);
2031 fputs (reg_names[REGNO (base)], file);
2033 /* The chip doesn't support this, but left in for generality. */
2034 else if (GET_CODE (index) == REG)
2035 fprintf (file, "%s,%s",
2036 reg_names[REGNO (base)], reg_names[REGNO (index)]);
2037 /* Not sure this can happen, but leave in for now. */
2038 else if (GET_CODE (index) == SYMBOL_REF)
2040 output_addr_const (file, index);
2042 fputs (reg_names[REGNO (base)], file);
2045 fatal_insn ("bad address", addr);
2047 else if (GET_CODE (base) == LO_SUM)
2049 gcc_assert (!index && GET_CODE (XEXP (base, 0)) == REG);
2050 if (small_data_operand (XEXP (base, 1), VOIDmode))
2051 fputs ("sda(", file);
2053 fputs ("low(", file);
2054 output_addr_const (file, plus_constant (XEXP (base, 1), offset));
2056 fputs (reg_names[REGNO (XEXP (base, 0))], file);
2059 fatal_insn ("bad address", addr);
2063 if (GET_CODE (XEXP (addr, 0)) != REG)
2064 fatal_insn ("lo_sum not of register", addr);
2065 if (small_data_operand (XEXP (addr, 1), VOIDmode))
2066 fputs ("sda(", file);
2068 fputs ("low(", file);
2069 output_addr_const (file, XEXP (addr, 1));
2071 fputs (reg_names[REGNO (XEXP (addr, 0))], file);
2074 case PRE_INC : /* Assume SImode. */
2075 fprintf (file, "+%s", reg_names[REGNO (XEXP (addr, 0))]);
2078 case PRE_DEC : /* Assume SImode. */
2079 fprintf (file, "-%s", reg_names[REGNO (XEXP (addr, 0))]);
2082 case POST_INC : /* Assume SImode. */
2083 fprintf (file, "%s+", reg_names[REGNO (XEXP (addr, 0))]);
2087 output_addr_const (file, addr);
2092 /* Return true if the operands are the constants 0 and 1. */
2095 zero_and_one (rtx operand1, rtx operand2)
2098 GET_CODE (operand1) == CONST_INT
2099 && GET_CODE (operand2) == CONST_INT
2100 && ( ((INTVAL (operand1) == 0) && (INTVAL (operand2) == 1))
2101 ||((INTVAL (operand1) == 1) && (INTVAL (operand2) == 0)));
2104 /* Generate the correct assembler code to handle the conditional loading of a
2105 value into a register. It is known that the operands satisfy the
2106 conditional_move_operand() function above. The destination is operand[0].
2107 The condition is operand [1]. The 'true' value is operand [2] and the
2108 'false' value is operand [3]. */
2111 emit_cond_move (rtx * operands, rtx insn ATTRIBUTE_UNUSED)
2113 static char buffer [100];
2114 const char * dest = reg_names [REGNO (operands [0])];
2118 /* Destination must be a register. */
2119 gcc_assert (GET_CODE (operands [0]) == REG);
2120 gcc_assert (conditional_move_operand (operands [2], SImode));
2121 gcc_assert (conditional_move_operand (operands [3], SImode));
2123 /* Check to see if the test is reversed. */
2124 if (GET_CODE (operands [1]) == NE)
2126 rtx tmp = operands [2];
2127 operands [2] = operands [3];
2131 sprintf (buffer, "mvfc %s, cbr", dest);
2133 /* If the true value was '0' then we need to invert the results of the move. */
2134 if (INTVAL (operands [2]) == 0)
2135 sprintf (buffer + strlen (buffer), "\n\txor3 %s, %s, #1",
2141 /* Returns true if the registers contained in the two
2142 rtl expressions are different. */
2145 m32r_not_same_reg (rtx a, rtx b)
2150 while (GET_CODE (a) == SUBREG)
2153 if (GET_CODE (a) == REG)
2156 while (GET_CODE (b) == SUBREG)
2159 if (GET_CODE (b) == REG)
2162 return reg_a != reg_b;
2167 m32r_function_symbol (const char *name)
2169 int extra_flags = 0;
2170 enum m32r_model model;
2171 rtx sym = gen_rtx_SYMBOL_REF (Pmode, name);
2173 if (TARGET_MODEL_SMALL)
2174 model = M32R_MODEL_SMALL;
2175 else if (TARGET_MODEL_MEDIUM)
2176 model = M32R_MODEL_MEDIUM;
2177 else if (TARGET_MODEL_LARGE)
2178 model = M32R_MODEL_LARGE;
2180 gcc_unreachable (); /* Shouldn't happen. */
2181 extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT;
2184 SYMBOL_REF_FLAGS (sym) |= extra_flags;
2189 /* Use a library function to move some bytes. */
2192 block_move_call (rtx dest_reg, rtx src_reg, rtx bytes_rtx)
2194 /* We want to pass the size as Pmode, which will normally be SImode
2195 but will be DImode if we are using 64-bit longs and pointers. */
2196 if (GET_MODE (bytes_rtx) != VOIDmode
2197 && GET_MODE (bytes_rtx) != Pmode)
2198 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
2200 emit_library_call (m32r_function_symbol ("memcpy"), 0,
2201 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
2202 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
2203 TYPE_UNSIGNED (sizetype)),
2204 TYPE_MODE (sizetype));
2207 /* Expand string/block move operations.
2209 operands[0] is the pointer to the destination.
2210 operands[1] is the pointer to the source.
2211 operands[2] is the number of bytes to move.
2212 operands[3] is the alignment.
2214 Returns 1 upon success, 0 otherwise. */
2217 m32r_expand_block_move (rtx operands[])
2219 rtx orig_dst = operands[0];
2220 rtx orig_src = operands[1];
2221 rtx bytes_rtx = operands[2];
2222 rtx align_rtx = operands[3];
2223 int constp = GET_CODE (bytes_rtx) == CONST_INT;
2224 HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
2225 int align = INTVAL (align_rtx);
2230 if (constp && bytes <= 0)
2233 /* Move the address into scratch registers. */
2234 dst_reg = copy_addr_to_reg (XEXP (orig_dst, 0));
2235 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2237 if (align > UNITS_PER_WORD)
2238 align = UNITS_PER_WORD;
2240 /* If we prefer size over speed, always use a function call.
2241 If we do not know the size, use a function call.
2242 If the blocks are not word aligned, use a function call. */
2243 if (optimize_size || ! constp || align != UNITS_PER_WORD)
2245 block_move_call (dst_reg, src_reg, bytes_rtx);
2249 leftover = bytes % MAX_MOVE_BYTES;
2252 /* If necessary, generate a loop to handle the bulk of the copy. */
2255 rtx label = NULL_RTX;
2256 rtx final_src = NULL_RTX;
2257 rtx at_a_time = GEN_INT (MAX_MOVE_BYTES);
2258 rtx rounded_total = GEN_INT (bytes);
2259 rtx new_dst_reg = gen_reg_rtx (SImode);
2260 rtx new_src_reg = gen_reg_rtx (SImode);
2262 /* If we are going to have to perform this loop more than
2263 once, then generate a label and compute the address the
2264 source register will contain upon completion of the final
2266 if (bytes > MAX_MOVE_BYTES)
2268 final_src = gen_reg_rtx (Pmode);
2271 emit_insn (gen_addsi3 (final_src, src_reg, rounded_total));
2274 emit_insn (gen_movsi (final_src, rounded_total));
2275 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
2278 label = gen_label_rtx ();
2282 /* It is known that output_block_move() will update src_reg to point
2283 to the word after the end of the source block, and dst_reg to point
2284 to the last word of the destination block, provided that the block
2285 is MAX_MOVE_BYTES long. */
2286 emit_insn (gen_movmemsi_internal (dst_reg, src_reg, at_a_time,
2287 new_dst_reg, new_src_reg));
2288 emit_move_insn (dst_reg, new_dst_reg);
2289 emit_move_insn (src_reg, new_src_reg);
2290 emit_insn (gen_addsi3 (dst_reg, dst_reg, GEN_INT (4)));
2292 if (bytes > MAX_MOVE_BYTES)
2294 emit_insn (gen_cmpsi (src_reg, final_src));
2295 emit_jump_insn (gen_bne (label));
2300 emit_insn (gen_movmemsi_internal (dst_reg, src_reg, GEN_INT (leftover),
2301 gen_reg_rtx (SImode),
2302 gen_reg_rtx (SImode)));
2307 /* Emit load/stores for a small constant word aligned block_move.
2309 operands[0] is the memory address of the destination.
2310 operands[1] is the memory address of the source.
2311 operands[2] is the number of bytes to move.
2312 operands[3] is a temp register.
2313 operands[4] is a temp register. */
2316 m32r_output_block_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[])
2318 HOST_WIDE_INT bytes = INTVAL (operands[2]);
2322 gcc_assert (bytes >= 1 && bytes <= MAX_MOVE_BYTES);
2324 /* We do not have a post-increment store available, so the first set of
2325 stores are done without any increment, then the remaining ones can use
2326 the pre-increment addressing mode.
2328 Note: expand_block_move() also relies upon this behavior when building
2329 loops to copy large blocks. */
2338 output_asm_insn ("ld\t%5, %p1", operands);
2339 output_asm_insn ("ld\t%6, %p1", operands);
2340 output_asm_insn ("st\t%5, @%0", operands);
2341 output_asm_insn ("st\t%6, %s0", operands);
2345 output_asm_insn ("ld\t%5, %p1", operands);
2346 output_asm_insn ("ld\t%6, %p1", operands);
2347 output_asm_insn ("st\t%5, %s0", operands);
2348 output_asm_insn ("st\t%6, %s0", operands);
2353 else if (bytes >= 4)
2358 output_asm_insn ("ld\t%5, %p1", operands);
2361 output_asm_insn ("ld\t%6, %p1", operands);
2364 output_asm_insn ("st\t%5, @%0", operands);
2366 output_asm_insn ("st\t%5, %s0", operands);
2372 /* Get the entire next word, even though we do not want all of it.
2373 The saves us from doing several smaller loads, and we assume that
2374 we cannot cause a page fault when at least part of the word is in
2375 valid memory [since we don't get called if things aren't properly
2377 int dst_offset = first_time ? 0 : 4;
2378 /* The amount of increment we have to make to the
2379 destination pointer. */
2380 int dst_inc_amount = dst_offset + bytes - 4;
2381 /* The same for the source pointer. */
2382 int src_inc_amount = bytes;
2386 /* If got_extra is true then we have already loaded
2387 the next word as part of loading and storing the previous word. */
2389 output_asm_insn ("ld\t%6, @%1", operands);
2395 output_asm_insn ("sra3\t%5, %6, #16", operands);
2396 my_operands[0] = operands[5];
2397 my_operands[1] = GEN_INT (dst_offset);
2398 my_operands[2] = operands[0];
2399 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands);
2401 /* If there is a byte left to store then increment the
2402 destination address and shift the contents of the source
2403 register down by 8 bits. We could not do the address
2404 increment in the store half word instruction, because it does
2405 not have an auto increment mode. */
2406 if (bytes > 0) /* assert (bytes == 1) */
2417 my_operands[0] = operands[6];
2418 my_operands[1] = GEN_INT (last_shift);
2419 output_asm_insn ("srai\t%0, #%1", my_operands);
2420 my_operands[0] = operands[6];
2421 my_operands[1] = GEN_INT (dst_offset);
2422 my_operands[2] = operands[0];
2423 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands);
2426 /* Update the destination pointer if needed. We have to do
2427 this so that the patterns matches what we output in this
2430 && !find_reg_note (insn, REG_UNUSED, operands[0]))
2432 my_operands[0] = operands[0];
2433 my_operands[1] = GEN_INT (dst_inc_amount);
2434 output_asm_insn ("addi\t%0, #%1", my_operands);
2437 /* Update the source pointer if needed. We have to do this
2438 so that the patterns matches what we output in this
2441 && !find_reg_note (insn, REG_UNUSED, operands[1]))
2443 my_operands[0] = operands[1];
2444 my_operands[1] = GEN_INT (src_inc_amount);
2445 output_asm_insn ("addi\t%0, #%1", my_operands);
2455 /* Return true if using NEW_REG in place of OLD_REG is ok. */
2458 m32r_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
2459 unsigned int new_reg)
2461 /* Interrupt routines can't clobber any register that isn't already used. */
2462 if (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl))
2463 && !df_regs_ever_live_p (new_reg))
2470 m32r_return_addr (int count)
2475 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);