1 ;; Constraint definitions for Renesas M32R cpu for GNU C compiler
2 ;; Copyright (C) 2007 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify it
7 ;; under the terms of the GNU General Public License as published
8 ;; by the Free Software Foundation; either version 3, or (at your
9 ;; option) any later version.
11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 ;; License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
21 ;; The letters I, J, K, L, M, N, O, P in a register constraint string
22 ;; can be used to stand for particular ranges of immediate operands.
23 ;; The letters Q, R, S, T, U are used to segregate specific types of
24 ;; operands, usually memory references, for the target machine.
26 ;; I is used for 8-bit signed immediates.
27 ;; J is used for 16-bit signed immediates.
28 ;; K is used for 16-bit unsigned immediates.
29 ;; L is used for 16-bit immediates left shifted by 16 (sign ???).
30 ;; M is used for 24-bit unsigned immediates.
31 ;; N is used for 8-bit signed immediates for compares
32 ;; (values in the range -127 to +128).
33 ;; O is used for 5-bit unsigned immediates (shift count).
34 ;; P is used for 16-bit signed immediates for compares
35 ;; (values in the range -32767 to +32768).
37 ;; Q is for symbolic addresses loadable with ld24.
38 ;; R is for symbolic addresses when ld24 can't be used.
39 ;; S is for stores with pre {inc,dec}rement
40 ;; T is for indirect of a pointer.
41 ;; U is for loads with post increment.
43 ;; Register constraints
45 (define_register_constraint "a" "ACCUM_REGS"
48 (define_register_constraint "c" "CARRY_REG"
51 ;; Integer constraints
52 (define_constraint "I"
53 "8-bit signed immediate."
54 (and (match_code "const_int")
55 (match_test "ival >= -0x80 && ival <= 0x7f")))
57 (define_constraint "J"
58 "16-bit signed immediate."
59 (and (match_code "const_int")
60 (match_test "ival >= -0x8000 && ival <= 0x7fff")))
62 (define_constraint "K"
63 "16-bit unsigned immediate."
64 (and (match_code "const_int")
65 (match_test "(unsigned HOST_WIDE_INT) ival <= 0x0000ffff")))
67 (define_constraint "L"
68 "16-bit signed immediate left shifted by 16."
69 (and (match_code "const_int")
70 (match_test "(ival & 0xffff) == 0")
71 (match_test "(ival >> 16) >= -0x8000 && (ival >> 16) <= 0x7fff")))
73 (define_constraint "M"
74 "24-bit unsigned immediate."
75 (and (match_code "const_int")
76 (match_test "(unsigned HOST_WIDE_INT) ival <= 0x00ffffff")))
78 (define_constraint "N"
79 "8-bit signed immediate for compare."
80 (and (match_code "const_int")
81 (match_test "ival >= -127 && ival <= 128")))
83 (define_constraint "O"
84 "5-bit unsigned immediate."
85 (and (match_code "const_int")
86 (match_test "ival >= 0 && ival < 32")))
88 (define_constraint "P"
89 "16-bit signed immediate for compare."
90 (and (match_code "const_int")
91 (match_test "ival >= -0x7fff && ival <= 0x8000")))
93 ;; Floating-point constraints
94 (define_constraint "G"
95 "Double constant loadable with 2 ldi insns."
96 (and (match_code "const_double")
97 (match_test "easy_di_const (op)")))
99 (define_constraint "H"
100 "Double constant loadable with movdf."
101 (and (match_code "const_double")
102 (match_test "easy_df_const (op)")))
105 (define_constraint "Q"
106 "A symbolic address loadable when ld24."
107 (ior (and (match_test "TARGET_ADDR24")
108 (match_test "GET_CODE (op) == LABEL_REF"))
109 (match_test "addr24_operand (op, VOIDmode)")))
111 (define_constraint "R"
112 "A symbolic address loadable with ld24 can't be used."
113 (ior (and (match_test "TARGET_ADDR32")
114 (match_test "GET_CODE (op) == LABEL_REF"))
115 (match_test "addr32_operand (op, VOIDmode)")))
117 (define_constraint "S"
118 "A store with pre {inc,dec}rement."
119 (and (match_code "mem")
120 (match_test "STORE_PREINC_PREDEC_P (GET_MODE (op), XEXP (op, 0))")))
122 (define_constraint "T"
123 "An indirect of a pointer."
124 (and (match_code "mem")
125 (match_test "memreg_operand (op, GET_MODE (op))")))
127 (define_constraint "U"
128 "A load with post increment."
129 (and (match_code "mem")
130 (match_test "LOAD_POSTINC_P (GET_MODE (op), XEXP (op, 0))")))