1 /* Target Code for R8C/M16C/M32C
2 Copyright (C) 2005, 2006, 2007
3 Free Software Foundation, Inc.
4 Contributed by Red Hat.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 3, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
47 #include "target-def.h"
49 #include "langhooks.h"
50 #include "tree-gimple.h"
55 /* Used by m32c_pushm_popm. */
63 static tree interrupt_handler (tree *, tree, tree, int, bool *);
64 static tree function_vector_handler (tree *, tree, tree, int, bool *);
65 static int interrupt_p (tree node);
66 static bool m32c_asm_integer (rtx, unsigned int, int);
67 static int m32c_comp_type_attributes (const_tree, const_tree);
68 static bool m32c_fixed_condition_code_regs (unsigned int *, unsigned int *);
69 static struct machine_function *m32c_init_machine_status (void);
70 static void m32c_insert_attributes (tree, tree *);
71 static bool m32c_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
73 static bool m32c_promote_prototypes (const_tree);
74 static int m32c_pushm_popm (Push_Pop_Type);
75 static bool m32c_strict_argument_naming (CUMULATIVE_ARGS *);
76 static rtx m32c_struct_value_rtx (tree, int);
77 static rtx m32c_subreg (enum machine_mode, rtx, enum machine_mode, int);
78 static int need_to_save (int);
79 int current_function_special_page_vector (rtx);
81 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
83 #define streq(a,b) (strcmp ((a), (b)) == 0)
85 /* Internal support routines */
87 /* Debugging statements are tagged with DEBUG0 only so that they can
88 be easily enabled individually, by replacing the '0' with '1' as
94 /* This is needed by some of the commented-out debug statements
96 static char const *class_names[LIM_REG_CLASSES] = REG_CLASS_NAMES;
98 static int class_contents[LIM_REG_CLASSES][1] = REG_CLASS_CONTENTS;
100 /* These are all to support encode_pattern(). */
101 static char pattern[30], *patternp;
102 static GTY(()) rtx patternr[30];
103 #define RTX_IS(x) (streq (pattern, x))
105 /* Some macros to simplify the logic throughout this file. */
106 #define IS_MEM_REGNO(regno) ((regno) >= MEM0_REGNO && (regno) <= MEM7_REGNO)
107 #define IS_MEM_REG(rtx) (GET_CODE (rtx) == REG && IS_MEM_REGNO (REGNO (rtx)))
109 #define IS_CR_REGNO(regno) ((regno) >= SB_REGNO && (regno) <= PC_REGNO)
110 #define IS_CR_REG(rtx) (GET_CODE (rtx) == REG && IS_CR_REGNO (REGNO (rtx)))
112 /* We do most RTX matching by converting the RTX into a string, and
113 using string compares. This vastly simplifies the logic in many of
114 the functions in this file.
116 On exit, pattern[] has the encoded string (use RTX_IS("...") to
117 compare it) and patternr[] has pointers to the nodes in the RTX
118 corresponding to each character in the encoded string. The latter
119 is mostly used by print_operand().
121 Unrecognized patterns have '?' in them; this shows up when the
122 assembler complains about syntax errors.
126 encode_pattern_1 (rtx x)
130 if (patternp == pattern + sizeof (pattern) - 2)
136 patternr[patternp - pattern] = x;
138 switch (GET_CODE (x))
144 if (GET_MODE_SIZE (GET_MODE (x)) !=
145 GET_MODE_SIZE (GET_MODE (XEXP (x, 0))))
147 encode_pattern_1 (XEXP (x, 0));
152 encode_pattern_1 (XEXP (x, 0));
156 encode_pattern_1 (XEXP (x, 0));
157 encode_pattern_1 (XEXP (x, 1));
161 encode_pattern_1 (XEXP (x, 0));
165 encode_pattern_1 (XEXP (x, 0));
169 encode_pattern_1 (XEXP (x, 0));
170 encode_pattern_1 (XEXP (x, 1));
174 encode_pattern_1 (XEXP (x, 0));
191 *patternp++ = '0' + XCINT (x, 1, UNSPEC);
192 for (i = 0; i < XVECLEN (x, 0); i++)
193 encode_pattern_1 (XVECEXP (x, 0, i));
200 for (i = 0; i < XVECLEN (x, 0); i++)
201 encode_pattern_1 (XVECEXP (x, 0, i));
205 encode_pattern_1 (XEXP (x, 0));
207 encode_pattern_1 (XEXP (x, 1));
212 fprintf (stderr, "can't encode pattern %s\n",
213 GET_RTX_NAME (GET_CODE (x)));
222 encode_pattern (rtx x)
225 encode_pattern_1 (x);
229 /* Since register names indicate the mode they're used in, we need a
230 way to determine which name to refer to the register with. Called
231 by print_operand(). */
234 reg_name_with_mode (int regno, enum machine_mode mode)
236 int mlen = GET_MODE_SIZE (mode);
237 if (regno == R0_REGNO && mlen == 1)
239 if (regno == R0_REGNO && (mlen == 3 || mlen == 4))
241 if (regno == R0_REGNO && mlen == 6)
243 if (regno == R0_REGNO && mlen == 8)
245 if (regno == R1_REGNO && mlen == 1)
247 if (regno == R1_REGNO && (mlen == 3 || mlen == 4))
249 if (regno == A0_REGNO && TARGET_A16 && (mlen == 3 || mlen == 4))
251 return reg_names[regno];
254 /* How many bytes a register uses on stack when it's pushed. We need
255 to know this because the push opcode needs to explicitly indicate
256 the size of the register, even though the name of the register
257 already tells it that. Used by m32c_output_reg_{push,pop}, which
258 is only used through calls to ASM_OUTPUT_REG_{PUSH,POP}. */
261 reg_push_size (int regno)
286 static int *class_sizes = 0;
288 /* Given two register classes, find the largest intersection between
289 them. If there is no intersection, return RETURNED_IF_EMPTY
292 reduce_class (int original_class, int limiting_class, int returned_if_empty)
294 int cc = class_contents[original_class][0];
295 int i, best = NO_REGS;
298 if (original_class == limiting_class)
299 return original_class;
304 class_sizes = (int *) xmalloc (LIM_REG_CLASSES * sizeof (int));
305 for (i = 0; i < LIM_REG_CLASSES; i++)
308 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
309 if (class_contents[i][0] & (1 << r))
314 cc &= class_contents[limiting_class][0];
315 for (i = 0; i < LIM_REG_CLASSES; i++)
317 int ic = class_contents[i][0];
320 if (best_size < class_sizes[i])
323 best_size = class_sizes[i];
328 return returned_if_empty;
332 /* Returns TRUE If there are any registers that exist in both register
335 classes_intersect (int class1, int class2)
337 return class_contents[class1][0] & class_contents[class2][0];
340 /* Used by m32c_register_move_cost to determine if a move is
341 impossibly expensive. */
343 class_can_hold_mode (int class, enum machine_mode mode)
345 /* Cache the results: 0=untested 1=no 2=yes */
346 static char results[LIM_REG_CLASSES][MAX_MACHINE_MODE];
347 if (results[class][mode] == 0)
350 results[class][mode] = 1;
351 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
352 if (class_contents[class][0] & (1 << r)
353 && HARD_REGNO_MODE_OK (r, mode))
356 n = HARD_REGNO_NREGS (r, mode);
357 for (i = 1; i < n; i++)
358 if (!(class_contents[class][0] & (1 << (r + i))))
362 results[class][mode] = 2;
368 fprintf (stderr, "class %s can hold %s? %s\n",
369 class_names[class], mode_name[mode],
370 (results[class][mode] == 2) ? "yes" : "no");
372 return results[class][mode] == 2;
375 /* Run-time Target Specification. */
377 /* Memregs are memory locations that gcc treats like general
378 registers, as there are a limited number of true registers and the
379 m32c families can use memory in most places that registers can be
382 However, since memory accesses are more expensive than registers,
383 we allow the user to limit the number of memregs available, in
384 order to try to persuade gcc to try harder to use real registers.
386 Memregs are provided by m32c-lib1.S.
389 int target_memregs = 16;
390 static bool target_memregs_set = FALSE;
391 int ok_to_change_target_memregs = TRUE;
393 #undef TARGET_HANDLE_OPTION
394 #define TARGET_HANDLE_OPTION m32c_handle_option
396 m32c_handle_option (size_t code,
397 const char *arg ATTRIBUTE_UNUSED,
398 int value ATTRIBUTE_UNUSED)
400 if (code == OPT_memregs_)
402 target_memregs_set = TRUE;
403 target_memregs = atoi (arg);
408 /* Implements OVERRIDE_OPTIONS. We limit memregs to 0..16, and
409 provide a default. */
411 m32c_override_options (void)
413 if (target_memregs_set)
415 if (target_memregs < 0 || target_memregs > 16)
416 error ("invalid target memregs value '%d'", target_memregs);
422 /* Defining data structures for per-function information */
424 /* The usual; we set up our machine_function data. */
425 static struct machine_function *
426 m32c_init_machine_status (void)
428 struct machine_function *machine;
430 (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
435 /* Implements INIT_EXPANDERS. We just set up to call the above
438 m32c_init_expanders (void)
440 init_machine_status = m32c_init_machine_status;
445 #undef TARGET_PROMOTE_FUNCTION_RETURN
446 #define TARGET_PROMOTE_FUNCTION_RETURN m32c_promote_function_return
448 m32c_promote_function_return (const_tree fntype ATTRIBUTE_UNUSED)
453 /* Register Basics */
455 /* Basic Characteristics of Registers */
457 /* Whether a mode fits in a register is complex enough to warrant a
466 } nregs_table[FIRST_PSEUDO_REGISTER] =
468 { 1, 1, 2, 2, 4 }, /* r0 */
469 { 0, 1, 0, 0, 0 }, /* r2 */
470 { 1, 1, 2, 2, 0 }, /* r1 */
471 { 0, 1, 0, 0, 0 }, /* r3 */
472 { 0, 1, 1, 0, 0 }, /* a0 */
473 { 0, 1, 1, 0, 0 }, /* a1 */
474 { 0, 1, 1, 0, 0 }, /* sb */
475 { 0, 1, 1, 0, 0 }, /* fb */
476 { 0, 1, 1, 0, 0 }, /* sp */
477 { 1, 1, 1, 0, 0 }, /* pc */
478 { 0, 0, 0, 0, 0 }, /* fl */
479 { 1, 1, 1, 0, 0 }, /* ap */
480 { 1, 1, 2, 2, 4 }, /* mem0 */
481 { 1, 1, 2, 2, 4 }, /* mem1 */
482 { 1, 1, 2, 2, 4 }, /* mem2 */
483 { 1, 1, 2, 2, 4 }, /* mem3 */
484 { 1, 1, 2, 2, 4 }, /* mem4 */
485 { 1, 1, 2, 2, 0 }, /* mem5 */
486 { 1, 1, 2, 2, 0 }, /* mem6 */
487 { 1, 1, 0, 0, 0 }, /* mem7 */
490 /* Implements CONDITIONAL_REGISTER_USAGE. We adjust the number of
491 available memregs, and select which registers need to be preserved
492 across calls based on the chip family. */
495 m32c_conditional_register_usage (void)
499 if (0 <= target_memregs && target_memregs <= 16)
501 /* The command line option is bytes, but our "registers" are
503 for (i = target_memregs/2; i < 8; i++)
505 fixed_regs[MEM0_REGNO + i] = 1;
506 CLEAR_HARD_REG_BIT (reg_class_contents[MEM_REGS], MEM0_REGNO + i);
510 /* M32CM and M32C preserve more registers across function calls. */
513 call_used_regs[R1_REGNO] = 0;
514 call_used_regs[R2_REGNO] = 0;
515 call_used_regs[R3_REGNO] = 0;
516 call_used_regs[A0_REGNO] = 0;
517 call_used_regs[A1_REGNO] = 0;
521 /* How Values Fit in Registers */
523 /* Implements HARD_REGNO_NREGS. This is complicated by the fact that
524 different registers are different sizes from each other, *and* may
525 be different sizes in different chip families. */
527 m32c_hard_regno_nregs_1 (int regno, enum machine_mode mode)
529 if (regno == FLG_REGNO && mode == CCmode)
531 if (regno >= FIRST_PSEUDO_REGISTER)
532 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
534 if (regno >= MEM0_REGNO && regno <= MEM7_REGNO)
535 return (GET_MODE_SIZE (mode) + 1) / 2;
537 if (GET_MODE_SIZE (mode) <= 1)
538 return nregs_table[regno].qi_regs;
539 if (GET_MODE_SIZE (mode) <= 2)
540 return nregs_table[regno].hi_regs;
541 if (regno == A0_REGNO && mode == PSImode && TARGET_A16)
543 if ((GET_MODE_SIZE (mode) <= 3 || mode == PSImode) && TARGET_A24)
544 return nregs_table[regno].pi_regs;
545 if (GET_MODE_SIZE (mode) <= 4)
546 return nregs_table[regno].si_regs;
547 if (GET_MODE_SIZE (mode) <= 8)
548 return nregs_table[regno].di_regs;
553 m32c_hard_regno_nregs (int regno, enum machine_mode mode)
555 int rv = m32c_hard_regno_nregs_1 (regno, mode);
559 /* Implements HARD_REGNO_MODE_OK. The above function does the work
560 already; just test its return value. */
562 m32c_hard_regno_ok (int regno, enum machine_mode mode)
564 return m32c_hard_regno_nregs_1 (regno, mode) != 0;
567 /* Implements MODES_TIEABLE_P. In general, modes aren't tieable since
568 registers are all different sizes. However, since most modes are
569 bigger than our registers anyway, it's easier to implement this
570 function that way, leaving QImode as the only unique case. */
572 m32c_modes_tieable_p (enum machine_mode m1, enum machine_mode m2)
574 if (GET_MODE_SIZE (m1) == GET_MODE_SIZE (m2))
578 if (m1 == QImode || m2 == QImode)
585 /* Register Classes */
587 /* Implements REGNO_REG_CLASS. */
589 m32c_regno_reg_class (int regno)
613 if (IS_MEM_REGNO (regno))
619 /* Implements REG_CLASS_FROM_CONSTRAINT. Note that some constraints only match
620 for certain chip families. */
622 m32c_reg_class_from_constraint (char c ATTRIBUTE_UNUSED, const char *s)
624 if (memcmp (s, "Rsp", 3) == 0)
626 if (memcmp (s, "Rfb", 3) == 0)
628 if (memcmp (s, "Rsb", 3) == 0)
630 if (memcmp (s, "Rcr", 3) == 0)
631 return TARGET_A16 ? CR_REGS : NO_REGS;
632 if (memcmp (s, "Rcl", 3) == 0)
633 return TARGET_A24 ? CR_REGS : NO_REGS;
634 if (memcmp (s, "R0w", 3) == 0)
636 if (memcmp (s, "R1w", 3) == 0)
638 if (memcmp (s, "R2w", 3) == 0)
640 if (memcmp (s, "R3w", 3) == 0)
642 if (memcmp (s, "R02", 3) == 0)
644 if (memcmp (s, "R03", 3) == 0)
646 if (memcmp (s, "Rdi", 3) == 0)
648 if (memcmp (s, "Rhl", 3) == 0)
650 if (memcmp (s, "R23", 3) == 0)
652 if (memcmp (s, "Ra0", 3) == 0)
654 if (memcmp (s, "Ra1", 3) == 0)
656 if (memcmp (s, "Raa", 3) == 0)
658 if (memcmp (s, "Raw", 3) == 0)
659 return TARGET_A16 ? A_REGS : NO_REGS;
660 if (memcmp (s, "Ral", 3) == 0)
661 return TARGET_A24 ? A_REGS : NO_REGS;
662 if (memcmp (s, "Rqi", 3) == 0)
664 if (memcmp (s, "Rad", 3) == 0)
666 if (memcmp (s, "Rsi", 3) == 0)
668 if (memcmp (s, "Rhi", 3) == 0)
670 if (memcmp (s, "Rhc", 3) == 0)
672 if (memcmp (s, "Rra", 3) == 0)
674 if (memcmp (s, "Rfl", 3) == 0)
676 if (memcmp (s, "Rmm", 3) == 0)
678 if (fixed_regs[MEM0_REGNO])
683 /* PSImode registers - i.e. whatever can hold a pointer. */
684 if (memcmp (s, "Rpi", 3) == 0)
689 return RA_REGS; /* r2r0 and r3r1 can hold pointers. */
692 /* We handle this one as an EXTRA_CONSTRAINT. */
693 if (memcmp (s, "Rpa", 3) == 0)
698 fprintf(stderr, "unrecognized R constraint: %.3s\n", s);
705 /* Implements REGNO_OK_FOR_BASE_P. */
707 m32c_regno_ok_for_base_p (int regno)
709 if (regno == A0_REGNO
710 || regno == A1_REGNO || regno >= FIRST_PSEUDO_REGISTER)
715 #define DEBUG_RELOAD 0
717 /* Implements PREFERRED_RELOAD_CLASS. In general, prefer general
718 registers of the appropriate size. */
720 m32c_preferred_reload_class (rtx x, int rclass)
722 int newclass = rclass;
725 fprintf (stderr, "\npreferred_reload_class for %s is ",
726 class_names[rclass]);
728 if (rclass == NO_REGS)
729 rclass = GET_MODE (x) == QImode ? HL_REGS : R03_REGS;
731 if (classes_intersect (rclass, CR_REGS))
733 switch (GET_MODE (x))
739 /* newclass = HI_REGS; */
744 else if (newclass == QI_REGS && GET_MODE_SIZE (GET_MODE (x)) > 2)
746 else if (GET_MODE_SIZE (GET_MODE (x)) > 4
747 && ~class_contents[rclass][0] & 0x000f)
750 rclass = reduce_class (rclass, newclass, rclass);
752 if (GET_MODE (x) == QImode)
753 rclass = reduce_class (rclass, HL_REGS, rclass);
756 fprintf (stderr, "%s\n", class_names[rclass]);
759 if (GET_CODE (x) == MEM
760 && GET_CODE (XEXP (x, 0)) == PLUS
761 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
762 fprintf (stderr, "Glorm!\n");
767 /* Implements PREFERRED_OUTPUT_RELOAD_CLASS. */
769 m32c_preferred_output_reload_class (rtx x, int rclass)
771 return m32c_preferred_reload_class (x, rclass);
774 /* Implements LIMIT_RELOAD_CLASS. We basically want to avoid using
775 address registers for reloads since they're needed for address
778 m32c_limit_reload_class (enum machine_mode mode, int rclass)
781 fprintf (stderr, "limit_reload_class for %s: %s ->",
782 mode_name[mode], class_names[rclass]);
786 rclass = reduce_class (rclass, HL_REGS, rclass);
787 else if (mode == HImode)
788 rclass = reduce_class (rclass, HI_REGS, rclass);
789 else if (mode == SImode)
790 rclass = reduce_class (rclass, SI_REGS, rclass);
792 if (rclass != A_REGS)
793 rclass = reduce_class (rclass, DI_REGS, rclass);
796 fprintf (stderr, " %s\n", class_names[rclass]);
801 /* Implements SECONDARY_RELOAD_CLASS. QImode have to be reloaded in
802 r0 or r1, as those are the only real QImode registers. CR regs get
803 reloaded through appropriately sized general or address
806 m32c_secondary_reload_class (int rclass, enum machine_mode mode, rtx x)
808 int cc = class_contents[rclass][0];
810 fprintf (stderr, "\nsecondary reload class %s %s\n",
811 class_names[rclass], mode_name[mode]);
815 && GET_CODE (x) == MEM && (cc & ~class_contents[R23_REGS][0]) == 0)
817 if (classes_intersect (rclass, CR_REGS)
818 && GET_CODE (x) == REG
819 && REGNO (x) >= SB_REGNO && REGNO (x) <= SP_REGNO)
820 return TARGET_A16 ? HI_REGS : A_REGS;
824 /* Implements CLASS_LIKELY_SPILLED_P. A_REGS is needed for address
827 m32c_class_likely_spilled_p (int regclass)
829 if (regclass == A_REGS)
831 return reg_class_size[regclass] == 1;
834 /* Implements CLASS_MAX_NREGS. We calculate this according to its
835 documented meaning, to avoid potential inconsistencies with actual
836 class definitions. */
838 m32c_class_max_nregs (int regclass, enum machine_mode mode)
842 for (rn = 0; rn < FIRST_PSEUDO_REGISTER; rn++)
843 if (class_contents[regclass][0] & (1 << rn))
845 int n = m32c_hard_regno_nregs (rn, mode);
852 /* Implements CANNOT_CHANGE_MODE_CLASS. Only r0 and r1 can change to
853 QI (r0l, r1l) because the chip doesn't support QI ops on other
854 registers (well, it does on a0/a1 but if we let gcc do that, reload
855 suffers). Otherwise, we allow changes to larger modes. */
857 m32c_cannot_change_mode_class (enum machine_mode from,
858 enum machine_mode to, int rclass)
862 fprintf (stderr, "cannot change from %s to %s in %s\n",
863 mode_name[from], mode_name[to], class_names[rclass]);
866 /* If the larger mode isn't allowed in any of these registers, we
867 can't allow the change. */
868 for (rn = 0; rn < FIRST_PSEUDO_REGISTER; rn++)
869 if (class_contents[rclass][0] & (1 << rn))
870 if (! m32c_hard_regno_ok (rn, to))
874 return (class_contents[rclass][0] & 0x1ffa);
876 if (class_contents[rclass][0] & 0x0005 /* r0, r1 */
877 && GET_MODE_SIZE (from) > 1)
879 if (GET_MODE_SIZE (from) > 2) /* all other regs */
885 /* Helpers for the rest of the file. */
886 /* TRUE if the rtx is a REG rtx for the given register. */
887 #define IS_REG(rtx,regno) (GET_CODE (rtx) == REG \
888 && REGNO (rtx) == regno)
889 /* TRUE if the rtx is a pseudo - specifically, one we can use as a
890 base register in address calculations (hence the "strict"
892 #define IS_PSEUDO(rtx,strict) (!strict && GET_CODE (rtx) == REG \
893 && (REGNO (rtx) == AP_REGNO \
894 || REGNO (rtx) >= FIRST_PSEUDO_REGISTER))
896 /* Implements CONST_OK_FOR_CONSTRAINT_P. Currently, all constant
897 constraints start with 'I', with the next two characters indicating
898 the type and size of the range allowed. */
900 m32c_const_ok_for_constraint_p (HOST_WIDE_INT value,
901 char c ATTRIBUTE_UNUSED, const char *str)
903 /* s=signed u=unsigned n=nonzero m=minus l=log2able,
904 [sun] bits [SUN] bytes, p=pointer size
905 I[-0-9][0-9] matches that number */
906 if (memcmp (str, "Is3", 3) == 0)
908 return (-8 <= value && value <= 7);
910 if (memcmp (str, "IS1", 3) == 0)
912 return (-128 <= value && value <= 127);
914 if (memcmp (str, "IS2", 3) == 0)
916 return (-32768 <= value && value <= 32767);
918 if (memcmp (str, "IU2", 3) == 0)
920 return (0 <= value && value <= 65535);
922 if (memcmp (str, "IU3", 3) == 0)
924 return (0 <= value && value <= 0x00ffffff);
926 if (memcmp (str, "In4", 3) == 0)
928 return (-8 <= value && value && value <= 8);
930 if (memcmp (str, "In5", 3) == 0)
932 return (-16 <= value && value && value <= 16);
934 if (memcmp (str, "In6", 3) == 0)
936 return (-32 <= value && value && value <= 32);
938 if (memcmp (str, "IM2", 3) == 0)
940 return (-65536 <= value && value && value <= -1);
942 if (memcmp (str, "Ilb", 3) == 0)
944 int b = exact_log2 (value);
945 return (b >= 0 && b <= 7);
947 if (memcmp (str, "Imb", 3) == 0)
949 int b = exact_log2 ((value ^ 0xff) & 0xff);
950 return (b >= 0 && b <= 7);
952 if (memcmp (str, "Ilw", 3) == 0)
954 int b = exact_log2 (value);
955 return (b >= 0 && b <= 15);
957 if (memcmp (str, "Imw", 3) == 0)
959 int b = exact_log2 ((value ^ 0xffff) & 0xffff);
960 return (b >= 0 && b <= 15);
962 if (memcmp (str, "I00", 3) == 0)
969 /* Implements EXTRA_CONSTRAINT_STR (see next function too). 'S' is
970 for memory constraints, plus "Rpa" for PARALLEL rtx's we use for
971 call return values. */
973 m32c_extra_constraint_p2 (rtx value, char c ATTRIBUTE_UNUSED, const char *str)
975 encode_pattern (value);
976 if (memcmp (str, "Sd", 2) == 0)
978 /* This is the common "src/dest" address */
980 if (GET_CODE (value) == MEM && CONSTANT_P (XEXP (value, 0)))
982 if (RTX_IS ("ms") || RTX_IS ("m+si"))
984 if (RTX_IS ("m++rii"))
986 if (REGNO (patternr[3]) == FB_REGNO
987 && INTVAL (patternr[4]) == 0)
992 else if (RTX_IS ("m+ri") || RTX_IS ("m+rs") || RTX_IS ("m+r+si"))
996 if (REGNO (r) == SP_REGNO)
998 return m32c_legitimate_address_p (GET_MODE (value), XEXP (value, 0), 1);
1000 else if (memcmp (str, "Sa", 2) == 0)
1005 else if (RTX_IS ("m+ri"))
1009 return (IS_REG (r, A0_REGNO) || IS_REG (r, A1_REGNO));
1011 else if (memcmp (str, "Si", 2) == 0)
1013 return (RTX_IS ("mi") || RTX_IS ("ms") || RTX_IS ("m+si"));
1015 else if (memcmp (str, "Ss", 2) == 0)
1017 return ((RTX_IS ("mr")
1018 && (IS_REG (patternr[1], SP_REGNO)))
1019 || (RTX_IS ("m+ri") && (IS_REG (patternr[2], SP_REGNO))));
1021 else if (memcmp (str, "Sf", 2) == 0)
1023 return ((RTX_IS ("mr")
1024 && (IS_REG (patternr[1], FB_REGNO)))
1025 || (RTX_IS ("m+ri") && (IS_REG (patternr[2], FB_REGNO))));
1027 else if (memcmp (str, "Sb", 2) == 0)
1029 return ((RTX_IS ("mr")
1030 && (IS_REG (patternr[1], SB_REGNO)))
1031 || (RTX_IS ("m+ri") && (IS_REG (patternr[2], SB_REGNO))));
1033 else if (memcmp (str, "Sp", 2) == 0)
1035 /* Absolute addresses 0..0x1fff used for bit addressing (I/O ports) */
1036 return (RTX_IS ("mi")
1037 && !(INTVAL (patternr[1]) & ~0x1fff));
1039 else if (memcmp (str, "S1", 2) == 0)
1041 return r1h_operand (value, QImode);
1044 gcc_assert (str[0] != 'S');
1046 if (memcmp (str, "Rpa", 2) == 0)
1047 return GET_CODE (value) == PARALLEL;
1052 /* This is for when we're debugging the above. */
1054 m32c_extra_constraint_p (rtx value, char c, const char *str)
1056 int rv = m32c_extra_constraint_p2 (value, c, str);
1058 fprintf (stderr, "\nconstraint %.*s: %d\n", CONSTRAINT_LEN (c, str), str,
1065 /* Implements EXTRA_MEMORY_CONSTRAINT. Currently, we only use strings
1066 starting with 'S'. */
1068 m32c_extra_memory_constraint (char c, const char *str ATTRIBUTE_UNUSED)
1073 /* Implements EXTRA_ADDRESS_CONSTRAINT. We reserve 'A' strings for these,
1074 but don't currently define any. */
1076 m32c_extra_address_constraint (char c, const char *str ATTRIBUTE_UNUSED)
1081 /* STACK AND CALLING */
1085 /* Implements RETURN_ADDR_RTX. Note that R8C and M16C push 24 bits
1086 (yes, THREE bytes) onto the stack for the return address, but we
1087 don't support pointers bigger than 16 bits on those chips. This
1088 will likely wreak havoc with exception unwinding. FIXME. */
1090 m32c_return_addr_rtx (int count)
1092 enum machine_mode mode;
1098 /* we want 2[$fb] */
1107 /* FIXME: it's really 3 bytes */
1113 gen_rtx_MEM (mode, plus_constant (gen_rtx_REG (Pmode, FP_REGNO), offset));
1114 return copy_to_mode_reg (mode, ra_mem);
1117 /* Implements INCOMING_RETURN_ADDR_RTX. See comment above. */
1119 m32c_incoming_return_addr_rtx (void)
1122 return gen_rtx_MEM (PSImode, gen_rtx_REG (PSImode, SP_REGNO));
1125 /* Exception Handling Support */
1127 /* Implements EH_RETURN_DATA_REGNO. Choose registers able to hold
1130 m32c_eh_return_data_regno (int n)
1142 return INVALID_REGNUM;
1146 /* Implements EH_RETURN_STACKADJ_RTX. Saved and used later in
1147 m32c_emit_eh_epilogue. */
1149 m32c_eh_return_stackadj_rtx (void)
1151 if (!cfun->machine->eh_stack_adjust)
1155 sa = gen_rtx_REG (Pmode, R0_REGNO);
1156 cfun->machine->eh_stack_adjust = sa;
1158 return cfun->machine->eh_stack_adjust;
1161 /* Registers That Address the Stack Frame */
1163 /* Implements DWARF_FRAME_REGNUM and DBX_REGISTER_NUMBER. Note that
1164 the original spec called for dwarf numbers to vary with register
1165 width as well, for example, r0l, r0, and r2r0 would each have
1166 different dwarf numbers. GCC doesn't support this, and we don't do
1167 it, and gdb seems to like it this way anyway. */
1169 m32c_dwarf_frame_regnum (int n)
1195 return DWARF_FRAME_REGISTERS + 1;
1199 /* The frame looks like this:
1201 ap -> +------------------------------
1202 | Return address (3 or 4 bytes)
1203 | Saved FB (2 or 4 bytes)
1204 fb -> +------------------------------
1207 | through r0 as needed
1208 sp -> +------------------------------
1211 /* We use this to wrap all emitted insns in the prologue. */
1215 RTX_FRAME_RELATED_P (x) = 1;
1219 /* This maps register numbers to the PUSHM/POPM bitfield, and tells us
1220 how much the stack pointer moves for each, for each cpu family. */
1229 /* These are in reverse push (nearest-to-sp) order. */
1230 { R0_REGNO, 0x80, 2, 2 },
1231 { R1_REGNO, 0x40, 2, 2 },
1232 { R2_REGNO, 0x20, 2, 2 },
1233 { R3_REGNO, 0x10, 2, 2 },
1234 { A0_REGNO, 0x08, 2, 4 },
1235 { A1_REGNO, 0x04, 2, 4 },
1236 { SB_REGNO, 0x02, 2, 4 },
1237 { FB_REGNO, 0x01, 2, 4 }
1240 #define PUSHM_N (sizeof(pushm_info)/sizeof(pushm_info[0]))
1242 /* Returns TRUE if we need to save/restore the given register. We
1243 save everything for exception handlers, so that any register can be
1244 unwound. For interrupt handlers, we save everything if the handler
1245 calls something else (because we don't know what *that* function
1246 might do), but try to be a bit smarter if the handler is a leaf
1247 function. We always save $a0, though, because we use that in the
1248 epilogue to copy $fb to $sp. */
1250 need_to_save (int regno)
1252 if (fixed_regs[regno])
1254 if (cfun->calls_eh_return)
1256 if (regno == FP_REGNO)
1258 if (cfun->machine->is_interrupt
1259 && (!cfun->machine->is_leaf || regno == A0_REGNO))
1261 if (df_regs_ever_live_p (regno)
1262 && (!call_used_regs[regno] || cfun->machine->is_interrupt))
1267 /* This function contains all the intelligence about saving and
1268 restoring registers. It always figures out the register save set.
1269 When called with PP_justcount, it merely returns the size of the
1270 save set (for eliminating the frame pointer, for example). When
1271 called with PP_pushm or PP_popm, it emits the appropriate
1272 instructions for saving (pushm) or restoring (popm) the
1275 m32c_pushm_popm (Push_Pop_Type ppt)
1278 int byte_count = 0, bytes;
1280 rtx dwarf_set[PUSHM_N];
1282 int nosave_mask = 0;
1284 if (cfun->return_rtx
1285 && GET_CODE (cfun->return_rtx) == PARALLEL
1286 && !(cfun->calls_eh_return || cfun->machine->is_interrupt))
1288 rtx exp = XVECEXP (cfun->return_rtx, 0, 0);
1289 rtx rv = XEXP (exp, 0);
1290 int rv_bytes = GET_MODE_SIZE (GET_MODE (rv));
1293 nosave_mask |= 0x20; /* PSI, SI */
1295 nosave_mask |= 0xf0; /* DF */
1297 nosave_mask |= 0x50; /* DI */
1300 for (i = 0; i < (int) PUSHM_N; i++)
1302 /* Skip if neither register needs saving. */
1303 if (!need_to_save (pushm_info[i].reg1))
1306 if (pushm_info[i].bit & nosave_mask)
1309 reg_mask |= pushm_info[i].bit;
1310 bytes = TARGET_A16 ? pushm_info[i].a16_bytes : pushm_info[i].a24_bytes;
1312 if (ppt == PP_pushm)
1314 enum machine_mode mode = (bytes == 2) ? HImode : SImode;
1317 /* Always use stack_pointer_rtx instead of calling
1318 rtx_gen_REG ourselves. Code elsewhere in GCC assumes
1319 that there is a single rtx representing the stack pointer,
1320 namely stack_pointer_rtx, and uses == to recognize it. */
1321 addr = stack_pointer_rtx;
1323 if (byte_count != 0)
1324 addr = gen_rtx_PLUS (GET_MODE (addr), addr, GEN_INT (byte_count));
1326 dwarf_set[n_dwarfs++] =
1327 gen_rtx_SET (VOIDmode,
1328 gen_rtx_MEM (mode, addr),
1329 gen_rtx_REG (mode, pushm_info[i].reg1));
1330 F (dwarf_set[n_dwarfs - 1]);
1333 byte_count += bytes;
1336 if (cfun->machine->is_interrupt)
1338 cfun->machine->intr_pushm = reg_mask & 0xfe;
1343 if (cfun->machine->is_interrupt)
1344 for (i = MEM0_REGNO; i <= MEM7_REGNO; i++)
1345 if (need_to_save (i))
1348 cfun->machine->intr_pushmem[i - MEM0_REGNO] = 1;
1351 if (ppt == PP_pushm && byte_count)
1353 rtx note = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (n_dwarfs + 1));
1358 XVECEXP (note, 0, 0)
1359 = gen_rtx_SET (VOIDmode,
1361 gen_rtx_PLUS (GET_MODE (stack_pointer_rtx),
1363 GEN_INT (-byte_count)));
1364 F (XVECEXP (note, 0, 0));
1366 for (i = 0; i < n_dwarfs; i++)
1367 XVECEXP (note, 0, i + 1) = dwarf_set[i];
1369 pushm = F (emit_insn (gen_pushm (GEN_INT (reg_mask))));
1371 REG_NOTES (pushm) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, note,
1375 if (cfun->machine->is_interrupt)
1376 for (i = MEM0_REGNO; i <= MEM7_REGNO; i++)
1377 if (cfun->machine->intr_pushmem[i - MEM0_REGNO])
1380 pushm = emit_insn (gen_pushhi_16 (gen_rtx_REG (HImode, i)));
1382 pushm = emit_insn (gen_pushhi_24 (gen_rtx_REG (HImode, i)));
1386 if (ppt == PP_popm && byte_count)
1388 if (cfun->machine->is_interrupt)
1389 for (i = MEM7_REGNO; i >= MEM0_REGNO; i--)
1390 if (cfun->machine->intr_pushmem[i - MEM0_REGNO])
1393 emit_insn (gen_pophi_16 (gen_rtx_REG (HImode, i)));
1395 emit_insn (gen_pophi_24 (gen_rtx_REG (HImode, i)));
1398 emit_insn (gen_popm (GEN_INT (reg_mask)));
1404 /* Implements INITIAL_ELIMINATION_OFFSET. See the comment above that
1405 diagrams our call frame. */
1407 m32c_initial_elimination_offset (int from, int to)
1411 if (from == AP_REGNO)
1421 ofs += m32c_pushm_popm (PP_justcount);
1422 ofs += get_frame_size ();
1425 /* Account for push rounding. */
1427 ofs = (ofs + 1) & ~1;
1429 fprintf (stderr, "initial_elimination_offset from=%d to=%d, ofs=%d\n", from,
1435 /* Passing Function Arguments on the Stack */
1437 #undef TARGET_PROMOTE_PROTOTYPES
1438 #define TARGET_PROMOTE_PROTOTYPES m32c_promote_prototypes
1440 m32c_promote_prototypes (const_tree fntype ATTRIBUTE_UNUSED)
1445 /* Implements PUSH_ROUNDING. The R8C and M16C have byte stacks, the
1446 M32C has word stacks. */
1448 m32c_push_rounding (int n)
1450 if (TARGET_R8C || TARGET_M16C)
1452 return (n + 1) & ~1;
1455 /* Passing Arguments in Registers */
1457 /* Implements FUNCTION_ARG. Arguments are passed partly in registers,
1458 partly on stack. If our function returns a struct, a pointer to a
1459 buffer for it is at the top of the stack (last thing pushed). The
1460 first few real arguments may be in registers as follows:
1462 R8C/M16C: arg1 in r1 if it's QI or HI (else it's pushed on stack)
1463 arg2 in r2 if it's HI (else pushed on stack)
1465 M32C: arg1 in r0 if it's QI or HI (else it's pushed on stack)
1468 Structs are not passed in registers, even if they fit. Only
1469 integer and pointer types are passed in registers.
1471 Note that when arg1 doesn't fit in r1, arg2 may still be passed in
1474 m32c_function_arg (CUMULATIVE_ARGS * ca,
1475 enum machine_mode mode, tree type, int named)
1477 /* Can return a reg, parallel, or 0 for stack */
1480 fprintf (stderr, "func_arg %d (%s, %d)\n",
1481 ca->parm_num, mode_name[mode], named);
1485 if (mode == VOIDmode)
1488 if (ca->force_mem || !named)
1491 fprintf (stderr, "func arg: force %d named %d, mem\n", ca->force_mem,
1497 if (type && INTEGRAL_TYPE_P (type) && POINTER_TYPE_P (type))
1500 if (type && AGGREGATE_TYPE_P (type))
1503 switch (ca->parm_num)
1506 if (GET_MODE_SIZE (mode) == 1 || GET_MODE_SIZE (mode) == 2)
1507 rv = gen_rtx_REG (mode, TARGET_A16 ? R1_REGNO : R0_REGNO);
1511 if (TARGET_A16 && GET_MODE_SIZE (mode) == 2)
1512 rv = gen_rtx_REG (mode, R2_REGNO);
1522 #undef TARGET_PASS_BY_REFERENCE
1523 #define TARGET_PASS_BY_REFERENCE m32c_pass_by_reference
1525 m32c_pass_by_reference (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED,
1526 enum machine_mode mode ATTRIBUTE_UNUSED,
1527 const_tree type ATTRIBUTE_UNUSED,
1528 bool named ATTRIBUTE_UNUSED)
1533 /* Implements INIT_CUMULATIVE_ARGS. */
1535 m32c_init_cumulative_args (CUMULATIVE_ARGS * ca,
1537 rtx libname ATTRIBUTE_UNUSED,
1539 int n_named_args ATTRIBUTE_UNUSED)
1541 if (fntype && aggregate_value_p (TREE_TYPE (fntype), fndecl))
1548 /* Implements FUNCTION_ARG_ADVANCE. force_mem is set for functions
1549 returning structures, so we always reset that. Otherwise, we only
1550 need to know the sequence number of the argument to know what to do
1553 m32c_function_arg_advance (CUMULATIVE_ARGS * ca,
1554 enum machine_mode mode ATTRIBUTE_UNUSED,
1555 tree type ATTRIBUTE_UNUSED,
1556 int named ATTRIBUTE_UNUSED)
1564 /* Implements FUNCTION_ARG_REGNO_P. */
1566 m32c_function_arg_regno_p (int r)
1569 return (r == R0_REGNO);
1570 return (r == R1_REGNO || r == R2_REGNO);
1573 /* HImode and PSImode are the two "native" modes as far as GCC is
1574 concerned, but the chips also support a 32-bit mode which is used
1575 for some opcodes in R8C/M16C and for reset vectors and such. */
1576 #undef TARGET_VALID_POINTER_MODE
1577 #define TARGET_VALID_POINTER_MODE m32c_valid_pointer_mode
1579 m32c_valid_pointer_mode (enum machine_mode mode)
1589 /* How Scalar Function Values Are Returned */
1591 /* Implements LIBCALL_VALUE. Most values are returned in $r0, or some
1592 combination of registers starting there (r2r0 for longs, r3r1r2r0
1593 for long long, r3r2r1r0 for doubles), except that that ABI
1594 currently doesn't work because it ends up using all available
1595 general registers and gcc often can't compile it. So, instead, we
1596 return anything bigger than 16 bits in "mem0" (effectively, a
1597 memory location). */
1599 m32c_libcall_value (enum machine_mode mode)
1601 /* return reg or parallel */
1603 /* FIXME: GCC has difficulty returning large values in registers,
1604 because that ties up most of the general registers and gives the
1605 register allocator little to work with. Until we can resolve
1606 this, large values are returned in memory. */
1611 rv = gen_rtx_PARALLEL (mode, rtvec_alloc (4));
1612 XVECEXP (rv, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode,
1613 gen_rtx_REG (HImode,
1616 XVECEXP (rv, 0, 1) = gen_rtx_EXPR_LIST (VOIDmode,
1617 gen_rtx_REG (HImode,
1620 XVECEXP (rv, 0, 2) = gen_rtx_EXPR_LIST (VOIDmode,
1621 gen_rtx_REG (HImode,
1624 XVECEXP (rv, 0, 3) = gen_rtx_EXPR_LIST (VOIDmode,
1625 gen_rtx_REG (HImode,
1631 if (TARGET_A24 && GET_MODE_SIZE (mode) > 2)
1635 rv = gen_rtx_PARALLEL (mode, rtvec_alloc (1));
1636 XVECEXP (rv, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode,
1644 if (GET_MODE_SIZE (mode) > 2)
1645 return gen_rtx_REG (mode, MEM0_REGNO);
1646 return gen_rtx_REG (mode, R0_REGNO);
1649 /* Implements FUNCTION_VALUE. Functions and libcalls have the same
1652 m32c_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED)
1654 /* return reg or parallel */
1655 const enum machine_mode mode = TYPE_MODE (valtype);
1656 return m32c_libcall_value (mode);
1659 /* How Large Values Are Returned */
1661 /* We return structures by pushing the address on the stack, even if
1662 we use registers for the first few "real" arguments. */
1663 #undef TARGET_STRUCT_VALUE_RTX
1664 #define TARGET_STRUCT_VALUE_RTX m32c_struct_value_rtx
1666 m32c_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED,
1667 int incoming ATTRIBUTE_UNUSED)
1672 /* Function Entry and Exit */
1674 /* Implements EPILOGUE_USES. Interrupts restore all registers. */
1676 m32c_epilogue_uses (int regno ATTRIBUTE_UNUSED)
1678 if (cfun->machine->is_interrupt)
1683 /* Implementing the Varargs Macros */
1685 #undef TARGET_STRICT_ARGUMENT_NAMING
1686 #define TARGET_STRICT_ARGUMENT_NAMING m32c_strict_argument_naming
1688 m32c_strict_argument_naming (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED)
1693 /* Trampolines for Nested Functions */
1697 1 0000 75C43412 mov.w #0x1234,a0
1698 2 0004 FC000000 jmp.a label
1701 1 0000 BC563412 mov.l:s #0x123456,a0
1702 2 0004 CC000000 jmp.a label
1705 /* Implements TRAMPOLINE_SIZE. */
1707 m32c_trampoline_size (void)
1709 /* Allocate extra space so we can avoid the messy shifts when we
1710 initialize the trampoline; we just write past the end of the
1712 return TARGET_A16 ? 8 : 10;
1715 /* Implements TRAMPOLINE_ALIGNMENT. */
1717 m32c_trampoline_alignment (void)
1722 /* Implements INITIALIZE_TRAMPOLINE. */
1724 m32c_initialize_trampoline (rtx tramp, rtx function, rtx chainval)
1726 #define A0(m,i) gen_rtx_MEM (m, plus_constant (tramp, i))
1729 /* Note: we subtract a "word" because the moves want signed
1730 constants, not unsigned constants. */
1731 emit_move_insn (A0 (HImode, 0), GEN_INT (0xc475 - 0x10000));
1732 emit_move_insn (A0 (HImode, 2), chainval);
1733 emit_move_insn (A0 (QImode, 4), GEN_INT (0xfc - 0x100));
1734 /* We use 16-bit addresses here, but store the zero to turn it
1735 into a 24-bit offset. */
1736 emit_move_insn (A0 (HImode, 5), function);
1737 emit_move_insn (A0 (QImode, 7), GEN_INT (0x00));
1741 /* Note that the PSI moves actually write 4 bytes. Make sure we
1742 write stuff out in the right order, and leave room for the
1743 extra byte at the end. */
1744 emit_move_insn (A0 (QImode, 0), GEN_INT (0xbc - 0x100));
1745 emit_move_insn (A0 (PSImode, 1), chainval);
1746 emit_move_insn (A0 (QImode, 4), GEN_INT (0xcc - 0x100));
1747 emit_move_insn (A0 (PSImode, 5), function);
1752 /* Implicit Calls to Library Routines */
1754 #undef TARGET_INIT_LIBFUNCS
1755 #define TARGET_INIT_LIBFUNCS m32c_init_libfuncs
1757 m32c_init_libfuncs (void)
1761 /* We do this because the M32C has an HImode operand, but the
1762 M16C has an 8-bit operand. Since gcc looks at the match data
1763 and not the expanded rtl, we have to reset the array so that
1764 the right modes are found. */
1765 setcc_gen_code[EQ] = CODE_FOR_seq_24;
1766 setcc_gen_code[NE] = CODE_FOR_sne_24;
1767 setcc_gen_code[GT] = CODE_FOR_sgt_24;
1768 setcc_gen_code[GE] = CODE_FOR_sge_24;
1769 setcc_gen_code[LT] = CODE_FOR_slt_24;
1770 setcc_gen_code[LE] = CODE_FOR_sle_24;
1771 setcc_gen_code[GTU] = CODE_FOR_sgtu_24;
1772 setcc_gen_code[GEU] = CODE_FOR_sgeu_24;
1773 setcc_gen_code[LTU] = CODE_FOR_sltu_24;
1774 setcc_gen_code[LEU] = CODE_FOR_sleu_24;
1778 /* Addressing Modes */
1780 /* Used by GO_IF_LEGITIMATE_ADDRESS. The r8c/m32c family supports a
1781 wide range of non-orthogonal addressing modes, including the
1782 ability to double-indirect on *some* of them. Not all insns
1783 support all modes, either, but we rely on predicates and
1784 constraints to deal with that. */
1786 m32c_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1792 /* Wide references to memory will be split after reload, so we must
1793 ensure that all parts of such splits remain legitimate
1795 mode_adjust = GET_MODE_SIZE (mode) - 1;
1797 /* allowing PLUS yields mem:HI(plus:SI(mem:SI(plus:SI in m32c_split_move */
1798 if (GET_CODE (x) == PRE_DEC
1799 || GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_MODIFY)
1801 return (GET_CODE (XEXP (x, 0)) == REG
1802 && REGNO (XEXP (x, 0)) == SP_REGNO);
1806 /* This is the double indirection detection, but it currently
1807 doesn't work as cleanly as this code implies, so until we've had
1808 a chance to debug it, leave it disabled. */
1809 if (TARGET_A24 && GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) != PLUS)
1812 fprintf (stderr, "double indirect\n");
1821 /* Most indexable registers can be used without displacements,
1822 although some of them will be emitted with an explicit zero
1823 to please the assembler. */
1824 switch (REGNO (patternr[0]))
1834 if (IS_PSEUDO (patternr[0], strict))
1841 /* This is more interesting, because different base registers
1842 allow for different displacements - both range and signedness
1843 - and it differs from chip series to chip series too. */
1844 int rn = REGNO (patternr[1]);
1845 HOST_WIDE_INT offs = INTVAL (patternr[2]);
1851 /* The syntax only allows positive offsets, but when the
1852 offsets span the entire memory range, we can simulate
1853 negative offsets by wrapping. */
1855 return (offs >= -65536 && offs <= 65535 - mode_adjust);
1857 return (offs >= 0 && offs <= 65535 - mode_adjust);
1859 return (offs >= -16777216 && offs <= 16777215);
1863 return (offs >= -128 && offs <= 127 - mode_adjust);
1864 return (offs >= -65536 && offs <= 65535 - mode_adjust);
1867 return (offs >= -128 && offs <= 127 - mode_adjust);
1870 if (IS_PSEUDO (patternr[1], strict))
1875 if (RTX_IS ("+rs") || RTX_IS ("+r+si"))
1877 rtx reg = patternr[1];
1879 /* We don't know where the symbol is, so only allow base
1880 registers which support displacements spanning the whole
1882 switch (REGNO (reg))
1886 /* $sb needs a secondary reload, but since it's involved in
1887 memory address reloads too, we don't deal with it very
1889 /* case SB_REGNO: */
1892 if (IS_PSEUDO (reg, strict))
1900 /* Implements REG_OK_FOR_BASE_P. */
1902 m32c_reg_ok_for_base_p (rtx x, int strict)
1904 if (GET_CODE (x) != REG)
1915 if (IS_PSEUDO (x, strict))
1921 /* We have three choices for choosing fb->aN offsets. If we choose -128,
1922 we need one MOVA -128[fb],aN opcode and 16-bit aN displacements,
1924 EB 4B FF mova -128[$fb],$a0
1925 D8 0C FF FF mov.w:Q #0,-1[$a0]
1927 Alternately, we subtract the frame size, and hopefully use 8-bit aN
1930 77 54 00 01 sub #256,$a0
1931 D8 08 01 mov.w:Q #0,1[$a0]
1933 If we don't offset (i.e. offset by zero), we end up with:
1935 D8 0C 00 FF mov.w:Q #0,-256[$a0]
1937 We have to subtract *something* so that we have a PLUS rtx to mark
1938 that we've done this reload. The -128 offset will never result in
1939 an 8-bit aN offset, and the payoff for the second case is five
1940 loads *if* those loads are within 256 bytes of the other end of the
1941 frame, so the third case seems best. Note that we subtract the
1942 zero, but detect that in the addhi3 pattern. */
1944 #define BIG_FB_ADJ 0
1946 /* Implements LEGITIMIZE_ADDRESS. The only address we really have to
1947 worry about is frame base offsets, as $fb has a limited
1948 displacement range. We deal with this by attempting to reload $fb
1949 itself into an address register; that seems to result in the best
1952 m32c_legitimize_address (rtx * x ATTRIBUTE_UNUSED,
1953 rtx oldx ATTRIBUTE_UNUSED,
1954 enum machine_mode mode ATTRIBUTE_UNUSED)
1957 fprintf (stderr, "m32c_legitimize_address for mode %s\n", mode_name[mode]);
1959 fprintf (stderr, "\n");
1962 if (GET_CODE (*x) == PLUS
1963 && GET_CODE (XEXP (*x, 0)) == REG
1964 && REGNO (XEXP (*x, 0)) == FB_REGNO
1965 && GET_CODE (XEXP (*x, 1)) == CONST_INT
1966 && (INTVAL (XEXP (*x, 1)) < -128
1967 || INTVAL (XEXP (*x, 1)) > (128 - GET_MODE_SIZE (mode))))
1969 /* reload FB to A_REGS */
1970 rtx temp = gen_reg_rtx (Pmode);
1972 emit_insn (gen_rtx_SET (VOIDmode, temp, XEXP (*x, 0)));
1973 XEXP (*x, 0) = temp;
1980 /* Implements LEGITIMIZE_RELOAD_ADDRESS. See comment above. */
1982 m32c_legitimize_reload_address (rtx * x,
1983 enum machine_mode mode,
1985 int type, int ind_levels ATTRIBUTE_UNUSED)
1988 fprintf (stderr, "\nm32c_legitimize_reload_address for mode %s\n",
1993 /* At one point, this function tried to get $fb copied to an address
1994 register, which in theory would maximize sharing, but gcc was
1995 *also* still trying to reload the whole address, and we'd run out
1996 of address registers. So we let gcc do the naive (but safe)
1997 reload instead, when the above function doesn't handle it for
2000 The code below is a second attempt at the above. */
2002 if (GET_CODE (*x) == PLUS
2003 && GET_CODE (XEXP (*x, 0)) == REG
2004 && REGNO (XEXP (*x, 0)) == FB_REGNO
2005 && GET_CODE (XEXP (*x, 1)) == CONST_INT
2006 && (INTVAL (XEXP (*x, 1)) < -128
2007 || INTVAL (XEXP (*x, 1)) > (128 - GET_MODE_SIZE (mode))))
2010 int offset = INTVAL (XEXP (*x, 1));
2011 int adjustment = -BIG_FB_ADJ;
2013 sum = gen_rtx_PLUS (Pmode, XEXP (*x, 0),
2014 GEN_INT (adjustment));
2015 *x = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - adjustment));
2016 if (type == RELOAD_OTHER)
2017 type = RELOAD_FOR_OTHER_ADDRESS;
2018 push_reload (sum, NULL_RTX, &XEXP (*x, 0), NULL,
2019 A_REGS, Pmode, VOIDmode, 0, 0, opnum,
2024 if (GET_CODE (*x) == PLUS
2025 && GET_CODE (XEXP (*x, 0)) == PLUS
2026 && GET_CODE (XEXP (XEXP (*x, 0), 0)) == REG
2027 && REGNO (XEXP (XEXP (*x, 0), 0)) == FB_REGNO
2028 && GET_CODE (XEXP (XEXP (*x, 0), 1)) == CONST_INT
2029 && GET_CODE (XEXP (*x, 1)) == CONST_INT
2032 if (type == RELOAD_OTHER)
2033 type = RELOAD_FOR_OTHER_ADDRESS;
2034 push_reload (XEXP (*x, 0), NULL_RTX, &XEXP (*x, 0), NULL,
2035 A_REGS, Pmode, VOIDmode, 0, 0, opnum,
2043 /* Implements LEGITIMATE_CONSTANT_P. We split large constants anyway,
2044 so we can allow anything. */
2046 m32c_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED)
2052 /* Condition Code Status */
2054 #undef TARGET_FIXED_CONDITION_CODE_REGS
2055 #define TARGET_FIXED_CONDITION_CODE_REGS m32c_fixed_condition_code_regs
2057 m32c_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
2060 *p2 = INVALID_REGNUM;
2064 /* Describing Relative Costs of Operations */
2066 /* Implements REGISTER_MOVE_COST. We make impossible moves
2067 prohibitively expensive, like trying to put QIs in r2/r3 (there are
2068 no opcodes to do that). We also discourage use of mem* registers
2069 since they're really memory. */
2071 m32c_register_move_cost (enum machine_mode mode, int from, int to)
2073 int cost = COSTS_N_INSNS (3);
2074 int cc = class_contents[from][0] | class_contents[to][0];
2075 /* FIXME: pick real values, but not 2 for now. */
2076 if (mode == QImode && (cc & class_contents[R23_REGS][0]))
2078 if (!(cc & ~class_contents[R23_REGS][0]))
2079 cost = COSTS_N_INSNS (1000);
2081 cost = COSTS_N_INSNS (80);
2084 if (!class_can_hold_mode (from, mode) || !class_can_hold_mode (to, mode))
2085 cost = COSTS_N_INSNS (1000);
2087 if (classes_intersect (from, CR_REGS))
2088 cost += COSTS_N_INSNS (5);
2090 if (classes_intersect (to, CR_REGS))
2091 cost += COSTS_N_INSNS (5);
2093 if (from == MEM_REGS || to == MEM_REGS)
2094 cost += COSTS_N_INSNS (50);
2095 else if (classes_intersect (from, MEM_REGS)
2096 || classes_intersect (to, MEM_REGS))
2097 cost += COSTS_N_INSNS (10);
2100 fprintf (stderr, "register_move_cost %s from %s to %s = %d\n",
2101 mode_name[mode], class_names[from], class_names[to], cost);
2106 /* Implements MEMORY_MOVE_COST. */
2108 m32c_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2109 int reg_class ATTRIBUTE_UNUSED,
2110 int in ATTRIBUTE_UNUSED)
2112 /* FIXME: pick real values. */
2113 return COSTS_N_INSNS (10);
2116 /* Here we try to describe when we use multiple opcodes for one RTX so
2117 that gcc knows when to use them. */
2118 #undef TARGET_RTX_COSTS
2119 #define TARGET_RTX_COSTS m32c_rtx_costs
2121 m32c_rtx_costs (rtx x, int code, int outer_code, int *total)
2126 if (REGNO (x) >= MEM0_REGNO && REGNO (x) <= MEM7_REGNO)
2127 *total += COSTS_N_INSNS (500);
2129 *total += COSTS_N_INSNS (1);
2135 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2137 /* mov.b r1l, r1h */
2138 *total += COSTS_N_INSNS (1);
2141 if (INTVAL (XEXP (x, 1)) > 8
2142 || INTVAL (XEXP (x, 1)) < -8)
2145 /* mov.b r1l, r1h */
2146 *total += COSTS_N_INSNS (2);
2161 if (outer_code == SET)
2163 *total += COSTS_N_INSNS (2);
2170 rtx dest = XEXP (x, 0);
2171 rtx addr = XEXP (dest, 0);
2172 switch (GET_CODE (addr))
2175 *total += COSTS_N_INSNS (1);
2178 *total += COSTS_N_INSNS (3);
2181 *total += COSTS_N_INSNS (2);
2189 /* Reasonable default. */
2190 if (TARGET_A16 && GET_MODE(x) == SImode)
2191 *total += COSTS_N_INSNS (2);
2197 #undef TARGET_ADDRESS_COST
2198 #define TARGET_ADDRESS_COST m32c_address_cost
2200 m32c_address_cost (rtx addr)
2202 /* fprintf(stderr, "\naddress_cost\n");
2204 switch (GET_CODE (addr))
2207 return COSTS_N_INSNS(1);
2209 return COSTS_N_INSNS(3);
2211 return COSTS_N_INSNS(2);
2217 /* Defining the Output Assembler Language */
2219 /* The Overall Framework of an Assembler File */
2221 #undef TARGET_HAVE_NAMED_SECTIONS
2222 #define TARGET_HAVE_NAMED_SECTIONS true
2224 /* Output of Data */
2226 /* We may have 24 bit sizes, which is the native address size.
2227 Currently unused, but provided for completeness. */
2228 #undef TARGET_ASM_INTEGER
2229 #define TARGET_ASM_INTEGER m32c_asm_integer
2231 m32c_asm_integer (rtx x, unsigned int size, int aligned_p)
2236 fprintf (asm_out_file, "\t.3byte\t");
2237 output_addr_const (asm_out_file, x);
2238 fputc ('\n', asm_out_file);
2241 if (GET_CODE (x) == SYMBOL_REF)
2243 fprintf (asm_out_file, "\t.long\t");
2244 output_addr_const (asm_out_file, x);
2245 fputc ('\n', asm_out_file);
2250 return default_assemble_integer (x, size, aligned_p);
2253 /* Output of Assembler Instructions */
2255 /* We use a lookup table because the addressing modes are non-orthogonal. */
2260 char const *pattern;
2263 const conversions[] = {
2266 { 0, "mr", "z[1]" },
2267 { 0, "m+ri", "3[2]" },
2268 { 0, "m+rs", "3[2]" },
2269 { 0, "m+r+si", "4+5[2]" },
2272 { 0, "m+si", "2+3" },
2274 { 0, "mmr", "[z[2]]" },
2275 { 0, "mm+ri", "[4[3]]" },
2276 { 0, "mm+rs", "[4[3]]" },
2277 { 0, "mm+r+si", "[5+6[3]]" },
2278 { 0, "mms", "[[2]]" },
2279 { 0, "mmi", "[[2]]" },
2280 { 0, "mm+si", "[4[3]]" },
2284 { 0, "+si", "#1+2" },
2290 { 'd', "+si", "1+2" },
2293 { 'D', "+si", "1+2" },
2304 /* This is in order according to the bitfield that pushm/popm use. */
2305 static char const *pushm_regs[] = {
2306 "fb", "sb", "a1", "a0", "r3", "r2", "r1", "r0"
2309 /* Implements PRINT_OPERAND. */
2311 m32c_print_operand (FILE * file, rtx x, int code)
2316 int unsigned_const = 0;
2319 /* Multiplies; constants are converted to sign-extended format but
2320 we need unsigned, so 'u' and 'U' tell us what size unsigned we
2332 /* This one is only for debugging; you can put it in a pattern to
2333 force this error. */
2336 fprintf (stderr, "dj: unreviewed pattern:");
2337 if (current_output_insn)
2338 debug_rtx (current_output_insn);
2341 /* PSImode operations are either .w or .l depending on the target. */
2345 fprintf (file, "w");
2347 fprintf (file, "l");
2350 /* Inverted conditionals. */
2353 switch (GET_CODE (x))
2359 fputs ("gtu", file);
2365 fputs ("geu", file);
2371 fputs ("leu", file);
2377 fputs ("ltu", file);
2390 /* Regular conditionals. */
2393 switch (GET_CODE (x))
2399 fputs ("leu", file);
2405 fputs ("ltu", file);
2411 fputs ("gtu", file);
2417 fputs ("geu", file);
2430 /* Used in negsi2 to do HImode ops on the two parts of an SImode
2432 if (code == 'h' && GET_MODE (x) == SImode)
2434 x = m32c_subreg (HImode, x, SImode, 0);
2437 if (code == 'H' && GET_MODE (x) == SImode)
2439 x = m32c_subreg (HImode, x, SImode, 2);
2442 if (code == 'h' && GET_MODE (x) == HImode)
2444 x = m32c_subreg (QImode, x, HImode, 0);
2447 if (code == 'H' && GET_MODE (x) == HImode)
2449 /* We can't actually represent this as an rtx. Do it here. */
2450 if (GET_CODE (x) == REG)
2455 fputs ("r0h", file);
2458 fputs ("r1h", file);
2464 /* This should be a MEM. */
2465 x = m32c_subreg (QImode, x, HImode, 1);
2468 /* This is for BMcond, which always wants word register names. */
2469 if (code == 'h' && GET_MODE (x) == QImode)
2471 if (GET_CODE (x) == REG)
2472 x = gen_rtx_REG (HImode, REGNO (x));
2475 /* 'x' and 'X' need to be ignored for non-immediates. */
2476 if ((code == 'x' || code == 'X') && GET_CODE (x) != CONST_INT)
2481 for (i = 0; conversions[i].pattern; i++)
2482 if (conversions[i].code == code
2483 && streq (conversions[i].pattern, pattern))
2485 for (j = 0; conversions[i].format[j]; j++)
2486 /* backslash quotes the next character in the output pattern. */
2487 if (conversions[i].format[j] == '\\')
2489 fputc (conversions[i].format[j + 1], file);
2492 /* Digits in the output pattern indicate that the
2493 corresponding RTX is to be output at that point. */
2494 else if (ISDIGIT (conversions[i].format[j]))
2496 rtx r = patternr[conversions[i].format[j] - '0'];
2497 switch (GET_CODE (r))
2500 fprintf (file, "%s",
2501 reg_name_with_mode (REGNO (r), GET_MODE (r)));
2510 int i = (int) exact_log2 (v);
2512 i = (int) exact_log2 ((v ^ 0xffff) & 0xffff);
2514 i = (int) exact_log2 ((v ^ 0xff) & 0xff);
2516 fprintf (file, "%d", i);
2520 /* Unsigned byte. */
2521 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2525 /* Unsigned word. */
2526 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2527 INTVAL (r) & 0xffff);
2530 /* pushm and popm encode a register set into a single byte. */
2532 for (b = 7; b >= 0; b--)
2533 if (INTVAL (r) & (1 << b))
2535 fprintf (file, "%s%s", comma, pushm_regs[b]);
2540 /* "Minus". Output -X */
2541 ival = (-INTVAL (r) & 0xffff);
2543 ival = ival - 0x10000;
2544 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
2548 if (conversions[i].format[j + 1] == '[' && ival < 0)
2550 /* We can simulate negative displacements by
2551 taking advantage of address space
2552 wrapping when the offset can span the
2553 entire address range. */
2555 patternr[conversions[i].format[j + 2] - '0'];
2556 if (GET_CODE (base) == REG)
2557 switch (REGNO (base))
2562 ival = 0x1000000 + ival;
2564 ival = 0x10000 + ival;
2568 ival = 0x10000 + ival;
2572 else if (code == 'd' && ival < 0 && j == 0)
2573 /* The "mova" opcode is used to do addition by
2574 computing displacements, but again, we need
2575 displacements to be unsigned *if* they're
2576 the only component of the displacement
2577 (i.e. no "symbol-4" type displacement). */
2578 ival = (TARGET_A24 ? 0x1000000 : 0x10000) + ival;
2580 if (conversions[i].format[j] == '0')
2582 /* More conversions to unsigned. */
2583 if (unsigned_const == 2)
2585 if (unsigned_const == 1)
2588 if (streq (conversions[i].pattern, "mi")
2589 || streq (conversions[i].pattern, "mmi"))
2591 /* Integers used as addresses are unsigned. */
2592 ival &= (TARGET_A24 ? 0xffffff : 0xffff);
2594 if (force_sign && ival >= 0)
2596 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
2601 /* We don't have const_double constants. If it
2602 happens, make it obvious. */
2603 fprintf (file, "[const_double 0x%lx]",
2604 (unsigned long) CONST_DOUBLE_HIGH (r));
2607 assemble_name (file, XSTR (r, 0));
2610 output_asm_label (r);
2613 fprintf (stderr, "don't know how to print this operand:");
2620 if (conversions[i].format[j] == 'z')
2622 /* Some addressing modes *must* have a displacement,
2623 so insert a zero here if needed. */
2625 for (k = j + 1; conversions[i].format[k]; k++)
2626 if (ISDIGIT (conversions[i].format[k]))
2628 rtx reg = patternr[conversions[i].format[k] - '0'];
2629 if (GET_CODE (reg) == REG
2630 && (REGNO (reg) == SB_REGNO
2631 || REGNO (reg) == FB_REGNO
2632 || REGNO (reg) == SP_REGNO))
2637 /* Signed displacements off symbols need to have signs
2639 if (conversions[i].format[j] == '+'
2640 && (!code || code == 'D' || code == 'd')
2641 && ISDIGIT (conversions[i].format[j + 1])
2642 && (GET_CODE (patternr[conversions[i].format[j + 1] - '0'])
2648 fputc (conversions[i].format[j], file);
2652 if (!conversions[i].pattern)
2654 fprintf (stderr, "unconvertible operand %c `%s'", code ? code : '-',
2657 fprintf (file, "[%c.%s]", code ? code : '-', pattern);
2663 /* Implements PRINT_OPERAND_PUNCT_VALID_P. See m32c_print_operand
2664 above for descriptions of what these do. */
2666 m32c_print_operand_punct_valid_p (int c)
2668 if (c == '&' || c == '!')
2673 /* Implements PRINT_OPERAND_ADDRESS. Nothing unusual here. */
2675 m32c_print_operand_address (FILE * stream, rtx address)
2677 gcc_assert (GET_CODE (address) == MEM);
2678 m32c_print_operand (stream, XEXP (address, 0), 0);
2681 /* Implements ASM_OUTPUT_REG_PUSH. Control registers are pushed
2682 differently than general registers. */
2684 m32c_output_reg_push (FILE * s, int regno)
2686 if (regno == FLG_REGNO)
2687 fprintf (s, "\tpushc\tflg\n");
2689 fprintf (s, "\tpush.%c\t%s\n",
2690 " bwll"[reg_push_size (regno)], reg_names[regno]);
2693 /* Likewise for ASM_OUTPUT_REG_POP. */
2695 m32c_output_reg_pop (FILE * s, int regno)
2697 if (regno == FLG_REGNO)
2698 fprintf (s, "\tpopc\tflg\n");
2700 fprintf (s, "\tpop.%c\t%s\n",
2701 " bwll"[reg_push_size (regno)], reg_names[regno]);
2704 /* Defining target-specific uses of `__attribute__' */
2706 /* Used to simplify the logic below. Find the attributes wherever
2708 #define M32C_ATTRIBUTES(decl) \
2709 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
2710 : DECL_ATTRIBUTES (decl) \
2711 ? (DECL_ATTRIBUTES (decl)) \
2712 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
2714 /* Returns TRUE if the given tree has the "interrupt" attribute. */
2716 interrupt_p (tree node ATTRIBUTE_UNUSED)
2718 tree list = M32C_ATTRIBUTES (node);
2721 if (is_attribute_p ("interrupt", TREE_PURPOSE (list)))
2723 list = TREE_CHAIN (list);
2729 interrupt_handler (tree * node ATTRIBUTE_UNUSED,
2730 tree name ATTRIBUTE_UNUSED,
2731 tree args ATTRIBUTE_UNUSED,
2732 int flags ATTRIBUTE_UNUSED,
2733 bool * no_add_attrs ATTRIBUTE_UNUSED)
2738 /* Returns TRUE if given tree has the "function_vector" attribute. */
2740 m32c_special_page_vector_p (tree func)
2742 if (TREE_CODE (func) != FUNCTION_DECL)
2745 tree list = M32C_ATTRIBUTES (func);
2748 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
2750 list = TREE_CHAIN (list);
2756 function_vector_handler (tree * node ATTRIBUTE_UNUSED,
2757 tree name ATTRIBUTE_UNUSED,
2758 tree args ATTRIBUTE_UNUSED,
2759 int flags ATTRIBUTE_UNUSED,
2760 bool * no_add_attrs ATTRIBUTE_UNUSED)
2764 /* The attribute is not supported for R8C target. */
2765 warning (OPT_Wattributes,
2766 "`%s' attribute is not supported for R8C target",
2767 IDENTIFIER_POINTER (name));
2768 *no_add_attrs = true;
2770 else if (TREE_CODE (*node) != FUNCTION_DECL)
2772 /* The attribute must be applied to functions only. */
2773 warning (OPT_Wattributes,
2774 "`%s' attribute applies only to functions",
2775 IDENTIFIER_POINTER (name));
2776 *no_add_attrs = true;
2778 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
2780 /* The argument must be a constant integer. */
2781 warning (OPT_Wattributes,
2782 "`%s' attribute argument not an integer constant",
2783 IDENTIFIER_POINTER (name));
2784 *no_add_attrs = true;
2786 else if (TREE_INT_CST_LOW (TREE_VALUE (args)) < 18
2787 || TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
2789 /* The argument value must be between 18 to 255. */
2790 warning (OPT_Wattributes,
2791 "`%s' attribute argument should be between 18 to 255",
2792 IDENTIFIER_POINTER (name));
2793 *no_add_attrs = true;
2798 /* If the function is assigned the attribute 'function_vector', it
2799 returns the function vector number, otherwise returns zero. */
2801 current_function_special_page_vector (rtx x)
2805 if ((GET_CODE(x) == SYMBOL_REF)
2806 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
2808 tree t = SYMBOL_REF_DECL (x);
2810 if (TREE_CODE (t) != FUNCTION_DECL)
2813 tree list = M32C_ATTRIBUTES (t);
2816 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
2818 num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
2822 list = TREE_CHAIN (list);
2831 #undef TARGET_ATTRIBUTE_TABLE
2832 #define TARGET_ATTRIBUTE_TABLE m32c_attribute_table
2833 static const struct attribute_spec m32c_attribute_table[] = {
2834 {"interrupt", 0, 0, false, false, false, interrupt_handler},
2835 {"function_vector", 1, 1, true, false, false, function_vector_handler},
2836 {0, 0, 0, 0, 0, 0, 0}
2839 #undef TARGET_COMP_TYPE_ATTRIBUTES
2840 #define TARGET_COMP_TYPE_ATTRIBUTES m32c_comp_type_attributes
2842 m32c_comp_type_attributes (const_tree type1 ATTRIBUTE_UNUSED,
2843 const_tree type2 ATTRIBUTE_UNUSED)
2845 /* 0=incompatible 1=compatible 2=warning */
2849 #undef TARGET_INSERT_ATTRIBUTES
2850 #define TARGET_INSERT_ATTRIBUTES m32c_insert_attributes
2852 m32c_insert_attributes (tree node ATTRIBUTE_UNUSED,
2853 tree * attr_ptr ATTRIBUTE_UNUSED)
2855 /* Nothing to do here. */
2860 /* This is a list of legal subregs of hard regs. */
2861 static const struct {
2862 unsigned char outer_mode_size;
2863 unsigned char inner_mode_size;
2864 unsigned char byte_mask;
2865 unsigned char legal_when;
2867 } legal_subregs[] = {
2868 {1, 2, 0x03, 1, R0_REGNO}, /* r0h r0l */
2869 {1, 2, 0x03, 1, R1_REGNO}, /* r1h r1l */
2870 {1, 2, 0x01, 1, A0_REGNO},
2871 {1, 2, 0x01, 1, A1_REGNO},
2873 {1, 4, 0x01, 1, A0_REGNO},
2874 {1, 4, 0x01, 1, A1_REGNO},
2876 {2, 4, 0x05, 1, R0_REGNO}, /* r2 r0 */
2877 {2, 4, 0x05, 1, R1_REGNO}, /* r3 r1 */
2878 {2, 4, 0x05, 16, A0_REGNO}, /* a1 a0 */
2879 {2, 4, 0x01, 24, A0_REGNO}, /* a1 a0 */
2880 {2, 4, 0x01, 24, A1_REGNO}, /* a1 a0 */
2882 {4, 8, 0x55, 1, R0_REGNO}, /* r3 r1 r2 r0 */
2885 /* Returns TRUE if OP is a subreg of a hard reg which we don't
2888 m32c_illegal_subreg_p (rtx op)
2892 int src_mode, dest_mode;
2894 if (GET_CODE (op) != SUBREG)
2897 dest_mode = GET_MODE (op);
2898 offset = SUBREG_BYTE (op);
2899 op = SUBREG_REG (op);
2900 src_mode = GET_MODE (op);
2902 if (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (src_mode))
2904 if (GET_CODE (op) != REG)
2906 if (REGNO (op) >= MEM0_REGNO)
2909 offset = (1 << offset);
2911 for (i = 0; i < ARRAY_SIZE (legal_subregs); i ++)
2912 if (legal_subregs[i].outer_mode_size == GET_MODE_SIZE (dest_mode)
2913 && legal_subregs[i].regno == REGNO (op)
2914 && legal_subregs[i].inner_mode_size == GET_MODE_SIZE (src_mode)
2915 && legal_subregs[i].byte_mask & offset)
2917 switch (legal_subregs[i].legal_when)
2934 /* Returns TRUE if we support a move between the first two operands.
2935 At the moment, we just want to discourage mem to mem moves until
2936 after reload, because reload has a hard time with our limited
2937 number of address registers, and we can get into a situation where
2938 we need three of them when we only have two. */
2940 m32c_mov_ok (rtx * operands, enum machine_mode mode ATTRIBUTE_UNUSED)
2942 rtx op0 = operands[0];
2943 rtx op1 = operands[1];
2948 #define DEBUG_MOV_OK 0
2950 fprintf (stderr, "m32c_mov_ok %s\n", mode_name[mode]);
2955 if (GET_CODE (op0) == SUBREG)
2956 op0 = XEXP (op0, 0);
2957 if (GET_CODE (op1) == SUBREG)
2958 op1 = XEXP (op1, 0);
2960 if (GET_CODE (op0) == MEM
2961 && GET_CODE (op1) == MEM
2962 && ! reload_completed)
2965 fprintf (stderr, " - no, mem to mem\n");
2971 fprintf (stderr, " - ok\n");
2976 /* Returns TRUE if two consecutive HImode mov instructions, generated
2977 for moving an immediate double data to a double data type variable
2978 location, can be combined into single SImode mov instruction. */
2980 m32c_immd_dbl_mov (rtx * operands,
2981 enum machine_mode mode ATTRIBUTE_UNUSED)
2983 int flag = 0, okflag = 0, offset1 = 0, offset2 = 0, offsetsign = 0;
2987 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
2988 && MEM_SCALAR_P (operands[0])
2989 && !MEM_IN_STRUCT_P (operands[0])
2990 && GET_CODE (XEXP (operands[2], 0)) == CONST
2991 && GET_CODE (XEXP (XEXP (operands[2], 0), 0)) == PLUS
2992 && GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 0)) == SYMBOL_REF
2993 && GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 1)) == CONST_INT
2994 && MEM_SCALAR_P (operands[2])
2995 && !MEM_IN_STRUCT_P (operands[2]))
2998 else if (GET_CODE (XEXP (operands[0], 0)) == CONST
2999 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == PLUS
3000 && GET_CODE (XEXP (XEXP (XEXP (operands[0], 0), 0), 0)) == SYMBOL_REF
3001 && MEM_SCALAR_P (operands[0])
3002 && !MEM_IN_STRUCT_P (operands[0])
3003 && !(INTVAL (XEXP (XEXP (XEXP (operands[0], 0), 0), 1)) %4)
3004 && GET_CODE (XEXP (operands[2], 0)) == CONST
3005 && GET_CODE (XEXP (XEXP (operands[2], 0), 0)) == PLUS
3006 && GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 0)) == SYMBOL_REF
3007 && MEM_SCALAR_P (operands[2])
3008 && !MEM_IN_STRUCT_P (operands[2]))
3011 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
3012 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
3013 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == FB_REGNO
3014 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT
3015 && MEM_SCALAR_P (operands[0])
3016 && !MEM_IN_STRUCT_P (operands[0])
3017 && !(INTVAL (XEXP (XEXP (operands[0], 0), 1)) %4)
3018 && REGNO (XEXP (XEXP (operands[2], 0), 0)) == FB_REGNO
3019 && GET_CODE (XEXP (XEXP (operands[2], 0), 1)) == CONST_INT
3020 && MEM_SCALAR_P (operands[2])
3021 && !MEM_IN_STRUCT_P (operands[2]))
3030 str1 = XSTR (XEXP (operands[0], 0), 0);
3031 str2 = XSTR (XEXP (XEXP (XEXP (operands[2], 0), 0), 0), 0);
3032 if (strcmp (str1, str2) == 0)
3038 str1 = XSTR (XEXP (XEXP (XEXP (operands[0], 0), 0), 0), 0);
3039 str2 = XSTR (XEXP (XEXP (XEXP (operands[2], 0), 0), 0), 0);
3040 if (strcmp(str1,str2) == 0)
3046 offset1 = INTVAL (XEXP (XEXP (operands[0], 0), 1));
3047 offset2 = INTVAL (XEXP (XEXP (operands[2], 0), 1));
3048 offsetsign = offset1 >> ((sizeof (offset1) * 8) -1);
3049 if (((offset2-offset1) == 2) && offsetsign != 0)
3061 operands[4] = gen_rtx_MEM (SImode, XEXP (operands[0], 0));
3063 val = (INTVAL (operands[3]) << 16) + (INTVAL (operands[1]) & 0xFFFF);
3064 operands[5] = gen_rtx_CONST_INT (VOIDmode, val);
3074 /* Subregs are non-orthogonal for us, because our registers are all
3077 m32c_subreg (enum machine_mode outer,
3078 rtx x, enum machine_mode inner, int byte)
3082 /* Converting MEMs to different types that are the same size, we
3083 just rewrite them. */
3084 if (GET_CODE (x) == SUBREG
3085 && SUBREG_BYTE (x) == 0
3086 && GET_CODE (SUBREG_REG (x)) == MEM
3087 && (GET_MODE_SIZE (GET_MODE (x))
3088 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3091 x = gen_rtx_MEM (GET_MODE (x), XEXP (SUBREG_REG (x), 0));
3092 MEM_COPY_ATTRIBUTES (x, SUBREG_REG (oldx));
3095 /* Push/pop get done as smaller push/pops. */
3096 if (GET_CODE (x) == MEM
3097 && (GET_CODE (XEXP (x, 0)) == PRE_DEC
3098 || GET_CODE (XEXP (x, 0)) == POST_INC))
3099 return gen_rtx_MEM (outer, XEXP (x, 0));
3100 if (GET_CODE (x) == SUBREG
3101 && GET_CODE (XEXP (x, 0)) == MEM
3102 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == PRE_DEC
3103 || GET_CODE (XEXP (XEXP (x, 0), 0)) == POST_INC))
3104 return gen_rtx_MEM (outer, XEXP (XEXP (x, 0), 0));
3106 if (GET_CODE (x) != REG)
3107 return simplify_gen_subreg (outer, x, inner, byte);
3110 if (r >= FIRST_PSEUDO_REGISTER || r == AP_REGNO)
3111 return simplify_gen_subreg (outer, x, inner, byte);
3113 if (IS_MEM_REGNO (r))
3114 return simplify_gen_subreg (outer, x, inner, byte);
3116 /* This is where the complexities of our register layout are
3120 else if (outer == HImode)
3122 if (r == R0_REGNO && byte == 2)
3124 else if (r == R0_REGNO && byte == 4)
3126 else if (r == R0_REGNO && byte == 6)
3128 else if (r == R1_REGNO && byte == 2)
3130 else if (r == A0_REGNO && byte == 2)
3133 else if (outer == SImode)
3135 if (r == R0_REGNO && byte == 0)
3137 else if (r == R0_REGNO && byte == 4)
3142 fprintf (stderr, "m32c_subreg %s %s %d\n",
3143 mode_name[outer], mode_name[inner], byte);
3147 return gen_rtx_REG (outer, nr);
3150 /* Used to emit move instructions. We split some moves,
3151 and avoid mem-mem moves. */
3153 m32c_prepare_move (rtx * operands, enum machine_mode mode)
3155 if (TARGET_A16 && mode == PSImode)
3156 return m32c_split_move (operands, mode, 1);
3157 if ((GET_CODE (operands[0]) == MEM)
3158 && (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY))
3160 rtx pmv = XEXP (operands[0], 0);
3161 rtx dest_reg = XEXP (pmv, 0);
3162 rtx dest_mod = XEXP (pmv, 1);
3164 emit_insn (gen_rtx_SET (Pmode, dest_reg, dest_mod));
3165 operands[0] = gen_rtx_MEM (mode, dest_reg);
3167 if (can_create_pseudo_p () && MEM_P (operands[0]) && MEM_P (operands[1]))
3168 operands[1] = copy_to_mode_reg (mode, operands[1]);
3172 #define DEBUG_SPLIT 0
3174 /* Returns TRUE if the given PSImode move should be split. We split
3175 for all r8c/m16c moves, since it doesn't support them, and for
3176 POP.L as we can only *push* SImode. */
3178 m32c_split_psi_p (rtx * operands)
3181 fprintf (stderr, "\nm32c_split_psi_p\n");
3182 debug_rtx (operands[0]);
3183 debug_rtx (operands[1]);
3188 fprintf (stderr, "yes, A16\n");
3192 if (GET_CODE (operands[1]) == MEM
3193 && GET_CODE (XEXP (operands[1], 0)) == POST_INC)
3196 fprintf (stderr, "yes, pop.l\n");
3201 fprintf (stderr, "no, default\n");
3206 /* Split the given move. SPLIT_ALL is 0 if splitting is optional
3207 (define_expand), 1 if it is not optional (define_insn_and_split),
3208 and 3 for define_split (alternate api). */
3210 m32c_split_move (rtx * operands, enum machine_mode mode, int split_all)
3213 int parts, si, di, rev = 0;
3214 int rv = 0, opi = 2;
3215 enum machine_mode submode = HImode;
3216 rtx *ops, local_ops[10];
3218 /* define_split modifies the existing operands, but the other two
3219 emit new insns. OPS is where we store the operand pairs, which
3230 /* Before splitting mem-mem moves, force one operand into a
3232 if (can_create_pseudo_p () && MEM_P (operands[0]) && MEM_P (operands[1]))
3235 fprintf (stderr, "force_reg...\n");
3236 debug_rtx (operands[1]);
3238 operands[1] = force_reg (mode, operands[1]);
3240 debug_rtx (operands[1]);
3247 fprintf (stderr, "\nsplit_move %d all=%d\n", !can_create_pseudo_p (),
3249 debug_rtx (operands[0]);
3250 debug_rtx (operands[1]);
3253 /* Note that split_all is not used to select the api after this
3254 point, so it's safe to set it to 3 even with define_insn. */
3255 /* None of the chips can move SI operands to sp-relative addresses,
3256 so we always split those. */
3257 if (m32c_extra_constraint_p (operands[0], 'S', "Ss"))
3260 /* We don't need to split these. */
3263 && (mode == SImode || mode == PSImode)
3264 && !(GET_CODE (operands[1]) == MEM
3265 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
3268 /* First, enumerate the subregs we'll be dealing with. */
3269 for (si = 0; si < parts; si++)
3272 m32c_subreg (submode, operands[0], mode,
3273 si * GET_MODE_SIZE (submode));
3275 m32c_subreg (submode, operands[1], mode,
3276 si * GET_MODE_SIZE (submode));
3279 /* Split pushes by emitting a sequence of smaller pushes. */
3280 if (GET_CODE (d[0]) == MEM && GET_CODE (XEXP (d[0], 0)) == PRE_DEC)
3282 for (si = parts - 1; si >= 0; si--)
3284 ops[opi++] = gen_rtx_MEM (submode,
3285 gen_rtx_PRE_DEC (Pmode,
3293 /* Likewise for pops. */
3294 else if (GET_CODE (s[0]) == MEM && GET_CODE (XEXP (s[0], 0)) == POST_INC)
3296 for (di = 0; di < parts; di++)
3299 ops[opi++] = gen_rtx_MEM (submode,
3300 gen_rtx_POST_INC (Pmode,
3308 /* if d[di] == s[si] for any di < si, we'll early clobber. */
3309 for (di = 0; di < parts - 1; di++)
3310 for (si = di + 1; si < parts; si++)
3311 if (reg_mentioned_p (d[di], s[si]))
3315 for (si = 0; si < parts; si++)
3321 for (si = parts - 1; si >= 0; si--)
3328 /* Now emit any moves we may have accumulated. */
3329 if (rv && split_all != 3)
3332 for (i = 2; i < opi; i += 2)
3333 emit_move_insn (ops[i], ops[i + 1]);
3338 /* The m32c has a number of opcodes that act like memcpy, strcmp, and
3339 the like. For the R8C they expect one of the addresses to be in
3340 R1L:An so we need to arrange for that. Otherwise, it's just a
3341 matter of picking out the operands we want and emitting the right
3342 pattern for them. All these expanders, which correspond to
3343 patterns in blkmov.md, must return nonzero if they expand the insn,
3344 or zero if they should FAIL. */
3346 /* This is a memset() opcode. All operands are implied, so we need to
3347 arrange for them to be in the right registers. The opcode wants
3348 addresses, not [mem] syntax. $0 is the destination (MEM:BLK), $1
3349 the count (HI), and $2 the value (QI). */
3351 m32c_expand_setmemhi(rtx *operands)
3353 rtx desta, count, val;
3356 desta = XEXP (operands[0], 0);
3357 count = operands[1];
3360 desto = gen_reg_rtx (Pmode);
3361 counto = gen_reg_rtx (HImode);
3363 if (GET_CODE (desta) != REG
3364 || REGNO (desta) < FIRST_PSEUDO_REGISTER)
3365 desta = copy_to_mode_reg (Pmode, desta);
3367 /* This looks like an arbitrary restriction, but this is by far the
3368 most common case. For counts 8..14 this actually results in
3369 smaller code with no speed penalty because the half-sized
3370 constant can be loaded with a shorter opcode. */
3371 if (GET_CODE (count) == CONST_INT
3372 && GET_CODE (val) == CONST_INT
3373 && ! (INTVAL (count) & 1)
3374 && (INTVAL (count) > 1)
3375 && (INTVAL (val) <= 7 && INTVAL (val) >= -8))
3377 unsigned v = INTVAL (val) & 0xff;
3379 count = copy_to_mode_reg (HImode, GEN_INT (INTVAL (count) / 2));
3380 val = copy_to_mode_reg (HImode, GEN_INT (v));
3382 emit_insn (gen_setmemhi_whi_op (desto, counto, val, desta, count));
3384 emit_insn (gen_setmemhi_wpsi_op (desto, counto, val, desta, count));
3388 /* This is the generalized memset() case. */
3389 if (GET_CODE (val) != REG
3390 || REGNO (val) < FIRST_PSEUDO_REGISTER)
3391 val = copy_to_mode_reg (QImode, val);
3393 if (GET_CODE (count) != REG
3394 || REGNO (count) < FIRST_PSEUDO_REGISTER)
3395 count = copy_to_mode_reg (HImode, count);
3398 emit_insn (gen_setmemhi_bhi_op (desto, counto, val, desta, count));
3400 emit_insn (gen_setmemhi_bpsi_op (desto, counto, val, desta, count));
3405 /* This is a memcpy() opcode. All operands are implied, so we need to
3406 arrange for them to be in the right registers. The opcode wants
3407 addresses, not [mem] syntax. $0 is the destination (MEM:BLK), $1
3408 is the source (MEM:BLK), and $2 the count (HI). */
3410 m32c_expand_movmemhi(rtx *operands)
3412 rtx desta, srca, count;
3413 rtx desto, srco, counto;
3415 desta = XEXP (operands[0], 0);
3416 srca = XEXP (operands[1], 0);
3417 count = operands[2];
3419 desto = gen_reg_rtx (Pmode);
3420 srco = gen_reg_rtx (Pmode);
3421 counto = gen_reg_rtx (HImode);
3423 if (GET_CODE (desta) != REG
3424 || REGNO (desta) < FIRST_PSEUDO_REGISTER)
3425 desta = copy_to_mode_reg (Pmode, desta);
3427 if (GET_CODE (srca) != REG
3428 || REGNO (srca) < FIRST_PSEUDO_REGISTER)
3429 srca = copy_to_mode_reg (Pmode, srca);
3431 /* Similar to setmem, but we don't need to check the value. */
3432 if (GET_CODE (count) == CONST_INT
3433 && ! (INTVAL (count) & 1)
3434 && (INTVAL (count) > 1))
3436 count = copy_to_mode_reg (HImode, GEN_INT (INTVAL (count) / 2));
3438 emit_insn (gen_movmemhi_whi_op (desto, srco, counto, desta, srca, count));
3440 emit_insn (gen_movmemhi_wpsi_op (desto, srco, counto, desta, srca, count));
3444 /* This is the generalized memset() case. */
3445 if (GET_CODE (count) != REG
3446 || REGNO (count) < FIRST_PSEUDO_REGISTER)
3447 count = copy_to_mode_reg (HImode, count);
3450 emit_insn (gen_movmemhi_bhi_op (desto, srco, counto, desta, srca, count));
3452 emit_insn (gen_movmemhi_bpsi_op (desto, srco, counto, desta, srca, count));
3457 /* This is a stpcpy() opcode. $0 is the destination (MEM:BLK) after
3458 the copy, which should point to the NUL at the end of the string,
3459 $1 is the destination (MEM:BLK), and $2 is the source (MEM:BLK).
3460 Since our opcode leaves the destination pointing *after* the NUL,
3461 we must emit an adjustment. */
3463 m32c_expand_movstr(rtx *operands)
3468 desta = XEXP (operands[1], 0);
3469 srca = XEXP (operands[2], 0);
3471 desto = gen_reg_rtx (Pmode);
3472 srco = gen_reg_rtx (Pmode);
3474 if (GET_CODE (desta) != REG
3475 || REGNO (desta) < FIRST_PSEUDO_REGISTER)
3476 desta = copy_to_mode_reg (Pmode, desta);
3478 if (GET_CODE (srca) != REG
3479 || REGNO (srca) < FIRST_PSEUDO_REGISTER)
3480 srca = copy_to_mode_reg (Pmode, srca);
3482 emit_insn (gen_movstr_op (desto, srco, desta, srca));
3483 /* desto ends up being a1, which allows this type of add through MOVA. */
3484 emit_insn (gen_addpsi3 (operands[0], desto, GEN_INT (-1)));
3489 /* This is a strcmp() opcode. $0 is the destination (HI) which holds
3490 <=>0 depending on the comparison, $1 is one string (MEM:BLK), and
3491 $2 is the other (MEM:BLK). We must do the comparison, and then
3492 convert the flags to a signed integer result. */
3494 m32c_expand_cmpstr(rtx *operands)
3498 src1a = XEXP (operands[1], 0);
3499 src2a = XEXP (operands[2], 0);
3501 if (GET_CODE (src1a) != REG
3502 || REGNO (src1a) < FIRST_PSEUDO_REGISTER)
3503 src1a = copy_to_mode_reg (Pmode, src1a);
3505 if (GET_CODE (src2a) != REG
3506 || REGNO (src2a) < FIRST_PSEUDO_REGISTER)
3507 src2a = copy_to_mode_reg (Pmode, src2a);
3509 emit_insn (gen_cmpstrhi_op (src1a, src2a, src1a, src2a));
3510 emit_insn (gen_cond_to_int (operands[0]));
3516 typedef rtx (*shift_gen_func)(rtx, rtx, rtx);
3518 static shift_gen_func
3519 shift_gen_func_for (int mode, int code)
3521 #define GFF(m,c,f) if (mode == m && code == c) return f
3522 GFF(QImode, ASHIFT, gen_ashlqi3_i);
3523 GFF(QImode, ASHIFTRT, gen_ashrqi3_i);
3524 GFF(QImode, LSHIFTRT, gen_lshrqi3_i);
3525 GFF(HImode, ASHIFT, gen_ashlhi3_i);
3526 GFF(HImode, ASHIFTRT, gen_ashrhi3_i);
3527 GFF(HImode, LSHIFTRT, gen_lshrhi3_i);
3528 GFF(PSImode, ASHIFT, gen_ashlpsi3_i);
3529 GFF(PSImode, ASHIFTRT, gen_ashrpsi3_i);
3530 GFF(PSImode, LSHIFTRT, gen_lshrpsi3_i);
3531 GFF(SImode, ASHIFT, TARGET_A16 ? gen_ashlsi3_16 : gen_ashlsi3_24);
3532 GFF(SImode, ASHIFTRT, TARGET_A16 ? gen_ashrsi3_16 : gen_ashrsi3_24);
3533 GFF(SImode, LSHIFTRT, TARGET_A16 ? gen_lshrsi3_16 : gen_lshrsi3_24);
3538 /* The m32c only has one shift, but it takes a signed count. GCC
3539 doesn't want this, so we fake it by negating any shift count when
3540 we're pretending to shift the other way. Also, the shift count is
3541 limited to -8..8. It's slightly better to use two shifts for 9..15
3542 than to load the count into r1h, so we do that too. */
3544 m32c_prepare_shift (rtx * operands, int scale, int shift_code)
3546 enum machine_mode mode = GET_MODE (operands[0]);
3547 shift_gen_func func = shift_gen_func_for (mode, shift_code);
3550 if (GET_CODE (operands[2]) == CONST_INT)
3552 int maxc = TARGET_A24 && (mode == PSImode || mode == SImode) ? 32 : 8;
3553 int count = INTVAL (operands[2]) * scale;
3555 while (count > maxc)
3557 temp = gen_reg_rtx (mode);
3558 emit_insn (func (temp, operands[1], GEN_INT (maxc)));
3562 while (count < -maxc)
3564 temp = gen_reg_rtx (mode);
3565 emit_insn (func (temp, operands[1], GEN_INT (-maxc)));
3569 emit_insn (func (operands[0], operands[1], GEN_INT (count)));
3573 temp = gen_reg_rtx (QImode);
3575 /* The pattern has a NEG that corresponds to this. */
3576 emit_move_insn (temp, gen_rtx_NEG (QImode, operands[2]));
3577 else if (TARGET_A16 && mode == SImode)
3578 /* We do this because the code below may modify this, we don't
3579 want to modify the origin of this value. */
3580 emit_move_insn (temp, operands[2]);
3582 /* We'll only use it for the shift, no point emitting a move. */
3585 if (TARGET_A16 && GET_MODE_SIZE (mode) == 4)
3587 /* The m16c has a limit of -16..16 for SI shifts, even when the
3588 shift count is in a register. Since there are so many targets
3589 of these shifts, it's better to expand the RTL here than to
3590 call a helper function.
3592 The resulting code looks something like this:
3604 We take advantage of the fact that "negative" shifts are
3605 undefined to skip one of the comparisons. */
3608 rtx label, lref, insn, tempvar;
3610 emit_move_insn (operands[0], operands[1]);
3613 label = gen_label_rtx ();
3614 lref = gen_rtx_LABEL_REF (VOIDmode, label);
3615 LABEL_NUSES (label) ++;
3617 tempvar = gen_reg_rtx (mode);
3619 if (shift_code == ASHIFT)
3621 /* This is a left shift. We only need check positive counts. */
3622 emit_jump_insn (gen_cbranchqi4 (gen_rtx_LE (VOIDmode, 0, 0),
3623 count, GEN_INT (16), label));
3624 emit_insn (func (tempvar, operands[0], GEN_INT (8)));
3625 emit_insn (func (operands[0], tempvar, GEN_INT (8)));
3626 insn = emit_insn (gen_addqi3 (count, count, GEN_INT (-16)));
3627 emit_label_after (label, insn);
3631 /* This is a right shift. We only need check negative counts. */
3632 emit_jump_insn (gen_cbranchqi4 (gen_rtx_GE (VOIDmode, 0, 0),
3633 count, GEN_INT (-16), label));
3634 emit_insn (func (tempvar, operands[0], GEN_INT (-8)));
3635 emit_insn (func (operands[0], tempvar, GEN_INT (-8)));
3636 insn = emit_insn (gen_addqi3 (count, count, GEN_INT (16)));
3637 emit_label_after (label, insn);
3639 operands[1] = operands[0];
3640 emit_insn (func (operands[0], operands[0], count));
3648 /* The m32c has a limited range of operations that work on PSImode
3649 values; we have to expand to SI, do the math, and truncate back to
3650 PSI. Yes, this is expensive, but hopefully gcc will learn to avoid
3653 m32c_expand_neg_mulpsi3 (rtx * operands)
3655 /* operands: a = b * i */
3656 rtx temp1; /* b as SI */
3657 rtx scale /* i as SI */;
3658 rtx temp2; /* a*b as SI */
3660 temp1 = gen_reg_rtx (SImode);
3661 temp2 = gen_reg_rtx (SImode);
3662 if (GET_CODE (operands[2]) != CONST_INT)
3664 scale = gen_reg_rtx (SImode);
3665 emit_insn (gen_zero_extendpsisi2 (scale, operands[2]));
3668 scale = copy_to_mode_reg (SImode, operands[2]);
3670 emit_insn (gen_zero_extendpsisi2 (temp1, operands[1]));
3671 temp2 = expand_simple_binop (SImode, MULT, temp1, scale, temp2, 1, OPTAB_LIB);
3672 emit_insn (gen_truncsipsi2 (operands[0], temp2));
3675 static rtx compare_op0, compare_op1;
3678 m32c_pend_compare (rtx *operands)
3680 compare_op0 = operands[0];
3681 compare_op1 = operands[1];
3685 m32c_unpend_compare (void)
3687 switch (GET_MODE (compare_op0))
3690 emit_insn (gen_cmpqi_op (compare_op0, compare_op1));
3692 emit_insn (gen_cmphi_op (compare_op0, compare_op1));
3694 emit_insn (gen_cmppsi_op (compare_op0, compare_op1));
3696 /* Just to silence the "missing case" warnings. */ ;
3701 m32c_expand_scc (int code, rtx *operands)
3703 enum machine_mode mode = TARGET_A16 ? QImode : HImode;
3705 emit_insn (gen_rtx_SET (mode,
3707 gen_rtx_fmt_ee (code,
3713 /* Pattern Output Functions */
3715 /* Returns a (OP (reg:CC FLG_REGNO) (const_int 0)) from some other
3716 match_operand rtx's OP. */
3718 m32c_cmp_flg_0 (rtx cmp)
3720 return gen_rtx_fmt_ee (GET_CODE (cmp),
3722 gen_rtx_REG (CCmode, FLG_REGNO),
3727 m32c_expand_movcc (rtx *operands)
3729 rtx rel = operands[1];
3732 if (GET_CODE (rel) != EQ && GET_CODE (rel) != NE)
3734 if (GET_CODE (operands[2]) != CONST_INT
3735 || GET_CODE (operands[3]) != CONST_INT)
3737 emit_insn (gen_cmpqi(XEXP (rel, 0), XEXP (rel, 1)));
3738 if (GET_CODE (rel) == NE)
3740 rtx tmp = operands[2];
3741 operands[2] = operands[3];
3745 cmp = gen_rtx_fmt_ee (GET_CODE (rel),
3750 emit_move_insn (operands[0],
3751 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
3758 /* Used for the "insv" pattern. Return nonzero to fail, else done. */
3760 m32c_expand_insv (rtx *operands)
3765 if (INTVAL (operands[1]) != 1)
3768 /* Our insv opcode (bset, bclr) can only insert a one-bit constant. */
3769 if (GET_CODE (operands[3]) != CONST_INT)
3771 if (INTVAL (operands[3]) != 0
3772 && INTVAL (operands[3]) != 1
3773 && INTVAL (operands[3]) != -1)
3776 mask = 1 << INTVAL (operands[2]);
3779 if (GET_CODE (op0) == SUBREG
3780 && SUBREG_BYTE (op0) == 0)
3782 rtx sub = SUBREG_REG (op0);
3783 if (GET_MODE (sub) == HImode || GET_MODE (sub) == QImode)
3787 if (!can_create_pseudo_p ()
3788 || (GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0)))
3792 src0 = gen_reg_rtx (GET_MODE (op0));
3793 emit_move_insn (src0, op0);
3796 if (GET_MODE (op0) == HImode
3797 && INTVAL (operands[2]) >= 8
3798 && GET_MODE (op0) == MEM)
3800 /* We are little endian. */
3801 rtx new_mem = gen_rtx_MEM (QImode, plus_constant (XEXP (op0, 0), 1));
3802 MEM_COPY_ATTRIBUTES (new_mem, op0);
3806 /* First, we generate a mask with the correct polarity. If we are
3807 storing a zero, we want an AND mask, so invert it. */
3808 if (INTVAL (operands[3]) == 0)
3810 /* Storing a zero, use an AND mask */
3811 if (GET_MODE (op0) == HImode)
3816 /* Now we need to properly sign-extend the mask in case we need to
3817 fall back to an AND or OR opcode. */
3818 if (GET_MODE (op0) == HImode)
3829 switch ( (INTVAL (operands[3]) ? 4 : 0)
3830 + ((GET_MODE (op0) == HImode) ? 2 : 0)
3831 + (TARGET_A24 ? 1 : 0))
3833 case 0: p = gen_andqi3_16 (op0, src0, GEN_INT (mask)); break;
3834 case 1: p = gen_andqi3_24 (op0, src0, GEN_INT (mask)); break;
3835 case 2: p = gen_andhi3_16 (op0, src0, GEN_INT (mask)); break;
3836 case 3: p = gen_andhi3_24 (op0, src0, GEN_INT (mask)); break;
3837 case 4: p = gen_iorqi3_16 (op0, src0, GEN_INT (mask)); break;
3838 case 5: p = gen_iorqi3_24 (op0, src0, GEN_INT (mask)); break;
3839 case 6: p = gen_iorhi3_16 (op0, src0, GEN_INT (mask)); break;
3840 case 7: p = gen_iorhi3_24 (op0, src0, GEN_INT (mask)); break;
3848 m32c_scc_pattern(rtx *operands, RTX_CODE code)
3850 static char buf[30];
3851 if (GET_CODE (operands[0]) == REG
3852 && REGNO (operands[0]) == R0_REGNO)
3855 return "stzx\t#1,#0,r0l";
3857 return "stzx\t#0,#1,r0l";
3859 sprintf(buf, "bm%s\t0,%%h0\n\tand.b\t#1,%%0", GET_RTX_NAME (code));
3863 /* Encode symbol attributes of a SYMBOL_REF into its
3864 SYMBOL_REF_FLAGS. */
3866 m32c_encode_section_info (tree decl, rtx rtl, int first)
3868 int extra_flags = 0;
3870 default_encode_section_info (decl, rtl, first);
3871 if (TREE_CODE (decl) == FUNCTION_DECL
3872 && m32c_special_page_vector_p (decl))
3874 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
3877 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
3880 /* Returns TRUE if the current function is a leaf, and thus we can
3881 determine which registers an interrupt function really needs to
3882 save. The logic below is mostly about finding the insn sequence
3883 that's the function, versus any sequence that might be open for the
3886 m32c_leaf_function_p (void)
3888 rtx saved_first, saved_last;
3889 struct sequence_stack *seq;
3892 saved_first = crtl->emit.x_first_insn;
3893 saved_last = crtl->emit.x_last_insn;
3894 for (seq = crtl->emit.sequence_stack; seq && seq->next; seq = seq->next)
3898 crtl->emit.x_first_insn = seq->first;
3899 crtl->emit.x_last_insn = seq->last;
3902 rv = leaf_function_p ();
3904 crtl->emit.x_first_insn = saved_first;
3905 crtl->emit.x_last_insn = saved_last;
3909 /* Returns TRUE if the current function needs to use the ENTER/EXIT
3910 opcodes. If the function doesn't need the frame base or stack
3911 pointer, it can use the simpler RTS opcode. */
3913 m32c_function_needs_enter (void)
3916 struct sequence_stack *seq;
3917 rtx sp = gen_rtx_REG (Pmode, SP_REGNO);
3918 rtx fb = gen_rtx_REG (Pmode, FB_REGNO);
3920 insn = get_insns ();
3921 for (seq = crtl->emit.sequence_stack;
3923 insn = seq->first, seq = seq->next);
3927 if (reg_mentioned_p (sp, insn))
3929 if (reg_mentioned_p (fb, insn))
3931 insn = NEXT_INSN (insn);
3936 /* Mark all the subexpressions of the PARALLEL rtx PAR as
3937 frame-related. Return PAR.
3939 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
3940 PARALLEL rtx other than the first if they do not have the
3941 FRAME_RELATED flag set on them. So this function is handy for
3942 marking up 'enter' instructions. */
3944 m32c_all_frame_related (rtx par)
3946 int len = XVECLEN (par, 0);
3949 for (i = 0; i < len; i++)
3950 F (XVECEXP (par, 0, i));
3955 /* Emits the prologue. See the frame layout comment earlier in this
3956 file. We can reserve up to 256 bytes with the ENTER opcode, beyond
3957 that we manually update sp. */
3959 m32c_emit_prologue (void)
3961 int frame_size, extra_frame_size = 0, reg_save_size;
3962 int complex_prologue = 0;
3964 cfun->machine->is_leaf = m32c_leaf_function_p ();
3965 if (interrupt_p (cfun->decl))
3967 cfun->machine->is_interrupt = 1;
3968 complex_prologue = 1;
3971 reg_save_size = m32c_pushm_popm (PP_justcount);
3973 if (interrupt_p (cfun->decl))
3974 emit_insn (gen_pushm (GEN_INT (cfun->machine->intr_pushm)));
3977 m32c_initial_elimination_offset (FB_REGNO, SP_REGNO) - reg_save_size;
3979 && !cfun->machine->is_interrupt
3980 && !m32c_function_needs_enter ())
3981 cfun->machine->use_rts = 1;
3983 if (frame_size > 254)
3985 extra_frame_size = frame_size - 254;
3988 if (cfun->machine->use_rts == 0)
3989 F (emit_insn (m32c_all_frame_related
3991 ? gen_prologue_enter_16 (GEN_INT (frame_size + 2))
3992 : gen_prologue_enter_24 (GEN_INT (frame_size + 4)))));
3994 if (extra_frame_size)
3996 complex_prologue = 1;
3998 F (emit_insn (gen_addhi3 (gen_rtx_REG (HImode, SP_REGNO),
3999 gen_rtx_REG (HImode, SP_REGNO),
4000 GEN_INT (-extra_frame_size))));
4002 F (emit_insn (gen_addpsi3 (gen_rtx_REG (PSImode, SP_REGNO),
4003 gen_rtx_REG (PSImode, SP_REGNO),
4004 GEN_INT (-extra_frame_size))));
4007 complex_prologue += m32c_pushm_popm (PP_pushm);
4009 /* This just emits a comment into the .s file for debugging. */
4010 if (complex_prologue)
4011 emit_insn (gen_prologue_end ());
4014 /* Likewise, for the epilogue. The only exception is that, for
4015 interrupts, we must manually unwind the frame as the REIT opcode
4018 m32c_emit_epilogue (void)
4020 /* This just emits a comment into the .s file for debugging. */
4021 if (m32c_pushm_popm (PP_justcount) > 0 || cfun->machine->is_interrupt)
4022 emit_insn (gen_epilogue_start ());
4024 m32c_pushm_popm (PP_popm);
4026 if (cfun->machine->is_interrupt)
4028 enum machine_mode spmode = TARGET_A16 ? HImode : PSImode;
4030 emit_move_insn (gen_rtx_REG (spmode, A0_REGNO),
4031 gen_rtx_REG (spmode, FP_REGNO));
4032 emit_move_insn (gen_rtx_REG (spmode, SP_REGNO),
4033 gen_rtx_REG (spmode, A0_REGNO));
4035 emit_insn (gen_pophi_16 (gen_rtx_REG (HImode, FP_REGNO)));
4037 emit_insn (gen_poppsi (gen_rtx_REG (PSImode, FP_REGNO)));
4038 emit_insn (gen_popm (GEN_INT (cfun->machine->intr_pushm)));
4040 emit_jump_insn (gen_epilogue_reit_16 ());
4042 emit_jump_insn (gen_epilogue_reit_24 ());
4044 else if (cfun->machine->use_rts)
4045 emit_jump_insn (gen_epilogue_rts ());
4046 else if (TARGET_A16)
4047 emit_jump_insn (gen_epilogue_exitd_16 ());
4049 emit_jump_insn (gen_epilogue_exitd_24 ());
4054 m32c_emit_eh_epilogue (rtx ret_addr)
4056 /* R0[R2] has the stack adjustment. R1[R3] has the address to
4057 return to. We have to fudge the stack, pop everything, pop SP
4058 (fudged), and return (fudged). This is actually easier to do in
4059 assembler, so punt to libgcc. */
4060 emit_jump_insn (gen_eh_epilogue (ret_addr, cfun->machine->eh_stack_adjust));
4061 /* emit_insn (gen_rtx_CLOBBER (HImode, gen_rtx_REG (HImode, R0L_REGNO))); */
4065 /* Indicate which flags must be properly set for a given conditional. */
4067 flags_needed_for_conditional (rtx cond)
4069 switch (GET_CODE (cond))
4093 /* Returns true if a compare insn is redundant because it would only
4094 set flags that are already set correctly. */
4096 m32c_compare_redundant (rtx cmp, rtx *operands)
4111 fprintf(stderr, "\n\033[32mm32c_compare_redundant\033[0m\n");
4115 fprintf(stderr, "operands[%d] = ", i);
4116 debug_rtx(operands[i]);
4120 next = next_nonnote_insn (cmp);
4121 if (!next || !INSN_P (next))
4124 fprintf(stderr, "compare not followed by insn\n");
4129 if (GET_CODE (PATTERN (next)) == SET
4130 && GET_CODE (XEXP ( PATTERN (next), 1)) == IF_THEN_ELSE)
4132 next = XEXP (XEXP (PATTERN (next), 1), 0);
4134 else if (GET_CODE (PATTERN (next)) == SET)
4136 /* If this is a conditional, flags_needed will be something
4137 other than FLAGS_N, which we test below. */
4138 next = XEXP (PATTERN (next), 1);
4143 fprintf(stderr, "compare not followed by conditional\n");
4149 fprintf(stderr, "conditional is: ");
4153 flags_needed = flags_needed_for_conditional (next);
4154 if (flags_needed == FLAGS_N)
4157 fprintf(stderr, "compare not followed by conditional\n");
4163 /* Compare doesn't set overflow and carry the same way that
4164 arithmetic instructions do, so we can't replace those. */
4165 if (flags_needed & FLAGS_OC)
4170 prev = prev_nonnote_insn (prev);
4174 fprintf(stderr, "No previous insn.\n");
4181 fprintf(stderr, "Previous insn is a non-insn.\n");
4185 pp = PATTERN (prev);
4186 if (GET_CODE (pp) != SET)
4189 fprintf(stderr, "Previous insn is not a SET.\n");
4193 pflags = get_attr_flags (prev);
4195 /* Looking up attributes of previous insns corrupted the recog
4197 INSN_UID (cmp) = -1;
4198 recog (PATTERN (cmp), cmp, 0);
4200 if (pflags == FLAGS_N
4201 && reg_mentioned_p (op0, pp))
4204 fprintf(stderr, "intermediate non-flags insn uses op:\n");
4209 } while (pflags == FLAGS_N);
4211 fprintf(stderr, "previous flag-setting insn:\n");
4216 if (GET_CODE (pp) == SET
4217 && GET_CODE (XEXP (pp, 0)) == REG
4218 && REGNO (XEXP (pp, 0)) == FLG_REGNO
4219 && GET_CODE (XEXP (pp, 1)) == COMPARE)
4221 /* Adjacent cbranches must have the same operands to be
4223 rtx pop0 = XEXP (XEXP (pp, 1), 0);
4224 rtx pop1 = XEXP (XEXP (pp, 1), 1);
4226 fprintf(stderr, "adjacent cbranches\n");
4230 if (rtx_equal_p (op0, pop0)
4231 && rtx_equal_p (op1, pop1))
4234 fprintf(stderr, "prev cmp not same\n");
4239 /* Else the previous insn must be a SET, with either the source or
4240 dest equal to operands[0], and operands[1] must be zero. */
4242 if (!rtx_equal_p (op1, const0_rtx))
4245 fprintf(stderr, "operands[1] not const0_rtx\n");
4249 if (GET_CODE (pp) != SET)
4252 fprintf (stderr, "pp not set\n");
4256 if (!rtx_equal_p (op0, SET_SRC (pp))
4257 && !rtx_equal_p (op0, SET_DEST (pp)))
4260 fprintf(stderr, "operands[0] not found in set\n");
4266 fprintf(stderr, "cmp flags %x prev flags %x\n", flags_needed, pflags);
4268 if ((pflags & flags_needed) == flags_needed)
4274 /* Return the pattern for a compare. This will be commented out if
4275 the compare is redundant, else a normal pattern is returned. Thus,
4276 the assembler output says where the compare would have been. */
4278 m32c_output_compare (rtx insn, rtx *operands)
4280 static char template[] = ";cmp.b\t%1,%0";
4283 template[5] = " bwll"[GET_MODE_SIZE(GET_MODE(operands[0]))];
4284 if (m32c_compare_redundant (insn, operands))
4287 fprintf(stderr, "cbranch: cmp not needed\n");
4293 fprintf(stderr, "cbranch: cmp needed: `%s'\n", template);
4295 return template + 1;
4298 #undef TARGET_ENCODE_SECTION_INFO
4299 #define TARGET_ENCODE_SECTION_INFO m32c_encode_section_info
4301 /* The Global `targetm' Variable. */
4303 struct gcc_target targetm = TARGET_INITIALIZER;
4305 #include "gt-m32c.h"