1 /* Target Code for R8C/M16C/M32C
2 Copyright (C) 2005, 2006, 2007
3 Free Software Foundation, Inc.
4 Contributed by Red Hat.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 3, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
47 #include "target-def.h"
49 #include "langhooks.h"
50 #include "tree-gimple.h"
55 /* Used by m32c_pushm_popm. */
63 static tree interrupt_handler (tree *, tree, tree, int, bool *);
64 static tree function_vector_handler (tree *, tree, tree, int, bool *);
65 static int interrupt_p (tree node);
66 static bool m32c_asm_integer (rtx, unsigned int, int);
67 static int m32c_comp_type_attributes (const_tree, const_tree);
68 static bool m32c_fixed_condition_code_regs (unsigned int *, unsigned int *);
69 static struct machine_function *m32c_init_machine_status (void);
70 static void m32c_insert_attributes (tree, tree *);
71 static bool m32c_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
73 static bool m32c_promote_prototypes (const_tree);
74 static int m32c_pushm_popm (Push_Pop_Type);
75 static bool m32c_strict_argument_naming (CUMULATIVE_ARGS *);
76 static rtx m32c_struct_value_rtx (tree, int);
77 static rtx m32c_subreg (enum machine_mode, rtx, enum machine_mode, int);
78 static int need_to_save (int);
79 int current_function_special_page_vector (rtx);
81 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
83 #define streq(a,b) (strcmp ((a), (b)) == 0)
85 /* Internal support routines */
87 /* Debugging statements are tagged with DEBUG0 only so that they can
88 be easily enabled individually, by replacing the '0' with '1' as
94 /* This is needed by some of the commented-out debug statements
96 static char const *class_names[LIM_REG_CLASSES] = REG_CLASS_NAMES;
98 static int class_contents[LIM_REG_CLASSES][1] = REG_CLASS_CONTENTS;
100 /* These are all to support encode_pattern(). */
101 static char pattern[30], *patternp;
102 static GTY(()) rtx patternr[30];
103 #define RTX_IS(x) (streq (pattern, x))
105 /* Some macros to simplify the logic throughout this file. */
106 #define IS_MEM_REGNO(regno) ((regno) >= MEM0_REGNO && (regno) <= MEM7_REGNO)
107 #define IS_MEM_REG(rtx) (GET_CODE (rtx) == REG && IS_MEM_REGNO (REGNO (rtx)))
109 #define IS_CR_REGNO(regno) ((regno) >= SB_REGNO && (regno) <= PC_REGNO)
110 #define IS_CR_REG(rtx) (GET_CODE (rtx) == REG && IS_CR_REGNO (REGNO (rtx)))
112 /* We do most RTX matching by converting the RTX into a string, and
113 using string compares. This vastly simplifies the logic in many of
114 the functions in this file.
116 On exit, pattern[] has the encoded string (use RTX_IS("...") to
117 compare it) and patternr[] has pointers to the nodes in the RTX
118 corresponding to each character in the encoded string. The latter
119 is mostly used by print_operand().
121 Unrecognized patterns have '?' in them; this shows up when the
122 assembler complains about syntax errors.
126 encode_pattern_1 (rtx x)
130 if (patternp == pattern + sizeof (pattern) - 2)
136 patternr[patternp - pattern] = x;
138 switch (GET_CODE (x))
144 if (GET_MODE_SIZE (GET_MODE (x)) !=
145 GET_MODE_SIZE (GET_MODE (XEXP (x, 0))))
147 encode_pattern_1 (XEXP (x, 0));
152 encode_pattern_1 (XEXP (x, 0));
156 encode_pattern_1 (XEXP (x, 0));
157 encode_pattern_1 (XEXP (x, 1));
161 encode_pattern_1 (XEXP (x, 0));
165 encode_pattern_1 (XEXP (x, 0));
169 encode_pattern_1 (XEXP (x, 0));
170 encode_pattern_1 (XEXP (x, 1));
174 encode_pattern_1 (XEXP (x, 0));
191 *patternp++ = '0' + XCINT (x, 1, UNSPEC);
192 for (i = 0; i < XVECLEN (x, 0); i++)
193 encode_pattern_1 (XVECEXP (x, 0, i));
200 for (i = 0; i < XVECLEN (x, 0); i++)
201 encode_pattern_1 (XVECEXP (x, 0, i));
205 encode_pattern_1 (XEXP (x, 0));
207 encode_pattern_1 (XEXP (x, 1));
212 fprintf (stderr, "can't encode pattern %s\n",
213 GET_RTX_NAME (GET_CODE (x)));
222 encode_pattern (rtx x)
225 encode_pattern_1 (x);
229 /* Since register names indicate the mode they're used in, we need a
230 way to determine which name to refer to the register with. Called
231 by print_operand(). */
234 reg_name_with_mode (int regno, enum machine_mode mode)
236 int mlen = GET_MODE_SIZE (mode);
237 if (regno == R0_REGNO && mlen == 1)
239 if (regno == R0_REGNO && (mlen == 3 || mlen == 4))
241 if (regno == R0_REGNO && mlen == 6)
243 if (regno == R0_REGNO && mlen == 8)
245 if (regno == R1_REGNO && mlen == 1)
247 if (regno == R1_REGNO && (mlen == 3 || mlen == 4))
249 if (regno == A0_REGNO && TARGET_A16 && (mlen == 3 || mlen == 4))
251 return reg_names[regno];
254 /* How many bytes a register uses on stack when it's pushed. We need
255 to know this because the push opcode needs to explicitly indicate
256 the size of the register, even though the name of the register
257 already tells it that. Used by m32c_output_reg_{push,pop}, which
258 is only used through calls to ASM_OUTPUT_REG_{PUSH,POP}. */
261 reg_push_size (int regno)
286 static int *class_sizes = 0;
288 /* Given two register classes, find the largest intersection between
289 them. If there is no intersection, return RETURNED_IF_EMPTY
292 reduce_class (int original_class, int limiting_class, int returned_if_empty)
294 int cc = class_contents[original_class][0];
295 int i, best = NO_REGS;
298 if (original_class == limiting_class)
299 return original_class;
304 class_sizes = (int *) xmalloc (LIM_REG_CLASSES * sizeof (int));
305 for (i = 0; i < LIM_REG_CLASSES; i++)
308 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
309 if (class_contents[i][0] & (1 << r))
314 cc &= class_contents[limiting_class][0];
315 for (i = 0; i < LIM_REG_CLASSES; i++)
317 int ic = class_contents[i][0];
320 if (best_size < class_sizes[i])
323 best_size = class_sizes[i];
328 return returned_if_empty;
332 /* Returns TRUE If there are any registers that exist in both register
335 classes_intersect (int class1, int class2)
337 return class_contents[class1][0] & class_contents[class2][0];
340 /* Used by m32c_register_move_cost to determine if a move is
341 impossibly expensive. */
343 class_can_hold_mode (int class, enum machine_mode mode)
345 /* Cache the results: 0=untested 1=no 2=yes */
346 static char results[LIM_REG_CLASSES][MAX_MACHINE_MODE];
347 if (results[class][mode] == 0)
350 results[class][mode] = 1;
351 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
352 if (class_contents[class][0] & (1 << r)
353 && HARD_REGNO_MODE_OK (r, mode))
356 n = HARD_REGNO_NREGS (r, mode);
357 for (i = 1; i < n; i++)
358 if (!(class_contents[class][0] & (1 << (r + i))))
362 results[class][mode] = 2;
368 fprintf (stderr, "class %s can hold %s? %s\n",
369 class_names[class], mode_name[mode],
370 (results[class][mode] == 2) ? "yes" : "no");
372 return results[class][mode] == 2;
375 /* Run-time Target Specification. */
377 /* Memregs are memory locations that gcc treats like general
378 registers, as there are a limited number of true registers and the
379 m32c families can use memory in most places that registers can be
382 However, since memory accesses are more expensive than registers,
383 we allow the user to limit the number of memregs available, in
384 order to try to persuade gcc to try harder to use real registers.
386 Memregs are provided by m32c-lib1.S.
389 int target_memregs = 16;
390 static bool target_memregs_set = FALSE;
391 int ok_to_change_target_memregs = TRUE;
393 #undef TARGET_HANDLE_OPTION
394 #define TARGET_HANDLE_OPTION m32c_handle_option
396 m32c_handle_option (size_t code,
397 const char *arg ATTRIBUTE_UNUSED,
398 int value ATTRIBUTE_UNUSED)
400 if (code == OPT_memregs_)
402 target_memregs_set = TRUE;
403 target_memregs = atoi (arg);
408 /* Implements OVERRIDE_OPTIONS. We limit memregs to 0..16, and
409 provide a default. */
411 m32c_override_options (void)
413 if (target_memregs_set)
415 if (target_memregs < 0 || target_memregs > 16)
416 error ("invalid target memregs value '%d'", target_memregs);
422 /* Defining data structures for per-function information */
424 /* The usual; we set up our machine_function data. */
425 static struct machine_function *
426 m32c_init_machine_status (void)
428 struct machine_function *machine;
430 (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
435 /* Implements INIT_EXPANDERS. We just set up to call the above
438 m32c_init_expanders (void)
440 init_machine_status = m32c_init_machine_status;
445 #undef TARGET_PROMOTE_FUNCTION_RETURN
446 #define TARGET_PROMOTE_FUNCTION_RETURN m32c_promote_function_return
448 m32c_promote_function_return (const_tree fntype ATTRIBUTE_UNUSED)
453 /* Register Basics */
455 /* Basic Characteristics of Registers */
457 /* Whether a mode fits in a register is complex enough to warrant a
466 } nregs_table[FIRST_PSEUDO_REGISTER] =
468 { 1, 1, 2, 2, 4 }, /* r0 */
469 { 0, 1, 0, 0, 0 }, /* r2 */
470 { 1, 1, 2, 2, 0 }, /* r1 */
471 { 0, 1, 0, 0, 0 }, /* r3 */
472 { 0, 1, 1, 0, 0 }, /* a0 */
473 { 0, 1, 1, 0, 0 }, /* a1 */
474 { 0, 1, 1, 0, 0 }, /* sb */
475 { 0, 1, 1, 0, 0 }, /* fb */
476 { 0, 1, 1, 0, 0 }, /* sp */
477 { 1, 1, 1, 0, 0 }, /* pc */
478 { 0, 0, 0, 0, 0 }, /* fl */
479 { 1, 1, 1, 0, 0 }, /* ap */
480 { 1, 1, 2, 2, 4 }, /* mem0 */
481 { 1, 1, 2, 2, 4 }, /* mem1 */
482 { 1, 1, 2, 2, 4 }, /* mem2 */
483 { 1, 1, 2, 2, 4 }, /* mem3 */
484 { 1, 1, 2, 2, 4 }, /* mem4 */
485 { 1, 1, 2, 2, 0 }, /* mem5 */
486 { 1, 1, 2, 2, 0 }, /* mem6 */
487 { 1, 1, 0, 0, 0 }, /* mem7 */
490 /* Implements CONDITIONAL_REGISTER_USAGE. We adjust the number of
491 available memregs, and select which registers need to be preserved
492 across calls based on the chip family. */
495 m32c_conditional_register_usage (void)
499 if (0 <= target_memregs && target_memregs <= 16)
501 /* The command line option is bytes, but our "registers" are
503 for (i = target_memregs/2; i < 8; i++)
505 fixed_regs[MEM0_REGNO + i] = 1;
506 CLEAR_HARD_REG_BIT (reg_class_contents[MEM_REGS], MEM0_REGNO + i);
510 /* M32CM and M32C preserve more registers across function calls. */
513 call_used_regs[R1_REGNO] = 0;
514 call_used_regs[R2_REGNO] = 0;
515 call_used_regs[R3_REGNO] = 0;
516 call_used_regs[A0_REGNO] = 0;
517 call_used_regs[A1_REGNO] = 0;
521 /* How Values Fit in Registers */
523 /* Implements HARD_REGNO_NREGS. This is complicated by the fact that
524 different registers are different sizes from each other, *and* may
525 be different sizes in different chip families. */
527 m32c_hard_regno_nregs_1 (int regno, enum machine_mode mode)
529 if (regno == FLG_REGNO && mode == CCmode)
531 if (regno >= FIRST_PSEUDO_REGISTER)
532 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
534 if (regno >= MEM0_REGNO && regno <= MEM7_REGNO)
535 return (GET_MODE_SIZE (mode) + 1) / 2;
537 if (GET_MODE_SIZE (mode) <= 1)
538 return nregs_table[regno].qi_regs;
539 if (GET_MODE_SIZE (mode) <= 2)
540 return nregs_table[regno].hi_regs;
541 if (regno == A0_REGNO && mode == PSImode && TARGET_A16)
543 if ((GET_MODE_SIZE (mode) <= 3 || mode == PSImode) && TARGET_A24)
544 return nregs_table[regno].pi_regs;
545 if (GET_MODE_SIZE (mode) <= 4)
546 return nregs_table[regno].si_regs;
547 if (GET_MODE_SIZE (mode) <= 8)
548 return nregs_table[regno].di_regs;
553 m32c_hard_regno_nregs (int regno, enum machine_mode mode)
555 int rv = m32c_hard_regno_nregs_1 (regno, mode);
559 /* Implements HARD_REGNO_MODE_OK. The above function does the work
560 already; just test its return value. */
562 m32c_hard_regno_ok (int regno, enum machine_mode mode)
564 return m32c_hard_regno_nregs_1 (regno, mode) != 0;
567 /* Implements MODES_TIEABLE_P. In general, modes aren't tieable since
568 registers are all different sizes. However, since most modes are
569 bigger than our registers anyway, it's easier to implement this
570 function that way, leaving QImode as the only unique case. */
572 m32c_modes_tieable_p (enum machine_mode m1, enum machine_mode m2)
574 if (GET_MODE_SIZE (m1) == GET_MODE_SIZE (m2))
578 if (m1 == QImode || m2 == QImode)
585 /* Register Classes */
587 /* Implements REGNO_REG_CLASS. */
589 m32c_regno_reg_class (int regno)
613 if (IS_MEM_REGNO (regno))
619 /* Implements REG_CLASS_FROM_CONSTRAINT. Note that some constraints only match
620 for certain chip families. */
622 m32c_reg_class_from_constraint (char c ATTRIBUTE_UNUSED, const char *s)
624 if (memcmp (s, "Rsp", 3) == 0)
626 if (memcmp (s, "Rfb", 3) == 0)
628 if (memcmp (s, "Rsb", 3) == 0)
630 if (memcmp (s, "Rcr", 3) == 0)
631 return TARGET_A16 ? CR_REGS : NO_REGS;
632 if (memcmp (s, "Rcl", 3) == 0)
633 return TARGET_A24 ? CR_REGS : NO_REGS;
634 if (memcmp (s, "R0w", 3) == 0)
636 if (memcmp (s, "R1w", 3) == 0)
638 if (memcmp (s, "R2w", 3) == 0)
640 if (memcmp (s, "R3w", 3) == 0)
642 if (memcmp (s, "R02", 3) == 0)
644 if (memcmp (s, "R03", 3) == 0)
646 if (memcmp (s, "Rdi", 3) == 0)
648 if (memcmp (s, "Rhl", 3) == 0)
650 if (memcmp (s, "R23", 3) == 0)
652 if (memcmp (s, "Ra0", 3) == 0)
654 if (memcmp (s, "Ra1", 3) == 0)
656 if (memcmp (s, "Raa", 3) == 0)
658 if (memcmp (s, "Raw", 3) == 0)
659 return TARGET_A16 ? A_REGS : NO_REGS;
660 if (memcmp (s, "Ral", 3) == 0)
661 return TARGET_A24 ? A_REGS : NO_REGS;
662 if (memcmp (s, "Rqi", 3) == 0)
664 if (memcmp (s, "Rad", 3) == 0)
666 if (memcmp (s, "Rsi", 3) == 0)
668 if (memcmp (s, "Rhi", 3) == 0)
670 if (memcmp (s, "Rhc", 3) == 0)
672 if (memcmp (s, "Rra", 3) == 0)
674 if (memcmp (s, "Rfl", 3) == 0)
676 if (memcmp (s, "Rmm", 3) == 0)
678 if (fixed_regs[MEM0_REGNO])
683 /* PSImode registers - i.e. whatever can hold a pointer. */
684 if (memcmp (s, "Rpi", 3) == 0)
689 return RA_REGS; /* r2r0 and r3r1 can hold pointers. */
692 /* We handle this one as an EXTRA_CONSTRAINT. */
693 if (memcmp (s, "Rpa", 3) == 0)
698 fprintf(stderr, "unrecognized R constraint: %.3s\n", s);
705 /* Implements REGNO_OK_FOR_BASE_P. */
707 m32c_regno_ok_for_base_p (int regno)
709 if (regno == A0_REGNO
710 || regno == A1_REGNO || regno >= FIRST_PSEUDO_REGISTER)
715 #define DEBUG_RELOAD 0
717 /* Implements PREFERRED_RELOAD_CLASS. In general, prefer general
718 registers of the appropriate size. */
720 m32c_preferred_reload_class (rtx x, int rclass)
722 int newclass = rclass;
725 fprintf (stderr, "\npreferred_reload_class for %s is ",
726 class_names[rclass]);
728 if (rclass == NO_REGS)
729 rclass = GET_MODE (x) == QImode ? HL_REGS : R03_REGS;
731 if (classes_intersect (rclass, CR_REGS))
733 switch (GET_MODE (x))
739 /* newclass = HI_REGS; */
744 else if (newclass == QI_REGS && GET_MODE_SIZE (GET_MODE (x)) > 2)
746 else if (GET_MODE_SIZE (GET_MODE (x)) > 4
747 && ~class_contents[rclass][0] & 0x000f)
750 rclass = reduce_class (rclass, newclass, rclass);
752 if (GET_MODE (x) == QImode)
753 rclass = reduce_class (rclass, HL_REGS, rclass);
756 fprintf (stderr, "%s\n", class_names[rclass]);
759 if (GET_CODE (x) == MEM
760 && GET_CODE (XEXP (x, 0)) == PLUS
761 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
762 fprintf (stderr, "Glorm!\n");
767 /* Implements PREFERRED_OUTPUT_RELOAD_CLASS. */
769 m32c_preferred_output_reload_class (rtx x, int rclass)
771 return m32c_preferred_reload_class (x, rclass);
774 /* Implements LIMIT_RELOAD_CLASS. We basically want to avoid using
775 address registers for reloads since they're needed for address
778 m32c_limit_reload_class (enum machine_mode mode, int rclass)
781 fprintf (stderr, "limit_reload_class for %s: %s ->",
782 mode_name[mode], class_names[rclass]);
786 rclass = reduce_class (rclass, HL_REGS, rclass);
787 else if (mode == HImode)
788 rclass = reduce_class (rclass, HI_REGS, rclass);
789 else if (mode == SImode)
790 rclass = reduce_class (rclass, SI_REGS, rclass);
792 if (rclass != A_REGS)
793 rclass = reduce_class (rclass, DI_REGS, rclass);
796 fprintf (stderr, " %s\n", class_names[rclass]);
801 /* Implements SECONDARY_RELOAD_CLASS. QImode have to be reloaded in
802 r0 or r1, as those are the only real QImode registers. CR regs get
803 reloaded through appropriately sized general or address
806 m32c_secondary_reload_class (int rclass, enum machine_mode mode, rtx x)
808 int cc = class_contents[rclass][0];
810 fprintf (stderr, "\nsecondary reload class %s %s\n",
811 class_names[rclass], mode_name[mode]);
815 && GET_CODE (x) == MEM && (cc & ~class_contents[R23_REGS][0]) == 0)
817 if (classes_intersect (rclass, CR_REGS)
818 && GET_CODE (x) == REG
819 && REGNO (x) >= SB_REGNO && REGNO (x) <= SP_REGNO)
820 return TARGET_A16 ? HI_REGS : A_REGS;
824 /* Implements CLASS_LIKELY_SPILLED_P. A_REGS is needed for address
827 m32c_class_likely_spilled_p (int regclass)
829 if (regclass == A_REGS)
831 return reg_class_size[regclass] == 1;
834 /* Implements CLASS_MAX_NREGS. We calculate this according to its
835 documented meaning, to avoid potential inconsistencies with actual
836 class definitions. */
838 m32c_class_max_nregs (int regclass, enum machine_mode mode)
842 for (rn = 0; rn < FIRST_PSEUDO_REGISTER; rn++)
843 if (class_contents[regclass][0] & (1 << rn))
845 int n = m32c_hard_regno_nregs (rn, mode);
852 /* Implements CANNOT_CHANGE_MODE_CLASS. Only r0 and r1 can change to
853 QI (r0l, r1l) because the chip doesn't support QI ops on other
854 registers (well, it does on a0/a1 but if we let gcc do that, reload
855 suffers). Otherwise, we allow changes to larger modes. */
857 m32c_cannot_change_mode_class (enum machine_mode from,
858 enum machine_mode to, int rclass)
862 fprintf (stderr, "cannot change from %s to %s in %s\n",
863 mode_name[from], mode_name[to], class_names[rclass]);
866 /* If the larger mode isn't allowed in any of these registers, we
867 can't allow the change. */
868 for (rn = 0; rn < FIRST_PSEUDO_REGISTER; rn++)
869 if (class_contents[rclass][0] & (1 << rn))
870 if (! m32c_hard_regno_ok (rn, to))
874 return (class_contents[rclass][0] & 0x1ffa);
876 if (class_contents[rclass][0] & 0x0005 /* r0, r1 */
877 && GET_MODE_SIZE (from) > 1)
879 if (GET_MODE_SIZE (from) > 2) /* all other regs */
885 /* Helpers for the rest of the file. */
886 /* TRUE if the rtx is a REG rtx for the given register. */
887 #define IS_REG(rtx,regno) (GET_CODE (rtx) == REG \
888 && REGNO (rtx) == regno)
889 /* TRUE if the rtx is a pseudo - specifically, one we can use as a
890 base register in address calculations (hence the "strict"
892 #define IS_PSEUDO(rtx,strict) (!strict && GET_CODE (rtx) == REG \
893 && (REGNO (rtx) == AP_REGNO \
894 || REGNO (rtx) >= FIRST_PSEUDO_REGISTER))
896 /* Implements CONST_OK_FOR_CONSTRAINT_P. Currently, all constant
897 constraints start with 'I', with the next two characters indicating
898 the type and size of the range allowed. */
900 m32c_const_ok_for_constraint_p (HOST_WIDE_INT value,
901 char c ATTRIBUTE_UNUSED, const char *str)
903 /* s=signed u=unsigned n=nonzero m=minus l=log2able,
904 [sun] bits [SUN] bytes, p=pointer size
905 I[-0-9][0-9] matches that number */
906 if (memcmp (str, "Is3", 3) == 0)
908 return (-8 <= value && value <= 7);
910 if (memcmp (str, "IS1", 3) == 0)
912 return (-128 <= value && value <= 127);
914 if (memcmp (str, "IS2", 3) == 0)
916 return (-32768 <= value && value <= 32767);
918 if (memcmp (str, "IU2", 3) == 0)
920 return (0 <= value && value <= 65535);
922 if (memcmp (str, "IU3", 3) == 0)
924 return (0 <= value && value <= 0x00ffffff);
926 if (memcmp (str, "In4", 3) == 0)
928 return (-8 <= value && value && value <= 8);
930 if (memcmp (str, "In5", 3) == 0)
932 return (-16 <= value && value && value <= 16);
934 if (memcmp (str, "In6", 3) == 0)
936 return (-32 <= value && value && value <= 32);
938 if (memcmp (str, "IM2", 3) == 0)
940 return (-65536 <= value && value && value <= -1);
942 if (memcmp (str, "Ilb", 3) == 0)
944 int b = exact_log2 (value);
945 return (b >= 0 && b <= 7);
947 if (memcmp (str, "Imb", 3) == 0)
949 int b = exact_log2 ((value ^ 0xff) & 0xff);
950 return (b >= 0 && b <= 7);
952 if (memcmp (str, "Ilw", 3) == 0)
954 int b = exact_log2 (value);
955 return (b >= 0 && b <= 15);
957 if (memcmp (str, "Imw", 3) == 0)
959 int b = exact_log2 ((value ^ 0xffff) & 0xffff);
960 return (b >= 0 && b <= 15);
962 if (memcmp (str, "I00", 3) == 0)
969 /* Implements EXTRA_CONSTRAINT_STR (see next function too). 'S' is
970 for memory constraints, plus "Rpa" for PARALLEL rtx's we use for
971 call return values. */
973 m32c_extra_constraint_p2 (rtx value, char c ATTRIBUTE_UNUSED, const char *str)
975 encode_pattern (value);
976 if (memcmp (str, "Sd", 2) == 0)
978 /* This is the common "src/dest" address */
980 if (GET_CODE (value) == MEM && CONSTANT_P (XEXP (value, 0)))
982 if (RTX_IS ("ms") || RTX_IS ("m+si"))
984 if (RTX_IS ("m++rii"))
986 if (REGNO (patternr[3]) == FB_REGNO
987 && INTVAL (patternr[4]) == 0)
992 else if (RTX_IS ("m+ri") || RTX_IS ("m+rs") || RTX_IS ("m+r+si"))
996 if (REGNO (r) == SP_REGNO)
998 return m32c_legitimate_address_p (GET_MODE (value), XEXP (value, 0), 1);
1000 else if (memcmp (str, "Sa", 2) == 0)
1005 else if (RTX_IS ("m+ri"))
1009 return (IS_REG (r, A0_REGNO) || IS_REG (r, A1_REGNO));
1011 else if (memcmp (str, "Si", 2) == 0)
1013 return (RTX_IS ("mi") || RTX_IS ("ms") || RTX_IS ("m+si"));
1015 else if (memcmp (str, "Ss", 2) == 0)
1017 return ((RTX_IS ("mr")
1018 && (IS_REG (patternr[1], SP_REGNO)))
1019 || (RTX_IS ("m+ri") && (IS_REG (patternr[2], SP_REGNO))));
1021 else if (memcmp (str, "Sf", 2) == 0)
1023 return ((RTX_IS ("mr")
1024 && (IS_REG (patternr[1], FB_REGNO)))
1025 || (RTX_IS ("m+ri") && (IS_REG (patternr[2], FB_REGNO))));
1027 else if (memcmp (str, "Sb", 2) == 0)
1029 return ((RTX_IS ("mr")
1030 && (IS_REG (patternr[1], SB_REGNO)))
1031 || (RTX_IS ("m+ri") && (IS_REG (patternr[2], SB_REGNO))));
1033 else if (memcmp (str, "Sp", 2) == 0)
1035 /* Absolute addresses 0..0x1fff used for bit addressing (I/O ports) */
1036 return (RTX_IS ("mi")
1037 && !(INTVAL (patternr[1]) & ~0x1fff));
1039 else if (memcmp (str, "S1", 2) == 0)
1041 return r1h_operand (value, QImode);
1044 gcc_assert (str[0] != 'S');
1046 if (memcmp (str, "Rpa", 2) == 0)
1047 return GET_CODE (value) == PARALLEL;
1052 /* This is for when we're debugging the above. */
1054 m32c_extra_constraint_p (rtx value, char c, const char *str)
1056 int rv = m32c_extra_constraint_p2 (value, c, str);
1058 fprintf (stderr, "\nconstraint %.*s: %d\n", CONSTRAINT_LEN (c, str), str,
1065 /* Implements EXTRA_MEMORY_CONSTRAINT. Currently, we only use strings
1066 starting with 'S'. */
1068 m32c_extra_memory_constraint (char c, const char *str ATTRIBUTE_UNUSED)
1073 /* Implements EXTRA_ADDRESS_CONSTRAINT. We reserve 'A' strings for these,
1074 but don't currently define any. */
1076 m32c_extra_address_constraint (char c, const char *str ATTRIBUTE_UNUSED)
1081 /* STACK AND CALLING */
1085 /* Implements RETURN_ADDR_RTX. Note that R8C and M16C push 24 bits
1086 (yes, THREE bytes) onto the stack for the return address, but we
1087 don't support pointers bigger than 16 bits on those chips. This
1088 will likely wreak havoc with exception unwinding. FIXME. */
1090 m32c_return_addr_rtx (int count)
1092 enum machine_mode mode;
1098 /* we want 2[$fb] */
1102 /* It's four bytes */
1108 /* FIXME: it's really 3 bytes */
1114 gen_rtx_MEM (mode, plus_constant (gen_rtx_REG (Pmode, FP_REGNO), offset));
1115 return copy_to_mode_reg (mode, ra_mem);
1118 /* Implements INCOMING_RETURN_ADDR_RTX. See comment above. */
1120 m32c_incoming_return_addr_rtx (void)
1123 return gen_rtx_MEM (PSImode, gen_rtx_REG (PSImode, SP_REGNO));
1126 /* Exception Handling Support */
1128 /* Implements EH_RETURN_DATA_REGNO. Choose registers able to hold
1131 m32c_eh_return_data_regno (int n)
1143 return INVALID_REGNUM;
1147 /* Implements EH_RETURN_STACKADJ_RTX. Saved and used later in
1148 m32c_emit_eh_epilogue. */
1150 m32c_eh_return_stackadj_rtx (void)
1152 if (!cfun->machine->eh_stack_adjust)
1156 sa = gen_rtx_REG (Pmode, R0_REGNO);
1157 cfun->machine->eh_stack_adjust = sa;
1159 return cfun->machine->eh_stack_adjust;
1162 /* Registers That Address the Stack Frame */
1164 /* Implements DWARF_FRAME_REGNUM and DBX_REGISTER_NUMBER. Note that
1165 the original spec called for dwarf numbers to vary with register
1166 width as well, for example, r0l, r0, and r2r0 would each have
1167 different dwarf numbers. GCC doesn't support this, and we don't do
1168 it, and gdb seems to like it this way anyway. */
1170 m32c_dwarf_frame_regnum (int n)
1196 return DWARF_FRAME_REGISTERS + 1;
1200 /* The frame looks like this:
1202 ap -> +------------------------------
1203 | Return address (3 or 4 bytes)
1204 | Saved FB (2 or 4 bytes)
1205 fb -> +------------------------------
1208 | through r0 as needed
1209 sp -> +------------------------------
1212 /* We use this to wrap all emitted insns in the prologue. */
1216 RTX_FRAME_RELATED_P (x) = 1;
1220 /* This maps register numbers to the PUSHM/POPM bitfield, and tells us
1221 how much the stack pointer moves for each, for each cpu family. */
1230 /* These are in reverse push (nearest-to-sp) order. */
1231 { R0_REGNO, 0x80, 2, 2 },
1232 { R1_REGNO, 0x40, 2, 2 },
1233 { R2_REGNO, 0x20, 2, 2 },
1234 { R3_REGNO, 0x10, 2, 2 },
1235 { A0_REGNO, 0x08, 2, 4 },
1236 { A1_REGNO, 0x04, 2, 4 },
1237 { SB_REGNO, 0x02, 2, 4 },
1238 { FB_REGNO, 0x01, 2, 4 }
1241 #define PUSHM_N (sizeof(pushm_info)/sizeof(pushm_info[0]))
1243 /* Returns TRUE if we need to save/restore the given register. We
1244 save everything for exception handlers, so that any register can be
1245 unwound. For interrupt handlers, we save everything if the handler
1246 calls something else (because we don't know what *that* function
1247 might do), but try to be a bit smarter if the handler is a leaf
1248 function. We always save $a0, though, because we use that in the
1249 epilogue to copy $fb to $sp. */
1251 need_to_save (int regno)
1253 if (fixed_regs[regno])
1255 if (crtl->calls_eh_return)
1257 if (regno == FP_REGNO)
1259 if (cfun->machine->is_interrupt
1260 && (!cfun->machine->is_leaf || regno == A0_REGNO))
1262 if (df_regs_ever_live_p (regno)
1263 && (!call_used_regs[regno] || cfun->machine->is_interrupt))
1268 /* This function contains all the intelligence about saving and
1269 restoring registers. It always figures out the register save set.
1270 When called with PP_justcount, it merely returns the size of the
1271 save set (for eliminating the frame pointer, for example). When
1272 called with PP_pushm or PP_popm, it emits the appropriate
1273 instructions for saving (pushm) or restoring (popm) the
1276 m32c_pushm_popm (Push_Pop_Type ppt)
1279 int byte_count = 0, bytes;
1281 rtx dwarf_set[PUSHM_N];
1283 int nosave_mask = 0;
1285 if (crtl->return_rtx
1286 && GET_CODE (crtl->return_rtx) == PARALLEL
1287 && !(crtl->calls_eh_return || cfun->machine->is_interrupt))
1289 rtx exp = XVECEXP (crtl->return_rtx, 0, 0);
1290 rtx rv = XEXP (exp, 0);
1291 int rv_bytes = GET_MODE_SIZE (GET_MODE (rv));
1294 nosave_mask |= 0x20; /* PSI, SI */
1296 nosave_mask |= 0xf0; /* DF */
1298 nosave_mask |= 0x50; /* DI */
1301 for (i = 0; i < (int) PUSHM_N; i++)
1303 /* Skip if neither register needs saving. */
1304 if (!need_to_save (pushm_info[i].reg1))
1307 if (pushm_info[i].bit & nosave_mask)
1310 reg_mask |= pushm_info[i].bit;
1311 bytes = TARGET_A16 ? pushm_info[i].a16_bytes : pushm_info[i].a24_bytes;
1313 if (ppt == PP_pushm)
1315 enum machine_mode mode = (bytes == 2) ? HImode : SImode;
1318 /* Always use stack_pointer_rtx instead of calling
1319 rtx_gen_REG ourselves. Code elsewhere in GCC assumes
1320 that there is a single rtx representing the stack pointer,
1321 namely stack_pointer_rtx, and uses == to recognize it. */
1322 addr = stack_pointer_rtx;
1324 if (byte_count != 0)
1325 addr = gen_rtx_PLUS (GET_MODE (addr), addr, GEN_INT (byte_count));
1327 dwarf_set[n_dwarfs++] =
1328 gen_rtx_SET (VOIDmode,
1329 gen_rtx_MEM (mode, addr),
1330 gen_rtx_REG (mode, pushm_info[i].reg1));
1331 F (dwarf_set[n_dwarfs - 1]);
1334 byte_count += bytes;
1337 if (cfun->machine->is_interrupt)
1339 cfun->machine->intr_pushm = reg_mask & 0xfe;
1344 if (cfun->machine->is_interrupt)
1345 for (i = MEM0_REGNO; i <= MEM7_REGNO; i++)
1346 if (need_to_save (i))
1349 cfun->machine->intr_pushmem[i - MEM0_REGNO] = 1;
1352 if (ppt == PP_pushm && byte_count)
1354 rtx note = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (n_dwarfs + 1));
1359 XVECEXP (note, 0, 0)
1360 = gen_rtx_SET (VOIDmode,
1362 gen_rtx_PLUS (GET_MODE (stack_pointer_rtx),
1364 GEN_INT (-byte_count)));
1365 F (XVECEXP (note, 0, 0));
1367 for (i = 0; i < n_dwarfs; i++)
1368 XVECEXP (note, 0, i + 1) = dwarf_set[i];
1370 pushm = F (emit_insn (gen_pushm (GEN_INT (reg_mask))));
1372 REG_NOTES (pushm) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, note,
1376 if (cfun->machine->is_interrupt)
1377 for (i = MEM0_REGNO; i <= MEM7_REGNO; i++)
1378 if (cfun->machine->intr_pushmem[i - MEM0_REGNO])
1381 pushm = emit_insn (gen_pushhi_16 (gen_rtx_REG (HImode, i)));
1383 pushm = emit_insn (gen_pushhi_24 (gen_rtx_REG (HImode, i)));
1387 if (ppt == PP_popm && byte_count)
1389 if (cfun->machine->is_interrupt)
1390 for (i = MEM7_REGNO; i >= MEM0_REGNO; i--)
1391 if (cfun->machine->intr_pushmem[i - MEM0_REGNO])
1394 emit_insn (gen_pophi_16 (gen_rtx_REG (HImode, i)));
1396 emit_insn (gen_pophi_24 (gen_rtx_REG (HImode, i)));
1399 emit_insn (gen_popm (GEN_INT (reg_mask)));
1405 /* Implements INITIAL_ELIMINATION_OFFSET. See the comment above that
1406 diagrams our call frame. */
1408 m32c_initial_elimination_offset (int from, int to)
1412 if (from == AP_REGNO)
1422 ofs += m32c_pushm_popm (PP_justcount);
1423 ofs += get_frame_size ();
1426 /* Account for push rounding. */
1428 ofs = (ofs + 1) & ~1;
1430 fprintf (stderr, "initial_elimination_offset from=%d to=%d, ofs=%d\n", from,
1436 /* Passing Function Arguments on the Stack */
1438 #undef TARGET_PROMOTE_PROTOTYPES
1439 #define TARGET_PROMOTE_PROTOTYPES m32c_promote_prototypes
1441 m32c_promote_prototypes (const_tree fntype ATTRIBUTE_UNUSED)
1446 /* Implements PUSH_ROUNDING. The R8C and M16C have byte stacks, the
1447 M32C has word stacks. */
1449 m32c_push_rounding (int n)
1451 if (TARGET_R8C || TARGET_M16C)
1453 return (n + 1) & ~1;
1456 /* Passing Arguments in Registers */
1458 /* Implements FUNCTION_ARG. Arguments are passed partly in registers,
1459 partly on stack. If our function returns a struct, a pointer to a
1460 buffer for it is at the top of the stack (last thing pushed). The
1461 first few real arguments may be in registers as follows:
1463 R8C/M16C: arg1 in r1 if it's QI or HI (else it's pushed on stack)
1464 arg2 in r2 if it's HI (else pushed on stack)
1466 M32C: arg1 in r0 if it's QI or HI (else it's pushed on stack)
1469 Structs are not passed in registers, even if they fit. Only
1470 integer and pointer types are passed in registers.
1472 Note that when arg1 doesn't fit in r1, arg2 may still be passed in
1475 m32c_function_arg (CUMULATIVE_ARGS * ca,
1476 enum machine_mode mode, tree type, int named)
1478 /* Can return a reg, parallel, or 0 for stack */
1481 fprintf (stderr, "func_arg %d (%s, %d)\n",
1482 ca->parm_num, mode_name[mode], named);
1486 if (mode == VOIDmode)
1489 if (ca->force_mem || !named)
1492 fprintf (stderr, "func arg: force %d named %d, mem\n", ca->force_mem,
1498 if (type && INTEGRAL_TYPE_P (type) && POINTER_TYPE_P (type))
1501 if (type && AGGREGATE_TYPE_P (type))
1504 switch (ca->parm_num)
1507 if (GET_MODE_SIZE (mode) == 1 || GET_MODE_SIZE (mode) == 2)
1508 rv = gen_rtx_REG (mode, TARGET_A16 ? R1_REGNO : R0_REGNO);
1512 if (TARGET_A16 && GET_MODE_SIZE (mode) == 2)
1513 rv = gen_rtx_REG (mode, R2_REGNO);
1523 #undef TARGET_PASS_BY_REFERENCE
1524 #define TARGET_PASS_BY_REFERENCE m32c_pass_by_reference
1526 m32c_pass_by_reference (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED,
1527 enum machine_mode mode ATTRIBUTE_UNUSED,
1528 const_tree type ATTRIBUTE_UNUSED,
1529 bool named ATTRIBUTE_UNUSED)
1534 /* Implements INIT_CUMULATIVE_ARGS. */
1536 m32c_init_cumulative_args (CUMULATIVE_ARGS * ca,
1538 rtx libname ATTRIBUTE_UNUSED,
1540 int n_named_args ATTRIBUTE_UNUSED)
1542 if (fntype && aggregate_value_p (TREE_TYPE (fntype), fndecl))
1549 /* Implements FUNCTION_ARG_ADVANCE. force_mem is set for functions
1550 returning structures, so we always reset that. Otherwise, we only
1551 need to know the sequence number of the argument to know what to do
1554 m32c_function_arg_advance (CUMULATIVE_ARGS * ca,
1555 enum machine_mode mode ATTRIBUTE_UNUSED,
1556 tree type ATTRIBUTE_UNUSED,
1557 int named ATTRIBUTE_UNUSED)
1565 /* Implements FUNCTION_ARG_REGNO_P. */
1567 m32c_function_arg_regno_p (int r)
1570 return (r == R0_REGNO);
1571 return (r == R1_REGNO || r == R2_REGNO);
1574 /* HImode and PSImode are the two "native" modes as far as GCC is
1575 concerned, but the chips also support a 32-bit mode which is used
1576 for some opcodes in R8C/M16C and for reset vectors and such. */
1577 #undef TARGET_VALID_POINTER_MODE
1578 #define TARGET_VALID_POINTER_MODE m32c_valid_pointer_mode
1580 m32c_valid_pointer_mode (enum machine_mode mode)
1590 /* How Scalar Function Values Are Returned */
1592 /* Implements LIBCALL_VALUE. Most values are returned in $r0, or some
1593 combination of registers starting there (r2r0 for longs, r3r1r2r0
1594 for long long, r3r2r1r0 for doubles), except that that ABI
1595 currently doesn't work because it ends up using all available
1596 general registers and gcc often can't compile it. So, instead, we
1597 return anything bigger than 16 bits in "mem0" (effectively, a
1598 memory location). */
1600 m32c_libcall_value (enum machine_mode mode)
1602 /* return reg or parallel */
1604 /* FIXME: GCC has difficulty returning large values in registers,
1605 because that ties up most of the general registers and gives the
1606 register allocator little to work with. Until we can resolve
1607 this, large values are returned in memory. */
1612 rv = gen_rtx_PARALLEL (mode, rtvec_alloc (4));
1613 XVECEXP (rv, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode,
1614 gen_rtx_REG (HImode,
1617 XVECEXP (rv, 0, 1) = gen_rtx_EXPR_LIST (VOIDmode,
1618 gen_rtx_REG (HImode,
1621 XVECEXP (rv, 0, 2) = gen_rtx_EXPR_LIST (VOIDmode,
1622 gen_rtx_REG (HImode,
1625 XVECEXP (rv, 0, 3) = gen_rtx_EXPR_LIST (VOIDmode,
1626 gen_rtx_REG (HImode,
1632 if (TARGET_A24 && GET_MODE_SIZE (mode) > 2)
1636 rv = gen_rtx_PARALLEL (mode, rtvec_alloc (1));
1637 XVECEXP (rv, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode,
1645 if (GET_MODE_SIZE (mode) > 2)
1646 return gen_rtx_REG (mode, MEM0_REGNO);
1647 return gen_rtx_REG (mode, R0_REGNO);
1650 /* Implements FUNCTION_VALUE. Functions and libcalls have the same
1653 m32c_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED)
1655 /* return reg or parallel */
1656 const enum machine_mode mode = TYPE_MODE (valtype);
1657 return m32c_libcall_value (mode);
1660 /* How Large Values Are Returned */
1662 /* We return structures by pushing the address on the stack, even if
1663 we use registers for the first few "real" arguments. */
1664 #undef TARGET_STRUCT_VALUE_RTX
1665 #define TARGET_STRUCT_VALUE_RTX m32c_struct_value_rtx
1667 m32c_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED,
1668 int incoming ATTRIBUTE_UNUSED)
1673 /* Function Entry and Exit */
1675 /* Implements EPILOGUE_USES. Interrupts restore all registers. */
1677 m32c_epilogue_uses (int regno ATTRIBUTE_UNUSED)
1679 if (cfun->machine->is_interrupt)
1684 /* Implementing the Varargs Macros */
1686 #undef TARGET_STRICT_ARGUMENT_NAMING
1687 #define TARGET_STRICT_ARGUMENT_NAMING m32c_strict_argument_naming
1689 m32c_strict_argument_naming (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED)
1694 /* Trampolines for Nested Functions */
1698 1 0000 75C43412 mov.w #0x1234,a0
1699 2 0004 FC000000 jmp.a label
1702 1 0000 BC563412 mov.l:s #0x123456,a0
1703 2 0004 CC000000 jmp.a label
1706 /* Implements TRAMPOLINE_SIZE. */
1708 m32c_trampoline_size (void)
1710 /* Allocate extra space so we can avoid the messy shifts when we
1711 initialize the trampoline; we just write past the end of the
1713 return TARGET_A16 ? 8 : 10;
1716 /* Implements TRAMPOLINE_ALIGNMENT. */
1718 m32c_trampoline_alignment (void)
1723 /* Implements INITIALIZE_TRAMPOLINE. */
1725 m32c_initialize_trampoline (rtx tramp, rtx function, rtx chainval)
1727 #define A0(m,i) gen_rtx_MEM (m, plus_constant (tramp, i))
1730 /* Note: we subtract a "word" because the moves want signed
1731 constants, not unsigned constants. */
1732 emit_move_insn (A0 (HImode, 0), GEN_INT (0xc475 - 0x10000));
1733 emit_move_insn (A0 (HImode, 2), chainval);
1734 emit_move_insn (A0 (QImode, 4), GEN_INT (0xfc - 0x100));
1735 /* We use 16-bit addresses here, but store the zero to turn it
1736 into a 24-bit offset. */
1737 emit_move_insn (A0 (HImode, 5), function);
1738 emit_move_insn (A0 (QImode, 7), GEN_INT (0x00));
1742 /* Note that the PSI moves actually write 4 bytes. Make sure we
1743 write stuff out in the right order, and leave room for the
1744 extra byte at the end. */
1745 emit_move_insn (A0 (QImode, 0), GEN_INT (0xbc - 0x100));
1746 emit_move_insn (A0 (PSImode, 1), chainval);
1747 emit_move_insn (A0 (QImode, 4), GEN_INT (0xcc - 0x100));
1748 emit_move_insn (A0 (PSImode, 5), function);
1753 /* Implicit Calls to Library Routines */
1755 #undef TARGET_INIT_LIBFUNCS
1756 #define TARGET_INIT_LIBFUNCS m32c_init_libfuncs
1758 m32c_init_libfuncs (void)
1762 /* We do this because the M32C has an HImode operand, but the
1763 M16C has an 8-bit operand. Since gcc looks at the match data
1764 and not the expanded rtl, we have to reset the array so that
1765 the right modes are found. */
1766 setcc_gen_code[EQ] = CODE_FOR_seq_24;
1767 setcc_gen_code[NE] = CODE_FOR_sne_24;
1768 setcc_gen_code[GT] = CODE_FOR_sgt_24;
1769 setcc_gen_code[GE] = CODE_FOR_sge_24;
1770 setcc_gen_code[LT] = CODE_FOR_slt_24;
1771 setcc_gen_code[LE] = CODE_FOR_sle_24;
1772 setcc_gen_code[GTU] = CODE_FOR_sgtu_24;
1773 setcc_gen_code[GEU] = CODE_FOR_sgeu_24;
1774 setcc_gen_code[LTU] = CODE_FOR_sltu_24;
1775 setcc_gen_code[LEU] = CODE_FOR_sleu_24;
1779 /* Addressing Modes */
1781 #define BIG_FB_ADJ 0
1783 /* Used by GO_IF_LEGITIMATE_ADDRESS. The r8c/m32c family supports a
1784 wide range of non-orthogonal addressing modes, including the
1785 ability to double-indirect on *some* of them. Not all insns
1786 support all modes, either, but we rely on predicates and
1787 constraints to deal with that. */
1789 m32c_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1795 /* Wide references to memory will be split after reload, so we must
1796 ensure that all parts of such splits remain legitimate
1798 mode_adjust = GET_MODE_SIZE (mode) - 1;
1800 /* allowing PLUS yields mem:HI(plus:SI(mem:SI(plus:SI in m32c_split_move */
1801 if (GET_CODE (x) == PRE_DEC
1802 || GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_MODIFY)
1804 return (GET_CODE (XEXP (x, 0)) == REG
1805 && REGNO (XEXP (x, 0)) == SP_REGNO);
1809 /* This is the double indirection detection, but it currently
1810 doesn't work as cleanly as this code implies, so until we've had
1811 a chance to debug it, leave it disabled. */
1812 if (TARGET_A24 && GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) != PLUS)
1815 fprintf (stderr, "double indirect\n");
1824 /* Most indexable registers can be used without displacements,
1825 although some of them will be emitted with an explicit zero
1826 to please the assembler. */
1827 switch (REGNO (patternr[0]))
1837 if (IS_PSEUDO (patternr[0], strict))
1844 /* This is more interesting, because different base registers
1845 allow for different displacements - both range and signedness
1846 - and it differs from chip series to chip series too. */
1847 int rn = REGNO (patternr[1]);
1848 HOST_WIDE_INT offs = INTVAL (patternr[2]);
1854 /* The syntax only allows positive offsets, but when the
1855 offsets span the entire memory range, we can simulate
1856 negative offsets by wrapping. */
1858 return (offs >= -65536 && offs <= 65535 - mode_adjust);
1860 return (offs >= 0 && offs <= 65535 - mode_adjust);
1862 return (offs >= -16777216 && offs <= 16777215);
1866 return (offs >= -128 && offs <= 127 - mode_adjust);
1867 return (offs >= -65536 && offs <= 65535 - mode_adjust);
1870 return (offs >= -128 && offs <= 127 - mode_adjust);
1873 if (IS_PSEUDO (patternr[1], strict))
1878 if (RTX_IS ("+rs") || RTX_IS ("+r+si"))
1880 rtx reg = patternr[1];
1882 /* We don't know where the symbol is, so only allow base
1883 registers which support displacements spanning the whole
1885 switch (REGNO (reg))
1889 /* $sb needs a secondary reload, but since it's involved in
1890 memory address reloads too, we don't deal with it very
1892 /* case SB_REGNO: */
1895 if (IS_PSEUDO (reg, strict))
1900 if (RTX_IS ("++rii"))
1902 rtx reg = patternr[2];
1903 HOST_WIDE_INT offs = INTVAL (patternr[3]);
1905 /* Avoid reloads for addresses generated by
1906 m32c_legitimize_reload_address being generated by
1907 find_reloads_subreg_address. */
1908 if (REGNO (reg) == FB_REGNO && offs == -BIG_FB_ADJ)
1914 /* Implements REG_OK_FOR_BASE_P. */
1916 m32c_reg_ok_for_base_p (rtx x, int strict)
1918 if (GET_CODE (x) != REG)
1929 if (IS_PSEUDO (x, strict))
1935 /* We have three choices for choosing fb->aN offsets. If we choose -128,
1936 we need one MOVA -128[fb],aN opcode and 16-bit aN displacements,
1938 EB 4B FF mova -128[$fb],$a0
1939 D8 0C FF FF mov.w:Q #0,-1[$a0]
1941 Alternately, we subtract the frame size, and hopefully use 8-bit aN
1944 77 54 00 01 sub #256,$a0
1945 D8 08 01 mov.w:Q #0,1[$a0]
1947 If we don't offset (i.e. offset by zero), we end up with:
1949 D8 0C 00 FF mov.w:Q #0,-256[$a0]
1951 We have to subtract *something* so that we have a PLUS rtx to mark
1952 that we've done this reload. The -128 offset will never result in
1953 an 8-bit aN offset, and the payoff for the second case is five
1954 loads *if* those loads are within 256 bytes of the other end of the
1955 frame, so the third case seems best. Note that we subtract the
1956 zero, but detect that in the addhi3 pattern. */
1958 /* Implements LEGITIMIZE_ADDRESS. The only address we really have to
1959 worry about is frame base offsets, as $fb has a limited
1960 displacement range. We deal with this by attempting to reload $fb
1961 itself into an address register; that seems to result in the best
1964 m32c_legitimize_address (rtx * x ATTRIBUTE_UNUSED,
1965 rtx oldx ATTRIBUTE_UNUSED,
1966 enum machine_mode mode ATTRIBUTE_UNUSED)
1969 fprintf (stderr, "m32c_legitimize_address for mode %s\n", mode_name[mode]);
1971 fprintf (stderr, "\n");
1974 if (GET_CODE (*x) == PLUS
1975 && GET_CODE (XEXP (*x, 0)) == REG
1976 && REGNO (XEXP (*x, 0)) == FB_REGNO
1977 && GET_CODE (XEXP (*x, 1)) == CONST_INT
1978 && (INTVAL (XEXP (*x, 1)) < -128
1979 || INTVAL (XEXP (*x, 1)) > (128 - GET_MODE_SIZE (mode))))
1981 /* reload FB to A_REGS */
1982 rtx temp = gen_reg_rtx (Pmode);
1984 emit_insn (gen_rtx_SET (VOIDmode, temp, XEXP (*x, 0)));
1985 XEXP (*x, 0) = temp;
1992 /* Implements LEGITIMIZE_RELOAD_ADDRESS. See comment above. */
1994 m32c_legitimize_reload_address (rtx * x,
1995 enum machine_mode mode,
1997 int type, int ind_levels ATTRIBUTE_UNUSED)
2000 fprintf (stderr, "\nm32c_legitimize_reload_address for mode %s\n",
2005 /* At one point, this function tried to get $fb copied to an address
2006 register, which in theory would maximize sharing, but gcc was
2007 *also* still trying to reload the whole address, and we'd run out
2008 of address registers. So we let gcc do the naive (but safe)
2009 reload instead, when the above function doesn't handle it for
2012 The code below is a second attempt at the above. */
2014 if (GET_CODE (*x) == PLUS
2015 && GET_CODE (XEXP (*x, 0)) == REG
2016 && REGNO (XEXP (*x, 0)) == FB_REGNO
2017 && GET_CODE (XEXP (*x, 1)) == CONST_INT
2018 && (INTVAL (XEXP (*x, 1)) < -128
2019 || INTVAL (XEXP (*x, 1)) > (128 - GET_MODE_SIZE (mode))))
2022 int offset = INTVAL (XEXP (*x, 1));
2023 int adjustment = -BIG_FB_ADJ;
2025 sum = gen_rtx_PLUS (Pmode, XEXP (*x, 0),
2026 GEN_INT (adjustment));
2027 *x = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - adjustment));
2028 if (type == RELOAD_OTHER)
2029 type = RELOAD_FOR_OTHER_ADDRESS;
2030 push_reload (sum, NULL_RTX, &XEXP (*x, 0), NULL,
2031 A_REGS, Pmode, VOIDmode, 0, 0, opnum,
2036 if (GET_CODE (*x) == PLUS
2037 && GET_CODE (XEXP (*x, 0)) == PLUS
2038 && GET_CODE (XEXP (XEXP (*x, 0), 0)) == REG
2039 && REGNO (XEXP (XEXP (*x, 0), 0)) == FB_REGNO
2040 && GET_CODE (XEXP (XEXP (*x, 0), 1)) == CONST_INT
2041 && GET_CODE (XEXP (*x, 1)) == CONST_INT
2044 if (type == RELOAD_OTHER)
2045 type = RELOAD_FOR_OTHER_ADDRESS;
2046 push_reload (XEXP (*x, 0), NULL_RTX, &XEXP (*x, 0), NULL,
2047 A_REGS, Pmode, VOIDmode, 0, 0, opnum,
2055 /* Implements LEGITIMATE_CONSTANT_P. We split large constants anyway,
2056 so we can allow anything. */
2058 m32c_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED)
2064 /* Condition Code Status */
2066 #undef TARGET_FIXED_CONDITION_CODE_REGS
2067 #define TARGET_FIXED_CONDITION_CODE_REGS m32c_fixed_condition_code_regs
2069 m32c_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
2072 *p2 = INVALID_REGNUM;
2076 /* Describing Relative Costs of Operations */
2078 /* Implements REGISTER_MOVE_COST. We make impossible moves
2079 prohibitively expensive, like trying to put QIs in r2/r3 (there are
2080 no opcodes to do that). We also discourage use of mem* registers
2081 since they're really memory. */
2083 m32c_register_move_cost (enum machine_mode mode, int from, int to)
2085 int cost = COSTS_N_INSNS (3);
2086 int cc = class_contents[from][0] | class_contents[to][0];
2087 /* FIXME: pick real values, but not 2 for now. */
2088 if (mode == QImode && (cc & class_contents[R23_REGS][0]))
2090 if (!(cc & ~class_contents[R23_REGS][0]))
2091 cost = COSTS_N_INSNS (1000);
2093 cost = COSTS_N_INSNS (80);
2096 if (!class_can_hold_mode (from, mode) || !class_can_hold_mode (to, mode))
2097 cost = COSTS_N_INSNS (1000);
2099 if (classes_intersect (from, CR_REGS))
2100 cost += COSTS_N_INSNS (5);
2102 if (classes_intersect (to, CR_REGS))
2103 cost += COSTS_N_INSNS (5);
2105 if (from == MEM_REGS || to == MEM_REGS)
2106 cost += COSTS_N_INSNS (50);
2107 else if (classes_intersect (from, MEM_REGS)
2108 || classes_intersect (to, MEM_REGS))
2109 cost += COSTS_N_INSNS (10);
2112 fprintf (stderr, "register_move_cost %s from %s to %s = %d\n",
2113 mode_name[mode], class_names[from], class_names[to], cost);
2118 /* Implements MEMORY_MOVE_COST. */
2120 m32c_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2121 int reg_class ATTRIBUTE_UNUSED,
2122 int in ATTRIBUTE_UNUSED)
2124 /* FIXME: pick real values. */
2125 return COSTS_N_INSNS (10);
2128 /* Here we try to describe when we use multiple opcodes for one RTX so
2129 that gcc knows when to use them. */
2130 #undef TARGET_RTX_COSTS
2131 #define TARGET_RTX_COSTS m32c_rtx_costs
2133 m32c_rtx_costs (rtx x, int code, int outer_code, int *total)
2138 if (REGNO (x) >= MEM0_REGNO && REGNO (x) <= MEM7_REGNO)
2139 *total += COSTS_N_INSNS (500);
2141 *total += COSTS_N_INSNS (1);
2147 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2149 /* mov.b r1l, r1h */
2150 *total += COSTS_N_INSNS (1);
2153 if (INTVAL (XEXP (x, 1)) > 8
2154 || INTVAL (XEXP (x, 1)) < -8)
2157 /* mov.b r1l, r1h */
2158 *total += COSTS_N_INSNS (2);
2173 if (outer_code == SET)
2175 *total += COSTS_N_INSNS (2);
2182 rtx dest = XEXP (x, 0);
2183 rtx addr = XEXP (dest, 0);
2184 switch (GET_CODE (addr))
2187 *total += COSTS_N_INSNS (1);
2190 *total += COSTS_N_INSNS (3);
2193 *total += COSTS_N_INSNS (2);
2201 /* Reasonable default. */
2202 if (TARGET_A16 && GET_MODE(x) == SImode)
2203 *total += COSTS_N_INSNS (2);
2209 #undef TARGET_ADDRESS_COST
2210 #define TARGET_ADDRESS_COST m32c_address_cost
2212 m32c_address_cost (rtx addr)
2215 /* fprintf(stderr, "\naddress_cost\n");
2217 switch (GET_CODE (addr))
2222 return COSTS_N_INSNS(1);
2223 if (0 < i && i <= 255)
2224 return COSTS_N_INSNS(2);
2225 if (0 < i && i <= 65535)
2226 return COSTS_N_INSNS(3);
2227 return COSTS_N_INSNS(4);
2229 return COSTS_N_INSNS(4);
2231 return COSTS_N_INSNS(1);
2233 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2235 i = INTVAL (XEXP (addr, 1));
2237 return COSTS_N_INSNS(1);
2238 if (0 < i && i <= 255)
2239 return COSTS_N_INSNS(2);
2240 if (0 < i && i <= 65535)
2241 return COSTS_N_INSNS(3);
2243 return COSTS_N_INSNS(4);
2249 /* Defining the Output Assembler Language */
2251 /* The Overall Framework of an Assembler File */
2253 #undef TARGET_HAVE_NAMED_SECTIONS
2254 #define TARGET_HAVE_NAMED_SECTIONS true
2256 /* Output of Data */
2258 /* We may have 24 bit sizes, which is the native address size.
2259 Currently unused, but provided for completeness. */
2260 #undef TARGET_ASM_INTEGER
2261 #define TARGET_ASM_INTEGER m32c_asm_integer
2263 m32c_asm_integer (rtx x, unsigned int size, int aligned_p)
2268 fprintf (asm_out_file, "\t.3byte\t");
2269 output_addr_const (asm_out_file, x);
2270 fputc ('\n', asm_out_file);
2273 if (GET_CODE (x) == SYMBOL_REF)
2275 fprintf (asm_out_file, "\t.long\t");
2276 output_addr_const (asm_out_file, x);
2277 fputc ('\n', asm_out_file);
2282 return default_assemble_integer (x, size, aligned_p);
2285 /* Output of Assembler Instructions */
2287 /* We use a lookup table because the addressing modes are non-orthogonal. */
2292 char const *pattern;
2295 const conversions[] = {
2298 { 0, "mr", "z[1]" },
2299 { 0, "m+ri", "3[2]" },
2300 { 0, "m+rs", "3[2]" },
2301 { 0, "m+r+si", "4+5[2]" },
2304 { 0, "m+si", "2+3" },
2306 { 0, "mmr", "[z[2]]" },
2307 { 0, "mm+ri", "[4[3]]" },
2308 { 0, "mm+rs", "[4[3]]" },
2309 { 0, "mm+r+si", "[5+6[3]]" },
2310 { 0, "mms", "[[2]]" },
2311 { 0, "mmi", "[[2]]" },
2312 { 0, "mm+si", "[4[3]]" },
2316 { 0, "+si", "#1+2" },
2322 { 'd', "+si", "1+2" },
2325 { 'D', "+si", "1+2" },
2336 /* This is in order according to the bitfield that pushm/popm use. */
2337 static char const *pushm_regs[] = {
2338 "fb", "sb", "a1", "a0", "r3", "r2", "r1", "r0"
2341 /* Implements PRINT_OPERAND. */
2343 m32c_print_operand (FILE * file, rtx x, int code)
2348 int unsigned_const = 0;
2351 /* Multiplies; constants are converted to sign-extended format but
2352 we need unsigned, so 'u' and 'U' tell us what size unsigned we
2364 /* This one is only for debugging; you can put it in a pattern to
2365 force this error. */
2368 fprintf (stderr, "dj: unreviewed pattern:");
2369 if (current_output_insn)
2370 debug_rtx (current_output_insn);
2373 /* PSImode operations are either .w or .l depending on the target. */
2377 fprintf (file, "w");
2379 fprintf (file, "l");
2382 /* Inverted conditionals. */
2385 switch (GET_CODE (x))
2391 fputs ("gtu", file);
2397 fputs ("geu", file);
2403 fputs ("leu", file);
2409 fputs ("ltu", file);
2422 /* Regular conditionals. */
2425 switch (GET_CODE (x))
2431 fputs ("leu", file);
2437 fputs ("ltu", file);
2443 fputs ("gtu", file);
2449 fputs ("geu", file);
2462 /* Used in negsi2 to do HImode ops on the two parts of an SImode
2464 if (code == 'h' && GET_MODE (x) == SImode)
2466 x = m32c_subreg (HImode, x, SImode, 0);
2469 if (code == 'H' && GET_MODE (x) == SImode)
2471 x = m32c_subreg (HImode, x, SImode, 2);
2474 if (code == 'h' && GET_MODE (x) == HImode)
2476 x = m32c_subreg (QImode, x, HImode, 0);
2479 if (code == 'H' && GET_MODE (x) == HImode)
2481 /* We can't actually represent this as an rtx. Do it here. */
2482 if (GET_CODE (x) == REG)
2487 fputs ("r0h", file);
2490 fputs ("r1h", file);
2496 /* This should be a MEM. */
2497 x = m32c_subreg (QImode, x, HImode, 1);
2500 /* This is for BMcond, which always wants word register names. */
2501 if (code == 'h' && GET_MODE (x) == QImode)
2503 if (GET_CODE (x) == REG)
2504 x = gen_rtx_REG (HImode, REGNO (x));
2507 /* 'x' and 'X' need to be ignored for non-immediates. */
2508 if ((code == 'x' || code == 'X') && GET_CODE (x) != CONST_INT)
2513 for (i = 0; conversions[i].pattern; i++)
2514 if (conversions[i].code == code
2515 && streq (conversions[i].pattern, pattern))
2517 for (j = 0; conversions[i].format[j]; j++)
2518 /* backslash quotes the next character in the output pattern. */
2519 if (conversions[i].format[j] == '\\')
2521 fputc (conversions[i].format[j + 1], file);
2524 /* Digits in the output pattern indicate that the
2525 corresponding RTX is to be output at that point. */
2526 else if (ISDIGIT (conversions[i].format[j]))
2528 rtx r = patternr[conversions[i].format[j] - '0'];
2529 switch (GET_CODE (r))
2532 fprintf (file, "%s",
2533 reg_name_with_mode (REGNO (r), GET_MODE (r)));
2542 int i = (int) exact_log2 (v);
2544 i = (int) exact_log2 ((v ^ 0xffff) & 0xffff);
2546 i = (int) exact_log2 ((v ^ 0xff) & 0xff);
2548 fprintf (file, "%d", i);
2552 /* Unsigned byte. */
2553 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2557 /* Unsigned word. */
2558 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2559 INTVAL (r) & 0xffff);
2562 /* pushm and popm encode a register set into a single byte. */
2564 for (b = 7; b >= 0; b--)
2565 if (INTVAL (r) & (1 << b))
2567 fprintf (file, "%s%s", comma, pushm_regs[b]);
2572 /* "Minus". Output -X */
2573 ival = (-INTVAL (r) & 0xffff);
2575 ival = ival - 0x10000;
2576 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
2580 if (conversions[i].format[j + 1] == '[' && ival < 0)
2582 /* We can simulate negative displacements by
2583 taking advantage of address space
2584 wrapping when the offset can span the
2585 entire address range. */
2587 patternr[conversions[i].format[j + 2] - '0'];
2588 if (GET_CODE (base) == REG)
2589 switch (REGNO (base))
2594 ival = 0x1000000 + ival;
2596 ival = 0x10000 + ival;
2600 ival = 0x10000 + ival;
2604 else if (code == 'd' && ival < 0 && j == 0)
2605 /* The "mova" opcode is used to do addition by
2606 computing displacements, but again, we need
2607 displacements to be unsigned *if* they're
2608 the only component of the displacement
2609 (i.e. no "symbol-4" type displacement). */
2610 ival = (TARGET_A24 ? 0x1000000 : 0x10000) + ival;
2612 if (conversions[i].format[j] == '0')
2614 /* More conversions to unsigned. */
2615 if (unsigned_const == 2)
2617 if (unsigned_const == 1)
2620 if (streq (conversions[i].pattern, "mi")
2621 || streq (conversions[i].pattern, "mmi"))
2623 /* Integers used as addresses are unsigned. */
2624 ival &= (TARGET_A24 ? 0xffffff : 0xffff);
2626 if (force_sign && ival >= 0)
2628 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
2633 /* We don't have const_double constants. If it
2634 happens, make it obvious. */
2635 fprintf (file, "[const_double 0x%lx]",
2636 (unsigned long) CONST_DOUBLE_HIGH (r));
2639 assemble_name (file, XSTR (r, 0));
2642 output_asm_label (r);
2645 fprintf (stderr, "don't know how to print this operand:");
2652 if (conversions[i].format[j] == 'z')
2654 /* Some addressing modes *must* have a displacement,
2655 so insert a zero here if needed. */
2657 for (k = j + 1; conversions[i].format[k]; k++)
2658 if (ISDIGIT (conversions[i].format[k]))
2660 rtx reg = patternr[conversions[i].format[k] - '0'];
2661 if (GET_CODE (reg) == REG
2662 && (REGNO (reg) == SB_REGNO
2663 || REGNO (reg) == FB_REGNO
2664 || REGNO (reg) == SP_REGNO))
2669 /* Signed displacements off symbols need to have signs
2671 if (conversions[i].format[j] == '+'
2672 && (!code || code == 'D' || code == 'd')
2673 && ISDIGIT (conversions[i].format[j + 1])
2674 && (GET_CODE (patternr[conversions[i].format[j + 1] - '0'])
2680 fputc (conversions[i].format[j], file);
2684 if (!conversions[i].pattern)
2686 fprintf (stderr, "unconvertible operand %c `%s'", code ? code : '-',
2689 fprintf (file, "[%c.%s]", code ? code : '-', pattern);
2695 /* Implements PRINT_OPERAND_PUNCT_VALID_P. See m32c_print_operand
2696 above for descriptions of what these do. */
2698 m32c_print_operand_punct_valid_p (int c)
2700 if (c == '&' || c == '!')
2705 /* Implements PRINT_OPERAND_ADDRESS. Nothing unusual here. */
2707 m32c_print_operand_address (FILE * stream, rtx address)
2709 gcc_assert (GET_CODE (address) == MEM);
2710 m32c_print_operand (stream, XEXP (address, 0), 0);
2713 /* Implements ASM_OUTPUT_REG_PUSH. Control registers are pushed
2714 differently than general registers. */
2716 m32c_output_reg_push (FILE * s, int regno)
2718 if (regno == FLG_REGNO)
2719 fprintf (s, "\tpushc\tflg\n");
2721 fprintf (s, "\tpush.%c\t%s\n",
2722 " bwll"[reg_push_size (regno)], reg_names[regno]);
2725 /* Likewise for ASM_OUTPUT_REG_POP. */
2727 m32c_output_reg_pop (FILE * s, int regno)
2729 if (regno == FLG_REGNO)
2730 fprintf (s, "\tpopc\tflg\n");
2732 fprintf (s, "\tpop.%c\t%s\n",
2733 " bwll"[reg_push_size (regno)], reg_names[regno]);
2736 /* Defining target-specific uses of `__attribute__' */
2738 /* Used to simplify the logic below. Find the attributes wherever
2740 #define M32C_ATTRIBUTES(decl) \
2741 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
2742 : DECL_ATTRIBUTES (decl) \
2743 ? (DECL_ATTRIBUTES (decl)) \
2744 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
2746 /* Returns TRUE if the given tree has the "interrupt" attribute. */
2748 interrupt_p (tree node ATTRIBUTE_UNUSED)
2750 tree list = M32C_ATTRIBUTES (node);
2753 if (is_attribute_p ("interrupt", TREE_PURPOSE (list)))
2755 list = TREE_CHAIN (list);
2761 interrupt_handler (tree * node ATTRIBUTE_UNUSED,
2762 tree name ATTRIBUTE_UNUSED,
2763 tree args ATTRIBUTE_UNUSED,
2764 int flags ATTRIBUTE_UNUSED,
2765 bool * no_add_attrs ATTRIBUTE_UNUSED)
2770 /* Returns TRUE if given tree has the "function_vector" attribute. */
2772 m32c_special_page_vector_p (tree func)
2774 if (TREE_CODE (func) != FUNCTION_DECL)
2777 tree list = M32C_ATTRIBUTES (func);
2780 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
2782 list = TREE_CHAIN (list);
2788 function_vector_handler (tree * node ATTRIBUTE_UNUSED,
2789 tree name ATTRIBUTE_UNUSED,
2790 tree args ATTRIBUTE_UNUSED,
2791 int flags ATTRIBUTE_UNUSED,
2792 bool * no_add_attrs ATTRIBUTE_UNUSED)
2796 /* The attribute is not supported for R8C target. */
2797 warning (OPT_Wattributes,
2798 "`%s' attribute is not supported for R8C target",
2799 IDENTIFIER_POINTER (name));
2800 *no_add_attrs = true;
2802 else if (TREE_CODE (*node) != FUNCTION_DECL)
2804 /* The attribute must be applied to functions only. */
2805 warning (OPT_Wattributes,
2806 "`%s' attribute applies only to functions",
2807 IDENTIFIER_POINTER (name));
2808 *no_add_attrs = true;
2810 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
2812 /* The argument must be a constant integer. */
2813 warning (OPT_Wattributes,
2814 "`%s' attribute argument not an integer constant",
2815 IDENTIFIER_POINTER (name));
2816 *no_add_attrs = true;
2818 else if (TREE_INT_CST_LOW (TREE_VALUE (args)) < 18
2819 || TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
2821 /* The argument value must be between 18 to 255. */
2822 warning (OPT_Wattributes,
2823 "`%s' attribute argument should be between 18 to 255",
2824 IDENTIFIER_POINTER (name));
2825 *no_add_attrs = true;
2830 /* If the function is assigned the attribute 'function_vector', it
2831 returns the function vector number, otherwise returns zero. */
2833 current_function_special_page_vector (rtx x)
2837 if ((GET_CODE(x) == SYMBOL_REF)
2838 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
2840 tree t = SYMBOL_REF_DECL (x);
2842 if (TREE_CODE (t) != FUNCTION_DECL)
2845 tree list = M32C_ATTRIBUTES (t);
2848 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
2850 num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
2854 list = TREE_CHAIN (list);
2863 #undef TARGET_ATTRIBUTE_TABLE
2864 #define TARGET_ATTRIBUTE_TABLE m32c_attribute_table
2865 static const struct attribute_spec m32c_attribute_table[] = {
2866 {"interrupt", 0, 0, false, false, false, interrupt_handler},
2867 {"function_vector", 1, 1, true, false, false, function_vector_handler},
2868 {0, 0, 0, 0, 0, 0, 0}
2871 #undef TARGET_COMP_TYPE_ATTRIBUTES
2872 #define TARGET_COMP_TYPE_ATTRIBUTES m32c_comp_type_attributes
2874 m32c_comp_type_attributes (const_tree type1 ATTRIBUTE_UNUSED,
2875 const_tree type2 ATTRIBUTE_UNUSED)
2877 /* 0=incompatible 1=compatible 2=warning */
2881 #undef TARGET_INSERT_ATTRIBUTES
2882 #define TARGET_INSERT_ATTRIBUTES m32c_insert_attributes
2884 m32c_insert_attributes (tree node ATTRIBUTE_UNUSED,
2885 tree * attr_ptr ATTRIBUTE_UNUSED)
2887 /* Nothing to do here. */
2892 /* This is a list of legal subregs of hard regs. */
2893 static const struct {
2894 unsigned char outer_mode_size;
2895 unsigned char inner_mode_size;
2896 unsigned char byte_mask;
2897 unsigned char legal_when;
2899 } legal_subregs[] = {
2900 {1, 2, 0x03, 1, R0_REGNO}, /* r0h r0l */
2901 {1, 2, 0x03, 1, R1_REGNO}, /* r1h r1l */
2902 {1, 2, 0x01, 1, A0_REGNO},
2903 {1, 2, 0x01, 1, A1_REGNO},
2905 {1, 4, 0x01, 1, A0_REGNO},
2906 {1, 4, 0x01, 1, A1_REGNO},
2908 {2, 4, 0x05, 1, R0_REGNO}, /* r2 r0 */
2909 {2, 4, 0x05, 1, R1_REGNO}, /* r3 r1 */
2910 {2, 4, 0x05, 16, A0_REGNO}, /* a1 a0 */
2911 {2, 4, 0x01, 24, A0_REGNO}, /* a1 a0 */
2912 {2, 4, 0x01, 24, A1_REGNO}, /* a1 a0 */
2914 {4, 8, 0x55, 1, R0_REGNO}, /* r3 r1 r2 r0 */
2917 /* Returns TRUE if OP is a subreg of a hard reg which we don't
2920 m32c_illegal_subreg_p (rtx op)
2924 int src_mode, dest_mode;
2926 if (GET_CODE (op) != SUBREG)
2929 dest_mode = GET_MODE (op);
2930 offset = SUBREG_BYTE (op);
2931 op = SUBREG_REG (op);
2932 src_mode = GET_MODE (op);
2934 if (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (src_mode))
2936 if (GET_CODE (op) != REG)
2938 if (REGNO (op) >= MEM0_REGNO)
2941 offset = (1 << offset);
2943 for (i = 0; i < ARRAY_SIZE (legal_subregs); i ++)
2944 if (legal_subregs[i].outer_mode_size == GET_MODE_SIZE (dest_mode)
2945 && legal_subregs[i].regno == REGNO (op)
2946 && legal_subregs[i].inner_mode_size == GET_MODE_SIZE (src_mode)
2947 && legal_subregs[i].byte_mask & offset)
2949 switch (legal_subregs[i].legal_when)
2966 /* Returns TRUE if we support a move between the first two operands.
2967 At the moment, we just want to discourage mem to mem moves until
2968 after reload, because reload has a hard time with our limited
2969 number of address registers, and we can get into a situation where
2970 we need three of them when we only have two. */
2972 m32c_mov_ok (rtx * operands, enum machine_mode mode ATTRIBUTE_UNUSED)
2974 rtx op0 = operands[0];
2975 rtx op1 = operands[1];
2980 #define DEBUG_MOV_OK 0
2982 fprintf (stderr, "m32c_mov_ok %s\n", mode_name[mode]);
2987 if (GET_CODE (op0) == SUBREG)
2988 op0 = XEXP (op0, 0);
2989 if (GET_CODE (op1) == SUBREG)
2990 op1 = XEXP (op1, 0);
2992 if (GET_CODE (op0) == MEM
2993 && GET_CODE (op1) == MEM
2994 && ! reload_completed)
2997 fprintf (stderr, " - no, mem to mem\n");
3003 fprintf (stderr, " - ok\n");
3008 /* Returns TRUE if two consecutive HImode mov instructions, generated
3009 for moving an immediate double data to a double data type variable
3010 location, can be combined into single SImode mov instruction. */
3012 m32c_immd_dbl_mov (rtx * operands,
3013 enum machine_mode mode ATTRIBUTE_UNUSED)
3015 int flag = 0, okflag = 0, offset1 = 0, offset2 = 0, offsetsign = 0;
3019 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
3020 && MEM_SCALAR_P (operands[0])
3021 && !MEM_IN_STRUCT_P (operands[0])
3022 && GET_CODE (XEXP (operands[2], 0)) == CONST
3023 && GET_CODE (XEXP (XEXP (operands[2], 0), 0)) == PLUS
3024 && GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 0)) == SYMBOL_REF
3025 && GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 1)) == CONST_INT
3026 && MEM_SCALAR_P (operands[2])
3027 && !MEM_IN_STRUCT_P (operands[2]))
3030 else if (GET_CODE (XEXP (operands[0], 0)) == CONST
3031 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == PLUS
3032 && GET_CODE (XEXP (XEXP (XEXP (operands[0], 0), 0), 0)) == SYMBOL_REF
3033 && MEM_SCALAR_P (operands[0])
3034 && !MEM_IN_STRUCT_P (operands[0])
3035 && !(INTVAL (XEXP (XEXP (XEXP (operands[0], 0), 0), 1)) %4)
3036 && GET_CODE (XEXP (operands[2], 0)) == CONST
3037 && GET_CODE (XEXP (XEXP (operands[2], 0), 0)) == PLUS
3038 && GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 0)) == SYMBOL_REF
3039 && MEM_SCALAR_P (operands[2])
3040 && !MEM_IN_STRUCT_P (operands[2]))
3043 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
3044 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
3045 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == FB_REGNO
3046 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT
3047 && MEM_SCALAR_P (operands[0])
3048 && !MEM_IN_STRUCT_P (operands[0])
3049 && !(INTVAL (XEXP (XEXP (operands[0], 0), 1)) %4)
3050 && REGNO (XEXP (XEXP (operands[2], 0), 0)) == FB_REGNO
3051 && GET_CODE (XEXP (XEXP (operands[2], 0), 1)) == CONST_INT
3052 && MEM_SCALAR_P (operands[2])
3053 && !MEM_IN_STRUCT_P (operands[2]))
3062 str1 = XSTR (XEXP (operands[0], 0), 0);
3063 str2 = XSTR (XEXP (XEXP (XEXP (operands[2], 0), 0), 0), 0);
3064 if (strcmp (str1, str2) == 0)
3070 str1 = XSTR (XEXP (XEXP (XEXP (operands[0], 0), 0), 0), 0);
3071 str2 = XSTR (XEXP (XEXP (XEXP (operands[2], 0), 0), 0), 0);
3072 if (strcmp(str1,str2) == 0)
3078 offset1 = INTVAL (XEXP (XEXP (operands[0], 0), 1));
3079 offset2 = INTVAL (XEXP (XEXP (operands[2], 0), 1));
3080 offsetsign = offset1 >> ((sizeof (offset1) * 8) -1);
3081 if (((offset2-offset1) == 2) && offsetsign != 0)
3093 operands[4] = gen_rtx_MEM (SImode, XEXP (operands[0], 0));
3095 val = (INTVAL (operands[3]) << 16) + (INTVAL (operands[1]) & 0xFFFF);
3096 operands[5] = gen_rtx_CONST_INT (VOIDmode, val);
3106 /* Subregs are non-orthogonal for us, because our registers are all
3109 m32c_subreg (enum machine_mode outer,
3110 rtx x, enum machine_mode inner, int byte)
3114 /* Converting MEMs to different types that are the same size, we
3115 just rewrite them. */
3116 if (GET_CODE (x) == SUBREG
3117 && SUBREG_BYTE (x) == 0
3118 && GET_CODE (SUBREG_REG (x)) == MEM
3119 && (GET_MODE_SIZE (GET_MODE (x))
3120 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3123 x = gen_rtx_MEM (GET_MODE (x), XEXP (SUBREG_REG (x), 0));
3124 MEM_COPY_ATTRIBUTES (x, SUBREG_REG (oldx));
3127 /* Push/pop get done as smaller push/pops. */
3128 if (GET_CODE (x) == MEM
3129 && (GET_CODE (XEXP (x, 0)) == PRE_DEC
3130 || GET_CODE (XEXP (x, 0)) == POST_INC))
3131 return gen_rtx_MEM (outer, XEXP (x, 0));
3132 if (GET_CODE (x) == SUBREG
3133 && GET_CODE (XEXP (x, 0)) == MEM
3134 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == PRE_DEC
3135 || GET_CODE (XEXP (XEXP (x, 0), 0)) == POST_INC))
3136 return gen_rtx_MEM (outer, XEXP (XEXP (x, 0), 0));
3138 if (GET_CODE (x) != REG)
3139 return simplify_gen_subreg (outer, x, inner, byte);
3142 if (r >= FIRST_PSEUDO_REGISTER || r == AP_REGNO)
3143 return simplify_gen_subreg (outer, x, inner, byte);
3145 if (IS_MEM_REGNO (r))
3146 return simplify_gen_subreg (outer, x, inner, byte);
3148 /* This is where the complexities of our register layout are
3152 else if (outer == HImode)
3154 if (r == R0_REGNO && byte == 2)
3156 else if (r == R0_REGNO && byte == 4)
3158 else if (r == R0_REGNO && byte == 6)
3160 else if (r == R1_REGNO && byte == 2)
3162 else if (r == A0_REGNO && byte == 2)
3165 else if (outer == SImode)
3167 if (r == R0_REGNO && byte == 0)
3169 else if (r == R0_REGNO && byte == 4)
3174 fprintf (stderr, "m32c_subreg %s %s %d\n",
3175 mode_name[outer], mode_name[inner], byte);
3179 return gen_rtx_REG (outer, nr);
3182 /* Used to emit move instructions. We split some moves,
3183 and avoid mem-mem moves. */
3185 m32c_prepare_move (rtx * operands, enum machine_mode mode)
3187 if (TARGET_A16 && mode == PSImode)
3188 return m32c_split_move (operands, mode, 1);
3189 if ((GET_CODE (operands[0]) == MEM)
3190 && (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY))
3192 rtx pmv = XEXP (operands[0], 0);
3193 rtx dest_reg = XEXP (pmv, 0);
3194 rtx dest_mod = XEXP (pmv, 1);
3196 emit_insn (gen_rtx_SET (Pmode, dest_reg, dest_mod));
3197 operands[0] = gen_rtx_MEM (mode, dest_reg);
3199 if (can_create_pseudo_p () && MEM_P (operands[0]) && MEM_P (operands[1]))
3200 operands[1] = copy_to_mode_reg (mode, operands[1]);
3204 #define DEBUG_SPLIT 0
3206 /* Returns TRUE if the given PSImode move should be split. We split
3207 for all r8c/m16c moves, since it doesn't support them, and for
3208 POP.L as we can only *push* SImode. */
3210 m32c_split_psi_p (rtx * operands)
3213 fprintf (stderr, "\nm32c_split_psi_p\n");
3214 debug_rtx (operands[0]);
3215 debug_rtx (operands[1]);
3220 fprintf (stderr, "yes, A16\n");
3224 if (GET_CODE (operands[1]) == MEM
3225 && GET_CODE (XEXP (operands[1], 0)) == POST_INC)
3228 fprintf (stderr, "yes, pop.l\n");
3233 fprintf (stderr, "no, default\n");
3238 /* Split the given move. SPLIT_ALL is 0 if splitting is optional
3239 (define_expand), 1 if it is not optional (define_insn_and_split),
3240 and 3 for define_split (alternate api). */
3242 m32c_split_move (rtx * operands, enum machine_mode mode, int split_all)
3245 int parts, si, di, rev = 0;
3246 int rv = 0, opi = 2;
3247 enum machine_mode submode = HImode;
3248 rtx *ops, local_ops[10];
3250 /* define_split modifies the existing operands, but the other two
3251 emit new insns. OPS is where we store the operand pairs, which
3262 /* Before splitting mem-mem moves, force one operand into a
3264 if (can_create_pseudo_p () && MEM_P (operands[0]) && MEM_P (operands[1]))
3267 fprintf (stderr, "force_reg...\n");
3268 debug_rtx (operands[1]);
3270 operands[1] = force_reg (mode, operands[1]);
3272 debug_rtx (operands[1]);
3279 fprintf (stderr, "\nsplit_move %d all=%d\n", !can_create_pseudo_p (),
3281 debug_rtx (operands[0]);
3282 debug_rtx (operands[1]);
3285 /* Note that split_all is not used to select the api after this
3286 point, so it's safe to set it to 3 even with define_insn. */
3287 /* None of the chips can move SI operands to sp-relative addresses,
3288 so we always split those. */
3289 if (m32c_extra_constraint_p (operands[0], 'S', "Ss"))
3292 /* We don't need to split these. */
3295 && (mode == SImode || mode == PSImode)
3296 && !(GET_CODE (operands[1]) == MEM
3297 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
3300 /* First, enumerate the subregs we'll be dealing with. */
3301 for (si = 0; si < parts; si++)
3304 m32c_subreg (submode, operands[0], mode,
3305 si * GET_MODE_SIZE (submode));
3307 m32c_subreg (submode, operands[1], mode,
3308 si * GET_MODE_SIZE (submode));
3311 /* Split pushes by emitting a sequence of smaller pushes. */
3312 if (GET_CODE (d[0]) == MEM && GET_CODE (XEXP (d[0], 0)) == PRE_DEC)
3314 for (si = parts - 1; si >= 0; si--)
3316 ops[opi++] = gen_rtx_MEM (submode,
3317 gen_rtx_PRE_DEC (Pmode,
3325 /* Likewise for pops. */
3326 else if (GET_CODE (s[0]) == MEM && GET_CODE (XEXP (s[0], 0)) == POST_INC)
3328 for (di = 0; di < parts; di++)
3331 ops[opi++] = gen_rtx_MEM (submode,
3332 gen_rtx_POST_INC (Pmode,
3340 /* if d[di] == s[si] for any di < si, we'll early clobber. */
3341 for (di = 0; di < parts - 1; di++)
3342 for (si = di + 1; si < parts; si++)
3343 if (reg_mentioned_p (d[di], s[si]))
3347 for (si = 0; si < parts; si++)
3353 for (si = parts - 1; si >= 0; si--)
3360 /* Now emit any moves we may have accumulated. */
3361 if (rv && split_all != 3)
3364 for (i = 2; i < opi; i += 2)
3365 emit_move_insn (ops[i], ops[i + 1]);
3370 /* The m32c has a number of opcodes that act like memcpy, strcmp, and
3371 the like. For the R8C they expect one of the addresses to be in
3372 R1L:An so we need to arrange for that. Otherwise, it's just a
3373 matter of picking out the operands we want and emitting the right
3374 pattern for them. All these expanders, which correspond to
3375 patterns in blkmov.md, must return nonzero if they expand the insn,
3376 or zero if they should FAIL. */
3378 /* This is a memset() opcode. All operands are implied, so we need to
3379 arrange for them to be in the right registers. The opcode wants
3380 addresses, not [mem] syntax. $0 is the destination (MEM:BLK), $1
3381 the count (HI), and $2 the value (QI). */
3383 m32c_expand_setmemhi(rtx *operands)
3385 rtx desta, count, val;
3388 desta = XEXP (operands[0], 0);
3389 count = operands[1];
3392 desto = gen_reg_rtx (Pmode);
3393 counto = gen_reg_rtx (HImode);
3395 if (GET_CODE (desta) != REG
3396 || REGNO (desta) < FIRST_PSEUDO_REGISTER)
3397 desta = copy_to_mode_reg (Pmode, desta);
3399 /* This looks like an arbitrary restriction, but this is by far the
3400 most common case. For counts 8..14 this actually results in
3401 smaller code with no speed penalty because the half-sized
3402 constant can be loaded with a shorter opcode. */
3403 if (GET_CODE (count) == CONST_INT
3404 && GET_CODE (val) == CONST_INT
3405 && ! (INTVAL (count) & 1)
3406 && (INTVAL (count) > 1)
3407 && (INTVAL (val) <= 7 && INTVAL (val) >= -8))
3409 unsigned v = INTVAL (val) & 0xff;
3411 count = copy_to_mode_reg (HImode, GEN_INT (INTVAL (count) / 2));
3412 val = copy_to_mode_reg (HImode, GEN_INT (v));
3414 emit_insn (gen_setmemhi_whi_op (desto, counto, val, desta, count));
3416 emit_insn (gen_setmemhi_wpsi_op (desto, counto, val, desta, count));
3420 /* This is the generalized memset() case. */
3421 if (GET_CODE (val) != REG
3422 || REGNO (val) < FIRST_PSEUDO_REGISTER)
3423 val = copy_to_mode_reg (QImode, val);
3425 if (GET_CODE (count) != REG
3426 || REGNO (count) < FIRST_PSEUDO_REGISTER)
3427 count = copy_to_mode_reg (HImode, count);
3430 emit_insn (gen_setmemhi_bhi_op (desto, counto, val, desta, count));
3432 emit_insn (gen_setmemhi_bpsi_op (desto, counto, val, desta, count));
3437 /* This is a memcpy() opcode. All operands are implied, so we need to
3438 arrange for them to be in the right registers. The opcode wants
3439 addresses, not [mem] syntax. $0 is the destination (MEM:BLK), $1
3440 is the source (MEM:BLK), and $2 the count (HI). */
3442 m32c_expand_movmemhi(rtx *operands)
3444 rtx desta, srca, count;
3445 rtx desto, srco, counto;
3447 desta = XEXP (operands[0], 0);
3448 srca = XEXP (operands[1], 0);
3449 count = operands[2];
3451 desto = gen_reg_rtx (Pmode);
3452 srco = gen_reg_rtx (Pmode);
3453 counto = gen_reg_rtx (HImode);
3455 if (GET_CODE (desta) != REG
3456 || REGNO (desta) < FIRST_PSEUDO_REGISTER)
3457 desta = copy_to_mode_reg (Pmode, desta);
3459 if (GET_CODE (srca) != REG
3460 || REGNO (srca) < FIRST_PSEUDO_REGISTER)
3461 srca = copy_to_mode_reg (Pmode, srca);
3463 /* Similar to setmem, but we don't need to check the value. */
3464 if (GET_CODE (count) == CONST_INT
3465 && ! (INTVAL (count) & 1)
3466 && (INTVAL (count) > 1))
3468 count = copy_to_mode_reg (HImode, GEN_INT (INTVAL (count) / 2));
3470 emit_insn (gen_movmemhi_whi_op (desto, srco, counto, desta, srca, count));
3472 emit_insn (gen_movmemhi_wpsi_op (desto, srco, counto, desta, srca, count));
3476 /* This is the generalized memset() case. */
3477 if (GET_CODE (count) != REG
3478 || REGNO (count) < FIRST_PSEUDO_REGISTER)
3479 count = copy_to_mode_reg (HImode, count);
3482 emit_insn (gen_movmemhi_bhi_op (desto, srco, counto, desta, srca, count));
3484 emit_insn (gen_movmemhi_bpsi_op (desto, srco, counto, desta, srca, count));
3489 /* This is a stpcpy() opcode. $0 is the destination (MEM:BLK) after
3490 the copy, which should point to the NUL at the end of the string,
3491 $1 is the destination (MEM:BLK), and $2 is the source (MEM:BLK).
3492 Since our opcode leaves the destination pointing *after* the NUL,
3493 we must emit an adjustment. */
3495 m32c_expand_movstr(rtx *operands)
3500 desta = XEXP (operands[1], 0);
3501 srca = XEXP (operands[2], 0);
3503 desto = gen_reg_rtx (Pmode);
3504 srco = gen_reg_rtx (Pmode);
3506 if (GET_CODE (desta) != REG
3507 || REGNO (desta) < FIRST_PSEUDO_REGISTER)
3508 desta = copy_to_mode_reg (Pmode, desta);
3510 if (GET_CODE (srca) != REG
3511 || REGNO (srca) < FIRST_PSEUDO_REGISTER)
3512 srca = copy_to_mode_reg (Pmode, srca);
3514 emit_insn (gen_movstr_op (desto, srco, desta, srca));
3515 /* desto ends up being a1, which allows this type of add through MOVA. */
3516 emit_insn (gen_addpsi3 (operands[0], desto, GEN_INT (-1)));
3521 /* This is a strcmp() opcode. $0 is the destination (HI) which holds
3522 <=>0 depending on the comparison, $1 is one string (MEM:BLK), and
3523 $2 is the other (MEM:BLK). We must do the comparison, and then
3524 convert the flags to a signed integer result. */
3526 m32c_expand_cmpstr(rtx *operands)
3530 src1a = XEXP (operands[1], 0);
3531 src2a = XEXP (operands[2], 0);
3533 if (GET_CODE (src1a) != REG
3534 || REGNO (src1a) < FIRST_PSEUDO_REGISTER)
3535 src1a = copy_to_mode_reg (Pmode, src1a);
3537 if (GET_CODE (src2a) != REG
3538 || REGNO (src2a) < FIRST_PSEUDO_REGISTER)
3539 src2a = copy_to_mode_reg (Pmode, src2a);
3541 emit_insn (gen_cmpstrhi_op (src1a, src2a, src1a, src2a));
3542 emit_insn (gen_cond_to_int (operands[0]));
3548 typedef rtx (*shift_gen_func)(rtx, rtx, rtx);
3550 static shift_gen_func
3551 shift_gen_func_for (int mode, int code)
3553 #define GFF(m,c,f) if (mode == m && code == c) return f
3554 GFF(QImode, ASHIFT, gen_ashlqi3_i);
3555 GFF(QImode, ASHIFTRT, gen_ashrqi3_i);
3556 GFF(QImode, LSHIFTRT, gen_lshrqi3_i);
3557 GFF(HImode, ASHIFT, gen_ashlhi3_i);
3558 GFF(HImode, ASHIFTRT, gen_ashrhi3_i);
3559 GFF(HImode, LSHIFTRT, gen_lshrhi3_i);
3560 GFF(PSImode, ASHIFT, gen_ashlpsi3_i);
3561 GFF(PSImode, ASHIFTRT, gen_ashrpsi3_i);
3562 GFF(PSImode, LSHIFTRT, gen_lshrpsi3_i);
3563 GFF(SImode, ASHIFT, TARGET_A16 ? gen_ashlsi3_16 : gen_ashlsi3_24);
3564 GFF(SImode, ASHIFTRT, TARGET_A16 ? gen_ashrsi3_16 : gen_ashrsi3_24);
3565 GFF(SImode, LSHIFTRT, TARGET_A16 ? gen_lshrsi3_16 : gen_lshrsi3_24);
3570 /* The m32c only has one shift, but it takes a signed count. GCC
3571 doesn't want this, so we fake it by negating any shift count when
3572 we're pretending to shift the other way. Also, the shift count is
3573 limited to -8..8. It's slightly better to use two shifts for 9..15
3574 than to load the count into r1h, so we do that too. */
3576 m32c_prepare_shift (rtx * operands, int scale, int shift_code)
3578 enum machine_mode mode = GET_MODE (operands[0]);
3579 shift_gen_func func = shift_gen_func_for (mode, shift_code);
3582 if (GET_CODE (operands[2]) == CONST_INT)
3584 int maxc = TARGET_A24 && (mode == PSImode || mode == SImode) ? 32 : 8;
3585 int count = INTVAL (operands[2]) * scale;
3587 while (count > maxc)
3589 temp = gen_reg_rtx (mode);
3590 emit_insn (func (temp, operands[1], GEN_INT (maxc)));
3594 while (count < -maxc)
3596 temp = gen_reg_rtx (mode);
3597 emit_insn (func (temp, operands[1], GEN_INT (-maxc)));
3601 emit_insn (func (operands[0], operands[1], GEN_INT (count)));
3605 temp = gen_reg_rtx (QImode);
3607 /* The pattern has a NEG that corresponds to this. */
3608 emit_move_insn (temp, gen_rtx_NEG (QImode, operands[2]));
3609 else if (TARGET_A16 && mode == SImode)
3610 /* We do this because the code below may modify this, we don't
3611 want to modify the origin of this value. */
3612 emit_move_insn (temp, operands[2]);
3614 /* We'll only use it for the shift, no point emitting a move. */
3617 if (TARGET_A16 && GET_MODE_SIZE (mode) == 4)
3619 /* The m16c has a limit of -16..16 for SI shifts, even when the
3620 shift count is in a register. Since there are so many targets
3621 of these shifts, it's better to expand the RTL here than to
3622 call a helper function.
3624 The resulting code looks something like this:
3636 We take advantage of the fact that "negative" shifts are
3637 undefined to skip one of the comparisons. */
3640 rtx label, lref, insn, tempvar;
3642 emit_move_insn (operands[0], operands[1]);
3645 label = gen_label_rtx ();
3646 lref = gen_rtx_LABEL_REF (VOIDmode, label);
3647 LABEL_NUSES (label) ++;
3649 tempvar = gen_reg_rtx (mode);
3651 if (shift_code == ASHIFT)
3653 /* This is a left shift. We only need check positive counts. */
3654 emit_jump_insn (gen_cbranchqi4 (gen_rtx_LE (VOIDmode, 0, 0),
3655 count, GEN_INT (16), label));
3656 emit_insn (func (tempvar, operands[0], GEN_INT (8)));
3657 emit_insn (func (operands[0], tempvar, GEN_INT (8)));
3658 insn = emit_insn (gen_addqi3 (count, count, GEN_INT (-16)));
3659 emit_label_after (label, insn);
3663 /* This is a right shift. We only need check negative counts. */
3664 emit_jump_insn (gen_cbranchqi4 (gen_rtx_GE (VOIDmode, 0, 0),
3665 count, GEN_INT (-16), label));
3666 emit_insn (func (tempvar, operands[0], GEN_INT (-8)));
3667 emit_insn (func (operands[0], tempvar, GEN_INT (-8)));
3668 insn = emit_insn (gen_addqi3 (count, count, GEN_INT (16)));
3669 emit_label_after (label, insn);
3671 operands[1] = operands[0];
3672 emit_insn (func (operands[0], operands[0], count));
3680 /* The m32c has a limited range of operations that work on PSImode
3681 values; we have to expand to SI, do the math, and truncate back to
3682 PSI. Yes, this is expensive, but hopefully gcc will learn to avoid
3685 m32c_expand_neg_mulpsi3 (rtx * operands)
3687 /* operands: a = b * i */
3688 rtx temp1; /* b as SI */
3689 rtx scale /* i as SI */;
3690 rtx temp2; /* a*b as SI */
3692 temp1 = gen_reg_rtx (SImode);
3693 temp2 = gen_reg_rtx (SImode);
3694 if (GET_CODE (operands[2]) != CONST_INT)
3696 scale = gen_reg_rtx (SImode);
3697 emit_insn (gen_zero_extendpsisi2 (scale, operands[2]));
3700 scale = copy_to_mode_reg (SImode, operands[2]);
3702 emit_insn (gen_zero_extendpsisi2 (temp1, operands[1]));
3703 temp2 = expand_simple_binop (SImode, MULT, temp1, scale, temp2, 1, OPTAB_LIB);
3704 emit_insn (gen_truncsipsi2 (operands[0], temp2));
3707 static rtx compare_op0, compare_op1;
3710 m32c_pend_compare (rtx *operands)
3712 compare_op0 = operands[0];
3713 compare_op1 = operands[1];
3717 m32c_unpend_compare (void)
3719 switch (GET_MODE (compare_op0))
3722 emit_insn (gen_cmpqi_op (compare_op0, compare_op1));
3724 emit_insn (gen_cmphi_op (compare_op0, compare_op1));
3726 emit_insn (gen_cmppsi_op (compare_op0, compare_op1));
3728 /* Just to silence the "missing case" warnings. */ ;
3733 m32c_expand_scc (int code, rtx *operands)
3735 enum machine_mode mode = TARGET_A16 ? QImode : HImode;
3737 emit_insn (gen_rtx_SET (mode,
3739 gen_rtx_fmt_ee (code,
3745 /* Pattern Output Functions */
3747 /* Returns a (OP (reg:CC FLG_REGNO) (const_int 0)) from some other
3748 match_operand rtx's OP. */
3750 m32c_cmp_flg_0 (rtx cmp)
3752 return gen_rtx_fmt_ee (GET_CODE (cmp),
3754 gen_rtx_REG (CCmode, FLG_REGNO),
3759 m32c_expand_movcc (rtx *operands)
3761 rtx rel = operands[1];
3764 if (GET_CODE (rel) != EQ && GET_CODE (rel) != NE)
3766 if (GET_CODE (operands[2]) != CONST_INT
3767 || GET_CODE (operands[3]) != CONST_INT)
3769 emit_insn (gen_cmpqi(XEXP (rel, 0), XEXP (rel, 1)));
3770 if (GET_CODE (rel) == NE)
3772 rtx tmp = operands[2];
3773 operands[2] = operands[3];
3777 cmp = gen_rtx_fmt_ee (GET_CODE (rel),
3782 emit_move_insn (operands[0],
3783 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
3790 /* Used for the "insv" pattern. Return nonzero to fail, else done. */
3792 m32c_expand_insv (rtx *operands)
3797 if (INTVAL (operands[1]) != 1)
3800 /* Our insv opcode (bset, bclr) can only insert a one-bit constant. */
3801 if (GET_CODE (operands[3]) != CONST_INT)
3803 if (INTVAL (operands[3]) != 0
3804 && INTVAL (operands[3]) != 1
3805 && INTVAL (operands[3]) != -1)
3808 mask = 1 << INTVAL (operands[2]);
3811 if (GET_CODE (op0) == SUBREG
3812 && SUBREG_BYTE (op0) == 0)
3814 rtx sub = SUBREG_REG (op0);
3815 if (GET_MODE (sub) == HImode || GET_MODE (sub) == QImode)
3819 if (!can_create_pseudo_p ()
3820 || (GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0)))
3824 src0 = gen_reg_rtx (GET_MODE (op0));
3825 emit_move_insn (src0, op0);
3828 if (GET_MODE (op0) == HImode
3829 && INTVAL (operands[2]) >= 8
3830 && GET_MODE (op0) == MEM)
3832 /* We are little endian. */
3833 rtx new_mem = gen_rtx_MEM (QImode, plus_constant (XEXP (op0, 0), 1));
3834 MEM_COPY_ATTRIBUTES (new_mem, op0);
3838 /* First, we generate a mask with the correct polarity. If we are
3839 storing a zero, we want an AND mask, so invert it. */
3840 if (INTVAL (operands[3]) == 0)
3842 /* Storing a zero, use an AND mask */
3843 if (GET_MODE (op0) == HImode)
3848 /* Now we need to properly sign-extend the mask in case we need to
3849 fall back to an AND or OR opcode. */
3850 if (GET_MODE (op0) == HImode)
3861 switch ( (INTVAL (operands[3]) ? 4 : 0)
3862 + ((GET_MODE (op0) == HImode) ? 2 : 0)
3863 + (TARGET_A24 ? 1 : 0))
3865 case 0: p = gen_andqi3_16 (op0, src0, GEN_INT (mask)); break;
3866 case 1: p = gen_andqi3_24 (op0, src0, GEN_INT (mask)); break;
3867 case 2: p = gen_andhi3_16 (op0, src0, GEN_INT (mask)); break;
3868 case 3: p = gen_andhi3_24 (op0, src0, GEN_INT (mask)); break;
3869 case 4: p = gen_iorqi3_16 (op0, src0, GEN_INT (mask)); break;
3870 case 5: p = gen_iorqi3_24 (op0, src0, GEN_INT (mask)); break;
3871 case 6: p = gen_iorhi3_16 (op0, src0, GEN_INT (mask)); break;
3872 case 7: p = gen_iorhi3_24 (op0, src0, GEN_INT (mask)); break;
3880 m32c_scc_pattern(rtx *operands, RTX_CODE code)
3882 static char buf[30];
3883 if (GET_CODE (operands[0]) == REG
3884 && REGNO (operands[0]) == R0_REGNO)
3887 return "stzx\t#1,#0,r0l";
3889 return "stzx\t#0,#1,r0l";
3891 sprintf(buf, "bm%s\t0,%%h0\n\tand.b\t#1,%%0", GET_RTX_NAME (code));
3895 /* Encode symbol attributes of a SYMBOL_REF into its
3896 SYMBOL_REF_FLAGS. */
3898 m32c_encode_section_info (tree decl, rtx rtl, int first)
3900 int extra_flags = 0;
3902 default_encode_section_info (decl, rtl, first);
3903 if (TREE_CODE (decl) == FUNCTION_DECL
3904 && m32c_special_page_vector_p (decl))
3906 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
3909 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
3912 /* Returns TRUE if the current function is a leaf, and thus we can
3913 determine which registers an interrupt function really needs to
3914 save. The logic below is mostly about finding the insn sequence
3915 that's the function, versus any sequence that might be open for the
3918 m32c_leaf_function_p (void)
3920 rtx saved_first, saved_last;
3921 struct sequence_stack *seq;
3924 saved_first = crtl->emit.x_first_insn;
3925 saved_last = crtl->emit.x_last_insn;
3926 for (seq = crtl->emit.sequence_stack; seq && seq->next; seq = seq->next)
3930 crtl->emit.x_first_insn = seq->first;
3931 crtl->emit.x_last_insn = seq->last;
3934 rv = leaf_function_p ();
3936 crtl->emit.x_first_insn = saved_first;
3937 crtl->emit.x_last_insn = saved_last;
3941 /* Returns TRUE if the current function needs to use the ENTER/EXIT
3942 opcodes. If the function doesn't need the frame base or stack
3943 pointer, it can use the simpler RTS opcode. */
3945 m32c_function_needs_enter (void)
3948 struct sequence_stack *seq;
3949 rtx sp = gen_rtx_REG (Pmode, SP_REGNO);
3950 rtx fb = gen_rtx_REG (Pmode, FB_REGNO);
3952 insn = get_insns ();
3953 for (seq = crtl->emit.sequence_stack;
3955 insn = seq->first, seq = seq->next);
3959 if (reg_mentioned_p (sp, insn))
3961 if (reg_mentioned_p (fb, insn))
3963 insn = NEXT_INSN (insn);
3968 /* Mark all the subexpressions of the PARALLEL rtx PAR as
3969 frame-related. Return PAR.
3971 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
3972 PARALLEL rtx other than the first if they do not have the
3973 FRAME_RELATED flag set on them. So this function is handy for
3974 marking up 'enter' instructions. */
3976 m32c_all_frame_related (rtx par)
3978 int len = XVECLEN (par, 0);
3981 for (i = 0; i < len; i++)
3982 F (XVECEXP (par, 0, i));
3987 /* Emits the prologue. See the frame layout comment earlier in this
3988 file. We can reserve up to 256 bytes with the ENTER opcode, beyond
3989 that we manually update sp. */
3991 m32c_emit_prologue (void)
3993 int frame_size, extra_frame_size = 0, reg_save_size;
3994 int complex_prologue = 0;
3996 cfun->machine->is_leaf = m32c_leaf_function_p ();
3997 if (interrupt_p (cfun->decl))
3999 cfun->machine->is_interrupt = 1;
4000 complex_prologue = 1;
4003 reg_save_size = m32c_pushm_popm (PP_justcount);
4005 if (interrupt_p (cfun->decl))
4006 emit_insn (gen_pushm (GEN_INT (cfun->machine->intr_pushm)));
4009 m32c_initial_elimination_offset (FB_REGNO, SP_REGNO) - reg_save_size;
4011 && !cfun->machine->is_interrupt
4012 && !m32c_function_needs_enter ())
4013 cfun->machine->use_rts = 1;
4015 if (frame_size > 254)
4017 extra_frame_size = frame_size - 254;
4020 if (cfun->machine->use_rts == 0)
4021 F (emit_insn (m32c_all_frame_related
4023 ? gen_prologue_enter_16 (GEN_INT (frame_size + 2))
4024 : gen_prologue_enter_24 (GEN_INT (frame_size + 4)))));
4026 if (extra_frame_size)
4028 complex_prologue = 1;
4030 F (emit_insn (gen_addhi3 (gen_rtx_REG (HImode, SP_REGNO),
4031 gen_rtx_REG (HImode, SP_REGNO),
4032 GEN_INT (-extra_frame_size))));
4034 F (emit_insn (gen_addpsi3 (gen_rtx_REG (PSImode, SP_REGNO),
4035 gen_rtx_REG (PSImode, SP_REGNO),
4036 GEN_INT (-extra_frame_size))));
4039 complex_prologue += m32c_pushm_popm (PP_pushm);
4041 /* This just emits a comment into the .s file for debugging. */
4042 if (complex_prologue)
4043 emit_insn (gen_prologue_end ());
4046 /* Likewise, for the epilogue. The only exception is that, for
4047 interrupts, we must manually unwind the frame as the REIT opcode
4050 m32c_emit_epilogue (void)
4052 /* This just emits a comment into the .s file for debugging. */
4053 if (m32c_pushm_popm (PP_justcount) > 0 || cfun->machine->is_interrupt)
4054 emit_insn (gen_epilogue_start ());
4056 m32c_pushm_popm (PP_popm);
4058 if (cfun->machine->is_interrupt)
4060 enum machine_mode spmode = TARGET_A16 ? HImode : PSImode;
4062 emit_move_insn (gen_rtx_REG (spmode, A0_REGNO),
4063 gen_rtx_REG (spmode, FP_REGNO));
4064 emit_move_insn (gen_rtx_REG (spmode, SP_REGNO),
4065 gen_rtx_REG (spmode, A0_REGNO));
4067 emit_insn (gen_pophi_16 (gen_rtx_REG (HImode, FP_REGNO)));
4069 emit_insn (gen_poppsi (gen_rtx_REG (PSImode, FP_REGNO)));
4070 emit_insn (gen_popm (GEN_INT (cfun->machine->intr_pushm)));
4072 emit_jump_insn (gen_epilogue_reit_16 ());
4074 emit_jump_insn (gen_epilogue_reit_24 ());
4076 else if (cfun->machine->use_rts)
4077 emit_jump_insn (gen_epilogue_rts ());
4078 else if (TARGET_A16)
4079 emit_jump_insn (gen_epilogue_exitd_16 ());
4081 emit_jump_insn (gen_epilogue_exitd_24 ());
4086 m32c_emit_eh_epilogue (rtx ret_addr)
4088 /* R0[R2] has the stack adjustment. R1[R3] has the address to
4089 return to. We have to fudge the stack, pop everything, pop SP
4090 (fudged), and return (fudged). This is actually easier to do in
4091 assembler, so punt to libgcc. */
4092 emit_jump_insn (gen_eh_epilogue (ret_addr, cfun->machine->eh_stack_adjust));
4093 /* emit_clobber (gen_rtx_REG (HImode, R0L_REGNO)); */
4097 /* Indicate which flags must be properly set for a given conditional. */
4099 flags_needed_for_conditional (rtx cond)
4101 switch (GET_CODE (cond))
4125 /* Returns true if a compare insn is redundant because it would only
4126 set flags that are already set correctly. */
4128 m32c_compare_redundant (rtx cmp, rtx *operands)
4143 fprintf(stderr, "\n\033[32mm32c_compare_redundant\033[0m\n");
4147 fprintf(stderr, "operands[%d] = ", i);
4148 debug_rtx(operands[i]);
4152 next = next_nonnote_insn (cmp);
4153 if (!next || !INSN_P (next))
4156 fprintf(stderr, "compare not followed by insn\n");
4161 if (GET_CODE (PATTERN (next)) == SET
4162 && GET_CODE (XEXP ( PATTERN (next), 1)) == IF_THEN_ELSE)
4164 next = XEXP (XEXP (PATTERN (next), 1), 0);
4166 else if (GET_CODE (PATTERN (next)) == SET)
4168 /* If this is a conditional, flags_needed will be something
4169 other than FLAGS_N, which we test below. */
4170 next = XEXP (PATTERN (next), 1);
4175 fprintf(stderr, "compare not followed by conditional\n");
4181 fprintf(stderr, "conditional is: ");
4185 flags_needed = flags_needed_for_conditional (next);
4186 if (flags_needed == FLAGS_N)
4189 fprintf(stderr, "compare not followed by conditional\n");
4195 /* Compare doesn't set overflow and carry the same way that
4196 arithmetic instructions do, so we can't replace those. */
4197 if (flags_needed & FLAGS_OC)
4202 prev = prev_nonnote_insn (prev);
4206 fprintf(stderr, "No previous insn.\n");
4213 fprintf(stderr, "Previous insn is a non-insn.\n");
4217 pp = PATTERN (prev);
4218 if (GET_CODE (pp) != SET)
4221 fprintf(stderr, "Previous insn is not a SET.\n");
4225 pflags = get_attr_flags (prev);
4227 /* Looking up attributes of previous insns corrupted the recog
4229 INSN_UID (cmp) = -1;
4230 recog (PATTERN (cmp), cmp, 0);
4232 if (pflags == FLAGS_N
4233 && reg_mentioned_p (op0, pp))
4236 fprintf(stderr, "intermediate non-flags insn uses op:\n");
4241 } while (pflags == FLAGS_N);
4243 fprintf(stderr, "previous flag-setting insn:\n");
4248 if (GET_CODE (pp) == SET
4249 && GET_CODE (XEXP (pp, 0)) == REG
4250 && REGNO (XEXP (pp, 0)) == FLG_REGNO
4251 && GET_CODE (XEXP (pp, 1)) == COMPARE)
4253 /* Adjacent cbranches must have the same operands to be
4255 rtx pop0 = XEXP (XEXP (pp, 1), 0);
4256 rtx pop1 = XEXP (XEXP (pp, 1), 1);
4258 fprintf(stderr, "adjacent cbranches\n");
4262 if (rtx_equal_p (op0, pop0)
4263 && rtx_equal_p (op1, pop1))
4266 fprintf(stderr, "prev cmp not same\n");
4271 /* Else the previous insn must be a SET, with either the source or
4272 dest equal to operands[0], and operands[1] must be zero. */
4274 if (!rtx_equal_p (op1, const0_rtx))
4277 fprintf(stderr, "operands[1] not const0_rtx\n");
4281 if (GET_CODE (pp) != SET)
4284 fprintf (stderr, "pp not set\n");
4288 if (!rtx_equal_p (op0, SET_SRC (pp))
4289 && !rtx_equal_p (op0, SET_DEST (pp)))
4292 fprintf(stderr, "operands[0] not found in set\n");
4298 fprintf(stderr, "cmp flags %x prev flags %x\n", flags_needed, pflags);
4300 if ((pflags & flags_needed) == flags_needed)
4306 /* Return the pattern for a compare. This will be commented out if
4307 the compare is redundant, else a normal pattern is returned. Thus,
4308 the assembler output says where the compare would have been. */
4310 m32c_output_compare (rtx insn, rtx *operands)
4312 static char template[] = ";cmp.b\t%1,%0";
4315 template[5] = " bwll"[GET_MODE_SIZE(GET_MODE(operands[0]))];
4316 if (m32c_compare_redundant (insn, operands))
4319 fprintf(stderr, "cbranch: cmp not needed\n");
4325 fprintf(stderr, "cbranch: cmp needed: `%s'\n", template);
4327 return template + 1;
4330 #undef TARGET_ENCODE_SECTION_INFO
4331 #define TARGET_ENCODE_SECTION_INFO m32c_encode_section_info
4333 /* The Global `targetm' Variable. */
4335 struct gcc_target targetm = TARGET_INITIALIZER;
4337 #include "gt-m32c.h"