1 /* Definitions of target machine for GNU compiler.
2 Vitesse IQ2000 processors
3 Copyright (C) 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 2, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Set up System V.4 (aka ELF) defaults. */
27 /* Driver configuration. */
29 #undef SWITCH_TAKES_ARG
30 #define SWITCH_TAKES_ARG(CHAR) \
31 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
33 /* The svr4.h LIB_SPEC with -leval and --*group tacked on */
35 #define LIB_SPEC "%{!shared:%{!symbolic:--start-group -lc -leval -lgcc --end-group}}"
41 /* Run-time target specifications. */
43 #define TARGET_CPU_CPP_BUILTINS() \
46 builtin_define ("__iq2000__"); \
47 builtin_assert ("cpu=iq2000"); \
48 builtin_assert ("machine=iq2000"); \
53 extern int target_flags;
55 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
56 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
57 #define MASK_UNINIT_CONST_IN_RODATA \
58 0x00800000 /* Store uninitialized
61 /* Macros used in the machine description to test the flags. */
63 #define TARGET_STATS 0
65 /* for embedded systems, optimize for
66 reduced RAM space instead of for
68 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
70 #define TARGET_DEBUG_MODE (target_flags & 0)
71 #define TARGET_DEBUG_A_MODE (target_flags & 0)
72 #define TARGET_DEBUG_B_MODE (target_flags & 0)
73 #define TARGET_DEBUG_C_MODE (target_flags & 0)
74 #define TARGET_DEBUG_D_MODE (target_flags & 0)
76 #define TARGET_SWITCHES \
79 N_("No default crt0.o") }, \
80 {"gpopt", MASK_GPOPT, \
81 N_("Use GP relative sdata/sbss sections")}, \
82 {"no-gpopt", -MASK_GPOPT, \
83 N_("Don't use GP relative sdata/sbss sections")}, \
84 {"embedded-data", MASK_EMBEDDED_DATA, \
85 N_("Use ROM instead of RAM")}, \
86 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
87 N_("Don't use ROM instead of RAM")}, \
88 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
89 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
90 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
91 N_("Don't put uninitialized constants in ROM")}, \
92 {"", (TARGET_DEFAULT \
93 | TARGET_CPU_DEFAULT), \
97 /* Default target_flags if no switches are specified. */
99 #define TARGET_DEFAULT 0
101 #ifndef TARGET_CPU_DEFAULT
102 #define TARGET_CPU_DEFAULT 0
105 #ifndef IQ2000_ISA_DEFAULT
106 #define IQ2000_ISA_DEFAULT 1
109 #define TARGET_OPTIONS \
111 SUBTARGET_TARGET_OPTIONS \
112 { "cpu=", & iq2000_cpu_string, \
113 N_("Specify CPU for scheduling purposes")}, \
114 { "arch=", & iq2000_arch_string, \
115 N_("Specify CPU for code generation purposes")}, \
118 /* This is meant to be redefined in the host dependent files. */
119 #define SUBTARGET_TARGET_OPTIONS
121 #define IQ2000_VERSION "[1.0]"
124 #define MACHINE_TYPE "IQ2000"
127 #ifndef TARGET_VERSION_INTERNAL
128 #define TARGET_VERSION_INTERNAL(STREAM) \
129 fprintf (STREAM, " %s %s", IQ2000_VERSION, MACHINE_TYPE)
132 #ifndef TARGET_VERSION
133 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
136 #define OVERRIDE_OPTIONS override_options ()
138 #define CAN_DEBUG_WITHOUT_FP
140 /* Storage Layout. */
142 #define BITS_BIG_ENDIAN 0
144 #define BYTES_BIG_ENDIAN 1
146 #define WORDS_BIG_ENDIAN 1
148 #define LIBGCC2_WORDS_BIG_ENDIAN 1
150 #define BITS_PER_UNIT 8
152 #define BITS_PER_WORD 32
154 #define MAX_BITS_PER_WORD 64
156 #define UNITS_PER_WORD 4
158 #define MIN_UNITS_PER_WORD 4
160 #define POINTER_SIZE 32
162 /* Define this macro if it is advisable to hold scalars in registers
163 in a wider mode than that declared by the program. In such cases,
164 the value is constrained to be within the bounds of the declared
165 type, but kept valid in the wider mode. The signedness of the
166 extension may differ from that of the type.
168 We promote any value smaller than SImode up to SImode. */
170 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
171 if (GET_MODE_CLASS (MODE) == MODE_INT \
172 && GET_MODE_SIZE (MODE) < 4) \
175 #define PROMOTE_FUNCTION_ARGS
177 #define PROMOTE_FUNCTION_RETURN
179 #define PARM_BOUNDARY 32
181 #define STACK_BOUNDARY 64
183 #define FUNCTION_BOUNDARY 32
185 #define BIGGEST_ALIGNMENT 64
187 #undef DATA_ALIGNMENT
188 #define DATA_ALIGNMENT(TYPE, ALIGN) \
189 ((((ALIGN) < BITS_PER_WORD) \
190 && (TREE_CODE (TYPE) == ARRAY_TYPE \
191 || TREE_CODE (TYPE) == UNION_TYPE \
192 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
194 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
195 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
196 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
198 #define EMPTY_FIELD_BOUNDARY 32
200 #define STRUCTURE_SIZE_BOUNDARY 8
202 #define STRICT_ALIGNMENT 1
204 #define PCC_BITFIELD_TYPE_MATTERS 1
206 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
209 /* Layout of Source Language Data Types. */
211 #define INT_TYPE_SIZE 32
213 #define MAX_INT_TYPE_SIZE 32
215 #define SHORT_TYPE_SIZE 16
217 #define LONG_TYPE_SIZE 32
219 #define LONG_LONG_TYPE_SIZE 64
221 #define CHAR_TYPE_SIZE BITS_PER_UNIT
223 #define FLOAT_TYPE_SIZE 32
225 #define DOUBLE_TYPE_SIZE 64
227 #define LONG_DOUBLE_TYPE_SIZE 64
229 #define DEFAULT_SIGNED_CHAR 1
231 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
234 /* Register Basics. */
236 /* On the IQ2000, we have 32 integer registers. */
237 #define FIRST_PSEUDO_REGISTER 33
239 #define FIXED_REGISTERS \
241 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
242 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1 \
245 #define CALL_USED_REGISTERS \
247 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
248 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1 \
252 /* Order of allocation of registers. */
254 #define REG_ALLOC_ORDER \
255 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
256 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 \
260 /* How Values Fit in Registers. */
262 #define HARD_REGNO_NREGS(REGNO, MODE) \
263 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
265 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
266 ((REGNO_REG_CLASS (REGNO) == GR_REGS) \
267 ? ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) <= 4 \
268 : ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) == 4)
270 #define MODES_TIEABLE_P(MODE1, MODE2) \
271 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
272 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
273 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
274 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
276 #define AVOID_CCMODE_COPIES
279 /* Register Classes. */
283 NO_REGS, /* no registers in set */
284 GR_REGS, /* integer registers */
285 ALL_REGS, /* all registers */
286 LIM_REG_CLASSES /* max value + 1 */
289 #define GENERAL_REGS GR_REGS
291 #define N_REG_CLASSES (int) LIM_REG_CLASSES
293 #define REG_CLASS_NAMES \
300 #define REG_CLASS_CONTENTS \
302 { 0x00000000, 0x00000000 }, /* no registers */ \
303 { 0xffffffff, 0x00000000 }, /* integer registers */ \
304 { 0xffffffff, 0x00000001 } /* all registers */ \
307 #define REGNO_REG_CLASS(REGNO) \
308 ((REGNO) <= GP_REG_LAST + 1 ? GR_REGS : NO_REGS)
310 #define BASE_REG_CLASS (GR_REGS)
312 #define INDEX_REG_CLASS NO_REGS
314 #define REG_CLASS_FROM_LETTER(C) \
315 ((C) == 'd' ? GR_REGS : \
316 (C) == 'b' ? ALL_REGS : \
317 (C) == 'y' ? GR_REGS : \
320 #define REGNO_OK_FOR_INDEX_P(regno) 0
322 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
323 ((CLASS) != ALL_REGS \
325 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
326 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
328 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
329 || GET_MODE (X) == VOIDmode) \
333 #define SMALL_REGISTER_CLASSES 0
335 #define CLASS_MAX_NREGS(CLASS, MODE) \
336 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
340 `I' is used for the range of constants an arithmetic insn can
341 actually contain (16 bits signed integers).
343 `J' is used for the range which is just zero (ie, $r0).
345 `K' is used for the range of constants a logical insn can actually
346 contain (16 bit zero-extended integers).
348 `L' is used for the range of constants that be loaded with lui
349 (ie, the bottom 16 bits are zero).
351 `M' is used for the range of constants that take two words to load
352 (ie, not matched by `I', `K', and `L').
354 `N' is used for constants 0xffffnnnn or 0xnnnnffff
356 `O' is a 5 bit zero-extended integer.
359 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
360 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
361 : (C) == 'J' ? ((VALUE) == 0) \
362 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
363 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
364 && (((VALUE) & ~2147483647) == 0 \
365 || ((VALUE) & ~2147483647) == ~2147483647)) \
366 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
367 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
368 && (((VALUE) & 0x0000ffff) != 0 \
369 || (((VALUE) & ~2147483647) != 0 \
370 && ((VALUE) & ~2147483647) != ~2147483647))) \
371 : (C) == 'N' ? ((((VALUE) & 0xffff) == 0xffff) \
372 || (((VALUE) & 0xffff0000) == 0xffff0000)) \
373 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x20) < 0x40) \
376 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
378 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
380 /* `R' is for memory references which take 1 word for the instruction. */
382 #define EXTRA_CONSTRAINT(OP,CODE) \
383 (((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
387 /* Basic Stack Layout. */
389 #define STACK_GROWS_DOWNWARD
391 /* #define FRAME_GROWS_DOWNWARD */
393 #define STARTING_FRAME_OFFSET \
394 (current_function_outgoing_args_size)
396 /* Use the default value zero. */
397 /* #define STACK_POINTER_OFFSET 0 */
399 #define FIRST_PARM_OFFSET(FNDECL) 0
401 /* The return address for the current frame is in r31 if this is a leaf
402 function. Otherwise, it is on the stack. It is at a variable offset
403 from sp/fp/ap, so we define a fake hard register rap which is a
404 pointer to the return address on the stack. This always gets eliminated
405 during reload to be either the frame pointer or the stack pointer plus
408 #define RETURN_ADDR_RTX(count, frame) \
410 ? (leaf_function_p () \
411 ? gen_rtx_REG (Pmode, GP_REG_FIRST + 31) \
412 : gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, \
413 RETURN_ADDRESS_POINTER_REGNUM))) \
416 /* Before the prologue, RA lives in r31. */
417 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
420 /* Register That Address the Stack Frame. */
422 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
424 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
426 #define HARD_FRAME_POINTER_REGNUM \
429 #define ARG_POINTER_REGNUM GP_REG_FIRST
431 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
433 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
436 /* Eliminating the Frame Pointer and the Arg Pointer. */
438 #define FRAME_POINTER_REQUIRED 0
440 #define ELIMINABLE_REGS \
441 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
442 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
443 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
444 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
445 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31}, \
446 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
447 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
450 /* We can always eliminate to the frame pointer. We can eliminate to the
451 stack pointer unless a frame pointer is needed. */
453 #define CAN_ELIMINATE(FROM, TO) \
454 (((FROM) == RETURN_ADDRESS_POINTER_REGNUM && (! leaf_function_p () \
455 || (TO == GP_REG_FIRST + 31 && leaf_function_p))) \
456 || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
457 && ((TO) == HARD_FRAME_POINTER_REGNUM \
458 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed))))
460 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
461 (OFFSET) = iq2000_initial_elimination_offset ((FROM), (TO))
463 /* Passing Function Arguments on the Stack. */
465 #define PROMOTE_PROTOTYPES 1
467 /* #define PUSH_ROUNDING(BYTES) 0 */
469 #define ACCUMULATE_OUTGOING_ARGS 1
471 #define REG_PARM_STACK_SPACE(FNDECL) 0
473 #define OUTGOING_REG_PARM_STACK_SPACE
475 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
478 /* Function Arguments in Registers. */
480 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
481 function_arg( &CUM, MODE, TYPE, NAMED)
483 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
484 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
486 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
487 function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
489 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
490 ((NAMED) && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
492 #define MAX_ARGS_IN_REGISTERS 8
494 typedef struct iq2000_args {
495 int gp_reg_found; /* whether a gp register was found yet */
496 unsigned int arg_number; /* argument number */
497 unsigned int arg_words; /* # total words the arguments take */
498 unsigned int fp_arg_words; /* # words for FP args (IQ2000_EABI only) */
499 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
500 int fp_code; /* Mode of FP arguments */
501 unsigned int num_adjusts; /* number of adjustments made */
502 /* Adjustments made to args pass in regs. */
503 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
506 /* Initialize a variable CUM of type CUMULATIVE_ARGS
507 for a call to a function whose data type is FNTYPE.
508 For a library call, FNTYPE is 0. */
509 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
510 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
512 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
513 function_arg_advance (&CUM, MODE, TYPE, NAMED)
515 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
516 (! BYTES_BIG_ENDIAN \
518 : (((MODE) == BLKmode \
519 ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
520 && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
521 : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY \
522 && (GET_MODE_CLASS (MODE) == MODE_INT))) \
523 ? downward : upward))
525 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
527 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
529 : TYPE_ALIGN(TYPE)) \
530 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
532 : GET_MODE_ALIGNMENT(MODE)))
534 #define FUNCTION_ARG_REGNO_P(N) \
535 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST))
538 /* How Scalar Function Values are Returned. */
540 #define FUNCTION_VALUE(VALTYPE, FUNC) iq2000_function_value (VALTYPE, FUNC)
542 #define LIBCALL_VALUE(MODE) \
544 ((GET_MODE_CLASS (MODE) != MODE_INT \
545 || GET_MODE_SIZE (MODE) >= 4) \
550 /* On the IQ2000, R2 and R3 are the only register thus used. */
552 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN)
555 /* How Large Values are Returned. */
557 #define RETURN_IN_MEMORY(TYPE) \
558 (((int_size_in_bytes (TYPE) \
559 > (2 * UNITS_PER_WORD)) \
560 || (int_size_in_bytes (TYPE) == -1)))
562 #define DEFAULT_PCC_STRUCT_RETURN 0
564 #define STRUCT_VALUE 0
567 /* Function Entry and Exit. */
569 #define EXIT_IGNORE_STACK 1
572 /* Generating Code for Profiling. */
574 #define FUNCTION_PROFILER(FILE, LABELNO) \
576 fprintf (FILE, "\t.set\tnoreorder\n"); \
577 fprintf (FILE, "\t.set\tnoat\n"); \
578 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
579 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
580 fprintf (FILE, "\tjal\t_mcount\n"); \
582 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
584 reg_names[STACK_POINTER_REGNUM], \
585 reg_names[STACK_POINTER_REGNUM], \
586 Pmode == DImode ? 16 : 8); \
587 fprintf (FILE, "\t.set\treorder\n"); \
588 fprintf (FILE, "\t.set\tat\n"); \
592 /* Implementing the Varargs Macros. */
594 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
595 iq2000_setup_incoming_varargs (CUM,MODE,TYPE,&PRETEND_SIZE,NO_RTL);
597 #define STRICT_ARGUMENT_NAMING 1
599 #define BUILD_VA_LIST_TYPE(VALIST) \
600 (VALIST) = ptr_type_node
602 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
603 iq2000_va_start (valist, nextarg)
605 /* Implement `va_arg'. */
606 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
607 iq2000_va_arg (valist, type)
610 /* Trampolines for Nested Functions. */
612 /* A C statement to output, on the stream FILE, assembler code for a
613 block of data that contains the constant parts of a trampoline.
614 This code should not include a label--the label is taken care of
617 #define TRAMPOLINE_TEMPLATE(STREAM) \
619 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
620 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
621 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
622 if (Pmode == DImode) \
624 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
625 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
629 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
630 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
632 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
633 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
634 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
635 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
636 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
639 #define TRAMPOLINE_SIZE (40)
641 #define TRAMPOLINE_ALIGNMENT 32
643 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
646 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
647 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
651 /* Implicit Calls to Library Routines. */
653 #define INIT_TARGET_OPTABS \
656 INIT_SUBTARGET_OPTABS; \
661 /* Addressing Modes. */
663 #define CONSTANT_ADDRESS_P(X) \
664 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
665 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
666 || (GET_CODE (X) == CONST)))
668 #define MAX_REGS_PER_ADDRESS 1
671 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
673 if (iq2000_legitimate_address_p (MODE, X, 1)) \
677 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
679 if (iq2000_legitimate_address_p (MODE, X, 0)) \
684 #define REG_OK_FOR_INDEX_P(X) 0
687 /* For the IQ2000, transform:
689 memory(X + <large int>)
691 Y = <large int> & ~0x7fff;
693 memory (Z + (<large int> & 0x7fff));
696 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
698 register rtx xinsn = (X); \
700 if (TARGET_DEBUG_B_MODE) \
702 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
703 GO_DEBUG_RTX (xinsn); \
706 if (iq2000_check_split (X, MODE)) \
708 X = gen_rtx_LO_SUM (Pmode, \
709 copy_to_mode_reg (Pmode, \
710 gen_rtx (HIGH, Pmode, X)), \
715 if (GET_CODE (xinsn) == PLUS) \
717 register rtx xplus0 = XEXP (xinsn, 0); \
718 register rtx xplus1 = XEXP (xinsn, 1); \
719 register enum rtx_code code0 = GET_CODE (xplus0); \
720 register enum rtx_code code1 = GET_CODE (xplus1); \
722 if (code0 != REG && code1 == REG) \
724 xplus0 = XEXP (xinsn, 1); \
725 xplus1 = XEXP (xinsn, 0); \
726 code0 = GET_CODE (xplus0); \
727 code1 = GET_CODE (xplus1); \
730 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
731 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
733 rtx int_reg = gen_reg_rtx (Pmode); \
734 rtx ptr_reg = gen_reg_rtx (Pmode); \
736 emit_move_insn (int_reg, \
737 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
739 emit_insn (gen_rtx_SET (VOIDmode, \
741 gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
743 X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff); \
748 if (TARGET_DEBUG_B_MODE) \
749 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
752 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
754 #define LEGITIMATE_CONSTANT_P(X) (1)
757 /* Describing Relative Costs of Operations. */
759 #define CONST_COSTS(X,CODE,OUTER_CODE) \
764 return COSTS_N_INSNS (2); \
768 rtx offset = const0_rtx; \
769 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
771 if (GET_CODE (symref) == LABEL_REF) \
772 return COSTS_N_INSNS (2); \
774 if (GET_CODE (symref) != SYMBOL_REF) \
775 return COSTS_N_INSNS (4); \
777 /* let's be paranoid.... */ \
778 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
779 return COSTS_N_INSNS (2); \
781 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
785 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
790 split_double (X, &high, &low); \
791 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
792 || low == CONST0_RTX (GET_MODE (low))) \
796 #define RTX_COSTS(X,CODE,OUTER_CODE) \
799 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
800 if (simple_memory_operand (X, GET_MODE (X))) \
801 return COSTS_N_INSNS (num_words); \
803 return COSTS_N_INSNS (2*num_words); \
807 return COSTS_N_INSNS (6); \
810 return COSTS_N_INSNS (GET_MODE (X) == DImode && 2); \
815 if (GET_MODE (X) == DImode) \
816 return COSTS_N_INSNS (2); \
823 if (GET_MODE (X) == DImode) \
824 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
830 enum machine_mode xmode = GET_MODE (X); \
831 if (xmode == SFmode || xmode == DFmode) \
832 return COSTS_N_INSNS (1); \
834 return COSTS_N_INSNS (4); \
840 enum machine_mode xmode = GET_MODE (X); \
841 if (xmode == SFmode || xmode == DFmode) \
843 return COSTS_N_INSNS (6); \
846 if (xmode == DImode) \
847 return COSTS_N_INSNS (4); \
853 if (GET_MODE (X) == DImode) \
860 enum machine_mode xmode = GET_MODE (X); \
861 if (xmode == SFmode) \
863 return COSTS_N_INSNS (7); \
866 if (xmode == DFmode) \
868 return COSTS_N_INSNS (8); \
871 return COSTS_N_INSNS (10); \
877 enum machine_mode xmode = GET_MODE (X); \
878 if (xmode == SFmode) \
880 return COSTS_N_INSNS (23); \
883 if (xmode == DFmode) \
885 return COSTS_N_INSNS (36); \
892 return COSTS_N_INSNS (69); \
895 return COSTS_N_INSNS (2); \
898 return COSTS_N_INSNS (1);
900 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : iq2000_address_cost (ADDR))
902 #define REGISTER_MOVE_COST(MODE, FROM, TO) 2
904 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
907 #define BRANCH_COST 2
909 #define SLOW_BYTE_ACCESS 1
911 #define NO_FUNCTION_CSE 1
913 #define NO_RECURSIVE_FUNCTION_CSE 1
915 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
916 if (REG_NOTE_KIND (LINK) != 0) \
917 (COST) = 0; /* Anti or output dependence. */
920 /* Dividing the output into sections. */
922 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
924 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
927 /* The Overall Framework of an Assembler File. */
929 #define ASM_COMMENT_START " #"
931 #define ASM_APP_ON "#APP\n"
933 #define ASM_APP_OFF "#NO_APP\n"
936 /* Output and Generation of Labels. */
938 #undef ASM_OUTPUT_INTERNAL_LABEL
939 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
940 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
942 #undef ASM_GENERATE_INTERNAL_LABEL
943 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
944 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
946 #define GLOBAL_ASM_OP "\t.globl\t"
949 /* Output of Assembler Instructions. */
951 #define REGISTER_NAMES \
953 "%0", "%1", "%2", "%3", "%4", "%5", "%6", "%7", \
954 "%8", "%9", "%10", "%11", "%12", "%13", "%14", "%15", \
955 "%16", "%17", "%18", "%19", "%20", "%21", "%22", "%23", \
956 "%24", "%25", "%26", "%27", "%28", "%29", "%30", "%31", "%rap" \
959 #define ADDITIONAL_REGISTER_NAMES \
961 { "%0", 0 + GP_REG_FIRST }, \
962 { "%1", 1 + GP_REG_FIRST }, \
963 { "%2", 2 + GP_REG_FIRST }, \
964 { "%3", 3 + GP_REG_FIRST }, \
965 { "%4", 4 + GP_REG_FIRST }, \
966 { "%5", 5 + GP_REG_FIRST }, \
967 { "%6", 6 + GP_REG_FIRST }, \
968 { "%7", 7 + GP_REG_FIRST }, \
969 { "%8", 8 + GP_REG_FIRST }, \
970 { "%9", 9 + GP_REG_FIRST }, \
971 { "%10", 10 + GP_REG_FIRST }, \
972 { "%11", 11 + GP_REG_FIRST }, \
973 { "%12", 12 + GP_REG_FIRST }, \
974 { "%13", 13 + GP_REG_FIRST }, \
975 { "%14", 14 + GP_REG_FIRST }, \
976 { "%15", 15 + GP_REG_FIRST }, \
977 { "%16", 16 + GP_REG_FIRST }, \
978 { "%17", 17 + GP_REG_FIRST }, \
979 { "%18", 18 + GP_REG_FIRST }, \
980 { "%19", 19 + GP_REG_FIRST }, \
981 { "%20", 20 + GP_REG_FIRST }, \
982 { "%21", 21 + GP_REG_FIRST }, \
983 { "%22", 22 + GP_REG_FIRST }, \
984 { "%23", 23 + GP_REG_FIRST }, \
985 { "%24", 24 + GP_REG_FIRST }, \
986 { "%25", 25 + GP_REG_FIRST }, \
987 { "%26", 26 + GP_REG_FIRST }, \
988 { "%27", 27 + GP_REG_FIRST }, \
989 { "%28", 28 + GP_REG_FIRST }, \
990 { "%29", 29 + GP_REG_FIRST }, \
991 { "%30", 27 + GP_REG_FIRST }, \
992 { "%31", 31 + GP_REG_FIRST }, \
993 { "%rap", 32 + GP_REG_FIRST }, \
996 /* Check if the current insn needs a nop in front of it
997 because of load delays, and also update the delay slot statistics. */
999 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1000 final_prescan_insn (INSN, OPVEC, NOPERANDS)
1002 /* See iq2000.c for the IQ2000 specific codes. */
1003 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1005 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) iq2000_print_operand_punct[CODE]
1007 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1009 #define DBR_OUTPUT_SEQEND(STREAM) \
1012 dslots_jump_filled++; \
1013 fputs ("\n", STREAM); \
1017 #define LOCAL_LABEL_PREFIX "$"
1019 #define USER_LABEL_PREFIX ""
1022 /* Output of dispatch tables. */
1024 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
1026 fprintf (STREAM, "\t%s\t%sL%d\n", \
1027 Pmode == DImode ? ".dword" : ".word", \
1028 LOCAL_LABEL_PREFIX, VALUE); \
1031 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
1032 fprintf (STREAM, "\t%s\t%sL%d\n", \
1033 Pmode == DImode ? ".dword" : ".word", \
1034 LOCAL_LABEL_PREFIX, \
1038 /* Assembler Commands for Alignment. */
1040 #undef ASM_OUTPUT_SKIP
1041 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
1042 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
1044 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
1046 fprintf (STREAM, "\t.balign %d\n", 1<<(LOG))
1049 /* Macros Affecting all Debug Formats. */
1051 #define DEBUGGER_AUTO_OFFSET(X) \
1052 iq2000_debugger_offset (X, (HOST_WIDE_INT) 0)
1054 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1055 iq2000_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1057 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1059 #define DWARF2_DEBUGGING_INFO 1
1062 /* Miscellaneous Parameters. */
1064 #define PREDICATE_CODES \
1065 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
1066 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
1067 {"small_int", { CONST_INT }}, \
1068 {"large_int", { CONST_INT }}, \
1069 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
1070 {"simple_memory_operand", { MEM, SUBREG }}, \
1071 {"equality_op", { EQ, NE }}, \
1072 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
1074 {"pc_or_label_operand", { PC, LABEL_REF }}, \
1075 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
1076 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
1077 SYMBOL_REF, LABEL_REF, SUBREG, \
1079 {"power_of_2_operand", { CONST_INT }},
1081 #define CASE_VECTOR_MODE SImode
1083 #define CASE_VECTOR_PC_RELATIVE 0
1085 #define WORD_REGISTER_OPERATIONS
1087 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1091 #define MAX_MOVE_MAX 8
1093 #define SHIFT_COUNT_TRUNCATED 1
1095 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1097 #define STORE_FLAG_VALUE 1
1099 #define Pmode SImode
1101 #define FUNCTION_MODE SImode
1103 /* Standard GCC variables that we reference. */
1105 extern char call_used_regs[];
1107 /* IQ2000 external variables defined in iq2000.c. */
1109 /* Comparison type. */
1112 CMP_SI, /* compare four byte integers */
1113 CMP_DI, /* compare eight byte integers */
1114 CMP_SF, /* compare single precision floats */
1115 CMP_DF, /* compare double precision floats */
1116 CMP_MAX /* max comparison type */
1119 /* Types of delay slot. */
1122 DELAY_NONE, /* no delay slot */
1123 DELAY_LOAD, /* load from memory delay */
1124 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
1127 /* Which processor to schedule for. */
1136 /* Recast the cpu class to be the cpu attribute. */
1137 #define iq2000_cpu_attr ((enum attr_cpu)iq2000_tune)
1139 extern char iq2000_print_operand_punct[]; /* print_operand punctuation chars */
1140 extern int num_source_filenames; /* current .file # */
1141 extern int iq2000_branch_likely; /* emit 'l' after br (branch likely) */
1142 extern struct rtx_def *branch_cmp[2]; /* operands for compare */
1143 extern enum cmp_type branch_type; /* what type of branch to use */
1144 extern enum processor_type iq2000_arch; /* which cpu to codegen for */
1145 extern enum processor_type iq2000_tune; /* which cpu to schedule for */
1146 extern int iq2000_isa; /* architectural level */
1147 extern const char *iq2000_cpu_string; /* for -mcpu=<xxx> */
1148 extern const char *iq2000_arch_string; /* for -march=<xxx> */
1149 extern int dslots_load_total; /* total # load related delay slots */
1150 extern int dslots_load_filled; /* # filled load delay slots */
1151 extern int dslots_jump_total; /* total # jump related delay slots */
1152 extern int dslots_jump_filled; /* # filled jump delay slots */
1153 extern int dslots_number_nops; /* # of nops needed by previous insn */
1154 extern int num_refs[3]; /* # 1/2/3 word references */
1155 extern struct rtx_def *iq2000_load_reg; /* register to check for load delay */
1156 extern struct rtx_def *iq2000_load_reg2; /* 2nd reg to check for load delay */
1157 extern struct rtx_def *iq2000_load_reg3; /* 3rd reg to check for load delay */
1158 extern struct rtx_def *iq2000_load_reg4; /* 4th reg to check for load delay */
1160 /* Functions to change what output section we are using. */
1161 extern void rdata_section PARAMS ((void));
1162 extern void sdata_section PARAMS ((void));
1163 extern void sbss_section PARAMS ((void));
1165 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
1166 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
1169 #define GENERATE_BRANCHLIKELY (ISA_HAS_BRANCHLIKELY)
1171 /* Macros to decide whether certain features are available or not,
1172 depending on the instruction set architecture level. */
1174 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
1176 /* ISA has branch likely instructions. */
1177 #define ISA_HAS_BRANCHLIKELY (iq2000_isa == 1)
1181 #define ASM_SPEC "%{march=iq2000: -m2000} %{march=iq10: -m10} %{!march=*: -m2000}"
1184 /* The mapping from gcc register number to DWARF 2 CFA column number.
1185 This mapping does not allow for tracking register 0, since
1186 register 0 is fixed. */
1187 #define DWARF_FRAME_REGNUM(REG) \
1188 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1190 /* The DWARF 2 CFA column which tracks the return address. */
1191 #define DWARF_FRAME_RETURN_COLUMN ( GP_REG_FIRST + 26)
1193 /* Describe how we implement __builtin_eh_return. */
1194 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1196 /* The EH_RETURN_STACKADJ_RTX macro returns RTL which describes the
1197 location used to store the amount to adjust the stack. This is
1198 usually a register that is available from end of the function's body
1199 to the end of the epilogue. Thus, this cannot be a register used as a
1200 temporary by the epilogue.
1202 This must be an integer register. */
1203 #define EH_RETURN_STACKADJ_REGNO 3
1204 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
1206 /* The EH_RETURN_HANDLER_RTX macro returns RTL which describes the
1207 location used to store the address the processor should jump to
1208 catch exception. This is usually a registers that is available from
1209 end of the function's body to the end of the epilogue. Thus, this
1210 cannot be a register used as a temporary by the epilogue.
1212 This must be an address register. */
1213 #define EH_RETURN_HANDLER_REGNO 26
1214 #define EH_RETURN_HANDLER_RTX \
1215 gen_rtx_REG (Pmode, EH_RETURN_HANDLER_REGNO)
1217 /* Offsets recorded in opcodes are a multiple of this alignment factor. */
1218 #define DWARF_CIE_DATA_ALIGNMENT 4
1220 /* For IQ2000, width of a floating point register. */
1221 #define UNITS_PER_FPREG 4
1223 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1225 #define PAD_VARARGS_DOWN !BYTES_BIG_ENDIAN
1227 /* Internal macros to classify a register number as to whether it's a
1228 general purpose register, a floating point register, a
1229 multiply/divide register, or a status register. */
1231 #define GP_REG_FIRST 0
1232 #define GP_REG_LAST 31
1233 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1235 #define RAP_REG_NUM 32
1236 #define AT_REGNUM (GP_REG_FIRST + 1)
1238 #define GP_REG_P(REGNO) \
1239 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1241 /* IQ2000 registers used in prologue/epilogue code when the stack frame
1242 is larger than 32K bytes. These registers must come from the
1243 scratch register set, and not used for passing and returning
1244 arguments and any other information used in the calling sequence. */
1246 #define IQ2000_TEMP1_REGNUM (GP_REG_FIRST + 12)
1247 #define IQ2000_TEMP2_REGNUM (GP_REG_FIRST + 13)
1249 /* This macro is used later on in the file. */
1250 #define GR_REG_CLASS_P(CLASS) \
1251 ((CLASS) == GR_REGS)
1253 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1254 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
1256 /* Certain machines have the property that some registers cannot be
1257 copied to some other registers without using memory. Define this
1258 macro on those machines to be a C expression that is non-zero if
1259 objects of mode MODE in registers of CLASS1 can only be copied to
1260 registers of class CLASS2 by storing a register of CLASS1 into
1261 memory and loading that memory location into a register of CLASS2.
1263 Do not define this macro if its value would always be zero. */
1265 /* Return the maximum number of consecutive registers
1266 needed to represent mode MODE in a register of class CLASS. */
1268 #define CLASS_UNITS(mode, size) \
1269 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
1271 /* If defined, gives a class of registers that cannot be used as the
1272 operand of a SUBREG that changes the mode of the object illegally. */
1274 #define CLASS_CANNOT_CHANGE_MODE 0
1276 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
1278 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
1279 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
1281 /* Make sure 4 words are always allocated on the stack. */
1283 #ifndef STACK_ARGS_ADJUST
1284 #define STACK_ARGS_ADJUST(SIZE) \
1286 if (SIZE.constant < 4 * UNITS_PER_WORD) \
1287 SIZE.constant = 4 * UNITS_PER_WORD; \
1292 /* Symbolic macros for the registers used to return integer and floating
1295 #define GP_RETURN (GP_REG_FIRST + 2)
1297 /* Symbolic macros for the first/last argument registers. */
1299 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
1300 #define GP_ARG_LAST (GP_REG_FIRST + 11)
1302 #define MAX_ARGS_IN_REGISTERS 8
1305 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
1307 #define MUST_SAVE_REGISTER(regno) \
1308 ((regs_ever_live[regno] && !call_used_regs[regno]) \
1309 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
1310 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
1312 /* ALIGN FRAMES on double word boundaries */
1313 #ifndef IQ2000_STACK_ALIGN
1314 #define IQ2000_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
1318 /* These assume that REGNO is a hard or pseudo reg number.
1319 They give nonzero only if REGNO is a hard reg of the suitable class
1320 or a pseudo reg currently allocated to a suitable hard reg.
1321 These definitions are NOT overridden anywhere. */
1323 #define BASE_REG_P(regno, mode) \
1326 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
1327 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
1330 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
1331 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
1333 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
1334 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
1336 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1337 and check its validity for a certain class.
1338 We have two alternate definitions for each of them.
1339 The usual definition accepts all pseudo regs; the other rejects them all.
1340 The symbol REG_OK_STRICT causes the latter definition to be used.
1342 Most source files want to accept pseudo regs in the hope that
1343 they will get allocated to the class that the insn wants them to be in.
1344 Some source files that are used after register allocation
1345 need to be strict. */
1347 #ifndef REG_OK_STRICT
1348 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1349 iq2000_reg_mode_ok_for_base_p (X, MODE, 0)
1351 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1352 iq2000_reg_mode_ok_for_base_p (X, MODE, 1)
1356 #define GO_PRINTF(x) fprintf(stderr, (x))
1357 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
1358 #define GO_DEBUG_RTX(x) debug_rtx(x)
1361 #define GO_PRINTF(x)
1362 #define GO_PRINTF2(x,y)
1363 #define GO_DEBUG_RTX(x)
1366 /* Specify the tree operation to be used to convert reals to integers. */
1367 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1369 /* This is the kind of divide that is easiest to do in the general case. */
1370 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1372 /* Define this if zero-extension is slow (more than one real instruction). */
1373 #define SLOW_ZERO_EXTEND
1375 /* If defined, modifies the length assigned to instruction INSN as a
1376 function of the context in which it is used. LENGTH is an lvalue
1377 that contains the initially computed length of the insn and should
1378 be updated with the correct length of the insn. */
1379 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1380 ((LENGTH) = iq2000_adjust_insn_length ((INSN), (LENGTH)))
1383 /* A list of predicates that do special things with modes, and so
1384 should not elicit warnings for VOIDmode match_operand. */
1386 #define SPECIAL_MODE_PREDICATES \
1387 "pc_or_label_operand",
1392 /* How to tell the debugger about changes of source files. */
1394 #ifndef SET_FILE_NUMBER
1395 #define SET_FILE_NUMBER() ++num_source_filenames
1398 /* This is how to output a note the debugger telling it the line number
1399 to which the following sequence of instructions corresponds. */
1401 #ifndef LABEL_AFTER_LOC
1402 #define LABEL_AFTER_LOC(STREAM)
1405 /* Handle certain cpp directives used in header files on sysV. */
1406 #define SCCS_DIRECTIVE
1409 /* Default to -G 8 */
1410 #ifndef IQ2000_DEFAULT_GVALUE
1411 #define IQ2000_DEFAULT_GVALUE 8
1414 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
1416 /* Given a decl node or constant node, choose the section to output it in
1417 and select that section. */
1419 #undef TARGET_ASM_SELECT_SECTION
1420 #define TARGET_ASM_SELECT_SECTION iq2000_select_section
1422 /* See iq2000_expand_prologue's use of loadgp for when this should be
1425 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE 0
1428 #ifndef INIT_SUBTARGET_OPTABS
1429 #define INIT_SUBTARGET_OPTABS
1432 enum iq2000_builtins
1434 IQ2000_BUILTIN_ADO16,
1435 IQ2000_BUILTIN_CFC0,
1436 IQ2000_BUILTIN_CFC1,
1437 IQ2000_BUILTIN_CFC2,
1438 IQ2000_BUILTIN_CFC3,
1439 IQ2000_BUILTIN_CHKHDR,
1440 IQ2000_BUILTIN_CTC0,
1441 IQ2000_BUILTIN_CTC1,
1442 IQ2000_BUILTIN_CTC2,
1443 IQ2000_BUILTIN_CTC3,
1445 IQ2000_BUILTIN_LUC32L,
1446 IQ2000_BUILTIN_LUC64,
1447 IQ2000_BUILTIN_LUC64L,
1449 IQ2000_BUILTIN_LULCK,
1450 IQ2000_BUILTIN_LUM32,
1451 IQ2000_BUILTIN_LUM32L,
1452 IQ2000_BUILTIN_LUM64,
1453 IQ2000_BUILTIN_LUM64L,
1455 IQ2000_BUILTIN_LURL,
1456 IQ2000_BUILTIN_MFC0,
1457 IQ2000_BUILTIN_MFC1,
1458 IQ2000_BUILTIN_MFC2,
1459 IQ2000_BUILTIN_MFC3,
1460 IQ2000_BUILTIN_MRGB,
1461 IQ2000_BUILTIN_MTC0,
1462 IQ2000_BUILTIN_MTC1,
1463 IQ2000_BUILTIN_MTC2,
1464 IQ2000_BUILTIN_MTC3,
1465 IQ2000_BUILTIN_PKRL,
1469 IQ2000_BUILTIN_SRRD,
1470 IQ2000_BUILTIN_SRRDL,
1471 IQ2000_BUILTIN_SRULC,
1472 IQ2000_BUILTIN_SRULCK,
1473 IQ2000_BUILTIN_SRWR,
1474 IQ2000_BUILTIN_SRWRU,
1475 IQ2000_BUILTIN_TRAPQF,
1476 IQ2000_BUILTIN_TRAPQFL,
1477 IQ2000_BUILTIN_TRAPQN,
1478 IQ2000_BUILTIN_TRAPQNE,
1479 IQ2000_BUILTIN_TRAPRE,
1480 IQ2000_BUILTIN_TRAPREL,
1485 IQ2000_BUILTIN_SYSCALL