1 /* Definitions of target machine for GNU compiler.
2 Vitesse IQ2000 processors
3 Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 3, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* Driver configuration. */
24 #undef SWITCH_TAKES_ARG
25 #define SWITCH_TAKES_ARG(CHAR) \
26 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
28 /* The svr4.h LIB_SPEC with -leval and --*group tacked on */
30 #define LIB_SPEC "%{!shared:%{!symbolic:--start-group -lc -leval -lgcc --end-group}}"
36 /* Run-time target specifications. */
38 #define TARGET_CPU_CPP_BUILTINS() \
41 builtin_define ("__iq2000__"); \
42 builtin_assert ("cpu=iq2000"); \
43 builtin_assert ("machine=iq2000"); \
47 /* Macros used in the machine description to test the flags. */
49 #define TARGET_STATS 0
51 #define TARGET_DEBUG_MODE 0
52 #define TARGET_DEBUG_A_MODE 0
53 #define TARGET_DEBUG_B_MODE 0
54 #define TARGET_DEBUG_C_MODE 0
55 #define TARGET_DEBUG_D_MODE 0
57 #ifndef IQ2000_ISA_DEFAULT
58 #define IQ2000_ISA_DEFAULT 1
61 #define IQ2000_VERSION "[1.0]"
64 #define MACHINE_TYPE "IQ2000"
67 #ifndef TARGET_VERSION_INTERNAL
68 #define TARGET_VERSION_INTERNAL(STREAM) \
69 fprintf (STREAM, " %s %s", IQ2000_VERSION, MACHINE_TYPE)
72 #ifndef TARGET_VERSION
73 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
76 #define OVERRIDE_OPTIONS override_options ()
78 #define CAN_DEBUG_WITHOUT_FP
82 #define BITS_BIG_ENDIAN 0
83 #define BYTES_BIG_ENDIAN 1
84 #define WORDS_BIG_ENDIAN 1
85 #define LIBGCC2_WORDS_BIG_ENDIAN 1
86 #define BITS_PER_WORD 32
87 #define MAX_BITS_PER_WORD 64
88 #define UNITS_PER_WORD 4
89 #define MIN_UNITS_PER_WORD 4
90 #define POINTER_SIZE 32
92 /* Define this macro if it is advisable to hold scalars in registers
93 in a wider mode than that declared by the program. In such cases,
94 the value is constrained to be within the bounds of the declared
95 type, but kept valid in the wider mode. The signedness of the
96 extension may differ from that of the type.
98 We promote any value smaller than SImode up to SImode. */
100 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
101 if (GET_MODE_CLASS (MODE) == MODE_INT \
102 && GET_MODE_SIZE (MODE) < 4) \
105 #define PARM_BOUNDARY 32
107 #define STACK_BOUNDARY 64
109 #define FUNCTION_BOUNDARY 32
111 #define BIGGEST_ALIGNMENT 64
113 #undef DATA_ALIGNMENT
114 #define DATA_ALIGNMENT(TYPE, ALIGN) \
115 ((((ALIGN) < BITS_PER_WORD) \
116 && (TREE_CODE (TYPE) == ARRAY_TYPE \
117 || TREE_CODE (TYPE) == UNION_TYPE \
118 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
120 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
121 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
122 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
124 #define EMPTY_FIELD_BOUNDARY 32
126 #define STRUCTURE_SIZE_BOUNDARY 8
128 #define STRICT_ALIGNMENT 1
130 #define PCC_BITFIELD_TYPE_MATTERS 1
133 /* Layout of Source Language Data Types. */
135 #define INT_TYPE_SIZE 32
136 #define SHORT_TYPE_SIZE 16
137 #define LONG_TYPE_SIZE 32
138 #define LONG_LONG_TYPE_SIZE 64
139 #define CHAR_TYPE_SIZE BITS_PER_UNIT
140 #define FLOAT_TYPE_SIZE 32
141 #define DOUBLE_TYPE_SIZE 64
142 #define LONG_DOUBLE_TYPE_SIZE 64
143 #define DEFAULT_SIGNED_CHAR 1
146 /* Register Basics. */
148 /* On the IQ2000, we have 32 integer registers. */
149 #define FIRST_PSEUDO_REGISTER 33
151 #define FIXED_REGISTERS \
153 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
154 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1 \
157 #define CALL_USED_REGISTERS \
159 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
160 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1 \
164 /* Order of allocation of registers. */
166 #define REG_ALLOC_ORDER \
167 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
168 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 \
172 /* How Values Fit in Registers. */
174 #define HARD_REGNO_NREGS(REGNO, MODE) \
175 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
177 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
178 ((REGNO_REG_CLASS (REGNO) == GR_REGS) \
179 ? ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) <= 4 \
180 : ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) == 4)
182 #define MODES_TIEABLE_P(MODE1, MODE2) \
183 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
184 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
185 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
186 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
188 #define AVOID_CCMODE_COPIES
191 /* Register Classes. */
195 NO_REGS, /* No registers in set. */
196 GR_REGS, /* Integer registers. */
197 ALL_REGS, /* All registers. */
198 LIM_REG_CLASSES /* Max value + 1. */
201 #define GENERAL_REGS GR_REGS
203 #define N_REG_CLASSES (int) LIM_REG_CLASSES
205 #define IRA_COVER_CLASSES \
207 GR_REGS, LIM_REG_CLASSES \
210 #define REG_CLASS_NAMES \
217 #define REG_CLASS_CONTENTS \
219 { 0x00000000, 0x00000000 }, /* No registers, */ \
220 { 0xffffffff, 0x00000000 }, /* Integer registers. */ \
221 { 0xffffffff, 0x00000001 } /* All registers. */ \
224 #define REGNO_REG_CLASS(REGNO) \
225 ((REGNO) <= GP_REG_LAST + 1 ? GR_REGS : NO_REGS)
227 #define BASE_REG_CLASS (GR_REGS)
229 #define INDEX_REG_CLASS NO_REGS
231 #define REG_CLASS_FROM_LETTER(C) \
232 ((C) == 'd' ? GR_REGS : \
233 (C) == 'b' ? ALL_REGS : \
234 (C) == 'y' ? GR_REGS : \
237 #define REGNO_OK_FOR_INDEX_P(regno) 0
239 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
240 ((CLASS) != ALL_REGS \
242 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
243 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
245 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
246 || GET_MODE (X) == VOIDmode) \
250 #define SMALL_REGISTER_CLASSES 0
252 #define CLASS_MAX_NREGS(CLASS, MODE) \
253 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
257 `I' is used for the range of constants an arithmetic insn can
258 actually contain (16-bits signed integers).
260 `J' is used for the range which is just zero (i.e., $r0).
262 `K' is used for the range of constants a logical insn can actually
263 contain (16-bit zero-extended integers).
265 `L' is used for the range of constants that be loaded with lui
266 (i.e., the bottom 16 bits are zero).
268 `M' is used for the range of constants that take two words to load
269 (i.e., not matched by `I', `K', and `L').
271 `N' is used for constants 0xffffnnnn or 0xnnnnffff
273 `O' is a 5-bit zero-extended integer. */
275 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
276 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
277 : (C) == 'J' ? ((VALUE) == 0) \
278 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
279 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
280 && (((VALUE) & ~2147483647) == 0 \
281 || ((VALUE) & ~2147483647) == ~2147483647)) \
282 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
283 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
284 && (((VALUE) & 0x0000ffff) != 0 \
285 || (((VALUE) & ~2147483647) != 0 \
286 && ((VALUE) & ~2147483647) != ~2147483647))) \
287 : (C) == 'N' ? ((((VALUE) & 0xffff) == 0xffff) \
288 || (((VALUE) & 0xffff0000) == 0xffff0000)) \
289 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x20) < 0x40) \
292 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
294 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
296 /* `R' is for memory references which take 1 word for the instruction. */
298 #define EXTRA_CONSTRAINT(OP,CODE) \
299 (((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
303 /* Basic Stack Layout. */
305 #define STACK_GROWS_DOWNWARD
307 #define FRAME_GROWS_DOWNWARD 0
309 #define STARTING_FRAME_OFFSET \
310 (crtl->outgoing_args_size)
312 /* Use the default value zero. */
313 /* #define STACK_POINTER_OFFSET 0 */
315 #define FIRST_PARM_OFFSET(FNDECL) 0
317 /* The return address for the current frame is in r31 if this is a leaf
318 function. Otherwise, it is on the stack. It is at a variable offset
319 from sp/fp/ap, so we define a fake hard register rap which is a
320 pointer to the return address on the stack. This always gets eliminated
321 during reload to be either the frame pointer or the stack pointer plus
324 #define RETURN_ADDR_RTX(count, frame) \
326 ? (leaf_function_p () \
327 ? gen_rtx_REG (Pmode, GP_REG_FIRST + 31) \
328 : gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, \
329 RETURN_ADDRESS_POINTER_REGNUM))) \
332 /* Before the prologue, RA lives in r31. */
333 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
336 /* Register That Address the Stack Frame. */
338 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
339 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
340 #define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 27)
341 #define ARG_POINTER_REGNUM GP_REG_FIRST
342 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
343 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
346 /* Eliminating the Frame Pointer and the Arg Pointer. */
348 #define FRAME_POINTER_REQUIRED 0
350 #define ELIMINABLE_REGS \
351 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
352 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
353 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
354 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
355 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31}, \
356 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
357 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
360 /* We can always eliminate to the frame pointer. We can eliminate to the
361 stack pointer unless a frame pointer is needed. */
363 #define CAN_ELIMINATE(FROM, TO) \
364 (((FROM) == RETURN_ADDRESS_POINTER_REGNUM && (! leaf_function_p () \
365 || (TO == GP_REG_FIRST + 31 && leaf_function_p))) \
366 || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
367 && ((TO) == HARD_FRAME_POINTER_REGNUM \
368 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed))))
370 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
371 (OFFSET) = iq2000_initial_elimination_offset ((FROM), (TO))
373 /* Passing Function Arguments on the Stack. */
375 /* #define PUSH_ROUNDING(BYTES) 0 */
377 #define ACCUMULATE_OUTGOING_ARGS 1
379 #define REG_PARM_STACK_SPACE(FNDECL) 0
381 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
383 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
386 /* Function Arguments in Registers. */
388 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
389 function_arg (& CUM, MODE, TYPE, NAMED)
391 #define MAX_ARGS_IN_REGISTERS 8
393 typedef struct iq2000_args
395 int gp_reg_found; /* Whether a gp register was found yet. */
396 unsigned int arg_number; /* Argument number. */
397 unsigned int arg_words; /* # total words the arguments take. */
398 unsigned int fp_arg_words; /* # words for FP args (IQ2000_EABI only). */
399 int last_arg_fp; /* Nonzero if last arg was FP (EABI only). */
400 int fp_code; /* Mode of FP arguments. */
401 unsigned int num_adjusts; /* Number of adjustments made. */
402 /* Adjustments made to args pass in regs. */
403 struct rtx_def * adjust[MAX_ARGS_IN_REGISTERS * 2];
406 /* Initialize a variable CUM of type CUMULATIVE_ARGS
407 for a call to a function whose data type is FNTYPE.
408 For a library call, FNTYPE is 0. */
409 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
410 init_cumulative_args (& CUM, FNTYPE, LIBNAME) \
412 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
413 function_arg_advance (& CUM, MODE, TYPE, NAMED)
415 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
416 (! BYTES_BIG_ENDIAN \
418 : (((MODE) == BLKmode \
419 ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
420 && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
421 : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY \
422 && (GET_MODE_CLASS (MODE) == MODE_INT))) \
423 ? downward : upward))
425 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
427 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
429 : TYPE_ALIGN(TYPE)) \
430 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
432 : GET_MODE_ALIGNMENT(MODE)))
434 #define FUNCTION_ARG_REGNO_P(N) \
435 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST))
438 /* How Scalar Function Values are Returned. */
440 #define FUNCTION_VALUE(VALTYPE, FUNC) iq2000_function_value (VALTYPE, FUNC)
442 #define LIBCALL_VALUE(MODE) \
443 gen_rtx_REG (((GET_MODE_CLASS (MODE) != MODE_INT \
444 || GET_MODE_SIZE (MODE) >= 4) \
449 /* On the IQ2000, R2 and R3 are the only register thus used. */
451 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN)
454 /* How Large Values are Returned. */
456 #define DEFAULT_PCC_STRUCT_RETURN 0
458 /* Function Entry and Exit. */
460 #define EXIT_IGNORE_STACK 1
463 /* Generating Code for Profiling. */
465 #define FUNCTION_PROFILER(FILE, LABELNO) \
467 fprintf (FILE, "\t.set\tnoreorder\n"); \
468 fprintf (FILE, "\t.set\tnoat\n"); \
469 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
470 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
471 fprintf (FILE, "\tjal\t_mcount\n"); \
473 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
475 reg_names[STACK_POINTER_REGNUM], \
476 reg_names[STACK_POINTER_REGNUM], \
477 Pmode == DImode ? 16 : 8); \
478 fprintf (FILE, "\t.set\treorder\n"); \
479 fprintf (FILE, "\t.set\tat\n"); \
483 /* Trampolines for Nested Functions. */
485 /* A C statement to output, on the stream FILE, assembler code for a
486 block of data that contains the constant parts of a trampoline.
487 This code should not include a label--the label is taken care of
490 #define TRAMPOLINE_TEMPLATE(STREAM) \
492 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
493 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
494 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
495 if (Pmode == DImode) \
497 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
498 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
502 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
503 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
505 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
506 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
507 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
508 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
509 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
512 #define TRAMPOLINE_SIZE (40)
514 #define TRAMPOLINE_ALIGNMENT 32
516 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
519 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
520 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
524 /* Addressing Modes. */
526 #define CONSTANT_ADDRESS_P(X) \
527 ( (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
528 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
529 || (GET_CODE (X) == CONST)))
531 #define MAX_REGS_PER_ADDRESS 1
534 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
536 if (iq2000_legitimate_address_p (MODE, X, 1)) \
540 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
542 if (iq2000_legitimate_address_p (MODE, X, 0)) \
547 #define REG_OK_FOR_INDEX_P(X) 0
550 /* For the IQ2000, transform:
552 memory(X + <large int>)
554 Y = <large int> & ~0x7fff;
556 memory (Z + (<large int> & 0x7fff));
559 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
563 if (TARGET_DEBUG_B_MODE) \
565 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
566 GO_DEBUG_RTX (xinsn); \
569 if (iq2000_check_split (X, MODE)) \
571 X = gen_rtx_LO_SUM (Pmode, \
572 copy_to_mode_reg (Pmode, \
573 gen_rtx_HIGH (Pmode, X)), \
578 if (GET_CODE (xinsn) == PLUS) \
580 rtx xplus0 = XEXP (xinsn, 0); \
581 rtx xplus1 = XEXP (xinsn, 1); \
582 enum rtx_code code0 = GET_CODE (xplus0); \
583 enum rtx_code code1 = GET_CODE (xplus1); \
585 if (code0 != REG && code1 == REG) \
587 xplus0 = XEXP (xinsn, 1); \
588 xplus1 = XEXP (xinsn, 0); \
589 code0 = GET_CODE (xplus0); \
590 code1 = GET_CODE (xplus1); \
593 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
594 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
596 rtx int_reg = gen_reg_rtx (Pmode); \
597 rtx ptr_reg = gen_reg_rtx (Pmode); \
599 emit_move_insn (int_reg, \
600 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
602 emit_insn (gen_rtx_SET (VOIDmode, \
604 gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
606 X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff); \
611 if (TARGET_DEBUG_B_MODE) \
612 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
615 #define LEGITIMATE_CONSTANT_P(X) (1)
618 /* Describing Relative Costs of Operations. */
620 #define REGISTER_MOVE_COST(MODE, FROM, TO) 2
622 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
625 #define BRANCH_COST(speed_p, predictable_p) 2
627 #define SLOW_BYTE_ACCESS 1
629 #define NO_FUNCTION_CSE 1
631 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
632 if (REG_NOTE_KIND (LINK) != 0) \
633 (COST) = 0; /* Anti or output dependence. */
636 /* Dividing the output into sections. */
638 #define TEXT_SECTION_ASM_OP "\t.text" /* Instructions. */
640 #define DATA_SECTION_ASM_OP "\t.data" /* Large data. */
643 /* The Overall Framework of an Assembler File. */
645 #define ASM_COMMENT_START " #"
647 #define ASM_APP_ON "#APP\n"
649 #define ASM_APP_OFF "#NO_APP\n"
652 /* Output and Generation of Labels. */
654 #undef ASM_GENERATE_INTERNAL_LABEL
655 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
656 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long) (NUM))
658 #define GLOBAL_ASM_OP "\t.globl\t"
661 /* Output of Assembler Instructions. */
663 #define REGISTER_NAMES \
665 "%0", "%1", "%2", "%3", "%4", "%5", "%6", "%7", \
666 "%8", "%9", "%10", "%11", "%12", "%13", "%14", "%15", \
667 "%16", "%17", "%18", "%19", "%20", "%21", "%22", "%23", \
668 "%24", "%25", "%26", "%27", "%28", "%29", "%30", "%31", "%rap" \
671 #define ADDITIONAL_REGISTER_NAMES \
673 { "%0", 0 + GP_REG_FIRST }, \
674 { "%1", 1 + GP_REG_FIRST }, \
675 { "%2", 2 + GP_REG_FIRST }, \
676 { "%3", 3 + GP_REG_FIRST }, \
677 { "%4", 4 + GP_REG_FIRST }, \
678 { "%5", 5 + GP_REG_FIRST }, \
679 { "%6", 6 + GP_REG_FIRST }, \
680 { "%7", 7 + GP_REG_FIRST }, \
681 { "%8", 8 + GP_REG_FIRST }, \
682 { "%9", 9 + GP_REG_FIRST }, \
683 { "%10", 10 + GP_REG_FIRST }, \
684 { "%11", 11 + GP_REG_FIRST }, \
685 { "%12", 12 + GP_REG_FIRST }, \
686 { "%13", 13 + GP_REG_FIRST }, \
687 { "%14", 14 + GP_REG_FIRST }, \
688 { "%15", 15 + GP_REG_FIRST }, \
689 { "%16", 16 + GP_REG_FIRST }, \
690 { "%17", 17 + GP_REG_FIRST }, \
691 { "%18", 18 + GP_REG_FIRST }, \
692 { "%19", 19 + GP_REG_FIRST }, \
693 { "%20", 20 + GP_REG_FIRST }, \
694 { "%21", 21 + GP_REG_FIRST }, \
695 { "%22", 22 + GP_REG_FIRST }, \
696 { "%23", 23 + GP_REG_FIRST }, \
697 { "%24", 24 + GP_REG_FIRST }, \
698 { "%25", 25 + GP_REG_FIRST }, \
699 { "%26", 26 + GP_REG_FIRST }, \
700 { "%27", 27 + GP_REG_FIRST }, \
701 { "%28", 28 + GP_REG_FIRST }, \
702 { "%29", 29 + GP_REG_FIRST }, \
703 { "%30", 27 + GP_REG_FIRST }, \
704 { "%31", 31 + GP_REG_FIRST }, \
705 { "%rap", 32 + GP_REG_FIRST }, \
708 /* Check if the current insn needs a nop in front of it
709 because of load delays, and also update the delay slot statistics. */
711 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
712 final_prescan_insn (INSN, OPVEC, NOPERANDS)
714 /* See iq2000.c for the IQ2000 specific codes. */
715 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
717 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) iq2000_print_operand_punct[CODE]
719 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
721 #define DBR_OUTPUT_SEQEND(STREAM) \
724 fputs ("\n", STREAM); \
728 #define LOCAL_LABEL_PREFIX "$"
730 #define USER_LABEL_PREFIX ""
733 /* Output of dispatch tables. */
735 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
738 fprintf (STREAM, "\t%s\t%sL%d\n", \
739 Pmode == DImode ? ".dword" : ".word", \
740 LOCAL_LABEL_PREFIX, VALUE); \
744 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
745 fprintf (STREAM, "\t%s\t%sL%d\n", \
746 Pmode == DImode ? ".dword" : ".word", \
747 LOCAL_LABEL_PREFIX, \
751 /* Assembler Commands for Alignment. */
753 #undef ASM_OUTPUT_SKIP
754 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
755 fprintf (STREAM, "\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n", \
756 (unsigned HOST_WIDE_INT)(SIZE))
758 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
760 fprintf (STREAM, "\t.balign %d\n", 1<<(LOG))
763 /* Macros Affecting all Debug Formats. */
765 #define DEBUGGER_AUTO_OFFSET(X) \
766 iq2000_debugger_offset (X, (HOST_WIDE_INT) 0)
768 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
769 iq2000_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
771 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
773 #define DWARF2_DEBUGGING_INFO 1
776 /* Miscellaneous Parameters. */
778 #define CASE_VECTOR_MODE SImode
780 #define WORD_REGISTER_OPERATIONS
782 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
786 #define MAX_MOVE_MAX 8
788 #define SHIFT_COUNT_TRUNCATED 1
790 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
792 #define STORE_FLAG_VALUE 1
796 #define FUNCTION_MODE SImode
798 /* Standard GCC variables that we reference. */
800 extern char call_used_regs[];
802 /* IQ2000 external variables defined in iq2000.c. */
804 /* Comparison type. */
807 CMP_SI, /* Compare four byte integers. */
808 CMP_DI, /* Compare eight byte integers. */
809 CMP_SF, /* Compare single precision floats. */
810 CMP_DF, /* Compare double precision floats. */
811 CMP_MAX /* Max comparison type. */
814 /* Types of delay slot. */
817 DELAY_NONE, /* No delay slot. */
818 DELAY_LOAD, /* Load from memory delay. */
819 DELAY_FCMP /* Delay after doing c.<xx>.{d,s}. */
822 /* Which processor to schedule for. */
831 /* Recast the cpu class to be the cpu attribute. */
832 #define iq2000_cpu_attr ((enum attr_cpu) iq2000_tune)
834 #define BITMASK_UPPER16 ((unsigned long) 0xffff << 16) /* 0xffff0000 */
835 #define BITMASK_LOWER16 ((unsigned long) 0xffff) /* 0x0000ffff */
838 #define GENERATE_BRANCHLIKELY (ISA_HAS_BRANCHLIKELY)
840 /* Macros to decide whether certain features are available or not,
841 depending on the instruction set architecture level. */
843 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
845 /* ISA has branch likely instructions. */
846 #define ISA_HAS_BRANCHLIKELY (iq2000_isa == 1)
852 /* The mapping from gcc register number to DWARF 2 CFA column number. */
853 #define DWARF_FRAME_REGNUM(REG) (REG)
855 /* The DWARF 2 CFA column which tracks the return address. */
856 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
858 /* Describe how we implement __builtin_eh_return. */
859 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
861 /* The EH_RETURN_STACKADJ_RTX macro returns RTL which describes the
862 location used to store the amount to adjust the stack. This is
863 usually a register that is available from end of the function's body
864 to the end of the epilogue. Thus, this cannot be a register used as a
865 temporary by the epilogue.
867 This must be an integer register. */
868 #define EH_RETURN_STACKADJ_REGNO 3
869 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
871 /* The EH_RETURN_HANDLER_RTX macro returns RTL which describes the
872 location used to store the address the processor should jump to
873 catch exception. This is usually a registers that is available from
874 end of the function's body to the end of the epilogue. Thus, this
875 cannot be a register used as a temporary by the epilogue.
877 This must be an address register. */
878 #define EH_RETURN_HANDLER_REGNO 26
879 #define EH_RETURN_HANDLER_RTX \
880 gen_rtx_REG (Pmode, EH_RETURN_HANDLER_REGNO)
882 /* Offsets recorded in opcodes are a multiple of this alignment factor. */
883 #define DWARF_CIE_DATA_ALIGNMENT 4
885 /* For IQ2000, width of a floating point register. */
886 #define UNITS_PER_FPREG 4
888 /* Force right-alignment for small varargs in 32 bit little_endian mode */
890 #define PAD_VARARGS_DOWN !BYTES_BIG_ENDIAN
892 /* Internal macros to classify a register number as to whether it's a
893 general purpose register, a floating point register, a
894 multiply/divide register, or a status register. */
896 #define GP_REG_FIRST 0
897 #define GP_REG_LAST 31
898 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
900 #define RAP_REG_NUM 32
901 #define AT_REGNUM (GP_REG_FIRST + 1)
903 #define GP_REG_P(REGNO) \
904 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
906 /* IQ2000 registers used in prologue/epilogue code when the stack frame
907 is larger than 32K bytes. These registers must come from the
908 scratch register set, and not used for passing and returning
909 arguments and any other information used in the calling sequence. */
911 #define IQ2000_TEMP1_REGNUM (GP_REG_FIRST + 12)
912 #define IQ2000_TEMP2_REGNUM (GP_REG_FIRST + 13)
914 /* This macro is used later on in the file. */
915 #define GR_REG_CLASS_P(CLASS) \
918 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
919 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
921 /* Certain machines have the property that some registers cannot be
922 copied to some other registers without using memory. Define this
923 macro on those machines to be a C expression that is nonzero if
924 objects of mode MODE in registers of CLASS1 can only be copied to
925 registers of class CLASS2 by storing a register of CLASS1 into
926 memory and loading that memory location into a register of CLASS2.
928 Do not define this macro if its value would always be zero. */
930 /* Return the maximum number of consecutive registers
931 needed to represent mode MODE in a register of class CLASS. */
933 #define CLASS_UNITS(mode, size) \
934 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
936 /* If defined, gives a class of registers that cannot be used as the
937 operand of a SUBREG that changes the mode of the object illegally. */
939 #define CLASS_CANNOT_CHANGE_MODE 0
941 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
943 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
944 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
946 /* Make sure 4 words are always allocated on the stack. */
948 #ifndef STACK_ARGS_ADJUST
949 #define STACK_ARGS_ADJUST(SIZE) \
951 if (SIZE.constant < 4 * UNITS_PER_WORD) \
952 SIZE.constant = 4 * UNITS_PER_WORD; \
957 /* Symbolic macros for the registers used to return integer and floating
960 #define GP_RETURN (GP_REG_FIRST + 2)
962 /* Symbolic macros for the first/last argument registers. */
964 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
965 #define GP_ARG_LAST (GP_REG_FIRST + 11)
967 #define MAX_ARGS_IN_REGISTERS 8
970 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
972 #define MUST_SAVE_REGISTER(regno) \
973 ((df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
974 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
975 || (regno == (GP_REG_FIRST + 31) && df_regs_ever_live_p (GP_REG_FIRST + 31)))
977 /* ALIGN FRAMES on double word boundaries */
978 #ifndef IQ2000_STACK_ALIGN
979 #define IQ2000_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
983 /* These assume that REGNO is a hard or pseudo reg number.
984 They give nonzero only if REGNO is a hard reg of the suitable class
985 or a pseudo reg currently allocated to a suitable hard reg.
986 These definitions are NOT overridden anywhere. */
988 #define BASE_REG_P(regno, mode) \
991 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
992 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
995 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
996 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
998 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
999 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
1001 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1002 and check its validity for a certain class.
1003 We have two alternate definitions for each of them.
1004 The usual definition accepts all pseudo regs; the other rejects them all.
1005 The symbol REG_OK_STRICT causes the latter definition to be used.
1007 Most source files want to accept pseudo regs in the hope that
1008 they will get allocated to the class that the insn wants them to be in.
1009 Some source files that are used after register allocation
1010 need to be strict. */
1012 #ifndef REG_OK_STRICT
1013 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1014 iq2000_reg_mode_ok_for_base_p (X, MODE, 0)
1016 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1017 iq2000_reg_mode_ok_for_base_p (X, MODE, 1)
1021 #define GO_PRINTF(x) fprintf (stderr, (x))
1022 #define GO_PRINTF2(x,y) fprintf (stderr, (x), (y))
1023 #define GO_DEBUG_RTX(x) debug_rtx (x)
1026 #define GO_PRINTF(x)
1027 #define GO_PRINTF2(x,y)
1028 #define GO_DEBUG_RTX(x)
1031 /* If defined, modifies the length assigned to instruction INSN as a
1032 function of the context in which it is used. LENGTH is an lvalue
1033 that contains the initially computed length of the insn and should
1034 be updated with the correct length of the insn. */
1035 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1036 ((LENGTH) = iq2000_adjust_insn_length ((INSN), (LENGTH)))
1041 /* How to tell the debugger about changes of source files. */
1043 #ifndef SET_FILE_NUMBER
1044 #define SET_FILE_NUMBER() ++ num_source_filenames
1047 /* This is how to output a note the debugger telling it the line number
1048 to which the following sequence of instructions corresponds. */
1050 #ifndef LABEL_AFTER_LOC
1051 #define LABEL_AFTER_LOC(STREAM)
1055 /* Default to -G 8 */
1056 #ifndef IQ2000_DEFAULT_GVALUE
1057 #define IQ2000_DEFAULT_GVALUE 8
1060 #define SDATA_SECTION_ASM_OP "\t.sdata" /* Small data. */
1063 /* List of all IQ2000 punctuation characters used by print_operand. */
1064 extern char iq2000_print_operand_punct[256];
1066 /* The target cpu for optimization and scheduling. */
1067 extern enum processor_type iq2000_tune;
1069 /* Which instruction set architecture to use. */
1070 extern int iq2000_isa;
1072 /* Cached operands, and operator to compare for use in set/branch/trap
1073 on condition codes. */
1074 extern rtx branch_cmp[2];
1076 /* What type of branch to use. */
1077 extern enum cmp_type branch_type;
1079 enum iq2000_builtins
1081 IQ2000_BUILTIN_ADO16,
1082 IQ2000_BUILTIN_CFC0,
1083 IQ2000_BUILTIN_CFC1,
1084 IQ2000_BUILTIN_CFC2,
1085 IQ2000_BUILTIN_CFC3,
1086 IQ2000_BUILTIN_CHKHDR,
1087 IQ2000_BUILTIN_CTC0,
1088 IQ2000_BUILTIN_CTC1,
1089 IQ2000_BUILTIN_CTC2,
1090 IQ2000_BUILTIN_CTC3,
1092 IQ2000_BUILTIN_LUC32L,
1093 IQ2000_BUILTIN_LUC64,
1094 IQ2000_BUILTIN_LUC64L,
1096 IQ2000_BUILTIN_LULCK,
1097 IQ2000_BUILTIN_LUM32,
1098 IQ2000_BUILTIN_LUM32L,
1099 IQ2000_BUILTIN_LUM64,
1100 IQ2000_BUILTIN_LUM64L,
1102 IQ2000_BUILTIN_LURL,
1103 IQ2000_BUILTIN_MFC0,
1104 IQ2000_BUILTIN_MFC1,
1105 IQ2000_BUILTIN_MFC2,
1106 IQ2000_BUILTIN_MFC3,
1107 IQ2000_BUILTIN_MRGB,
1108 IQ2000_BUILTIN_MTC0,
1109 IQ2000_BUILTIN_MTC1,
1110 IQ2000_BUILTIN_MTC2,
1111 IQ2000_BUILTIN_MTC3,
1112 IQ2000_BUILTIN_PKRL,
1116 IQ2000_BUILTIN_SRRD,
1117 IQ2000_BUILTIN_SRRDL,
1118 IQ2000_BUILTIN_SRULC,
1119 IQ2000_BUILTIN_SRULCK,
1120 IQ2000_BUILTIN_SRWR,
1121 IQ2000_BUILTIN_SRWRU,
1122 IQ2000_BUILTIN_TRAPQF,
1123 IQ2000_BUILTIN_TRAPQFL,
1124 IQ2000_BUILTIN_TRAPQN,
1125 IQ2000_BUILTIN_TRAPQNE,
1126 IQ2000_BUILTIN_TRAPRE,
1127 IQ2000_BUILTIN_TRAPREL,
1132 IQ2000_BUILTIN_SYSCALL