1 ;; IA-64 machine description for vector operations.
2 ;; Copyright (C) 2004, 2005, 2007, 2010 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
21 ;; Integer vector operations
23 (define_mode_iterator VECINT [V8QI V4HI V2SI])
24 (define_mode_iterator VECINT12 [V8QI V4HI])
25 (define_mode_iterator VECINT24 [V4HI V2SI])
26 (define_mode_attr vecsize [(V8QI "1") (V4HI "2") (V2SI "4")])
27 (define_mode_attr vecwider [(V8QI "V4HI") (V4HI "V2SI")])
29 (define_expand "mov<mode>"
30 [(set (match_operand:VECINT 0 "general_operand" "")
31 (match_operand:VECINT 1 "general_operand" ""))]
34 rtx op1 = ia64_expand_move (operands[0], operands[1]);
40 (define_insn "*mov<mode>_internal"
41 [(set (match_operand:VECINT 0 "destination_operand"
42 "=r,r,r,r,m ,*f ,*f,Q ,r ,*f")
43 (match_operand:VECINT 1 "move_operand"
44 "rU,W,i,m,rU,U*f,Q ,*f,*f,r "))]
45 "ia64_move_ok (operands[0], operands[1])"
57 [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,fmisc,fld,stf,frfr,tofr")])
59 (define_insn "one_cmpl<mode>2"
60 [(set (match_operand:VECINT 0 "gr_register_operand" "=r")
61 (not:VECINT (match_operand:VECINT 1 "gr_register_operand" "r")))]
64 [(set_attr "itanium_class" "ilog")])
66 (define_insn "and<mode>3"
67 [(set (match_operand:VECINT 0 "grfr_register_operand" "=r,*f")
69 (match_operand:VECINT 1 "grfr_register_operand" "r,*f")
70 (match_operand:VECINT 2 "grfr_reg_or_8bit_operand" "r,*f")))]
75 [(set_attr "itanium_class" "ilog,fmisc")])
77 (define_insn "*andnot<mode>"
78 [(set (match_operand:VECINT 0 "grfr_register_operand" "=r,*f")
80 (not:VECINT (match_operand:VECINT 1 "grfr_register_operand" "r,*f"))
81 (match_operand:VECINT 2 "grfr_reg_or_8bit_operand" "r,*f")))]
86 [(set_attr "itanium_class" "ilog,fmisc")])
88 (define_insn "ior<mode>3"
89 [(set (match_operand:VECINT 0 "grfr_register_operand" "=r,*f")
91 (match_operand:VECINT 1 "grfr_register_operand" "r,*f")
92 (match_operand:VECINT 2 "grfr_reg_or_8bit_operand" "r,*f")))]
97 [(set_attr "itanium_class" "ilog,fmisc")])
99 (define_insn "xor<mode>3"
100 [(set (match_operand:VECINT 0 "grfr_register_operand" "=r,*f")
102 (match_operand:VECINT 1 "grfr_register_operand" "r,*f")
103 (match_operand:VECINT 2 "grfr_reg_or_8bit_operand" "r,*f")))]
108 [(set_attr "itanium_class" "ilog,fmisc")])
110 (define_insn "neg<mode>2"
111 [(set (match_operand:VECINT 0 "gr_register_operand" "=r")
112 (neg:VECINT (match_operand:VECINT 1 "gr_register_operand" "r")))]
114 "psub<vecsize> %0 = r0, %1"
115 [(set_attr "itanium_class" "mmalua")])
117 (define_insn "add<mode>3"
118 [(set (match_operand:VECINT 0 "gr_register_operand" "=r")
119 (plus:VECINT (match_operand:VECINT 1 "gr_register_operand" "r")
120 (match_operand:VECINT 2 "gr_register_operand" "r")))]
122 "padd<vecsize> %0 = %1, %2"
123 [(set_attr "itanium_class" "mmalua")])
125 (define_insn "*ssadd<mode>3"
126 [(set (match_operand:VECINT12 0 "gr_register_operand" "=r")
128 (match_operand:VECINT12 1 "gr_register_operand" "r")
129 (match_operand:VECINT12 2 "gr_register_operand" "r")))]
131 "padd<vecsize>.sss %0 = %1, %2"
132 [(set_attr "itanium_class" "mmalua")])
134 (define_insn "*usadd<mode>3"
135 [(set (match_operand:VECINT12 0 "gr_register_operand" "=r")
137 (match_operand:VECINT12 1 "gr_register_operand" "r")
138 (match_operand:VECINT12 2 "gr_register_operand" "r")))]
140 "padd<vecsize>.uuu %0 = %1, %2"
141 [(set_attr "itanium_class" "mmalua")])
143 (define_insn "sub<mode>3"
144 [(set (match_operand:VECINT 0 "gr_register_operand" "=r")
145 (minus:VECINT (match_operand:VECINT 1 "gr_register_operand" "r")
146 (match_operand:VECINT 2 "gr_register_operand" "r")))]
148 "psub<vecsize> %0 = %1, %2"
149 [(set_attr "itanium_class" "mmalua")])
151 (define_insn "*sssub<mode>3"
152 [(set (match_operand:VECINT12 0 "gr_register_operand" "=r")
154 (match_operand:VECINT12 1 "gr_register_operand" "r")
155 (match_operand:VECINT12 2 "gr_register_operand" "r")))]
157 "psub<vecsize>.sss %0 = %1, %2"
158 [(set_attr "itanium_class" "mmalua")])
160 (define_insn "*ussub<mode>3"
161 [(set (match_operand:VECINT12 0 "gr_register_operand" "=r")
163 (match_operand:VECINT12 1 "gr_register_operand" "r")
164 (match_operand:VECINT12 2 "gr_register_operand" "r")))]
166 "psub<vecsize>.uuu %0 = %1, %2"
167 [(set_attr "itanium_class" "mmalua")])
169 (define_expand "mulv8qi3"
170 [(set (match_operand:V8QI 0 "gr_register_operand" "")
171 (mult:V8QI (match_operand:V8QI 1 "gr_register_operand" "r")
172 (match_operand:V8QI 2 "gr_register_operand" "r")))]
175 rtx r1, l1, r2, l2, rm, lm;
177 r1 = gen_reg_rtx (V4HImode);
178 l1 = gen_reg_rtx (V4HImode);
179 r2 = gen_reg_rtx (V4HImode);
180 l2 = gen_reg_rtx (V4HImode);
182 /* Zero-extend the QImode elements into two words of HImode elements
183 by interleaving them with zero bytes. */
184 emit_insn (gen_mix1_r (gen_lowpart (V8QImode, r1),
185 operands[1], CONST0_RTX (V8QImode)));
186 emit_insn (gen_mix1_r (gen_lowpart (V8QImode, r2),
187 operands[2], CONST0_RTX (V8QImode)));
188 emit_insn (gen_mix1_l (gen_lowpart (V8QImode, l1),
189 operands[1], CONST0_RTX (V8QImode)));
190 emit_insn (gen_mix1_l (gen_lowpart (V8QImode, l2),
191 operands[2], CONST0_RTX (V8QImode)));
194 rm = gen_reg_rtx (V4HImode);
195 lm = gen_reg_rtx (V4HImode);
196 emit_insn (gen_mulv4hi3 (rm, r1, r2));
197 emit_insn (gen_mulv4hi3 (lm, l1, l2));
199 /* Zap the high order bytes of the HImode elements by overwriting those
200 in one part with the low order bytes of the other. */
201 emit_insn (gen_mix1_r (operands[0],
202 gen_lowpart (V8QImode, rm),
203 gen_lowpart (V8QImode, lm)));
207 (define_expand "vec_widen_umult_lo_v8qi"
208 [(match_operand:V4HI 0 "gr_register_operand" "")
209 (match_operand:V8QI 1 "gr_register_operand" "")
210 (match_operand:V8QI 2 "gr_register_operand" "")]
213 rtx op1 = gen_reg_rtx (V4HImode);
214 rtx op2 = gen_reg_rtx (V4HImode);
215 emit_insn (gen_vec_unpacku_lo_v8qi (op1, operands[1]));
216 emit_insn (gen_vec_unpacku_lo_v8qi (op2, operands[2]));
217 emit_insn (gen_mulv4hi3 (operands[0], op1, op2));
221 (define_expand "vec_widen_umult_hi_v8qi"
222 [(match_operand:V4HI 0 "gr_register_operand" "")
223 (match_operand:V8QI 1 "gr_register_operand" "")
224 (match_operand:V8QI 2 "gr_register_operand" "")]
227 rtx op1 = gen_reg_rtx (V4HImode);
228 rtx op2 = gen_reg_rtx (V4HImode);
229 emit_insn (gen_vec_unpacku_hi_v8qi (op1, operands[1]));
230 emit_insn (gen_vec_unpacku_hi_v8qi (op2, operands[2]));
231 emit_insn (gen_mulv4hi3 (operands[0], op1, op2));
235 (define_expand "vec_widen_smult_lo_v8qi"
236 [(match_operand:V4HI 0 "gr_register_operand" "")
237 (match_operand:V8QI 1 "gr_register_operand" "")
238 (match_operand:V8QI 2 "gr_register_operand" "")]
241 rtx op1 = gen_reg_rtx (V4HImode);
242 rtx op2 = gen_reg_rtx (V4HImode);
243 emit_insn (gen_vec_unpacks_lo_v8qi (op1, operands[1]));
244 emit_insn (gen_vec_unpacks_lo_v8qi (op2, operands[2]));
245 emit_insn (gen_mulv4hi3 (operands[0], op1, op2));
249 (define_expand "vec_widen_smult_hi_v8qi"
250 [(match_operand:V4HI 0 "gr_register_operand" "")
251 (match_operand:V8QI 1 "gr_register_operand" "")
252 (match_operand:V8QI 2 "gr_register_operand" "")]
255 rtx op1 = gen_reg_rtx (V4HImode);
256 rtx op2 = gen_reg_rtx (V4HImode);
257 emit_insn (gen_vec_unpacks_hi_v8qi (op1, operands[1]));
258 emit_insn (gen_vec_unpacks_hi_v8qi (op2, operands[2]));
259 emit_insn (gen_mulv4hi3 (operands[0], op1, op2));
263 (define_insn "mulv4hi3"
264 [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
265 (mult:V4HI (match_operand:V4HI 1 "gr_register_operand" "r")
266 (match_operand:V4HI 2 "gr_register_operand" "r")))]
268 "pmpyshr2 %0 = %1, %2, 0"
269 [(set_attr "itanium_class" "mmmul")])
271 (define_insn "pmpyshr2"
272 [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
277 (match_operand:V4HI 1 "gr_register_operand" "r"))
279 (match_operand:V4HI 2 "gr_register_operand" "r")))
280 (match_operand:SI 3 "pmpyshr_operand" "n"))))]
282 "pmpyshr2 %0 = %1, %2, %3"
283 [(set_attr "itanium_class" "mmmul")])
285 (define_insn "pmpyshr2_u"
286 [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
291 (match_operand:V4HI 1 "gr_register_operand" "r"))
293 (match_operand:V4HI 2 "gr_register_operand" "r")))
294 (match_operand:SI 3 "pmpyshr_operand" "n"))))]
296 "pmpyshr2.u %0 = %1, %2, %3"
297 [(set_attr "itanium_class" "mmmul")])
299 (define_insn "pmpy2_r"
300 [(set (match_operand:V2SI 0 "gr_register_operand" "=r")
304 (match_operand:V4HI 1 "gr_register_operand" "r"))
305 (parallel [(const_int 0) (const_int 2)]))
308 (match_operand:V4HI 2 "gr_register_operand" "r"))
309 (parallel [(const_int 0) (const_int 2)]))))]
311 "pmpy2.r %0 = %1, %2"
312 [(set_attr "itanium_class" "mmshf")])
314 (define_insn "pmpy2_l"
315 [(set (match_operand:V2SI 0 "gr_register_operand" "=r")
319 (match_operand:V4HI 1 "gr_register_operand" "r"))
320 (parallel [(const_int 1) (const_int 3)]))
323 (match_operand:V4HI 2 "gr_register_operand" "r"))
324 (parallel [(const_int 1) (const_int 3)]))))]
326 "pmpy2.l %0 = %1, %2"
327 [(set_attr "itanium_class" "mmshf")])
329 (define_expand "vec_widen_smult_lo_v4hi"
330 [(match_operand:V2SI 0 "gr_register_operand" "")
331 (match_operand:V4HI 1 "gr_register_operand" "")
332 (match_operand:V4HI 2 "gr_register_operand" "")]
335 ia64_expand_widen_mul_v4hi (operands, false, false);
339 (define_expand "vec_widen_smult_hi_v4hi"
340 [(match_operand:V2SI 0 "gr_register_operand" "")
341 (match_operand:V4HI 1 "gr_register_operand" "")
342 (match_operand:V4HI 2 "gr_register_operand" "")]
345 ia64_expand_widen_mul_v4hi (operands, false, true);
349 (define_expand "vec_widen_umult_lo_v4hi"
350 [(match_operand:V2SI 0 "gr_register_operand" "")
351 (match_operand:V4HI 1 "gr_register_operand" "")
352 (match_operand:V4HI 2 "gr_register_operand" "")]
355 ia64_expand_widen_mul_v4hi (operands, true, false);
359 (define_expand "vec_widen_umult_hi_v4hi"
360 [(match_operand:V2SI 0 "gr_register_operand" "")
361 (match_operand:V4HI 1 "gr_register_operand" "")
362 (match_operand:V4HI 2 "gr_register_operand" "")]
365 ia64_expand_widen_mul_v4hi (operands, true, true);
369 (define_expand "mulv2si3"
370 [(set (match_operand:V2SI 0 "gr_register_operand" "")
371 (mult:V2SI (match_operand:V2SI 1 "gr_register_operand" "r")
372 (match_operand:V2SI 2 "gr_register_operand" "r")))]
375 rtx t0, t1, t2, t3, t4, t5, t6, t7, x;
376 rtx op1h = gen_lowpart (V4HImode, operands[1]);
377 rtx op2h = gen_lowpart (V4HImode, operands[2]);
379 t0 = gen_reg_rtx (V4HImode);
380 t1 = gen_reg_rtx (V4HImode);
381 t2 = gen_reg_rtx (V4HImode);
382 t3 = gen_reg_rtx (V4HImode);
383 t4 = gen_reg_rtx (V2SImode);
384 t5 = gen_reg_rtx (V2SImode);
385 t6 = gen_reg_rtx (V2SImode);
386 t7 = gen_reg_rtx (V2SImode);
388 /* Consider the HImode components of op1 = DCBA, op2 = ZYXW.
389 Consider .l and .h suffixes below the low and high 16 bits
390 of the full 32-bit product. */
393 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (4, const1_rtx, const0_rtx,
394 GEN_INT (3), const2_rtx));
395 x = gen_rtx_VEC_SELECT (V4HImode, op1h, x);
396 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
398 /* T1 = DZ.l, CY.l, BX.l, AW.l. */
399 emit_insn (gen_mulv4hi3 (t1, op1h, op2h));
401 /* T2 = DZ.h, CY.h, BX.h, AW.h. */
402 emit_insn (gen_pmpyshr2_u (t2, op1h, op2h, GEN_INT (16)));
404 /* T3 = CZ.l, DY.l, AX.l, BW.l. */
405 emit_insn (gen_mulv4hi3 (t3, t0, op2h));
407 /* T4 = CY.h, CY.l, AW.h, AW.l = CY, AW. */
408 emit_insn (gen_mix2_r (gen_lowpart (V4HImode, t4), t1, t2));
410 /* T5 = CZ.l, 0, AX.l, 0 = CZ << 16, AX << 16. */
411 emit_insn (gen_mix2_l (gen_lowpart (V4HImode, t5),
412 CONST0_RTX (V4HImode), t3));
414 /* T6 = DY.l, 0, BW.l, 0 = DY << 16, BW << 16. */
415 emit_insn (gen_mix2_r (gen_lowpart (V4HImode, t6),
416 CONST0_RTX (V4HImode), t3));
418 emit_insn (gen_addv2si3 (t7, t4, t5));
419 emit_insn (gen_addv2si3 (operands[0], t6, t7));
423 (define_expand "umax<mode>3"
424 [(set (match_operand:VECINT 0 "gr_register_operand" "")
425 (umax:VECINT (match_operand:VECINT 1 "gr_register_operand" "")
426 (match_operand:VECINT 2 "gr_register_operand" "")))]
429 if (ia64_expand_vecint_minmax (UMAX, <MODE>mode, operands))
433 (define_expand "smax<mode>3"
434 [(set (match_operand:VECINT 0 "gr_register_operand" "")
435 (smax:VECINT (match_operand:VECINT 1 "gr_reg_or_0_operand" "")
436 (match_operand:VECINT 2 "gr_reg_or_0_operand" "")))]
439 if (ia64_expand_vecint_minmax (SMAX, <MODE>mode, operands))
443 (define_expand "umin<mode>3"
444 [(set (match_operand:VECINT 0 "gr_register_operand" "")
445 (umin:VECINT (match_operand:VECINT 1 "gr_register_operand" "")
446 (match_operand:VECINT 2 "gr_register_operand" "")))]
449 if (ia64_expand_vecint_minmax (UMIN, <MODE>mode, operands))
453 (define_expand "smin<mode>3"
454 [(set (match_operand:VECINT 0 "gr_register_operand" "")
455 (smin:VECINT (match_operand:VECINT 1 "gr_reg_or_0_operand" "")
456 (match_operand:VECINT 2 "gr_reg_or_0_operand" "")))]
459 if (ia64_expand_vecint_minmax (SMIN, <MODE>mode, operands))
463 (define_insn "*umaxv8qi3"
464 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
465 (umax:V8QI (match_operand:V8QI 1 "gr_register_operand" "r")
466 (match_operand:V8QI 2 "gr_register_operand" "r")))]
468 "pmax1.u %0 = %1, %2"
469 [(set_attr "itanium_class" "mmshf")])
471 (define_insn "*smaxv4hi3"
472 [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
473 (smax:V4HI (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU")
474 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU")))]
476 "pmax2 %0 = %r1, %r2"
477 [(set_attr "itanium_class" "mmshf")])
479 (define_insn "*uminv8qi3"
480 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
481 (umin:V8QI (match_operand:V8QI 1 "gr_register_operand" "r")
482 (match_operand:V8QI 2 "gr_register_operand" "r")))]
484 "pmin1.u %0 = %1, %2"
485 [(set_attr "itanium_class" "mmshf")])
487 (define_insn "*sminv4hi3"
488 [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
489 (smin:V4HI (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU")
490 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU")))]
492 "pmin2 %0 = %r1, %r2"
493 [(set_attr "itanium_class" "mmshf")])
495 (define_insn "ashl<mode>3"
496 [(set (match_operand:VECINT24 0 "gr_register_operand" "=r")
498 (match_operand:VECINT24 1 "gr_register_operand" "r")
499 (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))]
501 "pshl<vecsize> %0 = %1, %2"
502 [(set_attr "itanium_class" "mmshf")])
504 (define_insn "ashr<mode>3"
505 [(set (match_operand:VECINT24 0 "gr_register_operand" "=r")
507 (match_operand:VECINT24 1 "gr_register_operand" "r")
508 (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))]
510 "pshr<vecsize> %0 = %1, %2"
511 [(set_attr "itanium_class" "mmshf")])
513 (define_insn "lshr<mode>3"
514 [(set (match_operand:VECINT24 0 "gr_register_operand" "=r")
516 (match_operand:VECINT24 1 "gr_register_operand" "r")
517 (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))]
519 "pshr<vecsize>.u %0 = %1, %2"
520 [(set_attr "itanium_class" "mmshf")])
522 (define_expand "vec_shl_<mode>"
523 [(set (match_operand:VECINT 0 "gr_register_operand" "")
524 (ashift:DI (match_operand:VECINT 1 "gr_register_operand" "")
525 (match_operand:DI 2 "gr_reg_or_6bit_operand" "")))]
528 operands[0] = gen_lowpart (DImode, operands[0]);
529 operands[1] = gen_lowpart (DImode, operands[1]);
532 (define_expand "vec_shr_<mode>"
533 [(set (match_operand:VECINT 0 "gr_register_operand" "")
534 (lshiftrt:DI (match_operand:VECINT 1 "gr_register_operand" "")
535 (match_operand:DI 2 "gr_reg_or_6bit_operand" "")))]
538 operands[0] = gen_lowpart (DImode, operands[0]);
539 operands[1] = gen_lowpart (DImode, operands[1]);
542 (define_expand "widen_usumv8qi3"
543 [(match_operand:V4HI 0 "gr_register_operand" "")
544 (match_operand:V8QI 1 "gr_register_operand" "")
545 (match_operand:V4HI 2 "gr_register_operand" "")]
548 ia64_expand_widen_sum (operands, true);
552 (define_expand "widen_usumv4hi3"
553 [(match_operand:V2SI 0 "gr_register_operand" "")
554 (match_operand:V4HI 1 "gr_register_operand" "")
555 (match_operand:V2SI 2 "gr_register_operand" "")]
558 ia64_expand_widen_sum (operands, true);
562 (define_expand "widen_ssumv8qi3"
563 [(match_operand:V4HI 0 "gr_register_operand" "")
564 (match_operand:V8QI 1 "gr_register_operand" "")
565 (match_operand:V4HI 2 "gr_register_operand" "")]
568 ia64_expand_widen_sum (operands, false);
572 (define_expand "widen_ssumv4hi3"
573 [(match_operand:V2SI 0 "gr_register_operand" "")
574 (match_operand:V4HI 1 "gr_register_operand" "")
575 (match_operand:V2SI 2 "gr_register_operand" "")]
578 ia64_expand_widen_sum (operands, false);
582 (define_expand "udot_prodv8qi"
583 [(match_operand:V2SI 0 "gr_register_operand" "")
584 (match_operand:V8QI 1 "gr_register_operand" "")
585 (match_operand:V8QI 2 "gr_register_operand" "")
586 (match_operand:V2SI 3 "gr_register_operand" "")]
589 ia64_expand_dot_prod_v8qi (operands, true);
593 (define_expand "sdot_prodv8qi"
594 [(match_operand:V2SI 0 "gr_register_operand" "")
595 (match_operand:V8QI 1 "gr_register_operand" "")
596 (match_operand:V8QI 2 "gr_register_operand" "")
597 (match_operand:V2SI 3 "gr_register_operand" "")]
600 ia64_expand_dot_prod_v8qi (operands, false);
604 (define_expand "sdot_prodv4hi"
605 [(match_operand:V2SI 0 "gr_register_operand" "")
606 (match_operand:V4HI 1 "gr_register_operand" "")
607 (match_operand:V4HI 2 "gr_register_operand" "")
608 (match_operand:V2SI 3 "gr_register_operand" "")]
613 r = gen_reg_rtx (V2SImode);
614 l = gen_reg_rtx (V2SImode);
615 t = gen_reg_rtx (V2SImode);
617 emit_insn (gen_pmpy2_r (r, operands[1], operands[2]));
618 emit_insn (gen_pmpy2_l (l, operands[1], operands[2]));
619 emit_insn (gen_addv2si3 (t, r, operands[3]));
620 emit_insn (gen_addv2si3 (operands[0], t, l));
624 (define_expand "vcond<mode>"
625 [(set (match_operand:VECINT 0 "gr_register_operand" "")
628 [(match_operand:VECINT 4 "gr_reg_or_0_operand" "")
629 (match_operand:VECINT 5 "gr_reg_or_0_operand" "")])
630 (match_operand:VECINT 1 "gr_reg_or_0_operand" "")
631 (match_operand:VECINT 2 "gr_reg_or_0_operand" "")))]
634 ia64_expand_vecint_cmov (operands);
638 (define_expand "vcondu<mode>"
639 [(set (match_operand:VECINT 0 "gr_register_operand" "")
642 [(match_operand:VECINT 4 "gr_reg_or_0_operand" "")
643 (match_operand:VECINT 5 "gr_reg_or_0_operand" "")])
644 (match_operand:VECINT 1 "gr_reg_or_0_operand" "")
645 (match_operand:VECINT 2 "gr_reg_or_0_operand" "")))]
648 ia64_expand_vecint_cmov (operands);
652 (define_insn "*cmpeq_<mode>"
653 [(set (match_operand:VECINT 0 "gr_register_operand" "=r")
654 (eq:VECINT (match_operand:VECINT 1 "gr_reg_or_0_operand" "rU")
655 (match_operand:VECINT 2 "gr_reg_or_0_operand" "rU")))]
657 "pcmp<vecsize>.eq %0 = %r1, %r2"
658 [(set_attr "itanium_class" "mmalua")])
660 (define_insn "*cmpgt_<mode>"
661 [(set (match_operand:VECINT 0 "gr_register_operand" "=r")
662 (gt:VECINT (match_operand:VECINT 1 "gr_reg_or_0_operand" "rU")
663 (match_operand:VECINT 2 "gr_reg_or_0_operand" "rU")))]
665 "pcmp<vecsize>.gt %0 = %r1, %r2"
666 [(set_attr "itanium_class" "mmalua")])
668 (define_insn "vec_pack_ssat_v4hi"
669 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
672 (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU"))
674 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU"))))]
676 "pack2.sss %0 = %r1, %r2"
677 [(set_attr "itanium_class" "mmshf")])
679 (define_insn "vec_pack_usat_v4hi"
680 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
683 (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU"))
685 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU"))))]
687 "pack2.uss %0 = %r1, %r2"
688 [(set_attr "itanium_class" "mmshf")])
690 (define_insn "vec_pack_ssat_v2si"
691 [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
694 (match_operand:V2SI 1 "gr_reg_or_0_operand" "rU"))
696 (match_operand:V2SI 2 "gr_reg_or_0_operand" "rU"))))]
698 "pack4.sss %0 = %r1, %r2"
699 [(set_attr "itanium_class" "mmshf")])
701 (define_insn "vec_interleave_lowv8qi"
702 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
705 (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU")
706 (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU"))
707 (parallel [(const_int 0) (const_int 8)
708 (const_int 1) (const_int 9)
709 (const_int 2) (const_int 10)
710 (const_int 3) (const_int 11)])))]
712 "unpack1.l %0 = %r2, %r1"
713 [(set_attr "itanium_class" "mmshf")])
715 (define_insn "vec_interleave_highv8qi"
716 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
719 (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU")
720 (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU"))
721 (parallel [(const_int 4) (const_int 12)
722 (const_int 5) (const_int 13)
723 (const_int 6) (const_int 14)
724 (const_int 7) (const_int 15)])))]
726 "unpack1.h %0 = %r2, %r1"
727 [(set_attr "itanium_class" "mmshf")])
729 (define_insn "mix1_r"
730 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
733 (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU")
734 (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU"))
735 (parallel [(const_int 0)
744 "mix1.r %0 = %r2, %r1"
745 [(set_attr "itanium_class" "mmshf")])
747 (define_insn "mix1_l"
748 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
751 (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU")
752 (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU"))
753 (parallel [(const_int 1)
762 "mix1.l %0 = %r2, %r1"
763 [(set_attr "itanium_class" "mmshf")])
765 (define_insn "*mux1_rev"
766 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
768 (match_operand:V8QI 1 "gr_register_operand" "r")
769 (parallel [(const_int 7)
779 [(set_attr "itanium_class" "mmshf")])
781 (define_insn "*mux1_mix"
782 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
784 (match_operand:V8QI 1 "gr_register_operand" "r")
785 (parallel [(const_int 0)
795 [(set_attr "itanium_class" "mmshf")])
797 (define_insn "*mux1_shuf"
798 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
800 (match_operand:V8QI 1 "gr_register_operand" "r")
801 (parallel [(const_int 0)
810 "mux1 %0 = %1, @shuf"
811 [(set_attr "itanium_class" "mmshf")])
813 (define_insn "mux1_alt"
814 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
816 (match_operand:V8QI 1 "gr_register_operand" "r")
817 (parallel [(const_int 0)
827 [(set_attr "itanium_class" "mmshf")])
829 (define_insn "*mux1_brcst_v8qi"
830 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
832 (match_operand:V8QI 1 "gr_register_operand" "r")
833 (parallel [(const_int 0)
842 "mux1 %0 = %1, @brcst"
843 [(set_attr "itanium_class" "mmshf")])
845 (define_insn "*mux1_brcst_qi"
846 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
848 (match_operand:QI 1 "gr_register_operand" "r")))]
850 "mux1 %0 = %1, @brcst"
851 [(set_attr "itanium_class" "mmshf")])
853 (define_expand "vec_extract_evenv8qi"
854 [(match_operand:V8QI 0 "gr_register_operand" "")
855 (match_operand:V8QI 1 "gr_register_operand" "")
856 (match_operand:V8QI 2 "gr_register_operand" "")]
859 rtx temp = gen_reg_rtx (V8QImode);
860 emit_insn (gen_mix1_r (temp, operands[1], operands[2]));
861 emit_insn (gen_mux1_alt (operands[0], temp));
865 (define_expand "vec_extract_oddv8qi"
866 [(match_operand:V8QI 0 "gr_register_operand" "")
867 (match_operand:V8QI 1 "gr_register_operand" "")
868 (match_operand:V8QI 2 "gr_register_operand" "")]
871 rtx temp = gen_reg_rtx (V8QImode);
872 emit_insn (gen_mix1_l (temp, operands[1], operands[2]));
873 emit_insn (gen_mux1_alt (operands[0], temp));
877 (define_insn "vec_interleave_lowv4hi"
878 [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
881 (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU")
882 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU"))
883 (parallel [(const_int 0)
888 "unpack2.l %0 = %r2, %r1"
889 [(set_attr "itanium_class" "mmshf")])
891 (define_insn "vec_interleave_highv4hi"
892 [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
895 (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU")
896 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU"))
897 (parallel [(const_int 2)
902 "unpack2.h %0 = %r2, %r1"
903 [(set_attr "itanium_class" "mmshf")])
905 (define_insn "mix2_r"
906 [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
909 (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU")
910 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU"))
911 (parallel [(const_int 0)
916 "mix2.r %0 = %r2, %r1"
917 [(set_attr "itanium_class" "mmshf")])
919 (define_insn "mix2_l"
920 [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
923 (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU")
924 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU"))
925 (parallel [(const_int 1)
930 "mix2.l %0 = %r2, %r1"
931 [(set_attr "itanium_class" "mmshf")])
934 [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
936 (match_operand:V4HI 1 "gr_register_operand" "r")
937 (parallel [(match_operand 2 "const_int_2bit_operand" "")
938 (match_operand 3 "const_int_2bit_operand" "")
939 (match_operand 4 "const_int_2bit_operand" "")
940 (match_operand 5 "const_int_2bit_operand" "")])))]
944 mask = INTVAL (operands[2]);
945 mask |= INTVAL (operands[3]) << 2;
946 mask |= INTVAL (operands[4]) << 4;
947 mask |= INTVAL (operands[5]) << 6;
948 operands[2] = GEN_INT (mask);
949 return "%,mux2 %0 = %1, %2";
951 [(set_attr "itanium_class" "mmshf")])
953 (define_expand "vec_extract_evenodd_helper"
954 [(set (match_operand:V4HI 0 "gr_register_operand" "")
956 (match_operand:V4HI 1 "gr_register_operand" "")
957 (parallel [(const_int 0)
963 (define_expand "vec_extract_evenv4hi"
964 [(match_operand:V4HI 0 "gr_register_operand")
965 (match_operand:V4HI 1 "gr_reg_or_0_operand")
966 (match_operand:V4HI 2 "gr_reg_or_0_operand")]
969 rtx temp = gen_reg_rtx (V4HImode);
970 emit_insn (gen_mix2_r (temp, operands[1], operands[2]));
971 emit_insn (gen_vec_extract_evenodd_helper (operands[0], temp));
975 (define_expand "vec_extract_oddv4hi"
976 [(match_operand:V4HI 0 "gr_register_operand")
977 (match_operand:V4HI 1 "gr_reg_or_0_operand")
978 (match_operand:V4HI 2 "gr_reg_or_0_operand")]
981 rtx temp = gen_reg_rtx (V4HImode);
982 emit_insn (gen_mix2_l (temp, operands[1], operands[2]));
983 emit_insn (gen_vec_extract_evenodd_helper (operands[0], temp));
987 (define_insn "*mux2_brcst_hi"
988 [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
990 (match_operand:HI 1 "gr_register_operand" "r")))]
993 [(set_attr "itanium_class" "mmshf")])
995 ;; Note that mix4.r performs the exact same operation.
996 (define_insn "vec_interleave_lowv2si"
997 [(set (match_operand:V2SI 0 "gr_register_operand" "=r")
1000 (match_operand:V2SI 1 "gr_reg_or_0_operand" "rU")
1001 (match_operand:V2SI 2 "gr_reg_or_0_operand" "rU"))
1002 (parallel [(const_int 0)
1005 "unpack4.l %0 = %r2, %r1"
1006 [(set_attr "itanium_class" "mmshf")])
1008 ;; Note that mix4.l performs the exact same operation.
1009 (define_insn "vec_interleave_highv2si"
1010 [(set (match_operand:V2SI 0 "gr_register_operand" "=r")
1013 (match_operand:V2SI 1 "gr_reg_or_0_operand" "rU")
1014 (match_operand:V2SI 2 "gr_reg_or_0_operand" "rU"))
1015 (parallel [(const_int 1)
1018 "unpack4.h %0 = %r2, %r1"
1019 [(set_attr "itanium_class" "mmshf")])
1021 (define_expand "vec_extract_evenv2si"
1022 [(match_operand:V2SI 0 "gr_register_operand" "")
1023 (match_operand:V2SI 1 "gr_register_operand" "")
1024 (match_operand:V2SI 2 "gr_register_operand" "")]
1027 emit_insn (gen_vec_interleave_lowv2si (operands[0], operands[1],
1032 (define_expand "vec_extract_oddv2si"
1033 [(match_operand:V2SI 0 "gr_register_operand" "")
1034 (match_operand:V2SI 1 "gr_register_operand" "")
1035 (match_operand:V2SI 2 "gr_register_operand" "")]
1038 emit_insn (gen_vec_interleave_highv2si (operands[0], operands[1],
1043 (define_expand "vec_initv2si"
1044 [(match_operand:V2SI 0 "gr_register_operand" "")
1045 (match_operand 1 "" "")]
1048 rtx op1 = XVECEXP (operands[1], 0, 0);
1049 rtx op2 = XVECEXP (operands[1], 0, 1);
1052 if (GET_CODE (op1) == CONST_INT && GET_CODE (op2) == CONST_INT)
1054 x = gen_rtx_CONST_VECTOR (V2SImode, XVEC (operands[1], 0));
1055 emit_move_insn (operands[0], x);
1059 if (!gr_reg_or_0_operand (op1, SImode))
1060 op1 = force_reg (SImode, op1);
1061 if (!gr_reg_or_0_operand (op2, SImode))
1062 op2 = force_reg (SImode, op2);
1064 if (TARGET_BIG_ENDIAN)
1065 x = gen_rtx_VEC_CONCAT (V2SImode, op2, op1);
1067 x = gen_rtx_VEC_CONCAT (V2SImode, op1, op2);
1068 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1072 (define_insn "*vecinit_v2si"
1073 [(set (match_operand:V2SI 0 "gr_register_operand" "=r")
1075 (match_operand:SI 1 "gr_reg_or_0_operand" "rO")
1076 (match_operand:SI 2 "gr_reg_or_0_operand" "rO")))]
1078 "unpack4.l %0 = %r2, %r1"
1079 [(set_attr "itanium_class" "mmshf")])
1081 ;; Missing operations
1090 ;; Floating point vector operations
1092 (define_expand "movv2sf"
1093 [(set (match_operand:V2SF 0 "general_operand" "")
1094 (match_operand:V2SF 1 "general_operand" ""))]
1097 rtx op1 = ia64_expand_move (operands[0], operands[1]);
1103 (define_insn "*movv2sf_internal"
1104 [(set (match_operand:V2SF 0 "destination_operand"
1105 "=f,f,f,Q,*r ,*r,*r,*r,m ,f ,*r")
1106 (match_operand:V2SF 1 "move_operand"
1107 "fU,Y,Q,f,U*r,W ,i ,m ,*r,*r,f "))]
1108 "ia64_move_ok (operands[0], operands[1])"
1110 static const char * const alt[] = {
1112 "%,fpack %0 = %F2, %F1",
1113 "%,ldf8 %0 = %1%P1",
1114 "%,stf8 %0 = %1%P0",
1116 "%,addl %0 = %v1, r0",
1118 "%,ld8%O1 %0 = %1%P1",
1119 "%,st8%Q0 %0 = %r1%P0",
1120 "%,setf.sig %0 = %1",
1121 "%,getf.sig %0 = %1"
1124 if (which_alternative == 1)
1126 operands[2] = XVECEXP (operands[1], 0, TARGET_BIG_ENDIAN ? 0 : 1);
1127 operands[1] = XVECEXP (operands[1], 0, TARGET_BIG_ENDIAN ? 1 : 0);
1130 return alt[which_alternative];
1132 [(set_attr "itanium_class" "fmisc,fmisc,fld,stf,ialu,ialu,long_i,ld,st,tofr,frfr")])
1134 (define_insn "absv2sf2"
1135 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1136 (abs:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")))]
1139 [(set_attr "itanium_class" "fmisc")])
1141 (define_insn "negv2sf2"
1142 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1143 (neg:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")))]
1146 [(set_attr "itanium_class" "fmisc")])
1148 (define_insn "*negabsv2sf2"
1149 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1151 (abs:V2SF (match_operand:V2SF 1 "fr_register_operand" "f"))))]
1154 [(set_attr "itanium_class" "fmisc")])
1156 (define_expand "addv2sf3"
1157 [(set (match_operand:V2SF 0 "fr_register_operand" "")
1158 (fma:V2SF (match_operand:V2SF 1 "fr_register_operand" "")
1160 (match_operand:V2SF 2 "fr_register_operand" "")))]
1163 rtvec v = gen_rtvec (2, CONST1_RTX (SFmode), CONST1_RTX (SFmode));
1164 operands[3] = force_reg (V2SFmode, gen_rtx_CONST_VECTOR (V2SFmode, v));
1167 (define_expand "subv2sf3"
1168 [(set (match_operand:V2SF 0 "fr_register_operand" "")
1170 (match_operand:V2SF 1 "fr_register_operand" "")
1172 (neg:V2SF (match_operand:V2SF 2 "fr_register_operand" ""))))]
1175 rtvec v = gen_rtvec (2, CONST1_RTX (SFmode), CONST1_RTX (SFmode));
1176 operands[3] = force_reg (V2SFmode, gen_rtx_CONST_VECTOR (V2SFmode, v));
1179 (define_insn "mulv2sf3"
1180 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1181 (mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")
1182 (match_operand:V2SF 2 "fr_register_operand" "f")))]
1185 [(set_attr "itanium_class" "fmac")])
1187 (define_insn "fmav2sf4"
1188 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1190 (match_operand:V2SF 1 "fr_register_operand" "f")
1191 (match_operand:V2SF 2 "fr_register_operand" "f")
1192 (match_operand:V2SF 3 "fr_register_operand" "f")))]
1194 "fpma %0 = %1, %2, %3"
1195 [(set_attr "itanium_class" "fmac")])
1197 (define_insn "fmsv2sf4"
1198 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1200 (match_operand:V2SF 1 "fr_register_operand" "f")
1201 (match_operand:V2SF 2 "fr_register_operand" "f")
1202 (neg:V2SF (match_operand:V2SF 3 "fr_register_operand" "f"))))]
1204 "fpms %0 = %1, %2, %3"
1205 [(set_attr "itanium_class" "fmac")])
1207 (define_insn "*fpnmpy"
1208 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1210 (mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")
1211 (match_operand:V2SF 2 "fr_register_operand" "f"))))]
1213 "fpnmpy %0 = %1, %2"
1214 [(set_attr "itanium_class" "fmac")])
1216 (define_insn "fnmav2sf4"
1217 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1219 (neg:V2SF (match_operand:V2SF 1 "fr_register_operand" "f"))
1220 (match_operand:V2SF 2 "fr_register_operand" "f")
1221 (match_operand:V2SF 3 "fr_register_operand" "f")))]
1223 "fpnma %0 = %1, %2, %3"
1224 [(set_attr "itanium_class" "fmac")])
1226 (define_insn "smaxv2sf3"
1227 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1228 (smax:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")
1229 (match_operand:V2SF 2 "fr_register_operand" "f")))]
1232 [(set_attr "itanium_class" "fmisc")])
1234 (define_insn "sminv2sf3"
1235 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1236 (smin:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")
1237 (match_operand:V2SF 2 "fr_register_operand" "f")))]
1240 [(set_attr "itanium_class" "fmisc")])
1242 (define_expand "reduc_splus_v2sf"
1243 [(match_operand:V2SF 0 "fr_register_operand" "")
1244 (match_operand:V2SF 1 "fr_register_operand" "")]
1247 rtx tmp = gen_reg_rtx (V2SFmode);
1248 emit_insn (gen_fswap (tmp, operands[1], CONST0_RTX (V2SFmode)));
1249 emit_insn (gen_addv2sf3 (operands[0], operands[1], tmp));
1253 (define_expand "reduc_smax_v2sf"
1254 [(match_operand:V2SF 0 "fr_register_operand" "")
1255 (match_operand:V2SF 1 "fr_register_operand" "")]
1258 rtx tmp = gen_reg_rtx (V2SFmode);
1259 emit_insn (gen_fswap (tmp, operands[1], CONST0_RTX (V2SFmode)));
1260 emit_insn (gen_smaxv2sf3 (operands[0], operands[1], tmp));
1264 (define_expand "reduc_smin_v2sf"
1265 [(match_operand:V2SF 0 "fr_register_operand" "")
1266 (match_operand:V2SF 1 "fr_register_operand" "")]
1269 rtx tmp = gen_reg_rtx (V2SFmode);
1270 emit_insn (gen_fswap (tmp, operands[1], CONST0_RTX (V2SFmode)));
1271 emit_insn (gen_sminv2sf3 (operands[0], operands[1], tmp));
1275 (define_expand "vcondv2sf"
1276 [(set (match_operand:V2SF 0 "fr_register_operand" "")
1278 (match_operator 3 ""
1279 [(match_operand:V2SF 4 "fr_reg_or_0_operand" "")
1280 (match_operand:V2SF 5 "fr_reg_or_0_operand" "")])
1281 (match_operand:V2SF 1 "fr_reg_or_0_operand" "")
1282 (match_operand:V2SF 2 "fr_reg_or_0_operand" "")))]
1287 cmp = gen_reg_rtx (V2SFmode);
1288 PUT_MODE (operands[3], V2SFmode);
1289 emit_insn (gen_rtx_SET (VOIDmode, cmp, operands[3]));
1291 x = gen_rtx_IF_THEN_ELSE (V2SFmode, cmp, operands[1], operands[2]);
1292 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1296 (define_insn "*fpcmp"
1297 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1298 (match_operator:V2SF 3 "comparison_operator"
1299 [(match_operand:V2SF 1 "fr_reg_or_0_operand" "fU")
1300 (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU")]))]
1302 "fpcmp.%D3 %0 = %F1, %F2"
1303 [(set_attr "itanium_class" "fmisc")])
1305 (define_insn "*fselect"
1306 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1308 (match_operand:V2SF 1 "fr_register_operand" "f")
1309 (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU")
1310 (match_operand:V2SF 3 "fr_reg_or_0_operand" "fU")))]
1312 "fselect %0 = %F2, %F3, %1"
1313 [(set_attr "itanium_class" "fmisc")])
1315 (define_expand "vec_initv2sf"
1316 [(match_operand:V2SF 0 "fr_register_operand" "")
1317 (match_operand 1 "" "")]
1320 rtx op1 = XVECEXP (operands[1], 0, 0);
1321 rtx op2 = XVECEXP (operands[1], 0, 1);
1324 if (GET_CODE (op1) == CONST_DOUBLE && GET_CODE (op2) == CONST_DOUBLE)
1326 x = gen_rtx_CONST_VECTOR (V2SFmode, XVEC (operands[1], 0));
1327 emit_move_insn (operands[0], x);
1331 if (!fr_reg_or_fp01_operand (op1, SFmode))
1332 op1 = force_reg (SFmode, op1);
1333 if (!fr_reg_or_fp01_operand (op2, SFmode))
1334 op2 = force_reg (SFmode, op2);
1336 if (TARGET_BIG_ENDIAN)
1337 emit_insn (gen_fpack (operands[0], op2, op1));
1339 emit_insn (gen_fpack (operands[0], op1, op2));
1343 (define_insn "fpack"
1344 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1346 (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
1347 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
1349 "fpack %0 = %F2, %F1"
1350 [(set_attr "itanium_class" "fmisc")])
1352 (define_insn "fswap"
1353 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1356 (match_operand:V2SF 1 "fr_reg_or_0_operand" "fU")
1357 (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU"))
1358 (parallel [(const_int 1) (const_int 2)])))]
1360 "fswap %0 = %F1, %F2"
1361 [(set_attr "itanium_class" "fmisc")])
1363 (define_insn "vec_interleave_highv2sf"
1364 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1367 (match_operand:V2SF 1 "fr_reg_or_0_operand" "fU")
1368 (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU"))
1369 (parallel [(const_int 1) (const_int 3)])))]
1371 "fmix.l %0 = %F2, %F1"
1372 [(set_attr "itanium_class" "fmisc")])
1374 (define_insn "vec_interleave_lowv2sf"
1375 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1378 (match_operand:V2SF 1 "fr_reg_or_0_operand" "fU")
1379 (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU"))
1380 (parallel [(const_int 0) (const_int 2)])))]
1382 "fmix.r %0 = %F2, %F1"
1383 [(set_attr "itanium_class" "fmisc")])
1385 (define_insn "fmix_lr"
1386 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1389 (match_operand:V2SF 1 "fr_reg_or_0_operand" "fU")
1390 (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU"))
1391 (parallel [(const_int 0) (const_int 3)])))]
1393 "fmix.lr %0 = %F2, %F1"
1394 [(set_attr "itanium_class" "fmisc")])
1396 (define_expand "vec_extract_evenv2sf"
1397 [(match_operand:V2SF 0 "gr_register_operand" "")
1398 (match_operand:V2SF 1 "gr_register_operand" "")
1399 (match_operand:V2SF 2 "gr_register_operand" "")]
1402 emit_insn (gen_vec_interleave_lowv2sf (operands[0], operands[1],
1407 (define_expand "vec_extract_oddv2sf"
1408 [(match_operand:V2SF 0 "gr_register_operand" "")
1409 (match_operand:V2SF 1 "gr_register_operand" "")
1410 (match_operand:V2SF 2 "gr_register_operand" "")]
1413 emit_insn (gen_vec_interleave_highv2sf (operands[0], operands[1],
1419 (define_expand "vec_setv2sf"
1420 [(match_operand:V2SF 0 "fr_register_operand" "")
1421 (match_operand:SF 1 "fr_register_operand" "")
1422 (match_operand 2 "const_int_operand" "")]
1425 rtx tmp = gen_reg_rtx (V2SFmode);
1426 emit_insn (gen_fpack (tmp, operands[1], CONST0_RTX (SFmode)));
1428 switch (INTVAL (operands[2]))
1431 emit_insn (gen_fmix_lr (operands[0], tmp, operands[0]));
1434 emit_insn (gen_vec_interleave_lowv2sf (operands[0], operands[0], tmp));
1442 (define_insn_and_split "*vec_extractv2sf_0_le"
1443 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,f,m")
1444 (unspec:SF [(match_operand:V2SF 1 "nonimmediate_operand" "rfm,rm,r")
1447 "!TARGET_BIG_ENDIAN"
1450 [(set (match_dup 0) (match_dup 1))]
1452 if (REG_P (operands[1]) && FR_REGNO_P (REGNO (operands[1])))
1453 operands[0] = gen_rtx_REG (V2SFmode, REGNO (operands[0]));
1454 else if (MEM_P (operands[1]))
1455 operands[1] = adjust_address (operands[1], SFmode, 0);
1457 operands[1] = gen_rtx_REG (SFmode, REGNO (operands[1]));
1460 (define_insn_and_split "*vec_extractv2sf_0_be"
1461 [(set (match_operand:SF 0 "register_operand" "=r,f")
1462 (unspec:SF [(match_operand:V2SF 1 "register_operand" "rf,r")
1468 [(set (match_dup 0) (match_dup 1))]
1470 if (REG_P (operands[1]) && FR_REGNO_P (REGNO (operands[1])))
1471 operands[0] = gen_rtx_REG (V2SFmode, REGNO (operands[0]));
1473 operands[1] = gen_rtx_REG (SFmode, REGNO (operands[1]));
1476 (define_insn_and_split "*vec_extractv2sf_1"
1477 [(set (match_operand:SF 0 "register_operand" "=r")
1478 (unspec:SF [(match_operand:V2SF 1 "register_operand" "r")
1486 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
1487 operands[1] = gen_rtx_REG (DImode, REGNO (operands[1]));
1488 if (TARGET_BIG_ENDIAN)
1489 emit_move_insn (operands[0], operands[1]);
1491 emit_insn (gen_lshrdi3 (operands[0], operands[1], GEN_INT (32)));
1495 (define_expand "vec_extractv2sf"
1496 [(set (match_operand:SF 0 "register_operand" "")
1497 (unspec:SF [(match_operand:V2SF 1 "register_operand" "")
1498 (match_operand:DI 2 "const_int_operand" "")]
1503 (define_expand "vec_unpacku_lo_<mode>"
1504 [(match_operand:<vecwider> 0 "register_operand" "")
1505 (match_operand:VECINT12 1 "register_operand" "")]
1508 ia64_expand_unpack (operands, true, false);
1512 (define_expand "vec_unpacku_hi_<mode>"
1513 [(match_operand:<vecwider> 0 "register_operand" "")
1514 (match_operand:VECINT12 1 "register_operand" "")]
1517 ia64_expand_unpack (operands, true, true);
1521 (define_expand "vec_unpacks_lo_<mode>"
1522 [(match_operand:<vecwider> 0 "register_operand" "")
1523 (match_operand:VECINT12 1 "register_operand" "")]
1526 ia64_expand_unpack (operands, false, false);
1530 (define_expand "vec_unpacks_hi_<mode>"
1531 [(match_operand:<vecwider> 0 "register_operand" "")
1532 (match_operand:VECINT12 1 "register_operand" "")]
1535 ia64_expand_unpack (operands, false, true);
1539 (define_expand "vec_pack_trunc_v4hi"
1540 [(match_operand:V8QI 0 "gr_register_operand" "")
1541 (match_operand:V4HI 1 "gr_register_operand" "")
1542 (match_operand:V4HI 2 "gr_register_operand" "")]
1545 rtx op1 = gen_lowpart(V8QImode, operands[1]);
1546 rtx op2 = gen_lowpart(V8QImode, operands[2]);
1547 emit_insn (gen_vec_extract_evenv8qi (operands[0], op1, op2));
1551 (define_expand "vec_pack_trunc_v2si"
1552 [(match_operand:V4HI 0 "gr_register_operand" "")
1553 (match_operand:V2SI 1 "gr_register_operand" "")
1554 (match_operand:V2SI 2 "gr_register_operand" "")]
1557 rtx op1 = gen_lowpart(V4HImode, operands[1]);
1558 rtx op2 = gen_lowpart(V4HImode, operands[2]);
1559 emit_insn (gen_vec_extract_evenv4hi (operands[0], op1, op2));
1563 ;; Missing operations