1 ;; IA-64 Machine description template
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by James E. Wilson <wilson@cygnus.com> and
5 ;; David Mosberger <davidm@hpl.hp.com>.
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
24 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
26 ;; ??? register_operand accepts (subreg:DI (mem:SI X)) which forces later
27 ;; reload. This will be fixed once scheduling support is turned on.
29 ;; ??? Optimize for post-increment addressing modes.
31 ;; ??? fselect is not supported, because there is no integer register
34 ;; ??? fp abs/min/max instructions may also work for integer values.
36 ;; ??? Would a predicate_reg_operand predicate be useful? The HP one is buggy,
37 ;; it assumes the operand is a register and takes REGNO of it without checking.
39 ;; ??? Would a branch_reg_operand predicate be useful? The HP one is buggy,
40 ;; it assumes the operand is a register and takes REGNO of it without checking.
42 ;; ??? Go through list of documented named patterns and look for more to
45 ;; ??? Go through instruction manual and look for more instructions that
48 ;; ??? Add function unit scheduling info for Itanium (TM) processor.
50 ;; ??? Need a better way to describe alternate fp status registers.
54 (UNSPEC_LTOFF_DTPMOD 0)
55 (UNSPEC_LTOFF_DTPREL 1)
57 (UNSPEC_LTOFF_TPREL 3)
62 (UNSPEC_GR_RESTORE 11)
64 (UNSPEC_FR_RESTORE 13)
65 (UNSPEC_FR_RECIP_APPROX 14)
66 (UNSPEC_PRED_REL_MUTEX 15)
70 (UNSPEC_CMPXCHG_ACQ 19)
71 (UNSPEC_FETCHADD_ACQ 20)
74 (UNSPEC_BUNDLE_SELECTOR 23)
76 (UNSPEC_PROLOGUE_USE 25)
79 (UNSPEC_FR_SQRT_RECIP_APPROX 28)
85 (UNSPECV_INSN_GROUP_BARRIER 2)
88 (UNSPECV_PSAC_ALL 5) ; pred.safe_across_calls
89 (UNSPECV_PSAC_NORMAL 6)
90 (UNSPECV_SETJMP_RECEIVER 7)
93 ;; ::::::::::::::::::::
97 ;; ::::::::::::::::::::
99 ;; True if OP is a valid operand for the MEM of a CALL insn.
100 (define_predicate "call_operand"
101 (ior (match_code "symbol_ref")
102 (match_operand 0 "register_operand")))
104 ;; True if OP refers to any kind of symbol.
105 ;; For roughly the same reasons that pmode_register_operand exists, this
106 ;; predicate ignores its mode argument.
107 (define_special_predicate "symbolic_operand"
108 (match_code "symbol_ref,const,label_ref"))
110 ;; True if OP is a SYMBOL_REF which refers to a function.
111 (define_predicate "function_operand"
112 (and (match_code "symbol_ref")
113 (match_test "SYMBOL_REF_FUNCTION_P (op)")))
115 ;; True if OP refers to a symbol, and is appropriate for a GOT load.
116 (define_predicate "got_symbolic_operand"
117 (match_operand 0 "symbolic_operand" "")
119 switch (GET_CODE (op))
125 /* This sort of load should not be used for things in sdata. */
126 return !SYMBOL_REF_SMALL_ADDR_P (op);
129 /* Accept only (plus (symbol_ref) (const_int)). */
131 if (GET_CODE (op) != PLUS
132 || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
133 || GET_CODE (XEXP (op, 1)) != CONST_INT)
136 /* Ok if we're not using GOT entries at all. */
137 if (TARGET_NO_PIC || TARGET_AUTO_PIC)
140 /* The low 14 bits of the constant have been forced to zero
141 by ia64_expand_load_address, so that we do not use up so
142 many GOT entries. Prevent cse from undoing this. */
144 return (INTVAL (op) & 0x3fff) == 0;
151 ;; True if OP refers to a symbol in the sdata section.
152 (define_predicate "sdata_symbolic_operand"
153 (match_code "symbol_ref,const")
155 switch (GET_CODE (op))
159 if (GET_CODE (op) != PLUS
160 || GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
166 if (CONSTANT_POOL_ADDRESS_P (op))
167 return GET_MODE_SIZE (get_pool_mode (op)) <= ia64_section_threshold;
169 return SYMBOL_REF_LOCAL_P (op) && SYMBOL_REF_SMALL_P (op);
176 ;; Like nonimmediate_operand, but don't allow MEMs that try to use a
177 ;; POST_MODIFY with a REG as displacement.
178 (define_predicate "destination_operand"
179 (and (match_operand 0 "nonimmediate_operand")
180 (match_test "GET_CODE (op) != MEM
181 || GET_CODE (XEXP (op, 0)) != POST_MODIFY
182 || GET_CODE (XEXP (XEXP (XEXP (op, 0), 1), 1)) != REG")))
184 ;; Like memory_operand, but don't allow post-increments.
185 (define_predicate "not_postinc_memory_operand"
186 (and (match_operand 0 "memory_operand")
187 (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != RTX_AUTOINC")))
189 ;; True if OP is a general operand, excluding tls symbolic operands.
190 (define_predicate "move_operand"
191 (and (match_operand 0 "general_operand")
193 "GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (op)"))))
195 ;; True if OP is a register operand that is (or could be) a GR reg.
196 (define_predicate "gr_register_operand"
197 (match_operand 0 "register_operand")
200 if (GET_CODE (op) == SUBREG)
201 op = SUBREG_REG (op);
204 return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
207 ;; True if OP is a register operand that is (or could be) an FR reg.
208 (define_predicate "fr_register_operand"
209 (match_operand 0 "register_operand")
212 if (GET_CODE (op) == SUBREG)
213 op = SUBREG_REG (op);
216 return (regno >= FIRST_PSEUDO_REGISTER || FR_REGNO_P (regno));
219 ;; True if OP is a register operand that is (or could be) a GR/FR reg.
220 (define_predicate "grfr_register_operand"
221 (match_operand 0 "register_operand")
224 if (GET_CODE (op) == SUBREG)
225 op = SUBREG_REG (op);
228 return (regno >= FIRST_PSEUDO_REGISTER
229 || GENERAL_REGNO_P (regno)
230 || FR_REGNO_P (regno));
233 ;; True if OP is a nonimmediate operand that is (or could be) a GR reg.
234 (define_predicate "gr_nonimmediate_operand"
235 (match_operand 0 "nonimmediate_operand")
239 if (GET_CODE (op) == MEM)
241 if (GET_CODE (op) == SUBREG)
242 op = SUBREG_REG (op);
245 return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
248 ;; True if OP is a nonimmediate operand that is (or could be) a FR reg.
249 (define_predicate "fr_nonimmediate_operand"
250 (match_operand 0 "nonimmediate_operand")
254 if (GET_CODE (op) == MEM)
256 if (GET_CODE (op) == SUBREG)
257 op = SUBREG_REG (op);
260 return (regno >= FIRST_PSEUDO_REGISTER || FR_REGNO_P (regno));
263 ;; True if OP is a nonimmediate operand that is (or could be) a GR/FR reg.
264 (define_predicate "grfr_nonimmediate_operand"
265 (match_operand 0 "nonimmediate_operand")
269 if (GET_CODE (op) == MEM)
271 if (GET_CODE (op) == SUBREG)
272 op = SUBREG_REG (op);
275 return (regno >= FIRST_PSEUDO_REGISTER
276 || GENERAL_REGNO_P (regno)
277 || FR_REGNO_P (regno));
280 ;; True if OP is a GR register operand, or zero.
281 (define_predicate "gr_reg_or_0_operand"
282 (ior (match_operand 0 "gr_register_operand")
283 (and (match_code "const_int")
284 (match_test "op == const0_rtx"))))
286 ;; True if OP is a GR register operand, or a 5 bit immediate operand.
287 (define_predicate "gr_reg_or_5bit_operand"
288 (ior (match_operand 0 "gr_register_operand")
289 (and (match_code "const_int")
290 (match_test "INTVAL (op) >= 0 && INTVAL (op) < 32"))))
292 ;; True if OP is a GR register operand, or a 6 bit immediate operand.
293 (define_predicate "gr_reg_or_6bit_operand"
294 (ior (match_operand 0 "gr_register_operand")
295 (and (match_code "const_int")
296 (match_test "CONST_OK_FOR_M (INTVAL (op))"))))
298 ;; True if OP is a GR register operand, or an 8 bit immediate operand.
299 (define_predicate "gr_reg_or_8bit_operand"
300 (ior (match_operand 0 "gr_register_operand")
301 (and (match_code "const_int")
302 (match_test "CONST_OK_FOR_K (INTVAL (op))"))))
304 ;; True if OP is a GR/FR register operand, or an 8 bit immediate operand.
305 (define_predicate "grfr_reg_or_8bit_operand"
306 (ior (match_operand 0 "grfr_register_operand")
307 (and (match_code "const_int")
308 (match_test "CONST_OK_FOR_K (INTVAL (op))"))))
310 ;; True if OP is a register operand, or an 8 bit adjusted immediate operand.
311 (define_predicate "gr_reg_or_8bit_adjusted_operand"
312 (ior (match_operand 0 "gr_register_operand")
313 (and (match_code "const_int")
314 (match_test "CONST_OK_FOR_L (INTVAL (op))"))))
316 ;; True if OP is a register operand, or is valid for both an 8 bit
317 ;; immediate and an 8 bit adjusted immediate operand. This is necessary
318 ;; because when we emit a compare, we don't know what the condition will be,
319 ;; so we need the union of the immediates accepted by GT and LT.
320 (define_predicate "gr_reg_or_8bit_and_adjusted_operand"
321 (ior (match_operand 0 "gr_register_operand")
322 (and (match_code "const_int")
323 (match_test "CONST_OK_FOR_K (INTVAL (op))
324 && CONST_OK_FOR_L (INTVAL (op))"))))
326 ;; True if OP is a register operand, or a 14 bit immediate operand.
327 (define_predicate "gr_reg_or_14bit_operand"
328 (ior (match_operand 0 "gr_register_operand")
329 (and (match_code "const_int")
330 (match_test "CONST_OK_FOR_I (INTVAL (op))"))))
332 ;; True if OP is a register operand, or a 22 bit immediate operand.
333 (define_predicate "gr_reg_or_22bit_operand"
334 (ior (match_operand 0 "gr_register_operand")
335 (and (match_code "const_int")
336 (match_test "CONST_OK_FOR_J (INTVAL (op))"))))
338 ;; True if OP is a 6 bit immediate operand.
339 (define_predicate "shift_count_operand"
340 (and (match_code "const_int")
341 (match_test "CONST_OK_FOR_M (INTVAL (op))")))
343 ;; True if OP is a 5 bit immediate operand.
344 (define_predicate "shift_32bit_count_operand"
345 (and (match_code "const_int")
346 (match_test "INTVAL (op) >= 0 && INTVAL (op) < 32")))
348 ;; True if OP is one of the immediate valuse 2, 4, 8, or 16.
349 (define_predicate "shladd_operand"
350 (and (match_code "const_int")
351 (match_test "INTVAL (op) == 2 || INTVAL (op) == 4 ||
352 INTVAL (op) == 8 || INTVAL (op) == 16")))
354 ;; True if OP is one of the immediate values -16, -8, -4, -1, 1, 4, 8, 16.
355 (define_predicate "fetchadd_operand"
356 (and (match_code "const_int")
357 (match_test "INTVAL (op) == -16 || INTVAL (op) == -8 ||
358 INTVAL (op) == -4 || INTVAL (op) == -1 ||
359 INTVAL (op) == 1 || INTVAL (op) == 4 ||
360 INTVAL (op) == 8 || INTVAL (op) == 16")))
363 ;; True if OP is a floating-point constant zero, one, or a register.
364 (define_predicate "fr_reg_or_fp01_operand"
365 (ior (match_operand 0 "fr_register_operand")
366 (and (match_code "const_double")
367 (match_test "CONST_DOUBLE_OK_FOR_G (op)"))))
369 ;; Like fr_reg_or_fp01_operand, but don't allow any SUBREGs.
370 (define_predicate "xfreg_or_fp01_operand"
371 (and (match_operand 0 "fr_reg_or_fp01_operand")
372 (not (match_code "subreg"))))
374 ;; True if this is a comparison operator, which accepts a normal 8-bit
375 ;; signed immediate operand.
376 (define_predicate "normal_comparison_operator"
377 (match_code "eq,ne,gt,le,gtu,leu"))
379 ;; True if this is a comparison operator, which accepts an adjusted 8-bit
380 ;; signed immediate operand.
381 (define_predicate "adjusted_comparison_operator"
382 (match_code "lt,ge,ltu,geu"))
384 ;; True if this is a signed inequality operator.
385 (define_predicate "signed_inequality_operator"
386 (match_code "ge,gt,le,lt"))
388 ;; True if this operator is valid for predication.
389 (define_predicate "predicate_operator"
390 (match_code "eq,ne"))
392 ;; True if this operator can be used in a conditional operation.
393 (define_predicate "condop_operator"
394 (match_code "plus,minus,ior,xor,and"))
396 ;; These three are hardware registers that can only be addressed in
397 ;; DImode. It's not strictly necessary to test mode == DImode here,
398 ;; but it makes decent insurance against someone writing a
399 ;; match_operand wrong.
401 ;; True if this is the ar.lc register.
402 (define_predicate "ar_lc_reg_operand"
403 (and (match_code "reg")
404 (match_test "mode == DImode && REGNO (op) == AR_LC_REGNUM")))
406 ;; True if this is the ar.ccv register.
407 (define_predicate "ar_ccv_reg_operand"
408 (and (match_code "reg")
409 (match_test "mode == DImode && REGNO (op) == AR_CCV_REGNUM")))
411 ;; True if this is the ar.pfs register.
412 (define_predicate "ar_pfs_reg_operand"
413 (and (match_code "reg")
414 (match_test "mode == DImode && REGNO (op) == AR_PFS_REGNUM")))
416 ;; True if OP is valid as a base register in a reg + offset address.
417 ;; ??? Should I copy the flag_omit_frame_pointer and cse_not_expected
418 ;; checks from pa.c basereg_operand as well? Seems to be OK without them
420 (define_predicate "basereg_operand"
421 (match_operand 0 "register_operand")
423 if (GET_CODE (op) == SUBREG)
424 op = SUBREG_REG (op);
425 return REG_POINTER (op);
429 ;; ::::::::::::::::::::
433 ;; ::::::::::::::::::::
435 ;; Processor type. This attribute must exactly match the processor_type
436 ;; enumeration in ia64.h.
437 (define_attr "cpu" "itanium,itanium2" (const (symbol_ref "ia64_tune")))
439 ;; Instruction type. This primarily determines how instructions can be
440 ;; packed in bundles, and secondarily affects scheduling to function units.
442 ;; A alu, can go in I or M syllable of a bundle
447 ;; L long immediate, takes two syllables
450 ;; ??? Should not have any pattern with type unknown. Perhaps add code to
451 ;; check this in md_reorg? Currently use unknown for patterns which emit
452 ;; multiple instructions, patterns which emit 0 instructions, and patterns
453 ;; which emit instruction that can go in any slot (e.g. nop).
455 (define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld,
456 fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,ld,
457 chk_s,long_i,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,st,syst_m0,
458 syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop,nop_b,nop_f,
459 nop_i,nop_m,nop_x,lfetch,pre_cycle"
460 (const_string "unknown"))
462 ;; chk_s has an I and an M form; use type A for convenience.
463 (define_attr "type" "unknown,A,I,M,F,B,L,X,S"
464 (cond [(eq_attr "itanium_class" "ld,st,fld,stf,sem,nop_m") (const_string "M")
465 (eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M")
466 (eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M")
467 (eq_attr "itanium_class" "lfetch") (const_string "M")
468 (eq_attr "itanium_class" "chk_s,ialu,icmp,ilog") (const_string "A")
469 (eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F")
470 (eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F")
471 (eq_attr "itanium_class" "frar_i,toar_i,frbr,tobr") (const_string "I")
472 (eq_attr "itanium_class" "frpr,topr,ishf,xtd,tbit") (const_string "I")
473 (eq_attr "itanium_class" "mmmul,mmshf,mmshfi,nop_i") (const_string "I")
474 (eq_attr "itanium_class" "br,scall,nop_b") (const_string "B")
475 (eq_attr "itanium_class" "stop_bit") (const_string "S")
476 (eq_attr "itanium_class" "nop_x") (const_string "X")
477 (eq_attr "itanium_class" "long_i") (const_string "L")]
478 (const_string "unknown")))
480 (define_attr "itanium_requires_unit0" "no,yes"
481 (cond [(eq_attr "itanium_class" "syst_m0,sem,frfr,rse_m") (const_string "yes")
482 (eq_attr "itanium_class" "toar_m,frar_m") (const_string "yes")
483 (eq_attr "itanium_class" "frbr,tobr,mmmul") (const_string "yes")
484 (eq_attr "itanium_class" "tbit,ishf,topr,frpr") (const_string "yes")
485 (eq_attr "itanium_class" "toar_i,frar_i") (const_string "yes")
486 (eq_attr "itanium_class" "fmisc,fcmp") (const_string "yes")]
487 (const_string "no")))
489 ;; Predication. True iff this instruction can be predicated.
491 (define_attr "predicable" "no,yes" (const_string "yes"))
493 ;; Empty. True iff this insn does not generate any code.
495 (define_attr "empty" "no,yes" (const_string "no"))
499 ;; DFA descriptions of ia64 processors used for insn scheduling and
502 (automata_option "ndfa")
504 ;; Uncomment the following line to output automata for debugging.
505 ;; (automata_option "v")
507 (automata_option "w")
509 ;;(automata_option "no-minimization")
512 (include "itanium1.md")
513 (include "itanium2.md")
516 ;; ::::::::::::::::::::
520 ;; ::::::::::::::::::::
522 ;; Set of a single predicate register. This is only used to implement
523 ;; pr-to-pr move and complement.
525 (define_insn "*movcci"
526 [(set (match_operand:CCI 0 "register_operand" "=c,c,c")
527 (match_operand:CCI 1 "nonmemory_operand" "O,n,c"))]
530 cmp.ne %0, p0 = r0, r0
531 cmp.eq %0, p0 = r0, r0
532 (%1) cmp.eq.unc %0, p0 = r0, r0"
533 [(set_attr "itanium_class" "icmp")
534 (set_attr "predicable" "no")])
537 [(set (match_operand:BI 0 "nonimmediate_operand" "=c,c,?c,?*r, c,*r,*r,*m,*r")
538 (match_operand:BI 1 "move_operand" " O,n, c, c,*r, n,*m,*r,*r"))]
541 cmp.ne %0, %I0 = r0, r0
542 cmp.eq %0, %I0 = r0, r0
545 tbit.nz %0, %I0 = %1, 0
550 [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu")])
553 [(set (match_operand:BI 0 "register_operand" "")
554 (match_operand:BI 1 "register_operand" ""))]
556 && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0]))
557 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
558 [(cond_exec (ne (match_dup 1) (const_int 0))
559 (set (match_dup 0) (const_int 1)))
560 (cond_exec (eq (match_dup 1) (const_int 0))
561 (set (match_dup 0) (const_int 0)))]
565 [(set (match_operand:BI 0 "register_operand" "")
566 (match_operand:BI 1 "register_operand" ""))]
568 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
569 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
570 [(set (match_dup 2) (match_dup 4))
571 (set (match_dup 3) (match_dup 5))
572 (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
573 "operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0]));
574 operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1);
575 operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1]));
576 operands[5] = gen_rtx_REG (CCImode, REGNO (operands[1]) + 1);")
578 (define_expand "movqi"
579 [(set (match_operand:QI 0 "general_operand" "")
580 (match_operand:QI 1 "general_operand" ""))]
583 rtx op1 = ia64_expand_move (operands[0], operands[1]);
589 (define_insn "*movqi_internal"
590 [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
591 (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
592 "ia64_move_ok (operands[0], operands[1])"
601 [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")])
603 (define_expand "movhi"
604 [(set (match_operand:HI 0 "general_operand" "")
605 (match_operand:HI 1 "general_operand" ""))]
608 rtx op1 = ia64_expand_move (operands[0], operands[1]);
614 (define_insn "*movhi_internal"
615 [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
616 (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
617 "ia64_move_ok (operands[0], operands[1])"
626 [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")])
628 (define_expand "movsi"
629 [(set (match_operand:SI 0 "general_operand" "")
630 (match_operand:SI 1 "general_operand" ""))]
633 rtx op1 = ia64_expand_move (operands[0], operands[1]);
639 (define_insn "*movsi_internal"
640 [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d")
641 (match_operand:SI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f,*d,rK"))]
642 "ia64_move_ok (operands[0], operands[1])"
654 ;; frar_m, toar_m ??? why not frar_i and toar_i
655 [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")])
657 (define_expand "movdi"
658 [(set (match_operand:DI 0 "general_operand" "")
659 (match_operand:DI 1 "general_operand" ""))]
662 rtx op1 = ia64_expand_move (operands[0], operands[1]);
668 (define_insn "*movdi_internal"
669 [(set (match_operand:DI 0 "destination_operand"
670 "=r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c")
671 (match_operand:DI 1 "move_operand"
672 "rO,JT,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))]
673 "ia64_move_ok (operands[0], operands[1])"
675 static const char * const alt[] = {
677 "%,addl %0 = %1, r0",
679 "%,ld8%O1 %0 = %1%P1",
680 "%,st8%Q0 %0 = %r1%P0",
681 "%,getf.sig %0 = %1",
682 "%,setf.sig %0 = %r1",
696 if (which_alternative == 2 && ! TARGET_NO_PIC
697 && symbolic_operand (operands[1], VOIDmode))
700 return alt[which_alternative];
702 [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")])
705 [(set (match_operand 0 "register_operand" "")
706 (match_operand 1 "symbolic_operand" ""))]
707 "reload_completed && ! TARGET_NO_PIC"
710 ia64_expand_load_address (operands[0], operands[1]);
714 (define_expand "load_fptr"
716 (plus:DI (reg:DI 1) (match_operand 1 "function_operand" "")))
717 (set (match_operand:DI 0 "register_operand" "") (match_dup 3))]
720 operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode);
721 operands[3] = gen_rtx_MEM (DImode, operands[2]);
722 MEM_READONLY_P (operands[3]) = 1;
725 (define_insn "*load_fptr_internal1"
726 [(set (match_operand:DI 0 "register_operand" "=r")
727 (plus:DI (reg:DI 1) (match_operand 1 "function_operand" "s")))]
729 "addl %0 = @ltoff(@fptr(%1)), gp"
730 [(set_attr "itanium_class" "ialu")])
732 (define_insn "load_gprel"
733 [(set (match_operand:DI 0 "register_operand" "=r")
734 (plus:DI (reg:DI 1) (match_operand 1 "sdata_symbolic_operand" "s")))]
736 "addl %0 = @gprel(%1), gp"
737 [(set_attr "itanium_class" "ialu")])
739 (define_insn "gprel64_offset"
740 [(set (match_operand:DI 0 "register_operand" "=r")
741 (minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))]
743 "movl %0 = @gprel(%1)"
744 [(set_attr "itanium_class" "long_i")])
746 (define_expand "load_gprel64"
748 (minus:DI (match_operand:DI 1 "symbolic_operand" "") (match_dup 3)))
749 (set (match_operand:DI 0 "register_operand" "")
750 (plus:DI (match_dup 3) (match_dup 2)))]
753 operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode);
754 operands[3] = pic_offset_table_rtx;
757 ;; This is used as a placeholder for the return address during early
758 ;; compilation. We won't know where we've placed this until during
759 ;; reload, at which point it can wind up in b0, a general register,
760 ;; or memory. The only safe destination under these conditions is a
763 (define_insn_and_split "*movdi_ret_addr"
764 [(set (match_operand:DI 0 "register_operand" "=r")
765 (unspec:DI [(const_int 0)] UNSPEC_RET_ADDR))]
771 ia64_split_return_addr_rtx (operands[0]);
774 [(set_attr "itanium_class" "ialu")])
776 (define_insn "*load_symptr_high"
777 [(set (match_operand:DI 0 "register_operand" "=r")
778 (plus:DI (high:DI (match_operand 1 "got_symbolic_operand" "s"))
779 (match_operand:DI 2 "register_operand" "a")))]
782 if (HAVE_AS_LTOFFX_LDXMOV_RELOCS)
783 return "%,addl %0 = @ltoffx(%1), %2";
785 return "%,addl %0 = @ltoff(%1), %2";
787 [(set_attr "itanium_class" "ialu")])
789 (define_insn "*load_symptr_low"
790 [(set (match_operand:DI 0 "register_operand" "=r")
791 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
792 (match_operand 2 "got_symbolic_operand" "s")))]
795 if (HAVE_AS_LTOFFX_LDXMOV_RELOCS)
796 return "%,ld8.mov %0 = [%1], %2";
798 return "%,ld8 %0 = [%1]";
800 [(set_attr "itanium_class" "ld")])
802 (define_insn "load_ltoff_dtpmod"
803 [(set (match_operand:DI 0 "register_operand" "=r")
805 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
806 UNSPEC_LTOFF_DTPMOD)))]
808 "addl %0 = @ltoff(@dtpmod(%1)), gp"
809 [(set_attr "itanium_class" "ialu")])
811 (define_insn "load_ltoff_dtprel"
812 [(set (match_operand:DI 0 "register_operand" "=r")
814 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
815 UNSPEC_LTOFF_DTPREL)))]
817 "addl %0 = @ltoff(@dtprel(%1)), gp"
818 [(set_attr "itanium_class" "ialu")])
820 (define_expand "load_dtprel"
821 [(set (match_operand:DI 0 "register_operand" "")
822 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
827 (define_insn "*load_dtprel64"
828 [(set (match_operand:DI 0 "register_operand" "=r")
829 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
832 "movl %0 = @dtprel(%1)"
833 [(set_attr "itanium_class" "long_i")])
835 (define_insn "*load_dtprel22"
836 [(set (match_operand:DI 0 "register_operand" "=r")
837 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
840 "addl %0 = @dtprel(%1), r0"
841 [(set_attr "itanium_class" "ialu")])
843 (define_expand "add_dtprel"
844 [(set (match_operand:DI 0 "register_operand" "")
845 (plus:DI (match_operand:DI 1 "register_operand" "")
846 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
851 (define_insn "*add_dtprel14"
852 [(set (match_operand:DI 0 "register_operand" "=r")
853 (plus:DI (match_operand:DI 1 "register_operand" "r")
854 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
857 "adds %0 = @dtprel(%2), %1"
858 [(set_attr "itanium_class" "ialu")])
860 (define_insn "*add_dtprel22"
861 [(set (match_operand:DI 0 "register_operand" "=r")
862 (plus:DI (match_operand:DI 1 "register_operand" "a")
863 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
866 "addl %0 = @dtprel(%2), %1"
867 [(set_attr "itanium_class" "ialu")])
869 (define_insn "load_ltoff_tprel"
870 [(set (match_operand:DI 0 "register_operand" "=r")
872 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
873 UNSPEC_LTOFF_TPREL)))]
875 "addl %0 = @ltoff(@tprel(%1)), gp"
876 [(set_attr "itanium_class" "ialu")])
878 (define_expand "load_tprel"
879 [(set (match_operand:DI 0 "register_operand" "")
880 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
885 (define_insn "*load_tprel64"
886 [(set (match_operand:DI 0 "register_operand" "=r")
887 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
890 "movl %0 = @tprel(%1)"
891 [(set_attr "itanium_class" "long_i")])
893 (define_insn "*load_tprel22"
894 [(set (match_operand:DI 0 "register_operand" "=r")
895 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
898 "addl %0 = @tprel(%1), r0"
899 [(set_attr "itanium_class" "ialu")])
901 (define_expand "add_tprel"
902 [(set (match_operand:DI 0 "register_operand" "")
903 (plus:DI (match_operand:DI 1 "register_operand" "")
904 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
909 (define_insn "*add_tprel14"
910 [(set (match_operand:DI 0 "register_operand" "=r")
911 (plus:DI (match_operand:DI 1 "register_operand" "r")
912 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
915 "adds %0 = @tprel(%2), %1"
916 [(set_attr "itanium_class" "ialu")])
918 (define_insn "*add_tprel22"
919 [(set (match_operand:DI 0 "register_operand" "=r")
920 (plus:DI (match_operand:DI 1 "register_operand" "a")
921 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
924 "addl %0 = @tprel(%2), %1"
925 [(set_attr "itanium_class" "ialu")])
927 ;; With no offsettable memory references, we've got to have a scratch
928 ;; around to play with the second word. However, in order to avoid a
929 ;; reload nightmare we lie, claim we don't need one, and fix it up
930 ;; in ia64_split_tmode_move.
931 (define_expand "movti"
932 [(set (match_operand:TI 0 "general_operand" "")
933 (match_operand:TI 1 "general_operand" ""))]
936 rtx op1 = ia64_expand_move (operands[0], operands[1]);
942 (define_insn_and_split "*movti_internal"
943 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m")
944 (match_operand:TI 1 "general_operand" "ri,m,r"))]
945 "ia64_move_ok (operands[0], operands[1])"
950 ia64_split_tmode_move (operands);
953 [(set_attr "itanium_class" "unknown")
954 (set_attr "predicable" "no")])
956 ;; Floating Point Moves
958 ;; Note - Patterns for SF mode moves are compulsory, but
959 ;; patterns for DF are optional, as GCC can synthesize them.
961 (define_expand "movsf"
962 [(set (match_operand:SF 0 "general_operand" "")
963 (match_operand:SF 1 "general_operand" ""))]
966 rtx op1 = ia64_expand_move (operands[0], operands[1]);
972 (define_insn "*movsf_internal"
973 [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
974 (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
975 "ia64_move_ok (operands[0], operands[1])"
985 [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])
987 (define_expand "movdf"
988 [(set (match_operand:DF 0 "general_operand" "")
989 (match_operand:DF 1 "general_operand" ""))]
992 rtx op1 = ia64_expand_move (operands[0], operands[1]);
998 (define_insn "*movdf_internal"
999 [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
1000 (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
1001 "ia64_move_ok (operands[0], operands[1])"
1011 [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])
1013 ;; With no offsettable memory references, we've got to have a scratch
1014 ;; around to play with the second word if the variable winds up in GRs.
1015 (define_expand "movxf"
1016 [(set (match_operand:XF 0 "general_operand" "")
1017 (match_operand:XF 1 "general_operand" ""))]
1020 rtx op0 = operands[0];
1022 if (GET_CODE (op0) == SUBREG)
1023 op0 = SUBREG_REG (op0);
1025 /* We must support XFmode loads into general registers for stdarg/vararg
1026 and unprototyped calls. We split them into DImode loads for convenience.
1027 We don't need XFmode stores from general regs, because a stdarg/vararg
1028 routine does a block store to memory of unnamed arguments. */
1030 if (GET_CODE (op0) == REG && GR_REGNO_P (REGNO (op0)))
1032 /* We're hoping to transform everything that deals with XFmode
1033 quantities and GR registers early in the compiler. */
1037 /* Struct to register can just use TImode instead. */
1038 if ((GET_CODE (operands[1]) == SUBREG
1039 && GET_MODE (SUBREG_REG (operands[1])) == TImode)
1040 || (GET_CODE (operands[1]) == REG
1041 && GR_REGNO_P (REGNO (operands[1]))))
1043 rtx op1 = operands[1];
1045 if (GET_CODE (op1) == SUBREG)
1046 op1 = SUBREG_REG (op1);
1048 /* ??? Maybe we should make a SUBREG here? */
1049 op1 = gen_rtx_REG (TImode, REGNO (op1));
1051 emit_move_insn (gen_rtx_REG (TImode, REGNO (op0)), op1);
1055 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1057 emit_move_insn (gen_rtx_REG (DImode, REGNO (op0)),
1058 operand_subword (operands[1], 0, 0, XFmode));
1059 emit_move_insn (gen_rtx_REG (DImode, REGNO (op0) + 1),
1060 operand_subword (operands[1], 1, 0, XFmode));
1064 /* If the quantity is in a register not known to be GR, spill it. */
1065 if (register_operand (operands[1], XFmode))
1066 operands[1] = spill_xfmode_operand (operands[1], 1);
1068 if (GET_CODE (operands[1]) == MEM)
1072 out[WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (op0));
1073 out[!WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (op0) + 1);
1075 emit_move_insn (out[0], adjust_address (operands[1], DImode, 0));
1076 emit_move_insn (out[1], adjust_address (operands[1], DImode, 8));
1083 if (! reload_in_progress && ! reload_completed)
1085 operands[1] = spill_xfmode_operand (operands[1], 0);
1087 if (GET_MODE (op0) == TImode && GET_CODE (op0) == REG)
1089 rtx memt, memx, in = operands[1];
1090 if (CONSTANT_P (in))
1091 in = validize_mem (force_const_mem (XFmode, in));
1092 if (GET_CODE (in) == MEM)
1093 memt = adjust_address (in, TImode, 0);
1096 memt = assign_stack_temp (TImode, 16, 0);
1097 memx = adjust_address (memt, XFmode, 0);
1098 emit_move_insn (memx, in);
1100 emit_move_insn (op0, memt);
1104 if (! ia64_move_ok (operands[0], operands[1]))
1105 operands[1] = force_reg (XFmode, operands[1]);
1109 ;; ??? There's no easy way to mind volatile acquire/release semantics.
1111 (define_insn "*movxf_internal"
1112 [(set (match_operand:XF 0 "destination_operand" "=f,f, m")
1113 (match_operand:XF 1 "general_operand" "fG,m,fG"))]
1114 "ia64_move_ok (operands[0], operands[1])"
1119 [(set_attr "itanium_class" "fmisc,fld,stf")])
1121 ;; Better code generation via insns that deal with TFmode register pairs
1122 ;; directly. Same concerns apply as for TImode.
1123 (define_expand "movtf"
1124 [(set (match_operand:TF 0 "general_operand" "")
1125 (match_operand:TF 1 "general_operand" ""))]
1128 rtx op1 = ia64_expand_move (operands[0], operands[1]);
1134 (define_insn_and_split "*movtf_internal"
1135 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,r,m")
1136 (match_operand:TF 1 "general_operand" "ri,m,r"))]
1137 "ia64_move_ok (operands[0], operands[1])"
1142 ia64_split_tmode_move (operands);
1145 [(set_attr "itanium_class" "unknown")
1146 (set_attr "predicable" "no")])
1149 ;; ::::::::::::::::::::
1153 ;; ::::::::::::::::::::
1155 ;; Signed conversions from a smaller integer to a larger integer
1157 (define_insn "extendqidi2"
1158 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1159 (sign_extend:DI (match_operand:QI 1 "gr_register_operand" "r")))]
1162 [(set_attr "itanium_class" "xtd")])
1164 (define_insn "extendhidi2"
1165 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1166 (sign_extend:DI (match_operand:HI 1 "gr_register_operand" "r")))]
1169 [(set_attr "itanium_class" "xtd")])
1171 (define_insn "extendsidi2"
1172 [(set (match_operand:DI 0 "grfr_register_operand" "=r,?f")
1173 (sign_extend:DI (match_operand:SI 1 "grfr_register_operand" "r,f")))]
1178 [(set_attr "itanium_class" "xtd,fmisc")])
1180 ;; Unsigned conversions from a smaller integer to a larger integer
1182 (define_insn "zero_extendqidi2"
1183 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
1184 (zero_extend:DI (match_operand:QI 1 "gr_nonimmediate_operand" "r,m")))]
1189 [(set_attr "itanium_class" "xtd,ld")])
1191 (define_insn "zero_extendhidi2"
1192 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
1193 (zero_extend:DI (match_operand:HI 1 "gr_nonimmediate_operand" "r,m")))]
1198 [(set_attr "itanium_class" "xtd,ld")])
1200 (define_insn "zero_extendsidi2"
1201 [(set (match_operand:DI 0 "grfr_register_operand" "=r,r,?f")
1203 (match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))]
1209 [(set_attr "itanium_class" "xtd,ld,fmisc")])
1211 ;; Convert between floating point types of different sizes.
1213 ;; At first glance, it would appear that emitting fnorm for an extending
1214 ;; conversion is unnecessary. However, the stf and getf instructions work
1215 ;; correctly only if the input is properly rounded for its type. In
1216 ;; particular, we get the wrong result for getf.d/stfd if the input is a
1217 ;; denorm single. Since we don't know what the next instruction will be, we
1218 ;; have to emit an fnorm.
1220 ;; ??? Optimization opportunity here. Get rid of the insn altogether
1221 ;; when we can. Should probably use a scheme like has been proposed
1222 ;; for ia32 in dealing with operands that match unary operators. This
1223 ;; would let combine merge the thing into adjacent insns. See also how the
1224 ;; mips port handles SIGN_EXTEND as operands to integer arithmetic insns via
1225 ;; se_register_operand.
1227 (define_insn "extendsfdf2"
1228 [(set (match_operand:DF 0 "fr_register_operand" "=f")
1229 (float_extend:DF (match_operand:SF 1 "fr_register_operand" "f")))]
1232 [(set_attr "itanium_class" "fmac")])
1234 (define_insn "extendsfxf2"
1235 [(set (match_operand:XF 0 "fr_register_operand" "=f")
1236 (float_extend:XF (match_operand:SF 1 "fr_register_operand" "f")))]
1239 [(set_attr "itanium_class" "fmac")])
1241 (define_insn "extenddfxf2"
1242 [(set (match_operand:XF 0 "fr_register_operand" "=f")
1243 (float_extend:XF (match_operand:DF 1 "fr_register_operand" "f")))]
1246 [(set_attr "itanium_class" "fmac")])
1248 (define_insn "truncdfsf2"
1249 [(set (match_operand:SF 0 "fr_register_operand" "=f")
1250 (float_truncate:SF (match_operand:DF 1 "fr_register_operand" "f")))]
1253 [(set_attr "itanium_class" "fmac")])
1255 (define_insn "truncxfsf2"
1256 [(set (match_operand:SF 0 "fr_register_operand" "=f")
1257 (float_truncate:SF (match_operand:XF 1 "fr_register_operand" "f")))]
1260 [(set_attr "itanium_class" "fmac")])
1262 (define_insn "truncxfdf2"
1263 [(set (match_operand:DF 0 "fr_register_operand" "=f")
1264 (float_truncate:DF (match_operand:XF 1 "fr_register_operand" "f")))]
1267 [(set_attr "itanium_class" "fmac")])
1269 ;; Convert between signed integer types and floating point.
1271 (define_insn "floatdixf2"
1272 [(set (match_operand:XF 0 "fr_register_operand" "=f")
1273 (float:XF (match_operand:DI 1 "fr_register_operand" "f")))]
1276 [(set_attr "itanium_class" "fcvtfx")])
1278 (define_insn "fix_truncsfdi2"
1279 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1280 (fix:DI (match_operand:SF 1 "fr_register_operand" "f")))]
1282 "fcvt.fx.trunc %0 = %1"
1283 [(set_attr "itanium_class" "fcvtfx")])
1285 (define_insn "fix_truncdfdi2"
1286 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1287 (fix:DI (match_operand:DF 1 "fr_register_operand" "f")))]
1289 "fcvt.fx.trunc %0 = %1"
1290 [(set_attr "itanium_class" "fcvtfx")])
1292 (define_insn "fix_truncxfdi2"
1293 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1294 (fix:DI (match_operand:XF 1 "fr_register_operand" "f")))]
1296 "fcvt.fx.trunc %0 = %1"
1297 [(set_attr "itanium_class" "fcvtfx")])
1299 (define_insn "fix_truncxfdi2_alts"
1300 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1301 (fix:DI (match_operand:XF 1 "fr_register_operand" "f")))
1302 (use (match_operand:SI 2 "const_int_operand" ""))]
1304 "fcvt.fx.trunc.s%2 %0 = %1"
1305 [(set_attr "itanium_class" "fcvtfx")])
1307 ;; Convert between unsigned integer types and floating point.
1309 (define_insn "floatunsdisf2"
1310 [(set (match_operand:SF 0 "fr_register_operand" "=f")
1311 (unsigned_float:SF (match_operand:DI 1 "fr_register_operand" "f")))]
1313 "fcvt.xuf.s %0 = %1"
1314 [(set_attr "itanium_class" "fcvtfx")])
1316 (define_insn "floatunsdidf2"
1317 [(set (match_operand:DF 0 "fr_register_operand" "=f")
1318 (unsigned_float:DF (match_operand:DI 1 "fr_register_operand" "f")))]
1320 "fcvt.xuf.d %0 = %1"
1321 [(set_attr "itanium_class" "fcvtfx")])
1323 (define_insn "floatunsdixf2"
1324 [(set (match_operand:XF 0 "fr_register_operand" "=f")
1325 (unsigned_float:XF (match_operand:DI 1 "fr_register_operand" "f")))]
1328 [(set_attr "itanium_class" "fcvtfx")])
1330 (define_insn "fixuns_truncsfdi2"
1331 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1332 (unsigned_fix:DI (match_operand:SF 1 "fr_register_operand" "f")))]
1334 "fcvt.fxu.trunc %0 = %1"
1335 [(set_attr "itanium_class" "fcvtfx")])
1337 (define_insn "fixuns_truncdfdi2"
1338 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1339 (unsigned_fix:DI (match_operand:DF 1 "fr_register_operand" "f")))]
1341 "fcvt.fxu.trunc %0 = %1"
1342 [(set_attr "itanium_class" "fcvtfx")])
1344 (define_insn "fixuns_truncxfdi2"
1345 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1346 (unsigned_fix:DI (match_operand:XF 1 "fr_register_operand" "f")))]
1348 "fcvt.fxu.trunc %0 = %1"
1349 [(set_attr "itanium_class" "fcvtfx")])
1351 (define_insn "fixuns_truncxfdi2_alts"
1352 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1353 (unsigned_fix:DI (match_operand:XF 1 "fr_register_operand" "f")))
1354 (use (match_operand:SI 2 "const_int_operand" ""))]
1356 "fcvt.fxu.trunc.s%2 %0 = %1"
1357 [(set_attr "itanium_class" "fcvtfx")])
1359 ;; ::::::::::::::::::::
1361 ;; :: Bit field extraction
1363 ;; ::::::::::::::::::::
1366 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1367 (sign_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
1368 (match_operand:DI 2 "const_int_operand" "n")
1369 (match_operand:DI 3 "const_int_operand" "n")))]
1371 "extr %0 = %1, %3, %2"
1372 [(set_attr "itanium_class" "ishf")])
1374 (define_insn "extzv"
1375 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1376 (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
1377 (match_operand:DI 2 "const_int_operand" "n")
1378 (match_operand:DI 3 "const_int_operand" "n")))]
1380 "extr.u %0 = %1, %3, %2"
1381 [(set_attr "itanium_class" "ishf")])
1383 ;; Insert a bit field.
1384 ;; Can have 3 operands, source1 (inserter), source2 (insertee), dest.
1385 ;; Source1 can be 0 or -1.
1386 ;; Source2 can be 0.
1388 ;; ??? Actual dep instruction is more powerful than what these insv
1389 ;; patterns support. Unfortunately, combine is unable to create patterns
1390 ;; where source2 != dest.
1392 (define_expand "insv"
1393 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "")
1394 (match_operand:DI 1 "const_int_operand" "")
1395 (match_operand:DI 2 "const_int_operand" ""))
1396 (match_operand:DI 3 "nonmemory_operand" ""))]
1399 int width = INTVAL (operands[1]);
1400 int shift = INTVAL (operands[2]);
1402 /* If operand[3] is a constant, and isn't 0 or -1, then load it into a
1404 if (! register_operand (operands[3], DImode)
1405 && operands[3] != const0_rtx && operands[3] != constm1_rtx)
1406 operands[3] = force_reg (DImode, operands[3]);
1408 /* If this is a single dep instruction, we have nothing to do. */
1409 if (! ((register_operand (operands[3], DImode) && width <= 16)
1410 || operands[3] == const0_rtx || operands[3] == constm1_rtx))
1412 /* Check for cases that can be implemented with a mix instruction. */
1413 if (width == 32 && shift == 0)
1415 /* Directly generating the mix4left instruction confuses
1416 optimize_bit_field in function.c. Since this is performing
1417 a useful optimization, we defer generation of the complicated
1418 mix4left RTL to the first splitting phase. */
1419 rtx tmp = gen_reg_rtx (DImode);
1420 emit_insn (gen_shift_mix4left (operands[0], operands[3], tmp));
1423 else if (width == 32 && shift == 32)
1425 emit_insn (gen_mix4right (operands[0], operands[3]));
1429 /* We could handle remaining cases by emitting multiple dep
1432 If we need more than two dep instructions then we lose. A 6
1433 insn sequence mov mask1,mov mask2,shl;;and,and;;or is better than
1434 mov;;dep,shr;;dep,shr;;dep. The former can be executed in 3 cycles,
1435 the latter is 6 cycles on an Itanium (TM) processor, because there is
1436 only one function unit that can execute dep and shr immed.
1438 If we only need two dep instruction, then we still lose.
1439 mov;;dep,shr;;dep is still 4 cycles. Even if we optimize away
1440 the unnecessary mov, this is still undesirable because it will be
1441 hard to optimize, and it creates unnecessary pressure on the I0
1447 /* This code may be useful for other IA-64 processors, so we leave it in
1453 emit_insn (gen_insv (operands[0], GEN_INT (16), GEN_INT (shift),
1457 tmp = gen_reg_rtx (DImode);
1458 emit_insn (gen_lshrdi3 (tmp, operands[3], GEN_INT (16)));
1461 operands[1] = GEN_INT (width);
1462 operands[2] = GEN_INT (shift);
1467 (define_insn "*insv_internal"
1468 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1469 (match_operand:DI 1 "const_int_operand" "n")
1470 (match_operand:DI 2 "const_int_operand" "n"))
1471 (match_operand:DI 3 "nonmemory_operand" "rP"))]
1472 "(gr_register_operand (operands[3], DImode) && INTVAL (operands[1]) <= 16)
1473 || operands[3] == const0_rtx || operands[3] == constm1_rtx"
1474 "dep %0 = %3, %0, %2, %1"
1475 [(set_attr "itanium_class" "ishf")])
1477 ;; Combine doesn't like to create bit-field insertions into zero.
1478 (define_insn "*depz_internal"
1479 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1480 (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r")
1481 (match_operand:DI 2 "const_int_operand" "n"))
1482 (match_operand:DI 3 "const_int_operand" "n")))]
1483 "CONST_OK_FOR_M (INTVAL (operands[2]))
1484 && ia64_depz_field_mask (operands[3], operands[2]) > 0"
1486 operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2]));
1487 return "%,dep.z %0 = %1, %2, %3";
1489 [(set_attr "itanium_class" "ishf")])
1491 (define_insn "shift_mix4left"
1492 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1493 (const_int 32) (const_int 0))
1494 (match_operand:DI 1 "gr_register_operand" "r"))
1495 (clobber (match_operand:DI 2 "gr_register_operand" "=r"))]
1498 [(set_attr "itanium_class" "unknown")])
1501 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "")
1502 (const_int 32) (const_int 0))
1503 (match_operand:DI 1 "register_operand" ""))
1504 (clobber (match_operand:DI 2 "register_operand" ""))]
1506 [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32)))
1507 (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0))
1508 (lshiftrt:DI (match_dup 3) (const_int 32)))]
1509 "operands[3] = operands[2];")
1511 (define_insn "*mix4left"
1512 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1513 (const_int 32) (const_int 0))
1514 (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r")
1517 "mix4.l %0 = %0, %r1"
1518 [(set_attr "itanium_class" "mmshf")])
1520 (define_insn "mix4right"
1521 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1522 (const_int 32) (const_int 32))
1523 (match_operand:DI 1 "gr_reg_or_0_operand" "rO"))]
1525 "mix4.r %0 = %r1, %0"
1526 [(set_attr "itanium_class" "mmshf")])
1528 ;; This is used by the rotrsi3 pattern.
1530 (define_insn "*mix4right_3op"
1531 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1532 (ior:DI (zero_extend:DI (match_operand:SI 1 "gr_register_operand" "r"))
1533 (ashift:DI (zero_extend:DI
1534 (match_operand:SI 2 "gr_register_operand" "r"))
1537 "mix4.r %0 = %2, %1"
1538 [(set_attr "itanium_class" "mmshf")])
1541 ;; ::::::::::::::::::::
1543 ;; :: 1 bit Integer arithmetic
1545 ;; ::::::::::::::::::::
1547 (define_insn_and_split "andbi3"
1548 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1549 (and:BI (match_operand:BI 1 "register_operand" "%0,0,r")
1550 (match_operand:BI 2 "register_operand" "c,r,r")))]
1554 tbit.nz.and.orcm %0, %I0 = %2, 0
1557 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1558 && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
1559 [(cond_exec (eq (match_dup 2) (const_int 0))
1560 (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0))
1563 [(set_attr "itanium_class" "unknown,tbit,ilog")])
1565 (define_insn_and_split "*andcmbi3"
1566 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1567 (and:BI (not:BI (match_operand:BI 1 "register_operand" "c,r,r"))
1568 (match_operand:BI 2 "register_operand" "0,0,r")))]
1572 tbit.z.and.orcm %0, %I0 = %1, 0
1575 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1576 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
1577 [(cond_exec (ne (match_dup 1) (const_int 0))
1578 (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0))
1581 [(set_attr "itanium_class" "unknown,tbit,ilog")])
1583 (define_insn_and_split "iorbi3"
1584 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1585 (ior:BI (match_operand:BI 1 "register_operand" "%0,0,r")
1586 (match_operand:BI 2 "register_operand" "c,r,r")))]
1590 tbit.nz.or.andcm %0, %I0 = %2, 0
1593 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1594 && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
1595 [(cond_exec (ne (match_dup 2) (const_int 0))
1596 (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0))
1599 [(set_attr "itanium_class" "unknown,tbit,ilog")])
1601 (define_insn_and_split "*iorcmbi3"
1602 [(set (match_operand:BI 0 "register_operand" "=c,c")
1603 (ior:BI (not:BI (match_operand:BI 1 "register_operand" "c,r"))
1604 (match_operand:BI 2 "register_operand" "0,0")))]
1608 tbit.z.or.andcm %0, %I0 = %1, 0"
1610 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1611 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
1612 [(cond_exec (eq (match_dup 1) (const_int 0))
1613 (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0))
1616 [(set_attr "itanium_class" "unknown,tbit")])
1618 (define_insn "one_cmplbi2"
1619 [(set (match_operand:BI 0 "register_operand" "=c,r,c,&c")
1620 (not:BI (match_operand:BI 1 "register_operand" "r,r,0,c")))
1621 (clobber (match_scratch:BI 2 "=X,X,c,X"))]
1624 tbit.z %0, %I0 = %1, 0
1628 [(set_attr "itanium_class" "tbit,ilog,unknown,unknown")])
1631 [(set (match_operand:BI 0 "register_operand" "")
1632 (not:BI (match_operand:BI 1 "register_operand" "")))
1633 (clobber (match_scratch:BI 2 ""))]
1635 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1636 && rtx_equal_p (operands[0], operands[1])"
1637 [(set (match_dup 4) (match_dup 3))
1638 (set (match_dup 0) (const_int 1))
1639 (cond_exec (ne (match_dup 2) (const_int 0))
1640 (set (match_dup 0) (const_int 0)))
1641 (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
1642 "operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1]));
1643 operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));")
1646 [(set (match_operand:BI 0 "register_operand" "")
1647 (not:BI (match_operand:BI 1 "register_operand" "")))
1648 (clobber (match_scratch:BI 2 ""))]
1650 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1651 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))
1652 && ! rtx_equal_p (operands[0], operands[1])"
1653 [(cond_exec (ne (match_dup 1) (const_int 0))
1654 (set (match_dup 0) (const_int 0)))
1655 (cond_exec (eq (match_dup 1) (const_int 0))
1656 (set (match_dup 0) (const_int 1)))
1657 (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
1660 (define_insn "*cmpsi_and_0"
1661 [(set (match_operand:BI 0 "register_operand" "=c")
1662 (and:BI (match_operator:BI 4 "predicate_operator"
1663 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1664 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])
1665 (match_operand:BI 1 "register_operand" "0")))]
1667 "cmp4.%C4.and.orcm %0, %I0 = %3, %r2"
1668 [(set_attr "itanium_class" "icmp")])
1670 (define_insn "*cmpsi_and_1"
1671 [(set (match_operand:BI 0 "register_operand" "=c")
1672 (and:BI (match_operator:BI 3 "signed_inequality_operator"
1673 [(match_operand:SI 2 "gr_register_operand" "r")
1675 (match_operand:BI 1 "register_operand" "0")))]
1677 "cmp4.%C3.and.orcm %0, %I0 = r0, %2"
1678 [(set_attr "itanium_class" "icmp")])
1680 (define_insn "*cmpsi_andnot_0"
1681 [(set (match_operand:BI 0 "register_operand" "=c")
1682 (and:BI (not:BI (match_operator:BI 4 "predicate_operator"
1683 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1684 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))
1685 (match_operand:BI 1 "register_operand" "0")))]
1687 "cmp4.%C4.or.andcm %I0, %0 = %3, %r2"
1688 [(set_attr "itanium_class" "icmp")])
1690 (define_insn "*cmpsi_andnot_1"
1691 [(set (match_operand:BI 0 "register_operand" "=c")
1692 (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1693 [(match_operand:SI 2 "gr_register_operand" "r")
1695 (match_operand:BI 1 "register_operand" "0")))]
1697 "cmp4.%C3.or.andcm %I0, %0 = r0, %2"
1698 [(set_attr "itanium_class" "icmp")])
1700 (define_insn "*cmpdi_and_0"
1701 [(set (match_operand:BI 0 "register_operand" "=c")
1702 (and:BI (match_operator:BI 4 "predicate_operator"
1703 [(match_operand:DI 2 "gr_register_operand" "r")
1704 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])
1705 (match_operand:BI 1 "register_operand" "0")))]
1707 "cmp.%C4.and.orcm %0, %I0 = %3, %2"
1708 [(set_attr "itanium_class" "icmp")])
1710 (define_insn "*cmpdi_and_1"
1711 [(set (match_operand:BI 0 "register_operand" "=c")
1712 (and:BI (match_operator:BI 3 "signed_inequality_operator"
1713 [(match_operand:DI 2 "gr_register_operand" "r")
1715 (match_operand:BI 1 "register_operand" "0")))]
1717 "cmp.%C3.and.orcm %0, %I0 = r0, %2"
1718 [(set_attr "itanium_class" "icmp")])
1720 (define_insn "*cmpdi_andnot_0"
1721 [(set (match_operand:BI 0 "register_operand" "=c")
1722 (and:BI (not:BI (match_operator:BI 4 "predicate_operator"
1723 [(match_operand:DI 2 "gr_register_operand" "r")
1724 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))
1725 (match_operand:BI 1 "register_operand" "0")))]
1727 "cmp.%C4.or.andcm %I0, %0 = %3, %2"
1728 [(set_attr "itanium_class" "icmp")])
1730 (define_insn "*cmpdi_andnot_1"
1731 [(set (match_operand:BI 0 "register_operand" "=c")
1732 (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1733 [(match_operand:DI 2 "gr_register_operand" "r")
1735 (match_operand:BI 1 "register_operand" "0")))]
1737 "cmp.%C3.or.andcm %I0, %0 = r0, %2"
1738 [(set_attr "itanium_class" "icmp")])
1740 (define_insn "*tbit_and_0"
1741 [(set (match_operand:BI 0 "register_operand" "=c")
1742 (and:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1745 (match_operand:BI 2 "register_operand" "0")))]
1747 "tbit.nz.and.orcm %0, %I0 = %1, 0"
1748 [(set_attr "itanium_class" "tbit")])
1750 (define_insn "*tbit_and_1"
1751 [(set (match_operand:BI 0 "register_operand" "=c")
1752 (and:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1755 (match_operand:BI 2 "register_operand" "0")))]
1757 "tbit.z.and.orcm %0, %I0 = %1, 0"
1758 [(set_attr "itanium_class" "tbit")])
1760 (define_insn "*tbit_and_2"
1761 [(set (match_operand:BI 0 "register_operand" "=c")
1762 (and:BI (ne:BI (zero_extract:DI
1763 (match_operand:DI 1 "gr_register_operand" "r")
1765 (match_operand:DI 2 "const_int_operand" "n"))
1767 (match_operand:BI 3 "register_operand" "0")))]
1769 "tbit.nz.and.orcm %0, %I0 = %1, %2"
1770 [(set_attr "itanium_class" "tbit")])
1772 (define_insn "*tbit_and_3"
1773 [(set (match_operand:BI 0 "register_operand" "=c")
1774 (and:BI (eq:BI (zero_extract:DI
1775 (match_operand:DI 1 "gr_register_operand" "r")
1777 (match_operand:DI 2 "const_int_operand" "n"))
1779 (match_operand:BI 3 "register_operand" "0")))]
1781 "tbit.z.and.orcm %0, %I0 = %1, %2"
1782 [(set_attr "itanium_class" "tbit")])
1784 (define_insn "*cmpsi_or_0"
1785 [(set (match_operand:BI 0 "register_operand" "=c")
1786 (ior:BI (match_operator:BI 4 "predicate_operator"
1787 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1788 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])
1789 (match_operand:BI 1 "register_operand" "0")))]
1791 "cmp4.%C4.or.andcm %0, %I0 = %3, %r2"
1792 [(set_attr "itanium_class" "icmp")])
1794 (define_insn "*cmpsi_or_1"
1795 [(set (match_operand:BI 0 "register_operand" "=c")
1796 (ior:BI (match_operator:BI 3 "signed_inequality_operator"
1797 [(match_operand:SI 2 "gr_register_operand" "r")
1799 (match_operand:BI 1 "register_operand" "0")))]
1801 "cmp4.%C3.or.andcm %0, %I0 = r0, %2"
1802 [(set_attr "itanium_class" "icmp")])
1804 (define_insn "*cmpsi_orcm_0"
1805 [(set (match_operand:BI 0 "register_operand" "=c")
1806 (ior:BI (not:BI (match_operator:BI 4 "predicate_operator"
1807 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1808 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))
1809 (match_operand:BI 1 "register_operand" "0")))]
1811 "cmp4.%C4.and.orcm %I0, %0 = %3, %r2"
1812 [(set_attr "itanium_class" "icmp")])
1814 (define_insn "*cmpsi_orcm_1"
1815 [(set (match_operand:BI 0 "register_operand" "=c")
1816 (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1817 [(match_operand:SI 2 "gr_register_operand" "r")
1819 (match_operand:BI 1 "register_operand" "0")))]
1821 "cmp4.%C3.and.orcm %I0, %0 = r0, %2"
1822 [(set_attr "itanium_class" "icmp")])
1824 (define_insn "*cmpdi_or_0"
1825 [(set (match_operand:BI 0 "register_operand" "=c")
1826 (ior:BI (match_operator:BI 4 "predicate_operator"
1827 [(match_operand:DI 2 "gr_register_operand" "r")
1828 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])
1829 (match_operand:BI 1 "register_operand" "0")))]
1831 "cmp.%C4.or.andcm %0, %I0 = %3, %2"
1832 [(set_attr "itanium_class" "icmp")])
1834 (define_insn "*cmpdi_or_1"
1835 [(set (match_operand:BI 0 "register_operand" "=c")
1836 (ior:BI (match_operator:BI 3 "signed_inequality_operator"
1837 [(match_operand:DI 2 "gr_register_operand" "r")
1839 (match_operand:BI 1 "register_operand" "0")))]
1841 "cmp.%C3.or.andcm %0, %I0 = r0, %2"
1842 [(set_attr "itanium_class" "icmp")])
1844 (define_insn "*cmpdi_orcm_0"
1845 [(set (match_operand:BI 0 "register_operand" "=c")
1846 (ior:BI (not:BI (match_operator:BI 4 "predicate_operator"
1847 [(match_operand:DI 2 "gr_register_operand" "r")
1848 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))
1849 (match_operand:BI 1 "register_operand" "0")))]
1851 "cmp.%C4.and.orcm %I0, %0 = %3, %2"
1852 [(set_attr "itanium_class" "icmp")])
1854 (define_insn "*cmpdi_orcm_1"
1855 [(set (match_operand:BI 0 "register_operand" "=c")
1856 (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1857 [(match_operand:DI 2 "gr_register_operand" "r")
1859 (match_operand:BI 1 "register_operand" "0")))]
1861 "cmp.%C3.and.orcm %I0, %0 = r0, %2"
1862 [(set_attr "itanium_class" "icmp")])
1864 (define_insn "*tbit_or_0"
1865 [(set (match_operand:BI 0 "register_operand" "=c")
1866 (ior:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1869 (match_operand:BI 2 "register_operand" "0")))]
1871 "tbit.nz.or.andcm %0, %I0 = %1, 0"
1872 [(set_attr "itanium_class" "tbit")])
1874 (define_insn "*tbit_or_1"
1875 [(set (match_operand:BI 0 "register_operand" "=c")
1876 (ior:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1879 (match_operand:BI 2 "register_operand" "0")))]
1881 "tbit.z.or.andcm %0, %I0 = %1, 0"
1882 [(set_attr "itanium_class" "tbit")])
1884 (define_insn "*tbit_or_2"
1885 [(set (match_operand:BI 0 "register_operand" "=c")
1886 (ior:BI (ne:BI (zero_extract:DI
1887 (match_operand:DI 1 "gr_register_operand" "r")
1889 (match_operand:DI 2 "const_int_operand" "n"))
1891 (match_operand:BI 3 "register_operand" "0")))]
1893 "tbit.nz.or.andcm %0, %I0 = %1, %2"
1894 [(set_attr "itanium_class" "tbit")])
1896 (define_insn "*tbit_or_3"
1897 [(set (match_operand:BI 0 "register_operand" "=c")
1898 (ior:BI (eq:BI (zero_extract:DI
1899 (match_operand:DI 1 "gr_register_operand" "r")
1901 (match_operand:DI 2 "const_int_operand" "n"))
1903 (match_operand:BI 3 "register_operand" "0")))]
1905 "tbit.z.or.andcm %0, %I0 = %1, %2"
1906 [(set_attr "itanium_class" "tbit")])
1908 ;; Transform test of and/or of setcc into parallel comparisons.
1911 [(set (match_operand:BI 0 "register_operand" "")
1912 (ne:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1914 (match_operand:DI 3 "register_operand" ""))
1918 (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0))
1923 [(set (match_operand:BI 0 "register_operand" "")
1924 (eq:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1926 (match_operand:DI 3 "register_operand" ""))
1930 (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0))
1932 (parallel [(set (match_dup 0) (not:BI (match_dup 0)))
1933 (clobber (scratch))])]
1937 [(set (match_operand:BI 0 "register_operand" "")
1938 (ne:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1940 (match_operand:DI 3 "register_operand" ""))
1944 (ior:BI (ne:BI (match_dup 3) (const_int 0))
1949 [(set (match_operand:BI 0 "register_operand" "")
1950 (eq:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1952 (match_operand:DI 3 "register_operand" ""))
1956 (ior:BI (ne:BI (match_dup 3) (const_int 0))
1958 (parallel [(set (match_dup 0) (not:BI (match_dup 0)))
1959 (clobber (scratch))])]
1962 ;; ??? Incredibly hackish. Either need four proper patterns with all
1963 ;; the alternatives, or rely on sched1 to split the insn and hope that
1964 ;; nothing bad happens to the comparisons in the meantime.
1966 ;; Alternately, adjust combine to allow 2->2 and 3->3 splits, assuming
1967 ;; that we're doing height reduction.
1969 ;(define_insn_and_split ""
1970 ; [(set (match_operand:BI 0 "register_operand" "=c")
1971 ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator"
1972 ; [(match_operand 2 "" "")
1973 ; (match_operand 3 "" "")])
1974 ; (match_operator:BI 4 "comparison_operator"
1975 ; [(match_operand 5 "" "")
1976 ; (match_operand 6 "" "")]))
1978 ; "flag_schedule_insns"
1981 ; [(set (match_dup 0) (and:BI (match_dup 1) (match_dup 0)))
1982 ; (set (match_dup 0) (and:BI (match_dup 4) (match_dup 0)))]
1985 ;(define_insn_and_split ""
1986 ; [(set (match_operand:BI 0 "register_operand" "=c")
1987 ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator"
1988 ; [(match_operand 2 "" "")
1989 ; (match_operand 3 "" "")])
1990 ; (match_operator:BI 4 "comparison_operator"
1991 ; [(match_operand 5 "" "")
1992 ; (match_operand 6 "" "")]))
1994 ; "flag_schedule_insns"
1997 ; [(set (match_dup 0) (ior:BI (match_dup 1) (match_dup 0)))
1998 ; (set (match_dup 0) (ior:BI (match_dup 4) (match_dup 0)))]
2002 ; [(set (match_operand:BI 0 "register_operand" "")
2003 ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator"
2004 ; [(match_operand 2 "" "")
2005 ; (match_operand 3 "" "")])
2006 ; (match_operand:BI 7 "register_operand" ""))
2007 ; (and:BI (match_operator:BI 4 "comparison_operator"
2008 ; [(match_operand 5 "" "")
2009 ; (match_operand 6 "" "")])
2010 ; (match_operand:BI 8 "register_operand" ""))))]
2012 ; [(set (match_dup 0) (and:BI (match_dup 7) (match_dup 8)))
2013 ; (set (match_dup 0) (and:BI (and:BI (match_dup 1) (match_dup 4))
2018 ; [(set (match_operand:BI 0 "register_operand" "")
2019 ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator"
2020 ; [(match_operand 2 "" "")
2021 ; (match_operand 3 "" "")])
2022 ; (match_operand:BI 7 "register_operand" ""))
2023 ; (ior:BI (match_operator:BI 4 "comparison_operator"
2024 ; [(match_operand 5 "" "")
2025 ; (match_operand 6 "" "")])
2026 ; (match_operand:BI 8 "register_operand" ""))))]
2028 ; [(set (match_dup 0) (ior:BI (match_dup 7) (match_dup 8)))
2029 ; (set (match_dup 0) (ior:BI (ior:BI (match_dup 1) (match_dup 4))
2033 ;; Try harder to avoid predicate copies by duplicating compares.
2034 ;; Note that we'll have already split the predicate copy, which
2035 ;; is kind of a pain, but oh well.
2038 [(set (match_operand:BI 0 "register_operand" "")
2039 (match_operand:BI 1 "comparison_operator" ""))
2040 (set (match_operand:CCI 2 "register_operand" "")
2041 (match_operand:CCI 3 "register_operand" ""))
2042 (set (match_operand:CCI 4 "register_operand" "")
2043 (match_operand:CCI 5 "register_operand" ""))
2044 (set (match_operand:BI 6 "register_operand" "")
2045 (unspec:BI [(match_dup 6)] UNSPEC_PRED_REL_MUTEX))]
2046 "REGNO (operands[3]) == REGNO (operands[0])
2047 && REGNO (operands[4]) == REGNO (operands[0]) + 1
2048 && REGNO (operands[4]) == REGNO (operands[2]) + 1
2049 && REGNO (operands[6]) == REGNO (operands[2])"
2050 [(set (match_dup 0) (match_dup 1))
2051 (set (match_dup 6) (match_dup 7))]
2052 "operands[7] = copy_rtx (operands[1]);")
2054 ;; ::::::::::::::::::::
2056 ;; :: 16 bit Integer arithmetic
2058 ;; ::::::::::::::::::::
2060 (define_insn "mulhi3"
2061 [(set (match_operand:HI 0 "gr_register_operand" "=r")
2062 (mult:HI (match_operand:HI 1 "gr_register_operand" "r")
2063 (match_operand:HI 2 "gr_register_operand" "r")))]
2065 "pmpy2.r %0 = %1, %2"
2066 [(set_attr "itanium_class" "mmmul")])
2069 ;; ::::::::::::::::::::
2071 ;; :: 32 bit Integer arithmetic
2073 ;; ::::::::::::::::::::
2075 (define_insn "addsi3"
2076 [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r")
2077 (plus:SI (match_operand:SI 1 "gr_register_operand" "%r,r,a")
2078 (match_operand:SI 2 "gr_reg_or_22bit_operand" "r,I,J")))]
2084 [(set_attr "itanium_class" "ialu")])
2086 (define_insn "*addsi3_plus1"
2087 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2088 (plus:SI (plus:SI (match_operand:SI 1 "gr_register_operand" "r")
2089 (match_operand:SI 2 "gr_register_operand" "r"))
2092 "add %0 = %1, %2, 1"
2093 [(set_attr "itanium_class" "ialu")])
2095 (define_insn "*addsi3_plus1_alt"
2096 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2097 (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r")
2101 "add %0 = %1, %1, 1"
2102 [(set_attr "itanium_class" "ialu")])
2104 (define_insn "*addsi3_shladd"
2105 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2106 (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r")
2107 (match_operand:SI 2 "shladd_operand" "n"))
2108 (match_operand:SI 3 "gr_register_operand" "r")))]
2110 "shladd %0 = %1, %S2, %3"
2111 [(set_attr "itanium_class" "ialu")])
2113 (define_insn "subsi3"
2114 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2115 (minus:SI (match_operand:SI 1 "gr_reg_or_8bit_operand" "rK")
2116 (match_operand:SI 2 "gr_register_operand" "r")))]
2119 [(set_attr "itanium_class" "ialu")])
2121 (define_insn "*subsi3_minus1"
2122 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2123 (plus:SI (not:SI (match_operand:SI 1 "gr_register_operand" "r"))
2124 (match_operand:SI 2 "gr_register_operand" "r")))]
2126 "sub %0 = %2, %1, 1"
2127 [(set_attr "itanium_class" "ialu")])
2129 ;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns.
2131 (define_insn "mulsi3"
2132 [(set (match_operand:SI 0 "fr_register_operand" "=f")
2133 (mult:SI (match_operand:SI 1 "grfr_register_operand" "f")
2134 (match_operand:SI 2 "grfr_register_operand" "f")))]
2136 "xmpy.l %0 = %1, %2"
2137 [(set_attr "itanium_class" "xmpy")])
2139 (define_insn "maddsi4"
2140 [(set (match_operand:SI 0 "fr_register_operand" "=f")
2141 (plus:SI (mult:SI (match_operand:SI 1 "grfr_register_operand" "f")
2142 (match_operand:SI 2 "grfr_register_operand" "f"))
2143 (match_operand:SI 3 "grfr_register_operand" "f")))]
2145 "xma.l %0 = %1, %2, %3"
2146 [(set_attr "itanium_class" "xmpy")])
2148 (define_insn "negsi2"
2149 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2150 (neg:SI (match_operand:SI 1 "gr_register_operand" "r")))]
2153 [(set_attr "itanium_class" "ialu")])
2155 (define_expand "abssi2"
2157 (ge:BI (match_operand:SI 1 "gr_register_operand" "") (const_int 0)))
2158 (set (match_operand:SI 0 "gr_register_operand" "")
2159 (if_then_else:SI (eq (match_dup 2) (const_int 0))
2160 (neg:SI (match_dup 1))
2163 { operands[2] = gen_reg_rtx (BImode); })
2165 (define_expand "sminsi3"
2167 (ge:BI (match_operand:SI 1 "gr_register_operand" "")
2168 (match_operand:SI 2 "gr_register_operand" "")))
2169 (set (match_operand:SI 0 "gr_register_operand" "")
2170 (if_then_else:SI (ne (match_dup 3) (const_int 0))
2171 (match_dup 2) (match_dup 1)))]
2173 { operands[3] = gen_reg_rtx (BImode); })
2175 (define_expand "smaxsi3"
2177 (ge:BI (match_operand:SI 1 "gr_register_operand" "")
2178 (match_operand:SI 2 "gr_register_operand" "")))
2179 (set (match_operand:SI 0 "gr_register_operand" "")
2180 (if_then_else:SI (ne (match_dup 3) (const_int 0))
2181 (match_dup 1) (match_dup 2)))]
2183 { operands[3] = gen_reg_rtx (BImode); })
2185 (define_expand "uminsi3"
2187 (geu:BI (match_operand:SI 1 "gr_register_operand" "")
2188 (match_operand:SI 2 "gr_register_operand" "")))
2189 (set (match_operand:SI 0 "gr_register_operand" "")
2190 (if_then_else:SI (ne (match_dup 3) (const_int 0))
2191 (match_dup 2) (match_dup 1)))]
2193 { operands[3] = gen_reg_rtx (BImode); })
2195 (define_expand "umaxsi3"
2197 (geu:BI (match_operand:SI 1 "gr_register_operand" "")
2198 (match_operand:SI 2 "gr_register_operand" "")))
2199 (set (match_operand:SI 0 "gr_register_operand" "")
2200 (if_then_else:SI (ne (match_dup 3) (const_int 0))
2201 (match_dup 1) (match_dup 2)))]
2203 { operands[3] = gen_reg_rtx (BImode); })
2205 (define_expand "divsi3"
2206 [(set (match_operand:SI 0 "register_operand" "")
2207 (div:SI (match_operand:SI 1 "general_operand" "")
2208 (match_operand:SI 2 "general_operand" "")))]
2209 "TARGET_INLINE_INT_DIV"
2211 rtx op1_xf, op2_xf, op0_xf, op0_di, twon34, twon34_exp;
2213 op0_xf = gen_reg_rtx (XFmode);
2214 op0_di = gen_reg_rtx (DImode);
2216 if (CONSTANT_P (operands[1]))
2217 operands[1] = force_reg (SImode, operands[1]);
2218 op1_xf = gen_reg_rtx (XFmode);
2219 expand_float (op1_xf, operands[1], 0);
2221 if (CONSTANT_P (operands[2]))
2222 operands[2] = force_reg (SImode, operands[2]);
2223 op2_xf = gen_reg_rtx (XFmode);
2224 expand_float (op2_xf, operands[2], 0);
2227 twon34_exp = gen_reg_rtx (DImode);
2228 emit_move_insn (twon34_exp, GEN_INT (65501));
2229 twon34 = gen_reg_rtx (XFmode);
2230 emit_insn (gen_setf_exp_xf (twon34, twon34_exp));
2232 emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34));
2234 emit_insn (gen_fix_truncxfdi2_alts (op0_di, op0_xf, const1_rtx));
2235 emit_move_insn (operands[0], gen_lowpart (SImode, op0_di));
2239 (define_expand "modsi3"
2240 [(set (match_operand:SI 0 "register_operand" "")
2241 (mod:SI (match_operand:SI 1 "general_operand" "")
2242 (match_operand:SI 2 "general_operand" "")))]
2243 "TARGET_INLINE_INT_DIV"
2245 rtx op2_neg, op1_di, div;
2247 div = gen_reg_rtx (SImode);
2248 emit_insn (gen_divsi3 (div, operands[1], operands[2]));
2250 op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0);
2252 /* This is a trick to get us to reuse the value that we're sure to
2253 have already copied to the FP regs. */
2254 op1_di = gen_reg_rtx (DImode);
2255 convert_move (op1_di, operands[1], 0);
2257 emit_insn (gen_maddsi4 (operands[0], div, op2_neg,
2258 gen_lowpart (SImode, op1_di)));
2262 (define_expand "udivsi3"
2263 [(set (match_operand:SI 0 "register_operand" "")
2264 (udiv:SI (match_operand:SI 1 "general_operand" "")
2265 (match_operand:SI 2 "general_operand" "")))]
2266 "TARGET_INLINE_INT_DIV"
2268 rtx op1_xf, op2_xf, op0_xf, op0_di, twon34, twon34_exp;
2270 op0_xf = gen_reg_rtx (XFmode);
2271 op0_di = gen_reg_rtx (DImode);
2273 if (CONSTANT_P (operands[1]))
2274 operands[1] = force_reg (SImode, operands[1]);
2275 op1_xf = gen_reg_rtx (XFmode);
2276 expand_float (op1_xf, operands[1], 1);
2278 if (CONSTANT_P (operands[2]))
2279 operands[2] = force_reg (SImode, operands[2]);
2280 op2_xf = gen_reg_rtx (XFmode);
2281 expand_float (op2_xf, operands[2], 1);
2284 twon34_exp = gen_reg_rtx (DImode);
2285 emit_move_insn (twon34_exp, GEN_INT (65501));
2286 twon34 = gen_reg_rtx (XFmode);
2287 emit_insn (gen_setf_exp_xf (twon34, twon34_exp));
2289 emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34));
2291 emit_insn (gen_fixuns_truncxfdi2_alts (op0_di, op0_xf, const1_rtx));
2292 emit_move_insn (operands[0], gen_lowpart (SImode, op0_di));
2296 (define_expand "umodsi3"
2297 [(set (match_operand:SI 0 "register_operand" "")
2298 (umod:SI (match_operand:SI 1 "general_operand" "")
2299 (match_operand:SI 2 "general_operand" "")))]
2300 "TARGET_INLINE_INT_DIV"
2302 rtx op2_neg, op1_di, div;
2304 div = gen_reg_rtx (SImode);
2305 emit_insn (gen_udivsi3 (div, operands[1], operands[2]));
2307 op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0);
2309 /* This is a trick to get us to reuse the value that we're sure to
2310 have already copied to the FP regs. */
2311 op1_di = gen_reg_rtx (DImode);
2312 convert_move (op1_di, operands[1], 1);
2314 emit_insn (gen_maddsi4 (operands[0], div, op2_neg,
2315 gen_lowpart (SImode, op1_di)));
2319 (define_insn_and_split "divsi3_internal"
2320 [(set (match_operand:XF 0 "fr_register_operand" "=&f")
2321 (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f")
2322 (match_operand:XF 2 "fr_register_operand" "f"))))
2323 (clobber (match_scratch:XF 4 "=&f"))
2324 (clobber (match_scratch:XF 5 "=&f"))
2325 (clobber (match_scratch:BI 6 "=c"))
2326 (use (match_operand:XF 3 "fr_register_operand" "f"))]
2327 "TARGET_INLINE_INT_DIV"
2329 "&& reload_completed"
2330 [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2)))
2331 (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)]
2332 UNSPEC_FR_RECIP_APPROX))
2333 (use (const_int 1))])
2334 (cond_exec (ne (match_dup 6) (const_int 0))
2335 (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0)))
2336 (use (const_int 1))]))
2337 (cond_exec (ne (match_dup 6) (const_int 0))
2338 (parallel [(set (match_dup 5)
2339 (minus:XF (match_dup 7)
2340 (mult:XF (match_dup 2) (match_dup 0))))
2341 (use (const_int 1))]))
2342 (cond_exec (ne (match_dup 6) (const_int 0))
2343 (parallel [(set (match_dup 4)
2344 (plus:XF (mult:XF (match_dup 5) (match_dup 4))
2346 (use (const_int 1))]))
2347 (cond_exec (ne (match_dup 6) (const_int 0))
2348 (parallel [(set (match_dup 5)
2349 (plus:XF (mult:XF (match_dup 5) (match_dup 5))
2351 (use (const_int 1))]))
2352 (cond_exec (ne (match_dup 6) (const_int 0))
2353 (parallel [(set (match_dup 0)
2354 (plus:XF (mult:XF (match_dup 5) (match_dup 4))
2356 (use (const_int 1))]))
2358 "operands[7] = CONST1_RTX (XFmode);"
2359 [(set_attr "predicable" "no")])
2361 ;; ::::::::::::::::::::
2363 ;; :: 64 bit Integer arithmetic
2365 ;; ::::::::::::::::::::
2367 (define_insn "adddi3"
2368 [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r")
2369 (plus:DI (match_operand:DI 1 "gr_register_operand" "%r,r,a")
2370 (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))]
2376 [(set_attr "itanium_class" "ialu")])
2378 (define_insn "*adddi3_plus1"
2379 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2380 (plus:DI (plus:DI (match_operand:DI 1 "gr_register_operand" "r")
2381 (match_operand:DI 2 "gr_register_operand" "r"))
2384 "add %0 = %1, %2, 1"
2385 [(set_attr "itanium_class" "ialu")])
2387 ;; This has some of the same problems as shladd. We let the shladd
2388 ;; eliminator hack handle it, which results in the 1 being forced into
2389 ;; a register, but not more ugliness here.
2390 (define_insn "*adddi3_plus1_alt"
2391 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2392 (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
2396 "add %0 = %1, %1, 1"
2397 [(set_attr "itanium_class" "ialu")])
2399 (define_insn "subdi3"
2400 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2401 (minus:DI (match_operand:DI 1 "gr_reg_or_8bit_operand" "rK")
2402 (match_operand:DI 2 "gr_register_operand" "r")))]
2405 [(set_attr "itanium_class" "ialu")])
2407 (define_insn "*subdi3_minus1"
2408 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2409 (plus:DI (not:DI (match_operand:DI 1 "gr_register_operand" "r"))
2410 (match_operand:DI 2 "gr_register_operand" "r")))]
2412 "sub %0 = %2, %1, 1"
2413 [(set_attr "itanium_class" "ialu")])
2415 ;; ??? Use grfr instead of fr because of virtual register elimination
2416 ;; and silly test cases multiplying by the frame pointer.
2417 (define_insn "muldi3"
2418 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2419 (mult:DI (match_operand:DI 1 "grfr_register_operand" "f")
2420 (match_operand:DI 2 "grfr_register_operand" "f")))]
2422 "xmpy.l %0 = %1, %2"
2423 [(set_attr "itanium_class" "xmpy")])
2425 ;; ??? If operand 3 is an eliminable reg, then register elimination causes the
2426 ;; same problem that we have with shladd below. Unfortunately, this case is
2427 ;; much harder to fix because the multiply puts the result in an FP register,
2428 ;; but the add needs inputs from a general register. We add a spurious clobber
2429 ;; here so that it will be present just in case register elimination gives us
2430 ;; the funny result.
2432 ;; ??? Maybe validate_changes should try adding match_scratch clobbers?
2434 ;; ??? Maybe we should change how adds are canonicalized.
2436 (define_insn "madddi4"
2437 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2438 (plus:DI (mult:DI (match_operand:DI 1 "grfr_register_operand" "f")
2439 (match_operand:DI 2 "grfr_register_operand" "f"))
2440 (match_operand:DI 3 "grfr_register_operand" "f")))
2441 (clobber (match_scratch:DI 4 "=X"))]
2443 "xma.l %0 = %1, %2, %3"
2444 [(set_attr "itanium_class" "xmpy")])
2446 ;; This can be created by register elimination if operand3 of shladd is an
2447 ;; eliminable register or has reg_equiv_constant set.
2449 ;; We have to use nonmemory_operand for operand 4, to ensure that the
2450 ;; validate_changes call inside eliminate_regs will always succeed. If it
2451 ;; doesn't succeed, then this remain a madddi4 pattern, and will be reloaded
2454 (define_insn "*madddi4_elim"
2455 [(set (match_operand:DI 0 "register_operand" "=&r")
2456 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f")
2457 (match_operand:DI 2 "register_operand" "f"))
2458 (match_operand:DI 3 "register_operand" "f"))
2459 (match_operand:DI 4 "nonmemory_operand" "rI")))
2460 (clobber (match_scratch:DI 5 "=f"))]
2461 "reload_in_progress"
2463 [(set_attr "itanium_class" "unknown")])
2466 [(set (match_operand:DI 0 "register_operand" "")
2467 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2468 (match_operand:DI 2 "register_operand" ""))
2469 (match_operand:DI 3 "register_operand" ""))
2470 (match_operand:DI 4 "gr_reg_or_14bit_operand" "")))
2471 (clobber (match_scratch:DI 5 ""))]
2473 [(parallel [(set (match_dup 5) (plus:DI (mult:DI (match_dup 1) (match_dup 2))
2475 (clobber (match_dup 0))])
2476 (set (match_dup 0) (match_dup 5))
2477 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
2480 ;; ??? There are highpart multiply and add instructions, but we have no way
2481 ;; to generate them.
2483 (define_insn "smuldi3_highpart"
2484 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2487 (mult:TI (sign_extend:TI
2488 (match_operand:DI 1 "fr_register_operand" "f"))
2490 (match_operand:DI 2 "fr_register_operand" "f")))
2493 "xmpy.h %0 = %1, %2"
2494 [(set_attr "itanium_class" "xmpy")])
2496 (define_insn "umuldi3_highpart"
2497 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2500 (mult:TI (zero_extend:TI
2501 (match_operand:DI 1 "fr_register_operand" "f"))
2503 (match_operand:DI 2 "fr_register_operand" "f")))
2506 "xmpy.hu %0 = %1, %2"
2507 [(set_attr "itanium_class" "xmpy")])
2509 (define_insn "negdi2"
2510 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2511 (neg:DI (match_operand:DI 1 "gr_register_operand" "r")))]
2514 [(set_attr "itanium_class" "ialu")])
2516 (define_expand "absdi2"
2518 (ge:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0)))
2519 (set (match_operand:DI 0 "gr_register_operand" "")
2520 (if_then_else:DI (eq (match_dup 2) (const_int 0))
2521 (neg:DI (match_dup 1))
2524 { operands[2] = gen_reg_rtx (BImode); })
2526 (define_expand "smindi3"
2528 (ge:BI (match_operand:DI 1 "gr_register_operand" "")
2529 (match_operand:DI 2 "gr_register_operand" "")))
2530 (set (match_operand:DI 0 "gr_register_operand" "")
2531 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2532 (match_dup 2) (match_dup 1)))]
2534 { operands[3] = gen_reg_rtx (BImode); })
2536 (define_expand "smaxdi3"
2538 (ge:BI (match_operand:DI 1 "gr_register_operand" "")
2539 (match_operand:DI 2 "gr_register_operand" "")))
2540 (set (match_operand:DI 0 "gr_register_operand" "")
2541 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2542 (match_dup 1) (match_dup 2)))]
2544 { operands[3] = gen_reg_rtx (BImode); })
2546 (define_expand "umindi3"
2548 (geu:BI (match_operand:DI 1 "gr_register_operand" "")
2549 (match_operand:DI 2 "gr_register_operand" "")))
2550 (set (match_operand:DI 0 "gr_register_operand" "")
2551 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2552 (match_dup 2) (match_dup 1)))]
2554 { operands[3] = gen_reg_rtx (BImode); })
2556 (define_expand "umaxdi3"
2558 (geu:BI (match_operand:DI 1 "gr_register_operand" "")
2559 (match_operand:DI 2 "gr_register_operand" "")))
2560 (set (match_operand:DI 0 "gr_register_operand" "")
2561 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2562 (match_dup 1) (match_dup 2)))]
2564 { operands[3] = gen_reg_rtx (BImode); })
2566 (define_expand "ffsdi2"
2568 (eq:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0)))
2569 (set (match_dup 2) (plus:DI (match_dup 1) (const_int -1)))
2570 (set (match_dup 5) (const_int 0))
2571 (set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2)))
2572 (set (match_dup 4) (popcount:DI (match_dup 3)))
2573 (set (match_operand:DI 0 "gr_register_operand" "")
2574 (if_then_else:DI (ne (match_dup 6) (const_int 0))
2575 (match_dup 5) (match_dup 4)))]
2578 operands[2] = gen_reg_rtx (DImode);
2579 operands[3] = gen_reg_rtx (DImode);
2580 operands[4] = gen_reg_rtx (DImode);
2581 operands[5] = gen_reg_rtx (DImode);
2582 operands[6] = gen_reg_rtx (BImode);
2585 (define_expand "ctzdi2"
2586 [(set (match_dup 2) (plus:DI (match_operand:DI 1 "gr_register_operand" "")
2588 (set (match_dup 3) (not:DI (match_dup 1)))
2589 (set (match_dup 4) (and:DI (match_dup 2) (match_dup 3)))
2590 (set (match_operand:DI 0 "gr_register_operand" "")
2591 (popcount:DI (match_dup 4)))]
2594 operands[2] = gen_reg_rtx (DImode);
2595 operands[3] = gen_reg_rtx (DImode);
2596 operands[4] = gen_reg_rtx (DImode);
2599 ;; Note the computation here is op0 = 63 - (exp - 0xffff).
2600 (define_expand "clzdi2"
2602 (unsigned_float:XF (match_operand:DI 1 "fr_register_operand" "")))
2604 (unspec:DI [(match_dup 2)] UNSPEC_GETF_EXP))
2605 (set (match_dup 4) (const_int 65598))
2606 (set (match_operand:DI 0 "gr_register_operand" "")
2607 (minus:DI (match_dup 4) (match_dup 3)))]
2610 operands[2] = gen_reg_rtx (XFmode);
2611 operands[3] = gen_reg_rtx (DImode);
2612 operands[4] = gen_reg_rtx (DImode);
2615 (define_insn "popcountdi2"
2616 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2617 (popcount:DI (match_operand:DI 1 "gr_register_operand" "r")))]
2620 [(set_attr "itanium_class" "mmmul")])
2622 (define_insn "*getf_exp_xf"
2623 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2624 (unspec:DI [(match_operand:XF 1 "fr_register_operand" "f")]
2628 [(set_attr "itanium_class" "frfr")])
2630 (define_expand "divdi3"
2631 [(set (match_operand:DI 0 "register_operand" "")
2632 (div:DI (match_operand:DI 1 "general_operand" "")
2633 (match_operand:DI 2 "general_operand" "")))]
2634 "TARGET_INLINE_INT_DIV"
2636 rtx op1_xf, op2_xf, op0_xf;
2638 op0_xf = gen_reg_rtx (XFmode);
2640 if (CONSTANT_P (operands[1]))
2641 operands[1] = force_reg (DImode, operands[1]);
2642 op1_xf = gen_reg_rtx (XFmode);
2643 expand_float (op1_xf, operands[1], 0);
2645 if (CONSTANT_P (operands[2]))
2646 operands[2] = force_reg (DImode, operands[2]);
2647 op2_xf = gen_reg_rtx (XFmode);
2648 expand_float (op2_xf, operands[2], 0);
2650 if (TARGET_INLINE_INT_DIV_LAT)
2651 emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf));
2653 emit_insn (gen_divdi3_internal_thr (op0_xf, op1_xf, op2_xf));
2655 emit_insn (gen_fix_truncxfdi2_alts (operands[0], op0_xf, const1_rtx));
2659 (define_expand "moddi3"
2660 [(set (match_operand:DI 0 "register_operand" "")
2661 (mod:SI (match_operand:DI 1 "general_operand" "")
2662 (match_operand:DI 2 "general_operand" "")))]
2663 "TARGET_INLINE_INT_DIV"
2667 div = gen_reg_rtx (DImode);
2668 emit_insn (gen_divdi3 (div, operands[1], operands[2]));
2670 op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0);
2672 emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1]));
2676 (define_expand "udivdi3"
2677 [(set (match_operand:DI 0 "register_operand" "")
2678 (udiv:DI (match_operand:DI 1 "general_operand" "")
2679 (match_operand:DI 2 "general_operand" "")))]
2680 "TARGET_INLINE_INT_DIV"
2682 rtx op1_xf, op2_xf, op0_xf;
2684 op0_xf = gen_reg_rtx (XFmode);
2686 if (CONSTANT_P (operands[1]))
2687 operands[1] = force_reg (DImode, operands[1]);
2688 op1_xf = gen_reg_rtx (XFmode);
2689 expand_float (op1_xf, operands[1], 1);
2691 if (CONSTANT_P (operands[2]))
2692 operands[2] = force_reg (DImode, operands[2]);
2693 op2_xf = gen_reg_rtx (XFmode);
2694 expand_float (op2_xf, operands[2], 1);
2696 if (TARGET_INLINE_INT_DIV_LAT)
2697 emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf));
2699 emit_insn (gen_divdi3_internal_thr (op0_xf, op1_xf, op2_xf));
2701 emit_insn (gen_fixuns_truncxfdi2_alts (operands[0], op0_xf, const1_rtx));
2705 (define_expand "umoddi3"
2706 [(set (match_operand:DI 0 "register_operand" "")
2707 (umod:DI (match_operand:DI 1 "general_operand" "")
2708 (match_operand:DI 2 "general_operand" "")))]
2709 "TARGET_INLINE_INT_DIV"
2713 div = gen_reg_rtx (DImode);
2714 emit_insn (gen_udivdi3 (div, operands[1], operands[2]));
2716 op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0);
2718 emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1]));
2722 (define_insn_and_split "divdi3_internal_lat"
2723 [(set (match_operand:XF 0 "fr_register_operand" "=&f")
2724 (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f")
2725 (match_operand:XF 2 "fr_register_operand" "f"))))
2726 (clobber (match_scratch:XF 3 "=&f"))
2727 (clobber (match_scratch:XF 4 "=&f"))
2728 (clobber (match_scratch:XF 5 "=&f"))
2729 (clobber (match_scratch:BI 6 "=c"))]
2730 "TARGET_INLINE_INT_DIV_LAT"
2732 "&& reload_completed"
2733 [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2)))
2734 (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)]
2735 UNSPEC_FR_RECIP_APPROX))
2736 (use (const_int 1))])
2737 (cond_exec (ne (match_dup 6) (const_int 0))
2738 (parallel [(set (match_dup 3)
2739 (minus:XF (match_dup 7)
2740 (mult:XF (match_dup 2) (match_dup 0))))
2741 (use (const_int 1))]))
2742 (cond_exec (ne (match_dup 6) (const_int 0))
2743 (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0)))
2744 (use (const_int 1))]))
2745 (cond_exec (ne (match_dup 6) (const_int 0))
2746 (parallel [(set (match_dup 5) (mult:XF (match_dup 3) (match_dup 3)))
2747 (use (const_int 1))]))
2748 (cond_exec (ne (match_dup 6) (const_int 0))
2749 (parallel [(set (match_dup 4)
2750 (plus:XF (mult:XF (match_dup 3) (match_dup 4))
2752 (use (const_int 1))]))
2753 (cond_exec (ne (match_dup 6) (const_int 0))
2754 (parallel [(set (match_dup 0)
2755 (plus:XF (mult:XF (match_dup 3) (match_dup 0))
2757 (use (const_int 1))]))
2758 (cond_exec (ne (match_dup 6) (const_int 0))
2759 (parallel [(set (match_dup 3)
2760 (plus:XF (mult:XF (match_dup 5) (match_dup 4))
2762 (use (const_int 1))]))
2763 (cond_exec (ne (match_dup 6) (const_int 0))
2764 (parallel [(set (match_dup 0)
2765 (plus:XF (mult:XF (match_dup 5) (match_dup 0))
2767 (use (const_int 1))]))
2768 (cond_exec (ne (match_dup 6) (const_int 0))
2769 (parallel [(set (match_dup 4)
2770 (minus:XF (match_dup 1)
2771 (mult:XF (match_dup 2) (match_dup 3))))
2772 (use (const_int 1))]))
2773 (cond_exec (ne (match_dup 6) (const_int 0))
2774 (parallel [(set (match_dup 0)
2775 (plus:XF (mult:XF (match_dup 4) (match_dup 0))
2777 (use (const_int 1))]))
2779 "operands[7] = CONST1_RTX (XFmode);"
2780 [(set_attr "predicable" "no")])
2782 (define_insn_and_split "divdi3_internal_thr"
2783 [(set (match_operand:XF 0 "fr_register_operand" "=&f")
2784 (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f")
2785 (match_operand:XF 2 "fr_register_operand" "f"))))
2786 (clobber (match_scratch:XF 3 "=&f"))
2787 (clobber (match_scratch:XF 4 "=f"))
2788 (clobber (match_scratch:BI 5 "=c"))]
2789 "TARGET_INLINE_INT_DIV_THR"
2791 "&& reload_completed"
2792 [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2)))
2793 (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)]
2794 UNSPEC_FR_RECIP_APPROX))
2795 (use (const_int 1))])
2796 (cond_exec (ne (match_dup 5) (const_int 0))
2797 (parallel [(set (match_dup 3)
2798 (minus:XF (match_dup 6)
2799 (mult:XF (match_dup 2) (match_dup 0))))
2800 (use (const_int 1))]))
2801 (cond_exec (ne (match_dup 5) (const_int 0))
2802 (parallel [(set (match_dup 0)
2803 (plus:XF (mult:XF (match_dup 3) (match_dup 0))
2805 (use (const_int 1))]))
2806 (cond_exec (ne (match_dup 5) (const_int 0))
2807 (parallel [(set (match_dup 3) (mult:XF (match_dup 3) (match_dup 3)))
2808 (use (const_int 1))]))
2809 (cond_exec (ne (match_dup 5) (const_int 0))
2810 (parallel [(set (match_dup 0)
2811 (plus:XF (mult:XF (match_dup 3) (match_dup 0))
2813 (use (const_int 1))]))
2814 (cond_exec (ne (match_dup 5) (const_int 0))
2815 (parallel [(set (match_dup 3) (mult:XF (match_dup 0) (match_dup 1)))
2816 (use (const_int 1))]))
2817 (cond_exec (ne (match_dup 5) (const_int 0))
2818 (parallel [(set (match_dup 4)
2819 (minus:XF (match_dup 1)
2820 (mult:XF (match_dup 2) (match_dup 3))))
2821 (use (const_int 1))]))
2822 (cond_exec (ne (match_dup 5) (const_int 0))
2823 (parallel [(set (match_dup 0)
2824 (plus:XF (mult:XF (match_dup 4) (match_dup 0))
2826 (use (const_int 1))]))
2828 "operands[6] = CONST1_RTX (XFmode);"
2829 [(set_attr "predicable" "no")])
2831 ;; ::::::::::::::::::::
2833 ;; :: 32 bit floating point arithmetic
2835 ;; ::::::::::::::::::::
2837 (define_insn "addsf3"
2838 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2839 (plus:SF (match_operand:SF 1 "fr_register_operand" "%f")
2840 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2842 "fadd.s %0 = %1, %F2"
2843 [(set_attr "itanium_class" "fmac")])
2845 (define_insn "subsf3"
2846 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2847 (minus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2848 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2850 "fsub.s %0 = %F1, %F2"
2851 [(set_attr "itanium_class" "fmac")])
2853 (define_insn "mulsf3"
2854 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2855 (mult:SF (match_operand:SF 1 "fr_register_operand" "%f")
2856 (match_operand:SF 2 "fr_register_operand" "f")))]
2858 "fmpy.s %0 = %1, %2"
2859 [(set_attr "itanium_class" "fmac")])
2861 (define_insn "abssf2"
2862 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2863 (abs:SF (match_operand:SF 1 "fr_register_operand" "f")))]
2866 [(set_attr "itanium_class" "fmisc")])
2868 (define_insn "negsf2"
2869 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2870 (neg:SF (match_operand:SF 1 "fr_register_operand" "f")))]
2873 [(set_attr "itanium_class" "fmisc")])
2875 (define_insn "*nabssf2"
2876 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2877 (neg:SF (abs:SF (match_operand:SF 1 "fr_register_operand" "f"))))]
2880 [(set_attr "itanium_class" "fmisc")])
2882 (define_insn "minsf3"
2883 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2884 (smin:SF (match_operand:SF 1 "fr_register_operand" "f")
2885 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2888 [(set_attr "itanium_class" "fmisc")])
2890 (define_insn "maxsf3"
2891 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2892 (smax:SF (match_operand:SF 1 "fr_register_operand" "f")
2893 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2896 [(set_attr "itanium_class" "fmisc")])
2898 (define_insn "*maddsf4"
2899 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2900 (plus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
2901 (match_operand:SF 2 "fr_register_operand" "f"))
2902 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
2904 "fma.s %0 = %1, %2, %F3"
2905 [(set_attr "itanium_class" "fmac")])
2907 (define_insn "*msubsf4"
2908 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2909 (minus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
2910 (match_operand:SF 2 "fr_register_operand" "f"))
2911 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
2913 "fms.s %0 = %1, %2, %F3"
2914 [(set_attr "itanium_class" "fmac")])
2916 (define_insn "*nmulsf3"
2917 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2918 (neg:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
2919 (match_operand:SF 2 "fr_register_operand" "f"))))]
2921 "fnmpy.s %0 = %1, %2"
2922 [(set_attr "itanium_class" "fmac")])
2924 (define_insn "*nmaddsf4"
2925 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2926 (minus:SF (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")
2927 (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
2928 (match_operand:SF 2 "fr_register_operand" "f"))))]
2930 "fnma.s %0 = %1, %2, %F3"
2931 [(set_attr "itanium_class" "fmac")])
2933 (define_insn "*nmaddsf4_alts"
2934 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2935 (minus:SF (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")
2936 (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
2937 (match_operand:SF 2 "fr_register_operand" "f"))))
2938 (use (match_operand:SI 4 "const_int_operand" ""))]
2940 "fnma.s.s%4 %0 = %1, %2, %F3"
2941 [(set_attr "itanium_class" "fmac")])
2943 (define_expand "divsf3"
2944 [(set (match_operand:SF 0 "fr_register_operand" "")
2945 (div:SF (match_operand:SF 1 "fr_register_operand" "")
2946 (match_operand:SF 2 "fr_register_operand" "")))]
2947 "TARGET_INLINE_FLOAT_DIV"
2950 if (TARGET_INLINE_FLOAT_DIV_LAT)
2951 insn = gen_divsf3_internal_lat (operands[0], operands[1], operands[2]);
2953 insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]);
2958 (define_insn_and_split "divsf3_internal_lat"
2959 [(set (match_operand:SF 0 "fr_register_operand" "=&f")
2960 (div:SF (match_operand:SF 1 "fr_register_operand" "f")
2961 (match_operand:SF 2 "fr_register_operand" "f")))
2962 (clobber (match_scratch:XF 3 "=&f"))
2963 (clobber (match_scratch:XF 4 "=f"))
2964 (clobber (match_scratch:BI 5 "=c"))]
2965 "TARGET_INLINE_FLOAT_DIV_LAT"
2967 "&& reload_completed"
2968 [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8)))
2969 (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
2970 UNSPEC_FR_RECIP_APPROX))
2971 (use (const_int 1))])
2972 (cond_exec (ne (match_dup 5) (const_int 0))
2973 (parallel [(set (match_dup 3) (mult:XF (match_dup 7) (match_dup 6)))
2974 (use (const_int 1))]))
2975 (cond_exec (ne (match_dup 5) (const_int 0))
2976 (parallel [(set (match_dup 4)
2977 (minus:XF (match_dup 10)
2978 (mult:XF (match_dup 8) (match_dup 6))))
2979 (use (const_int 1))]))
2980 (cond_exec (ne (match_dup 5) (const_int 0))
2981 (parallel [(set (match_dup 3)
2982 (plus:XF (mult:XF (match_dup 4) (match_dup 3))
2984 (use (const_int 1))]))
2985 (cond_exec (ne (match_dup 5) (const_int 0))
2986 (parallel [(set (match_dup 4) (mult:XF (match_dup 4) (match_dup 4)))
2987 (use (const_int 1))]))
2988 (cond_exec (ne (match_dup 5) (const_int 0))
2989 (parallel [(set (match_dup 3)
2990 (plus:XF (mult:XF (match_dup 4) (match_dup 3))
2992 (use (const_int 1))]))
2993 (cond_exec (ne (match_dup 5) (const_int 0))
2994 (parallel [(set (match_dup 4) (mult:XF (match_dup 4) (match_dup 4)))
2995 (use (const_int 1))]))
2996 (cond_exec (ne (match_dup 5) (const_int 0))
2997 (parallel [(set (match_dup 9)
2999 (plus:XF (mult:XF (match_dup 4) (match_dup 3))
3001 (use (const_int 1))]))
3002 (cond_exec (ne (match_dup 5) (const_int 0))
3004 (float_truncate:SF (match_dup 6))))
3007 operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0]));
3008 operands[7] = gen_rtx_REG (XFmode, REGNO (operands[1]));
3009 operands[8] = gen_rtx_REG (XFmode, REGNO (operands[2]));
3010 operands[9] = gen_rtx_REG (DFmode, REGNO (operands[0]));
3011 operands[10] = CONST1_RTX (XFmode);
3013 [(set_attr "predicable" "no")])
3015 (define_insn_and_split "divsf3_internal_thr"
3016 [(set (match_operand:SF 0 "fr_register_operand" "=&f")
3017 (div:SF (match_operand:SF 1 "fr_register_operand" "f")
3018 (match_operand:SF 2 "fr_register_operand" "f")))
3019 (clobber (match_scratch:XF 3 "=&f"))
3020 (clobber (match_scratch:XF 4 "=f"))
3021 (clobber (match_scratch:BI 5 "=c"))]
3022 "TARGET_INLINE_FLOAT_DIV_THR"
3024 "&& reload_completed"
3025 [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8)))
3026 (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
3027 UNSPEC_FR_RECIP_APPROX))
3028 (use (const_int 1))])
3029 (cond_exec (ne (match_dup 5) (const_int 0))
3030 (parallel [(set (match_dup 3)
3031 (minus:XF (match_dup 10)
3032 (mult:XF (match_dup 8) (match_dup 6))))
3033 (use (const_int 1))]))
3034 (cond_exec (ne (match_dup 5) (const_int 0))
3035 (parallel [(set (match_dup 3)
3036 (plus:XF (mult:XF (match_dup 3) (match_dup 3))
3038 (use (const_int 1))]))
3039 (cond_exec (ne (match_dup 5) (const_int 0))
3040 (parallel [(set (match_dup 6)
3041 (plus:XF (mult:XF (match_dup 3) (match_dup 6))
3043 (use (const_int 1))]))
3044 (cond_exec (ne (match_dup 5) (const_int 0))
3045 (parallel [(set (match_dup 9)
3047 (mult:XF (match_dup 7) (match_dup 6))))
3048 (use (const_int 1))]))
3049 (cond_exec (ne (match_dup 5) (const_int 0))
3050 (parallel [(set (match_dup 4)
3051 (minus:XF (match_dup 7)
3052 (mult:XF (match_dup 8) (match_dup 3))))
3053 (use (const_int 1))]))
3054 (cond_exec (ne (match_dup 5) (const_int 0))
3057 (plus:XF (mult:XF (match_dup 4) (match_dup 6))
3061 operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0]));
3062 operands[7] = gen_rtx_REG (XFmode, REGNO (operands[1]));
3063 operands[8] = gen_rtx_REG (XFmode, REGNO (operands[2]));
3064 operands[9] = gen_rtx_REG (SFmode, REGNO (operands[3]));
3065 operands[10] = CONST1_RTX (XFmode);
3067 [(set_attr "predicable" "no")])
3069 ;; Inline square root.
3071 (define_insn "*sqrt_approx"
3072 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3073 (div:XF (const_int 1)
3074 (sqrt:XF (match_operand:XF 2 "fr_register_operand" "f"))))
3075 (set (match_operand:BI 1 "register_operand" "=c")
3076 (unspec:BI [(match_dup 2)] UNSPEC_FR_SQRT_RECIP_APPROX))
3077 (use (match_operand:SI 3 "const_int_operand" "")) ]
3079 "frsqrta.s%3 %0, %1 = %2"
3080 [(set_attr "itanium_class" "fmisc")
3081 (set_attr "predicable" "no")])
3083 (define_insn "setf_exp_xf"
3084 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3085 (unspec:XF [(match_operand:DI 1 "register_operand" "r")]
3089 [(set_attr "itanium_class" "frfr")])
3091 (define_expand "sqrtsf2"
3092 [(set (match_operand:SF 0 "fr_register_operand" "=&f")
3093 (sqrt:SF (match_operand:SF 1 "fr_register_operand" "f")))]
3094 "TARGET_INLINE_SQRT"
3097 if (TARGET_INLINE_SQRT_LAT)
3099 insn = gen_sqrtsf2_internal_lat (operands[0], operands[1]);
3104 insn = gen_sqrtsf2_internal_thr (operands[0], operands[1]);
3109 ;; Latency-optimized square root.
3110 ;; FIXME: Implement.
3112 ;; Throughput-optimized square root.
3114 (define_insn_and_split "sqrtsf2_internal_thr"
3115 [(set (match_operand:SF 0 "fr_register_operand" "=&f")
3116 (sqrt:SF (match_operand:SF 1 "fr_register_operand" "f")))
3117 ;; Register r2 in optimization guide.
3118 (clobber (match_scratch:DI 2 "=r"))
3119 ;; Register f8 in optimization guide
3120 (clobber (match_scratch:XF 3 "=&f"))
3121 ;; Register f9 in optimization guide
3122 (clobber (match_scratch:XF 4 "=&f"))
3123 ;; Register f10 in optimization guide
3124 (clobber (match_scratch:XF 5 "=&f"))
3125 ;; Register p6 in optimization guide.
3126 (clobber (match_scratch:BI 6 "=c"))]
3127 "TARGET_INLINE_SQRT_THR"
3129 "&& reload_completed"
3130 [ ;; exponent of +1/2 in r2
3131 (set (match_dup 2) (const_int 65534))
3134 (unspec:XF [(match_dup 2)] UNSPEC_SETF_EXP))
3136 ;; y0 = 1/sqrt(a) in f7
3137 (parallel [(set (match_dup 7)
3138 (div:XF (const_int 1)
3139 (sqrt:XF (match_dup 8))))
3141 (unspec:BI [(match_dup 8)]
3142 UNSPEC_FR_SQRT_RECIP_APPROX))
3143 (use (const_int 0))])
3145 ;; H0 = 1/2 * y0 in f9
3146 (cond_exec (ne (match_dup 6) (const_int 0))
3147 (parallel [(set (match_dup 4)
3148 (plus:XF (mult:XF (match_dup 3) (match_dup 7))
3150 (use (const_int 1))]))
3152 ;; S0 = a * y0 in f7
3153 (cond_exec (ne (match_dup 6) (const_int 0))
3154 (parallel [(set (match_dup 7)
3155 (plus:XF (mult:XF (match_dup 8) (match_dup 7))
3157 (use (const_int 1))]))
3159 ;; d = 1/2 - S0 * H0 in f10
3160 (cond_exec (ne (match_dup 6) (const_int 0))
3161 (parallel [(set (match_dup 5)
3162 (minus:XF (match_dup 3)
3163 (mult:XF (match_dup 7) (match_dup 4))))
3164 (use (const_int 1))]))
3166 ;; d' = d + 1/2 * d in f8
3167 (cond_exec (ne (match_dup 6) (const_int 0))
3168 (parallel [(set (match_dup 3)
3169 (plus:XF (mult:XF (match_dup 3) (match_dup 5))
3171 (use (const_int 1))]))
3173 ;; e = d + d * d' in f8
3174 (cond_exec (ne (match_dup 6) (const_int 0))
3175 (parallel [(set (match_dup 3)
3176 (plus:XF (mult:XF (match_dup 5) (match_dup 3))
3178 (use (const_int 1))]))
3180 ;; S1 = S0 + e * S0 in f7
3181 (cond_exec (ne (match_dup 6) (const_int 0))
3182 (parallel [(set (match_dup 0)
3184 (plus:XF (mult:XF (match_dup 3) (match_dup 7))
3186 (use (const_int 1))]))
3188 ;; H1 = H0 + e * H0 in f8
3189 (cond_exec (ne (match_dup 6) (const_int 0))
3190 (parallel [(set (match_dup 3)
3191 (plus:XF (mult:XF (match_dup 3) (match_dup 4))
3193 (use (const_int 1))]))
3195 ;; d1 = a - S1 * S1 in f9
3196 (cond_exec (ne (match_dup 6) (const_int 0))
3197 (parallel [(set (match_dup 4)
3198 (minus:XF (match_dup 8)
3199 (mult:XF (match_dup 7) (match_dup 7))))
3200 (use (const_int 1))]))
3202 ;; S = S1 + d1 * H1 in f7
3203 (cond_exec (ne (match_dup 6) (const_int 0))
3204 (parallel [(set (match_dup 0)
3206 (plus:XF (mult:XF (match_dup 4) (match_dup 3))
3208 (use (const_int 0))]))]
3210 /* Generate 82-bit versions of the input and output operands. */
3211 operands[7] = gen_rtx_REG (XFmode, REGNO (operands[0]));
3212 operands[8] = gen_rtx_REG (XFmode, REGNO (operands[1]));
3213 /* Generate required floating-point constants. */
3214 operands[9] = CONST0_RTX (XFmode);
3216 [(set_attr "predicable" "no")])
3218 ;; ::::::::::::::::::::
3220 ;; :: 64 bit floating point arithmetic
3222 ;; ::::::::::::::::::::
3224 (define_insn "adddf3"
3225 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3226 (plus:DF (match_operand:DF 1 "fr_register_operand" "%f")
3227 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
3229 "fadd.d %0 = %1, %F2"
3230 [(set_attr "itanium_class" "fmac")])
3232 (define_insn "*adddf3_trunc"
3233 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3235 (plus:DF (match_operand:DF 1 "fr_register_operand" "%f")
3236 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
3238 "fadd.s %0 = %1, %F2"
3239 [(set_attr "itanium_class" "fmac")])
3241 (define_insn "subdf3"
3242 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3243 (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
3244 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
3246 "fsub.d %0 = %F1, %F2"
3247 [(set_attr "itanium_class" "fmac")])
3249 (define_insn "*subdf3_trunc"
3250 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3252 (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
3253 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
3255 "fsub.s %0 = %F1, %F2"
3256 [(set_attr "itanium_class" "fmac")])
3258 (define_insn "muldf3"
3259 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3260 (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3261 (match_operand:DF 2 "fr_register_operand" "f")))]
3263 "fmpy.d %0 = %1, %2"
3264 [(set_attr "itanium_class" "fmac")])
3266 (define_insn "*muldf3_trunc"
3267 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3269 (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3270 (match_operand:DF 2 "fr_register_operand" "f"))))]
3272 "fmpy.s %0 = %1, %2"
3273 [(set_attr "itanium_class" "fmac")])
3275 (define_insn "absdf2"
3276 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3277 (abs:DF (match_operand:DF 1 "fr_register_operand" "f")))]
3280 [(set_attr "itanium_class" "fmisc")])
3282 (define_insn "negdf2"
3283 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3284 (neg:DF (match_operand:DF 1 "fr_register_operand" "f")))]
3287 [(set_attr "itanium_class" "fmisc")])
3289 (define_insn "*nabsdf2"
3290 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3291 (neg:DF (abs:DF (match_operand:DF 1 "fr_register_operand" "f"))))]
3294 [(set_attr "itanium_class" "fmisc")])
3296 (define_insn "mindf3"
3297 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3298 (smin:DF (match_operand:DF 1 "fr_register_operand" "f")
3299 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
3302 [(set_attr "itanium_class" "fmisc")])
3304 (define_insn "maxdf3"
3305 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3306 (smax:DF (match_operand:DF 1 "fr_register_operand" "f")
3307 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
3310 [(set_attr "itanium_class" "fmisc")])
3312 (define_insn "*madddf4"
3313 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3314 (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3315 (match_operand:DF 2 "fr_register_operand" "f"))
3316 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
3318 "fma.d %0 = %1, %2, %F3"
3319 [(set_attr "itanium_class" "fmac")])
3321 (define_insn "*madddf4_trunc"
3322 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3324 (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3325 (match_operand:DF 2 "fr_register_operand" "f"))
3326 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
3328 "fma.s %0 = %1, %2, %F3"
3329 [(set_attr "itanium_class" "fmac")])
3331 (define_insn "*msubdf4"
3332 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3333 (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3334 (match_operand:DF 2 "fr_register_operand" "f"))
3335 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
3337 "fms.d %0 = %1, %2, %F3"
3338 [(set_attr "itanium_class" "fmac")])
3340 (define_insn "*msubdf4_trunc"
3341 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3343 (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3344 (match_operand:DF 2 "fr_register_operand" "f"))
3345 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
3347 "fms.s %0 = %1, %2, %F3"
3348 [(set_attr "itanium_class" "fmac")])
3350 (define_insn "*nmuldf3"
3351 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3352 (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3353 (match_operand:DF 2 "fr_register_operand" "f"))))]
3355 "fnmpy.d %0 = %1, %2"
3356 [(set_attr "itanium_class" "fmac")])
3358 (define_insn "*nmuldf3_trunc"
3359 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3361 (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3362 (match_operand:DF 2 "fr_register_operand" "f")))))]
3364 "fnmpy.s %0 = %1, %2"
3365 [(set_attr "itanium_class" "fmac")])
3367 (define_insn "*nmadddf4"
3368 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3369 (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")
3370 (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3371 (match_operand:DF 2 "fr_register_operand" "f"))))]
3373 "fnma.d %0 = %1, %2, %F3"
3374 [(set_attr "itanium_class" "fmac")])
3376 (define_insn "*nmadddf4_alts"
3377 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3378 (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")
3379 (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3380 (match_operand:DF 2 "fr_register_operand" "f"))))
3381 (use (match_operand:SI 4 "const_int_operand" ""))]
3383 "fnma.d.s%4 %0 = %1, %2, %F3"
3384 [(set_attr "itanium_class" "fmac")])
3386 (define_insn "*nmadddf4_truncsf"
3387 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3389 (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")
3390 (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3391 (match_operand:DF 2 "fr_register_operand" "f")))))]
3393 "fnma.s %0 = %1, %2, %F3"
3394 [(set_attr "itanium_class" "fmac")])
3396 (define_insn "*nmadddf4_truncsf_alts"
3397 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3399 (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")
3400 (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3401 (match_operand:DF 2 "fr_register_operand" "f")))))
3402 (use (match_operand:SI 4 "const_int_operand" ""))]
3404 "fnma.s.s%4 %0 = %1, %2, %F3"
3405 [(set_attr "itanium_class" "fmac")])
3407 (define_expand "divdf3"
3408 [(set (match_operand:DF 0 "fr_register_operand" "")
3409 (div:DF (match_operand:DF 1 "fr_register_operand" "")
3410 (match_operand:DF 2 "fr_register_operand" "")))]
3411 "TARGET_INLINE_FLOAT_DIV"
3414 if (TARGET_INLINE_FLOAT_DIV_LAT)
3415 insn = gen_divdf3_internal_lat (operands[0], operands[1], operands[2]);
3417 insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]);
3422 (define_insn_and_split "divdf3_internal_lat"
3423 [(set (match_operand:DF 0 "fr_register_operand" "=&f")
3424 (div:DF (match_operand:DF 1 "fr_register_operand" "f")
3425 (match_operand:DF 2 "fr_register_operand" "f")))
3426 (clobber (match_scratch:XF 3 "=&f"))
3427 (clobber (match_scratch:XF 4 "=&f"))
3428 (clobber (match_scratch:XF 5 "=&f"))
3429 (clobber (match_scratch:BI 6 "=c"))]
3430 "TARGET_INLINE_FLOAT_DIV_LAT"
3432 "&& reload_completed"
3433 [(parallel [(set (match_dup 7) (div:XF (const_int 1) (match_dup 9)))
3434 (set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)]
3435 UNSPEC_FR_RECIP_APPROX))
3436 (use (const_int 1))])
3437 (cond_exec (ne (match_dup 6) (const_int 0))
3438 (parallel [(set (match_dup 3) (mult:XF (match_dup 8) (match_dup 7)))
3439 (use (const_int 1))]))
3440 (cond_exec (ne (match_dup 6) (const_int 0))
3441 (parallel [(set (match_dup 4)
3442 (minus:XF (match_dup 12)
3443 (mult:XF (match_dup 9) (match_dup 7))))
3444 (use (const_int 1))]))
3445 (cond_exec (ne (match_dup 6) (const_int 0))
3446 (parallel [(set (match_dup 3)
3447 (plus:XF (mult:XF (match_dup 4) (match_dup 3))
3449 (use (const_int 1))]))
3450 (cond_exec (ne (match_dup 6) (const_int 0))
3451 (parallel [(set (match_dup 5) (mult:XF (match_dup 4) (match_dup 4)))
3452 (use (const_int 1))]))
3453 (cond_exec (ne (match_dup 6) (const_int 0))
3454 (parallel [(set (match_dup 7)
3455 (plus:XF (mult:XF (match_dup 4) (match_dup 7))
3457 (use (const_int 1))]))
3458 (cond_exec (ne (match_dup 6) (const_int 0))
3459 (parallel [(set (match_dup 3)
3460 (plus:XF (mult:XF (match_dup 5) (match_dup 3))
3462 (use (const_int 1))]))
3463 (cond_exec (ne (match_dup 6) (const_int 0))
3464 (parallel [(set (match_dup 4) (mult:XF (match_dup 5) (match_dup 5)))
3465 (use (const_int 1))]))
3466 (cond_exec (ne (match_dup 6) (const_int 0))
3467 (parallel [(set (match_dup 7)
3468 (plus:XF (mult:XF (match_dup 5) (match_dup 7))
3470 (use (const_int 1))]))
3471 (cond_exec (ne (match_dup 6) (const_int 0))
3472 (parallel [(set (match_dup 10)
3474 (plus:XF (mult:XF (match_dup 4) (match_dup 3))
3476 (use (const_int 1))]))
3477 (cond_exec (ne (match_dup 6) (const_int 0))
3478 (parallel [(set (match_dup 7)
3479 (plus:XF (mult:XF (match_dup 4) (match_dup 7))
3481 (use (const_int 1))]))
3482 (cond_exec (ne (match_dup 6) (const_int 0))
3483 (parallel [(set (match_dup 11)
3485 (minus:XF (match_dup 8)
3486 (mult:XF (match_dup 9) (match_dup 3)))))
3487 (use (const_int 1))]))
3488 (cond_exec (ne (match_dup 6) (const_int 0))
3490 (float_truncate:DF (plus:XF (mult:XF (match_dup 5) (match_dup 7))
3494 operands[7] = gen_rtx_REG (XFmode, REGNO (operands[0]));
3495 operands[8] = gen_rtx_REG (XFmode, REGNO (operands[1]));
3496 operands[9] = gen_rtx_REG (XFmode, REGNO (operands[2]));
3497 operands[10] = gen_rtx_REG (DFmode, REGNO (operands[3]));
3498 operands[11] = gen_rtx_REG (DFmode, REGNO (operands[5]));
3499 operands[12] = CONST1_RTX (XFmode);
3501 [(set_attr "predicable" "no")])
3503 (define_insn_and_split "divdf3_internal_thr"
3504 [(set (match_operand:DF 0 "fr_register_operand" "=&f")
3505 (div:DF (match_operand:DF 1 "fr_register_operand" "f")
3506 (match_operand:DF 2 "fr_register_operand" "f")))
3507 (clobber (match_scratch:XF 3 "=&f"))
3508 (clobber (match_scratch:DF 4 "=f"))
3509 (clobber (match_scratch:BI 5 "=c"))]
3510 "TARGET_INLINE_FLOAT_DIV_THR"
3512 "&& reload_completed"
3513 [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8)))
3514 (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
3515 UNSPEC_FR_RECIP_APPROX))
3516 (use (const_int 1))])
3517 (cond_exec (ne (match_dup 5) (const_int 0))
3518 (parallel [(set (match_dup 3)
3519 (minus:XF (match_dup 10)
3520 (mult:XF (match_dup 8) (match_dup 6))))
3521 (use (const_int 1))]))
3522 (cond_exec (ne (match_dup 5) (const_int 0))
3523 (parallel [(set (match_dup 6)
3524 (plus:XF (mult:XF (match_dup 3) (match_dup 6))
3526 (use (const_int 1))]))
3527 (cond_exec (ne (match_dup 5) (const_int 0))
3528 (parallel [(set (match_dup 3)
3529 (mult:XF (match_dup 3) (match_dup 3)))
3530 (use (const_int 1))]))
3531 (cond_exec (ne (match_dup 5) (const_int 0))
3532 (parallel [(set (match_dup 6)
3533 (plus:XF (mult:XF (match_dup 3) (match_dup 6))
3535 (use (const_int 1))]))
3536 (cond_exec (ne (match_dup 5) (const_int 0))
3537 (parallel [(set (match_dup 3)
3538 (mult:XF (match_dup 3) (match_dup 3)))
3539 (use (const_int 1))]))
3540 (cond_exec (ne (match_dup 5) (const_int 0))
3541 (parallel [(set (match_dup 6)
3542 (plus:XF (mult:XF (match_dup 3) (match_dup 6))
3544 (use (const_int 1))]))
3545 (cond_exec (ne (match_dup 5) (const_int 0))
3546 (parallel [(set (match_dup 9)
3548 (mult:XF (match_dup 7) (match_dup 6))))
3549 (use (const_int 1))]))
3550 (cond_exec (ne (match_dup 5) (const_int 0))
3551 (parallel [(set (match_dup 4)
3552 (minus:DF (match_dup 1)
3553 (mult:DF (match_dup 2) (match_dup 9))))
3554 (use (const_int 1))]))
3555 (cond_exec (ne (match_dup 5) (const_int 0))
3557 (plus:DF (mult:DF (match_dup 4) (match_dup 0))
3561 operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0]));
3562 operands[7] = gen_rtx_REG (XFmode, REGNO (operands[1]));
3563 operands[8] = gen_rtx_REG (XFmode, REGNO (operands[2]));
3564 operands[9] = gen_rtx_REG (DFmode, REGNO (operands[3]));
3565 operands[10] = CONST1_RTX (XFmode);
3567 [(set_attr "predicable" "no")])
3569 ;; Inline square root.
3571 (define_expand "sqrtdf2"
3572 [(set (match_operand:DF 0 "fr_register_operand" "=&f")
3573 (sqrt:DF (match_operand:DF 1 "fr_register_operand" "f")))]
3574 "TARGET_INLINE_SQRT"
3577 if (TARGET_INLINE_SQRT_LAT)
3579 insn = gen_sqrtdf2_internal_lat (operands[0], operands[1]);
3584 insn = gen_sqrtdf2_internal_thr (operands[0], operands[1]);
3589 ;; Latency-optimized square root.
3590 ;; FIXME: Implement.
3592 ;; Throughput-optimized square root.
3594 (define_insn_and_split "sqrtdf2_internal_thr"
3595 [(set (match_operand:DF 0 "fr_register_operand" "=&f")
3596 (sqrt:DF (match_operand:DF 1 "fr_register_operand" "f")))
3597 ;; Register r2 in optimization guide.
3598 (clobber (match_scratch:DI 2 "=r"))
3599 ;; Register f8 in optimization guide
3600 (clobber (match_scratch:XF 3 "=&f"))
3601 ;; Register f9 in optimization guide
3602 (clobber (match_scratch:XF 4 "=&f"))
3603 ;; Register f10 in optimization guide
3604 (clobber (match_scratch:XF 5 "=&f"))
3605 ;; Register p6 in optimization guide.
3606 (clobber (match_scratch:BI 6 "=c"))]
3607 "TARGET_INLINE_SQRT_THR"
3609 "&& reload_completed"
3610 [ ;; exponent of +1/2 in r2
3611 (set (match_dup 2) (const_int 65534))
3614 (unspec:XF [(match_dup 2)] UNSPEC_SETF_EXP))
3616 ;; y0 = 1/sqrt(a) in f7
3617 (parallel [(set (match_dup 7)
3618 (div:XF (const_int 1)
3619 (sqrt:XF (match_dup 8))))
3621 (unspec:BI [(match_dup 8)]
3622 UNSPEC_FR_SQRT_RECIP_APPROX))
3623 (use (const_int 0))])
3625 ;; H0 = 1/2 * y0 in f8
3626 (cond_exec (ne (match_dup 6) (const_int 0))
3627 (parallel [(set (match_dup 3)
3628 (plus:XF (mult:XF (match_dup 5) (match_dup 7))
3630 (use (const_int 1))]))
3632 ;; G0 = a * y0 in f7
3633 (cond_exec (ne (match_dup 6) (const_int 0))
3634 (parallel [(set (match_dup 7)
3635 (plus:XF (mult:XF (match_dup 8) (match_dup 7))
3637 (use (const_int 1))]))
3639 ;; r0 = 1/2 - G0 * H0 in f9
3640 (cond_exec (ne (match_dup 6) (const_int 0))
3641 (parallel [(set (match_dup 4)
3642 (minus:XF (match_dup 5)
3643 (mult:XF (match_dup 7) (match_dup 3))))
3644 (use (const_int 1))]))
3646 ;; H1 = H0 + r0 * H0 in f8
3647 (cond_exec (ne (match_dup 6) (const_int 0))
3648 (parallel [(set (match_dup 3)
3649 (plus:XF (mult:XF (match_dup 4) (match_dup 3))
3651 (use (const_int 1))]))
3653 ;; G1 = G0 + r0 * G0 in f7
3654 (cond_exec (ne (match_dup 6) (const_int 0))
3655 (parallel [(set (match_dup 7)
3656 (plus:XF (mult:XF (match_dup 4) (match_dup 7))
3658 (use (const_int 1))]))
3660 ;; r1 = 1/2 - G1 * H1 in f9
3661 (cond_exec (ne (match_dup 6) (const_int 0))
3662 (parallel [(set (match_dup 4)
3663 (minus:XF (match_dup 5)
3664 (mult:XF (match_dup 7) (match_dup 3))))
3665 (use (const_int 1))]))
3667 ;; H2 = H1 + r1 * H1 in f8
3668 (cond_exec (ne (match_dup 6) (const_int 0))
3669 (parallel [(set (match_dup 3)
3670 (plus:XF (mult:XF (match_dup 4) (match_dup 3))
3672 (use (const_int 1))]))
3674 ;; G2 = G1 + r1 * G1 in f7
3675 (cond_exec (ne (match_dup 6) (const_int 0))
3676 (parallel [(set (match_dup 7)
3677 (plus:XF (mult:XF (match_dup 4) (match_dup 7))
3679 (use (const_int 1))]))
3681 ;; d2 = a - G2 * G2 in f9
3682 (cond_exec (ne (match_dup 6) (const_int 0))
3683 (parallel [(set (match_dup 4)
3684 (minus:XF (match_dup 8)
3685 (mult:XF (match_dup 7) (match_dup 7))))
3686 (use (const_int 1))]))
3688 ;; G3 = G2 + d2 * H2 in f7
3689 (cond_exec (ne (match_dup 6) (const_int 0))
3690 (parallel [(set (match_dup 7)
3691 (plus:XF (mult:XF (match_dup 4) (match_dup 3))
3693 (use (const_int 1))]))
3695 ;; d3 = a - G3 * G3 in f9
3696 (cond_exec (ne (match_dup 6) (const_int 0))
3697 (parallel [(set (match_dup 4)
3698 (minus:XF (match_dup 8)
3699 (mult:XF (match_dup 7) (match_dup 7))))
3700 (use (const_int 1))]))
3702 ;; S = G3 + d3 * H2 in f7
3703 (cond_exec (ne (match_dup 6) (const_int 0))
3704 (parallel [(set (match_dup 0)
3706 (plus:XF (mult:XF (match_dup 4) (match_dup 3))
3708 (use (const_int 0))]))]
3710 /* Generate 82-bit versions of the input and output operands. */
3711 operands[7] = gen_rtx_REG (XFmode, REGNO (operands[0]));
3712 operands[8] = gen_rtx_REG (XFmode, REGNO (operands[1]));
3713 /* Generate required floating-point constants. */
3714 operands[9] = CONST0_RTX (XFmode);
3716 [(set_attr "predicable" "no")])
3718 ;; ::::::::::::::::::::
3720 ;; :: 80 bit floating point arithmetic
3722 ;; ::::::::::::::::::::
3724 (define_insn "addxf3"
3725 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3726 (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3727 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
3729 "fadd %0 = %F1, %F2"
3730 [(set_attr "itanium_class" "fmac")])
3732 (define_insn "*addxf3_truncsf"
3733 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3735 (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3736 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3738 "fadd.s %0 = %F1, %F2"
3739 [(set_attr "itanium_class" "fmac")])
3741 (define_insn "*addxf3_truncdf"
3742 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3744 (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3745 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3747 "fadd.d %0 = %F1, %F2"
3748 [(set_attr "itanium_class" "fmac")])
3750 (define_insn "subxf3"
3751 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3752 (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3753 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
3755 "fsub %0 = %F1, %F2"
3756 [(set_attr "itanium_class" "fmac")])
3758 (define_insn "*subxf3_truncsf"
3759 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3761 (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3762 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3764 "fsub.s %0 = %F1, %F2"
3765 [(set_attr "itanium_class" "fmac")])
3767 (define_insn "*subxf3_truncdf"
3768 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3770 (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3771 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3773 "fsub.d %0 = %F1, %F2"
3774 [(set_attr "itanium_class" "fmac")])
3776 (define_insn "mulxf3"
3777 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3778 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3779 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
3781 "fmpy %0 = %F1, %F2"
3782 [(set_attr "itanium_class" "fmac")])
3784 (define_insn "*mulxf3_truncsf"
3785 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3787 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3788 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3790 "fmpy.s %0 = %F1, %F2"
3791 [(set_attr "itanium_class" "fmac")])
3793 (define_insn "*mulxf3_truncdf"
3794 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3796 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3797 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3799 "fmpy.d %0 = %F1, %F2"
3800 [(set_attr "itanium_class" "fmac")])
3802 (define_insn "*mulxf3_alts"
3803 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3804 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3805 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))
3806 (use (match_operand:SI 3 "const_int_operand" ""))]
3808 "fmpy.s%3 %0 = %F1, %F2"
3809 [(set_attr "itanium_class" "fmac")])
3811 (define_insn "*mulxf3_truncsf_alts"
3812 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3814 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3815 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))
3816 (use (match_operand:SI 3 "const_int_operand" ""))]
3818 "fmpy.s.s%3 %0 = %F1, %F2"
3819 [(set_attr "itanium_class" "fmac")])
3821 (define_insn "*mulxf3_truncdf_alts"
3822 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3824 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3825 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))
3826 (use (match_operand:SI 3 "const_int_operand" ""))]
3828 "fmpy.d.s%3 %0 = %F1, %F2"
3829 [(set_attr "itanium_class" "fmac")])
3831 (define_insn "absxf2"
3832 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3833 (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))]
3836 [(set_attr "itanium_class" "fmisc")])
3838 (define_insn "negxf2"
3839 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3840 (neg:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))]
3843 [(set_attr "itanium_class" "fmisc")])
3845 (define_insn "*nabsxf2"
3846 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3847 (neg:XF (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG"))))]
3850 [(set_attr "itanium_class" "fmisc")])
3852 (define_insn "minxf3"
3853 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3854 (smin:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3855 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
3857 "fmin %0 = %F1, %F2"
3858 [(set_attr "itanium_class" "fmisc")])
3860 (define_insn "maxxf3"
3861 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3862 (smax:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3863 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
3865 "fmax %0 = %F1, %F2"
3866 [(set_attr "itanium_class" "fmisc")])
3868 (define_insn "*maddxf4"
3869 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3870 (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3871 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
3872 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))]
3874 "fma %0 = %F1, %F2, %F3"
3875 [(set_attr "itanium_class" "fmac")])
3877 (define_insn "*maddxf4_truncsf"
3878 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3880 (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3881 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
3882 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))]
3884 "fma.s %0 = %F1, %F2, %F3"
3885 [(set_attr "itanium_class" "fmac")])
3887 (define_insn "*maddxf4_truncdf"
3888 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3890 (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3891 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
3892 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))]
3894 "fma.d %0 = %F1, %F2, %F3"
3895 [(set_attr "itanium_class" "fmac")])
3897 (define_insn "*maddxf4_alts"
3898 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3899 (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3900 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
3901 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))
3902 (use (match_operand:SI 4 "const_int_operand" ""))]
3904 "fma.s%4 %0 = %F1, %F2, %F3"
3905 [(set_attr "itanium_class" "fmac")])
3907 (define_insn "*maddxf4_alts_truncsf"
3908 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3910 (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3911 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
3912 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))
3913 (use (match_operand:SI 4 "const_int_operand" ""))]
3915 "fma.s.s%4 %0 = %F1, %F2, %F3"
3916 [(set_attr "itanium_class" "fmac")])
3918 (define_insn "*maddxf4_alts_truncdf"
3919 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3921 (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3922 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
3923 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))
3924 (use (match_operand:SI 4 "const_int_operand" ""))]
3926 "fma.d.s%4 %0 = %F1, %F2, %F3"
3927 [(set_attr "itanium_class" "fmac")])
3929 (define_insn "*msubxf4"
3930 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3931 (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3932 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
3933 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))]
3935 "fms %0 = %F1, %F2, %F3"
3936 [(set_attr "itanium_class" "fmac")])
3938 (define_insn "*msubxf4_truncsf"
3939 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3941 (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3942 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
3943 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))]
3945 "fms.s %0 = %F1, %F2, %F3"
3946 [(set_attr "itanium_class" "fmac")])
3948 (define_insn "*msubxf4_truncdf"
3949 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3951 (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3952 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
3953 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))]
3955 "fms.d %0 = %F1, %F2, %F3"
3956 [(set_attr "itanium_class" "fmac")])
3958 (define_insn "*nmulxf3"
3959 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3960 (neg:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3961 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3963 "fnmpy %0 = %F1, %F2"
3964 [(set_attr "itanium_class" "fmac")])
3966 (define_insn "*nmulxf3_truncsf"
3967 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3970 (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3971 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))]
3973 "fnmpy.s %0 = %F1, %F2"
3974 [(set_attr "itanium_class" "fmac")])
3976 (define_insn "*nmulxf3_truncdf"
3977 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3980 (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3981 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))]
3983 "fnmpy.d %0 = %F1, %F2"
3984 [(set_attr "itanium_class" "fmac")])
3986 (define_insn "*nmaddxf4"
3987 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3988 (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")
3989 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3990 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
3993 "fnma %0 = %F1, %F2, %F3"
3994 [(set_attr "itanium_class" "fmac")])
3996 (define_insn "*nmaddxf4_truncsf"
3997 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3999 (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")
4000 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
4001 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
4004 "fnma.s %0 = %F1, %F2, %F3"
4005 [(set_attr "itanium_class" "fmac")])
4007 (define_insn "*nmaddxf4_truncdf"
4008 [(set (match_operand:DF 0 "fr_register_operand" "=f")
4010 (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")
4011 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
4012 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
4015 "fnma.d %0 = %F1, %F2, %F3"
4016 [(set_attr "itanium_class" "fmac")])
4018 (define_insn "*nmaddxf4_alts"
4019 [(set (match_operand:XF 0 "fr_register_operand" "=f")
4020 (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")
4021 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
4022 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
4024 (use (match_operand:SI 4 "const_int_operand" ""))]
4026 "fnma.s%4 %0 = %F1, %F2, %F3"
4027 [(set_attr "itanium_class" "fmac")])
4029 (define_insn "*nmaddxf4_truncsf_alts"
4030 [(set (match_operand:SF 0 "fr_register_operand" "=f")
4032 (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")
4033 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
4034 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
4036 (use (match_operand:SI 4 "const_int_operand" ""))]
4038 "fnma.s.s%4 %0 = %F1, %F2, %F3"
4039 [(set_attr "itanium_class" "fmac")])
4041 (define_insn "*nmaddxf4_truncdf_alts"
4042 [(set (match_operand:DF 0 "fr_register_operand" "=f")
4044 (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")
4045 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
4046 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
4048 (use (match_operand:SI 4 "const_int_operand" ""))]
4050 "fnma.d.s%4 %0 = %F1, %F2, %F3"
4051 [(set_attr "itanium_class" "fmac")])
4053 (define_expand "divxf3"
4054 [(set (match_operand:XF 0 "fr_register_operand" "")
4055 (div:XF (match_operand:XF 1 "fr_register_operand" "")
4056 (match_operand:XF 2 "fr_register_operand" "")))]
4057 "TARGET_INLINE_FLOAT_DIV"
4060 if (TARGET_INLINE_FLOAT_DIV_LAT)
4061 insn = gen_divxf3_internal_lat (operands[0], operands[1], operands[2]);
4063 insn = gen_divxf3_internal_thr (operands[0], operands[1], operands[2]);
4068 (define_insn_and_split "divxf3_internal_lat"
4069 [(set (match_operand:XF 0 "fr_register_operand" "=&f")
4070 (div:XF (match_operand:XF 1 "fr_register_operand" "f")
4071 (match_operand:XF 2 "fr_register_operand" "f")))
4072 (clobber (match_scratch:XF 3 "=&f"))
4073 (clobber (match_scratch:XF 4 "=&f"))
4074 (clobber (match_scratch:XF 5 "=&f"))
4075 (clobber (match_scratch:XF 6 "=&f"))
4076 (clobber (match_scratch:BI 7 "=c"))]
4077 "TARGET_INLINE_FLOAT_DIV_LAT"
4079 "&& reload_completed"
4080 [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2)))
4081 (set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)]
4082 UNSPEC_FR_RECIP_APPROX))
4083 (use (const_int 1))])
4084 (cond_exec (ne (match_dup 7) (const_int 0))
4085 (parallel [(set (match_dup 3)
4086 (minus:XF (match_dup 8)
4087 (mult:XF (match_dup 2) (match_dup 0))))
4088 (use (const_int 1))]))
4089 (cond_exec (ne (match_dup 7) (const_int 0))
4090 (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0)))
4091 (use (const_int 1))]))
4092 (cond_exec (ne (match_dup 7) (const_int 0))
4093 (parallel [(set (match_dup 5) (mult:XF (match_dup 3) (match_dup 3)))
4094 (use (const_int 1))]))
4095 (cond_exec (ne (match_dup 7) (const_int 0))
4096 (parallel [(set (match_dup 6)
4097 (plus:XF (mult:XF (match_dup 3) (match_dup 3))
4099 (use (const_int 1))]))
4100 (cond_exec (ne (match_dup 7) (const_int 0))
4101 (parallel [(set (match_dup 3)
4102 (plus:XF (mult:XF (match_dup 5) (match_dup 5))
4104 (use (const_int 1))]))
4105 (cond_exec (ne (match_dup 7) (const_int 0))
4106 (parallel [(set (match_dup 5)
4107 (plus:XF (mult:XF (match_dup 6) (match_dup 0))
4109 (use (const_int 1))]))
4110 (cond_exec (ne (match_dup 7) (const_int 0))
4111 (parallel [(set (match_dup 0)
4112 (plus:XF (mult:XF (match_dup 5) (match_dup 3))
4114 (use (const_int 1))]))
4115 (cond_exec (ne (match_dup 7) (const_int 0))
4116 (parallel [(set (match_dup 4)
4117 (minus:XF (match_dup 1)
4118 (mult:XF (match_dup 2) (match_dup 4))))
4119 (use (const_int 1))]))
4120 (cond_exec (ne (match_dup 7) (const_int 0))
4121 (parallel [(set (match_dup 3)
4122 (plus:XF (mult:XF (match_dup 3) (match_dup 0))
4124 (use (const_int 1))]))
4125 (cond_exec (ne (match_dup 7) (const_int 0))
4126 (parallel [(set (match_dup 5)
4127 (minus:XF (match_dup 8)
4128 (mult:XF (match_dup 2) (match_dup 0))))
4129 (use (const_int 1))]))
4130 (cond_exec (ne (match_dup 7) (const_int 0))
4131 (parallel [(set (match_dup 0)
4132 (plus:XF (mult:XF (match_dup 4) (match_dup 0))
4134 (use (const_int 1))]))
4135 (cond_exec (ne (match_dup 7) (const_int 0))
4136 (parallel [(set (match_dup 4)
4137 (minus:XF (match_dup 1)
4138 (mult:XF (match_dup 2) (match_dup 3))))
4139 (use (const_int 1))]))
4140 (cond_exec (ne (match_dup 7) (const_int 0))
4142 (plus:XF (mult:XF (match_dup 4) (match_dup 0))
4145 "operands[8] = CONST1_RTX (XFmode);"
4146 [(set_attr "predicable" "no")])
4148 (define_insn_and_split "divxf3_internal_thr"
4149 [(set (match_operand:XF 0 "fr_register_operand" "=&f")
4150 (div:XF (match_operand:XF 1 "fr_register_operand" "f")
4151 (match_operand:XF 2 "fr_register_operand" "f")))
4152 (clobber (match_scratch:XF 3 "=&f"))
4153 (clobber (match_scratch:XF 4 "=&f"))
4154 (clobber (match_scratch:BI 5 "=c"))]
4155 "TARGET_INLINE_FLOAT_DIV_THR"
4157 "&& reload_completed"
4158 [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2)))
4159 (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)]
4160 UNSPEC_FR_RECIP_APPROX))
4161 (use (const_int 1))])
4162 (cond_exec (ne (match_dup 5) (const_int 0))
4163 (parallel [(set (match_dup 3)
4164 (minus:XF (match_dup 6)
4165 (mult:XF (match_dup 2) (match_dup 0))))
4166 (use (const_int 1))]))
4167 (cond_exec (ne (match_dup 5) (const_int 0))
4168 (parallel [(set (match_dup 4)
4169 (plus:XF (mult:XF (match_dup 3) (match_dup 0))
4171 (use (const_int 1))]))
4172 (cond_exec (ne (match_dup 5) (const_int 0))
4173 (parallel [(set (match_dup 3) (mult:XF (match_dup 3) (match_dup 3)))
4174 (use (const_int 1))]))
4175 (cond_exec (ne (match_dup 5) (const_int 0))
4176 (parallel [(set (match_dup 3)
4177 (plus:XF (mult:XF (match_dup 3) (match_dup 4))
4179 (use (const_int 1))]))
4180 (cond_exec (ne (match_dup 5) (const_int 0))
4181 (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0)))
4182 (use (const_int 1))]))
4183 (cond_exec (ne (match_dup 5) (const_int 0))
4184 (parallel [(set (match_dup 0)
4185 (minus:XF (match_dup 6)
4186 (mult:XF (match_dup 2) (match_dup 3))))
4187 (use (const_int 1))]))
4188 (cond_exec (ne (match_dup 5) (const_int 0))
4189 (parallel [(set (match_dup 0)
4190 (plus:XF (mult:XF (match_dup 0) (match_dup 3))
4192 (use (const_int 1))]))
4193 (cond_exec (ne (match_dup 5) (const_int 0))
4194 (parallel [(set (match_dup 3)
4195 (minus:XF (match_dup 1)
4196 (mult:XF (match_dup 2) (match_dup 4))))
4197 (use (const_int 1))]))
4198 (cond_exec (ne (match_dup 5) (const_int 0))
4199 (parallel [(set (match_dup 3)
4200 (plus:XF (mult:XF (match_dup 3) (match_dup 0))
4202 (use (const_int 1))]))
4203 (cond_exec (ne (match_dup 5) (const_int 0))
4204 (parallel [(set (match_dup 4)
4205 (minus:XF (match_dup 6)
4206 (mult:XF (match_dup 2) (match_dup 0))))
4207 (use (const_int 1))]))
4208 (cond_exec (ne (match_dup 5) (const_int 0))
4209 (parallel [(set (match_dup 0)
4210 (plus:XF (mult:XF (match_dup 4) (match_dup 0))
4212 (use (const_int 1))]))
4213 (cond_exec (ne (match_dup 5) (const_int 0))
4214 (parallel [(set (match_dup 4)
4215 (minus:XF (match_dup 1)
4216 (mult:XF (match_dup 2) (match_dup 3))))
4217 (use (const_int 1))]))
4218 (cond_exec (ne (match_dup 5) (const_int 0))
4220 (plus:XF (mult:XF (match_dup 4) (match_dup 0))
4223 "operands[6] = CONST1_RTX (XFmode);"
4224 [(set_attr "predicable" "no")])
4226 ;; Inline square root.
4228 (define_expand "sqrtxf2"
4229 [(set (match_operand:XF 0 "fr_register_operand" "=&f")
4230 (sqrt:XF (match_operand:XF 1 "fr_register_operand" "f")))]
4231 "TARGET_INLINE_SQRT"
4234 if (TARGET_INLINE_SQRT_LAT)
4236 insn = gen_sqrtxf2_internal_lat (operands[0], operands[1]);
4241 insn = gen_sqrtxf2_internal_thr (operands[0], operands[1]);
4246 ;; Latency-optimized square root.
4247 ;; FIXME: Implement.
4249 ;; Throughput-optimized square root.
4251 (define_insn_and_split "sqrtxf2_internal_thr"
4252 [(set (match_operand:XF 0 "fr_register_operand" "=&f")
4253 (sqrt:XF (match_operand:XF 1 "fr_register_operand" "f")))
4254 ;; Register r2 in optimization guide.
4255 (clobber (match_scratch:DI 2 "=r"))
4256 ;; Register f8 in optimization guide
4257 (clobber (match_scratch:XF 3 "=&f"))
4258 ;; Register f9 in optimization guide
4259 (clobber (match_scratch:XF 4 "=&f"))
4260 ;; Register f10 in optimization guide
4261 (clobber (match_scratch:XF 5 "=&f"))
4262 ;; Register f11 in optimization guide
4263 (clobber (match_scratch:XF 6 "=&f"))
4264 ;; Register p6 in optimization guide.
4265 (clobber (match_scratch:BI 7 "=c"))]
4266 "TARGET_INLINE_SQRT_THR"
4268 "&& reload_completed"
4269 [ ;; exponent of +1/2 in r2
4270 (set (match_dup 2) (const_int 65534))
4271 ;; +1/2 in f8. The Intel manual mistakenly specifies f10.
4273 (unspec:XF [(match_dup 2)] UNSPEC_SETF_EXP))
4275 ;; y0 = 1/sqrt(a) in f7
4276 (parallel [(set (match_dup 8)
4277 (div:XF (const_int 1)
4278 (sqrt:XF (match_dup 9))))
4280 (unspec:BI [(match_dup 9)]
4281 UNSPEC_FR_SQRT_RECIP_APPROX))
4282 (use (const_int 0))])
4284 ;; H0 = 1/2 * y0 in f9
4285 (cond_exec (ne (match_dup 7) (const_int 0))
4286 (parallel [(set (match_dup 4)
4287 (plus:XF (mult:XF (match_dup 3) (match_dup 8))
4289 (use (const_int 1))]))
4291 ;; S0 = a * y0 in f7
4292 (cond_exec (ne (match_dup 7) (const_int 0))
4293 (parallel [(set (match_dup 8)
4294 (plus:XF (mult:XF (match_dup 9) (match_dup 8))
4296 (use (const_int 1))]))
4298 ;; d0 = 1/2 - S0 * H0 in f10
4299 (cond_exec (ne (match_dup 7) (const_int 0))
4300 (parallel [(set (match_dup 5)
4301 (minus:XF (match_dup 3)
4302 (mult:XF (match_dup 8) (match_dup 4))))
4303 (use (const_int 1))]))
4305 ;; H1 = H0 + d0 * H0 in f9
4306 (cond_exec (ne (match_dup 7) (const_int 0))
4307 (parallel [(set (match_dup 4)
4308 (plus:XF (mult:XF (match_dup 5) (match_dup 4))
4310 (use (const_int 1))]))
4312 ;; S1 = S0 + d0 * S0 in f7
4313 (cond_exec (ne (match_dup 7) (const_int 0))
4314 (parallel [(set (match_dup 8)
4315 (plus:XF (mult:XF (match_dup 5) (match_dup 8))
4317 (use (const_int 1))]))
4319 ;; d1 = 1/2 - S1 * H1 in f10
4320 (cond_exec (ne (match_dup 7) (const_int 0))
4321 (parallel [(set (match_dup 5)
4322 (minus:XF (match_dup 3)
4323 (mult:XF (match_dup 8) (match_dup 4))))
4324 (use (const_int 1))]))
4326 ;; H2 = H1 + d1 * H1 in f9
4327 (cond_exec (ne (match_dup 7) (const_int 0))
4328 (parallel [(set (match_dup 4)
4329 (plus:XF (mult:XF (match_dup 5) (match_dup 4))
4331 (use (const_int 1))]))
4333 ;; S2 = S1 + d1 * S1 in f7
4334 (cond_exec (ne (match_dup 7) (const_int 0))
4335 (parallel [(set (match_dup 8)
4336 (plus:XF (mult:XF (match_dup 5) (match_dup 8))
4338 (use (const_int 1))]))
4340 ;; d2 = 1/2 - S2 * H2 in f10
4341 (cond_exec (ne (match_dup 7) (const_int 0))
4342 (parallel [(set (match_dup 5)
4343 (minus:XF (match_dup 3)
4344 (mult:XF (match_dup 8) (match_dup 4))))
4345 (use (const_int 1))]))
4347 ;; e2 = a - S2 * S2 in f8
4348 (cond_exec (ne (match_dup 7) (const_int 0))
4349 (parallel [(set (match_dup 3)
4350 (minus:XF (match_dup 9)
4351 (mult:XF (match_dup 8) (match_dup 8))))
4352 (use (const_int 1))]))
4354 ;; S3 = S2 + e2 * H2 in f7
4355 (cond_exec (ne (match_dup 7) (const_int 0))
4356 (parallel [(set (match_dup 8)
4357 (plus:XF (mult:XF (match_dup 3) (match_dup 4))
4359 (use (const_int 1))]))
4361 ;; H3 = H2 + d2 * H2 in f9
4362 (cond_exec (ne (match_dup 7) (const_int 0))
4363 (parallel [(set (match_dup 4)
4364 (plus:XF (mult:XF (match_dup 5) (match_dup 4))
4366 (use (const_int 1))]))
4368 ;; e3 = a - S3 * S3 in f8
4369 (cond_exec (ne (match_dup 7) (const_int 0))
4370 (parallel [(set (match_dup 3)
4371 (minus:XF (match_dup 9)
4372 (mult:XF (match_dup 8) (match_dup 8))))
4373 (use (const_int 1))]))
4375 ;; S = S3 + e3 * H3 in f7
4376 (cond_exec (ne (match_dup 7) (const_int 0))
4377 (parallel [(set (match_dup 0)
4378 (plus:XF (mult:XF (match_dup 3) (match_dup 4))
4380 (use (const_int 0))]))]
4382 /* Generate 82-bit versions of the input and output operands. */
4383 operands[8] = gen_rtx_REG (XFmode, REGNO (operands[0]));
4384 operands[9] = gen_rtx_REG (XFmode, REGNO (operands[1]));
4385 /* Generate required floating-point constants. */
4386 operands[10] = CONST0_RTX (XFmode);
4388 [(set_attr "predicable" "no")])
4390 ;; ??? frcpa works like cmp.foo.unc.
4392 (define_insn "*recip_approx"
4393 [(set (match_operand:XF 0 "fr_register_operand" "=f")
4394 (div:XF (const_int 1)
4395 (match_operand:XF 3 "fr_register_operand" "f")))
4396 (set (match_operand:BI 1 "register_operand" "=c")
4397 (unspec:BI [(match_operand:XF 2 "fr_register_operand" "f")
4398 (match_dup 3)] UNSPEC_FR_RECIP_APPROX))
4399 (use (match_operand:SI 4 "const_int_operand" ""))]
4401 "frcpa.s%4 %0, %1 = %2, %3"
4402 [(set_attr "itanium_class" "fmisc")
4403 (set_attr "predicable" "no")])
4405 ;; ::::::::::::::::::::
4407 ;; :: 32 bit Integer Shifts and Rotates
4409 ;; ::::::::::::::::::::
4411 (define_expand "ashlsi3"
4412 [(set (match_operand:SI 0 "gr_register_operand" "")
4413 (ashift:SI (match_operand:SI 1 "gr_register_operand" "")
4414 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
4417 if (GET_CODE (operands[2]) != CONST_INT)
4419 /* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED? Now
4420 we've got to get rid of stray bits outside the SImode register. */
4421 rtx subshift = gen_reg_rtx (DImode);
4422 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
4423 operands[2] = subshift;
4427 (define_insn "*ashlsi3_internal"
4428 [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r")
4429 (ashift:SI (match_operand:SI 1 "gr_register_operand" "r,r,r")
4430 (match_operand:DI 2 "gr_reg_or_5bit_operand" "R,n,r")))]
4433 shladd %0 = %1, %2, r0
4434 dep.z %0 = %1, %2, %E2
4436 [(set_attr "itanium_class" "ialu,ishf,mmshf")])
4438 (define_expand "ashrsi3"
4439 [(set (match_operand:SI 0 "gr_register_operand" "")
4440 (ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
4441 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
4444 rtx subtarget = gen_reg_rtx (DImode);
4445 if (GET_CODE (operands[2]) == CONST_INT)
4446 emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]),
4447 GEN_INT (32 - INTVAL (operands[2])), operands[2]));
4450 rtx subshift = gen_reg_rtx (DImode);
4451 emit_insn (gen_extendsidi2 (subtarget, operands[1]));
4452 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
4453 emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift));
4455 emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
4459 (define_expand "lshrsi3"
4460 [(set (match_operand:SI 0 "gr_register_operand" "")
4461 (lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
4462 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
4465 rtx subtarget = gen_reg_rtx (DImode);
4466 if (GET_CODE (operands[2]) == CONST_INT)
4467 emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]),
4468 GEN_INT (32 - INTVAL (operands[2])), operands[2]));
4471 rtx subshift = gen_reg_rtx (DImode);
4472 emit_insn (gen_zero_extendsidi2 (subtarget, operands[1]));
4473 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
4474 emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift));
4476 emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
4480 ;; Use mix4.r/shr to implement rotrsi3. We only get 32 bits of valid result
4481 ;; here, instead of 64 like the patterns above. Keep the pattern together
4482 ;; until after combine; otherwise it won't get matched often.
4484 (define_expand "rotrsi3"
4485 [(set (match_operand:SI 0 "gr_register_operand" "")
4486 (rotatert:SI (match_operand:SI 1 "gr_register_operand" "")
4487 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
4490 if (GET_MODE (operands[2]) != VOIDmode)
4492 rtx tmp = gen_reg_rtx (DImode);
4493 emit_insn (gen_zero_extendsidi2 (tmp, operands[2]));
4498 (define_insn_and_split "*rotrsi3_internal"
4499 [(set (match_operand:SI 0 "gr_register_operand" "=&r")
4500 (rotatert:SI (match_operand:SI 1 "gr_register_operand" "r")
4501 (match_operand:DI 2 "gr_reg_or_5bit_operand" "rM")))]
4506 (ior:DI (zero_extend:DI (match_dup 1))
4507 (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
4509 (lshiftrt:DI (match_dup 3) (match_dup 2)))]
4510 "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));")
4512 (define_expand "rotlsi3"
4513 [(set (match_operand:SI 0 "gr_register_operand" "")
4514 (rotate:SI (match_operand:SI 1 "gr_register_operand" "")
4515 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
4518 if (! shift_32bit_count_operand (operands[2], SImode))
4520 rtx tmp = gen_reg_rtx (SImode);
4521 emit_insn (gen_subsi3 (tmp, GEN_INT (32), operands[2]));
4522 emit_insn (gen_rotrsi3 (operands[0], operands[1], tmp));
4527 (define_insn_and_split "*rotlsi3_internal"
4528 [(set (match_operand:SI 0 "gr_register_operand" "=r")
4529 (rotate:SI (match_operand:SI 1 "gr_register_operand" "r")
4530 (match_operand:SI 2 "shift_32bit_count_operand" "n")))]
4535 (ior:DI (zero_extend:DI (match_dup 1))
4536 (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
4538 (lshiftrt:DI (match_dup 3) (match_dup 2)))]
4540 operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));
4541 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
4544 ;; ::::::::::::::::::::
4546 ;; :: 64 bit Integer Shifts and Rotates
4548 ;; ::::::::::::::::::::
4550 (define_insn "ashldi3"
4551 [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r")
4552 (ashift:DI (match_operand:DI 1 "gr_register_operand" "r,r,r")
4553 (match_operand:DI 2 "gr_reg_or_6bit_operand" "R,r,rM")))]
4556 shladd %0 = %1, %2, r0
4559 [(set_attr "itanium_class" "ialu,mmshf,mmshfi")])
4561 ;; ??? Maybe combine this with the multiply and add instruction?
4563 (define_insn "*shladd"
4564 [(set (match_operand:DI 0 "gr_register_operand" "=r")
4565 (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
4566 (match_operand:DI 2 "shladd_operand" "n"))
4567 (match_operand:DI 3 "gr_register_operand" "r")))]
4569 "shladd %0 = %1, %S2, %3"
4570 [(set_attr "itanium_class" "ialu")])
4572 ;; This can be created by register elimination if operand3 of shladd is an
4573 ;; eliminable register or has reg_equiv_constant set.
4575 ;; We have to use nonmemory_operand for operand 4, to ensure that the
4576 ;; validate_changes call inside eliminate_regs will always succeed. If it
4577 ;; doesn't succeed, then this remain a shladd pattern, and will be reloaded
4580 (define_insn_and_split "*shladd_elim"
4581 [(set (match_operand:DI 0 "gr_register_operand" "=&r")
4582 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
4583 (match_operand:DI 2 "shladd_operand" "n"))
4584 (match_operand:DI 3 "nonmemory_operand" "r"))
4585 (match_operand:DI 4 "nonmemory_operand" "rI")))]
4586 "reload_in_progress"
4589 [(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (match_dup 2))
4591 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
4593 [(set_attr "itanium_class" "unknown")])
4595 (define_insn "ashrdi3"
4596 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
4597 (ashiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r")
4598 (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))]
4603 [(set_attr "itanium_class" "mmshf,mmshfi")])
4605 (define_insn "lshrdi3"
4606 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
4607 (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r")
4608 (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))]
4613 [(set_attr "itanium_class" "mmshf,mmshfi")])
4615 ;; Using a predicate that accepts only constants doesn't work, because optabs
4616 ;; will load the operand into a register and call the pattern if the predicate
4617 ;; did not accept it on the first try. So we use nonmemory_operand and then
4618 ;; verify that we have an appropriate constant in the expander.
4620 (define_expand "rotrdi3"
4621 [(set (match_operand:DI 0 "gr_register_operand" "")
4622 (rotatert:DI (match_operand:DI 1 "gr_register_operand" "")
4623 (match_operand:DI 2 "nonmemory_operand" "")))]
4626 if (! shift_count_operand (operands[2], DImode))
4630 (define_insn "*rotrdi3_internal"
4631 [(set (match_operand:DI 0 "gr_register_operand" "=r")
4632 (rotatert:DI (match_operand:DI 1 "gr_register_operand" "r")
4633 (match_operand:DI 2 "shift_count_operand" "M")))]
4635 "shrp %0 = %1, %1, %2"
4636 [(set_attr "itanium_class" "ishf")])
4638 (define_expand "rotldi3"
4639 [(set (match_operand:DI 0 "gr_register_operand" "")
4640 (rotate:DI (match_operand:DI 1 "gr_register_operand" "")
4641 (match_operand:DI 2 "nonmemory_operand" "")))]
4644 if (! shift_count_operand (operands[2], DImode))
4648 (define_insn "*rotldi3_internal"
4649 [(set (match_operand:DI 0 "gr_register_operand" "=r")
4650 (rotate:DI (match_operand:DI 1 "gr_register_operand" "r")
4651 (match_operand:DI 2 "shift_count_operand" "M")))]
4653 "shrp %0 = %1, %1, %e2"
4654 [(set_attr "itanium_class" "ishf")])
4656 ;; ::::::::::::::::::::
4658 ;; :: 32 bit Integer Logical operations
4660 ;; ::::::::::::::::::::
4662 ;; We don't seem to need any other 32-bit logical operations, because gcc
4663 ;; generates zero-extend;zero-extend;DImode-op, which combine optimizes to
4664 ;; DImode-op;zero-extend, and then we can optimize away the zero-extend.
4665 ;; This doesn't work for unary logical operations, because we don't call
4666 ;; apply_distributive_law for them.
4668 ;; ??? Likewise, this doesn't work for andnot, which isn't handled by
4669 ;; apply_distributive_law. We get inefficient code for
4670 ;; int sub4 (int i, int j) { return i & ~j; }
4671 ;; We could convert (and (not (sign_extend A)) (sign_extend B)) to
4672 ;; (zero_extend (and (not A) B)) in combine.
4673 ;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the
4674 ;; one_cmplsi2 pattern.
4676 (define_insn "one_cmplsi2"
4677 [(set (match_operand:SI 0 "gr_register_operand" "=r")
4678 (not:SI (match_operand:SI 1 "gr_register_operand" "r")))]
4681 [(set_attr "itanium_class" "ilog")])
4683 ;; ::::::::::::::::::::
4685 ;; :: 64 bit Integer Logical operations
4687 ;; ::::::::::::::::::::
4689 (define_insn "anddi3"
4690 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
4691 (and:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
4692 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
4697 [(set_attr "itanium_class" "ilog,fmisc")])
4699 (define_insn "*andnot"
4700 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
4701 (and:DI (not:DI (match_operand:DI 1 "grfr_register_operand" "r,*f"))
4702 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
4707 [(set_attr "itanium_class" "ilog,fmisc")])
4709 (define_insn "iordi3"
4710 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
4711 (ior:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
4712 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
4717 [(set_attr "itanium_class" "ilog,fmisc")])
4719 (define_insn "xordi3"
4720 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
4721 (xor:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
4722 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
4727 [(set_attr "itanium_class" "ilog,fmisc")])
4729 (define_insn "one_cmpldi2"
4730 [(set (match_operand:DI 0 "gr_register_operand" "=r")
4731 (not:DI (match_operand:DI 1 "gr_register_operand" "r")))]
4734 [(set_attr "itanium_class" "ilog")])
4736 ;; ::::::::::::::::::::
4740 ;; ::::::::::::::::::::
4742 (define_expand "cmpbi"
4744 (compare (match_operand:BI 0 "register_operand" "")
4745 (match_operand:BI 1 "const_int_operand" "")))]
4748 ia64_compare_op0 = operands[0];
4749 ia64_compare_op1 = operands[1];
4753 (define_expand "cmpsi"
4755 (compare (match_operand:SI 0 "gr_register_operand" "")
4756 (match_operand:SI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))]
4759 ia64_compare_op0 = operands[0];
4760 ia64_compare_op1 = operands[1];
4764 (define_expand "cmpdi"
4766 (compare (match_operand:DI 0 "gr_register_operand" "")
4767 (match_operand:DI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))]
4770 ia64_compare_op0 = operands[0];
4771 ia64_compare_op1 = operands[1];
4775 (define_expand "cmpsf"
4777 (compare (match_operand:SF 0 "fr_reg_or_fp01_operand" "")
4778 (match_operand:SF 1 "fr_reg_or_fp01_operand" "")))]
4781 ia64_compare_op0 = operands[0];
4782 ia64_compare_op1 = operands[1];
4786 (define_expand "cmpdf"
4788 (compare (match_operand:DF 0 "fr_reg_or_fp01_operand" "")
4789 (match_operand:DF 1 "fr_reg_or_fp01_operand" "")))]
4792 ia64_compare_op0 = operands[0];
4793 ia64_compare_op1 = operands[1];
4797 (define_expand "cmpxf"
4799 (compare (match_operand:XF 0 "xfreg_or_fp01_operand" "")
4800 (match_operand:XF 1 "xfreg_or_fp01_operand" "")))]
4803 ia64_compare_op0 = operands[0];
4804 ia64_compare_op1 = operands[1];
4808 (define_expand "cmptf"
4810 (compare (match_operand:TF 0 "gr_register_operand" "")
4811 (match_operand:TF 1 "gr_register_operand" "")))]
4814 ia64_compare_op0 = operands[0];
4815 ia64_compare_op1 = operands[1];
4819 (define_insn "*cmpsi_normal"
4820 [(set (match_operand:BI 0 "register_operand" "=c")
4821 (match_operator:BI 1 "normal_comparison_operator"
4822 [(match_operand:SI 2 "gr_register_operand" "r")
4823 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))]
4825 "cmp4.%C1 %0, %I0 = %3, %2"
4826 [(set_attr "itanium_class" "icmp")])
4828 ;; We use %r3 because it is possible for us to match a 0, and two of the
4829 ;; unsigned comparisons don't accept immediate operands of zero.
4831 (define_insn "*cmpsi_adjusted"
4832 [(set (match_operand:BI 0 "register_operand" "=c")
4833 (match_operator:BI 1 "adjusted_comparison_operator"
4834 [(match_operand:SI 2 "gr_register_operand" "r")
4835 (match_operand:SI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
4837 "cmp4.%C1 %0, %I0 = %r3, %2"
4838 [(set_attr "itanium_class" "icmp")])
4840 (define_insn "*cmpdi_normal"
4841 [(set (match_operand:BI 0 "register_operand" "=c")
4842 (match_operator:BI 1 "normal_comparison_operator"
4843 [(match_operand:DI 2 "gr_reg_or_0_operand" "rO")
4844 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))]
4846 "cmp.%C1 %0, %I0 = %3, %r2"
4847 [(set_attr "itanium_class" "icmp")])
4849 ;; We use %r3 because it is possible for us to match a 0, and two of the
4850 ;; unsigned comparisons don't accept immediate operands of zero.
4852 (define_insn "*cmpdi_adjusted"
4853 [(set (match_operand:BI 0 "register_operand" "=c")
4854 (match_operator:BI 1 "adjusted_comparison_operator"
4855 [(match_operand:DI 2 "gr_register_operand" "r")
4856 (match_operand:DI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
4858 "cmp.%C1 %0, %I0 = %r3, %2"
4859 [(set_attr "itanium_class" "icmp")])
4861 (define_insn "*cmpsf_internal"
4862 [(set (match_operand:BI 0 "register_operand" "=c")
4863 (match_operator:BI 1 "comparison_operator"
4864 [(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")
4865 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")]))]
4867 "fcmp.%D1 %0, %I0 = %F2, %F3"
4868 [(set_attr "itanium_class" "fcmp")])
4870 (define_insn "*cmpdf_internal"
4871 [(set (match_operand:BI 0 "register_operand" "=c")
4872 (match_operator:BI 1 "comparison_operator"
4873 [(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")
4874 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")]))]
4876 "fcmp.%D1 %0, %I0 = %F2, %F3"
4877 [(set_attr "itanium_class" "fcmp")])
4879 (define_insn "*cmpxf_internal"
4880 [(set (match_operand:BI 0 "register_operand" "=c")
4881 (match_operator:BI 1 "comparison_operator"
4882 [(match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
4883 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")]))]
4885 "fcmp.%D1 %0, %I0 = %F2, %F3"
4886 [(set_attr "itanium_class" "fcmp")])
4888 ;; ??? Can this pattern be generated?
4890 (define_insn "*bit_zero"
4891 [(set (match_operand:BI 0 "register_operand" "=c")
4892 (eq:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
4894 (match_operand:DI 2 "immediate_operand" "n"))
4897 "tbit.z %0, %I0 = %1, %2"
4898 [(set_attr "itanium_class" "tbit")])
4900 (define_insn "*bit_one"
4901 [(set (match_operand:BI 0 "register_operand" "=c")
4902 (ne:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
4904 (match_operand:DI 2 "immediate_operand" "n"))
4907 "tbit.nz %0, %I0 = %1, %2"
4908 [(set_attr "itanium_class" "tbit")])
4910 ;; ::::::::::::::::::::
4914 ;; ::::::::::::::::::::
4916 (define_expand "beq"
4918 (if_then_else (match_dup 1)
4919 (label_ref (match_operand 0 "" ""))
4922 "operands[1] = ia64_expand_compare (EQ, VOIDmode);")
4924 (define_expand "bne"
4926 (if_then_else (match_dup 1)
4927 (label_ref (match_operand 0 "" ""))
4930 "operands[1] = ia64_expand_compare (NE, VOIDmode);")
4932 (define_expand "blt"
4934 (if_then_else (match_dup 1)
4935 (label_ref (match_operand 0 "" ""))
4938 "operands[1] = ia64_expand_compare (LT, VOIDmode);")
4940 (define_expand "ble"
4942 (if_then_else (match_dup 1)
4943 (label_ref (match_operand 0 "" ""))
4946 "operands[1] = ia64_expand_compare (LE, VOIDmode);")
4948 (define_expand "bgt"
4950 (if_then_else (match_dup 1)
4951 (label_ref (match_operand 0 "" ""))
4954 "operands[1] = ia64_expand_compare (GT, VOIDmode);")
4956 (define_expand "bge"
4958 (if_then_else (match_dup 1)
4959 (label_ref (match_operand 0 "" ""))
4962 "operands[1] = ia64_expand_compare (GE, VOIDmode);")
4964 (define_expand "bltu"
4966 (if_then_else (match_dup 1)
4967 (label_ref (match_operand 0 "" ""))
4970 "operands[1] = ia64_expand_compare (LTU, VOIDmode);")
4972 (define_expand "bleu"
4974 (if_then_else (match_dup 1)
4975 (label_ref (match_operand 0 "" ""))
4978 "operands[1] = ia64_expand_compare (LEU, VOIDmode);")
4980 (define_expand "bgtu"
4982 (if_then_else (match_dup 1)
4983 (label_ref (match_operand 0 "" ""))
4986 "operands[1] = ia64_expand_compare (GTU, VOIDmode);")
4988 (define_expand "bgeu"
4990 (if_then_else (match_dup 1)
4991 (label_ref (match_operand 0 "" ""))
4994 "operands[1] = ia64_expand_compare (GEU, VOIDmode);")
4996 (define_expand "bunordered"
4998 (if_then_else (match_dup 1)
4999 (label_ref (match_operand 0 "" ""))
5002 "operands[1] = ia64_expand_compare (UNORDERED, VOIDmode);")
5004 (define_expand "bordered"
5006 (if_then_else (match_dup 1)
5007 (label_ref (match_operand 0 "" ""))
5010 "operands[1] = ia64_expand_compare (ORDERED, VOIDmode);")
5012 (define_insn "*br_true"
5014 (if_then_else (match_operator 0 "predicate_operator"
5015 [(match_operand:BI 1 "register_operand" "c")
5017 (label_ref (match_operand 2 "" ""))
5020 "(%J0) br.cond%+ %l2"
5021 [(set_attr "itanium_class" "br")
5022 (set_attr "predicable" "no")])
5024 (define_insn "*br_false"
5026 (if_then_else (match_operator 0 "predicate_operator"
5027 [(match_operand:BI 1 "register_operand" "c")
5030 (label_ref (match_operand 2 "" ""))))]
5032 "(%j0) br.cond%+ %l2"
5033 [(set_attr "itanium_class" "br")
5034 (set_attr "predicable" "no")])
5036 ;; ::::::::::::::::::::
5038 ;; :: Counted loop operations
5040 ;; ::::::::::::::::::::
5042 (define_expand "doloop_end"
5043 [(use (match_operand 0 "" "")) ; loop pseudo
5044 (use (match_operand 1 "" "")) ; iterations; zero if unknown
5045 (use (match_operand 2 "" "")) ; max iterations
5046 (use (match_operand 3 "" "")) ; loop level
5047 (use (match_operand 4 "" ""))] ; label
5050 /* Only use cloop on innermost loops. */
5051 if (INTVAL (operands[3]) > 1)
5053 emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM),
5058 (define_insn "doloop_end_internal"
5059 [(set (pc) (if_then_else (ne (match_operand:DI 0 "ar_lc_reg_operand" "")
5061 (label_ref (match_operand 1 "" ""))
5063 (set (match_dup 0) (if_then_else:DI (ne (match_dup 0) (const_int 0))
5064 (plus:DI (match_dup 0) (const_int -1))
5067 "br.cloop.sptk.few %l1"
5068 [(set_attr "itanium_class" "br")
5069 (set_attr "predicable" "no")])
5071 ;; ::::::::::::::::::::
5073 ;; :: Set flag operations
5075 ;; ::::::::::::::::::::
5077 (define_expand "seq"
5078 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5080 "operands[1] = ia64_expand_compare (EQ, DImode);")
5082 (define_expand "sne"
5083 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5085 "operands[1] = ia64_expand_compare (NE, DImode);")
5087 (define_expand "slt"
5088 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5090 "operands[1] = ia64_expand_compare (LT, DImode);")
5092 (define_expand "sle"
5093 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5095 "operands[1] = ia64_expand_compare (LE, DImode);")
5097 (define_expand "sgt"
5098 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5100 "operands[1] = ia64_expand_compare (GT, DImode);")
5102 (define_expand "sge"
5103 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5105 "operands[1] = ia64_expand_compare (GE, DImode);")
5107 (define_expand "sltu"
5108 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5110 "operands[1] = ia64_expand_compare (LTU, DImode);")
5112 (define_expand "sleu"
5113 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5115 "operands[1] = ia64_expand_compare (LEU, DImode);")
5117 (define_expand "sgtu"
5118 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5120 "operands[1] = ia64_expand_compare (GTU, DImode);")
5122 (define_expand "sgeu"
5123 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5125 "operands[1] = ia64_expand_compare (GEU, DImode);")
5127 (define_expand "sunordered"
5128 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5130 "operands[1] = ia64_expand_compare (UNORDERED, DImode);")
5132 (define_expand "sordered"
5133 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
5135 "operands[1] = ia64_expand_compare (ORDERED, DImode);")
5137 ;; Don't allow memory as destination here, because cmov/cmov/st is more
5138 ;; efficient than mov/mov/cst/cst.
5140 (define_insn_and_split "*sne_internal"
5141 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5142 (ne:DI (match_operand:BI 1 "register_operand" "c")
5147 [(cond_exec (ne (match_dup 1) (const_int 0))
5148 (set (match_dup 0) (const_int 1)))
5149 (cond_exec (eq (match_dup 1) (const_int 0))
5150 (set (match_dup 0) (const_int 0)))]
5152 [(set_attr "itanium_class" "unknown")])
5154 (define_insn_and_split "*seq_internal"
5155 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5156 (eq:DI (match_operand:BI 1 "register_operand" "c")
5161 [(cond_exec (ne (match_dup 1) (const_int 0))
5162 (set (match_dup 0) (const_int 0)))
5163 (cond_exec (eq (match_dup 1) (const_int 0))
5164 (set (match_dup 0) (const_int 1)))]
5166 [(set_attr "itanium_class" "unknown")])
5168 ;; ::::::::::::::::::::
5170 ;; :: Conditional move instructions.
5172 ;; ::::::::::::::::::::
5174 ;; ??? Add movXXcc patterns?
5177 ;; DImode if_then_else patterns.
5180 (define_insn "*cmovdi_internal"
5181 [(set (match_operand:DI 0 "destination_operand"
5182 "= r, r, r, r, r, r, r, r, r, r, m, Q, *f,*b,*d*e")
5184 (match_operator 4 "predicate_operator"
5185 [(match_operand:BI 1 "register_operand"
5186 "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c")
5188 (match_operand:DI 2 "move_operand"
5189 "rim, *f, *b,*d*e,rim,rim, rim,*f,*b,*d*e,rO,*f,rOQ,rO, rK")
5190 (match_operand:DI 3 "move_operand"
5191 "rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))]
5192 "ia64_move_ok (operands[0], operands[2])
5193 && ia64_move_ok (operands[0], operands[3])"
5195 [(set_attr "predicable" "no")])
5198 [(set (match_operand 0 "destination_operand" "")
5200 (match_operator 4 "predicate_operator"
5201 [(match_operand:BI 1 "register_operand" "")
5203 (match_operand 2 "move_operand" "")
5204 (match_operand 3 "move_operand" "")))]
5208 bool emitted_something = false;
5209 rtx dest = operands[0];
5210 rtx srct = operands[2];
5211 rtx srcf = operands[3];
5212 rtx cond = operands[4];
5214 if (! rtx_equal_p (dest, srct))
5216 ia64_emit_cond_move (dest, srct, cond);
5217 emitted_something = true;
5219 if (! rtx_equal_p (dest, srcf))
5221 cond = gen_rtx_fmt_ee (GET_CODE (cond) == NE ? EQ : NE,
5222 VOIDmode, operands[1], const0_rtx);
5223 ia64_emit_cond_move (dest, srcf, cond);
5224 emitted_something = true;
5226 if (! emitted_something)
5227 emit_note (NOTE_INSN_DELETED);
5231 ;; Absolute value pattern.
5233 (define_insn "*absdi2_internal"
5234 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
5236 (match_operator 4 "predicate_operator"
5237 [(match_operand:BI 1 "register_operand" "c,c")
5239 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "rI,rI"))
5240 (match_operand:DI 3 "gr_reg_or_22bit_operand" "0,rI")))]
5243 [(set_attr "itanium_class" "ialu,unknown")
5244 (set_attr "predicable" "no")])
5247 [(set (match_operand:DI 0 "register_operand" "")
5249 (match_operator 4 "predicate_operator"
5250 [(match_operand:BI 1 "register_operand" "c,c")
5252 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" ""))
5253 (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))]
5254 "reload_completed && rtx_equal_p (operands[0], operands[3])"
5258 (neg:DI (match_dup 2))))]
5262 [(set (match_operand:DI 0 "register_operand" "")
5264 (match_operator 4 "predicate_operator"
5265 [(match_operand:BI 1 "register_operand" "c,c")
5267 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" ""))
5268 (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))]
5272 (set (match_dup 0) (neg:DI (match_dup 2))))
5275 (set (match_dup 0) (match_dup 3)))]
5277 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
5278 VOIDmode, operands[1], const0_rtx);
5282 ;; SImode if_then_else patterns.
5285 (define_insn "*cmovsi_internal"
5286 [(set (match_operand:SI 0 "destination_operand" "=r,m,*f,r,m,*f,r,m,*f")
5288 (match_operator 4 "predicate_operator"
5289 [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c,c,c,c")
5291 (match_operand:SI 2 "move_operand"
5292 "0,0,0,rim*f,rO,rO,rim*f,rO,rO")
5293 (match_operand:SI 3 "move_operand"
5294 "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))]
5295 "ia64_move_ok (operands[0], operands[2])
5296 && ia64_move_ok (operands[0], operands[3])"
5298 [(set_attr "predicable" "no")])
5300 (define_insn "*abssi2_internal"
5301 [(set (match_operand:SI 0 "gr_register_operand" "=r,r")
5303 (match_operator 4 "predicate_operator"
5304 [(match_operand:BI 1 "register_operand" "c,c")
5306 (neg:SI (match_operand:SI 3 "gr_reg_or_22bit_operand" "rI,rI"))
5307 (match_operand:SI 2 "gr_reg_or_22bit_operand" "0,rI")))]
5310 [(set_attr "itanium_class" "ialu,unknown")
5311 (set_attr "predicable" "no")])
5314 [(set (match_operand:SI 0 "register_operand" "")
5316 (match_operator 4 "predicate_operator"
5317 [(match_operand:BI 1 "register_operand" "c,c")
5319 (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" ""))
5320 (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))]
5321 "reload_completed && rtx_equal_p (operands[0], operands[3])"
5325 (neg:SI (match_dup 2))))]
5329 [(set (match_operand:SI 0 "register_operand" "")
5331 (match_operator 4 "predicate_operator"
5332 [(match_operand:BI 1 "register_operand" "c,c")
5334 (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" ""))
5335 (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))]
5339 (set (match_dup 0) (neg:SI (match_dup 2))))
5342 (set (match_dup 0) (match_dup 3)))]
5344 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
5345 VOIDmode, operands[1], const0_rtx);
5348 (define_insn_and_split "*cond_opsi2_internal"
5349 [(set (match_operand:SI 0 "gr_register_operand" "=r")
5350 (match_operator:SI 5 "condop_operator"
5352 (match_operator 6 "predicate_operator"
5353 [(match_operand:BI 1 "register_operand" "c")
5355 (match_operand:SI 2 "gr_register_operand" "r")
5356 (match_operand:SI 3 "gr_register_operand" "r"))
5357 (match_operand:SI 4 "gr_register_operand" "r")]))]
5363 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 2) (match_dup 4)])))
5366 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 3) (match_dup 4)])))]
5368 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE,
5369 VOIDmode, operands[1], const0_rtx);
5371 [(set_attr "itanium_class" "ialu")
5372 (set_attr "predicable" "no")])
5375 (define_insn_and_split "*cond_opsi2_internal_b"
5376 [(set (match_operand:SI 0 "gr_register_operand" "=r")
5377 (match_operator:SI 5 "condop_operator"
5378 [(match_operand:SI 4 "gr_register_operand" "r")
5380 (match_operator 6 "predicate_operator"
5381 [(match_operand:BI 1 "register_operand" "c")
5383 (match_operand:SI 2 "gr_register_operand" "r")
5384 (match_operand:SI 3 "gr_register_operand" "r"))]))]
5390 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 2)])))
5393 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 3)])))]
5395 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE,
5396 VOIDmode, operands[1], const0_rtx);
5398 [(set_attr "itanium_class" "ialu")
5399 (set_attr "predicable" "no")])
5402 ;; ::::::::::::::::::::
5404 ;; :: Call and branch instructions
5406 ;; ::::::::::::::::::::
5408 ;; Subroutine call instruction returning no value. Operand 0 is the function
5409 ;; to call; operand 1 is the number of bytes of arguments pushed (in mode
5410 ;; `SImode', except it is normally a `const_int'); operand 2 is the number of
5411 ;; registers used as operands.
5413 ;; On most machines, operand 2 is not actually stored into the RTL pattern. It
5414 ;; is supplied for the sake of some RISC machines which need to put this
5415 ;; information into the assembler code; they can put it in the RTL instead of
5418 (define_expand "call"
5419 [(use (match_operand:DI 0 "" ""))
5420 (use (match_operand 1 "" ""))
5421 (use (match_operand 2 "" ""))
5422 (use (match_operand 3 "" ""))]
5425 ia64_expand_call (NULL_RTX, operands[0], operands[2], false);
5429 (define_expand "sibcall"
5430 [(use (match_operand:DI 0 "" ""))
5431 (use (match_operand 1 "" ""))
5432 (use (match_operand 2 "" ""))
5433 (use (match_operand 3 "" ""))]
5436 ia64_expand_call (NULL_RTX, operands[0], operands[2], true);
5440 ;; Subroutine call instruction returning a value. Operand 0 is the hard
5441 ;; register in which the value is returned. There are three more operands,
5442 ;; the same as the three operands of the `call' instruction (but with numbers
5443 ;; increased by one).
5445 ;; Subroutines that return `BLKmode' objects use the `call' insn.
5447 (define_expand "call_value"
5448 [(use (match_operand 0 "" ""))
5449 (use (match_operand:DI 1 "" ""))
5450 (use (match_operand 2 "" ""))
5451 (use (match_operand 3 "" ""))
5452 (use (match_operand 4 "" ""))]
5455 ia64_expand_call (operands[0], operands[1], operands[3], false);
5459 (define_expand "sibcall_value"
5460 [(use (match_operand 0 "" ""))
5461 (use (match_operand:DI 1 "" ""))
5462 (use (match_operand 2 "" ""))
5463 (use (match_operand 3 "" ""))
5464 (use (match_operand 4 "" ""))]
5467 ia64_expand_call (operands[0], operands[1], operands[3], true);
5471 ;; Call subroutine returning any type.
5473 (define_expand "untyped_call"
5474 [(parallel [(call (match_operand 0 "" "")
5476 (match_operand 1 "" "")
5477 (match_operand 2 "" "")])]
5482 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
5484 for (i = 0; i < XVECLEN (operands[2], 0); i++)
5486 rtx set = XVECEXP (operands[2], 0, i);
5487 emit_move_insn (SET_DEST (set), SET_SRC (set));
5490 /* The optimizer does not know that the call sets the function value
5491 registers we stored in the result block. We avoid problems by
5492 claiming that all hard registers are used and clobbered at this
5494 emit_insn (gen_blockage ());
5499 (define_insn "call_nogp"
5500 [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i"))
5502 (clobber (match_operand:DI 1 "register_operand" "=b,b"))]
5504 "br.call%+.many %1 = %0"
5505 [(set_attr "itanium_class" "br,scall")])
5507 (define_insn "call_value_nogp"
5508 [(set (match_operand 0 "" "=X,X")
5509 (call (mem:DI (match_operand:DI 1 "call_operand" "?b,i"))
5511 (clobber (match_operand:DI 2 "register_operand" "=b,b"))]
5513 "br.call%+.many %2 = %1"
5514 [(set_attr "itanium_class" "br,scall")])
5516 (define_insn "sibcall_nogp"
5517 [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i"))
5521 [(set_attr "itanium_class" "br,scall")])
5523 (define_insn "call_gp"
5524 [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,i"))
5526 (clobber (match_operand:DI 1 "register_operand" "=b,b"))
5527 (clobber (match_scratch:DI 2 "=&r,X"))
5528 (clobber (match_scratch:DI 3 "=b,X"))]
5531 [(set_attr "itanium_class" "br,scall")])
5533 ;; Irritatingly, we don't have access to INSN within the split body.
5534 ;; See commentary in ia64_split_call as to why these aren't peep2.
5536 [(call (mem (match_operand 0 "call_operand" ""))
5538 (clobber (match_operand:DI 1 "register_operand" ""))
5539 (clobber (match_scratch:DI 2 ""))
5540 (clobber (match_scratch:DI 3 ""))]
5541 "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
5544 ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2],
5545 operands[3], true, false);
5550 [(call (mem (match_operand 0 "call_operand" ""))
5552 (clobber (match_operand:DI 1 "register_operand" ""))
5553 (clobber (match_scratch:DI 2 ""))
5554 (clobber (match_scratch:DI 3 ""))]
5558 ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2],
5559 operands[3], false, false);
5563 (define_insn "call_value_gp"
5564 [(set (match_operand 0 "" "=X,X")
5565 (call (mem:DI (match_operand:DI 1 "call_operand" "?r,i"))
5567 (clobber (match_operand:DI 2 "register_operand" "=b,b"))
5568 (clobber (match_scratch:DI 3 "=&r,X"))
5569 (clobber (match_scratch:DI 4 "=b,X"))]
5572 [(set_attr "itanium_class" "br,scall")])
5575 [(set (match_operand 0 "" "")
5576 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
5578 (clobber (match_operand:DI 2 "register_operand" ""))
5579 (clobber (match_scratch:DI 3 ""))
5580 (clobber (match_scratch:DI 4 ""))]
5581 "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
5584 ia64_split_call (operands[0], operands[1], operands[2], operands[3],
5585 operands[4], true, false);
5590 [(set (match_operand 0 "" "")
5591 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
5593 (clobber (match_operand:DI 2 "register_operand" ""))
5594 (clobber (match_scratch:DI 3 ""))
5595 (clobber (match_scratch:DI 4 ""))]
5599 ia64_split_call (operands[0], operands[1], operands[2], operands[3],
5600 operands[4], false, false);
5604 (define_insn_and_split "sibcall_gp"
5605 [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,i"))
5607 (clobber (match_scratch:DI 1 "=&r,X"))
5608 (clobber (match_scratch:DI 2 "=b,X"))]
5614 ia64_split_call (NULL_RTX, operands[0], NULL_RTX, operands[1],
5615 operands[2], true, true);
5618 [(set_attr "itanium_class" "br")])
5620 (define_insn "return_internal"
5622 (use (match_operand:DI 0 "register_operand" "b"))]
5624 "br.ret.sptk.many %0"
5625 [(set_attr "itanium_class" "br")])
5627 (define_insn "return"
5629 "ia64_direct_return ()"
5630 "br.ret.sptk.many rp"
5631 [(set_attr "itanium_class" "br")])
5633 (define_insn "*return_true"
5635 (if_then_else (match_operator 0 "predicate_operator"
5636 [(match_operand:BI 1 "register_operand" "c")
5640 "ia64_direct_return ()"
5641 "(%J0) br.ret%+.many rp"
5642 [(set_attr "itanium_class" "br")
5643 (set_attr "predicable" "no")])
5645 (define_insn "*return_false"
5647 (if_then_else (match_operator 0 "predicate_operator"
5648 [(match_operand:BI 1 "register_operand" "c")
5652 "ia64_direct_return ()"
5653 "(%j0) br.ret%+.many rp"
5654 [(set_attr "itanium_class" "br")
5655 (set_attr "predicable" "no")])
5658 [(set (pc) (label_ref (match_operand 0 "" "")))]
5661 [(set_attr "itanium_class" "br")])
5663 (define_insn "indirect_jump"
5664 [(set (pc) (match_operand:DI 0 "register_operand" "b"))]
5667 [(set_attr "itanium_class" "br")])
5669 (define_expand "tablejump"
5670 [(parallel [(set (pc) (match_operand:DI 0 "memory_operand" ""))
5671 (use (label_ref (match_operand 1 "" "")))])]
5674 rtx op0 = operands[0];
5677 /* ??? Bother -- do_tablejump is "helpful" and pulls the table
5678 element into a register without bothering to see whether that
5679 is necessary given the operand predicate. Check for MEM just
5680 in case someone fixes this. */
5681 if (GET_CODE (op0) == MEM)
5682 addr = XEXP (op0, 0);
5685 /* Otherwise, cheat and guess that the previous insn in the
5686 stream was the memory load. Grab the address from that.
5687 Note we have to momentarily pop out of the sequence started
5688 by the insn-emit wrapper in order to grab the last insn. */
5692 last = get_last_insn ();
5694 set = single_set (last);
5696 if (! rtx_equal_p (SET_DEST (set), op0)
5697 || GET_CODE (SET_SRC (set)) != MEM)
5699 addr = XEXP (SET_SRC (set), 0);
5700 if (rtx_equal_p (addr, op0))
5704 /* Jump table elements are stored pc-relative. That is, a displacement
5705 from the entry to the label. Thus to convert to an absolute address
5706 we add the address of the memory from which the value is loaded. */
5707 operands[0] = expand_simple_binop (DImode, PLUS, op0, addr,
5708 NULL_RTX, 1, OPTAB_DIRECT);
5711 (define_insn "*tablejump_internal"
5712 [(set (pc) (match_operand:DI 0 "register_operand" "b"))
5713 (use (label_ref (match_operand 1 "" "")))]
5716 [(set_attr "itanium_class" "br")])
5719 ;; ::::::::::::::::::::
5721 ;; :: Prologue and Epilogue instructions
5723 ;; ::::::::::::::::::::
5725 (define_expand "prologue"
5729 ia64_expand_prologue ();
5733 (define_expand "epilogue"
5737 ia64_expand_epilogue (0);
5741 (define_expand "sibcall_epilogue"
5745 ia64_expand_epilogue (1);
5749 ;; This prevents the scheduler from moving the SP decrement past FP-relative
5750 ;; stack accesses. This is the same as adddi3 plus the extra set.
5752 (define_insn "prologue_allocate_stack"
5753 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
5754 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,a")
5755 (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))
5756 (set (match_operand:DI 3 "register_operand" "+r,r,r")
5763 [(set_attr "itanium_class" "ialu")])
5765 ;; This prevents the scheduler from moving the SP restore past FP-relative
5766 ;; stack accesses. This is similar to movdi plus the extra set.
5768 (define_insn "epilogue_deallocate_stack"
5769 [(set (match_operand:DI 0 "register_operand" "=r")
5770 (match_operand:DI 1 "register_operand" "+r"))
5771 (set (match_dup 1) (match_dup 1))]
5774 [(set_attr "itanium_class" "ialu")])
5776 ;; As USE insns aren't meaningful after reload, this is used instead
5777 ;; to prevent deleting instructions setting registers for EH handling
5778 (define_insn "prologue_use"
5779 [(unspec:DI [(match_operand:DI 0 "register_operand" "")]
5780 UNSPEC_PROLOGUE_USE)]
5783 [(set_attr "itanium_class" "ignore")
5784 (set_attr "predicable" "no")
5785 (set_attr "empty" "yes")])
5787 ;; Allocate a new register frame.
5789 (define_insn "alloc"
5790 [(set (match_operand:DI 0 "register_operand" "=r")
5791 (unspec_volatile:DI [(const_int 0)] UNSPECV_ALLOC))
5792 (use (match_operand:DI 1 "const_int_operand" "i"))
5793 (use (match_operand:DI 2 "const_int_operand" "i"))
5794 (use (match_operand:DI 3 "const_int_operand" "i"))
5795 (use (match_operand:DI 4 "const_int_operand" "i"))]
5797 "alloc %0 = ar.pfs, %1, %2, %3, %4"
5798 [(set_attr "itanium_class" "syst_m0")
5799 (set_attr "predicable" "no")])
5802 (define_expand "gr_spill"
5803 [(parallel [(set (match_operand:DI 0 "memory_operand" "=m")
5804 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5805 (match_operand:DI 2 "const_int_operand" "")]
5807 (clobber (match_dup 3))])]
5809 "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
5811 (define_insn "gr_spill_internal"
5812 [(set (match_operand:DI 0 "memory_operand" "=m")
5813 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5814 (match_operand:DI 2 "const_int_operand" "")]
5816 (clobber (match_operand:DI 3 "register_operand" ""))]
5819 /* Note that we use a C output pattern here to avoid the predicate
5820 being automatically added before the .mem.offset directive. */
5821 return ".mem.offset %2, 0\;%,st8.spill %0 = %1%P0";
5823 [(set_attr "itanium_class" "st")])
5826 (define_expand "gr_restore"
5827 [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
5828 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
5829 (match_operand:DI 2 "const_int_operand" "")]
5831 (use (match_dup 3))])]
5833 "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
5835 (define_insn "gr_restore_internal"
5836 [(set (match_operand:DI 0 "register_operand" "=r")
5837 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
5838 (match_operand:DI 2 "const_int_operand" "")]
5840 (use (match_operand:DI 3 "register_operand" ""))]
5842 { return ".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1"; }
5843 [(set_attr "itanium_class" "ld")])
5845 (define_insn "fr_spill"
5846 [(set (match_operand:XF 0 "memory_operand" "=m")
5847 (unspec:XF [(match_operand:XF 1 "register_operand" "f")]
5850 "stf.spill %0 = %1%P0"
5851 [(set_attr "itanium_class" "stf")])
5853 (define_insn "fr_restore"
5854 [(set (match_operand:XF 0 "register_operand" "=f")
5855 (unspec:XF [(match_operand:XF 1 "memory_operand" "m")]
5856 UNSPEC_FR_RESTORE))]
5858 "ldf.fill %0 = %1%P1"
5859 [(set_attr "itanium_class" "fld")])
5861 ;; ??? The explicit stop is not ideal. It would be better if
5862 ;; rtx_needs_barrier took care of this, but this is something that can be
5863 ;; fixed later. This avoids an RSE DV.
5865 (define_insn "bsp_value"
5866 [(set (match_operand:DI 0 "register_operand" "=r")
5867 (unspec:DI [(const_int 0)] UNSPEC_BSP_VALUE))]
5871 return \";;\;%,mov %0 = ar.bsp\";
5873 [(set_attr "itanium_class" "frar_i")])
5875 (define_insn "set_bsp"
5876 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
5894 [(set_attr "itanium_class" "unknown")
5895 (set_attr "predicable" "no")])
5897 ;; ??? The explicit stops are not ideal. It would be better if
5898 ;; rtx_needs_barrier took care of this, but this is something that can be
5899 ;; fixed later. This avoids an RSE DV.
5901 (define_insn "flushrs"
5902 [(unspec [(const_int 0)] UNSPEC_FLUSHRS)]
5905 [(set_attr "itanium_class" "rse_m")
5906 (set_attr "predicable" "no")])
5908 ;; ::::::::::::::::::::
5910 ;; :: Miscellaneous instructions
5912 ;; ::::::::::::::::::::
5914 ;; ??? Emitting a NOP instruction isn't very useful. This should probably
5915 ;; be emitting ";;" to force a break in the instruction packing.
5917 ;; No operation, needed in case the user uses -g but not -O.
5922 [(set_attr "itanium_class" "nop")])
5924 (define_insn "nop_m"
5928 [(set_attr "itanium_class" "nop_m")])
5930 (define_insn "nop_i"
5934 [(set_attr "itanium_class" "nop_i")])
5936 (define_insn "nop_f"
5940 [(set_attr "itanium_class" "nop_f")])
5942 (define_insn "nop_b"
5946 [(set_attr "itanium_class" "nop_b")])
5948 (define_insn "nop_x"
5952 [(set_attr "itanium_class" "nop_x")
5953 (set_attr "empty" "yes")])
5955 ;; The following insn will be never generated. It is used only by
5956 ;; insn scheduler to change state before advancing cycle.
5957 (define_insn "pre_cycle"
5961 [(set_attr "itanium_class" "pre_cycle")])
5963 (define_insn "bundle_selector"
5964 [(unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BUNDLE_SELECTOR)]
5966 { return get_bundle_name (INTVAL (operands[0])); }
5967 [(set_attr "itanium_class" "ignore")
5968 (set_attr "predicable" "no")])
5970 ;; Pseudo instruction that prevents the scheduler from moving code above this
5972 (define_insn "blockage"
5973 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
5976 [(set_attr "itanium_class" "ignore")
5977 (set_attr "predicable" "no")])
5979 (define_insn "insn_group_barrier"
5980 [(unspec_volatile [(match_operand 0 "const_int_operand" "")]
5981 UNSPECV_INSN_GROUP_BARRIER)]
5984 [(set_attr "itanium_class" "stop_bit")
5985 (set_attr "predicable" "no")
5986 (set_attr "empty" "yes")])
5988 (define_expand "trap"
5989 [(trap_if (const_int 1) (const_int 0))]
5993 ;; ??? We don't have a match-any slot type. Setting the type to unknown
5994 ;; produces worse code that setting the slot type to A.
5996 (define_insn "*trap"
5997 [(trap_if (const_int 1) (match_operand 0 "const_int_operand" ""))]
6000 [(set_attr "itanium_class" "chk_s")])
6002 (define_expand "conditional_trap"
6003 [(trap_if (match_operand 0 "" "") (match_operand 1 "" ""))]
6006 operands[0] = ia64_expand_compare (GET_CODE (operands[0]), VOIDmode);
6009 (define_insn "*conditional_trap"
6010 [(trap_if (match_operator 0 "predicate_operator"
6011 [(match_operand:BI 1 "register_operand" "c")
6013 (match_operand 2 "const_int_operand" ""))]
6016 [(set_attr "itanium_class" "chk_s")
6017 (set_attr "predicable" "no")])
6019 (define_insn "break_f"
6020 [(unspec_volatile [(const_int 0)] UNSPECV_BREAK)]
6023 [(set_attr "itanium_class" "nop_f")])
6025 (define_insn "prefetch"
6026 [(prefetch (match_operand:DI 0 "address_operand" "p")
6027 (match_operand:DI 1 "const_int_operand" "n")
6028 (match_operand:DI 2 "const_int_operand" "n"))]
6031 static const char * const alt[2][4] = {
6033 "%,lfetch.nta [%0]",
6034 "%,lfetch.nt1 [%0]",
6035 "%,lfetch.nt2 [%0]",
6039 "%,lfetch.excl.nta [%0]",
6040 "%,lfetch.excl.nt1 [%0]",
6041 "%,lfetch.excl.nt2 [%0]",
6042 "%,lfetch.excl [%0]"
6045 int i = (INTVAL (operands[1]));
6046 int j = (INTVAL (operands[2]));
6048 if (i != 0 && i != 1)
6054 [(set_attr "itanium_class" "lfetch")])
6056 ;; Non-local goto support.
6058 (define_expand "save_stack_nonlocal"
6059 [(use (match_operand:OI 0 "memory_operand" ""))
6060 (use (match_operand:DI 1 "register_operand" ""))]
6063 emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
6064 \"__ia64_save_stack_nonlocal\"),
6065 0, VOIDmode, 2, XEXP (operands[0], 0), Pmode,
6066 operands[1], Pmode);
6070 (define_expand "nonlocal_goto"
6071 [(use (match_operand 0 "general_operand" ""))
6072 (use (match_operand 1 "general_operand" ""))
6073 (use (match_operand 2 "general_operand" ""))
6074 (use (match_operand 3 "general_operand" ""))]
6077 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"),
6078 LCT_NORETURN, VOIDmode, 3,
6080 copy_to_reg (XEXP (operands[2], 0)), Pmode,
6081 operands[3], Pmode);
6086 (define_insn_and_split "builtin_setjmp_receiver"
6087 [(unspec_volatile [(match_operand:DI 0 "" "")] UNSPECV_SETJMP_RECEIVER)]
6097 (define_expand "eh_epilogue"
6098 [(use (match_operand:DI 0 "register_operand" "r"))
6099 (use (match_operand:DI 1 "register_operand" "r"))
6100 (use (match_operand:DI 2 "register_operand" "r"))]
6103 rtx bsp = gen_rtx_REG (Pmode, 10);
6104 rtx sp = gen_rtx_REG (Pmode, 9);
6106 if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 10)
6108 emit_move_insn (bsp, operands[0]);
6111 if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 9)
6113 emit_move_insn (sp, operands[2]);
6116 emit_insn (gen_rtx_USE (VOIDmode, sp));
6117 emit_insn (gen_rtx_USE (VOIDmode, bsp));
6119 cfun->machine->ia64_eh_epilogue_sp = sp;
6120 cfun->machine->ia64_eh_epilogue_bsp = bsp;
6123 ;; Builtin apply support.
6125 (define_expand "restore_stack_nonlocal"
6126 [(use (match_operand:DI 0 "register_operand" ""))
6127 (use (match_operand:OI 1 "memory_operand" ""))]
6130 emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
6131 "__ia64_restore_stack_nonlocal"),
6133 copy_to_reg (XEXP (operands[1], 0)), Pmode);
6138 ;;; Intrinsics support.
6141 [(set (mem:BLK (match_dup 0))
6142 (unspec:BLK [(mem:BLK (match_dup 0))] UNSPEC_MF))]
6145 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
6146 MEM_VOLATILE_P (operands[0]) = 1;
6149 (define_insn "*mf_internal"
6150 [(set (match_operand:BLK 0 "" "")
6151 (unspec:BLK [(match_operand:BLK 1 "" "")] UNSPEC_MF))]
6154 [(set_attr "itanium_class" "syst_m")])
6156 (define_insn "fetchadd_acq_si"
6157 [(set (match_operand:SI 0 "gr_register_operand" "=r")
6158 (match_operand:SI 1 "not_postinc_memory_operand" "+S"))
6160 (unspec:SI [(match_dup 1)
6161 (match_operand:SI 2 "fetchadd_operand" "n")]
6162 UNSPEC_FETCHADD_ACQ))]
6164 "fetchadd4.acq %0 = %1, %2"
6165 [(set_attr "itanium_class" "sem")])
6167 (define_insn "fetchadd_acq_di"
6168 [(set (match_operand:DI 0 "gr_register_operand" "=r")
6169 (match_operand:DI 1 "not_postinc_memory_operand" "+S"))
6171 (unspec:DI [(match_dup 1)
6172 (match_operand:DI 2 "fetchadd_operand" "n")]
6173 UNSPEC_FETCHADD_ACQ))]
6175 "fetchadd8.acq %0 = %1, %2"
6176 [(set_attr "itanium_class" "sem")])
6178 (define_insn "cmpxchg_acq_si"
6179 [(set (match_operand:SI 0 "gr_register_operand" "=r")
6180 (match_operand:SI 1 "not_postinc_memory_operand" "+S"))
6182 (unspec:SI [(match_dup 1)
6183 (match_operand:SI 2 "gr_register_operand" "r")
6184 (match_operand:DI 3 "ar_ccv_reg_operand" "")]
6185 UNSPEC_CMPXCHG_ACQ))]
6187 "cmpxchg4.acq %0 = %1, %2, %3"
6188 [(set_attr "itanium_class" "sem")])
6190 (define_insn "cmpxchg_acq_di"
6191 [(set (match_operand:DI 0 "gr_register_operand" "=r")
6192 (match_operand:DI 1 "not_postinc_memory_operand" "+S"))
6194 (unspec:DI [(match_dup 1)
6195 (match_operand:DI 2 "gr_register_operand" "r")
6196 (match_operand:DI 3 "ar_ccv_reg_operand" "")]
6197 UNSPEC_CMPXCHG_ACQ))]
6199 "cmpxchg8.acq %0 = %1, %2, %3"
6200 [(set_attr "itanium_class" "sem")])
6202 (define_insn "xchgsi"
6203 [(set (match_operand:SI 0 "gr_register_operand" "=r")
6204 (match_operand:SI 1 "not_postinc_memory_operand" "+S"))
6206 (match_operand:SI 2 "gr_register_operand" "r"))]
6209 [(set_attr "itanium_class" "sem")])
6211 (define_insn "xchgdi"
6212 [(set (match_operand:DI 0 "gr_register_operand" "=r")
6213 (match_operand:DI 1 "not_postinc_memory_operand" "+S"))
6215 (match_operand:DI 2 "gr_register_operand" "r"))]
6218 [(set_attr "itanium_class" "sem")])
6223 [(match_operator 0 "predicate_operator"
6224 [(match_operand:BI 1 "register_operand" "c")
6229 (define_insn "pred_rel_mutex"
6230 [(set (match_operand:BI 0 "register_operand" "+c")
6231 (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
6233 ".pred.rel.mutex %0, %I0"
6234 [(set_attr "itanium_class" "ignore")
6235 (set_attr "predicable" "no")])
6237 (define_insn "safe_across_calls_all"
6238 [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_ALL)]
6240 ".pred.safe_across_calls p1-p63"
6241 [(set_attr "itanium_class" "ignore")
6242 (set_attr "predicable" "no")])
6244 (define_insn "safe_across_calls_normal"
6245 [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_NORMAL)]
6248 emit_safe_across_calls ();
6251 [(set_attr "itanium_class" "ignore")
6252 (set_attr "predicable" "no")])
6254 ;; UNSPEC instruction definition to "swizzle" 32 bit pointer into 64 bit
6255 ;; pointer. This is used by the HP-UX 32 bit mode.
6257 (define_insn "ptr_extend"
6258 [(set (match_operand:DI 0 "gr_register_operand" "=r")
6259 (unspec:DI [(match_operand:SI 1 "gr_register_operand" "r")]
6263 [(set_attr "itanium_class" "ialu")])
6266 ;; Optimizations for ptr_extend
6268 (define_insn "ptr_extend_plus_imm"
6269 [(set (match_operand:DI 0 "gr_register_operand" "=r")
6271 [(plus:SI (match_operand:SI 1 "basereg_operand" "r")
6272 (match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))]
6274 "addp4_optimize_ok (operands[1], operands[2])"
6276 [(set_attr "itanium_class" "ialu")])
6278 (define_insn "*ptr_extend_plus_2"
6279 [(set (match_operand:DI 0 "gr_register_operand" "=r")
6281 [(plus:SI (match_operand:SI 1 "gr_register_operand" "r")
6282 (match_operand:SI 2 "basereg_operand" "r"))]
6284 "addp4_optimize_ok (operands[1], operands[2])"
6286 [(set_attr "itanium_class" "ialu")])