1 ;; IA-64 Machine description template
2 ;; Copyright (C) 1999, 2000 Free Software Foundation, Inc.
3 ;; Contributed by James E. Wilson <wilson@cygnus.com> and
4 ;; David Mosberger <davidm@hpl.hp.com>.
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; ??? register_operand accepts (subreg:DI (mem:SI X)) which forces later
26 ;; reload. This will be fixed once scheduling support is turned on.
28 ;; ??? Optimize for post-increment addressing modes.
30 ;; ??? fselect is not supported, because there is no integer register
33 ;; ??? fp abs/min/max instructions may also work for integer values.
35 ;; ??? Would a predicate_reg_operand predicate be useful? The HP one is buggy,
36 ;; it assumes the operand is a register and takes REGNO of it without checking.
38 ;; ??? Would a branch_reg_operand predicate be useful? The HP one is buggy,
39 ;; it assumes the operand is a register and takes REGNO of it without checking.
41 ;; ??? Go through list of documented named patterns and look for more to
44 ;; ??? Go through instruction manual and look for more instructions that
47 ;; ??? Add function unit scheduling info for Itanium (TM) processor.
49 ;; ??? The explicit stop in the flushrs pattern is not ideal. It
50 ;; would be better if rtx_needs_barrier took care of this, but this is
51 ;; something that can be fixed later.
53 ;; ??? Need a better way to describe alternate fp status registers.
77 ;; 2 insn_group_barrier
79 ;; 8 pred.safe_across_calls all
80 ;; 9 pred.safe_across_calls normal
82 ;; ::::::::::::::::::::
86 ;; ::::::::::::::::::::
88 ;; Instruction type. This primarily determines how instructions can be
89 ;; packed in bundles, and secondarily affects scheduling to function units.
91 ;; A alu, can go in I or M syllable of a bundle
96 ;; L long immediate, takes two syllables
99 ;; ??? Should not have any pattern with type unknown. Perhaps add code to
100 ;; check this in md_reorg? Currently use unknown for patterns which emit
101 ;; multiple instructions, patterns which emit 0 instructions, and patterns
102 ;; which emit instruction that can go in any slot (e.g. nop).
104 (define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld,fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,ld,chk_s,long_i,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,st,syst_m0,syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop_b,nop_f,nop_i,nop_m,nop_x"
105 (const_string "unknown"))
107 ;; chk_s has an I and an M form; use type A for convenience.
108 (define_attr "type" "unknown,A,I,M,F,B,L,X,S"
109 (cond [(eq_attr "itanium_class" "ld,st,fld,stf,sem,nop_m") (const_string "M")
110 (eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M")
111 (eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M")
112 (eq_attr "itanium_class" "chk_s,ialu,icmp,ilog") (const_string "A")
113 (eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F")
114 (eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F")
115 (eq_attr "itanium_class" "frar_i,toar_i,frbr,tobr") (const_string "I")
116 (eq_attr "itanium_class" "frpr,topr,ishf,xtd,tbit") (const_string "I")
117 (eq_attr "itanium_class" "mmmul,mmshf,mmshfi,nop_i") (const_string "I")
118 (eq_attr "itanium_class" "br,scall,nop_b") (const_string "B")
119 (eq_attr "itanium_class" "stop_bit") (const_string "S")
120 (eq_attr "itanium_class" "nop_x") (const_string "X")
121 (eq_attr "itanium_class" "long_i") (const_string "L")]
122 (const_string "unknown")))
124 (define_attr "itanium_requires_unit0" "no,yes"
125 (cond [(eq_attr "itanium_class" "syst_m0,sem,frfr,rse_m") (const_string "yes")
126 (eq_attr "itanium_class" "toar_m,frar_m") (const_string "yes")
127 (eq_attr "itanium_class" "frbr,tobr,mmmul") (const_string "yes")
128 (eq_attr "itanium_class" "tbit,ishf,topr,frpr") (const_string "yes")
129 (eq_attr "itanium_class" "toar_i,frar_i") (const_string "yes")
130 (eq_attr "itanium_class" "fmisc,fcmp") (const_string "yes")]
131 (const_string "no")))
133 ;; Predication. True iff this instruction can be predicated.
135 (define_attr "predicable" "no,yes" (const_string "yes"))
138 ;; ::::::::::::::::::::
142 ;; ::::::::::::::::::::
144 ;; We define 6 "dummy" functional units. All the real work to decide which
145 ;; insn uses which unit is done by our MD_SCHED_REORDER hooks. We only
146 ;; have to ensure here that there are enough copies of the dummy unit so
147 ;; that the scheduler doesn't get confused by MD_SCHED_REORDER.
148 ;; Other than the 6 dummies for normal insns, we also add a single dummy unit
151 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "br") 0 0)
152 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "scall") 0 0)
153 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fcmp") 2 0)
154 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fcvtfx") 7 0)
155 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fld") 9 0)
156 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fmac") 5 0)
157 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fmisc") 5 0)
159 ;; There is only one insn `mov = ar.bsp' for frar_i:
160 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frar_i") 13 0)
161 ;; There is only ony insn `mov = ar.unat' for frar_m:
162 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frar_m") 6 0)
163 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frbr") 2 0)
164 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frfr") 2 0)
165 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frpr") 2 0)
167 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ialu") 1 0)
168 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "icmp") 1 0)
169 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ilog") 1 0)
170 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ishf") 1 0)
171 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ld") 2 0)
172 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "long_i") 1 0)
173 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "mmmul") 2 0)
174 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "mmshf") 2 0)
175 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "mmshfi") 2 0)
177 ;; Now we have only one insn (flushrs) of such class. We assume that flushrs
178 ;; is the 1st syllable of the bundle after stop bit.
179 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "rse_m") 0 0)
180 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "sem") 11 0)
181 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "stf") 1 0)
182 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "st") 1 0)
183 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "syst_m0") 1 0)
184 ;; Now we use only one insn `mf'. Therfore latency time is set up to 0.
185 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "syst_m") 0 0)
186 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "tbit") 1 0)
188 ;; There is only one insn `mov ar.pfs =' for toar_i therefore we use
189 ;; latency time equal to 0:
190 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "toar_i") 0 0)
191 ;; There are only ony 2 insns `mov ar.ccv =' and `mov ar.unat =' for toar_m:
192 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "toar_m") 5 0)
193 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "tobr") 1 0)
194 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "tofr") 9 0)
195 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "topr") 1 0)
196 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "xmpy") 7 0)
197 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "xtd") 1 0)
199 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_m") 0 0)
200 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_i") 0 0)
201 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_f") 0 0)
202 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_b") 0 0)
203 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_x") 0 0)
205 (define_function_unit "stop_bit" 1 1 (eq_attr "itanium_class" "stop_bit") 0 0)
206 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ignore") 0 0)
207 (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "unknown") 0 0)
209 ;; ::::::::::::::::::::
213 ;; ::::::::::::::::::::
215 ;; Set of a single predicate register. This is only used to implement
216 ;; pr-to-pr move and complement.
218 (define_insn "*movcci"
219 [(set (match_operand:CCI 0 "register_operand" "=c,c,c")
220 (match_operand:CCI 1 "nonmemory_operand" "O,n,c"))]
223 cmp.ne %0, p0 = r0, r0
224 cmp.eq %0, p0 = r0, r0
225 (%1) cmp.eq.unc %0, p0 = r0, r0"
226 [(set_attr "itanium_class" "icmp")
227 (set_attr "predicable" "no")])
230 [(set (match_operand:BI 0 "nonimmediate_operand" "=c,c,?c,?*r, c,*r,*r,*m,*r")
231 (match_operand:BI 1 "move_operand" " O,n, c, c,*r, n,*m,*r,*r"))]
234 cmp.ne %0, %I0 = r0, r0
235 cmp.eq %0, %I0 = r0, r0
238 tbit.nz %0, %I0 = %1, 0
243 [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu")])
246 [(set (match_operand:BI 0 "register_operand" "")
247 (match_operand:BI 1 "register_operand" ""))]
249 && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0]))
250 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
251 [(cond_exec (ne (match_dup 1) (const_int 0))
252 (set (match_dup 0) (const_int 1)))
253 (cond_exec (eq (match_dup 1) (const_int 0))
254 (set (match_dup 0) (const_int 0)))]
258 [(set (match_operand:BI 0 "register_operand" "")
259 (match_operand:BI 1 "register_operand" ""))]
261 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
262 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
263 [(set (match_dup 2) (match_dup 4))
264 (set (match_dup 3) (match_dup 5))
265 (set (match_dup 0) (unspec:BI [(match_dup 0)] 7))]
266 "operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0]));
267 operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1);
268 operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1]));
269 operands[5] = gen_rtx_REG (CCImode, REGNO (operands[1]) + 1);")
271 (define_expand "movqi"
272 [(set (match_operand:QI 0 "general_operand" "")
273 (match_operand:QI 1 "general_operand" ""))]
277 if (! reload_in_progress && ! reload_completed
278 && ! ia64_move_ok (operands[0], operands[1]))
279 operands[1] = force_reg (QImode, operands[1]);
282 ;; Errata 72 implies that we cannot use predicated loads and stores
283 ;; on affected systems. Reuse TARGET_A_STEP for convenience.
285 ;; ??? It would be convenient at this point if the cond_exec pattern
286 ;; expander understood non-constant conditions on attributes. Failing
287 ;; that we have to replicate patterns.
289 (define_insn "*movqicc_astep"
291 (match_operator 2 "predicate_operator"
292 [(match_operand:BI 3 "register_operand" "c,c,c,c,c")
294 (set (match_operand:QI 0 "register_operand" "=r,r, r,*f,*f")
295 (match_operand:QI 1 "nonmemory_operand" "rO,J,*f,rO,*f")))]
296 "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
299 (%J2) addl %0 = %1, r0
300 (%J2) getf.sig %0 = %1
301 (%J2) setf.sig %0 = %r1
303 [(set_attr "itanium_class" "ialu,ialu,frfr,tofr,fmisc")
304 (set_attr "predicable" "no")])
306 (define_insn "*movqi_internal_astep"
307 [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
308 (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
309 "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
318 [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")
319 (set_attr "predicable" "no")])
321 (define_insn "*movqi_internal"
322 [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
323 (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
324 "! TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
333 [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")])
335 (define_expand "movhi"
336 [(set (match_operand:HI 0 "general_operand" "")
337 (match_operand:HI 1 "general_operand" ""))]
341 if (! reload_in_progress && ! reload_completed
342 && ! ia64_move_ok (operands[0], operands[1]))
343 operands[1] = force_reg (HImode, operands[1]);
346 ;; Errata 72 workaround.
347 (define_insn "*movhicc_astep"
349 (match_operator 2 "predicate_operator"
350 [(match_operand:BI 3 "register_operand" "c,c,c,c,c")
352 (set (match_operand:HI 0 "register_operand" "=r,r, r,*f,*f")
353 (match_operand:HI 1 "nonmemory_operand" "rO,J,*f,rO,*f")))]
354 "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
357 (%J2) addl %0 = %1, r0
358 (%J2) getf.sig %0 = %1
359 (%J2) setf.sig %0 = %r1
361 [(set_attr "itanium_class" "ialu,ialu,frfr,tofr,fmisc")
362 (set_attr "predicable" "no")])
364 (define_insn "*movhi_internal_astep"
365 [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
366 (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
367 "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
376 [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")
377 (set_attr "predicable" "no")])
379 (define_insn "*movhi_internal"
380 [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
381 (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
382 "! TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
391 [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")])
393 (define_expand "movsi"
394 [(set (match_operand:SI 0 "general_operand" "")
395 (match_operand:SI 1 "general_operand" ""))]
399 if (! reload_in_progress && ! reload_completed
400 && ! ia64_move_ok (operands[0], operands[1]))
401 operands[1] = force_reg (SImode, operands[1]);
404 ;; Errata 72 workaround.
405 (define_insn "*movsicc_astep"
407 (match_operator 2 "predicate_operator"
408 [(match_operand:BI 3 "register_operand" "c,c,c,c,c,c,c,c")
410 (set (match_operand:SI 0 "register_operand" "=r,r,r, r,*f,*f, r,*d")
411 (match_operand:SI 1 "nonmemory_operand" "rO,J,i,*f,rO,*f,*d,rK")))]
412 "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
415 (%J2) addl %0 = %1, r0
417 (%J2) getf.sig %0 = %1
418 (%J2) setf.sig %0 = %r1
422 ;; frar_m, toar_m ??? why not frar_i and toar_i
423 [(set_attr "itanium_class" "ialu,ialu,long_i,frfr,tofr,fmisc,frar_m,toar_m")
424 (set_attr "predicable" "no")])
426 (define_insn "*movsi_internal_astep"
427 [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d")
428 (match_operand:SI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f,*d,rK"))]
429 "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
441 ;; frar_m, toar_m ??? why not frar_i and toar_i
442 [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")
443 (set_attr "predicable" "no")])
445 (define_insn "*movsi_internal"
446 [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d")
447 (match_operand:SI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f,*d,rK"))]
448 "! TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
460 ;; frar_m, toar_m ??? why not frar_i and toar_i
461 [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")])
463 (define_expand "movdi"
464 [(set (match_operand:DI 0 "general_operand" "")
465 (match_operand:DI 1 "general_operand" ""))]
469 if (! reload_in_progress && ! reload_completed
470 && ! ia64_move_ok (operands[0], operands[1]))
471 operands[1] = force_reg (DImode, operands[1]);
472 if (! TARGET_NO_PIC && symbolic_operand (operands[1], DImode))
474 /* Before optimization starts, delay committing to any particular
475 type of PIC address load. If this function gets deferred, we
476 may acquire information that changes the value of the
477 sdata_symbolic_operand predicate. */
478 /* But don't delay for function pointers. Loading a function address
479 actually loads the address of the descriptor not the function.
480 If we represent these as SYMBOL_REFs, then they get cse'd with
481 calls, and we end up with calls to the descriptor address instead of
482 calls to the function address. Functions are not candidates for
484 if (rtx_equal_function_value_matters
485 && ! (GET_CODE (operands[1]) == SYMBOL_REF
486 && SYMBOL_REF_FLAG (operands[1])))
487 emit_insn (gen_movdi_symbolic (operands[0], operands[1], gen_reg_rtx (DImode)));
489 ia64_expand_load_address (operands[0], operands[1], NULL_RTX);
494 ;; Errata 72 workaround.
497 (match_operator 2 "predicate_operator"
498 [(match_operand:BI 3 "register_operand" "c,c,c,c,c,c,c,c,c,c,c,c")
500 (set (match_operand:DI 0 "register_operand"
501 "=r,r,r, r,*f,*f, r,*b, r,*e, r,*d")
502 (match_operand:DI 1 "nonmemory_operand"
503 "rO,J,i,*f,rO,*f,*b,rO,*e,rK,*d,rK")))]
504 "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
507 static const char * const alt[] = {
508 \"(%J2) mov %0 = %r1\",
509 \"(%J2) addl %0 = %1, r0\",
510 \"(%J2) movl %0 = %1\",
511 \"(%J2) getf.sig %0 = %1\",
512 \"(%J2) setf.sig %0 = %r1\",
513 \"(%J2) mov %0 = %1\",
514 \"(%J2) mov %0 = %1\",
515 \"(%J2) mov %0 = %r1\",
516 \"(%J2) mov %0 = %1\",
517 \"(%J2) mov %0 = %1\",
518 \"(%J2) mov %0 = %1\",
519 \"(%J2) mov %0 = %1\"
522 /* We use 'i' for alternative 2 despite possible PIC problems.
524 If we define LEGITIMATE_CONSTANT_P such that symbols are not
525 allowed, then the compiler dumps the data into constant memory
526 instead of letting us read the values from the GOT. Similarly
527 if we use 'n' instead of 'i'.
529 Instead, we allow such insns through reload and then split them
530 afterward (even without optimization). Therefore, we should
531 never get so far with a symbolic operand. */
533 if (which_alternative == 2 && ! TARGET_NO_PIC
534 && symbolic_operand (operands[1], VOIDmode))
537 return alt[which_alternative];
539 [(set_attr "itanium_class" "ialu,ialu,long_i,frfr,tofr,fmisc,frbr,tobr,frar_i,toar_i,frar_m,toar_m")
540 (set_attr "predicable" "no")])
542 ;; This is used during early compilation to delay the decision on
543 ;; how to refer to a variable as long as possible. This is especially
544 ;; important between initial rtl generation and optimization for
545 ;; deferred functions, since we may acquire additional information
546 ;; on the variables used in the meantime.
548 ;; ??? This causes us to lose REG_LABEL notes, because the insn splitter
549 ;; does not attempt to preserve any REG_NOTES on the input instruction.
551 (define_insn_and_split "movdi_symbolic"
552 [(set (match_operand:DI 0 "register_operand" "=r")
553 (match_operand:DI 1 "symbolic_operand" "s"))
554 (clobber (match_operand:DI 2 "register_operand" "+r"))
560 "ia64_expand_load_address (operands[0], operands[1], operands[2]); DONE;")
562 (define_insn "*movdi_internal_astep"
563 [(set (match_operand:DI 0 "destination_operand"
564 "=r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c")
565 (match_operand:DI 1 "move_operand"
566 "rO,J,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))]
567 "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
570 static const char * const alt[] = {
572 \"addl %0 = %1, r0\",
574 \"ld8%O1 %0 = %1%P1\",
575 \"st8%Q0 %0 = %r1%P0\",
576 \"getf.sig %0 = %1\",
577 \"setf.sig %0 = %r1\",
591 if (which_alternative == 2 && ! TARGET_NO_PIC
592 && symbolic_operand (operands[1], VOIDmode))
595 return alt[which_alternative];
597 [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")
598 (set_attr "predicable" "no")])
600 (define_insn "*movdi_internal"
601 [(set (match_operand:DI 0 "destination_operand"
602 "=r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c")
603 (match_operand:DI 1 "move_operand"
604 "rO,J,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))]
605 "! TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
608 static const char * const alt[] = {
610 \"%,addl %0 = %1, r0\",
612 \"%,ld8%O1 %0 = %1%P1\",
613 \"%,st8%Q0 %0 = %r1%P0\",
614 \"%,getf.sig %0 = %1\",
615 \"%,setf.sig %0 = %r1\",
617 \"%,ldf8 %0 = %1%P1\",
618 \"%,stf8 %0 = %1%P0\",
629 if (which_alternative == 2 && ! TARGET_NO_PIC
630 && symbolic_operand (operands[1], VOIDmode))
633 return alt[which_alternative];
635 [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")])
638 [(set (match_operand:DI 0 "register_operand" "")
639 (match_operand:DI 1 "symbolic_operand" ""))]
640 "reload_completed && ! TARGET_NO_PIC"
644 ia64_expand_load_address (operands[0], operands[1], NULL_RTX);
648 (define_expand "load_fptr"
650 (plus:DI (reg:DI 1) (match_operand:DI 1 "function_operand" "")))
651 (set (match_operand:DI 0 "register_operand" "") (match_dup 3))]
655 operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode);
656 operands[3] = gen_rtx_MEM (DImode, operands[2]);
657 RTX_UNCHANGING_P (operands[3]) = 1;
660 (define_insn "*load_fptr_internal1"
661 [(set (match_operand:DI 0 "register_operand" "=r")
662 (plus:DI (reg:DI 1) (match_operand:DI 1 "function_operand" "s")))]
664 "addl %0 = @ltoff(@fptr(%1)), gp"
665 [(set_attr "itanium_class" "ialu")])
667 (define_insn "load_gprel"
668 [(set (match_operand:DI 0 "register_operand" "=r")
669 (plus:DI (reg:DI 1) (match_operand:DI 1 "sdata_symbolic_operand" "s")))]
671 "addl %0 = @gprel(%1), gp"
672 [(set_attr "itanium_class" "ialu")])
674 (define_insn "gprel64_offset"
675 [(set (match_operand:DI 0 "register_operand" "=r")
676 (minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))]
678 "movl %0 = @gprel(%1)"
679 [(set_attr "itanium_class" "long_i")])
681 (define_expand "load_gprel64"
683 (minus:DI (match_operand:DI 1 "symbolic_operand" "") (match_dup 3)))
684 (set (match_operand:DI 0 "register_operand" "")
685 (plus:DI (match_dup 3) (match_dup 2)))]
689 operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode);
690 operands[3] = pic_offset_table_rtx;
693 (define_expand "load_symptr"
694 [(set (match_operand:DI 2 "register_operand" "")
695 (plus:DI (match_dup 4) (match_operand:DI 1 "got_symbolic_operand" "")))
696 (set (match_operand:DI 0 "register_operand" "") (match_dup 3))]
700 operands[3] = gen_rtx_MEM (DImode, operands[2]);
701 operands[4] = pic_offset_table_rtx;
702 RTX_UNCHANGING_P (operands[3]) = 1;
705 (define_insn "*load_symptr_internal1"
706 [(set (match_operand:DI 0 "register_operand" "=r")
707 (plus:DI (reg:DI 1) (match_operand:DI 1 "got_symbolic_operand" "s")))]
709 "addl %0 = @ltoff(%1), gp"
710 [(set_attr "itanium_class" "ialu")])
712 ;; With no offsettable memory references, we've got to have a scratch
713 ;; around to play with the second word.
714 (define_expand "movti"
715 [(parallel [(set (match_operand:TI 0 "general_operand" "")
716 (match_operand:TI 1 "general_operand" ""))
717 (clobber (match_scratch:DI 2 ""))])]
721 if (! reload_in_progress && ! reload_completed
722 && ! ia64_move_ok (operands[0], operands[1]))
723 operands[1] = force_reg (TImode, operands[1]);
726 (define_insn_and_split "*movti_internal"
727 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m")
728 (match_operand:TI 1 "general_operand" "ri,m,r"))
729 (clobber (match_scratch:DI 2 "=X,&r,&r"))]
730 "ia64_move_ok (operands[0], operands[1])"
736 rtx adj1, adj2, in[2], out[2];
739 adj1 = ia64_split_timode (in, operands[1], operands[2]);
740 adj2 = ia64_split_timode (out, operands[0], operands[2]);
743 if (reg_overlap_mentioned_p (out[0], in[1]))
745 if (reg_overlap_mentioned_p (out[1], in[0]))
756 emit_insn (gen_rtx_SET (VOIDmode, out[first], in[first]));
757 emit_insn (gen_rtx_SET (VOIDmode, out[!first], in[!first]));
760 [(set_attr "itanium_class" "unknown")
761 (set_attr "predicable" "no")])
763 ;; ??? SSA creates these. Can't allow memories since we don't have
764 ;; the scratch register. Fortunately combine will know how to add
765 ;; the clobber and scratch.
766 (define_insn_and_split "*movti_internal_reg"
767 [(set (match_operand:TI 0 "register_operand" "=r")
768 (match_operand:TI 1 "nonmemory_operand" "ri"))]
778 ia64_split_timode (in, operands[1], NULL_RTX);
779 ia64_split_timode (out, operands[0], NULL_RTX);
782 if (reg_overlap_mentioned_p (out[0], in[1]))
784 if (reg_overlap_mentioned_p (out[1], in[0]))
789 emit_insn (gen_rtx_SET (VOIDmode, out[first], in[first]));
790 emit_insn (gen_rtx_SET (VOIDmode, out[!first], in[!first]));
793 [(set_attr "itanium_class" "unknown")
794 (set_attr "predicable" "no")])
796 (define_expand "reload_inti"
797 [(parallel [(set (match_operand:TI 0 "register_operand" "=r")
798 (match_operand:TI 1 "" "m"))
799 (clobber (match_operand:TI 2 "register_operand" "=&r"))])]
803 unsigned int s_regno = REGNO (operands[2]);
804 if (s_regno == REGNO (operands[0]))
806 operands[2] = gen_rtx_REG (DImode, s_regno);
809 (define_expand "reload_outti"
810 [(parallel [(set (match_operand:TI 0 "" "=m")
811 (match_operand:TI 1 "register_operand" "r"))
812 (clobber (match_operand:TI 2 "register_operand" "=&r"))])]
816 unsigned int s_regno = REGNO (operands[2]);
817 if (s_regno == REGNO (operands[1]))
819 operands[2] = gen_rtx_REG (DImode, s_regno);
822 ;; Floating Point Moves
824 ;; Note - Patterns for SF mode moves are compulsory, but
825 ;; patterns for DF are optional, as GCC can synthesise them.
827 (define_expand "movsf"
828 [(set (match_operand:SF 0 "general_operand" "")
829 (match_operand:SF 1 "general_operand" ""))]
833 if (! reload_in_progress && ! reload_completed
834 && ! ia64_move_ok (operands[0], operands[1]))
835 operands[1] = force_reg (SFmode, operands[1]);
838 ;; Errata 72 workaround.
839 (define_insn "*movsfcc_astep"
841 (match_operator 2 "predicate_operator"
842 [(match_operand:BI 3 "register_operand" "c,c,c,c")
844 (set (match_operand:SF 0 "register_operand" "=f,*r, f,*r")
845 (match_operand:SF 1 "nonmemory_operand" "fG,fG,*r,*r")))]
846 "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
849 (%J2) getf.s %0 = %F1
852 [(set_attr "itanium_class" "fmisc,frfr,tofr,ialu")
853 (set_attr "predicable" "no")])
855 (define_insn "*movsf_internal_astep"
856 [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
857 (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
858 "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
868 [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")
869 (set_attr "predicable" "no")])
871 (define_insn "*movsf_internal"
872 [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
873 (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
874 "! TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
884 [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])
886 (define_expand "movdf"
887 [(set (match_operand:DF 0 "general_operand" "")
888 (match_operand:DF 1 "general_operand" ""))]
892 if (! reload_in_progress && ! reload_completed
893 && ! ia64_move_ok (operands[0], operands[1]))
894 operands[1] = force_reg (DFmode, operands[1]);
897 ;; Errata 72 workaround.
898 (define_insn "*movdfcc_astep"
900 (match_operator 2 "predicate_operator"
901 [(match_operand:BI 3 "register_operand" "c,c,c,c")
903 (set (match_operand:DF 0 "register_operand" "=f,*r, f,*r")
904 (match_operand:DF 1 "nonmemory_operand" "fG,fG,*r,*r")))]
905 "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
908 (%J2) getf.d %0 = %F1
911 [(set_attr "itanium_class" "fmisc,frfr,tofr,ialu")
912 (set_attr "predicable" "no")])
914 (define_insn "*movdf_internal_astep"
915 [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
916 (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
917 "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
927 [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")
928 (set_attr "predicable" "no")])
930 (define_insn "*movdf_internal"
931 [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
932 (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
933 "! TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
943 [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])
945 ;; With no offsettable memory references, we've got to have a scratch
946 ;; around to play with the second word if the variable winds up in GRs.
947 (define_expand "movtf"
948 [(set (match_operand:TF 0 "general_operand" "")
949 (match_operand:TF 1 "general_operand" ""))]
953 /* We must support TFmode loads into general registers for stdarg/vararg
954 and unprototyped calls. We split them into DImode loads for convenience.
955 We don't need TFmode stores from general regs, because a stdarg/vararg
956 routine does a block store to memory of unnamed arguments. */
957 if (GET_CODE (operands[0]) == REG
958 && GR_REGNO_P (REGNO (operands[0])))
960 /* We're hoping to transform everything that deals with TFmode
961 quantities and GR registers early in the compiler. */
965 /* Struct to register can just use TImode instead. */
966 if ((GET_CODE (operands[1]) == SUBREG
967 && GET_MODE (SUBREG_REG (operands[1])) == TImode)
968 || (GET_CODE (operands[1]) == REG
969 && GR_REGNO_P (REGNO (operands[1]))))
971 emit_move_insn (gen_rtx_REG (TImode, REGNO (operands[0])),
972 SUBREG_REG (operands[1]));
976 if (GET_CODE (operands[1]) == CONST_DOUBLE)
978 emit_move_insn (gen_rtx_REG (DImode, REGNO (operands[0])),
979 operand_subword (operands[1], 0, 0, DImode));
980 emit_move_insn (gen_rtx_REG (DImode, REGNO (operands[0]) + 1),
981 operand_subword (operands[1], 1, 0, DImode));
985 /* If the quantity is in a register not known to be GR, spill it. */
986 if (register_operand (operands[1], TFmode))
987 operands[1] = spill_tfmode_operand (operands[1], 1);
989 if (GET_CODE (operands[1]) == MEM)
993 out[WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[0]));
994 out[!WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[0])+1);
996 emit_move_insn (out[0], change_address (operands[1], DImode, NULL));
997 emit_move_insn (out[1],
998 change_address (operands[1], DImode,
999 plus_constant (XEXP (operands[1], 0),
1007 if (! reload_in_progress && ! reload_completed)
1009 operands[0] = spill_tfmode_operand (operands[0], 0);
1010 operands[1] = spill_tfmode_operand (operands[1], 0);
1012 if (! ia64_move_ok (operands[0], operands[1]))
1013 operands[1] = force_reg (TFmode, operands[1]);
1017 ;; ??? There's no easy way to mind volatile acquire/release semantics.
1019 ;; Errata 72 workaround.
1020 (define_insn "*movtfcc_astep"
1022 (match_operator 2 "predicate_operator"
1023 [(match_operand:BI 3 "register_operand" "c")
1025 (set (match_operand:TF 0 "register_operand" "=f")
1026 (match_operand:TF 1 "nonmemory_operand" "fG")))]
1027 "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
1028 "(%J2) mov %0 = %F1"
1029 [(set_attr "itanium_class" "fmisc")
1030 (set_attr "predicable" "no")])
1032 (define_insn "*movtf_internal_astep"
1033 [(set (match_operand:TF 0 "destination_tfmode_operand" "=f,f, m")
1034 (match_operand:TF 1 "general_tfmode_operand" "fG,m,fG"))]
1035 "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
1040 [(set_attr "itanium_class" "fmisc,fld,stf")
1041 (set_attr "predicable" "no")])
1043 (define_insn "*movtf_internal"
1044 [(set (match_operand:TF 0 "destination_tfmode_operand" "=f,f, m")
1045 (match_operand:TF 1 "general_tfmode_operand" "fG,m,fG"))]
1046 "! TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
1051 [(set_attr "itanium_class" "fmisc,fld,stf")])
1053 ;; ::::::::::::::::::::
1057 ;; ::::::::::::::::::::
1059 ;; Signed conversions from a smaller integer to a larger integer
1061 (define_insn "extendqidi2"
1062 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1063 (sign_extend:DI (match_operand:QI 1 "gr_register_operand" "r")))]
1066 [(set_attr "itanium_class" "xtd")])
1068 (define_insn "extendhidi2"
1069 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1070 (sign_extend:DI (match_operand:HI 1 "gr_register_operand" "r")))]
1073 [(set_attr "itanium_class" "xtd")])
1075 (define_insn "extendsidi2"
1076 [(set (match_operand:DI 0 "grfr_register_operand" "=r,?f")
1077 (sign_extend:DI (match_operand:SI 1 "grfr_register_operand" "r,f")))]
1081 fsxt.r %0 = %1, %1%B0"
1082 [(set_attr "itanium_class" "xtd,fmisc")])
1084 ;; Unsigned conversions from a smaller integer to a larger integer
1086 (define_insn "zero_extendqidi2"
1087 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
1088 (zero_extend:DI (match_operand:QI 1 "gr_nonimmediate_operand" "r,m")))]
1093 [(set_attr "itanium_class" "xtd,ld")])
1095 (define_insn "zero_extendhidi2"
1096 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
1097 (zero_extend:DI (match_operand:HI 1 "gr_nonimmediate_operand" "r,m")))]
1102 [(set_attr "itanium_class" "xtd,ld")])
1104 (define_insn "zero_extendsidi2"
1105 [(set (match_operand:DI 0 "grfr_register_operand" "=r,r,?f")
1107 (match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))]
1112 fmix.r %0 = f0, %1%B0"
1113 [(set_attr "itanium_class" "xtd,ld,fmisc")])
1115 ;; Convert between floating point types of different sizes.
1117 ;; ??? Optimization opportunity here. Get rid of the insn altogether
1118 ;; when we can. Should probably use a scheme like has been proposed
1119 ;; for ia32 in dealing with operands that match unary operators. This
1120 ;; would let combine merge the thing into adjacent insns.
1122 (define_insn_and_split "extendsfdf2"
1123 [(set (match_operand:DF 0 "grfr_nonimmediate_operand" "=f,f,f,f,m,*r")
1125 (match_operand:SF 1 "grfr_nonimmediate_operand" "0,f,m,*r,f,f")))]
1135 [(set (match_dup 0) (float_extend:DF (match_dup 1)))]
1138 if (true_regnum (operands[0]) == true_regnum (operands[1]))
1140 emit_insn (gen_movdi (pic_offset_table_rtx, pic_offset_table_rtx));
1144 [(set_attr "itanium_class" "unknown,fmisc,fld,tofr,stf,frfr")])
1146 (define_insn_and_split "extendsftf2"
1147 [(set (match_operand:TF 0 "fr_nonimmediate_operand" "=f,f,f,f,Q")
1149 (match_operand:SF 1 "grfr_nonimmediate_operand" "0,f,Q,*r,f")))]
1158 [(set (match_dup 0) (float_extend:TF (match_dup 1)))]
1161 if (true_regnum (operands[0]) == true_regnum (operands[1]))
1163 emit_insn (gen_movdi (pic_offset_table_rtx, pic_offset_table_rtx));
1167 [(set_attr "itanium_class" "unknown,fmisc,fld,frfr,stf")])
1169 (define_insn_and_split "extenddftf2"
1170 [(set (match_operand:TF 0 "fr_nonimmediate_operand" "=f,f,f,f,Q")
1172 (match_operand:DF 1 "grfr_nonimmediate_operand" "0,f,Q,*r,f")))]
1181 [(set (match_dup 0) (float_extend:TF (match_dup 1)))]
1184 if (true_regnum (operands[0]) == true_regnum (operands[1]))
1186 emit_insn (gen_movdi (pic_offset_table_rtx, pic_offset_table_rtx));
1190 [(set_attr "itanium_class" "unknown,fmisc,fld,frfr,stf")])
1192 (define_insn "truncdfsf2"
1193 [(set (match_operand:SF 0 "fr_register_operand" "=f")
1194 (float_truncate:SF (match_operand:DF 1 "fr_register_operand" "f")))]
1196 "fnorm.s %0 = %1%B0"
1197 [(set_attr "itanium_class" "fmac")])
1199 (define_insn "trunctfsf2"
1200 [(set (match_operand:SF 0 "fr_register_operand" "=f")
1201 (float_truncate:SF (match_operand:TF 1 "fr_register_operand" "f")))]
1203 "fnorm.s %0 = %1%B0"
1204 [(set_attr "itanium_class" "fmac")])
1206 (define_insn "trunctfdf2"
1207 [(set (match_operand:DF 0 "fr_register_operand" "=f")
1208 (float_truncate:DF (match_operand:TF 1 "fr_register_operand" "f")))]
1210 "fnorm.d %0 = %1%B0"
1211 [(set_attr "itanium_class" "fmac")])
1213 ;; Convert between signed integer types and floating point.
1215 (define_insn "floatditf2"
1216 [(set (match_operand:TF 0 "fr_register_operand" "=f")
1217 (float:TF (match_operand:DI 1 "fr_register_operand" "f")))]
1220 [(set_attr "itanium_class" "fcvtfx")])
1222 (define_insn "fix_truncsfdi2"
1223 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1224 (fix:DI (match_operand:SF 1 "fr_register_operand" "f")))]
1226 "fcvt.fx.trunc %0 = %1%B0"
1227 [(set_attr "itanium_class" "fcvtfx")])
1229 (define_insn "fix_truncdfdi2"
1230 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1231 (fix:DI (match_operand:DF 1 "fr_register_operand" "f")))]
1233 "fcvt.fx.trunc %0 = %1%B0"
1234 [(set_attr "itanium_class" "fcvtfx")])
1236 (define_insn "fix_trunctfdi2"
1237 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1238 (fix:DI (match_operand:TF 1 "fr_register_operand" "f")))]
1240 "fcvt.fx.trunc %0 = %1%B0"
1241 [(set_attr "itanium_class" "fcvtfx")])
1243 (define_insn "fix_trunctfdi2_alts"
1244 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1245 (fix:DI (match_operand:TF 1 "fr_register_operand" "f")))
1246 (use (match_operand:SI 2 "const_int_operand" ""))]
1248 "fcvt.fx.trunc.s%2 %0 = %1%B0"
1249 [(set_attr "itanium_class" "fcvtfx")])
1251 ;; Convert between unsigned integer types and floating point.
1253 (define_insn "floatunsdisf2"
1254 [(set (match_operand:SF 0 "fr_register_operand" "=f")
1255 (unsigned_float:SF (match_operand:DI 1 "fr_register_operand" "f")))]
1257 "fcvt.xuf.s %0 = %1%B0"
1258 [(set_attr "itanium_class" "fcvtfx")])
1260 (define_insn "floatunsdidf2"
1261 [(set (match_operand:DF 0 "fr_register_operand" "=f")
1262 (unsigned_float:DF (match_operand:DI 1 "fr_register_operand" "f")))]
1264 "fcvt.xuf.d %0 = %1%B0"
1265 [(set_attr "itanium_class" "fcvtfx")])
1267 (define_insn "floatunsditf2"
1268 [(set (match_operand:TF 0 "fr_register_operand" "=f")
1269 (unsigned_float:TF (match_operand:DI 1 "fr_register_operand" "f")))]
1271 "fcvt.xuf %0 = %1%B0"
1272 [(set_attr "itanium_class" "fcvtfx")])
1274 (define_insn "fixuns_truncsfdi2"
1275 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1276 (unsigned_fix:DI (match_operand:SF 1 "fr_register_operand" "f")))]
1278 "fcvt.fxu.trunc %0 = %1%B0"
1279 [(set_attr "itanium_class" "fcvtfx")])
1281 (define_insn "fixuns_truncdfdi2"
1282 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1283 (unsigned_fix:DI (match_operand:DF 1 "fr_register_operand" "f")))]
1285 "fcvt.fxu.trunc %0 = %1%B0"
1286 [(set_attr "itanium_class" "fcvtfx")])
1288 (define_insn "fixuns_trunctfdi2"
1289 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1290 (unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f")))]
1292 "fcvt.fxu.trunc %0 = %1%B0"
1293 [(set_attr "itanium_class" "fcvtfx")])
1295 (define_insn "fixuns_trunctfdi2_alts"
1296 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1297 (unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f")))
1298 (use (match_operand:SI 2 "const_int_operand" ""))]
1300 "fcvt.fxu.trunc.s%2 %0 = %1%B0"
1301 [(set_attr "itanium_class" "fcvtfx")])
1303 ;; ::::::::::::::::::::
1305 ;; :: Bit field extraction
1307 ;; ::::::::::::::::::::
1310 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1311 (sign_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
1312 (match_operand:DI 2 "const_int_operand" "n")
1313 (match_operand:DI 3 "const_int_operand" "n")))]
1315 "extr %0 = %1, %3, %2"
1316 [(set_attr "itanium_class" "ishf")])
1318 (define_insn "extzv"
1319 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1320 (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
1321 (match_operand:DI 2 "const_int_operand" "n")
1322 (match_operand:DI 3 "const_int_operand" "n")))]
1324 "extr.u %0 = %1, %3, %2"
1325 [(set_attr "itanium_class" "ishf")])
1327 ;; Insert a bit field.
1328 ;; Can have 3 operands, source1 (inserter), source2 (insertee), dest.
1329 ;; Source1 can be 0 or -1.
1330 ;; Source2 can be 0.
1332 ;; ??? Actual dep instruction is more powerful than what these insv
1333 ;; patterns support. Unfortunately, combine is unable to create patterns
1334 ;; where source2 != dest.
1336 (define_expand "insv"
1337 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "")
1338 (match_operand:DI 1 "const_int_operand" "")
1339 (match_operand:DI 2 "const_int_operand" ""))
1340 (match_operand:DI 3 "nonmemory_operand" ""))]
1344 int width = INTVAL (operands[1]);
1345 int shift = INTVAL (operands[2]);
1347 /* If operand[3] is a constant, and isn't 0 or -1, then load it into a
1349 if (! register_operand (operands[3], DImode)
1350 && operands[3] != const0_rtx && operands[3] != constm1_rtx)
1351 operands[3] = force_reg (DImode, operands[3]);
1353 /* If this is a single dep instruction, we have nothing to do. */
1354 if (! ((register_operand (operands[3], DImode) && width <= 16)
1355 || operands[3] == const0_rtx || operands[3] == constm1_rtx))
1357 /* Check for cases that can be implemented with a mix instruction. */
1358 if (width == 32 && shift == 0)
1360 /* Directly generating the mix4left instruction confuses
1361 optimize_bit_field in function.c. Since this is performing
1362 a useful optimization, we defer generation of the complicated
1363 mix4left RTL to the first splitting phase. */
1364 rtx tmp = gen_reg_rtx (DImode);
1365 emit_insn (gen_shift_mix4left (operands[0], operands[3], tmp));
1368 else if (width == 32 && shift == 32)
1370 emit_insn (gen_mix4right (operands[0], operands[3]));
1374 /* We could handle remaining cases by emitting multiple dep
1377 If we need more than two dep instructions then we lose. A 6
1378 insn sequence mov mask1,mov mask2,shl;;and,and;;or is better than
1379 mov;;dep,shr;;dep,shr;;dep. The former can be executed in 3 cycles,
1380 the latter is 6 cycles on an Itanium (TM) processor, because there is
1381 only one function unit that can execute dep and shr immed.
1383 If we only need two dep instruction, then we still lose.
1384 mov;;dep,shr;;dep is still 4 cycles. Even if we optimize away
1385 the unnecessary mov, this is still undesirable because it will be
1386 hard to optimize, and it creates unnecessary pressure on the I0
1392 /* This code may be useful for other IA-64 processors, so we leave it in
1398 emit_insn (gen_insv (operands[0], GEN_INT (16), GEN_INT (shift),
1402 tmp = gen_reg_rtx (DImode);
1403 emit_insn (gen_lshrdi3 (tmp, operands[3], GEN_INT (16)));
1406 operands[1] = GEN_INT (width);
1407 operands[2] = GEN_INT (shift);
1412 (define_insn "*insv_internal"
1413 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1414 (match_operand:DI 1 "const_int_operand" "n")
1415 (match_operand:DI 2 "const_int_operand" "n"))
1416 (match_operand:DI 3 "nonmemory_operand" "rP"))]
1417 "(gr_register_operand (operands[3], DImode) && INTVAL (operands[1]) <= 16)
1418 || operands[3] == const0_rtx || operands[3] == constm1_rtx"
1419 "dep %0 = %3, %0, %2, %1"
1420 [(set_attr "itanium_class" "ishf")])
1422 ;; Combine doesn't like to create bitfield insertions into zero.
1423 (define_insn "*depz_internal"
1424 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1425 (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r")
1426 (match_operand:DI 2 "const_int_operand" "n"))
1427 (match_operand:DI 3 "const_int_operand" "n")))]
1428 "CONST_OK_FOR_M (INTVAL (operands[2]))
1429 && ia64_depz_field_mask (operands[3], operands[2]) > 0"
1432 operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2]));
1433 return \"%,dep.z %0 = %1, %2, %3\";
1435 [(set_attr "itanium_class" "ishf")])
1437 (define_insn "shift_mix4left"
1438 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1439 (const_int 32) (const_int 0))
1440 (match_operand:DI 1 "gr_register_operand" "r"))
1441 (clobber (match_operand:DI 2 "gr_register_operand" "=r"))]
1444 [(set_attr "itanium_class" "unknown")])
1447 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "")
1448 (const_int 32) (const_int 0))
1449 (match_operand:DI 1 "register_operand" ""))
1450 (clobber (match_operand:DI 2 "register_operand" ""))]
1452 [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32)))
1453 (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0))
1454 (lshiftrt:DI (match_dup 3) (const_int 32)))]
1455 "operands[3] = operands[2];")
1458 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "")
1459 (const_int 32) (const_int 0))
1460 (match_operand:DI 1 "register_operand" ""))
1461 (clobber (match_operand:DI 2 "register_operand" ""))]
1462 "! reload_completed"
1463 [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32)))
1464 (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0))
1465 (lshiftrt:DI (match_dup 3) (const_int 32)))]
1466 "operands[3] = operands[2];")
1468 (define_insn "*mix4left"
1469 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1470 (const_int 32) (const_int 0))
1471 (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r")
1474 "mix4.l %0 = %0, %r1"
1475 [(set_attr "itanium_class" "mmshf")])
1477 (define_insn "mix4right"
1478 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1479 (const_int 32) (const_int 32))
1480 (match_operand:DI 1 "gr_reg_or_0_operand" "rO"))]
1482 "mix4.r %0 = %r1, %0"
1483 [(set_attr "itanium_class" "mmshf")])
1485 ;; This is used by the rotrsi3 pattern.
1487 (define_insn "*mix4right_3op"
1488 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1489 (ior:DI (zero_extend:DI (match_operand:SI 1 "gr_register_operand" "r"))
1490 (ashift:DI (zero_extend:DI
1491 (match_operand:SI 2 "gr_register_operand" "r"))
1494 "mix4.r %0 = %2, %1"
1495 [(set_attr "itanium_class" "mmshf")])
1498 ;; ::::::::::::::::::::
1500 ;; :: 1 bit Integer arithmetic
1502 ;; ::::::::::::::::::::
1504 (define_insn_and_split "andbi3"
1505 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1506 (and:BI (match_operand:BI 1 "register_operand" "%0,0,r")
1507 (match_operand:BI 2 "register_operand" "c,r,r")))]
1511 tbit.nz.and.orcm %0, %I0 = %2, 0
1514 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1515 && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
1516 [(cond_exec (eq (match_dup 2) (const_int 0))
1517 (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0))
1520 [(set_attr "itanium_class" "unknown,tbit,ilog")])
1522 (define_insn_and_split "*andcmbi3"
1523 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1524 (and:BI (not:BI (match_operand:BI 1 "register_operand" "c,r,r"))
1525 (match_operand:BI 2 "register_operand" "0,0,r")))]
1529 tbit.z.and.orcm %0, %I0 = %2, 0
1532 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1533 && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
1534 [(cond_exec (ne (match_dup 1) (const_int 0))
1535 (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0))
1538 [(set_attr "itanium_class" "unknown,tbit,ilog")])
1540 (define_insn_and_split "iorbi3"
1541 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1542 (ior:BI (match_operand:BI 1 "register_operand" "%0,0,r")
1543 (match_operand:BI 2 "register_operand" "c,r,r")))]
1547 tbit.nz.or.andcm %0, %I0 = %2, 0
1550 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1551 && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
1552 [(cond_exec (ne (match_dup 2) (const_int 0))
1553 (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0))
1556 [(set_attr "itanium_class" "unknown,tbit,ilog")])
1558 (define_insn_and_split "*iorcmbi3"
1559 [(set (match_operand:BI 0 "register_operand" "=c,c")
1560 (ior:BI (not:BI (match_operand:BI 1 "register_operand" "c,r"))
1561 (match_operand:BI 2 "register_operand" "0,0")))]
1565 tbit.z.or.andcm %0, %I0 = %2, 0"
1567 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1568 && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
1569 [(cond_exec (eq (match_dup 1) (const_int 0))
1570 (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0))
1573 [(set_attr "itanium_class" "unknown,tbit")])
1575 (define_insn "one_cmplbi2"
1576 [(set (match_operand:BI 0 "register_operand" "=c,r,c,&c")
1577 (not:BI (match_operand:BI 1 "register_operand" "r,r,0,c")))
1578 (clobber (match_scratch:BI 2 "=X,X,c,X"))]
1581 tbit.z %0, %I0 = %1, 0
1585 [(set_attr "itanium_class" "tbit,ilog,unknown,unknown")])
1588 [(set (match_operand:BI 0 "register_operand" "")
1589 (not:BI (match_operand:BI 1 "register_operand" "")))
1590 (clobber (match_scratch:BI 2 ""))]
1592 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1593 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))
1594 && rtx_equal_p (operands[0], operands[1])"
1595 [(set (match_dup 4) (match_dup 3))
1596 (set (match_dup 0) (const_int 1))
1597 (cond_exec (ne (match_dup 2) (const_int 0))
1598 (set (match_dup 0) (const_int 0)))
1599 (set (match_dup 0) (unspec:BI [(match_dup 0)] 7))]
1600 "operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1]));
1601 operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));")
1604 [(set (match_operand:BI 0 "register_operand" "")
1605 (not:BI (match_operand:BI 1 "register_operand" "")))
1606 (clobber (match_scratch:BI 2 ""))]
1608 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1609 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))
1610 && ! rtx_equal_p (operands[0], operands[1])"
1611 [(cond_exec (ne (match_dup 1) (const_int 0))
1612 (set (match_dup 0) (const_int 0)))
1613 (cond_exec (eq (match_dup 1) (const_int 0))
1614 (set (match_dup 0) (const_int 1)))
1615 (set (match_dup 0) (unspec:BI [(match_dup 0)] 7))]
1618 (define_insn "*cmpsi_and_0"
1619 [(set (match_operand:BI 0 "register_operand" "=c")
1620 (and:BI (match_operator:BI 4 "predicate_operator"
1621 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1622 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])
1623 (match_operand:BI 1 "register_operand" "0")))]
1625 "cmp4.%C4.and.orcm %0, %I0 = %3, %r2"
1626 [(set_attr "itanium_class" "icmp")])
1628 (define_insn "*cmpsi_and_1"
1629 [(set (match_operand:BI 0 "register_operand" "=c")
1630 (and:BI (match_operator:BI 3 "signed_inequality_operator"
1631 [(match_operand:SI 2 "gr_register_operand" "r")
1633 (match_operand:BI 1 "register_operand" "0")))]
1635 "cmp4.%C3.and.orcm %0, %I0 = r0, %2"
1636 [(set_attr "itanium_class" "icmp")])
1638 (define_insn "*cmpsi_andnot_0"
1639 [(set (match_operand:BI 0 "register_operand" "=c")
1640 (and:BI (not:BI (match_operator:BI 4 "predicate_operator"
1641 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1642 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))
1643 (match_operand:BI 1 "register_operand" "0")))]
1645 "cmp4.%C4.or.andcm %I0, %0 = %3, %r2"
1646 [(set_attr "itanium_class" "icmp")])
1648 (define_insn "*cmpsi_andnot_1"
1649 [(set (match_operand:BI 0 "register_operand" "=c")
1650 (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1651 [(match_operand:SI 2 "gr_register_operand" "r")
1653 (match_operand:BI 1 "register_operand" "0")))]
1655 "cmp4.%C3.or.andcm %I0, %0 = r0, %2"
1656 [(set_attr "itanium_class" "icmp")])
1658 (define_insn "*cmpdi_and_0"
1659 [(set (match_operand:BI 0 "register_operand" "=c")
1660 (and:BI (match_operator:BI 4 "predicate_operator"
1661 [(match_operand:DI 2 "gr_register_operand" "r")
1662 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])
1663 (match_operand:BI 1 "register_operand" "0")))]
1665 "cmp.%C4.and.orcm %0, %I0 = %3, %2"
1666 [(set_attr "itanium_class" "icmp")])
1668 (define_insn "*cmpdi_and_1"
1669 [(set (match_operand:BI 0 "register_operand" "=c")
1670 (and:BI (match_operator:BI 3 "signed_inequality_operator"
1671 [(match_operand:DI 2 "gr_register_operand" "r")
1673 (match_operand:BI 1 "register_operand" "0")))]
1675 "cmp.%C3.and.orcm %0, %I0 = r0, %2"
1676 [(set_attr "itanium_class" "icmp")])
1678 (define_insn "*cmpdi_andnot_0"
1679 [(set (match_operand:BI 0 "register_operand" "=c")
1680 (and:BI (not:BI (match_operator:BI 4 "predicate_operator"
1681 [(match_operand:DI 2 "gr_register_operand" "r")
1682 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))
1683 (match_operand:BI 1 "register_operand" "0")))]
1685 "cmp.%C4.or.andcm %I0, %0 = %3, %2"
1686 [(set_attr "itanium_class" "icmp")])
1688 (define_insn "*cmpdi_andnot_1"
1689 [(set (match_operand:BI 0 "register_operand" "=c")
1690 (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1691 [(match_operand:DI 2 "gr_register_operand" "r")
1693 (match_operand:BI 1 "register_operand" "0")))]
1695 "cmp.%C3.or.andcm %I0, %0 = r0, %2"
1696 [(set_attr "itanium_class" "icmp")])
1698 (define_insn "*tbit_and_0"
1699 [(set (match_operand:BI 0 "register_operand" "=c")
1700 (and:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1703 (match_operand:BI 2 "register_operand" "0")))]
1705 "tbit.nz.and.orcm %0, %I0 = %1, 0"
1706 [(set_attr "itanium_class" "tbit")])
1708 (define_insn "*tbit_and_1"
1709 [(set (match_operand:BI 0 "register_operand" "=c")
1710 (and:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1713 (match_operand:BI 2 "register_operand" "0")))]
1715 "tbit.z.and.orcm %0, %I0 = %1, 0"
1716 [(set_attr "itanium_class" "tbit")])
1718 (define_insn "*tbit_and_2"
1719 [(set (match_operand:BI 0 "register_operand" "=c")
1720 (and:BI (ne:BI (zero_extract:DI
1721 (match_operand:DI 1 "gr_register_operand" "r")
1723 (match_operand:DI 2 "const_int_operand" "n"))
1725 (match_operand:BI 3 "register_operand" "0")))]
1727 "tbit.nz.and.orcm %0, %I0 = %1, %2"
1728 [(set_attr "itanium_class" "tbit")])
1730 (define_insn "*tbit_and_3"
1731 [(set (match_operand:BI 0 "register_operand" "=c")
1732 (and:BI (eq:BI (zero_extract:DI
1733 (match_operand:DI 1 "gr_register_operand" "r")
1735 (match_operand:DI 2 "const_int_operand" "n"))
1737 (match_operand:BI 3 "register_operand" "0")))]
1739 "tbit.z.and.orcm %0, %I0 = %1, %2"
1740 [(set_attr "itanium_class" "tbit")])
1742 (define_insn "*cmpsi_or_0"
1743 [(set (match_operand:BI 0 "register_operand" "=c")
1744 (ior:BI (match_operator:BI 4 "predicate_operator"
1745 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1746 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])
1747 (match_operand:BI 1 "register_operand" "0")))]
1749 "cmp4.%C4.or.andcm %0, %I0 = %3, %r2"
1750 [(set_attr "itanium_class" "icmp")])
1752 (define_insn "*cmpsi_or_1"
1753 [(set (match_operand:BI 0 "register_operand" "=c")
1754 (ior:BI (match_operator:BI 3 "signed_inequality_operator"
1755 [(match_operand:SI 2 "gr_register_operand" "r")
1757 (match_operand:BI 1 "register_operand" "0")))]
1759 "cmp4.%C3.or.andcm %0, %I0 = r0, %2"
1760 [(set_attr "itanium_class" "icmp")])
1762 (define_insn "*cmpsi_orcm_0"
1763 [(set (match_operand:BI 0 "register_operand" "=c")
1764 (ior:BI (not:BI (match_operator:BI 4 "predicate_operator"
1765 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1766 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))
1767 (match_operand:BI 1 "register_operand" "0")))]
1769 "cmp4.%C4.and.orcm %I0, %0 = %3, %r2"
1770 [(set_attr "itanium_class" "icmp")])
1772 (define_insn "*cmpsi_orcm_1"
1773 [(set (match_operand:BI 0 "register_operand" "=c")
1774 (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1775 [(match_operand:SI 2 "gr_register_operand" "r")
1777 (match_operand:BI 1 "register_operand" "0")))]
1779 "cmp4.%C3.and.orcm %I0, %0 = r0, %2"
1780 [(set_attr "itanium_class" "icmp")])
1782 (define_insn "*cmpdi_or_0"
1783 [(set (match_operand:BI 0 "register_operand" "=c")
1784 (ior:BI (match_operator:BI 4 "predicate_operator"
1785 [(match_operand:DI 2 "gr_register_operand" "r")
1786 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])
1787 (match_operand:BI 1 "register_operand" "0")))]
1789 "cmp.%C4.or.andcm %0, %I0 = %3, %2"
1790 [(set_attr "itanium_class" "icmp")])
1792 (define_insn "*cmpdi_or_1"
1793 [(set (match_operand:BI 0 "register_operand" "=c")
1794 (ior:BI (match_operator:BI 3 "signed_inequality_operator"
1795 [(match_operand:DI 2 "gr_register_operand" "r")
1797 (match_operand:BI 1 "register_operand" "0")))]
1799 "cmp.%C3.or.andcm %0, %I0 = r0, %2"
1800 [(set_attr "itanium_class" "icmp")])
1802 (define_insn "*cmpdi_orcm_0"
1803 [(set (match_operand:BI 0 "register_operand" "=c")
1804 (ior:BI (not:BI (match_operator:BI 4 "predicate_operator"
1805 [(match_operand:DI 2 "gr_register_operand" "r")
1806 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))
1807 (match_operand:BI 1 "register_operand" "0")))]
1809 "cmp.%C4.and.orcm %I0, %0 = %3, %2"
1810 [(set_attr "itanium_class" "icmp")])
1812 (define_insn "*cmpdi_orcm_1"
1813 [(set (match_operand:BI 0 "register_operand" "=c")
1814 (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1815 [(match_operand:DI 2 "gr_register_operand" "r")
1817 (match_operand:BI 1 "register_operand" "0")))]
1819 "cmp.%C3.and.orcm %I0, %0 = r0, %2"
1820 [(set_attr "itanium_class" "icmp")])
1822 (define_insn "*tbit_or_0"
1823 [(set (match_operand:BI 0 "register_operand" "=c")
1824 (ior:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1827 (match_operand:BI 2 "register_operand" "0")))]
1829 "tbit.nz.or.andcm %0, %I0 = %1, 0"
1830 [(set_attr "itanium_class" "tbit")])
1832 (define_insn "*tbit_or_1"
1833 [(set (match_operand:BI 0 "register_operand" "=c")
1834 (ior:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1837 (match_operand:BI 2 "register_operand" "0")))]
1839 "tbit.z.or.andcm %0, %I0 = %1, 0"
1840 [(set_attr "itanium_class" "tbit")])
1842 (define_insn "*tbit_or_2"
1843 [(set (match_operand:BI 0 "register_operand" "=c")
1844 (ior:BI (ne:BI (zero_extract:DI
1845 (match_operand:DI 1 "gr_register_operand" "r")
1847 (match_operand:DI 2 "const_int_operand" "n"))
1849 (match_operand:BI 3 "register_operand" "0")))]
1851 "tbit.nz.or.andcm %0, %I0 = %1, %2"
1852 [(set_attr "itanium_class" "tbit")])
1854 (define_insn "*tbit_or_3"
1855 [(set (match_operand:BI 0 "register_operand" "=c")
1856 (ior:BI (eq:BI (zero_extract:DI
1857 (match_operand:DI 1 "gr_register_operand" "r")
1859 (match_operand:DI 2 "const_int_operand" "n"))
1861 (match_operand:BI 3 "register_operand" "0")))]
1863 "tbit.z.or.andcm %0, %I0 = %1, %2"
1864 [(set_attr "itanium_class" "tbit")])
1866 ;; Transform test of and/or of setcc into parallel comparisons.
1869 [(set (match_operand:BI 0 "register_operand" "")
1870 (ne:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1872 (match_operand:DI 3 "register_operand" ""))
1876 (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0))
1881 [(set (match_operand:BI 0 "register_operand" "")
1882 (eq:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1884 (match_operand:DI 3 "register_operand" ""))
1888 (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0))
1890 (parallel [(set (match_dup 0) (not:BI (match_dup 0)))
1891 (clobber (scratch))])]
1895 [(set (match_operand:BI 0 "register_operand" "")
1896 (ne:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1898 (match_operand:DI 3 "register_operand" ""))
1902 (ior:BI (ne:BI (match_dup 3) (const_int 0))
1907 [(set (match_operand:BI 0 "register_operand" "")
1908 (eq:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1910 (match_operand:DI 3 "register_operand" ""))
1914 (ior:BI (ne:BI (match_dup 3) (const_int 0))
1916 (parallel [(set (match_dup 0) (not:BI (match_dup 0)))
1917 (clobber (scratch))])]
1920 ;; ??? Incredibly hackish. Either need four proper patterns with all
1921 ;; the alternatives, or rely on sched1 to split the insn and hope that
1922 ;; nothing bad happens to the comparisons in the meantime.
1924 ;; Alternately, adjust combine to allow 2->2 and 3->3 splits, assuming
1925 ;; that we're doing height reduction.
1927 ;(define_insn_and_split ""
1928 ; [(set (match_operand:BI 0 "register_operand" "=c")
1929 ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator"
1930 ; [(match_operand 2 "" "")
1931 ; (match_operand 3 "" "")])
1932 ; (match_operator:BI 4 "comparison_operator"
1933 ; [(match_operand 5 "" "")
1934 ; (match_operand 6 "" "")]))
1936 ; "flag_schedule_insns"
1939 ; [(set (match_dup 0) (and:BI (match_dup 1) (match_dup 0)))
1940 ; (set (match_dup 0) (and:BI (match_dup 4) (match_dup 0)))]
1943 ;(define_insn_and_split ""
1944 ; [(set (match_operand:BI 0 "register_operand" "=c")
1945 ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator"
1946 ; [(match_operand 2 "" "")
1947 ; (match_operand 3 "" "")])
1948 ; (match_operator:BI 4 "comparison_operator"
1949 ; [(match_operand 5 "" "")
1950 ; (match_operand 6 "" "")]))
1952 ; "flag_schedule_insns"
1955 ; [(set (match_dup 0) (ior:BI (match_dup 1) (match_dup 0)))
1956 ; (set (match_dup 0) (ior:BI (match_dup 4) (match_dup 0)))]
1960 ; [(set (match_operand:BI 0 "register_operand" "")
1961 ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator"
1962 ; [(match_operand 2 "" "")
1963 ; (match_operand 3 "" "")])
1964 ; (match_operand:BI 7 "register_operand" ""))
1965 ; (and:BI (match_operator:BI 4 "comparison_operator"
1966 ; [(match_operand 5 "" "")
1967 ; (match_operand 6 "" "")])
1968 ; (match_operand:BI 8 "register_operand" ""))))]
1970 ; [(set (match_dup 0) (and:BI (match_dup 7) (match_dup 8)))
1971 ; (set (match_dup 0) (and:BI (and:BI (match_dup 1) (match_dup 4))
1976 ; [(set (match_operand:BI 0 "register_operand" "")
1977 ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator"
1978 ; [(match_operand 2 "" "")
1979 ; (match_operand 3 "" "")])
1980 ; (match_operand:BI 7 "register_operand" ""))
1981 ; (ior:BI (match_operator:BI 4 "comparison_operator"
1982 ; [(match_operand 5 "" "")
1983 ; (match_operand 6 "" "")])
1984 ; (match_operand:BI 8 "register_operand" ""))))]
1986 ; [(set (match_dup 0) (ior:BI (match_dup 7) (match_dup 8)))
1987 ; (set (match_dup 0) (ior:BI (ior:BI (match_dup 1) (match_dup 4))
1991 ;; Try harder to avoid predicate copies by duplicating compares.
1992 ;; Note that we'll have already split the predicate copy, which
1993 ;; is kind of a pain, but oh well.
1996 [(set (match_operand:BI 0 "register_operand" "")
1997 (match_operand:BI 1 "comparison_operator" ""))
1998 (set (match_operand:CCI 2 "register_operand" "")
1999 (match_operand:CCI 3 "register_operand" ""))
2000 (set (match_operand:CCI 4 "register_operand" "")
2001 (match_operand:CCI 5 "register_operand" ""))
2002 (set (match_operand:BI 6 "register_operand" "")
2003 (unspec:BI [(match_dup 6)] 7))]
2004 "REGNO (operands[3]) == REGNO (operands[0])
2005 && REGNO (operands[4]) == REGNO (operands[0]) + 1
2006 && REGNO (operands[4]) == REGNO (operands[2]) + 1
2007 && REGNO (operands[6]) == REGNO (operands[2])"
2008 [(set (match_dup 0) (match_dup 1))
2009 (set (match_dup 6) (match_dup 7))]
2010 "operands[7] = copy_rtx (operands[1]);")
2012 ;; ::::::::::::::::::::
2014 ;; :: 16 bit Integer arithmetic
2016 ;; ::::::::::::::::::::
2018 (define_insn "mulhi3"
2019 [(set (match_operand:HI 0 "gr_register_operand" "=r")
2020 (mult:HI (match_operand:HI 1 "gr_register_operand" "r")
2021 (match_operand:HI 2 "gr_register_operand" "r")))]
2023 "pmpy2.r %0 = %1, %2"
2024 [(set_attr "itanium_class" "mmmul")])
2027 ;; ::::::::::::::::::::
2029 ;; :: 32 bit Integer arithmetic
2031 ;; ::::::::::::::::::::
2033 (define_insn "addsi3"
2034 [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r")
2035 (plus:SI (match_operand:SI 1 "gr_register_operand" "%r,r,a")
2036 (match_operand:SI 2 "gr_reg_or_22bit_operand" "r,I,J")))]
2042 [(set_attr "itanium_class" "ialu")])
2044 (define_insn "*addsi3_plus1"
2045 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2046 (plus:SI (plus:SI (match_operand:SI 1 "gr_register_operand" "r")
2047 (match_operand:SI 2 "gr_register_operand" "r"))
2050 "add %0 = %1, %2, 1"
2051 [(set_attr "itanium_class" "ialu")])
2053 (define_insn "*addsi3_plus1_alt"
2054 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2055 (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r")
2059 "add %0 = %1, %1, 1"
2060 [(set_attr "itanium_class" "ialu")])
2062 (define_insn "*addsi3_shladd"
2063 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2064 (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r")
2065 (match_operand:SI 2 "shladd_operand" "n"))
2066 (match_operand:SI 3 "gr_register_operand" "r")))]
2068 "shladd %0 = %1, %S2, %3"
2069 [(set_attr "itanium_class" "ialu")])
2071 (define_insn "subsi3"
2072 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2073 (minus:SI (match_operand:SI 1 "gr_reg_or_8bit_operand" "rK")
2074 (match_operand:SI 2 "gr_register_operand" "r")))]
2077 [(set_attr "itanium_class" "ialu")])
2079 (define_insn "*subsi3_minus1"
2080 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2081 (plus:SI (not:SI (match_operand:SI 1 "gr_register_operand" "r"))
2082 (match_operand:SI 2 "gr_register_operand" "r")))]
2084 "sub %0 = %2, %1, 1"
2085 [(set_attr "itanium_class" "ialu")])
2087 ;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns.
2089 (define_insn "mulsi3"
2090 [(set (match_operand:SI 0 "fr_register_operand" "=f")
2091 (mult:SI (match_operand:SI 1 "grfr_register_operand" "f")
2092 (match_operand:SI 2 "grfr_register_operand" "f")))]
2094 "xmpy.l %0 = %1, %2%B0"
2095 [(set_attr "itanium_class" "xmpy")])
2097 (define_insn "maddsi4"
2098 [(set (match_operand:SI 0 "fr_register_operand" "=f")
2099 (plus:SI (mult:SI (match_operand:SI 1 "grfr_register_operand" "f")
2100 (match_operand:SI 2 "grfr_register_operand" "f"))
2101 (match_operand:SI 3 "grfr_register_operand" "f")))]
2103 "xma.l %0 = %1, %2, %3%B0"
2104 [(set_attr "itanium_class" "xmpy")])
2106 (define_insn "negsi2"
2107 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2108 (neg:SI (match_operand:SI 1 "gr_register_operand" "r")))]
2111 [(set_attr "itanium_class" "ialu")])
2113 (define_expand "abssi2"
2115 (ge:BI (match_operand:SI 1 "gr_register_operand" "") (const_int 0)))
2116 (set (match_operand:SI 0 "gr_register_operand" "")
2117 (if_then_else:SI (eq (match_dup 2) (const_int 0))
2118 (neg:SI (match_dup 1))
2123 operands[2] = gen_reg_rtx (BImode);
2126 (define_expand "sminsi3"
2128 (ge:BI (match_operand:SI 1 "gr_register_operand" "")
2129 (match_operand:SI 2 "gr_register_operand" "")))
2130 (set (match_operand:SI 0 "gr_register_operand" "")
2131 (if_then_else:SI (ne (match_dup 3) (const_int 0))
2132 (match_dup 2) (match_dup 1)))]
2136 operands[3] = gen_reg_rtx (BImode);
2139 (define_expand "smaxsi3"
2141 (ge:BI (match_operand:SI 1 "gr_register_operand" "")
2142 (match_operand:SI 2 "gr_register_operand" "")))
2143 (set (match_operand:SI 0 "gr_register_operand" "")
2144 (if_then_else:SI (ne (match_dup 3) (const_int 0))
2145 (match_dup 1) (match_dup 2)))]
2149 operands[3] = gen_reg_rtx (BImode);
2152 (define_expand "uminsi3"
2154 (geu:BI (match_operand:SI 1 "gr_register_operand" "")
2155 (match_operand:SI 2 "gr_register_operand" "")))
2156 (set (match_operand:SI 0 "gr_register_operand" "")
2157 (if_then_else:SI (ne (match_dup 3) (const_int 0))
2158 (match_dup 2) (match_dup 1)))]
2162 operands[3] = gen_reg_rtx (BImode);
2165 (define_expand "umaxsi3"
2167 (geu:BI (match_operand:SI 1 "gr_register_operand" "")
2168 (match_operand:SI 2 "gr_register_operand" "")))
2169 (set (match_operand:SI 0 "gr_register_operand" "")
2170 (if_then_else:SI (ne (match_dup 3) (const_int 0))
2171 (match_dup 1) (match_dup 2)))]
2175 operands[3] = gen_reg_rtx (BImode);
2178 (define_expand "divsi3"
2179 [(set (match_operand:SI 0 "register_operand" "")
2180 (div:SI (match_operand:SI 1 "general_operand" "")
2181 (match_operand:SI 2 "general_operand" "")))]
2185 rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
2187 op0_tf = gen_reg_rtx (TFmode);
2188 op0_di = gen_reg_rtx (DImode);
2190 if (CONSTANT_P (operands[1]))
2191 operands[1] = force_reg (SImode, operands[1]);
2192 op1_tf = gen_reg_rtx (TFmode);
2193 expand_float (op1_tf, operands[1], 0);
2195 if (CONSTANT_P (operands[2]))
2196 operands[2] = force_reg (SImode, operands[2]);
2197 op2_tf = gen_reg_rtx (TFmode);
2198 expand_float (op2_tf, operands[2], 0);
2202 twon34 = (CONST_DOUBLE_FROM_REAL_VALUE
2203 (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), TFmode));
2204 twon34 = force_reg (TFmode, twon34);
2206 twon34 = gen_reg_rtx (TFmode);
2207 convert_move (twon34, force_const_mem (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), SFmode)), 0);
2210 emit_insn (gen_divsi3_internal (op0_tf, op1_tf, op2_tf, twon34));
2212 emit_insn (gen_fix_trunctfdi2_alts (op0_di, op0_tf, const1_rtx));
2213 emit_move_insn (operands[0], gen_lowpart (SImode, op0_di));
2217 (define_expand "modsi3"
2218 [(set (match_operand:SI 0 "register_operand" "")
2219 (mod:SI (match_operand:SI 1 "general_operand" "")
2220 (match_operand:SI 2 "general_operand" "")))]
2224 rtx op2_neg, op1_di, div;
2226 div = gen_reg_rtx (SImode);
2227 emit_insn (gen_divsi3 (div, operands[1], operands[2]));
2229 op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0);
2231 /* This is a trick to get us to reuse the value that we're sure to
2232 have already copied to the FP regs. */
2233 op1_di = gen_reg_rtx (DImode);
2234 convert_move (op1_di, operands[1], 0);
2236 emit_insn (gen_maddsi4 (operands[0], div, op2_neg,
2237 gen_lowpart (SImode, op1_di)));
2241 (define_expand "udivsi3"
2242 [(set (match_operand:SI 0 "register_operand" "")
2243 (udiv:SI (match_operand:SI 1 "general_operand" "")
2244 (match_operand:SI 2 "general_operand" "")))]
2248 rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
2250 op0_tf = gen_reg_rtx (TFmode);
2251 op0_di = gen_reg_rtx (DImode);
2253 if (CONSTANT_P (operands[1]))
2254 operands[1] = force_reg (SImode, operands[1]);
2255 op1_tf = gen_reg_rtx (TFmode);
2256 expand_float (op1_tf, operands[1], 1);
2258 if (CONSTANT_P (operands[2]))
2259 operands[2] = force_reg (SImode, operands[2]);
2260 op2_tf = gen_reg_rtx (TFmode);
2261 expand_float (op2_tf, operands[2], 1);
2265 twon34 = (CONST_DOUBLE_FROM_REAL_VALUE
2266 (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), TFmode));
2267 twon34 = force_reg (TFmode, twon34);
2269 twon34 = gen_reg_rtx (TFmode);
2270 convert_move (twon34, force_const_mem (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), SFmode)), 0);
2273 emit_insn (gen_divsi3_internal (op0_tf, op1_tf, op2_tf, twon34));
2275 emit_insn (gen_fixuns_trunctfdi2_alts (op0_di, op0_tf, const1_rtx));
2276 emit_move_insn (operands[0], gen_lowpart (SImode, op0_di));
2280 (define_expand "umodsi3"
2281 [(set (match_operand:SI 0 "register_operand" "")
2282 (umod:SI (match_operand:SI 1 "general_operand" "")
2283 (match_operand:SI 2 "general_operand" "")))]
2287 rtx op2_neg, op1_di, div;
2289 div = gen_reg_rtx (SImode);
2290 emit_insn (gen_udivsi3 (div, operands[1], operands[2]));
2292 op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0);
2294 /* This is a trick to get us to reuse the value that we're sure to
2295 have already copied to the FP regs. */
2296 op1_di = gen_reg_rtx (DImode);
2297 convert_move (op1_di, operands[1], 1);
2299 emit_insn (gen_maddsi4 (operands[0], div, op2_neg,
2300 gen_lowpart (SImode, op1_di)));
2304 (define_insn_and_split "divsi3_internal"
2305 [(set (match_operand:TF 0 "fr_register_operand" "=&f")
2306 (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f")
2307 (match_operand:TF 2 "fr_register_operand" "f"))))
2308 (clobber (match_scratch:TF 4 "=&f"))
2309 (clobber (match_scratch:TF 5 "=&f"))
2310 (clobber (match_scratch:BI 6 "=c"))
2311 (use (match_operand:TF 3 "fr_register_operand" "f"))]
2314 "&& reload_completed"
2315 [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
2316 (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] 5))
2317 (use (const_int 1))])
2318 (cond_exec (ne (match_dup 6) (const_int 0))
2319 (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0)))
2320 (use (const_int 1))]))
2321 (cond_exec (ne (match_dup 6) (const_int 0))
2322 (parallel [(set (match_dup 5)
2323 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
2325 (use (const_int 1))]))
2326 (cond_exec (ne (match_dup 6) (const_int 0))
2327 (parallel [(set (match_dup 4)
2328 (plus:TF (mult:TF (match_dup 5) (match_dup 4))
2330 (use (const_int 1))]))
2331 (cond_exec (ne (match_dup 6) (const_int 0))
2332 (parallel [(set (match_dup 5)
2333 (plus:TF (mult:TF (match_dup 5) (match_dup 5))
2335 (use (const_int 1))]))
2336 (cond_exec (ne (match_dup 6) (const_int 0))
2337 (parallel [(set (match_dup 0)
2338 (plus:TF (mult:TF (match_dup 5) (match_dup 4))
2340 (use (const_int 1))]))
2342 "operands[7] = CONST1_RTX (TFmode);"
2343 [(set_attr "predicable" "no")])
2345 ;; ::::::::::::::::::::
2347 ;; :: 64 bit Integer arithmetic
2349 ;; ::::::::::::::::::::
2351 (define_insn "adddi3"
2352 [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r")
2353 (plus:DI (match_operand:DI 1 "gr_register_operand" "%r,r,a")
2354 (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))]
2360 [(set_attr "itanium_class" "ialu")])
2362 (define_insn "*adddi3_plus1"
2363 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2364 (plus:DI (plus:DI (match_operand:DI 1 "gr_register_operand" "r")
2365 (match_operand:DI 2 "gr_register_operand" "r"))
2368 "add %0 = %1, %2, 1"
2369 [(set_attr "itanium_class" "ialu")])
2371 ;; This has some of the same problems as shladd. We let the shladd
2372 ;; eliminator hack handle it, which results in the 1 being forced into
2373 ;; a register, but not more ugliness here.
2374 (define_insn "*adddi3_plus1_alt"
2375 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2376 (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
2380 "add %0 = %1, %1, 1"
2381 [(set_attr "itanium_class" "ialu")])
2383 (define_insn "subdi3"
2384 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2385 (minus:DI (match_operand:DI 1 "gr_reg_or_8bit_operand" "rK")
2386 (match_operand:DI 2 "gr_register_operand" "r")))]
2389 [(set_attr "itanium_class" "ialu")])
2391 (define_insn "*subdi3_minus1"
2392 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2393 (plus:DI (not:DI (match_operand:DI 1 "gr_register_operand" "r"))
2394 (match_operand:DI 2 "gr_register_operand" "r")))]
2396 "sub %0 = %2, %1, 1"
2397 [(set_attr "itanium_class" "ialu")])
2399 ;; ??? Use grfr instead of fr because of virtual register elimination
2400 ;; and silly test cases multiplying by the frame pointer.
2401 (define_insn "muldi3"
2402 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2403 (mult:DI (match_operand:DI 1 "grfr_register_operand" "f")
2404 (match_operand:DI 2 "grfr_register_operand" "f")))]
2406 "xmpy.l %0 = %1, %2%B0"
2407 [(set_attr "itanium_class" "xmpy")])
2409 ;; ??? If operand 3 is an eliminable reg, then register elimination causes the
2410 ;; same problem that we have with shladd below. Unfortunately, this case is
2411 ;; much harder to fix because the multiply puts the result in an FP register,
2412 ;; but the add needs inputs from a general register. We add a spurious clobber
2413 ;; here so that it will be present just in case register elimination gives us
2414 ;; the funny result.
2416 ;; ??? Maybe validate_changes should try adding match_scratch clobbers?
2418 ;; ??? Maybe we should change how adds are canonicalized.
2420 (define_insn "madddi4"
2421 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2422 (plus:DI (mult:DI (match_operand:DI 1 "grfr_register_operand" "f")
2423 (match_operand:DI 2 "grfr_register_operand" "f"))
2424 (match_operand:DI 3 "grfr_register_operand" "f")))
2425 (clobber (match_scratch:DI 4 "=X"))]
2427 "xma.l %0 = %1, %2, %3%B0"
2428 [(set_attr "itanium_class" "xmpy")])
2430 ;; This can be created by register elimination if operand3 of shladd is an
2431 ;; eliminable register or has reg_equiv_constant set.
2433 ;; We have to use nonmemory_operand for operand 4, to ensure that the
2434 ;; validate_changes call inside eliminate_regs will always succeed. If it
2435 ;; doesn't succeed, then this remain a madddi4 pattern, and will be reloaded
2438 (define_insn "*madddi4_elim"
2439 [(set (match_operand:DI 0 "register_operand" "=&r")
2440 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f")
2441 (match_operand:DI 2 "register_operand" "f"))
2442 (match_operand:DI 3 "register_operand" "f"))
2443 (match_operand:DI 4 "nonmemory_operand" "rI")))
2444 (clobber (match_scratch:DI 5 "=f"))]
2445 "reload_in_progress"
2447 [(set_attr "itanium_class" "unknown")])
2450 [(set (match_operand:DI 0 "register_operand" "")
2451 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2452 (match_operand:DI 2 "register_operand" ""))
2453 (match_operand:DI 3 "register_operand" ""))
2454 (match_operand:DI 4 "gr_reg_or_14bit_operand" "")))
2455 (clobber (match_scratch:DI 5 ""))]
2457 [(parallel [(set (match_dup 5) (plus:DI (mult:DI (match_dup 1) (match_dup 2))
2459 (clobber (match_dup 0))])
2460 (set (match_dup 0) (match_dup 5))
2461 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
2464 ;; ??? There are highpart multiply and add instructions, but we have no way
2465 ;; to generate them.
2467 (define_insn "smuldi3_highpart"
2468 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2471 (mult:TI (sign_extend:TI
2472 (match_operand:DI 1 "fr_register_operand" "f"))
2474 (match_operand:DI 2 "fr_register_operand" "f")))
2477 "xmpy.h %0 = %1, %2%B0"
2478 [(set_attr "itanium_class" "xmpy")])
2480 (define_insn "umuldi3_highpart"
2481 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2484 (mult:TI (zero_extend:TI
2485 (match_operand:DI 1 "fr_register_operand" "f"))
2487 (match_operand:DI 2 "fr_register_operand" "f")))
2490 "xmpy.hu %0 = %1, %2%B0"
2491 [(set_attr "itanium_class" "xmpy")])
2493 (define_insn "negdi2"
2494 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2495 (neg:DI (match_operand:DI 1 "gr_register_operand" "r")))]
2498 [(set_attr "itanium_class" "ialu")])
2500 (define_expand "absdi2"
2502 (ge:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0)))
2503 (set (match_operand:DI 0 "gr_register_operand" "")
2504 (if_then_else:DI (eq (match_dup 2) (const_int 0))
2505 (neg:DI (match_dup 1))
2510 operands[2] = gen_reg_rtx (BImode);
2513 (define_expand "smindi3"
2515 (ge:BI (match_operand:DI 1 "gr_register_operand" "")
2516 (match_operand:DI 2 "gr_register_operand" "")))
2517 (set (match_operand:DI 0 "gr_register_operand" "")
2518 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2519 (match_dup 2) (match_dup 1)))]
2523 operands[3] = gen_reg_rtx (BImode);
2526 (define_expand "smaxdi3"
2528 (ge:BI (match_operand:DI 1 "gr_register_operand" "")
2529 (match_operand:DI 2 "gr_register_operand" "")))
2530 (set (match_operand:DI 0 "gr_register_operand" "")
2531 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2532 (match_dup 1) (match_dup 2)))]
2536 operands[3] = gen_reg_rtx (BImode);
2539 (define_expand "umindi3"
2541 (geu:BI (match_operand:DI 1 "gr_register_operand" "")
2542 (match_operand:DI 2 "gr_register_operand" "")))
2543 (set (match_operand:DI 0 "gr_register_operand" "")
2544 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2545 (match_dup 2) (match_dup 1)))]
2549 operands[3] = gen_reg_rtx (BImode);
2552 (define_expand "umaxdi3"
2554 (geu:BI (match_operand:DI 1 "gr_register_operand" "")
2555 (match_operand:DI 2 "gr_register_operand" "")))
2556 (set (match_operand:DI 0 "gr_register_operand" "")
2557 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2558 (match_dup 1) (match_dup 2)))]
2562 operands[3] = gen_reg_rtx (BImode);
2565 (define_expand "ffsdi2"
2567 (eq:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0)))
2568 (set (match_dup 2) (plus:DI (match_dup 1) (const_int -1)))
2569 (set (match_dup 5) (const_int 0))
2570 (set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2)))
2571 (set (match_dup 4) (unspec:DI [(match_dup 3)] 8))
2572 (set (match_operand:DI 0 "gr_register_operand" "")
2573 (if_then_else:DI (ne (match_dup 6) (const_int 0))
2574 (match_dup 5) (match_dup 4)))]
2578 operands[2] = gen_reg_rtx (DImode);
2579 operands[3] = gen_reg_rtx (DImode);
2580 operands[4] = gen_reg_rtx (DImode);
2581 operands[5] = gen_reg_rtx (DImode);
2582 operands[6] = gen_reg_rtx (BImode);
2585 (define_insn "*popcnt"
2586 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2587 (unspec:DI [(match_operand:DI 1 "gr_register_operand" "r")] 8))]
2590 [(set_attr "itanium_class" "mmmul")])
2592 (define_expand "divdi3"
2593 [(set (match_operand:DI 0 "register_operand" "")
2594 (div:DI (match_operand:DI 1 "general_operand" "")
2595 (match_operand:DI 2 "general_operand" "")))]
2599 rtx op1_tf, op2_tf, op0_tf;
2601 op0_tf = gen_reg_rtx (TFmode);
2603 if (CONSTANT_P (operands[1]))
2604 operands[1] = force_reg (DImode, operands[1]);
2605 op1_tf = gen_reg_rtx (TFmode);
2606 expand_float (op1_tf, operands[1], 0);
2608 if (CONSTANT_P (operands[2]))
2609 operands[2] = force_reg (DImode, operands[2]);
2610 op2_tf = gen_reg_rtx (TFmode);
2611 expand_float (op2_tf, operands[2], 0);
2613 if (TARGET_INLINE_DIV_LAT)
2614 emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf));
2616 emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf));
2618 emit_insn (gen_fix_trunctfdi2_alts (operands[0], op0_tf, const1_rtx));
2622 (define_expand "moddi3"
2623 [(set (match_operand:DI 0 "register_operand" "")
2624 (mod:SI (match_operand:DI 1 "general_operand" "")
2625 (match_operand:DI 2 "general_operand" "")))]
2631 div = gen_reg_rtx (DImode);
2632 emit_insn (gen_divdi3 (div, operands[1], operands[2]));
2634 op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0);
2636 emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1]));
2640 (define_expand "udivdi3"
2641 [(set (match_operand:DI 0 "register_operand" "")
2642 (udiv:DI (match_operand:DI 1 "general_operand" "")
2643 (match_operand:DI 2 "general_operand" "")))]
2647 rtx op1_tf, op2_tf, op0_tf;
2649 op0_tf = gen_reg_rtx (TFmode);
2651 if (CONSTANT_P (operands[1]))
2652 operands[1] = force_reg (DImode, operands[1]);
2653 op1_tf = gen_reg_rtx (TFmode);
2654 expand_float (op1_tf, operands[1], 1);
2656 if (CONSTANT_P (operands[2]))
2657 operands[2] = force_reg (DImode, operands[2]);
2658 op2_tf = gen_reg_rtx (TFmode);
2659 expand_float (op2_tf, operands[2], 1);
2661 if (TARGET_INLINE_DIV_LAT)
2662 emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf));
2664 emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf));
2666 emit_insn (gen_fixuns_trunctfdi2_alts (operands[0], op0_tf, const1_rtx));
2670 (define_expand "umoddi3"
2671 [(set (match_operand:DI 0 "register_operand" "")
2672 (umod:DI (match_operand:DI 1 "general_operand" "")
2673 (match_operand:DI 2 "general_operand" "")))]
2679 div = gen_reg_rtx (DImode);
2680 emit_insn (gen_udivdi3 (div, operands[1], operands[2]));
2682 op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0);
2684 emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1]));
2688 (define_insn_and_split "divdi3_internal_lat"
2689 [(set (match_operand:TF 0 "fr_register_operand" "=&f")
2690 (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f")
2691 (match_operand:TF 2 "fr_register_operand" "f"))))
2692 (clobber (match_scratch:TF 3 "=&f"))
2693 (clobber (match_scratch:TF 4 "=&f"))
2694 (clobber (match_scratch:TF 5 "=&f"))
2695 (clobber (match_scratch:BI 6 "=c"))]
2696 "TARGET_INLINE_DIV_LAT"
2698 "&& reload_completed"
2699 [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
2700 (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] 5))
2701 (use (const_int 1))])
2702 (cond_exec (ne (match_dup 6) (const_int 0))
2703 (parallel [(set (match_dup 3)
2704 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
2706 (use (const_int 1))]))
2707 (cond_exec (ne (match_dup 6) (const_int 0))
2708 (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0)))
2709 (use (const_int 1))]))
2710 (cond_exec (ne (match_dup 6) (const_int 0))
2711 (parallel [(set (match_dup 5) (mult:TF (match_dup 3) (match_dup 3)))
2712 (use (const_int 1))]))
2713 (cond_exec (ne (match_dup 6) (const_int 0))
2714 (parallel [(set (match_dup 4)
2715 (plus:TF (mult:TF (match_dup 3) (match_dup 4))
2717 (use (const_int 1))]))
2718 (cond_exec (ne (match_dup 6) (const_int 0))
2719 (parallel [(set (match_dup 0)
2720 (plus:TF (mult:TF (match_dup 3) (match_dup 0))
2722 (use (const_int 1))]))
2723 (cond_exec (ne (match_dup 6) (const_int 0))
2724 (parallel [(set (match_dup 3)
2725 (plus:TF (mult:TF (match_dup 5) (match_dup 4))
2727 (use (const_int 1))]))
2728 (cond_exec (ne (match_dup 6) (const_int 0))
2729 (parallel [(set (match_dup 0)
2730 (plus:TF (mult:TF (match_dup 5) (match_dup 0))
2732 (use (const_int 1))]))
2733 (cond_exec (ne (match_dup 6) (const_int 0))
2734 (parallel [(set (match_dup 4)
2735 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3)))
2737 (use (const_int 1))]))
2738 (cond_exec (ne (match_dup 6) (const_int 0))
2739 (parallel [(set (match_dup 0)
2740 (plus:TF (mult:TF (match_dup 4) (match_dup 0))
2742 (use (const_int 1))]))
2744 "operands[7] = CONST1_RTX (TFmode);"
2745 [(set_attr "predicable" "no")])
2747 (define_insn_and_split "divdi3_internal_thr"
2748 [(set (match_operand:TF 0 "fr_register_operand" "=&f")
2749 (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f")
2750 (match_operand:TF 2 "fr_register_operand" "f"))))
2751 (clobber (match_scratch:TF 3 "=&f"))
2752 (clobber (match_scratch:TF 4 "=f"))
2753 (clobber (match_scratch:BI 5 "=c"))]
2754 "TARGET_INLINE_DIV_THR"
2756 "&& reload_completed"
2757 [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
2758 (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] 5))
2759 (use (const_int 1))])
2760 (cond_exec (ne (match_dup 5) (const_int 0))
2761 (parallel [(set (match_dup 3)
2762 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
2764 (use (const_int 1))]))
2765 (cond_exec (ne (match_dup 5) (const_int 0))
2766 (parallel [(set (match_dup 0)
2767 (plus:TF (mult:TF (match_dup 3) (match_dup 0))
2769 (use (const_int 1))]))
2770 (cond_exec (ne (match_dup 5) (const_int 0))
2771 (parallel [(set (match_dup 3) (mult:TF (match_dup 3) (match_dup 3)))
2772 (use (const_int 1))]))
2773 (cond_exec (ne (match_dup 5) (const_int 0))
2774 (parallel [(set (match_dup 0)
2775 (plus:TF (mult:TF (match_dup 3) (match_dup 0))
2777 (use (const_int 1))]))
2778 (cond_exec (ne (match_dup 5) (const_int 0))
2779 (parallel [(set (match_dup 3) (mult:TF (match_dup 0) (match_dup 1)))
2780 (use (const_int 1))]))
2781 (cond_exec (ne (match_dup 5) (const_int 0))
2782 (parallel [(set (match_dup 4)
2783 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3)))
2785 (use (const_int 1))]))
2786 (cond_exec (ne (match_dup 5) (const_int 0))
2787 (parallel [(set (match_dup 0)
2788 (plus:TF (mult:TF (match_dup 4) (match_dup 0))
2790 (use (const_int 1))]))
2792 "operands[6] = CONST1_RTX (TFmode);"
2793 [(set_attr "predicable" "no")])
2795 ;; ::::::::::::::::::::
2797 ;; :: 32 bit floating point arithmetic
2799 ;; ::::::::::::::::::::
2801 (define_insn "addsf3"
2802 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2803 (plus:SF (match_operand:SF 1 "fr_register_operand" "%f")
2804 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2806 "fadd.s %0 = %1, %F2%B0"
2807 [(set_attr "itanium_class" "fmac")])
2809 (define_insn "subsf3"
2810 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2811 (minus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2812 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2814 "fsub.s %0 = %F1, %F2%B0"
2815 [(set_attr "itanium_class" "fmac")])
2817 (define_insn "mulsf3"
2818 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2819 (mult:SF (match_operand:SF 1 "fr_register_operand" "%f")
2820 (match_operand:SF 2 "fr_register_operand" "f")))]
2822 "fmpy.s %0 = %1, %2%B0"
2823 [(set_attr "itanium_class" "fmac")])
2825 (define_insn "abssf2"
2826 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2827 (abs:SF (match_operand:SF 1 "fr_register_operand" "f")))]
2830 [(set_attr "itanium_class" "fmisc")])
2832 (define_insn "negsf2"
2833 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2834 (neg:SF (match_operand:SF 1 "fr_register_operand" "f")))]
2837 [(set_attr "itanium_class" "fmisc")])
2839 (define_insn "*nabssf2"
2840 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2841 (neg:SF (abs:SF (match_operand:SF 1 "fr_register_operand" "f"))))]
2843 "fnegabs %0 = %1%B0"
2844 [(set_attr "itanium_class" "fmisc")])
2846 (define_insn "minsf3"
2847 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2848 (smin:SF (match_operand:SF 1 "fr_register_operand" "f")
2849 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2851 "fmin %0 = %1, %F2%B0"
2852 [(set_attr "itanium_class" "fmisc")])
2854 (define_insn "maxsf3"
2855 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2856 (smax:SF (match_operand:SF 1 "fr_register_operand" "f")
2857 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2859 "fmax %0 = %1, %F2%B0"
2860 [(set_attr "itanium_class" "fmisc")])
2862 (define_insn "*maddsf4"
2863 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2864 (plus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
2865 (match_operand:SF 2 "fr_register_operand" "f"))
2866 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
2868 "fma.s %0 = %1, %2, %F3%B0"
2869 [(set_attr "itanium_class" "fmac")])
2871 (define_insn "*msubsf4"
2872 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2873 (minus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
2874 (match_operand:SF 2 "fr_register_operand" "f"))
2875 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
2877 "fms.s %0 = %1, %2, %F3%B0"
2878 [(set_attr "itanium_class" "fmac")])
2880 (define_insn "*nmulsf3"
2881 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2882 (neg:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
2883 (match_operand:SF 2 "fr_register_operand" "f"))))]
2885 "fnmpy.s %0 = %1, %2%B0"
2886 [(set_attr "itanium_class" "fmac")])
2888 ;; ??? Is it possible to canonicalize this as (minus (reg) (mult))?
2890 (define_insn "*nmaddsf4"
2891 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2892 (plus:SF (neg:SF (mult:SF
2893 (match_operand:SF 1 "fr_register_operand" "f")
2894 (match_operand:SF 2 "fr_register_operand" "f")))
2895 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
2897 "fnma.s %0 = %1, %2, %F3%B0"
2898 [(set_attr "itanium_class" "fmac")])
2900 (define_expand "divsf3"
2901 [(set (match_operand:SF 0 "fr_register_operand" "")
2902 (div:SF (match_operand:SF 1 "fr_register_operand" "")
2903 (match_operand:SF 2 "fr_register_operand" "")))]
2908 if (TARGET_INLINE_DIV_LAT)
2909 insn = gen_divsf3_internal_lat (operands[0], operands[1], operands[2]);
2911 insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]);
2916 (define_insn_and_split "divsf3_internal_lat"
2917 [(set (match_operand:SF 0 "fr_register_operand" "=&f")
2918 (div:SF (match_operand:SF 1 "fr_register_operand" "f")
2919 (match_operand:SF 2 "fr_register_operand" "f")))
2920 (clobber (match_scratch:TF 3 "=&f"))
2921 (clobber (match_scratch:TF 4 "=f"))
2922 (clobber (match_scratch:BI 5 "=c"))]
2923 "TARGET_INLINE_DIV_LAT"
2925 "&& reload_completed"
2926 [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
2927 (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] 5))
2928 (use (const_int 1))])
2929 (cond_exec (ne (match_dup 5) (const_int 0))
2930 (parallel [(set (match_dup 3) (mult:TF (match_dup 7) (match_dup 6)))
2931 (use (const_int 1))]))
2932 (cond_exec (ne (match_dup 5) (const_int 0))
2933 (parallel [(set (match_dup 4)
2934 (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6)))
2936 (use (const_int 1))]))
2937 (cond_exec (ne (match_dup 5) (const_int 0))
2938 (parallel [(set (match_dup 3)
2939 (plus:TF (mult:TF (match_dup 4) (match_dup 3))
2941 (use (const_int 1))]))
2942 (cond_exec (ne (match_dup 5) (const_int 0))
2943 (parallel [(set (match_dup 4) (mult:TF (match_dup 4) (match_dup 4)))
2944 (use (const_int 1))]))
2945 (cond_exec (ne (match_dup 5) (const_int 0))
2946 (parallel [(set (match_dup 3)
2947 (plus:TF (mult:TF (match_dup 4) (match_dup 3))
2949 (use (const_int 1))]))
2950 (cond_exec (ne (match_dup 5) (const_int 0))
2951 (parallel [(set (match_dup 4) (mult:TF (match_dup 4) (match_dup 4)))
2952 (use (const_int 1))]))
2953 (cond_exec (ne (match_dup 5) (const_int 0))
2954 (parallel [(set (match_dup 9)
2956 (plus:TF (mult:TF (match_dup 4) (match_dup 3))
2958 (use (const_int 1))]))
2959 (cond_exec (ne (match_dup 5) (const_int 0))
2961 (float_truncate:SF (match_dup 6))))
2963 "operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
2964 operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
2965 operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
2966 operands[9] = gen_rtx_REG (DFmode, REGNO (operands[0]));
2967 operands[10] = CONST1_RTX (TFmode);"
2968 [(set_attr "predicable" "no")])
2970 (define_insn_and_split "divsf3_internal_thr"
2971 [(set (match_operand:SF 0 "fr_register_operand" "=&f")
2972 (div:SF (match_operand:SF 1 "fr_register_operand" "f")
2973 (match_operand:SF 2 "fr_register_operand" "f")))
2974 (clobber (match_scratch:TF 3 "=&f"))
2975 (clobber (match_scratch:TF 4 "=f"))
2976 (clobber (match_scratch:BI 5 "=c"))]
2977 "TARGET_INLINE_DIV_THR"
2979 "&& reload_completed"
2980 [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
2981 (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] 5))
2982 (use (const_int 1))])
2983 (cond_exec (ne (match_dup 5) (const_int 0))
2984 (parallel [(set (match_dup 3)
2985 (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6)))
2987 (use (const_int 1))]))
2988 (cond_exec (ne (match_dup 5) (const_int 0))
2989 (parallel [(set (match_dup 3)
2990 (plus:TF (mult:TF (match_dup 3) (match_dup 3))
2992 (use (const_int 1))]))
2993 (cond_exec (ne (match_dup 5) (const_int 0))
2994 (parallel [(set (match_dup 6)
2995 (plus:TF (mult:TF (match_dup 3) (match_dup 6))
2997 (use (const_int 1))]))
2998 (cond_exec (ne (match_dup 5) (const_int 0))
2999 (parallel [(set (match_dup 9)
3001 (mult:TF (match_dup 7) (match_dup 6))))
3002 (use (const_int 1))]))
3003 (cond_exec (ne (match_dup 5) (const_int 0))
3004 (parallel [(set (match_dup 4)
3005 (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 3)))
3007 (use (const_int 1))]))
3008 (cond_exec (ne (match_dup 5) (const_int 0))
3011 (plus:TF (mult:TF (match_dup 4) (match_dup 6))
3014 "operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
3015 operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
3016 operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
3017 operands[9] = gen_rtx_REG (SFmode, REGNO (operands[3]));
3018 operands[10] = CONST1_RTX (TFmode);"
3019 [(set_attr "predicable" "no")])
3021 ;; ::::::::::::::::::::
3023 ;; :: 64 bit floating point arithmetic
3025 ;; ::::::::::::::::::::
3027 (define_insn "adddf3"
3028 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3029 (plus:DF (match_operand:DF 1 "fr_register_operand" "%f")
3030 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
3032 "fadd.d %0 = %1, %F2%B0"
3033 [(set_attr "itanium_class" "fmac")])
3035 (define_insn "*adddf3_trunc"
3036 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3038 (plus:DF (match_operand:DF 1 "fr_register_operand" "%f")
3039 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
3041 "fadd.s %0 = %1, %F2%B0"
3042 [(set_attr "itanium_class" "fmac")])
3044 (define_insn "subdf3"
3045 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3046 (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
3047 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
3049 "fsub.d %0 = %F1, %F2%B0"
3050 [(set_attr "itanium_class" "fmac")])
3052 (define_insn "*subdf3_trunc"
3053 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3055 (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
3056 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
3058 "fsub.s %0 = %F1, %F2%B0"
3059 [(set_attr "itanium_class" "fmac")])
3061 (define_insn "muldf3"
3062 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3063 (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3064 (match_operand:DF 2 "fr_register_operand" "f")))]
3066 "fmpy.d %0 = %1, %2%B0"
3067 [(set_attr "itanium_class" "fmac")])
3069 (define_insn "*muldf3_trunc"
3070 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3072 (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3073 (match_operand:DF 2 "fr_register_operand" "f"))))]
3075 "fmpy.s %0 = %1, %2%B0"
3076 [(set_attr "itanium_class" "fmac")])
3078 (define_insn "absdf2"
3079 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3080 (abs:DF (match_operand:DF 1 "fr_register_operand" "f")))]
3083 [(set_attr "itanium_class" "fmisc")])
3085 (define_insn "negdf2"
3086 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3087 (neg:DF (match_operand:DF 1 "fr_register_operand" "f")))]
3090 [(set_attr "itanium_class" "fmisc")])
3092 (define_insn "*nabsdf2"
3093 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3094 (neg:DF (abs:DF (match_operand:DF 1 "fr_register_operand" "f"))))]
3096 "fnegabs %0 = %1%B0"
3097 [(set_attr "itanium_class" "fmisc")])
3099 (define_insn "mindf3"
3100 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3101 (smin:DF (match_operand:DF 1 "fr_register_operand" "f")
3102 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
3104 "fmin %0 = %1, %F2%B0"
3105 [(set_attr "itanium_class" "fmisc")])
3107 (define_insn "maxdf3"
3108 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3109 (smax:DF (match_operand:DF 1 "fr_register_operand" "f")
3110 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
3112 "fmax %0 = %1, %F2%B0"
3113 [(set_attr "itanium_class" "fmisc")])
3115 (define_insn "*madddf4"
3116 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3117 (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3118 (match_operand:DF 2 "fr_register_operand" "f"))
3119 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
3121 "fma.d %0 = %1, %2, %F3%B0"
3122 [(set_attr "itanium_class" "fmac")])
3124 (define_insn "*madddf4_trunc"
3125 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3127 (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3128 (match_operand:DF 2 "fr_register_operand" "f"))
3129 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
3131 "fma.s %0 = %1, %2, %F3%B0"
3132 [(set_attr "itanium_class" "fmac")])
3134 (define_insn "*msubdf4"
3135 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3136 (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3137 (match_operand:DF 2 "fr_register_operand" "f"))
3138 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
3140 "fms.d %0 = %1, %2, %F3%B0"
3141 [(set_attr "itanium_class" "fmac")])
3143 (define_insn "*msubdf4_trunc"
3144 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3146 (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3147 (match_operand:DF 2 "fr_register_operand" "f"))
3148 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
3150 "fms.s %0 = %1, %2, %F3%B0"
3151 [(set_attr "itanium_class" "fmac")])
3153 (define_insn "*nmuldf3"
3154 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3155 (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3156 (match_operand:DF 2 "fr_register_operand" "f"))))]
3158 "fnmpy.d %0 = %1, %2%B0"
3159 [(set_attr "itanium_class" "fmac")])
3161 (define_insn "*nmuldf3_trunc"
3162 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3164 (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3165 (match_operand:DF 2 "fr_register_operand" "f")))))]
3167 "fnmpy.s %0 = %1, %2%B0"
3168 [(set_attr "itanium_class" "fmac")])
3170 ;; ??? Is it possible to canonicalize this as (minus (reg) (mult))?
3172 (define_insn "*nmadddf4"
3173 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3174 (plus:DF (neg:DF (mult:DF
3175 (match_operand:DF 1 "fr_register_operand" "f")
3176 (match_operand:DF 2 "fr_register_operand" "f")))
3177 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
3179 "fnma.d %0 = %1, %2, %F3%B0"
3180 [(set_attr "itanium_class" "fmac")])
3182 (define_insn "*nmadddf4_alts"
3183 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3184 (plus:DF (neg:DF (mult:DF
3185 (match_operand:DF 1 "fr_register_operand" "f")
3186 (match_operand:DF 2 "fr_register_operand" "f")))
3187 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))
3188 (use (match_operand:SI 4 "const_int_operand" ""))]
3190 "fnma.d.s%4 %0 = %1, %2, %F3%B0"
3191 [(set_attr "itanium_class" "fmac")])
3193 (define_insn "*nmadddf4_trunc"
3194 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3196 (plus:DF (neg:DF (mult:DF
3197 (match_operand:DF 1 "fr_register_operand" "f")
3198 (match_operand:DF 2 "fr_register_operand" "f")))
3199 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
3201 "fnma.s %0 = %1, %2, %F3%B0"
3202 [(set_attr "itanium_class" "fmac")])
3204 (define_expand "divdf3"
3205 [(set (match_operand:DF 0 "fr_register_operand" "")
3206 (div:DF (match_operand:DF 1 "fr_register_operand" "")
3207 (match_operand:DF 2 "fr_register_operand" "")))]
3212 if (TARGET_INLINE_DIV_LAT)
3213 insn = gen_divdf3_internal_lat (operands[0], operands[1], operands[2]);
3215 insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]);
3220 (define_insn_and_split "divdf3_internal_lat"
3221 [(set (match_operand:DF 0 "fr_register_operand" "=&f")
3222 (div:DF (match_operand:DF 1 "fr_register_operand" "f")
3223 (match_operand:DF 2 "fr_register_operand" "f")))
3224 (clobber (match_scratch:TF 3 "=&f"))
3225 (clobber (match_scratch:TF 4 "=&f"))
3226 (clobber (match_scratch:TF 5 "=&f"))
3227 (clobber (match_scratch:BI 6 "=c"))]
3228 "TARGET_INLINE_DIV_LAT"
3230 "&& reload_completed"
3231 [(parallel [(set (match_dup 7) (div:TF (const_int 1) (match_dup 9)))
3232 (set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)] 5))
3233 (use (const_int 1))])
3234 (cond_exec (ne (match_dup 6) (const_int 0))
3235 (parallel [(set (match_dup 3) (mult:TF (match_dup 8) (match_dup 7)))
3236 (use (const_int 1))]))
3237 (cond_exec (ne (match_dup 6) (const_int 0))
3238 (parallel [(set (match_dup 4)
3239 (plus:TF (neg:TF (mult:TF (match_dup 9) (match_dup 7)))
3241 (use (const_int 1))]))
3242 (cond_exec (ne (match_dup 6) (const_int 0))
3243 (parallel [(set (match_dup 3)
3244 (plus:TF (mult:TF (match_dup 4) (match_dup 3))
3246 (use (const_int 1))]))
3247 (cond_exec (ne (match_dup 6) (const_int 0))
3248 (parallel [(set (match_dup 5) (mult:TF (match_dup 4) (match_dup 4)))
3249 (use (const_int 1))]))
3250 (cond_exec (ne (match_dup 6) (const_int 0))
3251 (parallel [(set (match_dup 7)
3252 (plus:TF (mult:TF (match_dup 4) (match_dup 7))
3254 (use (const_int 1))]))
3255 (cond_exec (ne (match_dup 6) (const_int 0))
3256 (parallel [(set (match_dup 3)
3257 (plus:TF (mult:TF (match_dup 5) (match_dup 3))
3259 (use (const_int 1))]))
3260 (cond_exec (ne (match_dup 6) (const_int 0))
3261 (parallel [(set (match_dup 4) (mult:TF (match_dup 5) (match_dup 5)))
3262 (use (const_int 1))]))
3263 (cond_exec (ne (match_dup 6) (const_int 0))
3264 (parallel [(set (match_dup 7)
3265 (plus:TF (mult:TF (match_dup 5) (match_dup 7))
3267 (use (const_int 1))]))
3268 (cond_exec (ne (match_dup 6) (const_int 0))
3269 (parallel [(set (match_dup 10)
3271 (plus:TF (mult:TF (match_dup 4) (match_dup 3))
3273 (use (const_int 1))]))
3274 (cond_exec (ne (match_dup 6) (const_int 0))
3275 (parallel [(set (match_dup 7)
3276 (plus:TF (mult:TF (match_dup 4) (match_dup 7))
3278 (use (const_int 1))]))
3279 (cond_exec (ne (match_dup 6) (const_int 0))
3280 (parallel [(set (match_dup 11)
3282 (plus:TF (neg:TF (mult:TF (match_dup 9) (match_dup 3)))
3284 (use (const_int 1))]))
3285 (cond_exec (ne (match_dup 6) (const_int 0))
3287 (float_truncate:DF (plus:TF (mult:TF (match_dup 5) (match_dup 7))
3290 "operands[7] = gen_rtx_REG (TFmode, REGNO (operands[0]));
3291 operands[8] = gen_rtx_REG (TFmode, REGNO (operands[1]));
3292 operands[9] = gen_rtx_REG (TFmode, REGNO (operands[2]));
3293 operands[10] = gen_rtx_REG (DFmode, REGNO (operands[3]));
3294 operands[11] = gen_rtx_REG (DFmode, REGNO (operands[5]));
3295 operands[12] = CONST1_RTX (TFmode);"
3296 [(set_attr "predicable" "no")])
3298 (define_insn_and_split "divdf3_internal_thr"
3299 [(set (match_operand:DF 0 "fr_register_operand" "=&f")
3300 (div:DF (match_operand:DF 1 "fr_register_operand" "f")
3301 (match_operand:DF 2 "fr_register_operand" "f")))
3302 (clobber (match_scratch:TF 3 "=&f"))
3303 (clobber (match_scratch:DF 4 "=f"))
3304 (clobber (match_scratch:BI 5 "=c"))]
3305 "TARGET_INLINE_DIV_THR"
3307 "&& reload_completed"
3308 [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
3309 (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] 5))
3310 (use (const_int 1))])
3311 (cond_exec (ne (match_dup 5) (const_int 0))
3312 (parallel [(set (match_dup 3)
3313 (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6)))
3315 (use (const_int 1))]))
3316 (cond_exec (ne (match_dup 5) (const_int 0))
3317 (parallel [(set (match_dup 6)
3318 (plus:TF (mult:TF (match_dup 3) (match_dup 6))
3320 (use (const_int 1))]))
3321 (cond_exec (ne (match_dup 5) (const_int 0))
3322 (parallel [(set (match_dup 3)
3323 (mult:TF (match_dup 3) (match_dup 3)))
3324 (use (const_int 1))]))
3325 (cond_exec (ne (match_dup 5) (const_int 0))
3326 (parallel [(set (match_dup 6)
3327 (plus:TF (mult:TF (match_dup 3) (match_dup 6))
3329 (use (const_int 1))]))
3330 (cond_exec (ne (match_dup 5) (const_int 0))
3331 (parallel [(set (match_dup 3)
3332 (mult:TF (match_dup 3) (match_dup 3)))
3333 (use (const_int 1))]))
3334 (cond_exec (ne (match_dup 5) (const_int 0))
3335 (parallel [(set (match_dup 6)
3336 (plus:TF (mult:TF (match_dup 3) (match_dup 6))
3338 (use (const_int 1))]))
3339 (cond_exec (ne (match_dup 5) (const_int 0))
3340 (parallel [(set (match_dup 9)
3342 (mult:TF (match_dup 7) (match_dup 3))))
3343 (use (const_int 1))]))
3344 (cond_exec (ne (match_dup 5) (const_int 0))
3345 (parallel [(set (match_dup 4)
3346 (plus:DF (neg:DF (mult:DF (match_dup 2) (match_dup 9)))
3348 (use (const_int 1))]))
3349 (cond_exec (ne (match_dup 5) (const_int 0))
3351 (plus:DF (mult:DF (match_dup 4) (match_dup 0))
3354 "operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
3355 operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
3356 operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
3357 operands[9] = gen_rtx_REG (DFmode, REGNO (operands[3]));
3358 operands[10] = CONST1_RTX (TFmode);"
3359 [(set_attr "predicable" "no")])
3361 ;; ::::::::::::::::::::
3363 ;; :: 80 bit floating point arithmetic
3365 ;; ::::::::::::::::::::
3367 (define_insn "addtf3"
3368 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3369 (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3370 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
3372 "fadd %0 = %F1, %F2%B0"
3373 [(set_attr "itanium_class" "fmac")])
3375 (define_insn "*addtf3_truncsf"
3376 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3378 (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3379 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
3381 "fadd.s %0 = %F1, %F2%B0"
3382 [(set_attr "itanium_class" "fmac")])
3384 (define_insn "*addtf3_truncdf"
3385 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3387 (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3388 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
3390 "fadd.d %0 = %F1, %F2%B0"
3391 [(set_attr "itanium_class" "fmac")])
3393 (define_insn "subtf3"
3394 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3395 (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3396 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
3398 "fsub %0 = %F1, %F2%B0"
3399 [(set_attr "itanium_class" "fmac")])
3401 (define_insn "*subtf3_truncsf"
3402 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3404 (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3405 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
3407 "fsub.s %0 = %F1, %F2%B0"
3408 [(set_attr "itanium_class" "fmac")])
3410 (define_insn "*subtf3_truncdf"
3411 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3413 (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3414 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
3416 "fsub.d %0 = %F1, %F2%B0"
3417 [(set_attr "itanium_class" "fmac")])
3419 (define_insn "multf3"
3420 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3421 (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3422 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
3424 "fmpy %0 = %F1, %F2%B0"
3425 [(set_attr "itanium_class" "fmac")])
3427 (define_insn "*multf3_truncsf"
3428 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3430 (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3431 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
3433 "fmpy.s %0 = %F1, %F2%B0"
3434 [(set_attr "itanium_class" "fmac")])
3436 (define_insn "*multf3_truncdf"
3437 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3439 (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3440 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
3442 "fmpy.d %0 = %F1, %F2%B0"
3443 [(set_attr "itanium_class" "fmac")])
3445 (define_insn "*multf3_alts"
3446 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3447 (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3448 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
3449 (use (match_operand:SI 3 "const_int_operand" ""))]
3451 "fmpy.s%3 %0 = %F1, %F2%B0"
3452 [(set_attr "itanium_class" "fmac")])
3454 (define_insn "*multf3_truncsf_alts"
3455 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3457 (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3458 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))
3459 (use (match_operand:SI 3 "const_int_operand" ""))]
3461 "fmpy.s.s%3 %0 = %F1, %F2%B0"
3462 [(set_attr "itanium_class" "fmac")])
3464 (define_insn "*multf3_truncdf_alts"
3465 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3467 (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3468 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))
3469 (use (match_operand:SI 3 "const_int_operand" ""))]
3471 "fmpy.d.s%3 %0 = %F1, %F2%B0"
3472 [(set_attr "itanium_class" "fmac")])
3474 (define_insn "abstf2"
3475 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3476 (abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))]
3479 [(set_attr "itanium_class" "fmisc")])
3481 (define_insn "negtf2"
3482 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3483 (neg:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))]
3486 [(set_attr "itanium_class" "fmisc")])
3488 (define_insn "*nabstf2"
3489 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3490 (neg:TF (abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG"))))]
3492 "fnegabs %0 = %F1%B0"
3493 [(set_attr "itanium_class" "fmisc")])
3495 (define_insn "mintf3"
3496 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3497 (smin:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3498 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
3500 "fmin %0 = %F1, %F2%B0"
3501 [(set_attr "itanium_class" "fmisc")])
3503 (define_insn "maxtf3"
3504 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3505 (smax:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3506 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
3508 "fmax %0 = %F1, %F2%B0"
3509 [(set_attr "itanium_class" "fmisc")])
3511 (define_insn "*maddtf4"
3512 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3513 (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3514 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3515 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
3517 "fma %0 = %F1, %F2, %F3%B0"
3518 [(set_attr "itanium_class" "fmac")])
3520 (define_insn "*maddtf4_truncsf"
3521 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3523 (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3524 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3525 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
3527 "fma.s %0 = %F1, %F2, %F3%B0"
3528 [(set_attr "itanium_class" "fmac")])
3530 (define_insn "*maddtf4_truncdf"
3531 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3533 (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3534 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3535 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
3537 "fma.d %0 = %F1, %F2, %F3%B0"
3538 [(set_attr "itanium_class" "fmac")])
3540 (define_insn "*maddtf4_alts"
3541 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3542 (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3543 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3544 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))
3545 (use (match_operand:SI 4 "const_int_operand" ""))]
3547 "fma.s%4 %0 = %F1, %F2, %F3%B0"
3548 [(set_attr "itanium_class" "fmac")])
3550 (define_insn "*maddtf4_alts_truncdf"
3551 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3553 (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3554 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3555 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))
3556 (use (match_operand:SI 4 "const_int_operand" ""))]
3558 "fma.d.s%4 %0 = %F1, %F2, %F3%B0"
3559 [(set_attr "itanium_class" "fmac")])
3561 (define_insn "*msubtf4"
3562 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3563 (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3564 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3565 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
3567 "fms %0 = %F1, %F2, %F3%B0"
3568 [(set_attr "itanium_class" "fmac")])
3570 (define_insn "*msubtf4_truncsf"
3571 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3573 (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3574 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3575 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
3577 "fms.s %0 = %F1, %F2, %F3%B0"
3578 [(set_attr "itanium_class" "fmac")])
3580 (define_insn "*msubtf4_truncdf"
3581 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3583 (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3584 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3585 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
3587 "fms.d %0 = %F1, %F2, %F3%B0"
3588 [(set_attr "itanium_class" "fmac")])
3590 (define_insn "*nmultf3"
3591 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3592 (neg:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3593 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
3595 "fnmpy %0 = %F1, %F2%B0"
3596 [(set_attr "itanium_class" "fmac")])
3598 (define_insn "*nmultf3_truncsf"
3599 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3602 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3603 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))]
3605 "fnmpy.s %0 = %F1, %F2%B0"
3606 [(set_attr "itanium_class" "fmac")])
3608 (define_insn "*nmultf3_truncdf"
3609 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3612 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3613 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))]
3615 "fnmpy.d %0 = %F1, %F2%B0"
3616 [(set_attr "itanium_class" "fmac")])
3618 ;; ??? Is it possible to canonicalize this as (minus (reg) (mult))?
3620 (define_insn "*nmaddtf4"
3621 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3622 (plus:TF (neg:TF (mult:TF
3623 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3624 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
3625 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
3627 "fnma %0 = %F1, %F2, %F3%B0"
3628 [(set_attr "itanium_class" "fmac")])
3630 (define_insn "*nmaddtf4_truncsf"
3631 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3633 (plus:TF (neg:TF (mult:TF
3634 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3635 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
3636 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
3638 "fnma.s %0 = %F1, %F2, %F3%B0"
3639 [(set_attr "itanium_class" "fmac")])
3641 (define_insn "*nmaddtf4_truncdf"
3642 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3644 (plus:TF (neg:TF (mult:TF
3645 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3646 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
3647 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
3649 "fnma.d %0 = %F1, %F2, %F3%B0"
3650 [(set_attr "itanium_class" "fmac")])
3652 (define_insn "*nmaddtf4_alts"
3653 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3654 (plus:TF (neg:TF (mult:TF
3655 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3656 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
3657 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))
3658 (use (match_operand:SI 4 "const_int_operand" ""))]
3660 "fnma.s%4 %0 = %F1, %F2, %F3%B0"
3661 [(set_attr "itanium_class" "fmac")])
3663 (define_insn "*nmaddtf4_truncdf_alts"
3664 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3668 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3669 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
3670 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))
3671 (use (match_operand:SI 4 "const_int_operand" ""))]
3673 "fnma.d.s%4 %0 = %F1, %F2, %F3%B0"
3674 [(set_attr "itanium_class" "fmac")])
3676 (define_expand "divtf3"
3677 [(set (match_operand:TF 0 "fr_register_operand" "")
3678 (div:TF (match_operand:TF 1 "fr_register_operand" "")
3679 (match_operand:TF 2 "fr_register_operand" "")))]
3684 if (TARGET_INLINE_DIV_LAT)
3685 insn = gen_divtf3_internal_lat (operands[0], operands[1], operands[2]);
3687 insn = gen_divtf3_internal_thr (operands[0], operands[1], operands[2]);
3692 (define_insn_and_split "divtf3_internal_lat"
3693 [(set (match_operand:TF 0 "fr_register_operand" "=&f")
3694 (div:TF (match_operand:TF 1 "fr_register_operand" "f")
3695 (match_operand:TF 2 "fr_register_operand" "f")))
3696 (clobber (match_scratch:TF 3 "=&f"))
3697 (clobber (match_scratch:TF 4 "=&f"))
3698 (clobber (match_scratch:TF 5 "=&f"))
3699 (clobber (match_scratch:TF 6 "=&f"))
3700 (clobber (match_scratch:BI 7 "=c"))]
3701 "TARGET_INLINE_DIV_LAT"
3703 "&& reload_completed"
3704 [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
3705 (set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)] 5))
3706 (use (const_int 1))])
3707 (cond_exec (ne (match_dup 7) (const_int 0))
3708 (parallel [(set (match_dup 3)
3709 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
3711 (use (const_int 1))]))
3712 (cond_exec (ne (match_dup 7) (const_int 0))
3713 (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0)))
3714 (use (const_int 1))]))
3715 (cond_exec (ne (match_dup 7) (const_int 0))
3716 (parallel [(set (match_dup 5) (mult:TF (match_dup 3) (match_dup 3)))
3717 (use (const_int 1))]))
3718 (cond_exec (ne (match_dup 7) (const_int 0))
3719 (parallel [(set (match_dup 6)
3720 (plus:TF (mult:TF (match_dup 3) (match_dup 3))
3722 (use (const_int 1))]))
3723 (cond_exec (ne (match_dup 7) (const_int 0))
3724 (parallel [(set (match_dup 3)
3725 (plus:TF (mult:TF (match_dup 5) (match_dup 5))
3727 (use (const_int 1))]))
3728 (cond_exec (ne (match_dup 7) (const_int 0))
3729 (parallel [(set (match_dup 5)
3730 (plus:TF (mult:TF (match_dup 6) (match_dup 0))
3732 (use (const_int 1))]))
3733 (cond_exec (ne (match_dup 7) (const_int 0))
3734 (parallel [(set (match_dup 0)
3735 (plus:TF (mult:TF (match_dup 5) (match_dup 3))
3737 (use (const_int 1))]))
3738 (cond_exec (ne (match_dup 7) (const_int 0))
3739 (parallel [(set (match_dup 4)
3740 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 4)))
3742 (use (const_int 1))]))
3743 (cond_exec (ne (match_dup 7) (const_int 0))
3744 (parallel [(set (match_dup 3)
3745 (plus:TF (mult:TF (match_dup 3) (match_dup 0))
3747 (use (const_int 1))]))
3748 (cond_exec (ne (match_dup 7) (const_int 0))
3749 (parallel [(set (match_dup 5)
3750 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
3752 (use (const_int 1))]))
3753 (cond_exec (ne (match_dup 7) (const_int 0))
3754 (parallel [(set (match_dup 0)
3755 (plus:TF (mult:TF (match_dup 4) (match_dup 0))
3757 (use (const_int 1))]))
3758 (cond_exec (ne (match_dup 7) (const_int 0))
3759 (parallel [(set (match_dup 4)
3760 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3)))
3762 (use (const_int 1))]))
3763 (cond_exec (ne (match_dup 7) (const_int 0))
3765 (plus:TF (mult:TF (match_dup 4) (match_dup 0))
3768 "operands[8] = CONST1_RTX (TFmode);"
3769 [(set_attr "predicable" "no")])
3771 (define_insn_and_split "divtf3_internal_thr"
3772 [(set (match_operand:TF 0 "fr_register_operand" "=&f")
3773 (div:TF (match_operand:TF 1 "fr_register_operand" "f")
3774 (match_operand:TF 2 "fr_register_operand" "f")))
3775 (clobber (match_scratch:TF 3 "=&f"))
3776 (clobber (match_scratch:TF 4 "=&f"))
3777 (clobber (match_scratch:BI 5 "=c"))]
3778 "TARGET_INLINE_DIV_THR"
3780 "&& reload_completed"
3781 [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
3782 (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] 5))
3783 (use (const_int 1))])
3784 (cond_exec (ne (match_dup 5) (const_int 0))
3785 (parallel [(set (match_dup 3)
3786 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
3788 (use (const_int 1))]))
3789 (cond_exec (ne (match_dup 5) (const_int 0))
3790 (parallel [(set (match_dup 4)
3791 (plus:TF (mult:TF (match_dup 3) (match_dup 0))
3793 (use (const_int 1))]))
3794 (cond_exec (ne (match_dup 5) (const_int 0))
3795 (parallel [(set (match_dup 3) (mult:TF (match_dup 3) (match_dup 3)))
3796 (use (const_int 1))]))
3797 (cond_exec (ne (match_dup 5) (const_int 0))
3798 (parallel [(set (match_dup 3)
3799 (plus:TF (mult:TF (match_dup 3) (match_dup 4))
3801 (use (const_int 1))]))
3802 (cond_exec (ne (match_dup 5) (const_int 0))
3803 (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0)))
3804 (use (const_int 1))]))
3805 (cond_exec (ne (match_dup 5) (const_int 0))
3806 (parallel [(set (match_dup 0)
3807 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3)))
3809 (use (const_int 1))]))
3810 (cond_exec (ne (match_dup 5) (const_int 0))
3811 (parallel [(set (match_dup 0)
3812 (plus:TF (mult:TF (match_dup 0) (match_dup 3))
3814 (use (const_int 1))]))
3815 (cond_exec (ne (match_dup 5) (const_int 0))
3816 (parallel [(set (match_dup 3)
3817 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 4)))
3819 (use (const_int 1))]))
3820 (cond_exec (ne (match_dup 5) (const_int 0))
3821 (parallel [(set (match_dup 3)
3822 (plus:TF (mult:TF (match_dup 3) (match_dup 0))
3824 (use (const_int 1))]))
3825 (cond_exec (ne (match_dup 5) (const_int 0))
3826 (parallel [(set (match_dup 4)
3827 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
3829 (use (const_int 1))]))
3830 (cond_exec (ne (match_dup 5) (const_int 0))
3831 (parallel [(set (match_dup 0)
3832 (plus:TF (mult:TF (match_dup 4) (match_dup 0))
3834 (use (const_int 1))]))
3835 (cond_exec (ne (match_dup 5) (const_int 0))
3836 (parallel [(set (match_dup 4)
3837 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3)))
3839 (use (const_int 1))]))
3840 (cond_exec (ne (match_dup 5) (const_int 0))
3842 (plus:TF (mult:TF (match_dup 4) (match_dup 0))
3845 "operands[6] = CONST1_RTX (TFmode);"
3846 [(set_attr "predicable" "no")])
3848 ;; ??? frcpa works like cmp.foo.unc.
3850 (define_insn "*recip_approx"
3851 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3852 (div:TF (const_int 1)
3853 (match_operand:TF 3 "fr_register_operand" "f")))
3854 (set (match_operand:BI 1 "register_operand" "=c")
3855 (unspec:BI [(match_operand:TF 2 "fr_register_operand" "f")
3857 (use (match_operand:SI 4 "const_int_operand" ""))]
3859 "frcpa.s%4 %0, %1 = %2, %3"
3860 [(set_attr "itanium_class" "fmisc")
3861 (set_attr "predicable" "no")])
3863 ;; ::::::::::::::::::::
3865 ;; :: 32 bit Integer Shifts and Rotates
3867 ;; ::::::::::::::::::::
3869 (define_expand "ashlsi3"
3870 [(set (match_operand:SI 0 "gr_register_operand" "")
3871 (ashift:SI (match_operand:SI 1 "gr_register_operand" "")
3872 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
3876 if (GET_CODE (operands[2]) != CONST_INT)
3878 /* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED? Now
3879 we've got to get rid of stray bits outside the SImode register. */
3880 rtx subshift = gen_reg_rtx (DImode);
3881 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
3882 operands[2] = subshift;
3886 (define_insn "*ashlsi3_internal"
3887 [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r")
3888 (ashift:SI (match_operand:SI 1 "gr_register_operand" "r,r,r")
3889 (match_operand:DI 2 "gr_reg_or_5bit_operand" "R,n,r")))]
3892 shladd %0 = %1, %2, r0
3893 dep.z %0 = %1, %2, %E2
3895 [(set_attr "itanium_class" "ialu,ishf,mmshf")])
3897 (define_expand "ashrsi3"
3898 [(set (match_operand:SI 0 "gr_register_operand" "")
3899 (ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
3900 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
3904 rtx subtarget = gen_reg_rtx (DImode);
3905 if (GET_CODE (operands[2]) == CONST_INT)
3906 emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]),
3907 GEN_INT (32 - INTVAL (operands[2])), operands[2]));
3910 rtx subshift = gen_reg_rtx (DImode);
3911 emit_insn (gen_extendsidi2 (subtarget, operands[1]));
3912 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
3913 emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift));
3915 emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
3919 (define_expand "lshrsi3"
3920 [(set (match_operand:SI 0 "gr_register_operand" "")
3921 (lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
3922 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
3926 rtx subtarget = gen_reg_rtx (DImode);
3927 if (GET_CODE (operands[2]) == CONST_INT)
3928 emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]),
3929 GEN_INT (32 - INTVAL (operands[2])), operands[2]));
3932 rtx subshift = gen_reg_rtx (DImode);
3933 emit_insn (gen_zero_extendsidi2 (subtarget, operands[1]));
3934 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
3935 emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift));
3937 emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
3941 ;; Use mix4.r/shr to implement rotrsi3. We only get 32 bits of valid result
3942 ;; here, instead of 64 like the patterns above. Keep the pattern together
3943 ;; until after combine; otherwise it won't get matched often.
3945 (define_expand "rotrsi3"
3946 [(set (match_operand:SI 0 "gr_register_operand" "")
3947 (rotatert:SI (match_operand:SI 1 "gr_register_operand" "")
3948 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
3952 if (GET_MODE (operands[2]) != VOIDmode)
3954 rtx tmp = gen_reg_rtx (DImode);
3955 emit_insn (gen_zero_extendsidi2 (tmp, operands[2]));
3960 (define_insn_and_split "*rotrsi3_internal"
3961 [(set (match_operand:SI 0 "gr_register_operand" "=&r")
3962 (rotatert:SI (match_operand:SI 1 "gr_register_operand" "r")
3963 (match_operand:DI 2 "gr_reg_or_5bit_operand" "rM")))]
3968 (ior:DI (zero_extend:DI (match_dup 1))
3969 (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
3971 (lshiftrt:DI (match_dup 3) (match_dup 2)))]
3972 "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));")
3974 (define_expand "rotlsi3"
3975 [(set (match_operand:SI 0 "gr_register_operand" "")
3976 (rotate:SI (match_operand:SI 1 "gr_register_operand" "")
3977 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
3981 if (! shift_32bit_count_operand (operands[2], SImode))
3983 rtx tmp = gen_reg_rtx (SImode);
3984 emit_insn (gen_subsi3 (tmp, GEN_INT (32), operands[2]));
3985 emit_insn (gen_rotrsi3 (operands[0], operands[1], tmp));
3990 (define_insn_and_split "*rotlsi3_internal"
3991 [(set (match_operand:SI 0 "gr_register_operand" "=r")
3992 (rotate:SI (match_operand:SI 1 "gr_register_operand" "r")
3993 (match_operand:SI 2 "shift_32bit_count_operand" "n")))]
3998 (ior:DI (zero_extend:DI (match_dup 1))
3999 (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
4001 (lshiftrt:DI (match_dup 3) (match_dup 2)))]
4002 "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));
4003 operands[2] = GEN_INT (32 - INTVAL (operands[2]));")
4005 ;; ::::::::::::::::::::
4007 ;; :: 64 bit Integer Shifts and Rotates
4009 ;; ::::::::::::::::::::
4011 (define_insn "ashldi3"
4012 [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r")
4013 (ashift:DI (match_operand:DI 1 "gr_register_operand" "r,r,r")
4014 (match_operand:DI 2 "gr_reg_or_6bit_operand" "R,r,rM")))]
4017 shladd %0 = %1, %2, r0
4020 [(set_attr "itanium_class" "ialu,mmshf,mmshfi")])
4022 ;; ??? Maybe combine this with the multiply and add instruction?
4024 (define_insn "*shladd"
4025 [(set (match_operand:DI 0 "gr_register_operand" "=r")
4026 (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
4027 (match_operand:DI 2 "shladd_operand" "n"))
4028 (match_operand:DI 3 "gr_register_operand" "r")))]
4030 "shladd %0 = %1, %S2, %3"
4031 [(set_attr "itanium_class" "ialu")])
4033 ;; This can be created by register elimination if operand3 of shladd is an
4034 ;; eliminable register or has reg_equiv_constant set.
4036 ;; We have to use nonmemory_operand for operand 4, to ensure that the
4037 ;; validate_changes call inside eliminate_regs will always succeed. If it
4038 ;; doesn't succeed, then this remain a shladd pattern, and will be reloaded
4041 (define_insn_and_split "*shladd_elim"
4042 [(set (match_operand:DI 0 "gr_register_operand" "=&r")
4043 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
4044 (match_operand:DI 2 "shladd_operand" "n"))
4045 (match_operand:DI 3 "nonmemory_operand" "r"))
4046 (match_operand:DI 4 "nonmemory_operand" "rI")))]
4047 "reload_in_progress"
4050 [(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (match_dup 2))
4052 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
4054 [(set_attr "itanium_class" "unknown")])
4056 (define_insn "ashrdi3"
4057 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
4058 (ashiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r")
4059 (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))]
4064 [(set_attr "itanium_class" "mmshf,mmshfi")])
4066 (define_insn "lshrdi3"
4067 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
4068 (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r")
4069 (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))]
4074 [(set_attr "itanium_class" "mmshf,mmshfi")])
4076 ;; Using a predicate that accepts only constants doesn't work, because optabs
4077 ;; will load the operand into a register and call the pattern if the predicate
4078 ;; did not accept it on the first try. So we use nonmemory_operand and then
4079 ;; verify that we have an appropriate constant in the expander.
4081 (define_expand "rotrdi3"
4082 [(set (match_operand:DI 0 "gr_register_operand" "")
4083 (rotatert:DI (match_operand:DI 1 "gr_register_operand" "")
4084 (match_operand:DI 2 "nonmemory_operand" "")))]
4088 if (! shift_count_operand (operands[2], DImode))
4092 (define_insn "*rotrdi3_internal"
4093 [(set (match_operand:DI 0 "gr_register_operand" "=r")
4094 (rotatert:DI (match_operand:DI 1 "gr_register_operand" "r")
4095 (match_operand:DI 2 "shift_count_operand" "M")))]
4097 "shrp %0 = %1, %1, %2"
4098 [(set_attr "itanium_class" "ishf")])
4100 (define_expand "rotldi3"
4101 [(set (match_operand:DI 0 "gr_register_operand" "")
4102 (rotate:DI (match_operand:DI 1 "gr_register_operand" "")
4103 (match_operand:DI 2 "nonmemory_operand" "")))]
4107 if (! shift_count_operand (operands[2], DImode))
4111 (define_insn "*rotldi3_internal"
4112 [(set (match_operand:DI 0 "gr_register_operand" "=r")
4113 (rotate:DI (match_operand:DI 1 "gr_register_operand" "r")
4114 (match_operand:DI 2 "shift_count_operand" "M")))]
4116 "shrp %0 = %1, %1, %e2"
4117 [(set_attr "itanium_class" "ishf")])
4119 ;; ::::::::::::::::::::
4121 ;; :: 32 bit Integer Logical operations
4123 ;; ::::::::::::::::::::
4125 ;; We don't seem to need any other 32-bit logical operations, because gcc
4126 ;; generates zero-extend;zero-extend;DImode-op, which combine optimizes to
4127 ;; DImode-op;zero-extend, and then we can optimize away the zero-extend.
4128 ;; This doesn't work for unary logical operations, because we don't call
4129 ;; apply_distributive_law for them.
4131 ;; ??? Likewise, this doesn't work for andnot, which isn't handled by
4132 ;; apply_distributive_law. We get inefficient code for
4133 ;; int sub4 (int i, int j) { return i & ~j; }
4134 ;; We could convert (and (not (sign_extend A)) (sign_extend B)) to
4135 ;; (zero_extend (and (not A) B)) in combine.
4136 ;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the
4137 ;; one_cmplsi2 pattern.
4139 (define_insn "one_cmplsi2"
4140 [(set (match_operand:SI 0 "gr_register_operand" "=r")
4141 (not:SI (match_operand:SI 1 "gr_register_operand" "r")))]
4144 [(set_attr "itanium_class" "ilog")])
4146 ;; ::::::::::::::::::::
4148 ;; :: 64 bit Integer Logical operations
4150 ;; ::::::::::::::::::::
4152 (define_insn "anddi3"
4153 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
4154 (and:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
4155 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
4159 fand %0 = %2, %1%B0"
4160 [(set_attr "itanium_class" "ilog,fmisc")])
4162 (define_insn "*andnot"
4163 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
4164 (and:DI (not:DI (match_operand:DI 1 "grfr_register_operand" "r,*f"))
4165 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
4169 fandcm %0 = %2, %1%B0"
4170 [(set_attr "itanium_class" "ilog,fmisc")])
4172 (define_insn "iordi3"
4173 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
4174 (ior:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
4175 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
4180 [(set_attr "itanium_class" "ilog,fmisc")])
4182 (define_insn "xordi3"
4183 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
4184 (xor:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
4185 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
4189 fxor %0 = %2, %1%B0"
4190 [(set_attr "itanium_class" "ilog,fmisc")])
4192 (define_insn "one_cmpldi2"
4193 [(set (match_operand:DI 0 "gr_register_operand" "=r")
4194 (not:DI (match_operand:DI 1 "gr_register_operand" "r")))]
4197 [(set_attr "itanium_class" "ilog")])
4199 ;; ::::::::::::::::::::
4203 ;; ::::::::::::::::::::
4205 (define_expand "cmpbi"
4207 (compare (match_operand:BI 0 "register_operand" "")
4208 (match_operand:BI 1 "const_int_operand" "")))]
4212 ia64_compare_op0 = operands[0];
4213 ia64_compare_op1 = operands[1];
4217 (define_expand "cmpsi"
4219 (compare (match_operand:SI 0 "gr_register_operand" "")
4220 (match_operand:SI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))]
4224 ia64_compare_op0 = operands[0];
4225 ia64_compare_op1 = operands[1];
4229 (define_expand "cmpdi"
4231 (compare (match_operand:DI 0 "gr_register_operand" "")
4232 (match_operand:DI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))]
4236 ia64_compare_op0 = operands[0];
4237 ia64_compare_op1 = operands[1];
4241 (define_expand "cmpsf"
4243 (compare (match_operand:SF 0 "fr_reg_or_fp01_operand" "")
4244 (match_operand:SF 1 "fr_reg_or_fp01_operand" "")))]
4248 ia64_compare_op0 = operands[0];
4249 ia64_compare_op1 = operands[1];
4253 (define_expand "cmpdf"
4255 (compare (match_operand:DF 0 "fr_reg_or_fp01_operand" "")
4256 (match_operand:DF 1 "fr_reg_or_fp01_operand" "")))]
4260 ia64_compare_op0 = operands[0];
4261 ia64_compare_op1 = operands[1];
4265 (define_expand "cmptf"
4267 (compare (match_operand:TF 0 "tfreg_or_fp01_operand" "")
4268 (match_operand:TF 1 "tfreg_or_fp01_operand" "")))]
4272 ia64_compare_op0 = operands[0];
4273 ia64_compare_op1 = operands[1];
4277 (define_insn "*cmpsi_normal"
4278 [(set (match_operand:BI 0 "register_operand" "=c")
4279 (match_operator:BI 1 "normal_comparison_operator"
4280 [(match_operand:SI 2 "gr_register_operand" "r")
4281 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))]
4283 "cmp4.%C1 %0, %I0 = %3, %2"
4284 [(set_attr "itanium_class" "icmp")])
4286 ;; We use %r3 because it is possible for us to match a 0, and two of the
4287 ;; unsigned comparisons don't accept immediate operands of zero.
4289 (define_insn "*cmpsi_adjusted"
4290 [(set (match_operand:BI 0 "register_operand" "=c")
4291 (match_operator:BI 1 "adjusted_comparison_operator"
4292 [(match_operand:SI 2 "gr_register_operand" "r")
4293 (match_operand:SI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
4295 "cmp4.%C1 %0, %I0 = %r3, %2"
4296 [(set_attr "itanium_class" "icmp")])
4298 (define_insn "*cmpdi_normal"
4299 [(set (match_operand:BI 0 "register_operand" "=c")
4300 (match_operator:BI 1 "normal_comparison_operator"
4301 [(match_operand:DI 2 "gr_reg_or_0_operand" "rO")
4302 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))]
4304 "cmp.%C1 %0, %I0 = %3, %r2"
4305 [(set_attr "itanium_class" "icmp")])
4307 ;; We use %r3 because it is possible for us to match a 0, and two of the
4308 ;; unsigned comparisons don't accept immediate operands of zero.
4310 (define_insn "*cmpdi_adjusted"
4311 [(set (match_operand:BI 0 "register_operand" "=c")
4312 (match_operator:BI 1 "adjusted_comparison_operator"
4313 [(match_operand:DI 2 "gr_register_operand" "r")
4314 (match_operand:DI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
4316 "cmp.%C1 %0, %I0 = %r3, %2"
4317 [(set_attr "itanium_class" "icmp")])
4319 (define_insn "*cmpsf_internal"
4320 [(set (match_operand:BI 0 "register_operand" "=c")
4321 (match_operator:BI 1 "comparison_operator"
4322 [(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")
4323 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")]))]
4325 "fcmp.%D1 %0, %I0 = %F2, %F3"
4326 [(set_attr "itanium_class" "fcmp")])
4328 (define_insn "*cmpdf_internal"
4329 [(set (match_operand:BI 0 "register_operand" "=c")
4330 (match_operator:BI 1 "comparison_operator"
4331 [(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")
4332 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")]))]
4334 "fcmp.%D1 %0, %I0 = %F2, %F3"
4335 [(set_attr "itanium_class" "fcmp")])
4337 (define_insn "*cmptf_internal"
4338 [(set (match_operand:BI 0 "register_operand" "=c")
4339 (match_operator:BI 1 "comparison_operator"
4340 [(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")
4341 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")]))]
4343 "fcmp.%D1 %0, %I0 = %F2, %F3"
4344 [(set_attr "itanium_class" "fcmp")])
4346 ;; ??? Can this pattern be generated?
4348 (define_insn "*bit_zero"
4349 [(set (match_operand:BI 0 "register_operand" "=c")
4350 (eq:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
4352 (match_operand:DI 2 "immediate_operand" "n"))
4355 "tbit.z %0, %I0 = %1, %2"
4356 [(set_attr "itanium_class" "tbit")])
4358 (define_insn "*bit_one"
4359 [(set (match_operand:BI 0 "register_operand" "=c")
4360 (ne:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
4362 (match_operand:DI 2 "immediate_operand" "n"))
4365 "tbit.nz %0, %I0 = %1, %2"
4366 [(set_attr "itanium_class" "tbit")])
4368 ;; ::::::::::::::::::::
4372 ;; ::::::::::::::::::::
4374 (define_expand "beq"
4376 (if_then_else (match_dup 1)
4377 (label_ref (match_operand 0 "" ""))
4380 "operands[1] = ia64_expand_compare (EQ, VOIDmode);")
4382 (define_expand "bne"
4384 (if_then_else (match_dup 1)
4385 (label_ref (match_operand 0 "" ""))
4388 "operands[1] = ia64_expand_compare (NE, VOIDmode);")
4390 (define_expand "blt"
4392 (if_then_else (match_dup 1)
4393 (label_ref (match_operand 0 "" ""))
4396 "operands[1] = ia64_expand_compare (LT, VOIDmode);")
4398 (define_expand "ble"
4400 (if_then_else (match_dup 1)
4401 (label_ref (match_operand 0 "" ""))
4404 "operands[1] = ia64_expand_compare (LE, VOIDmode);")
4406 (define_expand "bgt"
4408 (if_then_else (match_dup 1)
4409 (label_ref (match_operand 0 "" ""))
4412 "operands[1] = ia64_expand_compare (GT, VOIDmode);")
4414 (define_expand "bge"
4416 (if_then_else (match_dup 1)
4417 (label_ref (match_operand 0 "" ""))
4420 "operands[1] = ia64_expand_compare (GE, VOIDmode);")
4422 (define_expand "bltu"
4424 (if_then_else (match_dup 1)
4425 (label_ref (match_operand 0 "" ""))
4428 "operands[1] = ia64_expand_compare (LTU, VOIDmode);")
4430 (define_expand "bleu"
4432 (if_then_else (match_dup 1)
4433 (label_ref (match_operand 0 "" ""))
4436 "operands[1] = ia64_expand_compare (LEU, VOIDmode);")
4438 (define_expand "bgtu"
4440 (if_then_else (match_dup 1)
4441 (label_ref (match_operand 0 "" ""))
4444 "operands[1] = ia64_expand_compare (GTU, VOIDmode);")
4446 (define_expand "bgeu"
4448 (if_then_else (match_dup 1)
4449 (label_ref (match_operand 0 "" ""))
4452 "operands[1] = ia64_expand_compare (GEU, VOIDmode);")
4454 (define_expand "bunordered"
4456 (if_then_else (match_dup 1)
4457 (label_ref (match_operand 0 "" ""))
4460 "operands[1] = ia64_expand_compare (UNORDERED, VOIDmode);")
4462 (define_expand "bordered"
4464 (if_then_else (match_dup 1)
4465 (label_ref (match_operand 0 "" ""))
4468 "operands[1] = ia64_expand_compare (ORDERED, VOIDmode);")
4470 (define_insn "*br_true"
4472 (if_then_else (match_operator 0 "predicate_operator"
4473 [(match_operand:BI 1 "register_operand" "c")
4475 (label_ref (match_operand 2 "" ""))
4478 "(%J0) br.cond%+ %l2"
4479 [(set_attr "itanium_class" "br")
4480 (set_attr "predicable" "no")])
4482 (define_insn "*br_false"
4484 (if_then_else (match_operator 0 "predicate_operator"
4485 [(match_operand:BI 1 "register_operand" "c")
4488 (label_ref (match_operand 2 "" ""))))]
4490 "(%j0) br.cond%+ %l2"
4491 [(set_attr "itanium_class" "br")
4492 (set_attr "predicable" "no")])
4494 ;; ::::::::::::::::::::
4496 ;; :: Counted loop operations
4498 ;; ::::::::::::::::::::
4500 (define_expand "doloop_end"
4501 [(use (match_operand 0 "" "")) ; loop pseudo
4502 (use (match_operand 1 "" "")) ; iterations; zero if unknown
4503 (use (match_operand 2 "" "")) ; max iterations
4504 (use (match_operand 3 "" "")) ; loop level
4505 (use (match_operand 4 "" ""))] ; label
4509 /* Only use cloop on innermost loops. */
4510 if (INTVAL (operands[3]) > 1)
4512 emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM),
4517 (define_insn "doloop_end_internal"
4518 [(set (pc) (if_then_else (ne (match_operand:DI 0 "ar_lc_reg_operand" "")
4520 (label_ref (match_operand 1 "" ""))
4522 (set (match_dup 0) (if_then_else:DI (ne (match_dup 0) (const_int 0))
4524 (plus:DI (match_dup 0) (const_int -1))))]
4526 "br.cloop.sptk.few %l1"
4527 [(set_attr "itanium_class" "br")
4528 (set_attr "predicable" "no")])
4530 ;; ::::::::::::::::::::
4532 ;; :: Set flag operations
4534 ;; ::::::::::::::::::::
4536 (define_expand "seq"
4537 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4539 "operands[1] = ia64_expand_compare (EQ, DImode);")
4541 (define_expand "sne"
4542 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4544 "operands[1] = ia64_expand_compare (NE, DImode);")
4546 (define_expand "slt"
4547 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4549 "operands[1] = ia64_expand_compare (LT, DImode);")
4551 (define_expand "sle"
4552 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4554 "operands[1] = ia64_expand_compare (LE, DImode);")
4556 (define_expand "sgt"
4557 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4559 "operands[1] = ia64_expand_compare (GT, DImode);")
4561 (define_expand "sge"
4562 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4564 "operands[1] = ia64_expand_compare (GE, DImode);")
4566 (define_expand "sltu"
4567 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4569 "operands[1] = ia64_expand_compare (LTU, DImode);")
4571 (define_expand "sleu"
4572 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4574 "operands[1] = ia64_expand_compare (LEU, DImode);")
4576 (define_expand "sgtu"
4577 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4579 "operands[1] = ia64_expand_compare (GTU, DImode);")
4581 (define_expand "sgeu"
4582 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4584 "operands[1] = ia64_expand_compare (GEU, DImode);")
4586 (define_expand "sunordered"
4587 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4589 "operands[1] = ia64_expand_compare (UNORDERED, DImode);")
4591 (define_expand "sordered"
4592 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4594 "operands[1] = ia64_expand_compare (ORDERED, DImode);")
4596 ;; Don't allow memory as destination here, because cmov/cmov/st is more
4597 ;; efficient than mov/mov/cst/cst.
4599 (define_insn_and_split "*sne_internal"
4600 [(set (match_operand:DI 0 "gr_register_operand" "=r")
4601 (ne:DI (match_operand:BI 1 "register_operand" "c")
4606 [(cond_exec (ne (match_dup 1) (const_int 0))
4607 (set (match_dup 0) (const_int 1)))
4608 (cond_exec (eq (match_dup 1) (const_int 0))
4609 (set (match_dup 0) (const_int 0)))]
4611 [(set_attr "itanium_class" "unknown")])
4613 (define_insn_and_split "*seq_internal"
4614 [(set (match_operand:DI 0 "gr_register_operand" "=r")
4615 (eq:DI (match_operand:BI 1 "register_operand" "c")
4620 [(cond_exec (ne (match_dup 1) (const_int 0))
4621 (set (match_dup 0) (const_int 0)))
4622 (cond_exec (eq (match_dup 1) (const_int 0))
4623 (set (match_dup 0) (const_int 1)))]
4625 [(set_attr "itanium_class" "unknown")])
4627 ;; ::::::::::::::::::::
4629 ;; :: Conditional move instructions.
4631 ;; ::::::::::::::::::::
4633 ;; ??? Add movXXcc patterns?
4636 ;; DImode if_then_else patterns.
4639 ;; Errata 72 workaround.
4640 (define_insn "*cmovdi_internal_astep"
4641 [(set (match_operand:DI 0 "register_operand"
4642 "=r, r, r, r, r, r, r, r, r, r,*f,*b,*d*e")
4644 (match_operator 4 "predicate_operator"
4645 [(match_operand:BI 1 "register_operand"
4646 " c, c, c, c, c, c, c, c, c, c, c, c, c")
4648 (match_operand:DI 2 "move_operand"
4649 "ri,*f,*b,*d*e,ri,ri, ri,*f,*b,*d*e,rO,rO, rK")
4650 (match_operand:DI 3 "move_operand"
4651 "ri,ri,ri, ri,*f,*b,*d*e,*f,*b,*d*e,rO,rO, rK")))]
4653 && ia64_move_ok (operands[0], operands[2])
4654 && ia64_move_ok (operands[0], operands[3])"
4656 [(set_attr "predicable" "no")])
4658 (define_insn "*cmovdi_internal"
4659 [(set (match_operand:DI 0 "destination_operand"
4660 "= r, r, r, r, r, r, r, r, r, r, m, Q, *f,*b,*d*e")
4662 (match_operator 4 "predicate_operator"
4663 [(match_operand:BI 1 "register_operand"
4664 "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c")
4666 (match_operand:DI 2 "move_operand"
4667 "rim, *f, *b,*d*e,rim,rim, rim,*f,*b,*d*e,rO,*f,rOQ,rO, rK")
4668 (match_operand:DI 3 "move_operand"
4669 "rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))]
4671 && ia64_move_ok (operands[0], operands[2])
4672 && ia64_move_ok (operands[0], operands[3])"
4674 [(set_attr "predicable" "no")])
4677 [(set (match_operand 0 "destination_operand" "")
4679 (match_operator 4 "predicate_operator"
4680 [(match_operand:BI 1 "register_operand" "")
4682 (match_operand 2 "move_operand" "")
4683 (match_operand 3 "move_operand" "")))]
4689 if (! rtx_equal_p (operands[0], operands[2]))
4691 tmp = gen_rtx_SET (VOIDmode, operands[0], operands[2]);
4692 tmp = gen_rtx_COND_EXEC (VOIDmode, operands[4], tmp);
4695 if (! rtx_equal_p (operands[0], operands[3]))
4697 tmp = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
4698 VOIDmode, operands[1], const0_rtx);
4699 tmp = gen_rtx_COND_EXEC (VOIDmode, tmp,
4700 gen_rtx_SET (VOIDmode, operands[0],
4707 ;; Absolute value pattern.
4709 (define_insn "*absdi2_internal"
4710 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
4712 (match_operator 4 "predicate_operator"
4713 [(match_operand:BI 1 "register_operand" "c,c")
4715 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "rI,rI"))
4716 (match_operand:DI 3 "gr_reg_or_22bit_operand" "0,rI")))]
4719 [(set_attr "itanium_class" "ialu,unknown")
4720 (set_attr "predicable" "no")])
4723 [(set (match_operand:DI 0 "register_operand" "")
4725 (match_operator 4 "predicate_operator"
4726 [(match_operand:BI 1 "register_operand" "c,c")
4728 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" ""))
4729 (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))]
4730 "reload_completed && rtx_equal_p (operands[0], operands[3])"
4734 (neg:DI (match_dup 2))))]
4738 [(set (match_operand:DI 0 "register_operand" "")
4740 (match_operator 4 "predicate_operator"
4741 [(match_operand:BI 1 "register_operand" "c,c")
4743 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" ""))
4744 (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))]
4748 (set (match_dup 0) (neg:DI (match_dup 2))))
4751 (set (match_dup 0) (match_dup 3)))]
4754 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
4755 VOIDmode, operands[1], const0_rtx);
4759 ;; SImode if_then_else patterns.
4762 (define_insn "*cmovsi_internal_astep"
4763 [(set (match_operand:SI 0 "register_operand" "=r,*f,r,*f,r,*f")
4765 (match_operator 4 "predicate_operator"
4766 [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c")
4768 (match_operand:SI 2 "move_operand" "0,0,ri*f,rO,ri*f,rO")
4769 (match_operand:SI 3 "move_operand" "ri*f,rO,0,0,ri*f,rO")))]
4771 && ia64_move_ok (operands[0], operands[2])
4772 && ia64_move_ok (operands[0], operands[3])"
4774 [(set_attr "predicable" "no")])
4776 (define_insn "*cmovsi_internal"
4777 [(set (match_operand:SI 0 "destination_operand" "=r,m,*f,r,m,*f,r,m,*f")
4779 (match_operator 4 "predicate_operator"
4780 [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c,c,c,c")
4782 (match_operand:SI 2 "move_operand"
4783 "0,0,0,rim*f,rO,rO,rim*f,rO,rO")
4784 (match_operand:SI 3 "move_operand"
4785 "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))]
4787 && ia64_move_ok (operands[0], operands[2])
4788 && ia64_move_ok (operands[0], operands[3])"
4790 [(set_attr "predicable" "no")])
4792 (define_insn "*abssi2_internal"
4793 [(set (match_operand:SI 0 "gr_register_operand" "=r,r")
4795 (match_operator 4 "predicate_operator"
4796 [(match_operand:BI 1 "register_operand" "c,c")
4798 (neg:SI (match_operand:SI 3 "gr_reg_or_22bit_operand" "rI,rI"))
4799 (match_operand:SI 2 "gr_reg_or_22bit_operand" "0,rI")))]
4802 [(set_attr "itanium_class" "ialu,unknown")
4803 (set_attr "predicable" "no")])
4806 [(set (match_operand:SI 0 "register_operand" "")
4808 (match_operator 4 "predicate_operator"
4809 [(match_operand:BI 1 "register_operand" "c,c")
4811 (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" ""))
4812 (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))]
4813 "reload_completed && rtx_equal_p (operands[0], operands[3])"
4817 (neg:SI (match_dup 2))))]
4821 [(set (match_operand:SI 0 "register_operand" "")
4823 (match_operator 4 "predicate_operator"
4824 [(match_operand:BI 1 "register_operand" "c,c")
4826 (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" ""))
4827 (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))]
4831 (set (match_dup 0) (neg:SI (match_dup 2))))
4834 (set (match_dup 0) (match_dup 3)))]
4837 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
4838 VOIDmode, operands[1], const0_rtx);
4842 ;; ::::::::::::::::::::
4844 ;; :: Call and branch instructions
4846 ;; ::::::::::::::::::::
4848 ;; Subroutine call instruction returning no value. Operand 0 is the function
4849 ;; to call; operand 1 is the number of bytes of arguments pushed (in mode
4850 ;; `SImode', except it is normally a `const_int'); operand 2 is the number of
4851 ;; registers used as operands.
4853 ;; On most machines, operand 2 is not actually stored into the RTL pattern. It
4854 ;; is supplied for the sake of some RISC machines which need to put this
4855 ;; information into the assembler code; they can put it in the RTL instead of
4858 (define_expand "call"
4859 [(use (match_operand:DI 0 "" ""))
4860 (use (match_operand 1 "" ""))
4861 (use (match_operand 2 "" ""))
4862 (use (match_operand 3 "" ""))]
4866 ia64_expand_call (NULL_RTX, operands[0], operands[2], 0);
4870 (define_expand "sibcall"
4871 [(use (match_operand:DI 0 "" ""))
4872 (use (match_operand 1 "" ""))
4873 (use (match_operand 2 "" ""))
4874 (use (match_operand 3 "" ""))]
4878 ia64_expand_call (NULL_RTX, operands[0], operands[2], 1);
4882 ;; Subroutine call instruction returning a value. Operand 0 is the hard
4883 ;; register in which the value is returned. There are three more operands,
4884 ;; the same as the three operands of the `call' instruction (but with numbers
4885 ;; increased by one).
4887 ;; Subroutines that return `BLKmode' objects use the `call' insn.
4889 (define_expand "call_value"
4890 [(use (match_operand 0 "" ""))
4891 (use (match_operand:DI 1 "" ""))
4892 (use (match_operand 2 "" ""))
4893 (use (match_operand 3 "" ""))
4894 (use (match_operand 4 "" ""))]
4898 ia64_expand_call (operands[0], operands[1], operands[3], 0);
4902 (define_expand "sibcall_value"
4903 [(use (match_operand 0 "" ""))
4904 (use (match_operand:DI 1 "" ""))
4905 (use (match_operand 2 "" ""))
4906 (use (match_operand 3 "" ""))
4907 (use (match_operand 4 "" ""))]
4911 ia64_expand_call (operands[0], operands[1], operands[3], 1);
4915 ;; Call subroutine returning any type.
4917 (define_expand "untyped_call"
4918 [(parallel [(call (match_operand 0 "" "")
4920 (match_operand 1 "" "")
4921 (match_operand 2 "" "")])]
4927 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
4929 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4931 rtx set = XVECEXP (operands[2], 0, i);
4932 emit_move_insn (SET_DEST (set), SET_SRC (set));
4935 /* The optimizer does not know that the call sets the function value
4936 registers we stored in the result block. We avoid problems by
4937 claiming that all hard registers are used and clobbered at this
4939 emit_insn (gen_blockage ());
4944 (define_insn "call_nopic"
4945 [(call (mem:DI (match_operand:DI 0 "call_operand" "b,i"))
4946 (match_operand 1 "" ""))
4947 (clobber (match_operand:DI 2 "register_operand" "=b,b"))]
4949 "br.call%+.many %2 = %0"
4950 [(set_attr "itanium_class" "br,scall")])
4952 (define_insn "call_value_nopic"
4953 [(set (match_operand 0 "" "")
4954 (call (mem:DI (match_operand:DI 1 "call_operand" "b,i"))
4955 (match_operand 2 "" "")))
4956 (clobber (match_operand:DI 3 "register_operand" "=b,b"))]
4958 "br.call%+.many %3 = %1"
4959 [(set_attr "itanium_class" "br,scall")])
4961 (define_insn "sibcall_nopic"
4962 [(call (mem:DI (match_operand:DI 0 "call_operand" "b,i"))
4963 (match_operand 1 "" ""))
4964 (use (match_operand:DI 2 "register_operand" "=b,b"))]
4967 [(set_attr "itanium_class" "br,scall")])
4969 (define_insn "call_pic"
4970 [(call (mem:DI (match_operand:DI 0 "call_operand" "b,i"))
4971 (match_operand 1 "" ""))
4972 (use (unspec [(reg:DI 1)] 9))
4973 (clobber (match_operand:DI 2 "register_operand" "=b,b"))]
4975 "br.call%+.many %2 = %0"
4976 [(set_attr "itanium_class" "br,scall")])
4978 (define_insn "call_value_pic"
4979 [(set (match_operand 0 "" "")
4980 (call (mem:DI (match_operand:DI 1 "call_operand" "b,i"))
4981 (match_operand 2 "" "")))
4982 (use (unspec [(reg:DI 1)] 9))
4983 (clobber (match_operand:DI 3 "register_operand" "=b,b"))]
4985 "br.call%+.many %3 = %1"
4986 [(set_attr "itanium_class" "br,scall")])
4988 (define_insn "sibcall_pic"
4989 [(call (mem:DI (match_operand:DI 0 "call_operand" "bi"))
4990 (match_operand 1 "" ""))
4991 (use (unspec [(reg:DI 1)] 9))
4992 (use (match_operand:DI 2 "register_operand" "=b"))]
4995 [(set_attr "itanium_class" "br")])
4997 (define_insn "return_internal"
4999 (use (match_operand:DI 0 "register_operand" "b"))]
5001 "br.ret.sptk.many %0"
5002 [(set_attr "itanium_class" "br")])
5004 (define_insn "return"
5006 "ia64_direct_return ()"
5007 "br.ret.sptk.many rp"
5008 [(set_attr "itanium_class" "br")])
5010 (define_insn "*return_true"
5012 (if_then_else (match_operator 0 "predicate_operator"
5013 [(match_operand:BI 1 "register_operand" "c")
5017 "ia64_direct_return ()"
5018 "(%J0) br.ret%+.many rp"
5019 [(set_attr "itanium_class" "br")
5020 (set_attr "predicable" "no")])
5022 (define_insn "*return_false"
5024 (if_then_else (match_operator 0 "predicate_operator"
5025 [(match_operand:BI 1 "register_operand" "c")
5029 "ia64_direct_return ()"
5030 "(%j0) br.ret%+.many rp"
5031 [(set_attr "itanium_class" "br")
5032 (set_attr "predicable" "no")])
5035 [(set (pc) (label_ref (match_operand 0 "" "")))]
5038 [(set_attr "itanium_class" "br")])
5040 (define_insn "indirect_jump"
5041 [(set (pc) (match_operand:DI 0 "register_operand" "b"))]
5044 [(set_attr "itanium_class" "br")])
5046 (define_expand "tablejump"
5047 [(match_operand:DI 0 "register_operand" "")
5048 (match_operand 1 "" "")]
5052 rtx tmp1 = gen_reg_rtx (DImode);
5053 rtx tmp2 = gen_reg_rtx (DImode);
5055 emit_move_insn (tmp1, gen_rtx_LABEL_REF (Pmode, operands[1]));
5056 emit_insn (gen_adddi3 (tmp2, operands[0], tmp1));
5057 emit_jump_insn (gen_tablejump_internal (tmp2, operands[1]));
5061 (define_insn "tablejump_internal"
5062 [(set (pc) (match_operand:DI 0 "register_operand" "b"))
5063 (use (label_ref (match_operand 1 "" "")))]
5066 [(set_attr "itanium_class" "br")])
5069 ;; ::::::::::::::::::::
5071 ;; :: Prologue and Epilogue instructions
5073 ;; ::::::::::::::::::::
5075 (define_expand "prologue"
5080 ia64_expand_prologue ();
5084 (define_expand "epilogue"
5089 ia64_expand_epilogue (0);
5093 (define_expand "sibcall_epilogue"
5098 ia64_expand_epilogue (1);
5102 ;; This prevents the scheduler from moving the SP decrement past FP-relative
5103 ;; stack accesses. This is the same as adddi3 plus the extra set.
5105 (define_insn "prologue_allocate_stack"
5106 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
5107 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,a")
5108 (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))
5109 (set (match_operand:DI 3 "register_operand" "=r,r,r")
5116 [(set_attr "itanium_class" "ialu")])
5118 ;; This prevents the scheduler from moving the SP restore past FP-relative
5119 ;; stack accesses. This is similar to movdi plus the extra set.
5121 (define_insn "epilogue_deallocate_stack"
5122 [(set (match_operand:DI 0 "register_operand" "=r")
5123 (match_operand:DI 1 "register_operand" "+r"))
5124 (set (match_dup 1) (match_dup 1))]
5127 [(set_attr "itanium_class" "ialu")])
5129 ;; Allocate a new register frame.
5131 (define_insn "alloc"
5132 [(set (match_operand:DI 0 "register_operand" "=r")
5133 (unspec_volatile:DI [(const_int 0)] 0))
5134 (use (match_operand:DI 1 "const_int_operand" "i"))
5135 (use (match_operand:DI 2 "const_int_operand" "i"))
5136 (use (match_operand:DI 3 "const_int_operand" "i"))
5137 (use (match_operand:DI 4 "const_int_operand" "i"))]
5139 "alloc %0 = ar.pfs, %1, %2, %3, %4"
5140 [(set_attr "itanium_class" "syst_m0")
5141 (set_attr "predicable" "no")])
5144 (define_expand "gr_spill"
5145 [(parallel [(set (match_operand:DI 0 "memory_operand" "=m")
5146 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5147 (match_operand:DI 2 "const_int_operand" "")] 1))
5148 (clobber (match_dup 3))])]
5150 "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
5152 (define_insn "gr_spill_internal"
5153 [(set (match_operand:DI 0 "memory_operand" "=m")
5154 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5155 (match_operand:DI 2 "const_int_operand" "")] 1))
5156 (clobber (match_operand:DI 3 "register_operand" ""))]
5160 return \".mem.offset %2, 0\;%,st8.spill %0 = %1%P0\";
5162 [(set_attr "itanium_class" "st")])
5165 (define_expand "gr_restore"
5166 [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
5167 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
5168 (match_operand:DI 2 "const_int_operand" "")] 2))
5169 (use (match_dup 3))])]
5171 "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
5173 (define_insn "gr_restore_internal"
5174 [(set (match_operand:DI 0 "register_operand" "=r")
5175 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
5176 (match_operand:DI 2 "const_int_operand" "")] 2))
5177 (use (match_operand:DI 3 "register_operand" ""))]
5181 return \".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1\";
5183 [(set_attr "itanium_class" "ld")])
5185 (define_insn "fr_spill"
5186 [(set (match_operand:TF 0 "memory_operand" "=m")
5187 (unspec:TF [(match_operand:TF 1 "register_operand" "f")] 3))]
5189 "stf.spill %0 = %1%P0"
5190 [(set_attr "itanium_class" "stf")])
5192 (define_insn "fr_restore"
5193 [(set (match_operand:TF 0 "register_operand" "=f")
5194 (unspec:TF [(match_operand:TF 1 "memory_operand" "m")] 4))]
5196 "ldf.fill %0 = %1%P1"
5197 [(set_attr "itanium_class" "fld")])
5199 (define_insn "bsp_value"
5200 [(set (match_operand:DI 0 "register_operand" "=r")
5201 (unspec:DI [(const_int 0)] 20))]
5204 [(set_attr "itanium_class" "frar_i")])
5206 (define_insn "set_bsp"
5207 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 5)]
5209 "flushrs\;mov r19=ar.rsc\;;;\;and r19=0x1c,r19\;;;\;mov ar.rsc=r19\;;;\;mov ar.bspstore=%0\;;;\;or r19=0x3,r19\;;;\;loadrs\;invala\;;;\;mov ar.rsc=r19"
5210 [(set_attr "itanium_class" "unknown")
5211 (set_attr "predicable" "no")])
5213 (define_insn "flushrs"
5214 [(unspec [(const_int 0)] 21)]
5217 [(set_attr "itanium_class" "rse_m")])
5219 ;; ::::::::::::::::::::
5221 ;; :: Miscellaneous instructions
5223 ;; ::::::::::::::::::::
5225 ;; ??? Emiting a NOP instruction isn't very useful. This should probably
5226 ;; be emitting ";;" to force a break in the instruction packing.
5228 ;; No operation, needed in case the user uses -g but not -O.
5233 [(set_attr "itanium_class" "unknown")])
5235 (define_insn "nop_m"
5239 [(set_attr "itanium_class" "nop_m")])
5241 (define_insn "nop_i"
5245 [(set_attr "itanium_class" "nop_i")])
5247 (define_insn "nop_f"
5251 [(set_attr "itanium_class" "nop_f")])
5253 (define_insn "nop_b"
5257 [(set_attr "itanium_class" "nop_b")])
5259 (define_insn "nop_x"
5263 [(set_attr "itanium_class" "nop_x")])
5265 (define_expand "cycle_display"
5266 [(unspec [(match_operand 0 "const_int_operand" "")] 23)]
5267 "ia64_final_schedule"
5270 (define_insn "*cycle_display_1"
5271 [(unspec [(match_operand 0 "const_int_operand" "")] 23)]
5274 [(set_attr "itanium_class" "ignore")
5275 (set_attr "predicable" "no")])
5277 (define_insn "bundle_selector"
5278 [(unspec [(match_operand 0 "const_int_operand" "")] 22)]
5282 return get_bundle_name (INTVAL (operands[0]));
5284 [(set_attr "itanium_class" "ignore")
5285 (set_attr "predicable" "no")])
5287 ;; Pseudo instruction that prevents the scheduler from moving code above this
5289 (define_insn "blockage"
5290 [(unspec_volatile [(const_int 0)] 1)]
5293 [(set_attr "itanium_class" "ignore")
5294 (set_attr "predicable" "no")])
5296 (define_insn "insn_group_barrier"
5297 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] 2)]
5300 [(set_attr "itanium_class" "stop_bit")
5301 (set_attr "predicable" "no")])
5304 ;; Non-local goto support.
5306 (define_expand "save_stack_nonlocal"
5307 [(use (match_operand:OI 0 "memory_operand" ""))
5308 (use (match_operand:DI 1 "register_operand" ""))]
5312 emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
5313 \"__ia64_save_stack_nonlocal\"),
5314 0, VOIDmode, 2, XEXP (operands[0], 0), Pmode,
5315 operands[1], Pmode);
5319 (define_expand "nonlocal_goto"
5320 [(use (match_operand 0 "general_operand" ""))
5321 (use (match_operand 1 "general_operand" ""))
5322 (use (match_operand 2 "general_operand" ""))
5323 (use (match_operand 3 "general_operand" ""))]
5327 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"),
5330 copy_to_reg (XEXP (operands[2], 0)), Pmode,
5331 operands[3], Pmode);
5336 ;; Restore the GP after the exception/longjmp. The preceeding call will
5337 ;; have tucked it away.
5338 (define_expand "exception_receiver"
5339 [(set (reg:DI 1) (match_dup 0))]
5341 "operands[0] = ia64_gp_save_reg (0);")
5343 ;; The rest of the setjmp processing happens with the nonlocal_goto expander.
5344 ;; ??? This is not tested.
5345 (define_expand "builtin_setjmp_setup"
5346 [(use (match_operand:DI 0 "" ""))]
5350 emit_move_insn (ia64_gp_save_reg (0), gen_rtx_REG (DImode, GR_REG (1)));
5354 (define_expand "builtin_setjmp_receiver"
5355 [(use (match_operand:DI 0 "" ""))]
5359 emit_move_insn (gen_rtx_REG (DImode, GR_REG (1)), ia64_gp_save_reg (0));
5363 (define_expand "eh_epilogue"
5364 [(use (match_operand:DI 0 "register_operand" "r"))
5365 (use (match_operand:DI 1 "register_operand" "r"))
5366 (use (match_operand:DI 2 "register_operand" "r"))]
5370 rtx bsp = gen_rtx_REG (Pmode, 10);
5371 rtx sp = gen_rtx_REG (Pmode, 9);
5373 if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 10)
5375 emit_move_insn (bsp, operands[0]);
5378 if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 9)
5380 emit_move_insn (sp, operands[2]);
5383 emit_insn (gen_rtx_USE (VOIDmode, sp));
5384 emit_insn (gen_rtx_USE (VOIDmode, bsp));
5386 cfun->machine->ia64_eh_epilogue_sp = sp;
5387 cfun->machine->ia64_eh_epilogue_bsp = bsp;
5390 ;; Builtin apply support.
5392 (define_expand "restore_stack_nonlocal"
5393 [(use (match_operand:DI 0 "register_operand" ""))
5394 (use (match_operand:OI 1 "memory_operand" ""))]
5398 emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
5399 \"__ia64_restore_stack_nonlocal\"),
5401 copy_to_reg (XEXP (operands[1], 0)), Pmode);
5406 ;;; Intrinsics support.
5409 [(set (mem:BLK (match_dup 0))
5410 (unspec:BLK [(mem:BLK (match_dup 0))] 12))]
5414 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
5415 MEM_VOLATILE_P (operands[0]) = 1;
5418 (define_insn "*mf_internal"
5419 [(set (match_operand:BLK 0 "" "")
5420 (unspec:BLK [(match_operand:BLK 1 "" "")] 12))]
5423 [(set_attr "itanium_class" "syst_m")])
5425 (define_insn "fetchadd_acq_si"
5426 [(set (match_operand:SI 0 "gr_register_operand" "=r")
5428 (set (match_operand:SI 1 "not_postinc_memory_operand" "+S")
5429 (unspec:SI [(match_dup 1)
5430 (match_operand:SI 2 "fetchadd_operand" "n")] 19))]
5432 "fetchadd4.acq %0 = %1, %2"
5433 [(set_attr "itanium_class" "sem")])
5435 (define_insn "fetchadd_acq_di"
5436 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5438 (set (match_operand:DI 1 "not_postinc_memory_operand" "+S")
5439 (unspec:DI [(match_dup 1)
5440 (match_operand:DI 2 "fetchadd_operand" "n")] 19))]
5442 "fetchadd8.acq %0 = %1, %2"
5443 [(set_attr "itanium_class" "sem")])
5445 (define_insn "cmpxchg_acq_si"
5446 [(set (match_operand:SI 0 "gr_register_operand" "=r")
5448 (set (match_operand:SI 1 "not_postinc_memory_operand" "+S")
5449 (unspec:SI [(match_dup 1)
5450 (match_operand:SI 2 "gr_register_operand" "r")
5451 (match_operand:SI 3 "ar_ccv_reg_operand" "")] 13))]
5453 "cmpxchg4.acq %0 = %1, %2, %3"
5454 [(set_attr "itanium_class" "sem")])
5456 (define_insn "cmpxchg_acq_di"
5457 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5459 (set (match_operand:DI 1 "not_postinc_memory_operand" "+S")
5460 (unspec:DI [(match_dup 1)
5461 (match_operand:DI 2 "gr_register_operand" "r")
5462 (match_operand:DI 3 "ar_ccv_reg_operand" "")] 13))]
5464 "cmpxchg8.acq %0 = %1, %2, %3"
5465 [(set_attr "itanium_class" "sem")])
5467 (define_insn "xchgsi"
5468 [(set (match_operand:SI 0 "gr_register_operand" "=r")
5469 (match_operand:SI 1 "not_postinc_memory_operand" "+S"))
5471 (match_operand:SI 2 "gr_register_operand" "r"))]
5474 [(set_attr "itanium_class" "sem")])
5476 (define_insn "xchgdi"
5477 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5478 (match_operand:DI 1 "not_postinc_memory_operand" "+S"))
5480 (match_operand:DI 2 "gr_register_operand" "r"))]
5483 [(set_attr "itanium_class" "sem")])
5488 [(match_operator 0 "predicate_operator"
5489 [(match_operand:BI 1 "register_operand" "c")
5494 (define_insn "pred_rel_mutex"
5495 [(set (match_operand:BI 0 "register_operand" "+c")
5496 (unspec:BI [(match_dup 0)] 7))]
5498 ".pred.rel.mutex %0, %I0"
5499 [(set_attr "itanium_class" "ignore")
5500 (set_attr "predicable" "no")])
5502 (define_insn "safe_across_calls_all"
5503 [(unspec_volatile [(const_int 0)] 8)]
5505 ".pred.safe_across_calls p1-p63"
5506 [(set_attr "itanium_class" "ignore")
5507 (set_attr "predicable" "no")])
5509 (define_insn "safe_across_calls_normal"
5510 [(unspec_volatile [(const_int 0)] 9)]
5514 emit_safe_across_calls (asm_out_file);
5517 [(set_attr "itanium_class" "ignore")
5518 (set_attr "predicable" "no")])