1 /* Definitions of target machine GNU compiler. IA-64 version.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004
3 Free Software Foundation, Inc.
4 Contributed by James E. Wilson <wilson@cygnus.com> and
5 David Mosberger <davidm@hpl.hp.com>.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
24 /* ??? Look at ABI group documents for list of preprocessor macros and
25 other features required for ABI compliance. */
27 /* ??? Functions containing a non-local goto target save many registers. Why?
28 See for instance execute/920428-2.c. */
30 /* ??? Add support for short data/bss sections. */
33 /* Run-time target specifications */
35 /* Target CPU builtins. */
36 #define TARGET_CPU_CPP_BUILTINS() \
38 builtin_assert("cpu=ia64"); \
39 builtin_assert("machine=ia64"); \
40 builtin_define("__ia64"); \
41 builtin_define("__ia64__"); \
42 builtin_define("__itanium__"); \
43 if (TARGET_BIG_ENDIAN) \
44 builtin_define("__BIG_ENDIAN__"); \
48 { "asm_extra", ASM_EXTRA_SPEC },
50 #define CC1_SPEC "%(cc1_cpu) "
52 #define ASM_EXTRA_SPEC ""
55 /* This declaration should be present. */
56 extern int target_flags;
58 /* This series of macros is to allow compiler command arguments to enable or
59 disable the use of optional features of the target machine. */
61 #define MASK_BIG_ENDIAN 0x00000001 /* Generate big endian code. */
63 #define MASK_GNU_AS 0x00000002 /* Generate code for GNU as. */
65 #define MASK_GNU_LD 0x00000004 /* Generate code for GNU ld. */
67 #define MASK_NO_PIC 0x00000008 /* Generate code without GP reg. */
69 #define MASK_VOL_ASM_STOP 0x00000010 /* Emit stop bits for vol ext asm. */
71 #define MASK_ILP32 0x00000020 /* Generate ILP32 code. */
73 #define MASK_B_STEP 0x00000040 /* Emit code for Itanium B step. */
75 #define MASK_REG_NAMES 0x00000080 /* Use in/loc/out register names. */
77 #define MASK_NO_SDATA 0x00000100 /* Disable sdata/scommon/sbss. */
79 #define MASK_CONST_GP 0x00000200 /* treat gp as program-wide constant */
81 #define MASK_AUTO_PIC 0x00000400 /* generate automatically PIC */
83 #define MASK_INLINE_FLOAT_DIV_LAT 0x00000800 /* inline div, min latency. */
85 #define MASK_INLINE_FLOAT_DIV_THR 0x00001000 /* inline div, max throughput. */
87 #define MASK_INLINE_INT_DIV_LAT 0x00002000 /* inline div, min latency. */
89 #define MASK_INLINE_INT_DIV_THR 0x00004000 /* inline div, max throughput. */
91 #define MASK_INLINE_SQRT_LAT 0x00008000 /* inline sqrt, min latency. */
93 #define MASK_INLINE_SQRT_THR 0x00010000 /* inline sqrt, max throughput. */
95 #define MASK_DWARF2_ASM 0x00020000 /* test dwarf2 line info via gas. */
97 #define MASK_EARLY_STOP_BITS 0x00040000 /* tune stop bits for the model. */
99 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
101 #define TARGET_GNU_AS (target_flags & MASK_GNU_AS)
103 #define TARGET_GNU_LD (target_flags & MASK_GNU_LD)
105 #define TARGET_NO_PIC (target_flags & MASK_NO_PIC)
107 #define TARGET_VOL_ASM_STOP (target_flags & MASK_VOL_ASM_STOP)
109 #define TARGET_ILP32 (target_flags & MASK_ILP32)
111 #define TARGET_B_STEP (target_flags & MASK_B_STEP)
113 #define TARGET_REG_NAMES (target_flags & MASK_REG_NAMES)
115 #define TARGET_NO_SDATA (target_flags & MASK_NO_SDATA)
117 #define TARGET_CONST_GP (target_flags & MASK_CONST_GP)
119 #define TARGET_AUTO_PIC (target_flags & MASK_AUTO_PIC)
121 #define TARGET_INLINE_FLOAT_DIV_LAT (target_flags & MASK_INLINE_FLOAT_DIV_LAT)
123 #define TARGET_INLINE_FLOAT_DIV_THR (target_flags & MASK_INLINE_FLOAT_DIV_THR)
125 #define TARGET_INLINE_INT_DIV_LAT (target_flags & MASK_INLINE_INT_DIV_LAT)
127 #define TARGET_INLINE_INT_DIV_THR (target_flags & MASK_INLINE_INT_DIV_THR)
129 #define TARGET_INLINE_FLOAT_DIV \
130 (target_flags & (MASK_INLINE_FLOAT_DIV_LAT | MASK_INLINE_FLOAT_DIV_THR))
132 #define TARGET_INLINE_INT_DIV \
133 (target_flags & (MASK_INLINE_INT_DIV_LAT | MASK_INLINE_INT_DIV_THR))
135 #define TARGET_INLINE_SQRT_LAT (target_flags & MASK_INLINE_SQRT_LAT)
137 #define TARGET_INLINE_SQRT_THR (target_flags & MASK_INLINE_SQRT_THR)
139 #define TARGET_INLINE_SQRT \
140 (target_flags & (MASK_INLINE_SQRT_LAT | MASK_INLINE_SQRT_THR))
142 #define TARGET_DWARF2_ASM (target_flags & MASK_DWARF2_ASM)
144 /* If the assembler supports thread-local storage, assume that the
145 system does as well. If a particular target system has an
146 assembler that supports TLS -- but the rest of the system does not
147 support TLS -- that system should explicit define TARGET_HAVE_TLS
148 to false in its own configuration file. */
149 #if !defined(TARGET_HAVE_TLS) && defined(HAVE_AS_TLS)
150 #define TARGET_HAVE_TLS true
153 extern int ia64_tls_size;
154 #define TARGET_TLS14 (ia64_tls_size == 14)
155 #define TARGET_TLS22 (ia64_tls_size == 22)
156 #define TARGET_TLS64 (ia64_tls_size == 64)
157 #define TARGET_EARLY_STOP_BITS (target_flags & MASK_EARLY_STOP_BITS)
159 #define TARGET_HPUX 0
160 #define TARGET_HPUX_LD 0
162 #ifndef HAVE_AS_LTOFFX_LDXMOV_RELOCS
163 #define HAVE_AS_LTOFFX_LDXMOV_RELOCS 0
166 /* This macro defines names of command options to set and clear bits in
167 `target_flags'. Its definition is an initializer with a subgrouping for
168 each command option. */
170 #define TARGET_SWITCHES \
172 { "big-endian", MASK_BIG_ENDIAN, \
173 N_("Generate big endian code") }, \
174 { "little-endian", -MASK_BIG_ENDIAN, \
175 N_("Generate little endian code") }, \
176 { "gnu-as", MASK_GNU_AS, \
177 N_("Generate code for GNU as") }, \
178 { "no-gnu-as", -MASK_GNU_AS, \
179 N_("Generate code for Intel as") }, \
180 { "gnu-ld", MASK_GNU_LD, \
181 N_("Generate code for GNU ld") }, \
182 { "no-gnu-ld", -MASK_GNU_LD, \
183 N_("Generate code for Intel ld") }, \
184 { "no-pic", MASK_NO_PIC, \
185 N_("Generate code without GP reg") }, \
186 { "volatile-asm-stop", MASK_VOL_ASM_STOP, \
187 N_("Emit stop bits before and after volatile extended asms") }, \
188 { "no-volatile-asm-stop", -MASK_VOL_ASM_STOP, \
189 N_("Don't emit stop bits before and after volatile extended asms") }, \
190 { "b-step", MASK_B_STEP, \
191 N_("Emit code for Itanium (TM) processor B step")}, \
192 { "register-names", MASK_REG_NAMES, \
193 N_("Use in/loc/out register names")}, \
194 { "no-sdata", MASK_NO_SDATA, \
195 N_("Disable use of sdata/scommon/sbss")}, \
196 { "sdata", -MASK_NO_SDATA, \
197 N_("Enable use of sdata/scommon/sbss")}, \
198 { "constant-gp", MASK_CONST_GP, \
199 N_("gp is constant (but save/restore gp on indirect calls)") }, \
200 { "auto-pic", MASK_AUTO_PIC, \
201 N_("Generate self-relocatable code") }, \
202 { "inline-float-divide-min-latency", MASK_INLINE_FLOAT_DIV_LAT, \
203 N_("Generate inline floating point division, optimize for latency") },\
204 { "inline-float-divide-max-throughput", MASK_INLINE_FLOAT_DIV_THR, \
205 N_("Generate inline floating point division, optimize for throughput") },\
206 { "no-inline-float-divide", \
207 -(MASK_INLINE_FLOAT_DIV_LAT|MASK_INLINE_FLOAT_DIV_THR), \
208 N_("Do not inline floating point division") }, \
209 { "inline-int-divide-min-latency", MASK_INLINE_INT_DIV_LAT, \
210 N_("Generate inline integer division, optimize for latency") }, \
211 { "inline-int-divide-max-throughput", MASK_INLINE_INT_DIV_THR, \
212 N_("Generate inline integer division, optimize for throughput") },\
213 { "no-inline-int-divide", -(MASK_INLINE_INT_DIV_LAT|MASK_INLINE_INT_DIV_THR), \
214 N_("Do not inline integer division") }, \
215 { "inline-sqrt-min-latency", MASK_INLINE_SQRT_LAT, \
216 N_("Generate inline square root, optimize for latency") }, \
217 { "inline-sqrt-max-throughput", MASK_INLINE_SQRT_THR, \
218 N_("Generate inline square root, optimize for throughput") }, \
219 { "no-inline-sqrt", -(MASK_INLINE_SQRT_LAT|MASK_INLINE_SQRT_THR), \
220 N_("Do not inline square root") }, \
221 { "dwarf2-asm", MASK_DWARF2_ASM, \
222 N_("Enable Dwarf 2 line debug info via GNU as")}, \
223 { "no-dwarf2-asm", -MASK_DWARF2_ASM, \
224 N_("Disable Dwarf 2 line debug info via GNU as")}, \
225 { "early-stop-bits", MASK_EARLY_STOP_BITS, \
226 N_("Enable earlier placing stop bits for better scheduling")}, \
227 { "no-early-stop-bits", -MASK_EARLY_STOP_BITS, \
228 N_("Disable earlier placing stop bits")}, \
230 { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT, \
234 /* Default target_flags if no switches are specified */
236 #ifndef TARGET_DEFAULT
237 #define TARGET_DEFAULT (MASK_DWARF2_ASM | MASK_INLINE_FLOAT_DIV_THR)
240 #ifndef TARGET_CPU_DEFAULT
241 #define TARGET_CPU_DEFAULT 0
244 #ifndef SUBTARGET_SWITCHES
245 #define SUBTARGET_SWITCHES
248 /* This macro is similar to `TARGET_SWITCHES' but defines names of command
249 options that have values. Its definition is an initializer with a
250 subgrouping for each command option. */
252 extern const char *ia64_fixed_range_string;
253 extern const char *ia64_tls_size_string;
255 /* Which processor to schedule for. The cpu attribute defines a list
256 that mirrors this list, so changes to i64.md must be made at the
261 PROCESSOR_ITANIUM, /* Original Itanium. */
266 extern enum processor_type ia64_tune;
268 extern const char *ia64_tune_string;
270 #define TARGET_OPTIONS \
272 { "fixed-range=", &ia64_fixed_range_string, \
273 N_("Specify range of registers to make fixed"), 0}, \
274 { "tls-size=", &ia64_tls_size_string, \
275 N_("Specify bit size of immediate TLS offsets"), 0}, \
276 { "tune=", &ia64_tune_string, \
277 N_("Schedule code for given CPU"), 0}, \
280 /* Sometimes certain combinations of command options do not make sense on a
281 particular target machine. You can define a macro `OVERRIDE_OPTIONS' to
282 take account of this. This macro, if defined, is executed once just after
283 all the command options have been parsed. */
285 #define OVERRIDE_OPTIONS ia64_override_options ()
287 /* Some machines may desire to change what optimizations are performed for
288 various optimization levels. This macro, if defined, is executed once just
289 after the optimization level is determined and before the remainder of the
290 command options have been parsed. Values set in this macro are used as the
291 default values for the other command line options. */
293 /* #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) */
295 /* Driver configuration */
297 /* A C string constant that tells the GCC driver program options to pass to
298 `cc1'. It can also specify how to translate options you give to GCC into
299 options for GCC to pass to the `cc1'. */
302 #define CC1_SPEC "%{G*}"
304 /* A C string constant that tells the GCC driver program options to pass to
305 `cc1plus'. It can also specify how to translate options you give to GCC
306 into options for GCC to pass to the `cc1plus'. */
308 /* #define CC1PLUS_SPEC "" */
312 /* Define this macro to have the value 1 if the most significant bit in a byte
313 has the lowest number; otherwise define it to have the value zero. */
315 #define BITS_BIG_ENDIAN 0
317 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
319 /* Define this macro to have the value 1 if, in a multiword object, the most
320 significant word has the lowest number. */
322 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
324 #if defined(__BIG_ENDIAN__)
325 #define LIBGCC2_WORDS_BIG_ENDIAN 1
327 #define LIBGCC2_WORDS_BIG_ENDIAN 0
330 #define UNITS_PER_WORD 8
332 #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64)
334 /* A C expression whose value is zero if pointers that need to be extended
335 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and one if
336 they are zero-extended and negative one if there is a ptr_extend operation.
338 You need not define this macro if the `POINTER_SIZE' is equal to the width
340 /* Need this for 32 bit pointers, see hpux.h for setting it. */
341 /* #define POINTERS_EXTEND_UNSIGNED */
343 /* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and
344 which has the specified mode and signedness is to be stored in a register.
345 This macro is only called when TYPE is a scalar type. */
346 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
349 if (GET_MODE_CLASS (MODE) == MODE_INT \
350 && GET_MODE_SIZE (MODE) < 4) \
355 #define PARM_BOUNDARY 64
357 /* Define this macro if you wish to preserve a certain alignment for the stack
358 pointer. The definition is a C expression for the desired alignment
359 (measured in bits). */
361 #define STACK_BOUNDARY 128
363 /* Align frames on double word boundaries */
364 #ifndef IA64_STACK_ALIGN
365 #define IA64_STACK_ALIGN(LOC) (((LOC) + 15) & ~15)
368 #define FUNCTION_BOUNDARY 128
370 /* Optional x86 80-bit float, quad-precision 128-bit float, and quad-word
371 128 bit integers all require 128 bit alignment. */
372 #define BIGGEST_ALIGNMENT 128
374 /* If defined, a C expression to compute the alignment for a static variable.
375 TYPE is the data type, and ALIGN is the alignment that the object
376 would ordinarily have. The value of this macro is used instead of that
377 alignment to align the object. */
379 #define DATA_ALIGNMENT(TYPE, ALIGN) \
380 (TREE_CODE (TYPE) == ARRAY_TYPE \
381 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
382 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
384 /* If defined, a C expression to compute the alignment given to a constant that
385 is being placed in memory. CONSTANT is the constant and ALIGN is the
386 alignment that the object would ordinarily have. The value of this macro is
387 used instead of that alignment to align the object. */
389 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
390 (TREE_CODE (EXP) == STRING_CST \
391 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
393 #define STRICT_ALIGNMENT 1
395 /* Define this if you wish to imitate the way many other C compilers handle
396 alignment of bitfields and the structures that contain them.
397 The behavior is that the type written for a bit-field (`int', `short', or
398 other integer type) imposes an alignment for the entire structure, as if the
399 structure really did contain an ordinary field of that type. In addition,
400 the bit-field is placed within the structure so that it would fit within such
401 a field, not crossing a boundary for it. */
402 #define PCC_BITFIELD_TYPE_MATTERS 1
404 /* An integer expression for the size in bits of the largest integer machine
405 mode that should actually be used. */
407 /* Allow pairs of registers to be used, which is the intent of the default. */
408 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
410 /* By default, the C++ compiler will use function addresses in the
411 vtable entries. Setting this nonzero tells the compiler to use
412 function descriptors instead. The value of this macro says how
413 many words wide the descriptor is (normally 2). It is assumed
414 that the address of a function descriptor may be treated as a
415 pointer to a function.
417 For reasons known only to HP, the vtable entries (as opposed to
418 normal function descriptors) are 16 bytes wide in 32-bit mode as
419 well, even though the 3rd and 4th words are unused. */
420 #define TARGET_VTABLE_USES_DESCRIPTORS (TARGET_ILP32 ? 4 : 2)
422 /* Due to silliness in the HPUX linker, vtable entries must be
423 8-byte aligned even in 32-bit mode. Rather than create multiple
424 ABIs, force this restriction on everyone else too. */
425 #define TARGET_VTABLE_ENTRY_ALIGN 64
427 /* Due to the above, we need extra padding for the data entries below 0
428 to retain the alignment of the descriptors. */
429 #define TARGET_VTABLE_DATA_ENTRY_DISTANCE (TARGET_ILP32 ? 2 : 1)
431 /* Layout of Source Language Data Types */
433 #define INT_TYPE_SIZE 32
435 #define SHORT_TYPE_SIZE 16
437 #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64)
439 #define LONG_LONG_TYPE_SIZE 64
441 #define FLOAT_TYPE_SIZE 32
443 #define DOUBLE_TYPE_SIZE 64
445 /* long double is XFmode normally, TFmode for HPUX. */
446 #define LONG_DOUBLE_TYPE_SIZE (TARGET_HPUX ? 128 : 96)
448 /* We always want the XFmode operations from libgcc2.c. */
449 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
451 #define DEFAULT_SIGNED_CHAR 1
453 /* A C expression for a string describing the name of the data type to use for
454 size values. The typedef name `size_t' is defined using the contents of the
456 /* ??? Needs to be defined for P64 code. */
457 /* #define SIZE_TYPE */
459 /* A C expression for a string describing the name of the data type to use for
460 the result of subtracting two pointers. The typedef name `ptrdiff_t' is
461 defined using the contents of the string. See `SIZE_TYPE' above for more
463 /* ??? Needs to be defined for P64 code. */
464 /* #define PTRDIFF_TYPE */
466 /* A C expression for a string describing the name of the data type to use for
467 wide characters. The typedef name `wchar_t' is defined using the contents
468 of the string. See `SIZE_TYPE' above for more information. */
469 /* #define WCHAR_TYPE */
471 /* A C expression for the size in bits of the data type for wide characters.
472 This is used in `cpp', which cannot make use of `WCHAR_TYPE'. */
473 /* #define WCHAR_TYPE_SIZE */
476 /* Register Basics */
478 /* Number of hardware registers known to the compiler.
479 We have 128 general registers, 128 floating point registers,
480 64 predicate registers, 8 branch registers, one frame pointer,
481 and several "application" registers. */
483 #define FIRST_PSEUDO_REGISTER 334
485 /* Ranges for the various kinds of registers. */
486 #define ADDL_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 3)
487 #define GR_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 127)
488 #define FR_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 255)
489 #define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319)
490 #define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327)
491 #define GENERAL_REGNO_P(REGNO) \
492 (GR_REGNO_P (REGNO) || (REGNO) == FRAME_POINTER_REGNUM)
494 #define GR_REG(REGNO) ((REGNO) + 0)
495 #define FR_REG(REGNO) ((REGNO) + 128)
496 #define PR_REG(REGNO) ((REGNO) + 256)
497 #define BR_REG(REGNO) ((REGNO) + 320)
498 #define OUT_REG(REGNO) ((REGNO) + 120)
499 #define IN_REG(REGNO) ((REGNO) + 112)
500 #define LOC_REG(REGNO) ((REGNO) + 32)
502 #define AR_CCV_REGNUM 329
503 #define AR_UNAT_REGNUM 330
504 #define AR_PFS_REGNUM 331
505 #define AR_LC_REGNUM 332
506 #define AR_EC_REGNUM 333
508 #define IN_REGNO_P(REGNO) ((REGNO) >= IN_REG (0) && (REGNO) <= IN_REG (7))
509 #define LOC_REGNO_P(REGNO) ((REGNO) >= LOC_REG (0) && (REGNO) <= LOC_REG (79))
510 #define OUT_REGNO_P(REGNO) ((REGNO) >= OUT_REG (0) && (REGNO) <= OUT_REG (7))
512 #define AR_M_REGNO_P(REGNO) ((REGNO) == AR_CCV_REGNUM \
513 || (REGNO) == AR_UNAT_REGNUM)
514 #define AR_I_REGNO_P(REGNO) ((REGNO) >= AR_PFS_REGNUM \
515 && (REGNO) < FIRST_PSEUDO_REGISTER)
516 #define AR_REGNO_P(REGNO) ((REGNO) >= AR_CCV_REGNUM \
517 && (REGNO) < FIRST_PSEUDO_REGISTER)
520 /* ??? Don't really need two sets of macros. I like this one better because
521 it is less typing. */
522 #define R_GR(REGNO) GR_REG (REGNO)
523 #define R_FR(REGNO) FR_REG (REGNO)
524 #define R_PR(REGNO) PR_REG (REGNO)
525 #define R_BR(REGNO) BR_REG (REGNO)
527 /* An initializer that says which registers are used for fixed purposes all
528 throughout the compiled code and are therefore not available for general
532 r1: global pointer (gp)
533 r12: stack pointer (sp)
534 r13: thread pointer (tp)
538 fp: eliminable frame pointer */
540 /* The last 16 stacked regs are reserved for the 8 input and 8 output
543 #define FIXED_REGISTERS \
544 { /* General registers. */ \
545 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \
546 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
547 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
548 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
549 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
550 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
551 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
552 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
553 /* Floating-point registers. */ \
554 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
555 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
556 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
557 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
558 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
559 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
560 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
561 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
562 /* Predicate registers. */ \
563 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
564 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
565 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
566 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
567 /* Branch registers. */ \
568 0, 0, 0, 0, 0, 0, 0, 0, \
569 /*FP CCV UNAT PFS LC EC */ \
573 /* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered
574 (in general) by function calls as well as for fixed registers. This
575 macro therefore identifies the registers that are not available for
576 general allocation of values that must live across function calls. */
578 #define CALL_USED_REGISTERS \
579 { /* General registers. */ \
580 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
581 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
582 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
583 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
584 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
585 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
586 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
587 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
588 /* Floating-point registers. */ \
589 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
590 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
591 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
592 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
593 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
594 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
595 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
596 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
597 /* Predicate registers. */ \
598 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
599 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
600 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
601 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
602 /* Branch registers. */ \
603 1, 0, 0, 0, 0, 0, 1, 1, \
604 /*FP CCV UNAT PFS LC EC */ \
608 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
609 problem which makes CALL_USED_REGISTERS *always* include
610 all the FIXED_REGISTERS. Until this problem has been
611 resolved this macro can be used to overcome this situation.
612 In particular, block_propagate() requires this list
613 be accurate, or we can remove registers which should be live.
614 This macro is used in regs_invalidated_by_call. */
616 #define CALL_REALLY_USED_REGISTERS \
617 { /* General registers. */ \
618 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, \
619 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
620 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
621 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
622 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
623 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
624 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
625 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
626 /* Floating-point registers. */ \
627 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
628 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
629 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
630 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
631 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
632 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
633 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
634 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
635 /* Predicate registers. */ \
636 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
637 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
638 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
639 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
640 /* Branch registers. */ \
641 1, 0, 0, 0, 0, 0, 1, 1, \
642 /*FP CCV UNAT PFS LC EC */ \
647 /* Define this macro if the target machine has register windows. This C
648 expression returns the register number as seen by the called function
649 corresponding to the register number OUT as seen by the calling function.
650 Return OUT if register number OUT is not an outbound register. */
652 #define INCOMING_REGNO(OUT) \
653 ((unsigned) ((OUT) - OUT_REG (0)) < 8 ? IN_REG ((OUT) - OUT_REG (0)) : (OUT))
655 /* Define this macro if the target machine has register windows. This C
656 expression returns the register number as seen by the calling function
657 corresponding to the register number IN as seen by the called function.
658 Return IN if register number IN is not an inbound register. */
660 #define OUTGOING_REGNO(IN) \
661 ((unsigned) ((IN) - IN_REG (0)) < 8 ? OUT_REG ((IN) - IN_REG (0)) : (IN))
663 /* Define this macro if the target machine has register windows. This
664 C expression returns true if the register is call-saved but is in the
667 #define LOCAL_REGNO(REGNO) \
668 (IN_REGNO_P (REGNO) || LOC_REGNO_P (REGNO))
670 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
671 return the mode to be used for the comparison. Must be defined if
672 EXTRA_CC_MODES is defined. */
674 #define SELECT_CC_MODE(OP,X,Y) CCmode
676 /* Order of allocation of registers */
678 /* If defined, an initializer for a vector of integers, containing the numbers
679 of hard registers in the order in which GCC should prefer to use them
680 (from most preferred to least).
682 If this macro is not defined, registers are used lowest numbered first (all
685 One use of this macro is on machines where the highest numbered registers
686 must always be saved and the save-multiple-registers instruction supports
687 only sequences of consecutive registers. On such machines, define
688 `REG_ALLOC_ORDER' to be an initializer that lists the highest numbered
689 allocatable register first. */
691 /* ??? Should the GR return value registers come before or after the rest
692 of the caller-save GRs? */
694 #define REG_ALLOC_ORDER \
696 /* Caller-saved general registers. */ \
697 R_GR (14), R_GR (15), R_GR (16), R_GR (17), \
698 R_GR (18), R_GR (19), R_GR (20), R_GR (21), R_GR (22), R_GR (23), \
699 R_GR (24), R_GR (25), R_GR (26), R_GR (27), R_GR (28), R_GR (29), \
700 R_GR (30), R_GR (31), \
701 /* Output registers. */ \
702 R_GR (120), R_GR (121), R_GR (122), R_GR (123), R_GR (124), R_GR (125), \
703 R_GR (126), R_GR (127), \
704 /* Caller-saved general registers, also used for return values. */ \
705 R_GR (8), R_GR (9), R_GR (10), R_GR (11), \
706 /* addl caller-saved general registers. */ \
707 R_GR (2), R_GR (3), \
708 /* Caller-saved FP registers. */ \
709 R_FR (6), R_FR (7), \
710 /* Caller-saved FP registers, used for parameters and return values. */ \
711 R_FR (8), R_FR (9), R_FR (10), R_FR (11), \
712 R_FR (12), R_FR (13), R_FR (14), R_FR (15), \
713 /* Rotating caller-saved FP registers. */ \
714 R_FR (32), R_FR (33), R_FR (34), R_FR (35), \
715 R_FR (36), R_FR (37), R_FR (38), R_FR (39), R_FR (40), R_FR (41), \
716 R_FR (42), R_FR (43), R_FR (44), R_FR (45), R_FR (46), R_FR (47), \
717 R_FR (48), R_FR (49), R_FR (50), R_FR (51), R_FR (52), R_FR (53), \
718 R_FR (54), R_FR (55), R_FR (56), R_FR (57), R_FR (58), R_FR (59), \
719 R_FR (60), R_FR (61), R_FR (62), R_FR (63), R_FR (64), R_FR (65), \
720 R_FR (66), R_FR (67), R_FR (68), R_FR (69), R_FR (70), R_FR (71), \
721 R_FR (72), R_FR (73), R_FR (74), R_FR (75), R_FR (76), R_FR (77), \
722 R_FR (78), R_FR (79), R_FR (80), R_FR (81), R_FR (82), R_FR (83), \
723 R_FR (84), R_FR (85), R_FR (86), R_FR (87), R_FR (88), R_FR (89), \
724 R_FR (90), R_FR (91), R_FR (92), R_FR (93), R_FR (94), R_FR (95), \
725 R_FR (96), R_FR (97), R_FR (98), R_FR (99), R_FR (100), R_FR (101), \
726 R_FR (102), R_FR (103), R_FR (104), R_FR (105), R_FR (106), R_FR (107), \
727 R_FR (108), R_FR (109), R_FR (110), R_FR (111), R_FR (112), R_FR (113), \
728 R_FR (114), R_FR (115), R_FR (116), R_FR (117), R_FR (118), R_FR (119), \
729 R_FR (120), R_FR (121), R_FR (122), R_FR (123), R_FR (124), R_FR (125), \
730 R_FR (126), R_FR (127), \
731 /* Caller-saved predicate registers. */ \
732 R_PR (6), R_PR (7), R_PR (8), R_PR (9), R_PR (10), R_PR (11), \
733 R_PR (12), R_PR (13), R_PR (14), R_PR (15), \
734 /* Rotating caller-saved predicate registers. */ \
735 R_PR (16), R_PR (17), \
736 R_PR (18), R_PR (19), R_PR (20), R_PR (21), R_PR (22), R_PR (23), \
737 R_PR (24), R_PR (25), R_PR (26), R_PR (27), R_PR (28), R_PR (29), \
738 R_PR (30), R_PR (31), R_PR (32), R_PR (33), R_PR (34), R_PR (35), \
739 R_PR (36), R_PR (37), R_PR (38), R_PR (39), R_PR (40), R_PR (41), \
740 R_PR (42), R_PR (43), R_PR (44), R_PR (45), R_PR (46), R_PR (47), \
741 R_PR (48), R_PR (49), R_PR (50), R_PR (51), R_PR (52), R_PR (53), \
742 R_PR (54), R_PR (55), R_PR (56), R_PR (57), R_PR (58), R_PR (59), \
743 R_PR (60), R_PR (61), R_PR (62), R_PR (63), \
744 /* Caller-saved branch registers. */ \
745 R_BR (6), R_BR (7), \
747 /* Stacked callee-saved general registers. */ \
748 R_GR (32), R_GR (33), R_GR (34), R_GR (35), \
749 R_GR (36), R_GR (37), R_GR (38), R_GR (39), R_GR (40), R_GR (41), \
750 R_GR (42), R_GR (43), R_GR (44), R_GR (45), R_GR (46), R_GR (47), \
751 R_GR (48), R_GR (49), R_GR (50), R_GR (51), R_GR (52), R_GR (53), \
752 R_GR (54), R_GR (55), R_GR (56), R_GR (57), R_GR (58), R_GR (59), \
753 R_GR (60), R_GR (61), R_GR (62), R_GR (63), R_GR (64), R_GR (65), \
754 R_GR (66), R_GR (67), R_GR (68), R_GR (69), R_GR (70), R_GR (71), \
755 R_GR (72), R_GR (73), R_GR (74), R_GR (75), R_GR (76), R_GR (77), \
756 R_GR (78), R_GR (79), R_GR (80), R_GR (81), R_GR (82), R_GR (83), \
757 R_GR (84), R_GR (85), R_GR (86), R_GR (87), R_GR (88), R_GR (89), \
758 R_GR (90), R_GR (91), R_GR (92), R_GR (93), R_GR (94), R_GR (95), \
759 R_GR (96), R_GR (97), R_GR (98), R_GR (99), R_GR (100), R_GR (101), \
760 R_GR (102), R_GR (103), R_GR (104), R_GR (105), R_GR (106), R_GR (107), \
762 /* Input registers. */ \
763 R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (116), R_GR (117), \
764 R_GR (118), R_GR (119), \
765 /* Callee-saved general registers. */ \
766 R_GR (4), R_GR (5), R_GR (6), R_GR (7), \
767 /* Callee-saved FP registers. */ \
768 R_FR (2), R_FR (3), R_FR (4), R_FR (5), R_FR (16), R_FR (17), \
769 R_FR (18), R_FR (19), R_FR (20), R_FR (21), R_FR (22), R_FR (23), \
770 R_FR (24), R_FR (25), R_FR (26), R_FR (27), R_FR (28), R_FR (29), \
771 R_FR (30), R_FR (31), \
772 /* Callee-saved predicate registers. */ \
773 R_PR (1), R_PR (2), R_PR (3), R_PR (4), R_PR (5), \
774 /* Callee-saved branch registers. */ \
775 R_BR (1), R_BR (2), R_BR (3), R_BR (4), R_BR (5), \
777 /* ??? Stacked registers reserved for fp, rp, and ar.pfs. */ \
778 R_GR (109), R_GR (110), R_GR (111), \
780 /* Special general registers. */ \
781 R_GR (0), R_GR (1), R_GR (12), R_GR (13), \
782 /* Special FP registers. */ \
783 R_FR (0), R_FR (1), \
784 /* Special predicate registers. */ \
786 /* Special branch registers. */ \
788 /* Other fixed registers. */ \
789 FRAME_POINTER_REGNUM, \
790 AR_CCV_REGNUM, AR_UNAT_REGNUM, AR_PFS_REGNUM, AR_LC_REGNUM, \
794 /* How Values Fit in Registers */
796 /* A C expression for the number of consecutive hard registers, starting at
797 register number REGNO, required to hold a value of mode MODE. */
799 /* ??? We say that BImode PR values require two registers. This allows us to
800 easily store the normal and inverted values. We use CCImode to indicate
801 a single predicate register. */
803 #define HARD_REGNO_NREGS(REGNO, MODE) \
804 ((REGNO) == PR_REG (0) && (MODE) == DImode ? 64 \
805 : PR_REGNO_P (REGNO) && (MODE) == BImode ? 2 \
806 : PR_REGNO_P (REGNO) && (MODE) == CCImode ? 1 \
807 : FR_REGNO_P (REGNO) && (MODE) == XFmode ? 1 \
808 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
810 /* A C expression that is nonzero if it is permissible to store a value of mode
811 MODE in hard register number REGNO (or in several registers starting with
814 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
815 (FR_REGNO_P (REGNO) ? \
816 GET_MODE_CLASS (MODE) != MODE_CC && \
817 (MODE) != TImode && \
818 (MODE) != BImode && \
820 : PR_REGNO_P (REGNO) ? \
821 (MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \
822 : GR_REGNO_P (REGNO) ? (MODE) != CCImode && (MODE) != XFmode \
823 : AR_REGNO_P (REGNO) ? (MODE) == DImode \
824 : BR_REGNO_P (REGNO) ? (MODE) == DImode \
827 /* A C expression that is nonzero if it is desirable to choose register
828 allocation so as to avoid move instructions between a value of mode MODE1
829 and a value of mode MODE2.
831 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
832 ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
834 /* Don't tie integer and FP modes, as that causes us to get integer registers
835 allocated for FP instructions. XFmode only supported in FP registers so
836 we can't tie it with any other modes. */
837 #define MODES_TIEABLE_P(MODE1, MODE2) \
838 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
839 && (((MODE1) == XFmode) == ((MODE2) == XFmode)) \
840 && (((MODE1) == BImode) == ((MODE2) == BImode)))
842 /* Specify the modes required to caller save a given hard regno.
843 We need to ensure floating pt regs are not saved as DImode. */
845 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
846 ((FR_REGNO_P (REGNO) && (NREGS) == 1) ? XFmode \
847 : choose_hard_reg_mode ((REGNO), (NREGS), false))
849 /* Handling Leaf Functions */
851 /* A C initializer for a vector, indexed by hard register number, which
852 contains 1 for a register that is allowable in a candidate for leaf function
854 /* ??? This might be useful. */
855 /* #define LEAF_REGISTERS */
857 /* A C expression whose value is the register number to which REGNO should be
858 renumbered, when a function is treated as a leaf function. */
859 /* ??? This might be useful. */
860 /* #define LEAF_REG_REMAP(REGNO) */
863 /* Register Classes */
865 /* An enumeral type that must be defined with all the register class names as
866 enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last
867 register class, followed by one more enumeral value, `LIM_REG_CLASSES',
868 which is not a register class but rather tells how many classes there
870 /* ??? When compiling without optimization, it is possible for the only use of
871 a pseudo to be a parameter load from the stack with a REG_EQUIV note.
872 Regclass handles this case specially and does not assign any costs to the
873 pseudo. The pseudo then ends up using the last class before ALL_REGS.
874 Thus we must not let either PR_REGS or BR_REGS be the last class. The
875 testcase for this is gcc.c-torture/execute/va-arg-7.c. */
892 #define GENERAL_REGS GR_REGS
894 /* The number of distinct register classes. */
895 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
897 /* An initializer containing the names of the register classes as C string
898 constants. These names are used in writing some of the debugging dumps. */
899 #define REG_CLASS_NAMES \
900 { "NO_REGS", "PR_REGS", "BR_REGS", "AR_M_REGS", "AR_I_REGS", \
901 "ADDL_REGS", "GR_REGS", "FR_REGS", \
902 "GR_AND_BR_REGS", "GR_AND_FR_REGS", "ALL_REGS" }
904 /* An initializer containing the contents of the register classes, as integers
905 which are bit masks. The Nth integer specifies the contents of class N.
906 The way the integer MASK is interpreted is that register R is in the class
907 if `MASK & (1 << R)' is 1. */
908 #define REG_CLASS_CONTENTS \
911 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
912 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
913 0x00000000, 0x00000000, 0x0000 }, \
915 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
916 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
917 0xFFFFFFFF, 0xFFFFFFFF, 0x0000 }, \
919 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
920 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
921 0x00000000, 0x00000000, 0x00FF }, \
923 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
924 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
925 0x00000000, 0x00000000, 0x0600 }, \
927 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
928 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
929 0x00000000, 0x00000000, 0x3800 }, \
931 { 0x0000000F, 0x00000000, 0x00000000, 0x00000000, \
932 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
933 0x00000000, 0x00000000, 0x0000 }, \
935 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
936 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
937 0x00000000, 0x00000000, 0x0100 }, \
939 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
940 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
941 0x00000000, 0x00000000, 0x0000 }, \
942 /* GR_AND_BR_REGS. */ \
943 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
944 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
945 0x00000000, 0x00000000, 0x01FF }, \
946 /* GR_AND_FR_REGS. */ \
947 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
948 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
949 0x00000000, 0x00000000, 0x0100 }, \
951 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
952 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
953 0xFFFFFFFF, 0xFFFFFFFF, 0x3FFF }, \
956 /* A C expression whose value is a register class containing hard register
957 REGNO. In general there is more than one such class; choose a class which
958 is "minimal", meaning that no smaller class also contains the register. */
959 /* The NO_REGS case is primarily for the benefit of rws_access_reg, which
960 may call here with private (invalid) register numbers, such as
962 #define REGNO_REG_CLASS(REGNO) \
963 (ADDL_REGNO_P (REGNO) ? ADDL_REGS \
964 : GENERAL_REGNO_P (REGNO) ? GR_REGS \
965 : FR_REGNO_P (REGNO) ? FR_REGS \
966 : PR_REGNO_P (REGNO) ? PR_REGS \
967 : BR_REGNO_P (REGNO) ? BR_REGS \
968 : AR_M_REGNO_P (REGNO) ? AR_M_REGS \
969 : AR_I_REGNO_P (REGNO) ? AR_I_REGS \
972 /* A macro whose definition is the name of the class to which a valid base
973 register must belong. A base register is one used in an address which is
974 the register value plus a displacement. */
975 #define BASE_REG_CLASS GENERAL_REGS
977 /* A macro whose definition is the name of the class to which a valid index
978 register must belong. An index register is one used in an address where its
979 value is either multiplied by a scale factor or added to another register
980 (as well as added to a displacement). This is needed for POST_MODIFY. */
981 #define INDEX_REG_CLASS GENERAL_REGS
983 /* A C expression which defines the machine-dependent operand constraint
984 letters for register classes. If CHAR is such a letter, the value should be
985 the register class corresponding to it. Otherwise, the value should be
986 `NO_REGS'. The register letter `r', corresponding to class `GENERAL_REGS',
987 will not be passed to this macro; you do not need to handle it. */
989 #define REG_CLASS_FROM_LETTER(CHAR) \
990 ((CHAR) == 'f' ? FR_REGS \
991 : (CHAR) == 'a' ? ADDL_REGS \
992 : (CHAR) == 'b' ? BR_REGS \
993 : (CHAR) == 'c' ? PR_REGS \
994 : (CHAR) == 'd' ? AR_M_REGS \
995 : (CHAR) == 'e' ? AR_I_REGS \
998 /* A C expression which is nonzero if register number NUM is suitable for use
999 as a base register in operand addresses. It may be either a suitable hard
1000 register or a pseudo register that has been allocated such a hard reg. */
1001 #define REGNO_OK_FOR_BASE_P(REGNO) \
1002 (GENERAL_REGNO_P (REGNO) || GENERAL_REGNO_P (reg_renumber[REGNO]))
1004 /* A C expression which is nonzero if register number NUM is suitable for use
1005 as an index register in operand addresses. It may be either a suitable hard
1006 register or a pseudo register that has been allocated such a hard reg.
1007 This is needed for POST_MODIFY. */
1008 #define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM)
1010 /* A C expression that places additional restrictions on the register class to
1011 use when it is necessary to copy value X into a register in class CLASS.
1012 The value is a register class; perhaps CLASS, or perhaps another, smaller
1015 /* Don't allow volatile mem reloads into floating point registers. This
1016 is defined to force reload to choose the r/m case instead of the f/f case
1017 when reloading (set (reg fX) (mem/v)).
1019 Do not reload expressions into AR regs. */
1021 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1022 (CLASS == FR_REGS && GET_CODE (X) == MEM && MEM_VOLATILE_P (X) ? NO_REGS \
1023 : CLASS == FR_REGS && GET_CODE (X) == CONST_DOUBLE ? NO_REGS \
1025 && (CLASS == AR_M_REGS || CLASS == AR_I_REGS) ? NO_REGS \
1028 /* You should define this macro to indicate to the reload phase that it may
1029 need to allocate at least one register for a reload in addition to the
1030 register to contain the data. Specifically, if copying X to a register
1031 CLASS in MODE requires an intermediate register, you should define this
1032 to return the largest register class all of whose registers can be used
1033 as intermediate registers or scratch registers. */
1035 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
1036 ia64_secondary_reload_class (CLASS, MODE, X)
1038 /* Certain machines have the property that some registers cannot be copied to
1039 some other registers without using memory. Define this macro on those
1040 machines to be a C expression that is nonzero if objects of mode M in
1041 registers of CLASS1 can only be copied to registers of class CLASS2 by
1042 storing a register of CLASS1 into memory and loading that memory location
1043 into a register of CLASS2. */
1046 /* ??? May need this, but since we've disallowed XFmode in GR_REGS,
1047 I'm not quite sure how it could be invoked. The normal problems
1048 with unions should be solved with the addressof fiddling done by
1049 movxf and friends. */
1050 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1051 ((MODE) == XFmode && (((CLASS1) == GR_REGS && (CLASS2) == FR_REGS) \
1052 || ((CLASS1) == FR_REGS && (CLASS2) == GR_REGS)))
1055 /* A C expression for the maximum number of consecutive registers of
1056 class CLASS needed to hold a value of mode MODE.
1057 This is closely related to the macro `HARD_REGNO_NREGS'. */
1059 #define CLASS_MAX_NREGS(CLASS, MODE) \
1060 ((MODE) == BImode && (CLASS) == PR_REGS ? 2 \
1061 : ((CLASS) == FR_REGS && (MODE) == XFmode) ? 1 \
1062 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1064 /* In FP regs, we can't change FP values to integer values and vice
1065 versa, but we can change e.g. DImode to SImode. */
1067 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1068 (GET_MODE_CLASS (FROM) != GET_MODE_CLASS (TO) \
1069 ? reg_classes_intersect_p (CLASS, FR_REGS) : 0)
1071 /* A C expression that defines the machine-dependent operand constraint
1072 letters (`I', `J', `K', .. 'P') that specify particular ranges of
1075 /* 14 bit signed immediate for arithmetic instructions. */
1076 #define CONST_OK_FOR_I(VALUE) \
1077 ((unsigned HOST_WIDE_INT)(VALUE) + 0x2000 < 0x4000)
1078 /* 22 bit signed immediate for arith instructions with r0/r1/r2/r3 source. */
1079 #define CONST_OK_FOR_J(VALUE) \
1080 ((unsigned HOST_WIDE_INT)(VALUE) + 0x200000 < 0x400000)
1081 /* 8 bit signed immediate for logical instructions. */
1082 #define CONST_OK_FOR_K(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x80 < 0x100)
1083 /* 8 bit adjusted signed immediate for compare pseudo-ops. */
1084 #define CONST_OK_FOR_L(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x7F < 0x100)
1085 /* 6 bit unsigned immediate for shift counts. */
1086 #define CONST_OK_FOR_M(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) < 0x40)
1087 /* 9 bit signed immediate for load/store post-increments. */
1088 #define CONST_OK_FOR_N(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x100 < 0x200)
1089 /* 0 for r0. Used by Linux kernel, do not change. */
1090 #define CONST_OK_FOR_O(VALUE) ((VALUE) == 0)
1091 /* 0 or -1 for dep instruction. */
1092 #define CONST_OK_FOR_P(VALUE) ((VALUE) == 0 || (VALUE) == -1)
1094 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1095 ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
1096 : (C) == 'J' ? CONST_OK_FOR_J (VALUE) \
1097 : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
1098 : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
1099 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
1100 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
1101 : (C) == 'O' ? CONST_OK_FOR_O (VALUE) \
1102 : (C) == 'P' ? CONST_OK_FOR_P (VALUE) \
1105 /* A C expression that defines the machine-dependent operand constraint letters
1106 (`G', `H') that specify particular ranges of `const_double' values. */
1108 /* 0.0 and 1.0 for fr0 and fr1. */
1109 #define CONST_DOUBLE_OK_FOR_G(VALUE) \
1110 ((VALUE) == CONST0_RTX (GET_MODE (VALUE)) \
1111 || (VALUE) == CONST1_RTX (GET_MODE (VALUE)))
1113 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1114 ((C) == 'G' ? CONST_DOUBLE_OK_FOR_G (VALUE) : 0)
1116 /* A C expression that defines the optional machine-dependent constraint
1117 letters (`Q', `R', `S', `T', `U') that can be used to segregate specific
1118 types of operands, usually memory references, for the target machine. */
1120 /* Non-volatile memory for FP_REG loads/stores. */
1121 #define CONSTRAINT_OK_FOR_Q(VALUE) \
1122 (memory_operand((VALUE), VOIDmode) && ! MEM_VOLATILE_P (VALUE))
1123 /* 1..4 for shladd arguments. */
1124 #define CONSTRAINT_OK_FOR_R(VALUE) \
1125 (GET_CODE (VALUE) == CONST_INT && INTVAL (VALUE) >= 1 && INTVAL (VALUE) <= 4)
1126 /* Non-post-inc memory for asms and other unsavory creatures. */
1127 #define CONSTRAINT_OK_FOR_S(VALUE) \
1128 (GET_CODE (VALUE) == MEM \
1129 && GET_RTX_CLASS (GET_CODE (XEXP ((VALUE), 0))) != RTX_AUTOINC \
1130 && (reload_in_progress || memory_operand ((VALUE), VOIDmode)))
1131 /* Symbol ref to small-address-area: */
1132 #define CONSTRAINT_OK_FOR_T(VALUE) \
1133 (GET_CODE (VALUE) == SYMBOL_REF && SYMBOL_REF_SMALL_ADDR_P (VALUE))
1135 #define EXTRA_CONSTRAINT(VALUE, C) \
1136 ((C) == 'Q' ? CONSTRAINT_OK_FOR_Q (VALUE) \
1137 : (C) == 'R' ? CONSTRAINT_OK_FOR_R (VALUE) \
1138 : (C) == 'S' ? CONSTRAINT_OK_FOR_S (VALUE) \
1139 : (C) == 'T' ? CONSTRAINT_OK_FOR_T (VALUE) \
1142 /* Basic Stack Layout */
1144 /* Define this macro if pushing a word onto the stack moves the stack pointer
1145 to a smaller address. */
1146 #define STACK_GROWS_DOWNWARD 1
1148 /* Define this macro if the addresses of local variable slots are at negative
1149 offsets from the frame pointer. */
1150 /* #define FRAME_GROWS_DOWNWARD */
1152 /* Offset from the frame pointer to the first local variable slot to
1154 #define STARTING_FRAME_OFFSET 0
1156 /* Offset from the stack pointer register to the first location at which
1157 outgoing arguments are placed. If not specified, the default value of zero
1158 is used. This is the proper value for most machines. */
1159 /* IA64 has a 16 byte scratch area that is at the bottom of the stack. */
1160 #define STACK_POINTER_OFFSET 16
1162 /* Offset from the argument pointer register to the first argument's address.
1163 On some machines it may depend on the data type of the function. */
1164 #define FIRST_PARM_OFFSET(FUNDECL) 0
1166 /* A C expression whose value is RTL representing the value of the return
1167 address for the frame COUNT steps up from the current frame, after the
1170 /* ??? Frames other than zero would likely require interpreting the frame
1171 unwind info, so we don't try to support them. We would also need to define
1172 DYNAMIC_CHAIN_ADDRESS and SETUP_FRAME_ADDRESS (for the reg stack flush). */
1174 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1175 ia64_return_addr_rtx (COUNT, FRAME)
1177 /* A C expression whose value is RTL representing the location of the incoming
1178 return address at the beginning of any function, before the prologue. This
1179 RTL is either a `REG', indicating that the return value is saved in `REG',
1180 or a `MEM' representing a location in the stack. This enables DWARF2
1181 unwind info for C++ EH. */
1182 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, BR_REG (0))
1184 /* ??? This is not defined because of three problems.
1185 1) dwarf2out.c assumes that DWARF_FRAME_RETURN_COLUMN fits in one byte.
1186 The default value is FIRST_PSEUDO_REGISTER which doesn't. This can be
1187 worked around by setting PC_REGNUM to FR_REG (0) which is an otherwise
1188 unused register number.
1189 2) dwarf2out_frame_debug core dumps while processing prologue insns. We
1190 need to refine which insns have RTX_FRAME_RELATED_P set and which don't.
1191 3) It isn't possible to turn off EH frame info by defining DWARF2_UNIND_INFO
1192 to zero, despite what the documentation implies, because it is tested in
1193 a few places with #ifdef instead of #if. */
1194 #undef INCOMING_RETURN_ADDR_RTX
1196 /* A C expression whose value is an integer giving the offset, in bytes, from
1197 the value of the stack pointer register to the top of the stack frame at the
1198 beginning of any function, before the prologue. The top of the frame is
1199 defined to be the value of the stack pointer in the previous frame, just
1200 before the call instruction. */
1201 #define INCOMING_FRAME_SP_OFFSET 0
1204 /* Register That Address the Stack Frame. */
1206 /* The register number of the stack pointer register, which must also be a
1207 fixed register according to `FIXED_REGISTERS'. On most machines, the
1208 hardware determines which register this is. */
1210 #define STACK_POINTER_REGNUM 12
1212 /* The register number of the frame pointer register, which is used to access
1213 automatic variables in the stack frame. On some machines, the hardware
1214 determines which register this is. On other machines, you can choose any
1215 register you wish for this purpose. */
1217 #define FRAME_POINTER_REGNUM 328
1219 /* Base register for access to local variables of the function. */
1220 #define HARD_FRAME_POINTER_REGNUM LOC_REG (79)
1222 /* The register number of the arg pointer register, which is used to access the
1223 function's argument list. */
1224 /* r0 won't otherwise be used, so put the always eliminated argument pointer
1226 #define ARG_POINTER_REGNUM R_GR(0)
1228 /* Due to the way varargs and argument spilling happens, the argument
1229 pointer is not 16-byte aligned like the stack pointer. */
1230 #define INIT_EXPANDERS \
1232 if (cfun && cfun->emit->regno_pointer_align) \
1233 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = 64; \
1236 /* Register numbers used for passing a function's static chain pointer. */
1237 /* ??? The ABI sez the static chain should be passed as a normal parameter. */
1238 #define STATIC_CHAIN_REGNUM 15
1240 /* Eliminating the Frame Pointer and the Arg Pointer */
1242 /* A C expression which is nonzero if a function must have and use a frame
1243 pointer. This expression is evaluated in the reload pass. If its value is
1244 nonzero the function will have a frame pointer. */
1245 #define FRAME_POINTER_REQUIRED 0
1247 /* Show we can debug even without a frame pointer. */
1248 #define CAN_DEBUG_WITHOUT_FP
1250 /* If defined, this macro specifies a table of register pairs used to eliminate
1251 unneeded registers that point into the stack frame. */
1253 #define ELIMINABLE_REGS \
1255 {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1256 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1257 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1258 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1261 /* A C expression that returns nonzero if the compiler is allowed to try to
1262 replace register number FROM with register number TO. The frame pointer
1263 is automatically handled. */
1265 #define CAN_ELIMINATE(FROM, TO) \
1266 (TO == BR_REG (0) ? current_function_is_leaf : 1)
1268 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
1269 specifies the initial difference between the specified pair of
1270 registers. This macro must be defined if `ELIMINABLE_REGS' is
1272 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1273 ((OFFSET) = ia64_initial_elimination_offset ((FROM), (TO)))
1275 /* Passing Function Arguments on the Stack */
1277 /* If defined, the maximum amount of space required for outgoing arguments will
1278 be computed and placed into the variable
1279 `current_function_outgoing_args_size'. */
1281 #define ACCUMULATE_OUTGOING_ARGS 1
1283 /* A C expression that should indicate the number of bytes of its own arguments
1284 that a function pops on returning, or 0 if the function pops no arguments
1285 and the caller must therefore pop them all after the function returns. */
1287 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
1290 /* Function Arguments in Registers */
1292 #define MAX_ARGUMENT_SLOTS 8
1293 #define MAX_INT_RETURN_SLOTS 4
1294 #define GR_ARG_FIRST IN_REG (0)
1295 #define GR_RET_FIRST GR_REG (8)
1296 #define GR_RET_LAST GR_REG (11)
1297 #define FR_ARG_FIRST FR_REG (8)
1298 #define FR_RET_FIRST FR_REG (8)
1299 #define FR_RET_LAST FR_REG (15)
1300 #define AR_ARG_FIRST OUT_REG (0)
1302 /* A C expression that controls whether a function argument is passed in a
1303 register, and which register. */
1305 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1306 ia64_function_arg (&CUM, MODE, TYPE, NAMED, 0)
1308 /* Define this macro if the target machine has "register windows", so that the
1309 register in which a function sees an arguments is not necessarily the same
1310 as the one in which the caller passed the argument. */
1312 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1313 ia64_function_arg (&CUM, MODE, TYPE, NAMED, 1)
1315 /* A C expression for the number of words, at the beginning of an argument,
1316 must be put in registers. The value must be zero for arguments that are
1317 passed entirely in registers or that are entirely pushed on the stack. */
1319 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1320 ia64_function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
1322 /* A C expression that indicates when an argument must be passed by reference.
1323 If nonzero for an argument, a copy of that argument is made in memory and a
1324 pointer to the argument is passed instead of the argument itself. The
1325 pointer is passed in whatever way is appropriate for passing a pointer to
1328 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1329 ia64_function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
1331 /* Nonzero if we do not know how to pass TYPE solely in registers. */
1333 #define MUST_PASS_IN_STACK(MODE, TYPE) \
1335 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1336 || TREE_ADDRESSABLE (TYPE)))
1338 /* A C type for declaring a variable that is used as the first argument of
1339 `FUNCTION_ARG' and other related values. For some target machines, the type
1340 `int' suffices and can hold the number of bytes of argument so far. */
1342 typedef struct ia64_args
1344 int words; /* # words of arguments so far */
1345 int int_regs; /* # GR registers used so far */
1346 int fp_regs; /* # FR registers used so far */
1347 int prototype; /* whether function prototyped */
1350 /* A C statement (sans semicolon) for initializing the variable CUM for the
1351 state at the beginning of the argument list. */
1353 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1356 (CUM).int_regs = 0; \
1357 (CUM).fp_regs = 0; \
1358 (CUM).prototype = ((FNTYPE) && TYPE_ARG_TYPES (FNTYPE)) || (LIBNAME); \
1361 /* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of finding the
1362 arguments for the function being compiled. If this macro is undefined,
1363 `INIT_CUMULATIVE_ARGS' is used instead. */
1365 /* We set prototype to true so that we never try to return a PARALLEL from
1367 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1370 (CUM).int_regs = 0; \
1371 (CUM).fp_regs = 0; \
1372 (CUM).prototype = 1; \
1375 /* A C statement (sans semicolon) to update the summarizer variable CUM to
1376 advance past an argument in the argument list. The values MODE, TYPE and
1377 NAMED describe that argument. Once this is done, the variable CUM is
1378 suitable for analyzing the *following* argument with `FUNCTION_ARG'. */
1380 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1381 ia64_function_arg_advance (&CUM, MODE, TYPE, NAMED)
1383 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1384 argument with the specified mode and type. */
1386 /* Arguments with alignment larger than 8 bytes start at the next even
1387 boundary. See ia64_function_arg. */
1389 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1390 (((TYPE) ? (TYPE_ALIGN (TYPE) > 8 * BITS_PER_UNIT) \
1391 : (((((MODE) == BLKmode \
1392 ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \
1393 + UNITS_PER_WORD - 1) / UNITS_PER_WORD) > 1)) \
1394 ? 128 : PARM_BOUNDARY)
1396 /* A C expression that is nonzero if REGNO is the number of a hard register in
1397 which function arguments are sometimes passed. This does *not* include
1398 implicit arguments such as the static chain and the structure-value address.
1399 On many machines, no registers can be used for this purpose since all
1400 function arguments are pushed on the stack. */
1401 #define FUNCTION_ARG_REGNO_P(REGNO) \
1402 (((REGNO) >= AR_ARG_FIRST && (REGNO) < (AR_ARG_FIRST + MAX_ARGUMENT_SLOTS)) \
1403 || ((REGNO) >= FR_ARG_FIRST && (REGNO) < (FR_ARG_FIRST + MAX_ARGUMENT_SLOTS)))
1405 /* Implement `va_arg'. */
1406 #define EXPAND_BUILTIN_VA_ARG(valist, type) (abort (), NULL_RTX)
1408 /* How Scalar Function Values are Returned */
1410 /* A C expression to create an RTX representing the place where a function
1411 returns a value of data type VALTYPE. */
1413 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1414 ia64_function_value (VALTYPE, FUNC)
1416 /* A C expression to create an RTX representing the place where a library
1417 function returns a value of mode MODE. */
1419 #define LIBCALL_VALUE(MODE) \
1420 gen_rtx_REG (MODE, \
1421 (((GET_MODE_CLASS (MODE) == MODE_FLOAT \
1422 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) && \
1424 ? FR_RET_FIRST : GR_RET_FIRST))
1426 /* A C expression that is nonzero if REGNO is the number of a hard register in
1427 which the values of called function may come back. */
1429 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1430 (((REGNO) >= GR_RET_FIRST && (REGNO) <= GR_RET_LAST) \
1431 || ((REGNO) >= FR_RET_FIRST && (REGNO) <= FR_RET_LAST))
1434 /* How Large Values are Returned */
1436 #define DEFAULT_PCC_STRUCT_RETURN 0
1439 /* Caller-Saves Register Allocation */
1441 /* A C expression to determine whether it is worthwhile to consider placing a
1442 pseudo-register in a call-clobbered hard register and saving and restoring
1443 it around each function call. The expression should be 1 when this is worth
1444 doing, and 0 otherwise.
1446 If you don't define this macro, a default is used which is good on most
1447 machines: `4 * CALLS < REFS'. */
1448 /* ??? Investigate. */
1449 /* #define CALLER_SAVE_PROFITABLE(REFS, CALLS) */
1452 /* Function Entry and Exit */
1454 /* Define this macro as a C expression that is nonzero if the return
1455 instruction or the function epilogue ignores the value of the stack pointer;
1456 in other words, if it is safe to delete an instruction to adjust the stack
1457 pointer before a return from the function. */
1459 #define EXIT_IGNORE_STACK 1
1461 /* Define this macro as a C expression that is nonzero for registers
1462 used by the epilogue or the `return' pattern. */
1464 #define EPILOGUE_USES(REGNO) ia64_epilogue_uses (REGNO)
1466 /* Nonzero for registers used by the exception handling mechanism. */
1468 #define EH_USES(REGNO) ia64_eh_uses (REGNO)
1470 /* Output part N of a function descriptor for DECL. For ia64, both
1471 words are emitted with a single relocation, so ignore N > 0. */
1472 #define ASM_OUTPUT_FDESC(FILE, DECL, PART) \
1477 fputs ("\tdata8.ua @iplt(", FILE); \
1479 fputs ("\tdata16.ua @iplt(", FILE); \
1480 mark_decl_referenced (DECL); \
1481 assemble_name (FILE, XSTR (XEXP (DECL_RTL (DECL), 0), 0)); \
1482 fputs (")\n", FILE); \
1484 fputs ("\tdata8.ua 0\n", FILE); \
1488 /* Generating Code for Profiling. */
1490 /* A C statement or compound statement to output to FILE some assembler code to
1491 call the profiling subroutine `mcount'. */
1493 #undef FUNCTION_PROFILER
1494 #define FUNCTION_PROFILER(FILE, LABELNO) \
1497 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", LABELNO); \
1498 fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", FILE); \
1499 if (TARGET_AUTO_PIC) \
1500 fputs ("\tmovl out3 = @gprel(", FILE); \
1502 fputs ("\taddl out3 = @ltoff(", FILE); \
1503 assemble_name (FILE, buf); \
1504 if (TARGET_AUTO_PIC) \
1505 fputs (");;\n", FILE); \
1507 fputs ("), r1;;\n", FILE); \
1508 fputs ("\tmov out1 = r1\n", FILE); \
1509 fputs ("\tmov out2 = b0\n", FILE); \
1510 fputs ("\tbr.call.sptk.many b0 = _mcount;;\n", FILE); \
1513 /* Trampolines for Nested Functions. */
1515 /* We need 32 bytes, so we can save the sp, ar.rnat, ar.bsp, and ar.pfs of
1516 the function containing a non-local goto target. */
1518 #define STACK_SAVEAREA_MODE(LEVEL) \
1519 ((LEVEL) == SAVE_NONLOCAL ? OImode : Pmode)
1521 /* Output assembler code for a block containing the constant parts of
1522 a trampoline, leaving space for the variable parts.
1524 The trampoline should set the static chain pointer to value placed
1525 into the trampoline and should branch to the specified routine.
1526 To make the normal indirect-subroutine calling convention work,
1527 the trampoline must look like a function descriptor; the first
1528 word being the target address and the second being the target's
1531 We abuse the concept of a global pointer by arranging for it
1532 to point to the data we need to load. The complete trampoline
1533 has the following form:
1535 +-------------------+ \
1536 TRAMP: | __ia64_trampoline | |
1537 +-------------------+ > fake function descriptor
1539 +-------------------+ /
1540 | target descriptor |
1541 +-------------------+
1543 +-------------------+
1546 /* A C expression for the size in bytes of the trampoline, as an integer. */
1548 #define TRAMPOLINE_SIZE 32
1550 /* Alignment required for trampolines, in bits. */
1552 #define TRAMPOLINE_ALIGNMENT 64
1554 /* A C statement to initialize the variable parts of a trampoline. */
1556 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, STATIC_CHAIN) \
1557 ia64_initialize_trampoline((ADDR), (FNADDR), (STATIC_CHAIN))
1559 /* Implicit Calls to Library Routines */
1561 /* Define this macro if GCC should generate calls to the System V (and ANSI
1562 C) library functions `memcpy' and `memset' rather than the BSD functions
1563 `bcopy' and `bzero'. */
1565 #define TARGET_MEM_FUNCTIONS
1568 /* Addressing Modes */
1570 /* Define this macro if the machine supports post-increment addressing. */
1572 #define HAVE_POST_INCREMENT 1
1573 #define HAVE_POST_DECREMENT 1
1574 #define HAVE_POST_MODIFY_DISP 1
1575 #define HAVE_POST_MODIFY_REG 1
1577 /* A C expression that is 1 if the RTX X is a constant which is a valid
1580 #define CONSTANT_ADDRESS_P(X) 0
1582 /* The max number of registers that can appear in a valid memory address. */
1584 #define MAX_REGS_PER_ADDRESS 2
1586 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
1587 RTX) is a legitimate memory address on the target machine for a memory
1588 operand of mode MODE. */
1590 #define LEGITIMATE_ADDRESS_REG(X) \
1591 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1592 || (GET_CODE (X) == SUBREG && GET_CODE (XEXP (X, 0)) == REG \
1593 && REG_OK_FOR_BASE_P (XEXP (X, 0))))
1595 #define LEGITIMATE_ADDRESS_DISP(R, X) \
1596 (GET_CODE (X) == PLUS \
1597 && rtx_equal_p (R, XEXP (X, 0)) \
1598 && (LEGITIMATE_ADDRESS_REG (XEXP (X, 1)) \
1599 || (GET_CODE (XEXP (X, 1)) == CONST_INT \
1600 && INTVAL (XEXP (X, 1)) >= -256 \
1601 && INTVAL (XEXP (X, 1)) < 256)))
1603 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1605 if (LEGITIMATE_ADDRESS_REG (X)) \
1607 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
1608 && LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \
1609 && XEXP (X, 0) != arg_pointer_rtx) \
1611 else if (GET_CODE (X) == POST_MODIFY \
1612 && LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \
1613 && XEXP (X, 0) != arg_pointer_rtx \
1614 && LEGITIMATE_ADDRESS_DISP (XEXP (X, 0), XEXP (X, 1))) \
1618 /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
1619 use as a base register. */
1621 #ifdef REG_OK_STRICT
1622 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1624 #define REG_OK_FOR_BASE_P(X) \
1625 (GENERAL_REGNO_P (REGNO (X)) || (REGNO (X) >= FIRST_PSEUDO_REGISTER))
1628 /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
1629 use as an index register. This is needed for POST_MODIFY. */
1631 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1633 /* A C statement or compound statement with a conditional `goto LABEL;'
1634 executed if memory address X (an RTX) can have different meanings depending
1635 on the machine mode of the memory reference it is used for or if the address
1636 is valid for some modes but not others. */
1638 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1639 if (GET_CODE (ADDR) == POST_DEC || GET_CODE (ADDR) == POST_INC) \
1642 /* A C expression that is nonzero if X is a legitimate constant for an
1643 immediate operand on the target machine. */
1645 #define LEGITIMATE_CONSTANT_P(X) \
1646 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode \
1647 || GET_MODE (X) == DImode || CONST_DOUBLE_OK_FOR_G (X)) \
1650 /* Condition Code Status */
1652 /* One some machines not all possible comparisons are defined, but you can
1653 convert an invalid comparison into a valid one. */
1654 /* ??? Investigate. See the alpha definition. */
1655 /* #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) */
1658 /* Describing Relative Costs of Operations */
1660 /* A C expression for the cost of moving data from a register in class FROM to
1661 one in class TO, using MODE. */
1663 #define REGISTER_MOVE_COST ia64_register_move_cost
1665 /* A C expression for the cost of moving data of mode M between a
1666 register and memory. */
1667 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
1668 ((CLASS) == GENERAL_REGS || (CLASS) == FR_REGS \
1669 || (CLASS) == GR_AND_FR_REGS ? 4 : 10)
1671 /* A C expression for the cost of a branch instruction. A value of 1 is the
1672 default; other values are interpreted relative to that. Used by the
1673 if-conversion code as max instruction count. */
1674 /* ??? This requires investigation. The primary effect might be how
1675 many additional insn groups we run into, vs how good the dynamic
1676 branch predictor is. */
1678 #define BRANCH_COST 6
1680 /* Define this macro as a C expression which is nonzero if accessing less than
1681 a word of memory (i.e. a `char' or a `short') is no faster than accessing a
1684 #define SLOW_BYTE_ACCESS 1
1686 /* Define this macro if it is as good or better to call a constant function
1687 address than to call an address kept in a register.
1689 Indirect function calls are more expensive that direct function calls, so
1690 don't cse function addresses. */
1692 #define NO_FUNCTION_CSE
1695 /* Dividing the output into sections. */
1697 /* A C expression whose value is a string containing the assembler operation
1698 that should precede instructions and read-only data. */
1700 #define TEXT_SECTION_ASM_OP "\t.text"
1702 /* A C expression whose value is a string containing the assembler operation to
1703 identify the following data as writable initialized data. */
1705 #define DATA_SECTION_ASM_OP "\t.data"
1707 /* If defined, a C expression whose value is a string containing the assembler
1708 operation to identify the following data as uninitialized global data. */
1710 #define BSS_SECTION_ASM_OP "\t.bss"
1712 #define IA64_DEFAULT_GVALUE 8
1714 /* Position Independent Code. */
1716 /* The register number of the register used to address a table of static data
1717 addresses in memory. */
1719 /* ??? Should modify ia64.md to use pic_offset_table_rtx instead of
1720 gen_rtx_REG (DImode, 1). */
1722 /* ??? Should we set flag_pic? Probably need to define
1723 LEGITIMIZE_PIC_OPERAND_P to make that work. */
1725 #define PIC_OFFSET_TABLE_REGNUM GR_REG (1)
1727 /* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' is
1728 clobbered by calls. */
1730 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
1733 /* The Overall Framework of an Assembler File. */
1735 /* A C string constant describing how to begin a comment in the target
1736 assembler language. The compiler assumes that the comment will end at the
1739 #define ASM_COMMENT_START "//"
1741 /* A C string constant for text to be output before each `asm' statement or
1742 group of consecutive ones. */
1744 #define ASM_APP_ON (TARGET_GNU_AS ? "#APP\n" : "//APP\n")
1746 /* A C string constant for text to be output after each `asm' statement or
1747 group of consecutive ones. */
1749 #define ASM_APP_OFF (TARGET_GNU_AS ? "#NO_APP\n" : "//NO_APP\n")
1751 /* Output of Uninitialized Variables. */
1753 /* This is all handled by svr4.h. */
1756 /* Output and Generation of Labels. */
1758 /* A C statement (sans semicolon) to output to the stdio stream STREAM the
1759 assembler definition of a label named NAME. */
1761 /* See the ASM_OUTPUT_LABELREF definition in sysv4.h for an explanation of
1762 why ia64_asm_output_label exists. */
1764 extern int ia64_asm_output_label;
1765 #define ASM_OUTPUT_LABEL(STREAM, NAME) \
1767 ia64_asm_output_label = 1; \
1768 assemble_name (STREAM, NAME); \
1769 fputs (":\n", STREAM); \
1770 ia64_asm_output_label = 0; \
1773 /* Globalizing directive for a label. */
1774 #define GLOBAL_ASM_OP "\t.global "
1776 /* A C statement (sans semicolon) to output to the stdio stream STREAM any text
1777 necessary for declaring the name of an external symbol named NAME which is
1778 referenced in this compilation but not defined. */
1780 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
1781 ia64_asm_output_external (FILE, DECL, NAME)
1783 /* A C statement to store into the string STRING a label whose name is made
1784 from the string PREFIX and the number NUM. */
1786 #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \
1788 sprintf (LABEL, "*.%s%d", PREFIX, NUM); \
1791 /* ??? Not sure if using a ? in the name for Intel as is safe. */
1793 #define ASM_PN_FORMAT (TARGET_GNU_AS ? "%s.%lu" : "%s?%lu")
1795 /* A C statement to output to the stdio stream STREAM assembler code which
1796 defines (equates) the symbol NAME to have the value VALUE. */
1798 #define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \
1800 assemble_name (STREAM, NAME); \
1801 fputs (" = ", STREAM); \
1802 assemble_name (STREAM, VALUE); \
1803 fputc ('\n', STREAM); \
1807 /* Macros Controlling Initialization Routines. */
1809 /* This is handled by svr4.h and sysv4.h. */
1812 /* Output of Assembler Instructions. */
1814 /* A C initializer containing the assembler's names for the machine registers,
1815 each one as a C string constant. */
1817 #define REGISTER_NAMES \
1819 /* General registers. */ \
1820 "ap", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \
1821 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \
1822 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \
1824 /* Local registers. */ \
1825 "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7", \
1826 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15", \
1827 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23", \
1828 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31", \
1829 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39", \
1830 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47", \
1831 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55", \
1832 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63", \
1833 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71", \
1834 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79", \
1835 /* Input registers. */ \
1836 "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7", \
1837 /* Output registers. */ \
1838 "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7", \
1839 /* Floating-point registers. */ \
1840 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", \
1841 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", \
1842 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", \
1843 "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", \
1844 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", \
1845 "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", \
1846 "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69", \
1847 "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79", \
1848 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89", \
1849 "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99", \
1850 "f100","f101","f102","f103","f104","f105","f106","f107","f108","f109",\
1851 "f110","f111","f112","f113","f114","f115","f116","f117","f118","f119",\
1852 "f120","f121","f122","f123","f124","f125","f126","f127", \
1853 /* Predicate registers. */ \
1854 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", \
1855 "p10", "p11", "p12", "p13", "p14", "p15", "p16", "p17", "p18", "p19", \
1856 "p20", "p21", "p22", "p23", "p24", "p25", "p26", "p27", "p28", "p29", \
1857 "p30", "p31", "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39", \
1858 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47", "p48", "p49", \
1859 "p50", "p51", "p52", "p53", "p54", "p55", "p56", "p57", "p58", "p59", \
1860 "p60", "p61", "p62", "p63", \
1861 /* Branch registers. */ \
1862 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", \
1863 /* Frame pointer. Application registers. */ \
1864 "sfp", "ar.ccv", "ar.unat", "ar.pfs", "ar.lc", "ar.ec", \
1867 /* If defined, a C initializer for an array of structures containing a name and
1868 a register number. This macro defines additional names for hard registers,
1869 thus allowing the `asm' option in declarations to refer to registers using
1872 #define ADDITIONAL_REGISTER_NAMES \
1874 { "gp", R_GR (1) }, \
1875 { "sp", R_GR (12) }, \
1876 { "in0", IN_REG (0) }, \
1877 { "in1", IN_REG (1) }, \
1878 { "in2", IN_REG (2) }, \
1879 { "in3", IN_REG (3) }, \
1880 { "in4", IN_REG (4) }, \
1881 { "in5", IN_REG (5) }, \
1882 { "in6", IN_REG (6) }, \
1883 { "in7", IN_REG (7) }, \
1884 { "out0", OUT_REG (0) }, \
1885 { "out1", OUT_REG (1) }, \
1886 { "out2", OUT_REG (2) }, \
1887 { "out3", OUT_REG (3) }, \
1888 { "out4", OUT_REG (4) }, \
1889 { "out5", OUT_REG (5) }, \
1890 { "out6", OUT_REG (6) }, \
1891 { "out7", OUT_REG (7) }, \
1892 { "loc0", LOC_REG (0) }, \
1893 { "loc1", LOC_REG (1) }, \
1894 { "loc2", LOC_REG (2) }, \
1895 { "loc3", LOC_REG (3) }, \
1896 { "loc4", LOC_REG (4) }, \
1897 { "loc5", LOC_REG (5) }, \
1898 { "loc6", LOC_REG (6) }, \
1899 { "loc7", LOC_REG (7) }, \
1900 { "loc8", LOC_REG (8) }, \
1901 { "loc9", LOC_REG (9) }, \
1902 { "loc10", LOC_REG (10) }, \
1903 { "loc11", LOC_REG (11) }, \
1904 { "loc12", LOC_REG (12) }, \
1905 { "loc13", LOC_REG (13) }, \
1906 { "loc14", LOC_REG (14) }, \
1907 { "loc15", LOC_REG (15) }, \
1908 { "loc16", LOC_REG (16) }, \
1909 { "loc17", LOC_REG (17) }, \
1910 { "loc18", LOC_REG (18) }, \
1911 { "loc19", LOC_REG (19) }, \
1912 { "loc20", LOC_REG (20) }, \
1913 { "loc21", LOC_REG (21) }, \
1914 { "loc22", LOC_REG (22) }, \
1915 { "loc23", LOC_REG (23) }, \
1916 { "loc24", LOC_REG (24) }, \
1917 { "loc25", LOC_REG (25) }, \
1918 { "loc26", LOC_REG (26) }, \
1919 { "loc27", LOC_REG (27) }, \
1920 { "loc28", LOC_REG (28) }, \
1921 { "loc29", LOC_REG (29) }, \
1922 { "loc30", LOC_REG (30) }, \
1923 { "loc31", LOC_REG (31) }, \
1924 { "loc32", LOC_REG (32) }, \
1925 { "loc33", LOC_REG (33) }, \
1926 { "loc34", LOC_REG (34) }, \
1927 { "loc35", LOC_REG (35) }, \
1928 { "loc36", LOC_REG (36) }, \
1929 { "loc37", LOC_REG (37) }, \
1930 { "loc38", LOC_REG (38) }, \
1931 { "loc39", LOC_REG (39) }, \
1932 { "loc40", LOC_REG (40) }, \
1933 { "loc41", LOC_REG (41) }, \
1934 { "loc42", LOC_REG (42) }, \
1935 { "loc43", LOC_REG (43) }, \
1936 { "loc44", LOC_REG (44) }, \
1937 { "loc45", LOC_REG (45) }, \
1938 { "loc46", LOC_REG (46) }, \
1939 { "loc47", LOC_REG (47) }, \
1940 { "loc48", LOC_REG (48) }, \
1941 { "loc49", LOC_REG (49) }, \
1942 { "loc50", LOC_REG (50) }, \
1943 { "loc51", LOC_REG (51) }, \
1944 { "loc52", LOC_REG (52) }, \
1945 { "loc53", LOC_REG (53) }, \
1946 { "loc54", LOC_REG (54) }, \
1947 { "loc55", LOC_REG (55) }, \
1948 { "loc56", LOC_REG (56) }, \
1949 { "loc57", LOC_REG (57) }, \
1950 { "loc58", LOC_REG (58) }, \
1951 { "loc59", LOC_REG (59) }, \
1952 { "loc60", LOC_REG (60) }, \
1953 { "loc61", LOC_REG (61) }, \
1954 { "loc62", LOC_REG (62) }, \
1955 { "loc63", LOC_REG (63) }, \
1956 { "loc64", LOC_REG (64) }, \
1957 { "loc65", LOC_REG (65) }, \
1958 { "loc66", LOC_REG (66) }, \
1959 { "loc67", LOC_REG (67) }, \
1960 { "loc68", LOC_REG (68) }, \
1961 { "loc69", LOC_REG (69) }, \
1962 { "loc70", LOC_REG (70) }, \
1963 { "loc71", LOC_REG (71) }, \
1964 { "loc72", LOC_REG (72) }, \
1965 { "loc73", LOC_REG (73) }, \
1966 { "loc74", LOC_REG (74) }, \
1967 { "loc75", LOC_REG (75) }, \
1968 { "loc76", LOC_REG (76) }, \
1969 { "loc77", LOC_REG (77) }, \
1970 { "loc78", LOC_REG (78) }, \
1971 { "loc79", LOC_REG (79) }, \
1974 /* Emit a dtp-relative reference to a TLS variable. */
1977 #define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \
1978 ia64_output_dwarf_dtprel (FILE, SIZE, X)
1981 /* A C compound statement to output to stdio stream STREAM the assembler syntax
1982 for an instruction operand X. X is an RTL expression. */
1984 #define PRINT_OPERAND(STREAM, X, CODE) \
1985 ia64_print_operand (STREAM, X, CODE)
1987 /* A C expression which evaluates to true if CODE is a valid punctuation
1988 character for use in the `PRINT_OPERAND' macro. */
1990 /* ??? Keep this around for now, as we might need it later. */
1992 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1993 ((CODE) == '+' || (CODE) == ',')
1995 /* A C compound statement to output to stdio stream STREAM the assembler syntax
1996 for an instruction operand that is a memory reference whose address is X. X
1997 is an RTL expression. */
1999 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2000 ia64_print_operand_address (STREAM, X)
2002 /* If defined, C string expressions to be used for the `%R', `%L', `%U', and
2003 `%I' options of `asm_fprintf' (see `final.c'). */
2005 #define REGISTER_PREFIX ""
2006 #define LOCAL_LABEL_PREFIX "."
2007 #define USER_LABEL_PREFIX ""
2008 #define IMMEDIATE_PREFIX ""
2011 /* Output of dispatch tables. */
2013 /* This macro should be provided on machines where the addresses in a dispatch
2014 table are relative to the table's own address. */
2016 /* ??? Depends on the pointer size. */
2018 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2021 fprintf (STREAM, "\tdata4 @pcrel(.L%d)\n", VALUE); \
2023 fprintf (STREAM, "\tdata8 @pcrel(.L%d)\n", VALUE); \
2026 /* This is how to output an element of a case-vector that is absolute.
2027 (Ia64 does not use such vectors, but we must define this macro anyway.) */
2029 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) abort ()
2031 /* Jump tables only need 8 byte alignment. */
2033 #define ADDR_VEC_ALIGN(ADDR_VEC) 3
2036 /* Assembler Commands for Exception Regions. */
2038 /* Select a format to encode pointers in exception handling data. CODE
2039 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2040 true if the symbol may be affected by dynamic relocations. */
2041 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2042 (((CODE) == 1 ? DW_EH_PE_textrel : DW_EH_PE_datarel) \
2043 | ((GLOBAL) ? DW_EH_PE_indirect : 0) \
2044 | (TARGET_ILP32 ? DW_EH_PE_udata4 : DW_EH_PE_udata8))
2046 /* Handle special EH pointer encodings. Absolute, pc-relative, and
2047 indirect are handled automatically. */
2048 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
2050 const char *reltag = NULL; \
2051 if (((ENCODING) & 0xF0) == DW_EH_PE_textrel) \
2052 reltag = "@segrel("; \
2053 else if (((ENCODING) & 0xF0) == DW_EH_PE_datarel) \
2054 reltag = "@gprel("; \
2057 fputs (integer_asm_op (SIZE, FALSE), FILE); \
2058 fputs (reltag, FILE); \
2059 assemble_name (FILE, XSTR (ADDR, 0)); \
2060 fputc (')', FILE); \
2066 /* Assembler Commands for Alignment. */
2068 /* ??? Investigate. */
2070 /* The alignment (log base 2) to put in front of LABEL, which follows
2073 /* #define LABEL_ALIGN_AFTER_BARRIER(LABEL) */
2075 /* The desired alignment for the location counter at the beginning
2078 /* #define LOOP_ALIGN(LABEL) */
2080 /* Define this macro if `ASM_OUTPUT_SKIP' should not be used in the text
2081 section because it fails put zeros in the bytes that are skipped. */
2083 #define ASM_NO_SKIP_IN_TEXT 1
2085 /* A C statement to output to the stdio stream STREAM an assembler command to
2086 advance the location counter to a multiple of 2 to the POWER bytes. */
2088 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
2089 fprintf (STREAM, "\t.align %d\n", 1<<(POWER))
2092 /* Macros Affecting all Debug Formats. */
2094 /* This is handled in svr4.h and sysv4.h. */
2097 /* Specific Options for DBX Output. */
2099 /* This is handled by dbxelf.h which is included by svr4.h. */
2102 /* Open ended Hooks for DBX Output. */
2107 /* File names in DBX format. */
2112 /* Macros for SDB and Dwarf Output. */
2114 /* Define this macro if GCC should produce dwarf version 2 format debugging
2115 output in response to the `-g' option. */
2117 #define DWARF2_DEBUGGING_INFO 1
2119 #define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DWARF2_ASM)
2121 /* Use tags for debug info labels, so that they don't break instruction
2122 bundles. This also avoids getting spurious DV warnings from the
2123 assembler. This is similar to (*targetm.asm_out.internal_label), except that we
2124 add brackets around the label. */
2126 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2127 fprintf (FILE, TARGET_GNU_AS ? "[.%s%d:]\n" : ".%s%d:\n", PREFIX, NUM)
2129 /* Use section-relative relocations for debugging offsets. Unlike other
2130 targets that fake this by putting the section VMA at 0, IA-64 has
2131 proper relocations for them. */
2132 #define ASM_OUTPUT_DWARF_OFFSET(FILE, SIZE, LABEL) \
2134 fputs (integer_asm_op (SIZE, FALSE), FILE); \
2135 fputs ("@secrel(", FILE); \
2136 assemble_name (FILE, LABEL); \
2137 fputc (')', FILE); \
2140 /* Emit a PC-relative relocation. */
2141 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
2143 fputs (integer_asm_op (SIZE, FALSE), FILE); \
2144 fputs ("@pcrel(", FILE); \
2145 assemble_name (FILE, LABEL); \
2146 fputc (')', FILE); \
2149 /* Register Renaming Parameters. */
2151 /* A C expression that is nonzero if hard register number REGNO2 can be
2152 considered for use as a rename register for REGNO1 */
2154 #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \
2155 ia64_hard_regno_rename_ok((REGNO1), (REGNO2))
2158 /* Miscellaneous Parameters. */
2160 /* Flag to mark data that is in the small address area (addressable
2161 via "addl", that is, within a 2MByte offset of 0. */
2162 #define SYMBOL_FLAG_SMALL_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2163 #define SYMBOL_REF_SMALL_ADDR_P(X) \
2164 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_SMALL_ADDR) != 0)
2166 /* Define this if you have defined special-purpose predicates in the file
2167 `MACHINE.c'. For each predicate, list all rtl codes that can be in
2168 expressions matched by the predicate. */
2170 #define PREDICATE_CODES \
2171 { "call_operand", {SUBREG, REG, SYMBOL_REF}}, \
2172 { "got_symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2173 { "sdata_symbolic_operand", {SYMBOL_REF, CONST}}, \
2174 { "small_addr_symbolic_operand", {SYMBOL_REF}}, \
2175 { "symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2176 { "function_operand", {SYMBOL_REF}}, \
2177 { "setjmp_operand", {SYMBOL_REF}}, \
2178 { "destination_operand", {SUBREG, REG, MEM}}, \
2179 { "not_postinc_memory_operand", {MEM}}, \
2180 { "move_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2181 SYMBOL_REF, CONST, LABEL_REF}}, \
2182 { "gr_register_operand", {SUBREG, REG}}, \
2183 { "fr_register_operand", {SUBREG, REG}}, \
2184 { "grfr_register_operand", {SUBREG, REG}}, \
2185 { "gr_nonimmediate_operand", {SUBREG, REG, MEM}}, \
2186 { "fr_nonimmediate_operand", {SUBREG, REG, MEM}}, \
2187 { "grfr_nonimmediate_operand", {SUBREG, REG, MEM}}, \
2188 { "gr_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
2189 { "gr_reg_or_5bit_operand", {SUBREG, REG, CONST_INT}}, \
2190 { "gr_reg_or_6bit_operand", {SUBREG, REG, CONST_INT}}, \
2191 { "gr_reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \
2192 { "grfr_reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \
2193 { "gr_reg_or_8bit_adjusted_operand", {SUBREG, REG, CONST_INT}}, \
2194 { "gr_reg_or_8bit_and_adjusted_operand", {SUBREG, REG, CONST_INT}}, \
2195 { "gr_reg_or_14bit_operand", {SUBREG, REG, CONST_INT}}, \
2196 { "gr_reg_or_22bit_operand", {SUBREG, REG, CONST_INT}}, \
2197 { "shift_count_operand", {SUBREG, REG, CONST_INT}}, \
2198 { "shift_32bit_count_operand", {SUBREG, REG, CONST_INT}}, \
2199 { "shladd_operand", {CONST_INT}}, \
2200 { "fetchadd_operand", {CONST_INT}}, \
2201 { "fr_reg_or_fp01_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2202 { "normal_comparison_operator", {EQ, NE, GT, LE, GTU, LEU}}, \
2203 { "adjusted_comparison_operator", {LT, GE, LTU, GEU}}, \
2204 { "signed_inequality_operator", {GE, GT, LE, LT}}, \
2205 { "predicate_operator", {NE, EQ}}, \
2206 { "condop_operator", {PLUS, MINUS, IOR, XOR, AND}}, \
2207 { "ar_lc_reg_operand", {REG}}, \
2208 { "ar_ccv_reg_operand", {REG}}, \
2209 { "ar_pfs_reg_operand", {REG}}, \
2210 { "general_xfmode_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2211 { "destination_xfmode_operand", {SUBREG, REG, MEM}}, \
2212 { "xfreg_or_fp01_operand", {REG, CONST_DOUBLE}}, \
2213 { "basereg_operand", {SUBREG, REG}},
2215 /* An alias for a machine mode name. This is the machine mode that elements of
2216 a jump-table should have. */
2218 #define CASE_VECTOR_MODE ptr_mode
2220 /* Define as C expression which evaluates to nonzero if the tablejump
2221 instruction expects the table to contain offsets from the address of the
2224 #define CASE_VECTOR_PC_RELATIVE 1
2226 /* Define this macro if operations between registers with integral mode smaller
2227 than a word are always performed on the entire register. */
2229 #define WORD_REGISTER_OPERATIONS
2231 /* Define this macro to be a C expression indicating when insns that read
2232 memory in MODE, an integral mode narrower than a word, set the bits outside
2233 of MODE to be either the sign-extension or the zero-extension of the data
2236 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2238 /* The maximum number of bytes that a single instruction can move quickly from
2239 memory to memory. */
2242 /* A C expression which is nonzero if on this machine it is safe to "convert"
2243 an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller
2244 than INPREC) by merely operating on it as if it had only OUTPREC bits. */
2246 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2248 /* A C expression describing the value returned by a comparison operator with
2249 an integral mode and stored by a store-flag instruction (`sCOND') when the
2250 condition is true. */
2252 /* ??? Investigate using STORE_FLAG_VALUE of -1 instead of 1. */
2254 /* An alias for the machine mode for pointers. */
2256 /* ??? This would change if we had ILP32 support. */
2258 #define Pmode DImode
2260 /* An alias for the machine mode used for memory references to functions being
2261 called, in `call' RTL expressions. */
2263 #define FUNCTION_MODE Pmode
2265 /* Define this macro to handle System V style pragmas: #pragma pack and
2266 #pragma weak. Note, #pragma weak will only be supported if SUPPORT_WEAK is
2269 /* If this architecture supports prefetch, define this to be the number of
2270 prefetch commands that can be executed in parallel.
2272 ??? This number is bogus and needs to be replaced before the value is
2273 actually used in optimizations. */
2275 #define SIMULTANEOUS_PREFETCHES 6
2277 /* If this architecture supports prefetch, define this to be the size of
2278 the cache line that is prefetched. */
2280 #define PREFETCH_BLOCK 32
2282 #define HANDLE_SYSV_PRAGMA 1
2284 /* A C expression for the maximum number of instructions to execute via
2285 conditional execution instructions instead of a branch. A value of
2286 BRANCH_COST+1 is the default if the machine does not use
2287 cc0, and 1 if it does use cc0. */
2288 /* ??? Investigate. */
2289 #define MAX_CONDITIONAL_EXECUTE 12
2291 extern int ia64_final_schedule;
2293 #define IA64_UNWIND_INFO 1
2294 #define IA64_UNWIND_EMIT(f,i) process_for_unwind_directive (f,i)
2296 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 15 : INVALID_REGNUM)
2298 /* This function contains machine specific function data. */
2299 struct machine_function GTY(())
2301 /* The new stack pointer when unwinding from EH. */
2302 rtx ia64_eh_epilogue_sp;
2304 /* The new bsp value when unwinding from EH. */
2305 rtx ia64_eh_epilogue_bsp;
2307 /* The GP value save register. */
2310 /* The number of varargs registers to save. */
2317 IA64_BUILTIN_SYNCHRONIZE,
2319 IA64_BUILTIN_FETCH_AND_ADD_SI,
2320 IA64_BUILTIN_FETCH_AND_SUB_SI,
2321 IA64_BUILTIN_FETCH_AND_OR_SI,
2322 IA64_BUILTIN_FETCH_AND_AND_SI,
2323 IA64_BUILTIN_FETCH_AND_XOR_SI,
2324 IA64_BUILTIN_FETCH_AND_NAND_SI,
2326 IA64_BUILTIN_ADD_AND_FETCH_SI,
2327 IA64_BUILTIN_SUB_AND_FETCH_SI,
2328 IA64_BUILTIN_OR_AND_FETCH_SI,
2329 IA64_BUILTIN_AND_AND_FETCH_SI,
2330 IA64_BUILTIN_XOR_AND_FETCH_SI,
2331 IA64_BUILTIN_NAND_AND_FETCH_SI,
2333 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI,
2334 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI,
2336 IA64_BUILTIN_SYNCHRONIZE_SI,
2338 IA64_BUILTIN_LOCK_TEST_AND_SET_SI,
2340 IA64_BUILTIN_LOCK_RELEASE_SI,
2342 IA64_BUILTIN_FETCH_AND_ADD_DI,
2343 IA64_BUILTIN_FETCH_AND_SUB_DI,
2344 IA64_BUILTIN_FETCH_AND_OR_DI,
2345 IA64_BUILTIN_FETCH_AND_AND_DI,
2346 IA64_BUILTIN_FETCH_AND_XOR_DI,
2347 IA64_BUILTIN_FETCH_AND_NAND_DI,
2349 IA64_BUILTIN_ADD_AND_FETCH_DI,
2350 IA64_BUILTIN_SUB_AND_FETCH_DI,
2351 IA64_BUILTIN_OR_AND_FETCH_DI,
2352 IA64_BUILTIN_AND_AND_FETCH_DI,
2353 IA64_BUILTIN_XOR_AND_FETCH_DI,
2354 IA64_BUILTIN_NAND_AND_FETCH_DI,
2356 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI,
2357 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI,
2359 IA64_BUILTIN_SYNCHRONIZE_DI,
2361 IA64_BUILTIN_LOCK_TEST_AND_SET_DI,
2363 IA64_BUILTIN_LOCK_RELEASE_DI,
2366 IA64_BUILTIN_FLUSHRS
2369 /* Codes for expand_compare_and_swap and expand_swap_and_compare. */
2371 IA64_ADD_OP, IA64_SUB_OP, IA64_OR_OP, IA64_AND_OP, IA64_XOR_OP, IA64_NAND_OP
2374 #define DONT_USE_BUILTIN_SETJMP
2376 /* Output any profiling code before the prologue. */
2378 #undef PROFILE_BEFORE_PROLOGUE
2379 #define PROFILE_BEFORE_PROLOGUE 1
2381 /* Initialize library function table. */
2382 #undef TARGET_INIT_LIBFUNCS
2383 #define TARGET_INIT_LIBFUNCS ia64_init_libfuncs
2387 /* Switch on code for querying unit reservations. */
2388 #define CPU_UNITS_QUERY 1
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