1 /* Definitions of target machine GNU compiler. IA-64 version.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
3 2009, 2010, 2011 Free Software Foundation, Inc.
4 Contributed by James E. Wilson <wilson@cygnus.com> and
5 David Mosberger <davidm@hpl.hp.com>.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
23 /* ??? Look at ABI group documents for list of preprocessor macros and
24 other features required for ABI compliance. */
26 /* ??? Functions containing a non-local goto target save many registers. Why?
27 See for instance execute/920428-2.c. */
30 /* Run-time target specifications */
32 /* Target CPU builtins. */
33 #define TARGET_CPU_CPP_BUILTINS() \
35 builtin_assert("cpu=ia64"); \
36 builtin_assert("machine=ia64"); \
37 builtin_define("__ia64"); \
38 builtin_define("__ia64__"); \
39 builtin_define("__itanium__"); \
40 if (TARGET_BIG_ENDIAN) \
41 builtin_define("__BIG_ENDIAN__"); \
44 #ifndef SUBTARGET_EXTRA_SPECS
45 #define SUBTARGET_EXTRA_SPECS
49 { "asm_extra", ASM_EXTRA_SPEC }, \
52 #define CC1_SPEC "%(cc1_cpu) "
54 #define ASM_EXTRA_SPEC ""
56 /* Variables which are this size or smaller are put in the sdata/sbss
58 extern unsigned int ia64_section_threshold;
60 /* If the assembler supports thread-local storage, assume that the
61 system does as well. If a particular target system has an
62 assembler that supports TLS -- but the rest of the system does not
63 support TLS -- that system should explicit define TARGET_HAVE_TLS
64 to false in its own configuration file. */
65 #if !defined(TARGET_HAVE_TLS) && defined(HAVE_AS_TLS)
66 #define TARGET_HAVE_TLS true
69 #define TARGET_TLS14 (ia64_tls_size == 14)
70 #define TARGET_TLS22 (ia64_tls_size == 22)
71 #define TARGET_TLS64 (ia64_tls_size == 64)
74 #define TARGET_HPUX_LD 0
76 #define TARGET_ABI_OPEN_VMS 0
79 #define TARGET_ILP32 0
82 #ifndef HAVE_AS_LTOFFX_LDXMOV_RELOCS
83 #define HAVE_AS_LTOFFX_LDXMOV_RELOCS 0
86 /* Values for TARGET_INLINE_FLOAT_DIV, TARGET_INLINE_INT_DIV, and
87 TARGET_INLINE_SQRT. */
96 /* Default target_flags if no switches are specified */
98 #ifndef TARGET_DEFAULT
99 #define TARGET_DEFAULT (MASK_DWARF2_ASM)
102 #ifndef TARGET_CPU_DEFAULT
103 #define TARGET_CPU_DEFAULT 0
106 /* Driver configuration */
108 /* A C string constant that tells the GCC driver program options to pass to
109 `cc1'. It can also specify how to translate options you give to GCC into
110 options for GCC to pass to the `cc1'. */
113 #define CC1_SPEC "%{G*}"
115 /* A C string constant that tells the GCC driver program options to pass to
116 `cc1plus'. It can also specify how to translate options you give to GCC
117 into options for GCC to pass to the `cc1plus'. */
119 /* #define CC1PLUS_SPEC "" */
123 /* Define this macro to have the value 1 if the most significant bit in a byte
124 has the lowest number; otherwise define it to have the value zero. */
126 #define BITS_BIG_ENDIAN 0
128 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
130 /* Define this macro to have the value 1 if, in a multiword object, the most
131 significant word has the lowest number. */
133 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
135 #define UNITS_PER_WORD 8
137 #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64)
139 /* A C expression whose value is zero if pointers that need to be extended
140 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and one if
141 they are zero-extended and negative one if there is a ptr_extend operation.
143 You need not define this macro if the `POINTER_SIZE' is equal to the width
145 /* Need this for 32-bit pointers, see hpux.h for setting it. */
146 /* #define POINTERS_EXTEND_UNSIGNED */
148 /* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and
149 which has the specified mode and signedness is to be stored in a register.
150 This macro is only called when TYPE is a scalar type. */
151 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
154 if (GET_MODE_CLASS (MODE) == MODE_INT \
155 && GET_MODE_SIZE (MODE) < 4) \
160 #define PARM_BOUNDARY 64
162 /* Define this macro if you wish to preserve a certain alignment for the stack
163 pointer. The definition is a C expression for the desired alignment
164 (measured in bits). */
166 #define STACK_BOUNDARY 128
168 /* Align frames on double word boundaries */
169 #ifndef IA64_STACK_ALIGN
170 #define IA64_STACK_ALIGN(LOC) (((LOC) + 15) & ~15)
173 #define FUNCTION_BOUNDARY 128
175 /* Optional x86 80-bit float, quad-precision 128-bit float, and quad-word
176 128-bit integers all require 128-bit alignment. */
177 #define BIGGEST_ALIGNMENT 128
179 /* If defined, a C expression to compute the alignment for a static variable.
180 TYPE is the data type, and ALIGN is the alignment that the object
181 would ordinarily have. The value of this macro is used instead of that
182 alignment to align the object. */
184 #define DATA_ALIGNMENT(TYPE, ALIGN) \
185 (TREE_CODE (TYPE) == ARRAY_TYPE \
186 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
187 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
189 /* If defined, a C expression to compute the alignment given to a constant that
190 is being placed in memory. CONSTANT is the constant and ALIGN is the
191 alignment that the object would ordinarily have. The value of this macro is
192 used instead of that alignment to align the object. */
194 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
195 (TREE_CODE (EXP) == STRING_CST \
196 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
198 #define STRICT_ALIGNMENT 1
200 /* Define this if you wish to imitate the way many other C compilers handle
201 alignment of bitfields and the structures that contain them.
202 The behavior is that the type written for a bit-field (`int', `short', or
203 other integer type) imposes an alignment for the entire structure, as if the
204 structure really did contain an ordinary field of that type. In addition,
205 the bit-field is placed within the structure so that it would fit within such
206 a field, not crossing a boundary for it. */
207 #define PCC_BITFIELD_TYPE_MATTERS 1
209 /* An integer expression for the size in bits of the largest integer machine
210 mode that should actually be used. */
212 /* Allow pairs of registers to be used, which is the intent of the default. */
213 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
215 /* By default, the C++ compiler will use function addresses in the
216 vtable entries. Setting this nonzero tells the compiler to use
217 function descriptors instead. The value of this macro says how
218 many words wide the descriptor is (normally 2). It is assumed
219 that the address of a function descriptor may be treated as a
220 pointer to a function.
222 For reasons known only to HP, the vtable entries (as opposed to
223 normal function descriptors) are 16 bytes wide in 32-bit mode as
224 well, even though the 3rd and 4th words are unused. */
225 #define TARGET_VTABLE_USES_DESCRIPTORS (TARGET_ILP32 ? 4 : 2)
227 /* Due to silliness in the HPUX linker, vtable entries must be
228 8-byte aligned even in 32-bit mode. Rather than create multiple
229 ABIs, force this restriction on everyone else too. */
230 #define TARGET_VTABLE_ENTRY_ALIGN 64
232 /* Due to the above, we need extra padding for the data entries below 0
233 to retain the alignment of the descriptors. */
234 #define TARGET_VTABLE_DATA_ENTRY_DISTANCE (TARGET_ILP32 ? 2 : 1)
236 /* Layout of Source Language Data Types */
238 #define INT_TYPE_SIZE 32
240 #define SHORT_TYPE_SIZE 16
242 #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64)
244 #define LONG_LONG_TYPE_SIZE 64
246 #define FLOAT_TYPE_SIZE 32
248 #define DOUBLE_TYPE_SIZE 64
250 /* long double is XFmode normally, and TFmode for HPUX. It should be
251 TFmode for VMS as well but we only support up to DFmode now. */
252 #define LONG_DOUBLE_TYPE_SIZE \
254 : TARGET_ABI_OPEN_VMS ? 64 \
257 /* We always want the XFmode operations from libgcc2.c, except on VMS
258 where this yields references to unimplemented "insns". */
259 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE (TARGET_ABI_OPEN_VMS ? 64 : 80)
262 /* On HP-UX, we use the l suffix for TFmode in libgcc2.c. */
263 #define LIBGCC2_TF_CEXT l
265 #define DEFAULT_SIGNED_CHAR 1
267 /* A C expression for a string describing the name of the data type to use for
268 size values. The typedef name `size_t' is defined using the contents of the
270 /* ??? Needs to be defined for P64 code. */
271 /* #define SIZE_TYPE */
273 /* A C expression for a string describing the name of the data type to use for
274 the result of subtracting two pointers. The typedef name `ptrdiff_t' is
275 defined using the contents of the string. See `SIZE_TYPE' above for more
277 /* ??? Needs to be defined for P64 code. */
278 /* #define PTRDIFF_TYPE */
280 /* A C expression for a string describing the name of the data type to use for
281 wide characters. The typedef name `wchar_t' is defined using the contents
282 of the string. See `SIZE_TYPE' above for more information. */
283 /* #define WCHAR_TYPE */
285 /* A C expression for the size in bits of the data type for wide characters.
286 This is used in `cpp', which cannot make use of `WCHAR_TYPE'. */
287 /* #define WCHAR_TYPE_SIZE */
290 /* Register Basics */
292 /* Number of hardware registers known to the compiler.
293 We have 128 general registers, 128 floating point registers,
294 64 predicate registers, 8 branch registers, one frame pointer,
295 and several "application" registers. */
297 #define FIRST_PSEUDO_REGISTER 334
299 /* Ranges for the various kinds of registers. */
300 #define ADDL_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 3)
301 #define GR_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 127)
302 #define FR_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 255)
303 #define FP_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 254 && (REGNO) != 159)
304 #define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319)
305 #define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327)
306 #define GENERAL_REGNO_P(REGNO) \
307 (GR_REGNO_P (REGNO) || (REGNO) == FRAME_POINTER_REGNUM)
309 #define GR_REG(REGNO) ((REGNO) + 0)
310 #define FR_REG(REGNO) ((REGNO) + 128)
311 #define PR_REG(REGNO) ((REGNO) + 256)
312 #define BR_REG(REGNO) ((REGNO) + 320)
313 #define OUT_REG(REGNO) ((REGNO) + 120)
314 #define IN_REG(REGNO) ((REGNO) + 112)
315 #define LOC_REG(REGNO) ((REGNO) + 32)
317 #define AR_CCV_REGNUM 329
318 #define AR_UNAT_REGNUM 330
319 #define AR_PFS_REGNUM 331
320 #define AR_LC_REGNUM 332
321 #define AR_EC_REGNUM 333
323 #define IN_REGNO_P(REGNO) ((REGNO) >= IN_REG (0) && (REGNO) <= IN_REG (7))
324 #define LOC_REGNO_P(REGNO) ((REGNO) >= LOC_REG (0) && (REGNO) <= LOC_REG (79))
325 #define OUT_REGNO_P(REGNO) ((REGNO) >= OUT_REG (0) && (REGNO) <= OUT_REG (7))
327 #define AR_M_REGNO_P(REGNO) ((REGNO) == AR_CCV_REGNUM \
328 || (REGNO) == AR_UNAT_REGNUM)
329 #define AR_I_REGNO_P(REGNO) ((REGNO) >= AR_PFS_REGNUM \
330 && (REGNO) < FIRST_PSEUDO_REGISTER)
331 #define AR_REGNO_P(REGNO) ((REGNO) >= AR_CCV_REGNUM \
332 && (REGNO) < FIRST_PSEUDO_REGISTER)
335 /* ??? Don't really need two sets of macros. I like this one better because
336 it is less typing. */
337 #define R_GR(REGNO) GR_REG (REGNO)
338 #define R_FR(REGNO) FR_REG (REGNO)
339 #define R_PR(REGNO) PR_REG (REGNO)
340 #define R_BR(REGNO) BR_REG (REGNO)
342 /* An initializer that says which registers are used for fixed purposes all
343 throughout the compiled code and are therefore not available for general
347 r1: global pointer (gp)
348 r12: stack pointer (sp)
349 r13: thread pointer (tp)
353 fp: eliminable frame pointer */
355 /* The last 16 stacked regs are reserved for the 8 input and 8 output
358 #define FIXED_REGISTERS \
359 { /* General registers. */ \
360 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \
361 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
362 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
363 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
364 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
365 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
366 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
367 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
368 /* Floating-point registers. */ \
369 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
370 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
371 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
372 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
373 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
374 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
375 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
376 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
377 /* Predicate registers. */ \
378 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
379 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
380 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
381 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
382 /* Branch registers. */ \
383 0, 0, 0, 0, 0, 0, 0, 0, \
384 /*FP CCV UNAT PFS LC EC */ \
388 /* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered
389 (in general) by function calls as well as for fixed registers. This
390 macro therefore identifies the registers that are not available for
391 general allocation of values that must live across function calls. */
393 #define CALL_USED_REGISTERS \
394 { /* General registers. */ \
395 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
396 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
397 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
398 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
399 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
400 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
401 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
402 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
403 /* Floating-point registers. */ \
404 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
405 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
406 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
407 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
408 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
409 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
410 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
411 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
412 /* Predicate registers. */ \
413 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
414 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
415 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
416 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
417 /* Branch registers. */ \
418 1, 0, 0, 0, 0, 0, 1, 1, \
419 /*FP CCV UNAT PFS LC EC */ \
423 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
424 problem which makes CALL_USED_REGISTERS *always* include
425 all the FIXED_REGISTERS. Until this problem has been
426 resolved this macro can be used to overcome this situation.
427 In particular, block_propagate() requires this list
428 be accurate, or we can remove registers which should be live.
429 This macro is used in regs_invalidated_by_call. */
431 #define CALL_REALLY_USED_REGISTERS \
432 { /* General registers. */ \
433 0, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, \
434 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
435 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
436 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
437 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
438 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
439 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
440 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
441 /* Floating-point registers. */ \
442 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
443 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
444 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
445 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
446 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
447 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
448 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
449 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
450 /* Predicate registers. */ \
451 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
452 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
453 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
454 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
455 /* Branch registers. */ \
456 1, 0, 0, 0, 0, 0, 1, 1, \
457 /*FP CCV UNAT PFS LC EC */ \
462 /* Define this macro if the target machine has register windows. This C
463 expression returns the register number as seen by the called function
464 corresponding to the register number OUT as seen by the calling function.
465 Return OUT if register number OUT is not an outbound register. */
467 #define INCOMING_REGNO(OUT) \
468 ((unsigned) ((OUT) - OUT_REG (0)) < 8 ? IN_REG ((OUT) - OUT_REG (0)) : (OUT))
470 /* Define this macro if the target machine has register windows. This C
471 expression returns the register number as seen by the calling function
472 corresponding to the register number IN as seen by the called function.
473 Return IN if register number IN is not an inbound register. */
475 #define OUTGOING_REGNO(IN) \
476 ((unsigned) ((IN) - IN_REG (0)) < 8 ? OUT_REG ((IN) - IN_REG (0)) : (IN))
478 /* Define this macro if the target machine has register windows. This
479 C expression returns true if the register is call-saved but is in the
482 #define LOCAL_REGNO(REGNO) \
483 (IN_REGNO_P (REGNO) || LOC_REGNO_P (REGNO))
485 /* We define CCImode in ia64-modes.def so we need a selector. */
487 #define SELECT_CC_MODE(OP,X,Y) CCmode
489 /* Order of allocation of registers */
491 /* If defined, an initializer for a vector of integers, containing the numbers
492 of hard registers in the order in which GCC should prefer to use them
493 (from most preferred to least).
495 If this macro is not defined, registers are used lowest numbered first (all
498 One use of this macro is on machines where the highest numbered registers
499 must always be saved and the save-multiple-registers instruction supports
500 only sequences of consecutive registers. On such machines, define
501 `REG_ALLOC_ORDER' to be an initializer that lists the highest numbered
502 allocatable register first. */
504 /* ??? Should the GR return value registers come before or after the rest
505 of the caller-save GRs? */
507 #define REG_ALLOC_ORDER \
509 /* Caller-saved general registers. */ \
510 R_GR (14), R_GR (15), R_GR (16), R_GR (17), \
511 R_GR (18), R_GR (19), R_GR (20), R_GR (21), R_GR (22), R_GR (23), \
512 R_GR (24), R_GR (25), R_GR (26), R_GR (27), R_GR (28), R_GR (29), \
513 R_GR (30), R_GR (31), \
514 /* Output registers. */ \
515 R_GR (120), R_GR (121), R_GR (122), R_GR (123), R_GR (124), R_GR (125), \
516 R_GR (126), R_GR (127), \
517 /* Caller-saved general registers, also used for return values. */ \
518 R_GR (8), R_GR (9), R_GR (10), R_GR (11), \
519 /* addl caller-saved general registers. */ \
520 R_GR (2), R_GR (3), \
521 /* Caller-saved FP registers. */ \
522 R_FR (6), R_FR (7), \
523 /* Caller-saved FP registers, used for parameters and return values. */ \
524 R_FR (8), R_FR (9), R_FR (10), R_FR (11), \
525 R_FR (12), R_FR (13), R_FR (14), R_FR (15), \
526 /* Rotating caller-saved FP registers. */ \
527 R_FR (32), R_FR (33), R_FR (34), R_FR (35), \
528 R_FR (36), R_FR (37), R_FR (38), R_FR (39), R_FR (40), R_FR (41), \
529 R_FR (42), R_FR (43), R_FR (44), R_FR (45), R_FR (46), R_FR (47), \
530 R_FR (48), R_FR (49), R_FR (50), R_FR (51), R_FR (52), R_FR (53), \
531 R_FR (54), R_FR (55), R_FR (56), R_FR (57), R_FR (58), R_FR (59), \
532 R_FR (60), R_FR (61), R_FR (62), R_FR (63), R_FR (64), R_FR (65), \
533 R_FR (66), R_FR (67), R_FR (68), R_FR (69), R_FR (70), R_FR (71), \
534 R_FR (72), R_FR (73), R_FR (74), R_FR (75), R_FR (76), R_FR (77), \
535 R_FR (78), R_FR (79), R_FR (80), R_FR (81), R_FR (82), R_FR (83), \
536 R_FR (84), R_FR (85), R_FR (86), R_FR (87), R_FR (88), R_FR (89), \
537 R_FR (90), R_FR (91), R_FR (92), R_FR (93), R_FR (94), R_FR (95), \
538 R_FR (96), R_FR (97), R_FR (98), R_FR (99), R_FR (100), R_FR (101), \
539 R_FR (102), R_FR (103), R_FR (104), R_FR (105), R_FR (106), R_FR (107), \
540 R_FR (108), R_FR (109), R_FR (110), R_FR (111), R_FR (112), R_FR (113), \
541 R_FR (114), R_FR (115), R_FR (116), R_FR (117), R_FR (118), R_FR (119), \
542 R_FR (120), R_FR (121), R_FR (122), R_FR (123), R_FR (124), R_FR (125), \
543 R_FR (126), R_FR (127), \
544 /* Caller-saved predicate registers. */ \
545 R_PR (6), R_PR (7), R_PR (8), R_PR (9), R_PR (10), R_PR (11), \
546 R_PR (12), R_PR (13), R_PR (14), R_PR (15), \
547 /* Rotating caller-saved predicate registers. */ \
548 R_PR (16), R_PR (17), \
549 R_PR (18), R_PR (19), R_PR (20), R_PR (21), R_PR (22), R_PR (23), \
550 R_PR (24), R_PR (25), R_PR (26), R_PR (27), R_PR (28), R_PR (29), \
551 R_PR (30), R_PR (31), R_PR (32), R_PR (33), R_PR (34), R_PR (35), \
552 R_PR (36), R_PR (37), R_PR (38), R_PR (39), R_PR (40), R_PR (41), \
553 R_PR (42), R_PR (43), R_PR (44), R_PR (45), R_PR (46), R_PR (47), \
554 R_PR (48), R_PR (49), R_PR (50), R_PR (51), R_PR (52), R_PR (53), \
555 R_PR (54), R_PR (55), R_PR (56), R_PR (57), R_PR (58), R_PR (59), \
556 R_PR (60), R_PR (61), R_PR (62), R_PR (63), \
557 /* Caller-saved branch registers. */ \
558 R_BR (6), R_BR (7), \
560 /* Stacked callee-saved general registers. */ \
561 R_GR (32), R_GR (33), R_GR (34), R_GR (35), \
562 R_GR (36), R_GR (37), R_GR (38), R_GR (39), R_GR (40), R_GR (41), \
563 R_GR (42), R_GR (43), R_GR (44), R_GR (45), R_GR (46), R_GR (47), \
564 R_GR (48), R_GR (49), R_GR (50), R_GR (51), R_GR (52), R_GR (53), \
565 R_GR (54), R_GR (55), R_GR (56), R_GR (57), R_GR (58), R_GR (59), \
566 R_GR (60), R_GR (61), R_GR (62), R_GR (63), R_GR (64), R_GR (65), \
567 R_GR (66), R_GR (67), R_GR (68), R_GR (69), R_GR (70), R_GR (71), \
568 R_GR (72), R_GR (73), R_GR (74), R_GR (75), R_GR (76), R_GR (77), \
569 R_GR (78), R_GR (79), R_GR (80), R_GR (81), R_GR (82), R_GR (83), \
570 R_GR (84), R_GR (85), R_GR (86), R_GR (87), R_GR (88), R_GR (89), \
571 R_GR (90), R_GR (91), R_GR (92), R_GR (93), R_GR (94), R_GR (95), \
572 R_GR (96), R_GR (97), R_GR (98), R_GR (99), R_GR (100), R_GR (101), \
573 R_GR (102), R_GR (103), R_GR (104), R_GR (105), R_GR (106), R_GR (107), \
575 /* Input registers. */ \
576 R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (116), R_GR (117), \
577 R_GR (118), R_GR (119), \
578 /* Callee-saved general registers. */ \
579 R_GR (4), R_GR (5), R_GR (6), R_GR (7), \
580 /* Callee-saved FP registers. */ \
581 R_FR (2), R_FR (3), R_FR (4), R_FR (5), R_FR (16), R_FR (17), \
582 R_FR (18), R_FR (19), R_FR (20), R_FR (21), R_FR (22), R_FR (23), \
583 R_FR (24), R_FR (25), R_FR (26), R_FR (27), R_FR (28), R_FR (29), \
584 R_FR (30), R_FR (31), \
585 /* Callee-saved predicate registers. */ \
586 R_PR (1), R_PR (2), R_PR (3), R_PR (4), R_PR (5), \
587 /* Callee-saved branch registers. */ \
588 R_BR (1), R_BR (2), R_BR (3), R_BR (4), R_BR (5), \
590 /* ??? Stacked registers reserved for fp, rp, and ar.pfs. */ \
591 R_GR (109), R_GR (110), R_GR (111), \
593 /* Special general registers. */ \
594 R_GR (0), R_GR (1), R_GR (12), R_GR (13), \
595 /* Special FP registers. */ \
596 R_FR (0), R_FR (1), \
597 /* Special predicate registers. */ \
599 /* Special branch registers. */ \
601 /* Other fixed registers. */ \
602 FRAME_POINTER_REGNUM, \
603 AR_CCV_REGNUM, AR_UNAT_REGNUM, AR_PFS_REGNUM, AR_LC_REGNUM, \
607 /* How Values Fit in Registers */
609 /* A C expression for the number of consecutive hard registers, starting at
610 register number REGNO, required to hold a value of mode MODE. */
612 /* ??? We say that BImode PR values require two registers. This allows us to
613 easily store the normal and inverted values. We use CCImode to indicate
614 a single predicate register. */
616 #define HARD_REGNO_NREGS(REGNO, MODE) \
617 ((REGNO) == PR_REG (0) && (MODE) == DImode ? 64 \
618 : PR_REGNO_P (REGNO) && (MODE) == BImode ? 2 \
619 : (PR_REGNO_P (REGNO) || GR_REGNO_P (REGNO)) && (MODE) == CCImode ? 1\
620 : FR_REGNO_P (REGNO) && (MODE) == XFmode ? 1 \
621 : FR_REGNO_P (REGNO) && (MODE) == RFmode ? 1 \
622 : FR_REGNO_P (REGNO) && (MODE) == XCmode ? 2 \
623 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
625 /* A C expression that is nonzero if it is permissible to store a value of mode
626 MODE in hard register number REGNO (or in several registers starting with
629 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
630 (FR_REGNO_P (REGNO) ? \
631 GET_MODE_CLASS (MODE) != MODE_CC && \
632 (MODE) != BImode && \
634 : PR_REGNO_P (REGNO) ? \
635 (MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \
636 : GR_REGNO_P (REGNO) ? \
637 (MODE) != XFmode && (MODE) != XCmode && (MODE) != RFmode \
638 : AR_REGNO_P (REGNO) ? (MODE) == DImode \
639 : BR_REGNO_P (REGNO) ? (MODE) == DImode \
642 /* A C expression that is nonzero if it is desirable to choose register
643 allocation so as to avoid move instructions between a value of mode MODE1
644 and a value of mode MODE2.
646 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
647 ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
649 /* Don't tie integer and FP modes, as that causes us to get integer registers
650 allocated for FP instructions. XFmode only supported in FP registers so
651 we can't tie it with any other modes. */
652 #define MODES_TIEABLE_P(MODE1, MODE2) \
653 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
654 && ((((MODE1) == XFmode) || ((MODE1) == XCmode) || ((MODE1) == RFmode)) \
655 == (((MODE2) == XFmode) || ((MODE2) == XCmode) || ((MODE2) == RFmode))) \
656 && (((MODE1) == BImode) == ((MODE2) == BImode)))
658 /* Specify the modes required to caller save a given hard regno.
659 We need to ensure floating pt regs are not saved as DImode. */
661 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
662 ((FR_REGNO_P (REGNO) && (NREGS) == 1) ? RFmode \
663 : choose_hard_reg_mode ((REGNO), (NREGS), false))
665 /* Handling Leaf Functions */
667 /* A C initializer for a vector, indexed by hard register number, which
668 contains 1 for a register that is allowable in a candidate for leaf function
670 /* ??? This might be useful. */
671 /* #define LEAF_REGISTERS */
673 /* A C expression whose value is the register number to which REGNO should be
674 renumbered, when a function is treated as a leaf function. */
675 /* ??? This might be useful. */
676 /* #define LEAF_REG_REMAP(REGNO) */
679 /* Register Classes */
681 /* An enumeral type that must be defined with all the register class names as
682 enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last
683 register class, followed by one more enumeral value, `LIM_REG_CLASSES',
684 which is not a register class but rather tells how many classes there
686 /* ??? When compiling without optimization, it is possible for the only use of
687 a pseudo to be a parameter load from the stack with a REG_EQUIV note.
688 Regclass handles this case specially and does not assign any costs to the
689 pseudo. The pseudo then ends up using the last class before ALL_REGS.
690 Thus we must not let either PR_REGS or BR_REGS be the last class. The
691 testcase for this is gcc.c-torture/execute/va-arg-7.c. */
709 #define GENERAL_REGS GR_REGS
711 /* The number of distinct register classes. */
712 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
714 /* An initializer containing the names of the register classes as C string
715 constants. These names are used in writing some of the debugging dumps. */
716 #define REG_CLASS_NAMES \
717 { "NO_REGS", "PR_REGS", "BR_REGS", "AR_M_REGS", "AR_I_REGS", \
718 "ADDL_REGS", "GR_REGS", "FP_REGS", "FR_REGS", \
719 "GR_AND_BR_REGS", "GR_AND_FR_REGS", "ALL_REGS" }
721 /* An initializer containing the contents of the register classes, as integers
722 which are bit masks. The Nth integer specifies the contents of class N.
723 The way the integer MASK is interpreted is that register R is in the class
724 if `MASK & (1 << R)' is 1. */
725 #define REG_CLASS_CONTENTS \
728 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
729 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
730 0x00000000, 0x00000000, 0x0000 }, \
732 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
733 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
734 0xFFFFFFFF, 0xFFFFFFFF, 0x0000 }, \
736 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
737 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
738 0x00000000, 0x00000000, 0x00FF }, \
740 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
741 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
742 0x00000000, 0x00000000, 0x0600 }, \
744 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
745 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
746 0x00000000, 0x00000000, 0x3800 }, \
748 { 0x0000000F, 0x00000000, 0x00000000, 0x00000000, \
749 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
750 0x00000000, 0x00000000, 0x0000 }, \
752 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
753 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
754 0x00000000, 0x00000000, 0x0100 }, \
756 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
757 0x7FFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF, \
758 0x00000000, 0x00000000, 0x0000 }, \
760 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
761 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
762 0x00000000, 0x00000000, 0x0000 }, \
763 /* GR_AND_BR_REGS. */ \
764 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
765 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
766 0x00000000, 0x00000000, 0x01FF }, \
767 /* GR_AND_FR_REGS. */ \
768 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
769 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
770 0x00000000, 0x00000000, 0x0100 }, \
772 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
773 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
774 0xFFFFFFFF, 0xFFFFFFFF, 0x3FFF }, \
777 /* The following macro defines cover classes for Integrated Register
778 Allocator. Cover classes is a set of non-intersected register
779 classes covering all hard registers used for register allocation
780 purpose. Any move between two registers of a cover class should be
781 cheaper than load or store of the registers. The macro value is
782 array of register classes with LIM_REG_CLASSES used as the end
785 #define IRA_COVER_CLASSES \
787 PR_REGS, BR_REGS, AR_M_REGS, AR_I_REGS, GR_REGS, FR_REGS, LIM_REG_CLASSES \
790 /* A C expression whose value is a register class containing hard register
791 REGNO. In general there is more than one such class; choose a class which
792 is "minimal", meaning that no smaller class also contains the register. */
793 /* The NO_REGS case is primarily for the benefit of rws_access_reg, which
794 may call here with private (invalid) register numbers, such as
796 #define REGNO_REG_CLASS(REGNO) \
797 (ADDL_REGNO_P (REGNO) ? ADDL_REGS \
798 : GENERAL_REGNO_P (REGNO) ? GR_REGS \
799 : FR_REGNO_P (REGNO) ? (REGNO) != R_FR (31) \
800 && (REGNO) != R_FR(127) ? FP_REGS : FR_REGS \
801 : PR_REGNO_P (REGNO) ? PR_REGS \
802 : BR_REGNO_P (REGNO) ? BR_REGS \
803 : AR_M_REGNO_P (REGNO) ? AR_M_REGS \
804 : AR_I_REGNO_P (REGNO) ? AR_I_REGS \
807 /* A macro whose definition is the name of the class to which a valid base
808 register must belong. A base register is one used in an address which is
809 the register value plus a displacement. */
810 #define BASE_REG_CLASS GENERAL_REGS
812 /* A macro whose definition is the name of the class to which a valid index
813 register must belong. An index register is one used in an address where its
814 value is either multiplied by a scale factor or added to another register
815 (as well as added to a displacement). This is needed for POST_MODIFY. */
816 #define INDEX_REG_CLASS GENERAL_REGS
818 /* A C expression which is nonzero if register number NUM is suitable for use
819 as a base register in operand addresses. It may be either a suitable hard
820 register or a pseudo register that has been allocated such a hard reg. */
821 #define REGNO_OK_FOR_BASE_P(REGNO) \
822 (GENERAL_REGNO_P (REGNO) || GENERAL_REGNO_P (reg_renumber[REGNO]))
824 /* A C expression which is nonzero if register number NUM is suitable for use
825 as an index register in operand addresses. It may be either a suitable hard
826 register or a pseudo register that has been allocated such a hard reg.
827 This is needed for POST_MODIFY. */
828 #define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM)
830 /* You should define this macro to indicate to the reload phase that it may
831 need to allocate at least one register for a reload in addition to the
832 register to contain the data. Specifically, if copying X to a register
833 CLASS in MODE requires an intermediate register, you should define this
834 to return the largest register class all of whose registers can be used
835 as intermediate registers or scratch registers. */
837 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
838 ia64_secondary_reload_class (CLASS, MODE, X)
840 /* Certain machines have the property that some registers cannot be copied to
841 some other registers without using memory. Define this macro on those
842 machines to be a C expression that is nonzero if objects of mode M in
843 registers of CLASS1 can only be copied to registers of class CLASS2 by
844 storing a register of CLASS1 into memory and loading that memory location
845 into a register of CLASS2. */
848 /* ??? May need this, but since we've disallowed XFmode in GR_REGS,
849 I'm not quite sure how it could be invoked. The normal problems
850 with unions should be solved with the addressof fiddling done by
851 movxf and friends. */
852 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
853 (((MODE) == XFmode || (MODE) == XCmode) \
854 && (((CLASS1) == GR_REGS && (CLASS2) == FR_REGS) \
855 || ((CLASS1) == FR_REGS && (CLASS2) == GR_REGS)))
858 /* A C expression for the maximum number of consecutive registers of
859 class CLASS needed to hold a value of mode MODE.
860 This is closely related to the macro `HARD_REGNO_NREGS'. */
862 #define CLASS_MAX_NREGS(CLASS, MODE) \
863 ((MODE) == BImode && (CLASS) == PR_REGS ? 2 \
864 : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == XFmode) ? 1 \
865 : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == RFmode) ? 1 \
866 : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == XCmode) ? 2 \
867 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
869 /* In BR regs, we can't change the DImode at all.
870 In FP regs, we can't change FP values to integer values and vice versa,
871 but we can change e.g. DImode to SImode, and V2SFmode into DImode. */
873 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
874 (reg_classes_intersect_p (CLASS, BR_REGS) \
876 : (SCALAR_FLOAT_MODE_P (FROM) != SCALAR_FLOAT_MODE_P (TO) \
877 ? reg_classes_intersect_p (CLASS, FR_REGS) \
880 /* Basic Stack Layout */
882 /* Define this macro if pushing a word onto the stack moves the stack pointer
883 to a smaller address. */
884 #define STACK_GROWS_DOWNWARD 1
886 /* Define this macro to nonzero if the addresses of local variable slots
887 are at negative offsets from the frame pointer. */
888 #define FRAME_GROWS_DOWNWARD 0
890 /* Offset from the frame pointer to the first local variable slot to
892 #define STARTING_FRAME_OFFSET 0
894 /* Offset from the stack pointer register to the first location at which
895 outgoing arguments are placed. If not specified, the default value of zero
896 is used. This is the proper value for most machines. */
897 /* IA64 has a 16 byte scratch area that is at the bottom of the stack. */
898 #define STACK_POINTER_OFFSET 16
900 /* Offset from the argument pointer register to the first argument's address.
901 On some machines it may depend on the data type of the function. */
902 #define FIRST_PARM_OFFSET(FUNDECL) 0
904 /* A C expression whose value is RTL representing the value of the return
905 address for the frame COUNT steps up from the current frame, after the
908 /* ??? Frames other than zero would likely require interpreting the frame
909 unwind info, so we don't try to support them. We would also need to define
910 DYNAMIC_CHAIN_ADDRESS and SETUP_FRAME_ADDRESS (for the reg stack flush). */
912 #define RETURN_ADDR_RTX(COUNT, FRAME) \
913 ia64_return_addr_rtx (COUNT, FRAME)
915 /* A C expression whose value is RTL representing the location of the incoming
916 return address at the beginning of any function, before the prologue. This
917 RTL is either a `REG', indicating that the return value is saved in `REG',
918 or a `MEM' representing a location in the stack. This enables DWARF2
919 unwind info for C++ EH. */
920 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, BR_REG (0))
922 /* A C expression whose value is an integer giving the offset, in bytes, from
923 the value of the stack pointer register to the top of the stack frame at the
924 beginning of any function, before the prologue. The top of the frame is
925 defined to be the value of the stack pointer in the previous frame, just
926 before the call instruction. */
927 /* The CFA is past the red zone, not at the entry-point stack
929 #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET
931 /* We shorten debug info by using CFA-16 as DW_AT_frame_base. */
932 #define CFA_FRAME_BASE_OFFSET(FUNDECL) (-INCOMING_FRAME_SP_OFFSET)
935 /* Register That Address the Stack Frame. */
937 /* The register number of the stack pointer register, which must also be a
938 fixed register according to `FIXED_REGISTERS'. On most machines, the
939 hardware determines which register this is. */
941 #define STACK_POINTER_REGNUM 12
943 /* The register number of the frame pointer register, which is used to access
944 automatic variables in the stack frame. On some machines, the hardware
945 determines which register this is. On other machines, you can choose any
946 register you wish for this purpose. */
948 #define FRAME_POINTER_REGNUM 328
950 /* Base register for access to local variables of the function. */
951 #define HARD_FRAME_POINTER_REGNUM LOC_REG (79)
953 /* The register number of the arg pointer register, which is used to access the
954 function's argument list. */
955 /* r0 won't otherwise be used, so put the always eliminated argument pointer
957 #define ARG_POINTER_REGNUM R_GR(0)
959 /* Due to the way varargs and argument spilling happens, the argument
960 pointer is not 16-byte aligned like the stack pointer. */
961 #define INIT_EXPANDERS \
963 ia64_init_expanders (); \
964 if (crtl->emit.regno_pointer_align) \
965 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = 64; \
968 /* Register numbers used for passing a function's static chain pointer. */
969 /* ??? The ABI sez the static chain should be passed as a normal parameter. */
970 #define STATIC_CHAIN_REGNUM 15
972 /* Eliminating the Frame Pointer and the Arg Pointer */
974 /* If defined, this macro specifies a table of register pairs used to eliminate
975 unneeded registers that point into the stack frame. */
977 #define ELIMINABLE_REGS \
979 {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
980 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
981 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
982 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
985 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
986 specifies the initial difference between the specified pair of
987 registers. This macro must be defined if `ELIMINABLE_REGS' is
989 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
990 ((OFFSET) = ia64_initial_elimination_offset ((FROM), (TO)))
992 /* Passing Function Arguments on the Stack */
994 /* If defined, the maximum amount of space required for outgoing arguments will
995 be computed and placed into the variable
996 `crtl->outgoing_args_size'. */
998 #define ACCUMULATE_OUTGOING_ARGS 1
1001 /* Function Arguments in Registers */
1003 #define MAX_ARGUMENT_SLOTS 8
1004 #define MAX_INT_RETURN_SLOTS 4
1005 #define GR_ARG_FIRST IN_REG (0)
1006 #define GR_RET_FIRST GR_REG (8)
1007 #define GR_RET_LAST GR_REG (11)
1008 #define FR_ARG_FIRST FR_REG (8)
1009 #define FR_RET_FIRST FR_REG (8)
1010 #define FR_RET_LAST FR_REG (15)
1011 #define AR_ARG_FIRST OUT_REG (0)
1013 /* A C type for declaring a variable that is used as the first argument of
1014 `FUNCTION_ARG' and other related values. For some target machines, the type
1015 `int' suffices and can hold the number of bytes of argument so far. */
1017 enum ivms_arg_type {I64, FF, FD, FG, FS, FT};
1018 /* VMS floating point formats VAX F, VAX D, VAX G, IEEE S, IEEE T. */
1020 typedef struct ia64_args
1022 int words; /* # words of arguments so far */
1023 int int_regs; /* # GR registers used so far */
1024 int fp_regs; /* # FR registers used so far */
1025 int prototype; /* whether function prototyped */
1026 enum ivms_arg_type atypes[8]; /* which VMS float type or if not float */
1029 /* A C statement (sans semicolon) for initializing the variable CUM for the
1030 state at the beginning of the argument list. */
1032 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1035 (CUM).int_regs = 0; \
1036 (CUM).fp_regs = 0; \
1037 (CUM).prototype = ((FNTYPE) && prototype_p (FNTYPE)) || (LIBNAME); \
1038 (CUM).atypes[0] = (CUM).atypes[1] = (CUM).atypes[2] = I64; \
1039 (CUM).atypes[3] = (CUM).atypes[4] = (CUM).atypes[5] = I64; \
1040 (CUM).atypes[6] = (CUM).atypes[7] = I64; \
1043 /* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of finding the
1044 arguments for the function being compiled. If this macro is undefined,
1045 `INIT_CUMULATIVE_ARGS' is used instead. */
1047 /* We set prototype to true so that we never try to return a PARALLEL from
1049 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1052 (CUM).int_regs = 0; \
1053 (CUM).fp_regs = 0; \
1054 (CUM).prototype = 1; \
1055 (CUM).atypes[0] = (CUM).atypes[1] = (CUM).atypes[2] = I64; \
1056 (CUM).atypes[3] = (CUM).atypes[4] = (CUM).atypes[5] = I64; \
1057 (CUM).atypes[6] = (CUM).atypes[7] = I64; \
1060 /* A C expression that is nonzero if REGNO is the number of a hard register in
1061 which function arguments are sometimes passed. This does *not* include
1062 implicit arguments such as the static chain and the structure-value address.
1063 On many machines, no registers can be used for this purpose since all
1064 function arguments are pushed on the stack. */
1065 #define FUNCTION_ARG_REGNO_P(REGNO) \
1066 (((REGNO) >= AR_ARG_FIRST && (REGNO) < (AR_ARG_FIRST + MAX_ARGUMENT_SLOTS)) \
1067 || ((REGNO) >= FR_ARG_FIRST && (REGNO) < (FR_ARG_FIRST + MAX_ARGUMENT_SLOTS)))
1070 /* How Large Values are Returned */
1072 #define DEFAULT_PCC_STRUCT_RETURN 0
1075 /* Caller-Saves Register Allocation */
1077 /* A C expression to determine whether it is worthwhile to consider placing a
1078 pseudo-register in a call-clobbered hard register and saving and restoring
1079 it around each function call. The expression should be 1 when this is worth
1080 doing, and 0 otherwise.
1082 If you don't define this macro, a default is used which is good on most
1083 machines: `4 * CALLS < REFS'. */
1084 /* ??? Investigate. */
1085 /* #define CALLER_SAVE_PROFITABLE(REFS, CALLS) */
1088 /* Function Entry and Exit */
1090 /* Define this macro as a C expression that is nonzero if the return
1091 instruction or the function epilogue ignores the value of the stack pointer;
1092 in other words, if it is safe to delete an instruction to adjust the stack
1093 pointer before a return from the function. */
1095 #define EXIT_IGNORE_STACK 1
1097 /* Define this macro as a C expression that is nonzero for registers
1098 used by the epilogue or the `return' pattern. */
1100 #define EPILOGUE_USES(REGNO) ia64_epilogue_uses (REGNO)
1102 /* Nonzero for registers used by the exception handling mechanism. */
1104 #define EH_USES(REGNO) ia64_eh_uses (REGNO)
1106 /* Output part N of a function descriptor for DECL. For ia64, both
1107 words are emitted with a single relocation, so ignore N > 0. */
1108 #define ASM_OUTPUT_FDESC(FILE, DECL, PART) \
1113 fputs ("\tdata8.ua @iplt(", FILE); \
1115 fputs ("\tdata16.ua @iplt(", FILE); \
1116 mark_decl_referenced (DECL); \
1117 assemble_name (FILE, XSTR (XEXP (DECL_RTL (DECL), 0), 0)); \
1118 fputs (")\n", FILE); \
1120 fputs ("\tdata8.ua 0\n", FILE); \
1124 /* Generating Code for Profiling. */
1126 /* A C statement or compound statement to output to FILE some assembler code to
1127 call the profiling subroutine `mcount'. */
1129 #undef FUNCTION_PROFILER
1130 #define FUNCTION_PROFILER(FILE, LABELNO) \
1131 ia64_output_function_profiler(FILE, LABELNO)
1133 /* Neither hpux nor linux use profile counters. */
1134 #define NO_PROFILE_COUNTERS 1
1136 /* Trampolines for Nested Functions. */
1138 /* We need 32 bytes, so we can save the sp, ar.rnat, ar.bsp, and ar.pfs of
1139 the function containing a non-local goto target. */
1141 #define STACK_SAVEAREA_MODE(LEVEL) \
1142 ((LEVEL) == SAVE_NONLOCAL ? OImode : Pmode)
1144 /* A C expression for the size in bytes of the trampoline, as an integer. */
1146 #define TRAMPOLINE_SIZE 32
1148 /* Alignment required for trampolines, in bits. */
1150 #define TRAMPOLINE_ALIGNMENT 64
1152 /* Addressing Modes */
1154 /* Define this macro if the machine supports post-increment addressing. */
1156 #define HAVE_POST_INCREMENT 1
1157 #define HAVE_POST_DECREMENT 1
1158 #define HAVE_POST_MODIFY_DISP 1
1159 #define HAVE_POST_MODIFY_REG 1
1161 /* A C expression that is 1 if the RTX X is a constant which is a valid
1164 #define CONSTANT_ADDRESS_P(X) 0
1166 /* The max number of registers that can appear in a valid memory address. */
1168 #define MAX_REGS_PER_ADDRESS 2
1170 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
1171 RTX) is a legitimate memory address on the target machine for a memory
1172 operand of mode MODE. */
1174 #define LEGITIMATE_ADDRESS_REG(X) \
1175 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1176 || (GET_CODE (X) == SUBREG && GET_CODE (XEXP (X, 0)) == REG \
1177 && REG_OK_FOR_BASE_P (XEXP (X, 0))))
1179 #define LEGITIMATE_ADDRESS_DISP(R, X) \
1180 (GET_CODE (X) == PLUS \
1181 && rtx_equal_p (R, XEXP (X, 0)) \
1182 && (LEGITIMATE_ADDRESS_REG (XEXP (X, 1)) \
1183 || (GET_CODE (XEXP (X, 1)) == CONST_INT \
1184 && INTVAL (XEXP (X, 1)) >= -256 \
1185 && INTVAL (XEXP (X, 1)) < 256)))
1187 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1189 if (LEGITIMATE_ADDRESS_REG (X)) \
1191 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
1192 && LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \
1193 && XEXP (X, 0) != arg_pointer_rtx) \
1195 else if (GET_CODE (X) == POST_MODIFY \
1196 && LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \
1197 && XEXP (X, 0) != arg_pointer_rtx \
1198 && LEGITIMATE_ADDRESS_DISP (XEXP (X, 0), XEXP (X, 1))) \
1202 /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
1203 use as a base register. */
1205 #ifdef REG_OK_STRICT
1206 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1208 #define REG_OK_FOR_BASE_P(X) \
1209 (GENERAL_REGNO_P (REGNO (X)) || (REGNO (X) >= FIRST_PSEUDO_REGISTER))
1212 /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
1213 use as an index register. This is needed for POST_MODIFY. */
1215 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1217 /* A C expression that is nonzero if X is a legitimate constant for an
1218 immediate operand on the target machine. */
1220 #define LEGITIMATE_CONSTANT_P(X) ia64_legitimate_constant_p (X)
1222 /* Condition Code Status */
1224 /* One some machines not all possible comparisons are defined, but you can
1225 convert an invalid comparison into a valid one. */
1226 /* ??? Investigate. See the alpha definition. */
1227 /* #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) */
1230 /* Describing Relative Costs of Operations */
1232 /* A C expression for the cost of a branch instruction. A value of 1 is the
1233 default; other values are interpreted relative to that. Used by the
1234 if-conversion code as max instruction count. */
1235 /* ??? This requires investigation. The primary effect might be how
1236 many additional insn groups we run into, vs how good the dynamic
1237 branch predictor is. */
1239 #define BRANCH_COST(speed_p, predictable_p) 6
1241 /* Define this macro as a C expression which is nonzero if accessing less than
1242 a word of memory (i.e. a `char' or a `short') is no faster than accessing a
1245 #define SLOW_BYTE_ACCESS 1
1247 /* Define this macro if it is as good or better to call a constant function
1248 address than to call an address kept in a register.
1250 Indirect function calls are more expensive that direct function calls, so
1251 don't cse function addresses. */
1253 #define NO_FUNCTION_CSE
1256 /* Dividing the output into sections. */
1258 /* A C expression whose value is a string containing the assembler operation
1259 that should precede instructions and read-only data. */
1261 #define TEXT_SECTION_ASM_OP "\t.text"
1263 /* A C expression whose value is a string containing the assembler operation to
1264 identify the following data as writable initialized data. */
1266 #define DATA_SECTION_ASM_OP "\t.data"
1268 /* If defined, a C expression whose value is a string containing the assembler
1269 operation to identify the following data as uninitialized global data. */
1271 #define BSS_SECTION_ASM_OP "\t.bss"
1273 #define IA64_DEFAULT_GVALUE 8
1275 /* Position Independent Code. */
1277 /* The register number of the register used to address a table of static data
1278 addresses in memory. */
1280 /* ??? Should modify ia64.md to use pic_offset_table_rtx instead of
1281 gen_rtx_REG (DImode, 1). */
1283 /* ??? Should we set flag_pic? Probably need to define
1284 LEGITIMIZE_PIC_OPERAND_P to make that work. */
1286 #define PIC_OFFSET_TABLE_REGNUM GR_REG (1)
1288 /* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' is
1289 clobbered by calls. */
1291 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 1
1294 /* The Overall Framework of an Assembler File. */
1296 /* A C string constant describing how to begin a comment in the target
1297 assembler language. The compiler assumes that the comment will end at the
1300 #define ASM_COMMENT_START "//"
1302 /* A C string constant for text to be output before each `asm' statement or
1303 group of consecutive ones. */
1305 #define ASM_APP_ON (TARGET_GNU_AS ? "#APP\n" : "//APP\n")
1307 /* A C string constant for text to be output after each `asm' statement or
1308 group of consecutive ones. */
1310 #define ASM_APP_OFF (TARGET_GNU_AS ? "#NO_APP\n" : "//NO_APP\n")
1312 /* Output and Generation of Labels. */
1314 /* A C statement (sans semicolon) to output to the stdio stream STREAM the
1315 assembler definition of a label named NAME. */
1317 /* See the ASM_OUTPUT_LABELREF definition in sysv4.h for an explanation of
1318 why ia64_asm_output_label exists. */
1320 extern int ia64_asm_output_label;
1321 #define ASM_OUTPUT_LABEL(STREAM, NAME) \
1323 ia64_asm_output_label = 1; \
1324 assemble_name (STREAM, NAME); \
1325 fputs (":\n", STREAM); \
1326 ia64_asm_output_label = 0; \
1329 /* Globalizing directive for a label. */
1330 #define GLOBAL_ASM_OP "\t.global "
1332 /* A C statement (sans semicolon) to output to the stdio stream STREAM any text
1333 necessary for declaring the name of an external symbol named NAME which is
1334 referenced in this compilation but not defined. */
1336 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
1337 ia64_asm_output_external (FILE, DECL, NAME)
1339 /* A C statement to store into the string STRING a label whose name is made
1340 from the string PREFIX and the number NUM. */
1342 #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \
1344 sprintf (LABEL, "*.%s%d", PREFIX, NUM); \
1347 /* ??? Not sure if using a ? in the name for Intel as is safe. */
1349 #define ASM_PN_FORMAT (TARGET_GNU_AS ? "%s.%lu" : "%s?%lu")
1351 /* A C statement to output to the stdio stream STREAM assembler code which
1352 defines (equates) the symbol NAME to have the value VALUE. */
1354 #define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \
1356 assemble_name (STREAM, NAME); \
1357 fputs (" = ", STREAM); \
1358 if (ISDIGIT (*VALUE)) \
1359 ia64_asm_output_label = 1; \
1360 assemble_name (STREAM, VALUE); \
1361 fputc ('\n', STREAM); \
1362 ia64_asm_output_label = 0; \
1366 /* Macros Controlling Initialization Routines. */
1368 /* This is handled by sysv4.h. */
1371 /* Output of Assembler Instructions. */
1373 /* A C initializer containing the assembler's names for the machine registers,
1374 each one as a C string constant. */
1376 #define REGISTER_NAMES \
1378 /* General registers. */ \
1379 "ap", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \
1380 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \
1381 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \
1383 /* Local registers. */ \
1384 "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7", \
1385 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15", \
1386 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23", \
1387 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31", \
1388 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39", \
1389 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47", \
1390 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55", \
1391 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63", \
1392 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71", \
1393 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79", \
1394 /* Input registers. */ \
1395 "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7", \
1396 /* Output registers. */ \
1397 "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7", \
1398 /* Floating-point registers. */ \
1399 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", \
1400 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", \
1401 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", \
1402 "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", \
1403 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", \
1404 "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", \
1405 "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69", \
1406 "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79", \
1407 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89", \
1408 "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99", \
1409 "f100","f101","f102","f103","f104","f105","f106","f107","f108","f109",\
1410 "f110","f111","f112","f113","f114","f115","f116","f117","f118","f119",\
1411 "f120","f121","f122","f123","f124","f125","f126","f127", \
1412 /* Predicate registers. */ \
1413 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", \
1414 "p10", "p11", "p12", "p13", "p14", "p15", "p16", "p17", "p18", "p19", \
1415 "p20", "p21", "p22", "p23", "p24", "p25", "p26", "p27", "p28", "p29", \
1416 "p30", "p31", "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39", \
1417 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47", "p48", "p49", \
1418 "p50", "p51", "p52", "p53", "p54", "p55", "p56", "p57", "p58", "p59", \
1419 "p60", "p61", "p62", "p63", \
1420 /* Branch registers. */ \
1421 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", \
1422 /* Frame pointer. Application registers. */ \
1423 "sfp", "ar.ccv", "ar.unat", "ar.pfs", "ar.lc", "ar.ec", \
1426 /* If defined, a C initializer for an array of structures containing a name and
1427 a register number. This macro defines additional names for hard registers,
1428 thus allowing the `asm' option in declarations to refer to registers using
1431 #define ADDITIONAL_REGISTER_NAMES \
1433 { "gp", R_GR (1) }, \
1434 { "sp", R_GR (12) }, \
1435 { "in0", IN_REG (0) }, \
1436 { "in1", IN_REG (1) }, \
1437 { "in2", IN_REG (2) }, \
1438 { "in3", IN_REG (3) }, \
1439 { "in4", IN_REG (4) }, \
1440 { "in5", IN_REG (5) }, \
1441 { "in6", IN_REG (6) }, \
1442 { "in7", IN_REG (7) }, \
1443 { "out0", OUT_REG (0) }, \
1444 { "out1", OUT_REG (1) }, \
1445 { "out2", OUT_REG (2) }, \
1446 { "out3", OUT_REG (3) }, \
1447 { "out4", OUT_REG (4) }, \
1448 { "out5", OUT_REG (5) }, \
1449 { "out6", OUT_REG (6) }, \
1450 { "out7", OUT_REG (7) }, \
1451 { "loc0", LOC_REG (0) }, \
1452 { "loc1", LOC_REG (1) }, \
1453 { "loc2", LOC_REG (2) }, \
1454 { "loc3", LOC_REG (3) }, \
1455 { "loc4", LOC_REG (4) }, \
1456 { "loc5", LOC_REG (5) }, \
1457 { "loc6", LOC_REG (6) }, \
1458 { "loc7", LOC_REG (7) }, \
1459 { "loc8", LOC_REG (8) }, \
1460 { "loc9", LOC_REG (9) }, \
1461 { "loc10", LOC_REG (10) }, \
1462 { "loc11", LOC_REG (11) }, \
1463 { "loc12", LOC_REG (12) }, \
1464 { "loc13", LOC_REG (13) }, \
1465 { "loc14", LOC_REG (14) }, \
1466 { "loc15", LOC_REG (15) }, \
1467 { "loc16", LOC_REG (16) }, \
1468 { "loc17", LOC_REG (17) }, \
1469 { "loc18", LOC_REG (18) }, \
1470 { "loc19", LOC_REG (19) }, \
1471 { "loc20", LOC_REG (20) }, \
1472 { "loc21", LOC_REG (21) }, \
1473 { "loc22", LOC_REG (22) }, \
1474 { "loc23", LOC_REG (23) }, \
1475 { "loc24", LOC_REG (24) }, \
1476 { "loc25", LOC_REG (25) }, \
1477 { "loc26", LOC_REG (26) }, \
1478 { "loc27", LOC_REG (27) }, \
1479 { "loc28", LOC_REG (28) }, \
1480 { "loc29", LOC_REG (29) }, \
1481 { "loc30", LOC_REG (30) }, \
1482 { "loc31", LOC_REG (31) }, \
1483 { "loc32", LOC_REG (32) }, \
1484 { "loc33", LOC_REG (33) }, \
1485 { "loc34", LOC_REG (34) }, \
1486 { "loc35", LOC_REG (35) }, \
1487 { "loc36", LOC_REG (36) }, \
1488 { "loc37", LOC_REG (37) }, \
1489 { "loc38", LOC_REG (38) }, \
1490 { "loc39", LOC_REG (39) }, \
1491 { "loc40", LOC_REG (40) }, \
1492 { "loc41", LOC_REG (41) }, \
1493 { "loc42", LOC_REG (42) }, \
1494 { "loc43", LOC_REG (43) }, \
1495 { "loc44", LOC_REG (44) }, \
1496 { "loc45", LOC_REG (45) }, \
1497 { "loc46", LOC_REG (46) }, \
1498 { "loc47", LOC_REG (47) }, \
1499 { "loc48", LOC_REG (48) }, \
1500 { "loc49", LOC_REG (49) }, \
1501 { "loc50", LOC_REG (50) }, \
1502 { "loc51", LOC_REG (51) }, \
1503 { "loc52", LOC_REG (52) }, \
1504 { "loc53", LOC_REG (53) }, \
1505 { "loc54", LOC_REG (54) }, \
1506 { "loc55", LOC_REG (55) }, \
1507 { "loc56", LOC_REG (56) }, \
1508 { "loc57", LOC_REG (57) }, \
1509 { "loc58", LOC_REG (58) }, \
1510 { "loc59", LOC_REG (59) }, \
1511 { "loc60", LOC_REG (60) }, \
1512 { "loc61", LOC_REG (61) }, \
1513 { "loc62", LOC_REG (62) }, \
1514 { "loc63", LOC_REG (63) }, \
1515 { "loc64", LOC_REG (64) }, \
1516 { "loc65", LOC_REG (65) }, \
1517 { "loc66", LOC_REG (66) }, \
1518 { "loc67", LOC_REG (67) }, \
1519 { "loc68", LOC_REG (68) }, \
1520 { "loc69", LOC_REG (69) }, \
1521 { "loc70", LOC_REG (70) }, \
1522 { "loc71", LOC_REG (71) }, \
1523 { "loc72", LOC_REG (72) }, \
1524 { "loc73", LOC_REG (73) }, \
1525 { "loc74", LOC_REG (74) }, \
1526 { "loc75", LOC_REG (75) }, \
1527 { "loc76", LOC_REG (76) }, \
1528 { "loc77", LOC_REG (77) }, \
1529 { "loc78", LOC_REG (78) }, \
1530 { "loc79", LOC_REG (79) }, \
1533 /* A C compound statement to output to stdio stream STREAM the assembler syntax
1534 for an instruction operand X. X is an RTL expression. */
1536 #define PRINT_OPERAND(STREAM, X, CODE) \
1537 ia64_print_operand (STREAM, X, CODE)
1539 /* A C expression which evaluates to true if CODE is a valid punctuation
1540 character for use in the `PRINT_OPERAND' macro. */
1542 /* ??? Keep this around for now, as we might need it later. */
1544 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1545 ((CODE) == '+' || (CODE) == ',')
1547 /* A C compound statement to output to stdio stream STREAM the assembler syntax
1548 for an instruction operand that is a memory reference whose address is X. X
1549 is an RTL expression. */
1551 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
1552 ia64_print_operand_address (STREAM, X)
1554 /* If defined, C string expressions to be used for the `%R', `%L', `%U', and
1555 `%I' options of `asm_fprintf' (see `final.c'). */
1557 #define REGISTER_PREFIX ""
1558 #define LOCAL_LABEL_PREFIX "."
1559 #define USER_LABEL_PREFIX ""
1560 #define IMMEDIATE_PREFIX ""
1563 /* Output of dispatch tables. */
1565 /* This macro should be provided on machines where the addresses in a dispatch
1566 table are relative to the table's own address. */
1568 /* ??? Depends on the pointer size. */
1570 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
1573 fprintf (STREAM, "\tdata4 @pcrel(.L%d)\n", VALUE); \
1575 fprintf (STREAM, "\tdata8 @pcrel(.L%d)\n", VALUE); \
1578 /* Jump tables only need 8 byte alignment. */
1580 #define ADDR_VEC_ALIGN(ADDR_VEC) 3
1583 /* Assembler Commands for Exception Regions. */
1585 /* Select a format to encode pointers in exception handling data. CODE
1586 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1587 true if the symbol may be affected by dynamic relocations. */
1588 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1589 (((CODE) == 1 ? DW_EH_PE_textrel : DW_EH_PE_datarel) \
1590 | ((GLOBAL) ? DW_EH_PE_indirect : 0) \
1591 | (TARGET_ILP32 ? DW_EH_PE_udata4 : DW_EH_PE_udata8))
1593 /* Handle special EH pointer encodings. Absolute, pc-relative, and
1594 indirect are handled automatically. */
1595 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
1597 const char *reltag = NULL; \
1598 if (((ENCODING) & 0xF0) == DW_EH_PE_textrel) \
1599 reltag = "@segrel("; \
1600 else if (((ENCODING) & 0xF0) == DW_EH_PE_datarel) \
1601 reltag = "@gprel("; \
1604 fputs (integer_asm_op (SIZE, FALSE), FILE); \
1605 fputs (reltag, FILE); \
1606 assemble_name (FILE, XSTR (ADDR, 0)); \
1607 fputc (')', FILE); \
1613 /* Assembler Commands for Alignment. */
1615 /* ??? Investigate. */
1617 /* The alignment (log base 2) to put in front of LABEL, which follows
1620 /* #define LABEL_ALIGN_AFTER_BARRIER(LABEL) */
1622 /* The desired alignment for the location counter at the beginning
1625 /* #define LOOP_ALIGN(LABEL) */
1627 /* Define this macro if `ASM_OUTPUT_SKIP' should not be used in the text
1628 section because it fails put zeros in the bytes that are skipped. */
1630 #define ASM_NO_SKIP_IN_TEXT 1
1632 /* A C statement to output to the stdio stream STREAM an assembler command to
1633 advance the location counter to a multiple of 2 to the POWER bytes. */
1635 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
1636 fprintf (STREAM, "\t.align %d\n", 1<<(POWER))
1639 /* Macros Affecting all Debug Formats. */
1641 /* This is handled in sysv4.h. */
1644 /* Specific Options for DBX Output. */
1646 /* This is handled by dbxelf.h. */
1649 /* Open ended Hooks for DBX Output. */
1654 /* File names in DBX format. */
1659 /* Macros for SDB and Dwarf Output. */
1661 /* Define this macro if GCC should produce dwarf version 2 format debugging
1662 output in response to the `-g' option. */
1664 #define DWARF2_DEBUGGING_INFO 1
1666 #define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DWARF2_ASM)
1668 /* Use tags for debug info labels, so that they don't break instruction
1669 bundles. This also avoids getting spurious DV warnings from the
1670 assembler. This is similar to (*targetm.asm_out.internal_label), except that we
1671 add brackets around the label. */
1673 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
1674 fprintf (FILE, TARGET_GNU_AS ? "[.%s%d:]\n" : ".%s%d:\n", PREFIX, NUM)
1676 /* Use section-relative relocations for debugging offsets. Unlike other
1677 targets that fake this by putting the section VMA at 0, IA-64 has
1678 proper relocations for them. */
1679 #define ASM_OUTPUT_DWARF_OFFSET(FILE, SIZE, LABEL, SECTION) \
1681 fputs (integer_asm_op (SIZE, FALSE), FILE); \
1682 fputs ("@secrel(", FILE); \
1683 assemble_name (FILE, LABEL); \
1684 fputc (')', FILE); \
1687 /* Emit a PC-relative relocation. */
1688 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
1690 fputs (integer_asm_op (SIZE, FALSE), FILE); \
1691 fputs ("@pcrel(", FILE); \
1692 assemble_name (FILE, LABEL); \
1693 fputc (')', FILE); \
1696 /* Register Renaming Parameters. */
1698 /* A C expression that is nonzero if hard register number REGNO2 can be
1699 considered for use as a rename register for REGNO1 */
1701 #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \
1702 ia64_hard_regno_rename_ok((REGNO1), (REGNO2))
1705 /* Miscellaneous Parameters. */
1707 /* Flag to mark data that is in the small address area (addressable
1708 via "addl", that is, within a 2MByte offset of 0. */
1709 #define SYMBOL_FLAG_SMALL_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
1710 #define SYMBOL_REF_SMALL_ADDR_P(X) \
1711 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_SMALL_ADDR) != 0)
1713 /* An alias for a machine mode name. This is the machine mode that elements of
1714 a jump-table should have. */
1716 #define CASE_VECTOR_MODE ptr_mode
1718 /* Define as C expression which evaluates to nonzero if the tablejump
1719 instruction expects the table to contain offsets from the address of the
1722 #define CASE_VECTOR_PC_RELATIVE 1
1724 /* Define this macro if operations between registers with integral mode smaller
1725 than a word are always performed on the entire register. */
1727 #define WORD_REGISTER_OPERATIONS
1729 /* Define this macro to be a C expression indicating when insns that read
1730 memory in MODE, an integral mode narrower than a word, set the bits outside
1731 of MODE to be either the sign-extension or the zero-extension of the data
1734 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1736 /* The maximum number of bytes that a single instruction can move quickly from
1737 memory to memory. */
1740 /* A C expression which is nonzero if on this machine it is safe to "convert"
1741 an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller
1742 than INPREC) by merely operating on it as if it had only OUTPREC bits. */
1744 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1746 /* A C expression describing the value returned by a comparison operator with
1747 an integral mode and stored by a store-flag instruction (`sCOND') when the
1748 condition is true. */
1750 /* ??? Investigate using STORE_FLAG_VALUE of -1 instead of 1. */
1752 /* An alias for the machine mode for pointers. */
1754 /* ??? This would change if we had ILP32 support. */
1756 #define Pmode DImode
1758 /* An alias for the machine mode used for memory references to functions being
1759 called, in `call' RTL expressions. */
1761 #define FUNCTION_MODE Pmode
1763 /* A C expression for the maximum number of instructions to execute via
1764 conditional execution instructions instead of a branch. A value of
1765 BRANCH_COST+1 is the default if the machine does not use
1766 cc0, and 1 if it does use cc0. */
1767 /* ??? Investigate. */
1768 #define MAX_CONDITIONAL_EXECUTE 12
1770 extern int ia64_final_schedule;
1772 #define TARGET_UNWIND_TABLES_DEFAULT true
1774 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 15 : INVALID_REGNUM)
1776 /* This function contains machine specific function data. */
1777 struct GTY(()) machine_function
1779 /* The new stack pointer when unwinding from EH. */
1780 rtx ia64_eh_epilogue_sp;
1782 /* The new bsp value when unwinding from EH. */
1783 rtx ia64_eh_epilogue_bsp;
1785 /* The GP value save register. */
1788 /* The number of varargs registers to save. */
1791 /* The number of the next unwind state to copy. */
1795 #define DONT_USE_BUILTIN_SETJMP
1797 /* Output any profiling code before the prologue. */
1799 #undef PROFILE_BEFORE_PROLOGUE
1800 #define PROFILE_BEFORE_PROLOGUE 1
1802 /* Initialize library function table. */
1803 #undef TARGET_INIT_LIBFUNCS
1804 #define TARGET_INIT_LIBFUNCS ia64_init_libfuncs
1807 /* Switch on code for querying unit reservations. */
1808 #define CPU_UNITS_QUERY 1
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