1 /* Definitions of target machine GNU compiler. IA-64 version.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004
3 Free Software Foundation, Inc.
4 Contributed by James E. Wilson <wilson@cygnus.com> and
5 David Mosberger <davidm@hpl.hp.com>.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
24 /* ??? Look at ABI group documents for list of preprocessor macros and
25 other features required for ABI compliance. */
27 /* ??? Functions containing a non-local goto target save many registers. Why?
28 See for instance execute/920428-2.c. */
30 /* ??? Add support for short data/bss sections. */
33 /* Run-time target specifications */
35 /* Target CPU builtins. */
36 #define TARGET_CPU_CPP_BUILTINS() \
38 builtin_assert("cpu=ia64"); \
39 builtin_assert("machine=ia64"); \
40 builtin_define("__ia64"); \
41 builtin_define("__ia64__"); \
42 builtin_define("__itanium__"); \
43 if (TARGET_BIG_ENDIAN) \
44 builtin_define("__BIG_ENDIAN__"); \
47 #ifndef SUBTARGET_EXTRA_SPECS
48 #define SUBTARGET_EXTRA_SPECS
52 { "asm_extra", ASM_EXTRA_SPEC }, \
55 #define CC1_SPEC "%(cc1_cpu) "
57 #define ASM_EXTRA_SPEC ""
60 /* This declaration should be present. */
61 extern int target_flags;
63 /* This series of macros is to allow compiler command arguments to enable or
64 disable the use of optional features of the target machine. */
66 #define MASK_BIG_ENDIAN 0x00000001 /* Generate big endian code. */
68 #define MASK_GNU_AS 0x00000002 /* Generate code for GNU as. */
70 #define MASK_GNU_LD 0x00000004 /* Generate code for GNU ld. */
72 #define MASK_NO_PIC 0x00000008 /* Generate code without GP reg. */
74 #define MASK_VOL_ASM_STOP 0x00000010 /* Emit stop bits for vol ext asm. */
76 #define MASK_ILP32 0x00000020 /* Generate ILP32 code. */
78 #define MASK_B_STEP 0x00000040 /* Emit code for Itanium B step. */
80 #define MASK_REG_NAMES 0x00000080 /* Use in/loc/out register names. */
82 #define MASK_NO_SDATA 0x00000100 /* Disable sdata/scommon/sbss. */
84 #define MASK_CONST_GP 0x00000200 /* treat gp as program-wide constant */
86 #define MASK_AUTO_PIC 0x00000400 /* generate automatically PIC */
88 #define MASK_INLINE_FLOAT_DIV_LAT 0x00000800 /* inline div, min latency. */
90 #define MASK_INLINE_FLOAT_DIV_THR 0x00001000 /* inline div, max throughput. */
92 #define MASK_INLINE_INT_DIV_LAT 0x00002000 /* inline div, min latency. */
94 #define MASK_INLINE_INT_DIV_THR 0x00004000 /* inline div, max throughput. */
96 #define MASK_INLINE_SQRT_LAT 0x00008000 /* inline sqrt, min latency. */
98 #define MASK_INLINE_SQRT_THR 0x00010000 /* inline sqrt, max throughput. */
100 #define MASK_DWARF2_ASM 0x00020000 /* test dwarf2 line info via gas. */
102 #define MASK_EARLY_STOP_BITS 0x00040000 /* tune stop bits for the model. */
104 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
106 #define TARGET_GNU_AS (target_flags & MASK_GNU_AS)
108 #define TARGET_GNU_LD (target_flags & MASK_GNU_LD)
110 #define TARGET_NO_PIC (target_flags & MASK_NO_PIC)
112 #define TARGET_VOL_ASM_STOP (target_flags & MASK_VOL_ASM_STOP)
114 #define TARGET_ILP32 (target_flags & MASK_ILP32)
116 #define TARGET_B_STEP (target_flags & MASK_B_STEP)
118 #define TARGET_REG_NAMES (target_flags & MASK_REG_NAMES)
120 #define TARGET_NO_SDATA (target_flags & MASK_NO_SDATA)
122 #define TARGET_CONST_GP (target_flags & MASK_CONST_GP)
124 #define TARGET_AUTO_PIC (target_flags & MASK_AUTO_PIC)
126 #define TARGET_INLINE_FLOAT_DIV_LAT (target_flags & MASK_INLINE_FLOAT_DIV_LAT)
128 #define TARGET_INLINE_FLOAT_DIV_THR (target_flags & MASK_INLINE_FLOAT_DIV_THR)
130 #define TARGET_INLINE_INT_DIV_LAT (target_flags & MASK_INLINE_INT_DIV_LAT)
132 #define TARGET_INLINE_INT_DIV_THR (target_flags & MASK_INLINE_INT_DIV_THR)
134 #define TARGET_INLINE_FLOAT_DIV \
135 (target_flags & (MASK_INLINE_FLOAT_DIV_LAT | MASK_INLINE_FLOAT_DIV_THR))
137 #define TARGET_INLINE_INT_DIV \
138 (target_flags & (MASK_INLINE_INT_DIV_LAT | MASK_INLINE_INT_DIV_THR))
140 #define TARGET_INLINE_SQRT_LAT (target_flags & MASK_INLINE_SQRT_LAT)
142 #define TARGET_INLINE_SQRT_THR (target_flags & MASK_INLINE_SQRT_THR)
144 #define TARGET_INLINE_SQRT \
145 (target_flags & (MASK_INLINE_SQRT_LAT | MASK_INLINE_SQRT_THR))
147 #define TARGET_DWARF2_ASM (target_flags & MASK_DWARF2_ASM)
149 /* Variables which are this size or smaller are put in the sdata/sbss
151 extern unsigned int ia64_section_threshold;
153 /* If the assembler supports thread-local storage, assume that the
154 system does as well. If a particular target system has an
155 assembler that supports TLS -- but the rest of the system does not
156 support TLS -- that system should explicit define TARGET_HAVE_TLS
157 to false in its own configuration file. */
158 #if !defined(TARGET_HAVE_TLS) && defined(HAVE_AS_TLS)
159 #define TARGET_HAVE_TLS true
162 extern int ia64_tls_size;
163 #define TARGET_TLS14 (ia64_tls_size == 14)
164 #define TARGET_TLS22 (ia64_tls_size == 22)
165 #define TARGET_TLS64 (ia64_tls_size == 64)
166 #define TARGET_EARLY_STOP_BITS (target_flags & MASK_EARLY_STOP_BITS)
168 #define TARGET_HPUX 0
169 #define TARGET_HPUX_LD 0
171 #ifndef HAVE_AS_LTOFFX_LDXMOV_RELOCS
172 #define HAVE_AS_LTOFFX_LDXMOV_RELOCS 0
175 /* This macro defines names of command options to set and clear bits in
176 `target_flags'. Its definition is an initializer with a subgrouping for
177 each command option. */
179 #define TARGET_SWITCHES \
181 { "big-endian", MASK_BIG_ENDIAN, \
182 N_("Generate big endian code") }, \
183 { "little-endian", -MASK_BIG_ENDIAN, \
184 N_("Generate little endian code") }, \
185 { "gnu-as", MASK_GNU_AS, \
186 N_("Generate code for GNU as") }, \
187 { "no-gnu-as", -MASK_GNU_AS, \
188 N_("Generate code for Intel as") }, \
189 { "gnu-ld", MASK_GNU_LD, \
190 N_("Generate code for GNU ld") }, \
191 { "no-gnu-ld", -MASK_GNU_LD, \
192 N_("Generate code for Intel ld") }, \
193 { "no-pic", MASK_NO_PIC, \
194 N_("Generate code without GP reg") }, \
195 { "volatile-asm-stop", MASK_VOL_ASM_STOP, \
196 N_("Emit stop bits before and after volatile extended asms") }, \
197 { "no-volatile-asm-stop", -MASK_VOL_ASM_STOP, \
198 N_("Don't emit stop bits before and after volatile extended asms") }, \
199 { "b-step", MASK_B_STEP, \
200 N_("Emit code for Itanium (TM) processor B step")}, \
201 { "register-names", MASK_REG_NAMES, \
202 N_("Use in/loc/out register names")}, \
203 { "no-sdata", MASK_NO_SDATA, \
204 N_("Disable use of sdata/scommon/sbss")}, \
205 { "sdata", -MASK_NO_SDATA, \
206 N_("Enable use of sdata/scommon/sbss")}, \
207 { "constant-gp", MASK_CONST_GP, \
208 N_("gp is constant (but save/restore gp on indirect calls)") }, \
209 { "auto-pic", MASK_AUTO_PIC, \
210 N_("Generate self-relocatable code") }, \
211 { "inline-float-divide-min-latency", MASK_INLINE_FLOAT_DIV_LAT, \
212 N_("Generate inline floating point division, optimize for latency") },\
213 { "inline-float-divide-max-throughput", MASK_INLINE_FLOAT_DIV_THR, \
214 N_("Generate inline floating point division, optimize for throughput") },\
215 { "no-inline-float-divide", \
216 -(MASK_INLINE_FLOAT_DIV_LAT|MASK_INLINE_FLOAT_DIV_THR), \
217 N_("Do not inline floating point division") }, \
218 { "inline-int-divide-min-latency", MASK_INLINE_INT_DIV_LAT, \
219 N_("Generate inline integer division, optimize for latency") }, \
220 { "inline-int-divide-max-throughput", MASK_INLINE_INT_DIV_THR, \
221 N_("Generate inline integer division, optimize for throughput") },\
222 { "no-inline-int-divide", -(MASK_INLINE_INT_DIV_LAT|MASK_INLINE_INT_DIV_THR), \
223 N_("Do not inline integer division") }, \
224 { "inline-sqrt-min-latency", MASK_INLINE_SQRT_LAT, \
225 N_("Generate inline square root, optimize for latency") }, \
226 { "inline-sqrt-max-throughput", MASK_INLINE_SQRT_THR, \
227 N_("Generate inline square root, optimize for throughput") }, \
228 { "no-inline-sqrt", -(MASK_INLINE_SQRT_LAT|MASK_INLINE_SQRT_THR), \
229 N_("Do not inline square root") }, \
230 { "dwarf2-asm", MASK_DWARF2_ASM, \
231 N_("Enable Dwarf 2 line debug info via GNU as")}, \
232 { "no-dwarf2-asm", -MASK_DWARF2_ASM, \
233 N_("Disable Dwarf 2 line debug info via GNU as")}, \
234 { "early-stop-bits", MASK_EARLY_STOP_BITS, \
235 N_("Enable earlier placing stop bits for better scheduling")}, \
236 { "no-early-stop-bits", -MASK_EARLY_STOP_BITS, \
237 N_("Disable earlier placing stop bits")}, \
239 { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT, \
243 /* Default target_flags if no switches are specified */
245 #ifndef TARGET_DEFAULT
246 #define TARGET_DEFAULT (MASK_DWARF2_ASM | MASK_INLINE_FLOAT_DIV_THR)
249 #ifndef TARGET_CPU_DEFAULT
250 #define TARGET_CPU_DEFAULT 0
253 #ifndef SUBTARGET_SWITCHES
254 #define SUBTARGET_SWITCHES
257 /* This macro is similar to `TARGET_SWITCHES' but defines names of command
258 options that have values. Its definition is an initializer with a
259 subgrouping for each command option. */
261 extern const char *ia64_fixed_range_string;
262 extern const char *ia64_tls_size_string;
264 /* Which processor to schedule for. The cpu attribute defines a list
265 that mirrors this list, so changes to i64.md must be made at the
270 PROCESSOR_ITANIUM, /* Original Itanium. */
275 extern enum processor_type ia64_tune;
277 extern const char *ia64_tune_string;
279 #define TARGET_OPTIONS \
281 { "fixed-range=", &ia64_fixed_range_string, \
282 N_("Specify range of registers to make fixed"), 0}, \
283 { "tls-size=", &ia64_tls_size_string, \
284 N_("Specify bit size of immediate TLS offsets"), 0}, \
285 { "tune=", &ia64_tune_string, \
286 N_("Schedule code for given CPU"), 0}, \
289 /* Sometimes certain combinations of command options do not make sense on a
290 particular target machine. You can define a macro `OVERRIDE_OPTIONS' to
291 take account of this. This macro, if defined, is executed once just after
292 all the command options have been parsed. */
294 #define OVERRIDE_OPTIONS ia64_override_options ()
296 /* Some machines may desire to change what optimizations are performed for
297 various optimization levels. This macro, if defined, is executed once just
298 after the optimization level is determined and before the remainder of the
299 command options have been parsed. Values set in this macro are used as the
300 default values for the other command line options. */
302 /* #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) */
304 /* Driver configuration */
306 /* A C string constant that tells the GCC driver program options to pass to
307 `cc1'. It can also specify how to translate options you give to GCC into
308 options for GCC to pass to the `cc1'. */
311 #define CC1_SPEC "%{G*}"
313 /* A C string constant that tells the GCC driver program options to pass to
314 `cc1plus'. It can also specify how to translate options you give to GCC
315 into options for GCC to pass to the `cc1plus'. */
317 /* #define CC1PLUS_SPEC "" */
321 /* Define this macro to have the value 1 if the most significant bit in a byte
322 has the lowest number; otherwise define it to have the value zero. */
324 #define BITS_BIG_ENDIAN 0
326 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
328 /* Define this macro to have the value 1 if, in a multiword object, the most
329 significant word has the lowest number. */
331 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
333 #if defined(__BIG_ENDIAN__)
334 #define LIBGCC2_WORDS_BIG_ENDIAN 1
336 #define LIBGCC2_WORDS_BIG_ENDIAN 0
339 #define UNITS_PER_WORD 8
341 #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64)
343 /* A C expression whose value is zero if pointers that need to be extended
344 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and one if
345 they are zero-extended and negative one if there is a ptr_extend operation.
347 You need not define this macro if the `POINTER_SIZE' is equal to the width
349 /* Need this for 32 bit pointers, see hpux.h for setting it. */
350 /* #define POINTERS_EXTEND_UNSIGNED */
352 /* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and
353 which has the specified mode and signedness is to be stored in a register.
354 This macro is only called when TYPE is a scalar type. */
355 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
358 if (GET_MODE_CLASS (MODE) == MODE_INT \
359 && GET_MODE_SIZE (MODE) < 4) \
364 #define PARM_BOUNDARY 64
366 /* Define this macro if you wish to preserve a certain alignment for the stack
367 pointer. The definition is a C expression for the desired alignment
368 (measured in bits). */
370 #define STACK_BOUNDARY 128
372 /* Align frames on double word boundaries */
373 #ifndef IA64_STACK_ALIGN
374 #define IA64_STACK_ALIGN(LOC) (((LOC) + 15) & ~15)
377 #define FUNCTION_BOUNDARY 128
379 /* Optional x86 80-bit float, quad-precision 128-bit float, and quad-word
380 128 bit integers all require 128 bit alignment. */
381 #define BIGGEST_ALIGNMENT 128
383 /* If defined, a C expression to compute the alignment for a static variable.
384 TYPE is the data type, and ALIGN is the alignment that the object
385 would ordinarily have. The value of this macro is used instead of that
386 alignment to align the object. */
388 #define DATA_ALIGNMENT(TYPE, ALIGN) \
389 (TREE_CODE (TYPE) == ARRAY_TYPE \
390 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
391 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
393 /* If defined, a C expression to compute the alignment given to a constant that
394 is being placed in memory. CONSTANT is the constant and ALIGN is the
395 alignment that the object would ordinarily have. The value of this macro is
396 used instead of that alignment to align the object. */
398 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
399 (TREE_CODE (EXP) == STRING_CST \
400 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
402 #define STRICT_ALIGNMENT 1
404 /* Define this if you wish to imitate the way many other C compilers handle
405 alignment of bitfields and the structures that contain them.
406 The behavior is that the type written for a bit-field (`int', `short', or
407 other integer type) imposes an alignment for the entire structure, as if the
408 structure really did contain an ordinary field of that type. In addition,
409 the bit-field is placed within the structure so that it would fit within such
410 a field, not crossing a boundary for it. */
411 #define PCC_BITFIELD_TYPE_MATTERS 1
413 /* An integer expression for the size in bits of the largest integer machine
414 mode that should actually be used. */
416 /* Allow pairs of registers to be used, which is the intent of the default. */
417 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
419 /* By default, the C++ compiler will use function addresses in the
420 vtable entries. Setting this nonzero tells the compiler to use
421 function descriptors instead. The value of this macro says how
422 many words wide the descriptor is (normally 2). It is assumed
423 that the address of a function descriptor may be treated as a
424 pointer to a function.
426 For reasons known only to HP, the vtable entries (as opposed to
427 normal function descriptors) are 16 bytes wide in 32-bit mode as
428 well, even though the 3rd and 4th words are unused. */
429 #define TARGET_VTABLE_USES_DESCRIPTORS (TARGET_ILP32 ? 4 : 2)
431 /* Due to silliness in the HPUX linker, vtable entries must be
432 8-byte aligned even in 32-bit mode. Rather than create multiple
433 ABIs, force this restriction on everyone else too. */
434 #define TARGET_VTABLE_ENTRY_ALIGN 64
436 /* Due to the above, we need extra padding for the data entries below 0
437 to retain the alignment of the descriptors. */
438 #define TARGET_VTABLE_DATA_ENTRY_DISTANCE (TARGET_ILP32 ? 2 : 1)
440 /* Layout of Source Language Data Types */
442 #define INT_TYPE_SIZE 32
444 #define SHORT_TYPE_SIZE 16
446 #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64)
448 #define LONG_LONG_TYPE_SIZE 64
450 #define FLOAT_TYPE_SIZE 32
452 #define DOUBLE_TYPE_SIZE 64
454 /* long double is XFmode normally, TFmode for HPUX. */
455 #define LONG_DOUBLE_TYPE_SIZE (TARGET_HPUX ? 128 : 80)
457 /* We always want the XFmode operations from libgcc2.c. */
458 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 80
460 #define DEFAULT_SIGNED_CHAR 1
462 /* A C expression for a string describing the name of the data type to use for
463 size values. The typedef name `size_t' is defined using the contents of the
465 /* ??? Needs to be defined for P64 code. */
466 /* #define SIZE_TYPE */
468 /* A C expression for a string describing the name of the data type to use for
469 the result of subtracting two pointers. The typedef name `ptrdiff_t' is
470 defined using the contents of the string. See `SIZE_TYPE' above for more
472 /* ??? Needs to be defined for P64 code. */
473 /* #define PTRDIFF_TYPE */
475 /* A C expression for a string describing the name of the data type to use for
476 wide characters. The typedef name `wchar_t' is defined using the contents
477 of the string. See `SIZE_TYPE' above for more information. */
478 /* #define WCHAR_TYPE */
480 /* A C expression for the size in bits of the data type for wide characters.
481 This is used in `cpp', which cannot make use of `WCHAR_TYPE'. */
482 /* #define WCHAR_TYPE_SIZE */
485 /* Register Basics */
487 /* Number of hardware registers known to the compiler.
488 We have 128 general registers, 128 floating point registers,
489 64 predicate registers, 8 branch registers, one frame pointer,
490 and several "application" registers. */
492 #define FIRST_PSEUDO_REGISTER 334
494 /* Ranges for the various kinds of registers. */
495 #define ADDL_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 3)
496 #define GR_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 127)
497 #define FR_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 255)
498 #define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319)
499 #define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327)
500 #define GENERAL_REGNO_P(REGNO) \
501 (GR_REGNO_P (REGNO) || (REGNO) == FRAME_POINTER_REGNUM)
503 #define GR_REG(REGNO) ((REGNO) + 0)
504 #define FR_REG(REGNO) ((REGNO) + 128)
505 #define PR_REG(REGNO) ((REGNO) + 256)
506 #define BR_REG(REGNO) ((REGNO) + 320)
507 #define OUT_REG(REGNO) ((REGNO) + 120)
508 #define IN_REG(REGNO) ((REGNO) + 112)
509 #define LOC_REG(REGNO) ((REGNO) + 32)
511 #define AR_CCV_REGNUM 329
512 #define AR_UNAT_REGNUM 330
513 #define AR_PFS_REGNUM 331
514 #define AR_LC_REGNUM 332
515 #define AR_EC_REGNUM 333
517 #define IN_REGNO_P(REGNO) ((REGNO) >= IN_REG (0) && (REGNO) <= IN_REG (7))
518 #define LOC_REGNO_P(REGNO) ((REGNO) >= LOC_REG (0) && (REGNO) <= LOC_REG (79))
519 #define OUT_REGNO_P(REGNO) ((REGNO) >= OUT_REG (0) && (REGNO) <= OUT_REG (7))
521 #define AR_M_REGNO_P(REGNO) ((REGNO) == AR_CCV_REGNUM \
522 || (REGNO) == AR_UNAT_REGNUM)
523 #define AR_I_REGNO_P(REGNO) ((REGNO) >= AR_PFS_REGNUM \
524 && (REGNO) < FIRST_PSEUDO_REGISTER)
525 #define AR_REGNO_P(REGNO) ((REGNO) >= AR_CCV_REGNUM \
526 && (REGNO) < FIRST_PSEUDO_REGISTER)
529 /* ??? Don't really need two sets of macros. I like this one better because
530 it is less typing. */
531 #define R_GR(REGNO) GR_REG (REGNO)
532 #define R_FR(REGNO) FR_REG (REGNO)
533 #define R_PR(REGNO) PR_REG (REGNO)
534 #define R_BR(REGNO) BR_REG (REGNO)
536 /* An initializer that says which registers are used for fixed purposes all
537 throughout the compiled code and are therefore not available for general
541 r1: global pointer (gp)
542 r12: stack pointer (sp)
543 r13: thread pointer (tp)
547 fp: eliminable frame pointer */
549 /* The last 16 stacked regs are reserved for the 8 input and 8 output
552 #define FIXED_REGISTERS \
553 { /* General registers. */ \
554 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \
555 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
556 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
557 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
558 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
559 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
560 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
561 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
562 /* Floating-point registers. */ \
563 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
564 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
565 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
566 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
567 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
568 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
569 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
570 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
571 /* Predicate registers. */ \
572 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
573 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
574 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
575 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
576 /* Branch registers. */ \
577 0, 0, 0, 0, 0, 0, 0, 0, \
578 /*FP CCV UNAT PFS LC EC */ \
582 /* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered
583 (in general) by function calls as well as for fixed registers. This
584 macro therefore identifies the registers that are not available for
585 general allocation of values that must live across function calls. */
587 #define CALL_USED_REGISTERS \
588 { /* General registers. */ \
589 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
590 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
591 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
592 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
593 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
594 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
595 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
596 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
597 /* Floating-point registers. */ \
598 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
599 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
600 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
601 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
602 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
603 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
604 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
605 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
606 /* Predicate registers. */ \
607 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
608 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
609 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
610 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
611 /* Branch registers. */ \
612 1, 0, 0, 0, 0, 0, 1, 1, \
613 /*FP CCV UNAT PFS LC EC */ \
617 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
618 problem which makes CALL_USED_REGISTERS *always* include
619 all the FIXED_REGISTERS. Until this problem has been
620 resolved this macro can be used to overcome this situation.
621 In particular, block_propagate() requires this list
622 be accurate, or we can remove registers which should be live.
623 This macro is used in regs_invalidated_by_call. */
625 #define CALL_REALLY_USED_REGISTERS \
626 { /* General registers. */ \
627 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, \
628 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
629 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
630 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
631 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
632 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
633 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
634 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
635 /* Floating-point registers. */ \
636 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
637 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
638 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
639 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
640 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
641 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
642 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
643 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
644 /* Predicate registers. */ \
645 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
646 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
647 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
648 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
649 /* Branch registers. */ \
650 1, 0, 0, 0, 0, 0, 1, 1, \
651 /*FP CCV UNAT PFS LC EC */ \
656 /* Define this macro if the target machine has register windows. This C
657 expression returns the register number as seen by the called function
658 corresponding to the register number OUT as seen by the calling function.
659 Return OUT if register number OUT is not an outbound register. */
661 #define INCOMING_REGNO(OUT) \
662 ((unsigned) ((OUT) - OUT_REG (0)) < 8 ? IN_REG ((OUT) - OUT_REG (0)) : (OUT))
664 /* Define this macro if the target machine has register windows. This C
665 expression returns the register number as seen by the calling function
666 corresponding to the register number IN as seen by the called function.
667 Return IN if register number IN is not an inbound register. */
669 #define OUTGOING_REGNO(IN) \
670 ((unsigned) ((IN) - IN_REG (0)) < 8 ? OUT_REG ((IN) - IN_REG (0)) : (IN))
672 /* Define this macro if the target machine has register windows. This
673 C expression returns true if the register is call-saved but is in the
676 #define LOCAL_REGNO(REGNO) \
677 (IN_REGNO_P (REGNO) || LOC_REGNO_P (REGNO))
679 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
680 return the mode to be used for the comparison. Must be defined if
681 EXTRA_CC_MODES is defined. */
683 #define SELECT_CC_MODE(OP,X,Y) CCmode
685 /* Order of allocation of registers */
687 /* If defined, an initializer for a vector of integers, containing the numbers
688 of hard registers in the order in which GCC should prefer to use them
689 (from most preferred to least).
691 If this macro is not defined, registers are used lowest numbered first (all
694 One use of this macro is on machines where the highest numbered registers
695 must always be saved and the save-multiple-registers instruction supports
696 only sequences of consecutive registers. On such machines, define
697 `REG_ALLOC_ORDER' to be an initializer that lists the highest numbered
698 allocatable register first. */
700 /* ??? Should the GR return value registers come before or after the rest
701 of the caller-save GRs? */
703 #define REG_ALLOC_ORDER \
705 /* Caller-saved general registers. */ \
706 R_GR (14), R_GR (15), R_GR (16), R_GR (17), \
707 R_GR (18), R_GR (19), R_GR (20), R_GR (21), R_GR (22), R_GR (23), \
708 R_GR (24), R_GR (25), R_GR (26), R_GR (27), R_GR (28), R_GR (29), \
709 R_GR (30), R_GR (31), \
710 /* Output registers. */ \
711 R_GR (120), R_GR (121), R_GR (122), R_GR (123), R_GR (124), R_GR (125), \
712 R_GR (126), R_GR (127), \
713 /* Caller-saved general registers, also used for return values. */ \
714 R_GR (8), R_GR (9), R_GR (10), R_GR (11), \
715 /* addl caller-saved general registers. */ \
716 R_GR (2), R_GR (3), \
717 /* Caller-saved FP registers. */ \
718 R_FR (6), R_FR (7), \
719 /* Caller-saved FP registers, used for parameters and return values. */ \
720 R_FR (8), R_FR (9), R_FR (10), R_FR (11), \
721 R_FR (12), R_FR (13), R_FR (14), R_FR (15), \
722 /* Rotating caller-saved FP registers. */ \
723 R_FR (32), R_FR (33), R_FR (34), R_FR (35), \
724 R_FR (36), R_FR (37), R_FR (38), R_FR (39), R_FR (40), R_FR (41), \
725 R_FR (42), R_FR (43), R_FR (44), R_FR (45), R_FR (46), R_FR (47), \
726 R_FR (48), R_FR (49), R_FR (50), R_FR (51), R_FR (52), R_FR (53), \
727 R_FR (54), R_FR (55), R_FR (56), R_FR (57), R_FR (58), R_FR (59), \
728 R_FR (60), R_FR (61), R_FR (62), R_FR (63), R_FR (64), R_FR (65), \
729 R_FR (66), R_FR (67), R_FR (68), R_FR (69), R_FR (70), R_FR (71), \
730 R_FR (72), R_FR (73), R_FR (74), R_FR (75), R_FR (76), R_FR (77), \
731 R_FR (78), R_FR (79), R_FR (80), R_FR (81), R_FR (82), R_FR (83), \
732 R_FR (84), R_FR (85), R_FR (86), R_FR (87), R_FR (88), R_FR (89), \
733 R_FR (90), R_FR (91), R_FR (92), R_FR (93), R_FR (94), R_FR (95), \
734 R_FR (96), R_FR (97), R_FR (98), R_FR (99), R_FR (100), R_FR (101), \
735 R_FR (102), R_FR (103), R_FR (104), R_FR (105), R_FR (106), R_FR (107), \
736 R_FR (108), R_FR (109), R_FR (110), R_FR (111), R_FR (112), R_FR (113), \
737 R_FR (114), R_FR (115), R_FR (116), R_FR (117), R_FR (118), R_FR (119), \
738 R_FR (120), R_FR (121), R_FR (122), R_FR (123), R_FR (124), R_FR (125), \
739 R_FR (126), R_FR (127), \
740 /* Caller-saved predicate registers. */ \
741 R_PR (6), R_PR (7), R_PR (8), R_PR (9), R_PR (10), R_PR (11), \
742 R_PR (12), R_PR (13), R_PR (14), R_PR (15), \
743 /* Rotating caller-saved predicate registers. */ \
744 R_PR (16), R_PR (17), \
745 R_PR (18), R_PR (19), R_PR (20), R_PR (21), R_PR (22), R_PR (23), \
746 R_PR (24), R_PR (25), R_PR (26), R_PR (27), R_PR (28), R_PR (29), \
747 R_PR (30), R_PR (31), R_PR (32), R_PR (33), R_PR (34), R_PR (35), \
748 R_PR (36), R_PR (37), R_PR (38), R_PR (39), R_PR (40), R_PR (41), \
749 R_PR (42), R_PR (43), R_PR (44), R_PR (45), R_PR (46), R_PR (47), \
750 R_PR (48), R_PR (49), R_PR (50), R_PR (51), R_PR (52), R_PR (53), \
751 R_PR (54), R_PR (55), R_PR (56), R_PR (57), R_PR (58), R_PR (59), \
752 R_PR (60), R_PR (61), R_PR (62), R_PR (63), \
753 /* Caller-saved branch registers. */ \
754 R_BR (6), R_BR (7), \
756 /* Stacked callee-saved general registers. */ \
757 R_GR (32), R_GR (33), R_GR (34), R_GR (35), \
758 R_GR (36), R_GR (37), R_GR (38), R_GR (39), R_GR (40), R_GR (41), \
759 R_GR (42), R_GR (43), R_GR (44), R_GR (45), R_GR (46), R_GR (47), \
760 R_GR (48), R_GR (49), R_GR (50), R_GR (51), R_GR (52), R_GR (53), \
761 R_GR (54), R_GR (55), R_GR (56), R_GR (57), R_GR (58), R_GR (59), \
762 R_GR (60), R_GR (61), R_GR (62), R_GR (63), R_GR (64), R_GR (65), \
763 R_GR (66), R_GR (67), R_GR (68), R_GR (69), R_GR (70), R_GR (71), \
764 R_GR (72), R_GR (73), R_GR (74), R_GR (75), R_GR (76), R_GR (77), \
765 R_GR (78), R_GR (79), R_GR (80), R_GR (81), R_GR (82), R_GR (83), \
766 R_GR (84), R_GR (85), R_GR (86), R_GR (87), R_GR (88), R_GR (89), \
767 R_GR (90), R_GR (91), R_GR (92), R_GR (93), R_GR (94), R_GR (95), \
768 R_GR (96), R_GR (97), R_GR (98), R_GR (99), R_GR (100), R_GR (101), \
769 R_GR (102), R_GR (103), R_GR (104), R_GR (105), R_GR (106), R_GR (107), \
771 /* Input registers. */ \
772 R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (116), R_GR (117), \
773 R_GR (118), R_GR (119), \
774 /* Callee-saved general registers. */ \
775 R_GR (4), R_GR (5), R_GR (6), R_GR (7), \
776 /* Callee-saved FP registers. */ \
777 R_FR (2), R_FR (3), R_FR (4), R_FR (5), R_FR (16), R_FR (17), \
778 R_FR (18), R_FR (19), R_FR (20), R_FR (21), R_FR (22), R_FR (23), \
779 R_FR (24), R_FR (25), R_FR (26), R_FR (27), R_FR (28), R_FR (29), \
780 R_FR (30), R_FR (31), \
781 /* Callee-saved predicate registers. */ \
782 R_PR (1), R_PR (2), R_PR (3), R_PR (4), R_PR (5), \
783 /* Callee-saved branch registers. */ \
784 R_BR (1), R_BR (2), R_BR (3), R_BR (4), R_BR (5), \
786 /* ??? Stacked registers reserved for fp, rp, and ar.pfs. */ \
787 R_GR (109), R_GR (110), R_GR (111), \
789 /* Special general registers. */ \
790 R_GR (0), R_GR (1), R_GR (12), R_GR (13), \
791 /* Special FP registers. */ \
792 R_FR (0), R_FR (1), \
793 /* Special predicate registers. */ \
795 /* Special branch registers. */ \
797 /* Other fixed registers. */ \
798 FRAME_POINTER_REGNUM, \
799 AR_CCV_REGNUM, AR_UNAT_REGNUM, AR_PFS_REGNUM, AR_LC_REGNUM, \
803 /* How Values Fit in Registers */
805 /* A C expression for the number of consecutive hard registers, starting at
806 register number REGNO, required to hold a value of mode MODE. */
808 /* ??? We say that BImode PR values require two registers. This allows us to
809 easily store the normal and inverted values. We use CCImode to indicate
810 a single predicate register. */
812 #define HARD_REGNO_NREGS(REGNO, MODE) \
813 ((REGNO) == PR_REG (0) && (MODE) == DImode ? 64 \
814 : PR_REGNO_P (REGNO) && (MODE) == BImode ? 2 \
815 : PR_REGNO_P (REGNO) && (MODE) == CCImode ? 1 \
816 : FR_REGNO_P (REGNO) && (MODE) == XFmode ? 1 \
817 : FR_REGNO_P (REGNO) && (MODE) == XCmode ? 2 \
818 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
820 /* A C expression that is nonzero if it is permissible to store a value of mode
821 MODE in hard register number REGNO (or in several registers starting with
824 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
825 (FR_REGNO_P (REGNO) ? \
826 GET_MODE_CLASS (MODE) != MODE_CC && \
827 (MODE) != TImode && \
828 (MODE) != BImode && \
830 : PR_REGNO_P (REGNO) ? \
831 (MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \
832 : GR_REGNO_P (REGNO) ? \
833 (MODE) != CCImode && (MODE) != XFmode && (MODE) != XCmode \
834 : AR_REGNO_P (REGNO) ? (MODE) == DImode \
835 : BR_REGNO_P (REGNO) ? (MODE) == DImode \
838 /* A C expression that is nonzero if it is desirable to choose register
839 allocation so as to avoid move instructions between a value of mode MODE1
840 and a value of mode MODE2.
842 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
843 ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
845 /* Don't tie integer and FP modes, as that causes us to get integer registers
846 allocated for FP instructions. XFmode only supported in FP registers so
847 we can't tie it with any other modes. */
848 #define MODES_TIEABLE_P(MODE1, MODE2) \
849 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
850 && ((((MODE1) == XFmode) || ((MODE1) == XCmode)) \
851 == (((MODE2) == XFmode) || ((MODE2) == XCmode))) \
852 && (((MODE1) == BImode) == ((MODE2) == BImode)))
854 /* Specify the modes required to caller save a given hard regno.
855 We need to ensure floating pt regs are not saved as DImode. */
857 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
858 ((FR_REGNO_P (REGNO) && (NREGS) == 1) ? XFmode \
859 : choose_hard_reg_mode ((REGNO), (NREGS), false))
861 /* Handling Leaf Functions */
863 /* A C initializer for a vector, indexed by hard register number, which
864 contains 1 for a register that is allowable in a candidate for leaf function
866 /* ??? This might be useful. */
867 /* #define LEAF_REGISTERS */
869 /* A C expression whose value is the register number to which REGNO should be
870 renumbered, when a function is treated as a leaf function. */
871 /* ??? This might be useful. */
872 /* #define LEAF_REG_REMAP(REGNO) */
875 /* Register Classes */
877 /* An enumeral type that must be defined with all the register class names as
878 enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last
879 register class, followed by one more enumeral value, `LIM_REG_CLASSES',
880 which is not a register class but rather tells how many classes there
882 /* ??? When compiling without optimization, it is possible for the only use of
883 a pseudo to be a parameter load from the stack with a REG_EQUIV note.
884 Regclass handles this case specially and does not assign any costs to the
885 pseudo. The pseudo then ends up using the last class before ALL_REGS.
886 Thus we must not let either PR_REGS or BR_REGS be the last class. The
887 testcase for this is gcc.c-torture/execute/va-arg-7.c. */
904 #define GENERAL_REGS GR_REGS
906 /* The number of distinct register classes. */
907 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
909 /* An initializer containing the names of the register classes as C string
910 constants. These names are used in writing some of the debugging dumps. */
911 #define REG_CLASS_NAMES \
912 { "NO_REGS", "PR_REGS", "BR_REGS", "AR_M_REGS", "AR_I_REGS", \
913 "ADDL_REGS", "GR_REGS", "FR_REGS", \
914 "GR_AND_BR_REGS", "GR_AND_FR_REGS", "ALL_REGS" }
916 /* An initializer containing the contents of the register classes, as integers
917 which are bit masks. The Nth integer specifies the contents of class N.
918 The way the integer MASK is interpreted is that register R is in the class
919 if `MASK & (1 << R)' is 1. */
920 #define REG_CLASS_CONTENTS \
923 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
924 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
925 0x00000000, 0x00000000, 0x0000 }, \
927 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
928 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
929 0xFFFFFFFF, 0xFFFFFFFF, 0x0000 }, \
931 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
932 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
933 0x00000000, 0x00000000, 0x00FF }, \
935 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
936 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
937 0x00000000, 0x00000000, 0x0600 }, \
939 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
940 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
941 0x00000000, 0x00000000, 0x3800 }, \
943 { 0x0000000F, 0x00000000, 0x00000000, 0x00000000, \
944 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
945 0x00000000, 0x00000000, 0x0000 }, \
947 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
948 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
949 0x00000000, 0x00000000, 0x0100 }, \
951 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
952 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
953 0x00000000, 0x00000000, 0x0000 }, \
954 /* GR_AND_BR_REGS. */ \
955 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
956 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
957 0x00000000, 0x00000000, 0x01FF }, \
958 /* GR_AND_FR_REGS. */ \
959 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
960 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
961 0x00000000, 0x00000000, 0x0100 }, \
963 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
964 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
965 0xFFFFFFFF, 0xFFFFFFFF, 0x3FFF }, \
968 /* A C expression whose value is a register class containing hard register
969 REGNO. In general there is more than one such class; choose a class which
970 is "minimal", meaning that no smaller class also contains the register. */
971 /* The NO_REGS case is primarily for the benefit of rws_access_reg, which
972 may call here with private (invalid) register numbers, such as
974 #define REGNO_REG_CLASS(REGNO) \
975 (ADDL_REGNO_P (REGNO) ? ADDL_REGS \
976 : GENERAL_REGNO_P (REGNO) ? GR_REGS \
977 : FR_REGNO_P (REGNO) ? FR_REGS \
978 : PR_REGNO_P (REGNO) ? PR_REGS \
979 : BR_REGNO_P (REGNO) ? BR_REGS \
980 : AR_M_REGNO_P (REGNO) ? AR_M_REGS \
981 : AR_I_REGNO_P (REGNO) ? AR_I_REGS \
984 /* A macro whose definition is the name of the class to which a valid base
985 register must belong. A base register is one used in an address which is
986 the register value plus a displacement. */
987 #define BASE_REG_CLASS GENERAL_REGS
989 /* A macro whose definition is the name of the class to which a valid index
990 register must belong. An index register is one used in an address where its
991 value is either multiplied by a scale factor or added to another register
992 (as well as added to a displacement). This is needed for POST_MODIFY. */
993 #define INDEX_REG_CLASS GENERAL_REGS
995 /* A C expression which defines the machine-dependent operand constraint
996 letters for register classes. If CHAR is such a letter, the value should be
997 the register class corresponding to it. Otherwise, the value should be
998 `NO_REGS'. The register letter `r', corresponding to class `GENERAL_REGS',
999 will not be passed to this macro; you do not need to handle it. */
1001 #define REG_CLASS_FROM_LETTER(CHAR) \
1002 ((CHAR) == 'f' ? FR_REGS \
1003 : (CHAR) == 'a' ? ADDL_REGS \
1004 : (CHAR) == 'b' ? BR_REGS \
1005 : (CHAR) == 'c' ? PR_REGS \
1006 : (CHAR) == 'd' ? AR_M_REGS \
1007 : (CHAR) == 'e' ? AR_I_REGS \
1010 /* A C expression which is nonzero if register number NUM is suitable for use
1011 as a base register in operand addresses. It may be either a suitable hard
1012 register or a pseudo register that has been allocated such a hard reg. */
1013 #define REGNO_OK_FOR_BASE_P(REGNO) \
1014 (GENERAL_REGNO_P (REGNO) || GENERAL_REGNO_P (reg_renumber[REGNO]))
1016 /* A C expression which is nonzero if register number NUM is suitable for use
1017 as an index register in operand addresses. It may be either a suitable hard
1018 register or a pseudo register that has been allocated such a hard reg.
1019 This is needed for POST_MODIFY. */
1020 #define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM)
1022 /* A C expression that places additional restrictions on the register class to
1023 use when it is necessary to copy value X into a register in class CLASS.
1024 The value is a register class; perhaps CLASS, or perhaps another, smaller
1027 /* Don't allow volatile mem reloads into floating point registers. This
1028 is defined to force reload to choose the r/m case instead of the f/f case
1029 when reloading (set (reg fX) (mem/v)).
1031 Do not reload expressions into AR regs. */
1033 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1034 (CLASS == FR_REGS && GET_CODE (X) == MEM && MEM_VOLATILE_P (X) ? NO_REGS \
1035 : CLASS == FR_REGS && GET_CODE (X) == CONST_DOUBLE ? NO_REGS \
1037 && (CLASS == AR_M_REGS || CLASS == AR_I_REGS) ? NO_REGS \
1040 /* You should define this macro to indicate to the reload phase that it may
1041 need to allocate at least one register for a reload in addition to the
1042 register to contain the data. Specifically, if copying X to a register
1043 CLASS in MODE requires an intermediate register, you should define this
1044 to return the largest register class all of whose registers can be used
1045 as intermediate registers or scratch registers. */
1047 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
1048 ia64_secondary_reload_class (CLASS, MODE, X)
1050 /* Certain machines have the property that some registers cannot be copied to
1051 some other registers without using memory. Define this macro on those
1052 machines to be a C expression that is nonzero if objects of mode M in
1053 registers of CLASS1 can only be copied to registers of class CLASS2 by
1054 storing a register of CLASS1 into memory and loading that memory location
1055 into a register of CLASS2. */
1058 /* ??? May need this, but since we've disallowed XFmode in GR_REGS,
1059 I'm not quite sure how it could be invoked. The normal problems
1060 with unions should be solved with the addressof fiddling done by
1061 movxf and friends. */
1062 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1063 (((MODE) == XFmode || (MODE) == XCmode) \
1064 && (((CLASS1) == GR_REGS && (CLASS2) == FR_REGS) \
1065 || ((CLASS1) == FR_REGS && (CLASS2) == GR_REGS)))
1068 /* A C expression for the maximum number of consecutive registers of
1069 class CLASS needed to hold a value of mode MODE.
1070 This is closely related to the macro `HARD_REGNO_NREGS'. */
1072 #define CLASS_MAX_NREGS(CLASS, MODE) \
1073 ((MODE) == BImode && (CLASS) == PR_REGS ? 2 \
1074 : ((CLASS) == FR_REGS && (MODE) == XFmode) ? 1 \
1075 : ((CLASS) == FR_REGS && (MODE) == XCmode) ? 2 \
1076 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1078 /* In FP regs, we can't change FP values to integer values and vice
1079 versa, but we can change e.g. DImode to SImode. */
1081 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1082 (GET_MODE_CLASS (FROM) != GET_MODE_CLASS (TO) \
1083 ? reg_classes_intersect_p (CLASS, FR_REGS) : 0)
1085 /* A C expression that defines the machine-dependent operand constraint
1086 letters (`I', `J', `K', .. 'P') that specify particular ranges of
1089 /* 14 bit signed immediate for arithmetic instructions. */
1090 #define CONST_OK_FOR_I(VALUE) \
1091 ((unsigned HOST_WIDE_INT)(VALUE) + 0x2000 < 0x4000)
1092 /* 22 bit signed immediate for arith instructions with r0/r1/r2/r3 source. */
1093 #define CONST_OK_FOR_J(VALUE) \
1094 ((unsigned HOST_WIDE_INT)(VALUE) + 0x200000 < 0x400000)
1095 /* 8 bit signed immediate for logical instructions. */
1096 #define CONST_OK_FOR_K(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x80 < 0x100)
1097 /* 8 bit adjusted signed immediate for compare pseudo-ops. */
1098 #define CONST_OK_FOR_L(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x7F < 0x100)
1099 /* 6 bit unsigned immediate for shift counts. */
1100 #define CONST_OK_FOR_M(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) < 0x40)
1101 /* 9 bit signed immediate for load/store post-increments. */
1102 #define CONST_OK_FOR_N(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x100 < 0x200)
1103 /* 0 for r0. Used by Linux kernel, do not change. */
1104 #define CONST_OK_FOR_O(VALUE) ((VALUE) == 0)
1105 /* 0 or -1 for dep instruction. */
1106 #define CONST_OK_FOR_P(VALUE) ((VALUE) == 0 || (VALUE) == -1)
1108 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1109 ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
1110 : (C) == 'J' ? CONST_OK_FOR_J (VALUE) \
1111 : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
1112 : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
1113 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
1114 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
1115 : (C) == 'O' ? CONST_OK_FOR_O (VALUE) \
1116 : (C) == 'P' ? CONST_OK_FOR_P (VALUE) \
1119 /* A C expression that defines the machine-dependent operand constraint letters
1120 (`G', `H') that specify particular ranges of `const_double' values. */
1122 /* 0.0 and 1.0 for fr0 and fr1. */
1123 #define CONST_DOUBLE_OK_FOR_G(VALUE) \
1124 ((VALUE) == CONST0_RTX (GET_MODE (VALUE)) \
1125 || (VALUE) == CONST1_RTX (GET_MODE (VALUE)))
1127 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1128 ((C) == 'G' ? CONST_DOUBLE_OK_FOR_G (VALUE) : 0)
1130 /* A C expression that defines the optional machine-dependent constraint
1131 letters (`Q', `R', `S', `T', `U') that can be used to segregate specific
1132 types of operands, usually memory references, for the target machine. */
1134 /* Non-volatile memory for FP_REG loads/stores. */
1135 #define CONSTRAINT_OK_FOR_Q(VALUE) \
1136 (memory_operand((VALUE), VOIDmode) && ! MEM_VOLATILE_P (VALUE))
1137 /* 1..4 for shladd arguments. */
1138 #define CONSTRAINT_OK_FOR_R(VALUE) \
1139 (GET_CODE (VALUE) == CONST_INT && INTVAL (VALUE) >= 1 && INTVAL (VALUE) <= 4)
1140 /* Non-post-inc memory for asms and other unsavory creatures. */
1141 #define CONSTRAINT_OK_FOR_S(VALUE) \
1142 (GET_CODE (VALUE) == MEM \
1143 && GET_RTX_CLASS (GET_CODE (XEXP ((VALUE), 0))) != RTX_AUTOINC \
1144 && (reload_in_progress || memory_operand ((VALUE), VOIDmode)))
1145 /* Symbol ref to small-address-area: */
1146 #define CONSTRAINT_OK_FOR_T(VALUE) \
1147 (GET_CODE (VALUE) == SYMBOL_REF && SYMBOL_REF_SMALL_ADDR_P (VALUE))
1149 #define EXTRA_CONSTRAINT(VALUE, C) \
1150 ((C) == 'Q' ? CONSTRAINT_OK_FOR_Q (VALUE) \
1151 : (C) == 'R' ? CONSTRAINT_OK_FOR_R (VALUE) \
1152 : (C) == 'S' ? CONSTRAINT_OK_FOR_S (VALUE) \
1153 : (C) == 'T' ? CONSTRAINT_OK_FOR_T (VALUE) \
1156 /* Basic Stack Layout */
1158 /* Define this macro if pushing a word onto the stack moves the stack pointer
1159 to a smaller address. */
1160 #define STACK_GROWS_DOWNWARD 1
1162 /* Define this macro if the addresses of local variable slots are at negative
1163 offsets from the frame pointer. */
1164 /* #define FRAME_GROWS_DOWNWARD */
1166 /* Offset from the frame pointer to the first local variable slot to
1168 #define STARTING_FRAME_OFFSET 0
1170 /* Offset from the stack pointer register to the first location at which
1171 outgoing arguments are placed. If not specified, the default value of zero
1172 is used. This is the proper value for most machines. */
1173 /* IA64 has a 16 byte scratch area that is at the bottom of the stack. */
1174 #define STACK_POINTER_OFFSET 16
1176 /* Offset from the argument pointer register to the first argument's address.
1177 On some machines it may depend on the data type of the function. */
1178 #define FIRST_PARM_OFFSET(FUNDECL) 0
1180 /* A C expression whose value is RTL representing the value of the return
1181 address for the frame COUNT steps up from the current frame, after the
1184 /* ??? Frames other than zero would likely require interpreting the frame
1185 unwind info, so we don't try to support them. We would also need to define
1186 DYNAMIC_CHAIN_ADDRESS and SETUP_FRAME_ADDRESS (for the reg stack flush). */
1188 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1189 ia64_return_addr_rtx (COUNT, FRAME)
1191 /* A C expression whose value is RTL representing the location of the incoming
1192 return address at the beginning of any function, before the prologue. This
1193 RTL is either a `REG', indicating that the return value is saved in `REG',
1194 or a `MEM' representing a location in the stack. This enables DWARF2
1195 unwind info for C++ EH. */
1196 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, BR_REG (0))
1198 /* ??? This is not defined because of three problems.
1199 1) dwarf2out.c assumes that DWARF_FRAME_RETURN_COLUMN fits in one byte.
1200 The default value is FIRST_PSEUDO_REGISTER which doesn't. This can be
1201 worked around by setting PC_REGNUM to FR_REG (0) which is an otherwise
1202 unused register number.
1203 2) dwarf2out_frame_debug core dumps while processing prologue insns. We
1204 need to refine which insns have RTX_FRAME_RELATED_P set and which don't.
1205 3) It isn't possible to turn off EH frame info by defining DWARF2_UNIND_INFO
1206 to zero, despite what the documentation implies, because it is tested in
1207 a few places with #ifdef instead of #if. */
1208 #undef INCOMING_RETURN_ADDR_RTX
1210 /* A C expression whose value is an integer giving the offset, in bytes, from
1211 the value of the stack pointer register to the top of the stack frame at the
1212 beginning of any function, before the prologue. The top of the frame is
1213 defined to be the value of the stack pointer in the previous frame, just
1214 before the call instruction. */
1215 #define INCOMING_FRAME_SP_OFFSET 0
1218 /* Register That Address the Stack Frame. */
1220 /* The register number of the stack pointer register, which must also be a
1221 fixed register according to `FIXED_REGISTERS'. On most machines, the
1222 hardware determines which register this is. */
1224 #define STACK_POINTER_REGNUM 12
1226 /* The register number of the frame pointer register, which is used to access
1227 automatic variables in the stack frame. On some machines, the hardware
1228 determines which register this is. On other machines, you can choose any
1229 register you wish for this purpose. */
1231 #define FRAME_POINTER_REGNUM 328
1233 /* Base register for access to local variables of the function. */
1234 #define HARD_FRAME_POINTER_REGNUM LOC_REG (79)
1236 /* The register number of the arg pointer register, which is used to access the
1237 function's argument list. */
1238 /* r0 won't otherwise be used, so put the always eliminated argument pointer
1240 #define ARG_POINTER_REGNUM R_GR(0)
1242 /* Due to the way varargs and argument spilling happens, the argument
1243 pointer is not 16-byte aligned like the stack pointer. */
1244 #define INIT_EXPANDERS \
1246 if (cfun && cfun->emit->regno_pointer_align) \
1247 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = 64; \
1250 /* Register numbers used for passing a function's static chain pointer. */
1251 /* ??? The ABI sez the static chain should be passed as a normal parameter. */
1252 #define STATIC_CHAIN_REGNUM 15
1254 /* Eliminating the Frame Pointer and the Arg Pointer */
1256 /* A C expression which is nonzero if a function must have and use a frame
1257 pointer. This expression is evaluated in the reload pass. If its value is
1258 nonzero the function will have a frame pointer. */
1259 #define FRAME_POINTER_REQUIRED 0
1261 /* Show we can debug even without a frame pointer. */
1262 #define CAN_DEBUG_WITHOUT_FP
1264 /* If defined, this macro specifies a table of register pairs used to eliminate
1265 unneeded registers that point into the stack frame. */
1267 #define ELIMINABLE_REGS \
1269 {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1270 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1271 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1272 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1275 /* A C expression that returns nonzero if the compiler is allowed to try to
1276 replace register number FROM with register number TO. The frame pointer
1277 is automatically handled. */
1279 #define CAN_ELIMINATE(FROM, TO) \
1280 (TO == BR_REG (0) ? current_function_is_leaf : 1)
1282 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
1283 specifies the initial difference between the specified pair of
1284 registers. This macro must be defined if `ELIMINABLE_REGS' is
1286 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1287 ((OFFSET) = ia64_initial_elimination_offset ((FROM), (TO)))
1289 /* Passing Function Arguments on the Stack */
1291 /* If defined, the maximum amount of space required for outgoing arguments will
1292 be computed and placed into the variable
1293 `current_function_outgoing_args_size'. */
1295 #define ACCUMULATE_OUTGOING_ARGS 1
1297 /* A C expression that should indicate the number of bytes of its own arguments
1298 that a function pops on returning, or 0 if the function pops no arguments
1299 and the caller must therefore pop them all after the function returns. */
1301 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
1304 /* Function Arguments in Registers */
1306 #define MAX_ARGUMENT_SLOTS 8
1307 #define MAX_INT_RETURN_SLOTS 4
1308 #define GR_ARG_FIRST IN_REG (0)
1309 #define GR_RET_FIRST GR_REG (8)
1310 #define GR_RET_LAST GR_REG (11)
1311 #define FR_ARG_FIRST FR_REG (8)
1312 #define FR_RET_FIRST FR_REG (8)
1313 #define FR_RET_LAST FR_REG (15)
1314 #define AR_ARG_FIRST OUT_REG (0)
1316 /* A C expression that controls whether a function argument is passed in a
1317 register, and which register. */
1319 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1320 ia64_function_arg (&CUM, MODE, TYPE, NAMED, 0)
1322 /* Define this macro if the target machine has "register windows", so that the
1323 register in which a function sees an arguments is not necessarily the same
1324 as the one in which the caller passed the argument. */
1326 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1327 ia64_function_arg (&CUM, MODE, TYPE, NAMED, 1)
1329 /* A C expression for the number of words, at the beginning of an argument,
1330 must be put in registers. The value must be zero for arguments that are
1331 passed entirely in registers or that are entirely pushed on the stack. */
1333 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1334 ia64_function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
1336 /* A C type for declaring a variable that is used as the first argument of
1337 `FUNCTION_ARG' and other related values. For some target machines, the type
1338 `int' suffices and can hold the number of bytes of argument so far. */
1340 typedef struct ia64_args
1342 int words; /* # words of arguments so far */
1343 int int_regs; /* # GR registers used so far */
1344 int fp_regs; /* # FR registers used so far */
1345 int prototype; /* whether function prototyped */
1348 /* A C statement (sans semicolon) for initializing the variable CUM for the
1349 state at the beginning of the argument list. */
1351 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1354 (CUM).int_regs = 0; \
1355 (CUM).fp_regs = 0; \
1356 (CUM).prototype = ((FNTYPE) && TYPE_ARG_TYPES (FNTYPE)) || (LIBNAME); \
1359 /* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of finding the
1360 arguments for the function being compiled. If this macro is undefined,
1361 `INIT_CUMULATIVE_ARGS' is used instead. */
1363 /* We set prototype to true so that we never try to return a PARALLEL from
1365 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1368 (CUM).int_regs = 0; \
1369 (CUM).fp_regs = 0; \
1370 (CUM).prototype = 1; \
1373 /* A C statement (sans semicolon) to update the summarizer variable CUM to
1374 advance past an argument in the argument list. The values MODE, TYPE and
1375 NAMED describe that argument. Once this is done, the variable CUM is
1376 suitable for analyzing the *following* argument with `FUNCTION_ARG'. */
1378 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1379 ia64_function_arg_advance (&CUM, MODE, TYPE, NAMED)
1381 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1382 argument with the specified mode and type. */
1384 /* Return the alignment boundary in bits for an argument with a specified
1387 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1388 ia64_function_arg_boundary (MODE, TYPE)
1390 /* A C expression that is nonzero if REGNO is the number of a hard register in
1391 which function arguments are sometimes passed. This does *not* include
1392 implicit arguments such as the static chain and the structure-value address.
1393 On many machines, no registers can be used for this purpose since all
1394 function arguments are pushed on the stack. */
1395 #define FUNCTION_ARG_REGNO_P(REGNO) \
1396 (((REGNO) >= AR_ARG_FIRST && (REGNO) < (AR_ARG_FIRST + MAX_ARGUMENT_SLOTS)) \
1397 || ((REGNO) >= FR_ARG_FIRST && (REGNO) < (FR_ARG_FIRST + MAX_ARGUMENT_SLOTS)))
1399 /* How Scalar Function Values are Returned */
1401 /* A C expression to create an RTX representing the place where a function
1402 returns a value of data type VALTYPE. */
1404 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1405 ia64_function_value (VALTYPE, FUNC)
1407 /* A C expression to create an RTX representing the place where a library
1408 function returns a value of mode MODE. */
1410 #define LIBCALL_VALUE(MODE) \
1411 gen_rtx_REG (MODE, \
1412 (((GET_MODE_CLASS (MODE) == MODE_FLOAT \
1413 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) && \
1415 ? FR_RET_FIRST : GR_RET_FIRST))
1417 /* A C expression that is nonzero if REGNO is the number of a hard register in
1418 which the values of called function may come back. */
1420 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1421 (((REGNO) >= GR_RET_FIRST && (REGNO) <= GR_RET_LAST) \
1422 || ((REGNO) >= FR_RET_FIRST && (REGNO) <= FR_RET_LAST))
1425 /* How Large Values are Returned */
1427 #define DEFAULT_PCC_STRUCT_RETURN 0
1430 /* Caller-Saves Register Allocation */
1432 /* A C expression to determine whether it is worthwhile to consider placing a
1433 pseudo-register in a call-clobbered hard register and saving and restoring
1434 it around each function call. The expression should be 1 when this is worth
1435 doing, and 0 otherwise.
1437 If you don't define this macro, a default is used which is good on most
1438 machines: `4 * CALLS < REFS'. */
1439 /* ??? Investigate. */
1440 /* #define CALLER_SAVE_PROFITABLE(REFS, CALLS) */
1443 /* Function Entry and Exit */
1445 /* Define this macro as a C expression that is nonzero if the return
1446 instruction or the function epilogue ignores the value of the stack pointer;
1447 in other words, if it is safe to delete an instruction to adjust the stack
1448 pointer before a return from the function. */
1450 #define EXIT_IGNORE_STACK 1
1452 /* Define this macro as a C expression that is nonzero for registers
1453 used by the epilogue or the `return' pattern. */
1455 #define EPILOGUE_USES(REGNO) ia64_epilogue_uses (REGNO)
1457 /* Nonzero for registers used by the exception handling mechanism. */
1459 #define EH_USES(REGNO) ia64_eh_uses (REGNO)
1461 /* Output part N of a function descriptor for DECL. For ia64, both
1462 words are emitted with a single relocation, so ignore N > 0. */
1463 #define ASM_OUTPUT_FDESC(FILE, DECL, PART) \
1468 fputs ("\tdata8.ua @iplt(", FILE); \
1470 fputs ("\tdata16.ua @iplt(", FILE); \
1471 mark_decl_referenced (DECL); \
1472 assemble_name (FILE, XSTR (XEXP (DECL_RTL (DECL), 0), 0)); \
1473 fputs (")\n", FILE); \
1475 fputs ("\tdata8.ua 0\n", FILE); \
1479 /* Generating Code for Profiling. */
1481 /* A C statement or compound statement to output to FILE some assembler code to
1482 call the profiling subroutine `mcount'. */
1484 #undef FUNCTION_PROFILER
1485 #define FUNCTION_PROFILER(FILE, LABELNO) \
1488 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", LABELNO); \
1489 fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", FILE); \
1490 if (TARGET_AUTO_PIC) \
1491 fputs ("\tmovl out3 = @gprel(", FILE); \
1493 fputs ("\taddl out3 = @ltoff(", FILE); \
1494 assemble_name (FILE, buf); \
1495 if (TARGET_AUTO_PIC) \
1496 fputs (");;\n", FILE); \
1498 fputs ("), r1;;\n", FILE); \
1499 fputs ("\tmov out1 = r1\n", FILE); \
1500 fputs ("\tmov out2 = b0\n", FILE); \
1501 fputs ("\tbr.call.sptk.many b0 = _mcount;;\n", FILE); \
1504 /* Trampolines for Nested Functions. */
1506 /* We need 32 bytes, so we can save the sp, ar.rnat, ar.bsp, and ar.pfs of
1507 the function containing a non-local goto target. */
1509 #define STACK_SAVEAREA_MODE(LEVEL) \
1510 ((LEVEL) == SAVE_NONLOCAL ? OImode : Pmode)
1512 /* Output assembler code for a block containing the constant parts of
1513 a trampoline, leaving space for the variable parts.
1515 The trampoline should set the static chain pointer to value placed
1516 into the trampoline and should branch to the specified routine.
1517 To make the normal indirect-subroutine calling convention work,
1518 the trampoline must look like a function descriptor; the first
1519 word being the target address and the second being the target's
1522 We abuse the concept of a global pointer by arranging for it
1523 to point to the data we need to load. The complete trampoline
1524 has the following form:
1526 +-------------------+ \
1527 TRAMP: | __ia64_trampoline | |
1528 +-------------------+ > fake function descriptor
1530 +-------------------+ /
1531 | target descriptor |
1532 +-------------------+
1534 +-------------------+
1537 /* A C expression for the size in bytes of the trampoline, as an integer. */
1539 #define TRAMPOLINE_SIZE 32
1541 /* Alignment required for trampolines, in bits. */
1543 #define TRAMPOLINE_ALIGNMENT 64
1545 /* A C statement to initialize the variable parts of a trampoline. */
1547 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, STATIC_CHAIN) \
1548 ia64_initialize_trampoline((ADDR), (FNADDR), (STATIC_CHAIN))
1550 /* Addressing Modes */
1552 /* Define this macro if the machine supports post-increment addressing. */
1554 #define HAVE_POST_INCREMENT 1
1555 #define HAVE_POST_DECREMENT 1
1556 #define HAVE_POST_MODIFY_DISP 1
1557 #define HAVE_POST_MODIFY_REG 1
1559 /* A C expression that is 1 if the RTX X is a constant which is a valid
1562 #define CONSTANT_ADDRESS_P(X) 0
1564 /* The max number of registers that can appear in a valid memory address. */
1566 #define MAX_REGS_PER_ADDRESS 2
1568 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
1569 RTX) is a legitimate memory address on the target machine for a memory
1570 operand of mode MODE. */
1572 #define LEGITIMATE_ADDRESS_REG(X) \
1573 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1574 || (GET_CODE (X) == SUBREG && GET_CODE (XEXP (X, 0)) == REG \
1575 && REG_OK_FOR_BASE_P (XEXP (X, 0))))
1577 #define LEGITIMATE_ADDRESS_DISP(R, X) \
1578 (GET_CODE (X) == PLUS \
1579 && rtx_equal_p (R, XEXP (X, 0)) \
1580 && (LEGITIMATE_ADDRESS_REG (XEXP (X, 1)) \
1581 || (GET_CODE (XEXP (X, 1)) == CONST_INT \
1582 && INTVAL (XEXP (X, 1)) >= -256 \
1583 && INTVAL (XEXP (X, 1)) < 256)))
1585 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1587 if (LEGITIMATE_ADDRESS_REG (X)) \
1589 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
1590 && LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \
1591 && XEXP (X, 0) != arg_pointer_rtx) \
1593 else if (GET_CODE (X) == POST_MODIFY \
1594 && LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \
1595 && XEXP (X, 0) != arg_pointer_rtx \
1596 && LEGITIMATE_ADDRESS_DISP (XEXP (X, 0), XEXP (X, 1))) \
1600 /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
1601 use as a base register. */
1603 #ifdef REG_OK_STRICT
1604 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1606 #define REG_OK_FOR_BASE_P(X) \
1607 (GENERAL_REGNO_P (REGNO (X)) || (REGNO (X) >= FIRST_PSEUDO_REGISTER))
1610 /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
1611 use as an index register. This is needed for POST_MODIFY. */
1613 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1615 /* A C statement or compound statement with a conditional `goto LABEL;'
1616 executed if memory address X (an RTX) can have different meanings depending
1617 on the machine mode of the memory reference it is used for or if the address
1618 is valid for some modes but not others. */
1620 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1621 if (GET_CODE (ADDR) == POST_DEC || GET_CODE (ADDR) == POST_INC) \
1624 /* A C expression that is nonzero if X is a legitimate constant for an
1625 immediate operand on the target machine. */
1627 #define LEGITIMATE_CONSTANT_P(X) \
1628 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode \
1629 || GET_MODE (X) == DImode || CONST_DOUBLE_OK_FOR_G (X)) \
1632 /* Condition Code Status */
1634 /* One some machines not all possible comparisons are defined, but you can
1635 convert an invalid comparison into a valid one. */
1636 /* ??? Investigate. See the alpha definition. */
1637 /* #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) */
1640 /* Describing Relative Costs of Operations */
1642 /* A C expression for the cost of moving data from a register in class FROM to
1643 one in class TO, using MODE. */
1645 #define REGISTER_MOVE_COST ia64_register_move_cost
1647 /* A C expression for the cost of moving data of mode M between a
1648 register and memory. */
1649 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
1650 ((CLASS) == GENERAL_REGS || (CLASS) == FR_REGS \
1651 || (CLASS) == GR_AND_FR_REGS ? 4 : 10)
1653 /* A C expression for the cost of a branch instruction. A value of 1 is the
1654 default; other values are interpreted relative to that. Used by the
1655 if-conversion code as max instruction count. */
1656 /* ??? This requires investigation. The primary effect might be how
1657 many additional insn groups we run into, vs how good the dynamic
1658 branch predictor is. */
1660 #define BRANCH_COST 6
1662 /* Define this macro as a C expression which is nonzero if accessing less than
1663 a word of memory (i.e. a `char' or a `short') is no faster than accessing a
1666 #define SLOW_BYTE_ACCESS 1
1668 /* Define this macro if it is as good or better to call a constant function
1669 address than to call an address kept in a register.
1671 Indirect function calls are more expensive that direct function calls, so
1672 don't cse function addresses. */
1674 #define NO_FUNCTION_CSE
1677 /* Dividing the output into sections. */
1679 /* A C expression whose value is a string containing the assembler operation
1680 that should precede instructions and read-only data. */
1682 #define TEXT_SECTION_ASM_OP "\t.text"
1684 /* A C expression whose value is a string containing the assembler operation to
1685 identify the following data as writable initialized data. */
1687 #define DATA_SECTION_ASM_OP "\t.data"
1689 /* If defined, a C expression whose value is a string containing the assembler
1690 operation to identify the following data as uninitialized global data. */
1692 #define BSS_SECTION_ASM_OP "\t.bss"
1694 #define IA64_DEFAULT_GVALUE 8
1696 /* Position Independent Code. */
1698 /* The register number of the register used to address a table of static data
1699 addresses in memory. */
1701 /* ??? Should modify ia64.md to use pic_offset_table_rtx instead of
1702 gen_rtx_REG (DImode, 1). */
1704 /* ??? Should we set flag_pic? Probably need to define
1705 LEGITIMIZE_PIC_OPERAND_P to make that work. */
1707 #define PIC_OFFSET_TABLE_REGNUM GR_REG (1)
1709 /* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' is
1710 clobbered by calls. */
1712 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
1715 /* The Overall Framework of an Assembler File. */
1717 /* A C string constant describing how to begin a comment in the target
1718 assembler language. The compiler assumes that the comment will end at the
1721 #define ASM_COMMENT_START "//"
1723 /* A C string constant for text to be output before each `asm' statement or
1724 group of consecutive ones. */
1726 #define ASM_APP_ON (TARGET_GNU_AS ? "#APP\n" : "//APP\n")
1728 /* A C string constant for text to be output after each `asm' statement or
1729 group of consecutive ones. */
1731 #define ASM_APP_OFF (TARGET_GNU_AS ? "#NO_APP\n" : "//NO_APP\n")
1733 /* Output of Uninitialized Variables. */
1735 /* This is all handled by svr4.h. */
1738 /* Output and Generation of Labels. */
1740 /* A C statement (sans semicolon) to output to the stdio stream STREAM the
1741 assembler definition of a label named NAME. */
1743 /* See the ASM_OUTPUT_LABELREF definition in sysv4.h for an explanation of
1744 why ia64_asm_output_label exists. */
1746 extern int ia64_asm_output_label;
1747 #define ASM_OUTPUT_LABEL(STREAM, NAME) \
1749 ia64_asm_output_label = 1; \
1750 assemble_name (STREAM, NAME); \
1751 fputs (":\n", STREAM); \
1752 ia64_asm_output_label = 0; \
1755 /* Globalizing directive for a label. */
1756 #define GLOBAL_ASM_OP "\t.global "
1758 /* A C statement (sans semicolon) to output to the stdio stream STREAM any text
1759 necessary for declaring the name of an external symbol named NAME which is
1760 referenced in this compilation but not defined. */
1762 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
1763 ia64_asm_output_external (FILE, DECL, NAME)
1765 /* A C statement to store into the string STRING a label whose name is made
1766 from the string PREFIX and the number NUM. */
1768 #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \
1770 sprintf (LABEL, "*.%s%d", PREFIX, NUM); \
1773 /* ??? Not sure if using a ? in the name for Intel as is safe. */
1775 #define ASM_PN_FORMAT (TARGET_GNU_AS ? "%s.%lu" : "%s?%lu")
1777 /* A C statement to output to the stdio stream STREAM assembler code which
1778 defines (equates) the symbol NAME to have the value VALUE. */
1780 #define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \
1782 assemble_name (STREAM, NAME); \
1783 fputs (" = ", STREAM); \
1784 assemble_name (STREAM, VALUE); \
1785 fputc ('\n', STREAM); \
1789 /* Macros Controlling Initialization Routines. */
1791 /* This is handled by svr4.h and sysv4.h. */
1794 /* Output of Assembler Instructions. */
1796 /* A C initializer containing the assembler's names for the machine registers,
1797 each one as a C string constant. */
1799 #define REGISTER_NAMES \
1801 /* General registers. */ \
1802 "ap", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \
1803 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \
1804 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \
1806 /* Local registers. */ \
1807 "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7", \
1808 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15", \
1809 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23", \
1810 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31", \
1811 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39", \
1812 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47", \
1813 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55", \
1814 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63", \
1815 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71", \
1816 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79", \
1817 /* Input registers. */ \
1818 "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7", \
1819 /* Output registers. */ \
1820 "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7", \
1821 /* Floating-point registers. */ \
1822 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", \
1823 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", \
1824 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", \
1825 "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", \
1826 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", \
1827 "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", \
1828 "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69", \
1829 "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79", \
1830 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89", \
1831 "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99", \
1832 "f100","f101","f102","f103","f104","f105","f106","f107","f108","f109",\
1833 "f110","f111","f112","f113","f114","f115","f116","f117","f118","f119",\
1834 "f120","f121","f122","f123","f124","f125","f126","f127", \
1835 /* Predicate registers. */ \
1836 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", \
1837 "p10", "p11", "p12", "p13", "p14", "p15", "p16", "p17", "p18", "p19", \
1838 "p20", "p21", "p22", "p23", "p24", "p25", "p26", "p27", "p28", "p29", \
1839 "p30", "p31", "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39", \
1840 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47", "p48", "p49", \
1841 "p50", "p51", "p52", "p53", "p54", "p55", "p56", "p57", "p58", "p59", \
1842 "p60", "p61", "p62", "p63", \
1843 /* Branch registers. */ \
1844 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", \
1845 /* Frame pointer. Application registers. */ \
1846 "sfp", "ar.ccv", "ar.unat", "ar.pfs", "ar.lc", "ar.ec", \
1849 /* If defined, a C initializer for an array of structures containing a name and
1850 a register number. This macro defines additional names for hard registers,
1851 thus allowing the `asm' option in declarations to refer to registers using
1854 #define ADDITIONAL_REGISTER_NAMES \
1856 { "gp", R_GR (1) }, \
1857 { "sp", R_GR (12) }, \
1858 { "in0", IN_REG (0) }, \
1859 { "in1", IN_REG (1) }, \
1860 { "in2", IN_REG (2) }, \
1861 { "in3", IN_REG (3) }, \
1862 { "in4", IN_REG (4) }, \
1863 { "in5", IN_REG (5) }, \
1864 { "in6", IN_REG (6) }, \
1865 { "in7", IN_REG (7) }, \
1866 { "out0", OUT_REG (0) }, \
1867 { "out1", OUT_REG (1) }, \
1868 { "out2", OUT_REG (2) }, \
1869 { "out3", OUT_REG (3) }, \
1870 { "out4", OUT_REG (4) }, \
1871 { "out5", OUT_REG (5) }, \
1872 { "out6", OUT_REG (6) }, \
1873 { "out7", OUT_REG (7) }, \
1874 { "loc0", LOC_REG (0) }, \
1875 { "loc1", LOC_REG (1) }, \
1876 { "loc2", LOC_REG (2) }, \
1877 { "loc3", LOC_REG (3) }, \
1878 { "loc4", LOC_REG (4) }, \
1879 { "loc5", LOC_REG (5) }, \
1880 { "loc6", LOC_REG (6) }, \
1881 { "loc7", LOC_REG (7) }, \
1882 { "loc8", LOC_REG (8) }, \
1883 { "loc9", LOC_REG (9) }, \
1884 { "loc10", LOC_REG (10) }, \
1885 { "loc11", LOC_REG (11) }, \
1886 { "loc12", LOC_REG (12) }, \
1887 { "loc13", LOC_REG (13) }, \
1888 { "loc14", LOC_REG (14) }, \
1889 { "loc15", LOC_REG (15) }, \
1890 { "loc16", LOC_REG (16) }, \
1891 { "loc17", LOC_REG (17) }, \
1892 { "loc18", LOC_REG (18) }, \
1893 { "loc19", LOC_REG (19) }, \
1894 { "loc20", LOC_REG (20) }, \
1895 { "loc21", LOC_REG (21) }, \
1896 { "loc22", LOC_REG (22) }, \
1897 { "loc23", LOC_REG (23) }, \
1898 { "loc24", LOC_REG (24) }, \
1899 { "loc25", LOC_REG (25) }, \
1900 { "loc26", LOC_REG (26) }, \
1901 { "loc27", LOC_REG (27) }, \
1902 { "loc28", LOC_REG (28) }, \
1903 { "loc29", LOC_REG (29) }, \
1904 { "loc30", LOC_REG (30) }, \
1905 { "loc31", LOC_REG (31) }, \
1906 { "loc32", LOC_REG (32) }, \
1907 { "loc33", LOC_REG (33) }, \
1908 { "loc34", LOC_REG (34) }, \
1909 { "loc35", LOC_REG (35) }, \
1910 { "loc36", LOC_REG (36) }, \
1911 { "loc37", LOC_REG (37) }, \
1912 { "loc38", LOC_REG (38) }, \
1913 { "loc39", LOC_REG (39) }, \
1914 { "loc40", LOC_REG (40) }, \
1915 { "loc41", LOC_REG (41) }, \
1916 { "loc42", LOC_REG (42) }, \
1917 { "loc43", LOC_REG (43) }, \
1918 { "loc44", LOC_REG (44) }, \
1919 { "loc45", LOC_REG (45) }, \
1920 { "loc46", LOC_REG (46) }, \
1921 { "loc47", LOC_REG (47) }, \
1922 { "loc48", LOC_REG (48) }, \
1923 { "loc49", LOC_REG (49) }, \
1924 { "loc50", LOC_REG (50) }, \
1925 { "loc51", LOC_REG (51) }, \
1926 { "loc52", LOC_REG (52) }, \
1927 { "loc53", LOC_REG (53) }, \
1928 { "loc54", LOC_REG (54) }, \
1929 { "loc55", LOC_REG (55) }, \
1930 { "loc56", LOC_REG (56) }, \
1931 { "loc57", LOC_REG (57) }, \
1932 { "loc58", LOC_REG (58) }, \
1933 { "loc59", LOC_REG (59) }, \
1934 { "loc60", LOC_REG (60) }, \
1935 { "loc61", LOC_REG (61) }, \
1936 { "loc62", LOC_REG (62) }, \
1937 { "loc63", LOC_REG (63) }, \
1938 { "loc64", LOC_REG (64) }, \
1939 { "loc65", LOC_REG (65) }, \
1940 { "loc66", LOC_REG (66) }, \
1941 { "loc67", LOC_REG (67) }, \
1942 { "loc68", LOC_REG (68) }, \
1943 { "loc69", LOC_REG (69) }, \
1944 { "loc70", LOC_REG (70) }, \
1945 { "loc71", LOC_REG (71) }, \
1946 { "loc72", LOC_REG (72) }, \
1947 { "loc73", LOC_REG (73) }, \
1948 { "loc74", LOC_REG (74) }, \
1949 { "loc75", LOC_REG (75) }, \
1950 { "loc76", LOC_REG (76) }, \
1951 { "loc77", LOC_REG (77) }, \
1952 { "loc78", LOC_REG (78) }, \
1953 { "loc79", LOC_REG (79) }, \
1956 /* Emit a dtp-relative reference to a TLS variable. */
1959 #define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \
1960 ia64_output_dwarf_dtprel (FILE, SIZE, X)
1963 /* A C compound statement to output to stdio stream STREAM the assembler syntax
1964 for an instruction operand X. X is an RTL expression. */
1966 #define PRINT_OPERAND(STREAM, X, CODE) \
1967 ia64_print_operand (STREAM, X, CODE)
1969 /* A C expression which evaluates to true if CODE is a valid punctuation
1970 character for use in the `PRINT_OPERAND' macro. */
1972 /* ??? Keep this around for now, as we might need it later. */
1974 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1975 ((CODE) == '+' || (CODE) == ',')
1977 /* A C compound statement to output to stdio stream STREAM the assembler syntax
1978 for an instruction operand that is a memory reference whose address is X. X
1979 is an RTL expression. */
1981 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
1982 ia64_print_operand_address (STREAM, X)
1984 /* If defined, C string expressions to be used for the `%R', `%L', `%U', and
1985 `%I' options of `asm_fprintf' (see `final.c'). */
1987 #define REGISTER_PREFIX ""
1988 #define LOCAL_LABEL_PREFIX "."
1989 #define USER_LABEL_PREFIX ""
1990 #define IMMEDIATE_PREFIX ""
1993 /* Output of dispatch tables. */
1995 /* This macro should be provided on machines where the addresses in a dispatch
1996 table are relative to the table's own address. */
1998 /* ??? Depends on the pointer size. */
2000 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2003 fprintf (STREAM, "\tdata4 @pcrel(.L%d)\n", VALUE); \
2005 fprintf (STREAM, "\tdata8 @pcrel(.L%d)\n", VALUE); \
2008 /* This is how to output an element of a case-vector that is absolute.
2009 (Ia64 does not use such vectors, but we must define this macro anyway.) */
2011 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) abort ()
2013 /* Jump tables only need 8 byte alignment. */
2015 #define ADDR_VEC_ALIGN(ADDR_VEC) 3
2018 /* Assembler Commands for Exception Regions. */
2020 /* Select a format to encode pointers in exception handling data. CODE
2021 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2022 true if the symbol may be affected by dynamic relocations. */
2023 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2024 (((CODE) == 1 ? DW_EH_PE_textrel : DW_EH_PE_datarel) \
2025 | ((GLOBAL) ? DW_EH_PE_indirect : 0) \
2026 | (TARGET_ILP32 ? DW_EH_PE_udata4 : DW_EH_PE_udata8))
2028 /* Handle special EH pointer encodings. Absolute, pc-relative, and
2029 indirect are handled automatically. */
2030 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
2032 const char *reltag = NULL; \
2033 if (((ENCODING) & 0xF0) == DW_EH_PE_textrel) \
2034 reltag = "@segrel("; \
2035 else if (((ENCODING) & 0xF0) == DW_EH_PE_datarel) \
2036 reltag = "@gprel("; \
2039 fputs (integer_asm_op (SIZE, FALSE), FILE); \
2040 fputs (reltag, FILE); \
2041 assemble_name (FILE, XSTR (ADDR, 0)); \
2042 fputc (')', FILE); \
2048 /* Assembler Commands for Alignment. */
2050 /* ??? Investigate. */
2052 /* The alignment (log base 2) to put in front of LABEL, which follows
2055 /* #define LABEL_ALIGN_AFTER_BARRIER(LABEL) */
2057 /* The desired alignment for the location counter at the beginning
2060 /* #define LOOP_ALIGN(LABEL) */
2062 /* Define this macro if `ASM_OUTPUT_SKIP' should not be used in the text
2063 section because it fails put zeros in the bytes that are skipped. */
2065 #define ASM_NO_SKIP_IN_TEXT 1
2067 /* A C statement to output to the stdio stream STREAM an assembler command to
2068 advance the location counter to a multiple of 2 to the POWER bytes. */
2070 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
2071 fprintf (STREAM, "\t.align %d\n", 1<<(POWER))
2074 /* Macros Affecting all Debug Formats. */
2076 /* This is handled in svr4.h and sysv4.h. */
2079 /* Specific Options for DBX Output. */
2081 /* This is handled by dbxelf.h which is included by svr4.h. */
2084 /* Open ended Hooks for DBX Output. */
2089 /* File names in DBX format. */
2094 /* Macros for SDB and Dwarf Output. */
2096 /* Define this macro if GCC should produce dwarf version 2 format debugging
2097 output in response to the `-g' option. */
2099 #define DWARF2_DEBUGGING_INFO 1
2101 #define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DWARF2_ASM)
2103 /* Use tags for debug info labels, so that they don't break instruction
2104 bundles. This also avoids getting spurious DV warnings from the
2105 assembler. This is similar to (*targetm.asm_out.internal_label), except that we
2106 add brackets around the label. */
2108 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2109 fprintf (FILE, TARGET_GNU_AS ? "[.%s%d:]\n" : ".%s%d:\n", PREFIX, NUM)
2111 /* Use section-relative relocations for debugging offsets. Unlike other
2112 targets that fake this by putting the section VMA at 0, IA-64 has
2113 proper relocations for them. */
2114 #define ASM_OUTPUT_DWARF_OFFSET(FILE, SIZE, LABEL) \
2116 fputs (integer_asm_op (SIZE, FALSE), FILE); \
2117 fputs ("@secrel(", FILE); \
2118 assemble_name (FILE, LABEL); \
2119 fputc (')', FILE); \
2122 /* Emit a PC-relative relocation. */
2123 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
2125 fputs (integer_asm_op (SIZE, FALSE), FILE); \
2126 fputs ("@pcrel(", FILE); \
2127 assemble_name (FILE, LABEL); \
2128 fputc (')', FILE); \
2131 /* Register Renaming Parameters. */
2133 /* A C expression that is nonzero if hard register number REGNO2 can be
2134 considered for use as a rename register for REGNO1 */
2136 #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \
2137 ia64_hard_regno_rename_ok((REGNO1), (REGNO2))
2140 /* Miscellaneous Parameters. */
2142 /* Flag to mark data that is in the small address area (addressable
2143 via "addl", that is, within a 2MByte offset of 0. */
2144 #define SYMBOL_FLAG_SMALL_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2145 #define SYMBOL_REF_SMALL_ADDR_P(X) \
2146 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_SMALL_ADDR) != 0)
2148 /* An alias for a machine mode name. This is the machine mode that elements of
2149 a jump-table should have. */
2151 #define CASE_VECTOR_MODE ptr_mode
2153 /* Define as C expression which evaluates to nonzero if the tablejump
2154 instruction expects the table to contain offsets from the address of the
2157 #define CASE_VECTOR_PC_RELATIVE 1
2159 /* Define this macro if operations between registers with integral mode smaller
2160 than a word are always performed on the entire register. */
2162 #define WORD_REGISTER_OPERATIONS
2164 /* Define this macro to be a C expression indicating when insns that read
2165 memory in MODE, an integral mode narrower than a word, set the bits outside
2166 of MODE to be either the sign-extension or the zero-extension of the data
2169 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2171 /* The maximum number of bytes that a single instruction can move quickly from
2172 memory to memory. */
2175 /* A C expression which is nonzero if on this machine it is safe to "convert"
2176 an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller
2177 than INPREC) by merely operating on it as if it had only OUTPREC bits. */
2179 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2181 /* A C expression describing the value returned by a comparison operator with
2182 an integral mode and stored by a store-flag instruction (`sCOND') when the
2183 condition is true. */
2185 /* ??? Investigate using STORE_FLAG_VALUE of -1 instead of 1. */
2187 /* An alias for the machine mode for pointers. */
2189 /* ??? This would change if we had ILP32 support. */
2191 #define Pmode DImode
2193 /* An alias for the machine mode used for memory references to functions being
2194 called, in `call' RTL expressions. */
2196 #define FUNCTION_MODE Pmode
2198 /* Define this macro to handle System V style pragmas: #pragma pack and
2199 #pragma weak. Note, #pragma weak will only be supported if SUPPORT_WEAK is
2202 /* If this architecture supports prefetch, define this to be the number of
2203 prefetch commands that can be executed in parallel.
2205 ??? This number is bogus and needs to be replaced before the value is
2206 actually used in optimizations. */
2208 #define SIMULTANEOUS_PREFETCHES 6
2210 /* If this architecture supports prefetch, define this to be the size of
2211 the cache line that is prefetched. */
2213 #define PREFETCH_BLOCK 32
2215 #define HANDLE_SYSV_PRAGMA 1
2217 /* A C expression for the maximum number of instructions to execute via
2218 conditional execution instructions instead of a branch. A value of
2219 BRANCH_COST+1 is the default if the machine does not use
2220 cc0, and 1 if it does use cc0. */
2221 /* ??? Investigate. */
2222 #define MAX_CONDITIONAL_EXECUTE 12
2224 extern int ia64_final_schedule;
2226 #define TARGET_UNWIND_INFO 1
2228 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 15 : INVALID_REGNUM)
2230 /* This function contains machine specific function data. */
2231 struct machine_function GTY(())
2233 /* The new stack pointer when unwinding from EH. */
2234 rtx ia64_eh_epilogue_sp;
2236 /* The new bsp value when unwinding from EH. */
2237 rtx ia64_eh_epilogue_bsp;
2239 /* The GP value save register. */
2242 /* The number of varargs registers to save. */
2249 IA64_BUILTIN_SYNCHRONIZE,
2251 IA64_BUILTIN_FETCH_AND_ADD_SI,
2252 IA64_BUILTIN_FETCH_AND_SUB_SI,
2253 IA64_BUILTIN_FETCH_AND_OR_SI,
2254 IA64_BUILTIN_FETCH_AND_AND_SI,
2255 IA64_BUILTIN_FETCH_AND_XOR_SI,
2256 IA64_BUILTIN_FETCH_AND_NAND_SI,
2258 IA64_BUILTIN_ADD_AND_FETCH_SI,
2259 IA64_BUILTIN_SUB_AND_FETCH_SI,
2260 IA64_BUILTIN_OR_AND_FETCH_SI,
2261 IA64_BUILTIN_AND_AND_FETCH_SI,
2262 IA64_BUILTIN_XOR_AND_FETCH_SI,
2263 IA64_BUILTIN_NAND_AND_FETCH_SI,
2265 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI,
2266 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI,
2268 IA64_BUILTIN_SYNCHRONIZE_SI,
2270 IA64_BUILTIN_LOCK_TEST_AND_SET_SI,
2272 IA64_BUILTIN_LOCK_RELEASE_SI,
2274 IA64_BUILTIN_FETCH_AND_ADD_DI,
2275 IA64_BUILTIN_FETCH_AND_SUB_DI,
2276 IA64_BUILTIN_FETCH_AND_OR_DI,
2277 IA64_BUILTIN_FETCH_AND_AND_DI,
2278 IA64_BUILTIN_FETCH_AND_XOR_DI,
2279 IA64_BUILTIN_FETCH_AND_NAND_DI,
2281 IA64_BUILTIN_ADD_AND_FETCH_DI,
2282 IA64_BUILTIN_SUB_AND_FETCH_DI,
2283 IA64_BUILTIN_OR_AND_FETCH_DI,
2284 IA64_BUILTIN_AND_AND_FETCH_DI,
2285 IA64_BUILTIN_XOR_AND_FETCH_DI,
2286 IA64_BUILTIN_NAND_AND_FETCH_DI,
2288 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI,
2289 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI,
2291 IA64_BUILTIN_SYNCHRONIZE_DI,
2293 IA64_BUILTIN_LOCK_TEST_AND_SET_DI,
2295 IA64_BUILTIN_LOCK_RELEASE_DI,
2298 IA64_BUILTIN_FLUSHRS
2301 /* Codes for expand_compare_and_swap and expand_swap_and_compare. */
2303 IA64_ADD_OP, IA64_SUB_OP, IA64_OR_OP, IA64_AND_OP, IA64_XOR_OP, IA64_NAND_OP
2306 #define DONT_USE_BUILTIN_SETJMP
2308 /* Output any profiling code before the prologue. */
2310 #undef PROFILE_BEFORE_PROLOGUE
2311 #define PROFILE_BEFORE_PROLOGUE 1
2313 /* Initialize library function table. */
2314 #undef TARGET_INIT_LIBFUNCS
2315 #define TARGET_INIT_LIBFUNCS ia64_init_libfuncs
2319 /* Switch on code for querying unit reservations. */
2320 #define CPU_UNITS_QUERY 1
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