1 /* Definitions of target machine GNU compiler. IA-64 version.
2 Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
3 Contributed by James E. Wilson <wilson@cygnus.com> and
4 David Mosberger <davidm@hpl.hp.com>.
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 /* ??? Look at ABI group documents for list of preprocessor macros and
24 other features required for ABI compliance. */
26 /* ??? Functions containing a non-local goto target save many registers. Why?
27 See for instance execute/920428-2.c. */
29 /* ??? Add support for short data/bss sections. */
32 /* Run-time target specifications */
34 #define CPP_CPU_SPEC "\
35 -Acpu=ia64 -Amachine=ia64 \
36 %{!ansi:%{!std=c*:%{!std=i*:-Dia64}}} -D__ia64 -D__ia64__"
38 #define CC1_SPEC "%(cc1_cpu) "
40 /* This declaration should be present. */
41 extern int target_flags;
43 /* This series of macros is to allow compiler command arguments to enable or
44 disable the use of optional features of the target machine. */
46 #define MASK_BIG_ENDIAN 0x00000001 /* Generate big endian code. */
48 #define MASK_GNU_AS 0x00000002 /* Generate code for GNU as. */
50 #define MASK_GNU_LD 0x00000004 /* Generate code for GNU ld. */
52 #define MASK_NO_PIC 0x00000008 /* Generate code without GP reg. */
54 #define MASK_VOL_ASM_STOP 0x00000010 /* Emit stop bits for vol ext asm. */
56 #define MASK_ILP32 0x00000020 /* Generate ILP32 code. */
58 #define MASK_B_STEP 0x00000040 /* Emit code for Itanium B step. */
60 #define MASK_REG_NAMES 0x00000080 /* Use in/loc/out register names. */
62 #define MASK_NO_SDATA 0x00000100 /* Disable sdata/scommon/sbss. */
64 #define MASK_CONST_GP 0x00000200 /* treat gp as program-wide constant */
66 #define MASK_AUTO_PIC 0x00000400 /* generate automatically PIC */
68 #define MASK_INLINE_DIV_LAT 0x00000800 /* inline div, min latency. */
70 #define MASK_INLINE_DIV_THR 0x00001000 /* inline div, max throughput. */
72 #define MASK_DWARF2_ASM 0x40000000 /* test dwarf2 line info via gas. */
74 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
76 #define TARGET_GNU_AS (target_flags & MASK_GNU_AS)
78 #define TARGET_GNU_LD (target_flags & MASK_GNU_LD)
80 #define TARGET_NO_PIC (target_flags & MASK_NO_PIC)
82 #define TARGET_VOL_ASM_STOP (target_flags & MASK_VOL_ASM_STOP)
84 #define TARGET_ILP32 (target_flags & MASK_ILP32)
86 #define TARGET_B_STEP (target_flags & MASK_B_STEP)
88 #define TARGET_REG_NAMES (target_flags & MASK_REG_NAMES)
90 #define TARGET_NO_SDATA (target_flags & MASK_NO_SDATA)
92 #define TARGET_CONST_GP (target_flags & MASK_CONST_GP)
94 #define TARGET_AUTO_PIC (target_flags & MASK_AUTO_PIC)
96 #define TARGET_INLINE_DIV_LAT (target_flags & MASK_INLINE_DIV_LAT)
98 #define TARGET_INLINE_DIV_THR (target_flags & MASK_INLINE_DIV_THR)
100 #define TARGET_INLINE_DIV \
101 (target_flags & (MASK_INLINE_DIV_LAT | MASK_INLINE_DIV_THR))
103 #define TARGET_DWARF2_ASM (target_flags & MASK_DWARF2_ASM)
105 /* This macro defines names of command options to set and clear bits in
106 `target_flags'. Its definition is an initializer with a subgrouping for
107 each command option. */
109 #define TARGET_SWITCHES \
111 { "big-endian", MASK_BIG_ENDIAN, \
112 N_("Generate big endian code") }, \
113 { "little-endian", -MASK_BIG_ENDIAN, \
114 N_("Generate little endian code") }, \
115 { "gnu-as", MASK_GNU_AS, \
116 N_("Generate code for GNU as") }, \
117 { "no-gnu-as", -MASK_GNU_AS, \
118 N_("Generate code for Intel as") }, \
119 { "gnu-ld", MASK_GNU_LD, \
120 N_("Generate code for GNU ld") }, \
121 { "no-gnu-ld", -MASK_GNU_LD, \
122 N_("Generate code for Intel ld") }, \
123 { "no-pic", MASK_NO_PIC, \
124 N_("Generate code without GP reg") }, \
125 { "volatile-asm-stop", MASK_VOL_ASM_STOP, \
126 N_("Emit stop bits before and after volatile extended asms") }, \
127 { "no-volatile-asm-stop", -MASK_VOL_ASM_STOP, \
128 N_("Don't emit stop bits before and after volatile extended asms") }, \
129 { "b-step", MASK_B_STEP, \
130 N_("Emit code for Itanium (TM) processor B step")}, \
131 { "register-names", MASK_REG_NAMES, \
132 N_("Use in/loc/out register names")}, \
133 { "no-sdata", MASK_NO_SDATA, \
134 N_("Disable use of sdata/scommon/sbss")}, \
135 { "sdata", -MASK_NO_SDATA, \
136 N_("Enable use of sdata/scommon/sbss")}, \
137 { "constant-gp", MASK_CONST_GP, \
138 N_("gp is constant (but save/restore gp on indirect calls)") }, \
139 { "auto-pic", MASK_AUTO_PIC, \
140 N_("Generate self-relocatable code") }, \
141 { "inline-divide-min-latency", MASK_INLINE_DIV_LAT, \
142 N_("Generate inline division, optimize for latency") }, \
143 { "inline-divide-max-throughput", MASK_INLINE_DIV_THR, \
144 N_("Generate inline division, optimize for throughput") }, \
145 { "dwarf2-asm", MASK_DWARF2_ASM, \
146 N_("Enable Dwarf 2 line debug info via GNU as")}, \
147 { "no-dwarf2-asm", -MASK_DWARF2_ASM, \
148 N_("Disable Dwarf 2 line debug info via GNU as")}, \
150 { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT, \
154 /* Default target_flags if no switches are specified */
156 #ifndef TARGET_DEFAULT
157 #define TARGET_DEFAULT MASK_DWARF2_ASM
160 #ifndef TARGET_CPU_DEFAULT
161 #define TARGET_CPU_DEFAULT 0
164 #ifndef SUBTARGET_SWITCHES
165 #define SUBTARGET_SWITCHES
168 /* This macro is similar to `TARGET_SWITCHES' but defines names of command
169 options that have values. Its definition is an initializer with a
170 subgrouping for each command option. */
172 extern const char *ia64_fixed_range_string;
173 #define TARGET_OPTIONS \
175 { "fixed-range=", &ia64_fixed_range_string, \
176 N_("Specify range of registers to make fixed")}, \
179 /* Sometimes certain combinations of command options do not make sense on a
180 particular target machine. You can define a macro `OVERRIDE_OPTIONS' to
181 take account of this. This macro, if defined, is executed once just after
182 all the command options have been parsed. */
184 #define OVERRIDE_OPTIONS ia64_override_options ()
186 /* Some machines may desire to change what optimizations are performed for
187 various optimization levels. This macro, if defined, is executed once just
188 after the optimization level is determined and before the remainder of the
189 command options have been parsed. Values set in this macro are used as the
190 default values for the other command line options. */
192 /* #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) */
194 /* Driver configuration */
196 /* A C string constant that tells the GNU CC driver program options to pass to
197 CPP. It can also specify how to translate options you give to GNU CC into
198 options for GNU CC to pass to the CPP. */
200 /* ??? __LONG_MAX__ depends on LP64/ILP32 switch. */
201 /* ??? An alternative is to modify glimits.h to check for __LP64__ instead
202 of checked for CPU specific defines. We could also get rid of all LONG_MAX
203 defines in other tm.h files. */
205 "%{mcpu=itanium:-D__itanium__} %{mbig-endian:-D__BIG_ENDIAN__} \
206 -D__LONG_MAX__=9223372036854775807L"
208 /* This is always "long" so it doesn't "change" in ILP32 vs. LP64. */
209 /* #define NO_BUILTIN_SIZE_TYPE */
211 /* This is always "long" so it doesn't "change" in ILP32 vs. LP64. */
212 /* #define NO_BUILTIN_PTRDIFF_TYPE */
214 /* A C string constant that tells the GNU CC driver program options to pass to
215 `cc1'. It can also specify how to translate options you give to GNU CC into
216 options for GNU CC to pass to the `cc1'. */
219 #define CC1_SPEC "%{G*}"
221 /* A C string constant that tells the GNU CC driver program options to pass to
222 `cc1plus'. It can also specify how to translate options you give to GNU CC
223 into options for GNU CC to pass to the `cc1plus'. */
225 /* #define CC1PLUS_SPEC "" */
229 /* Define this macro to have the value 1 if the most significant bit in a byte
230 has the lowest number; otherwise define it to have the value zero. */
232 #define BITS_BIG_ENDIAN 0
234 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
236 /* Define this macro to have the value 1 if, in a multiword object, the most
237 significant word has the lowest number. */
239 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
241 #if defined(__BIG_ENDIAN__)
242 #define LIBGCC2_WORDS_BIG_ENDIAN 1
244 #define LIBGCC2_WORDS_BIG_ENDIAN 0
247 #define UNITS_PER_WORD 8
249 #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64)
251 /* A C expression whose value is zero if pointers that need to be extended
252 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and one if
253 they are zero-extended and negative one if there is an ptr_extend operation.
255 You need not define this macro if the `POINTER_SIZE' is equal to the width
257 /* Need this for 32 bit pointers, see hpux.h for setting it. */
258 /* #define POINTERS_EXTEND_UNSIGNED */
260 /* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and
261 which has the specified mode and signedness is to be stored in a register.
262 This macro is only called when TYPE is a scalar type. */
263 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
266 if (GET_MODE_CLASS (MODE) == MODE_INT \
267 && GET_MODE_SIZE (MODE) < 4) \
272 /* ??? ABI doesn't allow us to define this. */
273 /* #define PROMOTE_FUNCTION_ARGS */
275 /* ??? ABI doesn't allow us to define this. */
276 /* #define PROMOTE_FUNCTION_RETURN */
278 #define PARM_BOUNDARY 64
280 /* Define this macro if you wish to preserve a certain alignment for the stack
281 pointer. The definition is a C expression for the desired alignment
282 (measured in bits). */
284 #define STACK_BOUNDARY 128
286 /* Align frames on double word boundaries */
287 #ifndef IA64_STACK_ALIGN
288 #define IA64_STACK_ALIGN(LOC) (((LOC) + 15) & ~15)
291 #define FUNCTION_BOUNDARY 128
293 /* Optional x86 80-bit float, quad-precision 128-bit float, and quad-word
294 128 bit integers all require 128 bit alignment. */
295 #define BIGGEST_ALIGNMENT 128
297 /* If defined, a C expression to compute the alignment for a static variable.
298 TYPE is the data type, and ALIGN is the alignment that the object
299 would ordinarily have. The value of this macro is used instead of that
300 alignment to align the object. */
302 #define DATA_ALIGNMENT(TYPE, ALIGN) \
303 (TREE_CODE (TYPE) == ARRAY_TYPE \
304 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
305 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
307 /* If defined, a C expression to compute the alignment given to a constant that
308 is being placed in memory. CONSTANT is the constant and ALIGN is the
309 alignment that the object would ordinarily have. The value of this macro is
310 used instead of that alignment to align the object. */
312 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
313 (TREE_CODE (EXP) == STRING_CST \
314 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
316 #define STRICT_ALIGNMENT 1
318 /* Define this if you wish to imitate the way many other C compilers handle
319 alignment of bitfields and the structures that contain them.
320 The behavior is that the type written for a bitfield (`int', `short', or
321 other integer type) imposes an alignment for the entire structure, as if the
322 structure really did contain an ordinary field of that type. In addition,
323 the bitfield is placed within the structure so that it would fit within such
324 a field, not crossing a boundary for it. */
325 #define PCC_BITFIELD_TYPE_MATTERS 1
327 /* An integer expression for the size in bits of the largest integer machine
328 mode that should actually be used. */
330 /* Allow pairs of registers to be used, which is the intent of the default. */
331 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
333 /* A code distinguishing the floating point format of the target machine. */
334 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
336 /* By default, the C++ compiler will use function addresses in the
337 vtable entries. Setting this non-zero tells the compiler to use
338 function descriptors instead. The value of this macro says how
339 many words wide the descriptor is (normally 2). It is assumed
340 that the address of a function descriptor may be treated as a
341 pointer to a function. */
342 #define TARGET_VTABLE_USES_DESCRIPTORS 2
344 /* Layout of Source Language Data Types */
346 #define INT_TYPE_SIZE 32
348 #define SHORT_TYPE_SIZE 16
350 #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64)
352 #define MAX_LONG_TYPE_SIZE 64
354 #define LONG_LONG_TYPE_SIZE 64
356 #define FLOAT_TYPE_SIZE 32
358 #define DOUBLE_TYPE_SIZE 64
360 #define LONG_DOUBLE_TYPE_SIZE 128
362 /* Tell real.c that this is the 80-bit Intel extended float format
363 packaged in a 128-bit entity. */
365 #define INTEL_EXTENDED_IEEE_FORMAT 1
367 #define DEFAULT_SIGNED_CHAR 1
369 /* A C expression for a string describing the name of the data type to use for
370 size values. The typedef name `size_t' is defined using the contents of the
372 /* ??? Needs to be defined for P64 code. */
373 /* #define SIZE_TYPE */
375 /* A C expression for a string describing the name of the data type to use for
376 the result of subtracting two pointers. The typedef name `ptrdiff_t' is
377 defined using the contents of the string. See `SIZE_TYPE' above for more
379 /* ??? Needs to be defined for P64 code. */
380 /* #define PTRDIFF_TYPE */
382 /* A C expression for a string describing the name of the data type to use for
383 wide characters. The typedef name `wchar_t' is defined using the contents
384 of the string. See `SIZE_TYPE' above for more information. */
385 /* #define WCHAR_TYPE */
387 /* A C expression for the size in bits of the data type for wide characters.
388 This is used in `cpp', which cannot make use of `WCHAR_TYPE'. */
389 /* #define WCHAR_TYPE_SIZE */
392 /* Register Basics */
394 /* Number of hardware registers known to the compiler.
395 We have 128 general registers, 128 floating point registers,
396 64 predicate registers, 8 branch registers, one frame pointer,
397 and several "application" registers. */
399 #define FIRST_PSEUDO_REGISTER 335
401 /* Ranges for the various kinds of registers. */
402 #define ADDL_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 3)
403 #define GR_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 127)
404 #define FR_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 255)
405 #define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319)
406 #define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327)
407 #define GENERAL_REGNO_P(REGNO) \
408 (GR_REGNO_P (REGNO) \
409 || (REGNO) == FRAME_POINTER_REGNUM \
410 || (REGNO) == RETURN_ADDRESS_POINTER_REGNUM)
412 #define GR_REG(REGNO) ((REGNO) + 0)
413 #define FR_REG(REGNO) ((REGNO) + 128)
414 #define PR_REG(REGNO) ((REGNO) + 256)
415 #define BR_REG(REGNO) ((REGNO) + 320)
416 #define OUT_REG(REGNO) ((REGNO) + 120)
417 #define IN_REG(REGNO) ((REGNO) + 112)
418 #define LOC_REG(REGNO) ((REGNO) + 32)
420 #define AR_CCV_REGNUM 330
421 #define AR_UNAT_REGNUM 331
422 #define AR_PFS_REGNUM 332
423 #define AR_LC_REGNUM 333
424 #define AR_EC_REGNUM 334
426 #define IN_REGNO_P(REGNO) ((REGNO) >= IN_REG (0) && (REGNO) <= IN_REG (7))
427 #define LOC_REGNO_P(REGNO) ((REGNO) >= LOC_REG (0) && (REGNO) <= LOC_REG (79))
428 #define OUT_REGNO_P(REGNO) ((REGNO) >= OUT_REG (0) && (REGNO) <= OUT_REG (7))
430 #define AR_M_REGNO_P(REGNO) ((REGNO) == AR_CCV_REGNUM \
431 || (REGNO) == AR_UNAT_REGNUM)
432 #define AR_I_REGNO_P(REGNO) ((REGNO) >= AR_PFS_REGNUM \
433 && (REGNO) < FIRST_PSEUDO_REGISTER)
434 #define AR_REGNO_P(REGNO) ((REGNO) >= AR_CCV_REGNUM \
435 && (REGNO) < FIRST_PSEUDO_REGISTER)
438 /* ??? Don't really need two sets of macros. I like this one better because
439 it is less typing. */
440 #define R_GR(REGNO) GR_REG (REGNO)
441 #define R_FR(REGNO) FR_REG (REGNO)
442 #define R_PR(REGNO) PR_REG (REGNO)
443 #define R_BR(REGNO) BR_REG (REGNO)
445 /* An initializer that says which registers are used for fixed purposes all
446 throughout the compiled code and are therefore not available for general
450 r1: global pointer (gp)
451 r12: stack pointer (sp)
452 r13: thread pointer (tp)
456 fp: eliminable frame pointer */
458 /* The last 16 stacked regs are reserved for the 8 input and 8 output
461 #define FIXED_REGISTERS \
462 { /* General registers. */ \
463 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \
464 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
465 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
466 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
467 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
468 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
469 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
470 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
471 /* Floating-point registers. */ \
472 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
473 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
474 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
475 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
476 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
477 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
478 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
479 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
480 /* Predicate registers. */ \
481 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
482 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
483 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
484 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
485 /* Branch registers. */ \
486 0, 0, 0, 0, 0, 0, 0, 0, \
487 /*FP RA CCV UNAT PFS LC EC */ \
488 1, 1, 1, 1, 1, 0, 1 \
491 /* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered
492 (in general) by function calls as well as for fixed registers. This
493 macro therefore identifies the registers that are not available for
494 general allocation of values that must live across function calls. */
496 #define CALL_USED_REGISTERS \
497 { /* General registers. */ \
498 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
499 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
500 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
501 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
502 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
503 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
504 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
505 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
506 /* Floating-point registers. */ \
507 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
508 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
509 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
510 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
511 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
512 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
513 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
514 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
515 /* Predicate registers. */ \
516 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
517 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
518 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
519 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
520 /* Branch registers. */ \
521 1, 0, 0, 0, 0, 0, 1, 1, \
522 /*FP RA CCV UNAT PFS LC EC */ \
523 1, 1, 1, 1, 1, 0, 1 \
526 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
527 problem which makes CALL_USED_REGISTERS *always* include
528 all the FIXED_REGISTERS. Until this problem has been
529 resolved this macro can be used to overcome this situation.
530 In particular, block_propagate() requires this list
531 be acurate, or we can remove registers which should be live.
532 This macro is used in regs_invalidated_by_call. */
534 #define CALL_REALLY_USED_REGISTERS \
535 { /* General registers. */ \
536 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, \
537 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
538 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
539 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
540 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
541 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
542 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
543 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
544 /* Floating-point registers. */ \
545 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
546 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
547 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
548 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
549 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
550 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
551 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
552 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
553 /* Predicate registers. */ \
554 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
555 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
556 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
557 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
558 /* Branch registers. */ \
559 1, 0, 0, 0, 0, 0, 1, 1, \
560 /*FP RA CCV UNAT PFS LC EC */ \
561 0, 0, 1, 0, 1, 0, 0 \
565 /* Define this macro if the target machine has register windows. This C
566 expression returns the register number as seen by the called function
567 corresponding to the register number OUT as seen by the calling function.
568 Return OUT if register number OUT is not an outbound register. */
570 #define INCOMING_REGNO(OUT) \
571 ((unsigned) ((OUT) - OUT_REG (0)) < 8 ? IN_REG ((OUT) - OUT_REG (0)) : (OUT))
573 /* Define this macro if the target machine has register windows. This C
574 expression returns the register number as seen by the calling function
575 corresponding to the register number IN as seen by the called function.
576 Return IN if register number IN is not an inbound register. */
578 #define OUTGOING_REGNO(IN) \
579 ((unsigned) ((IN) - IN_REG (0)) < 8 ? OUT_REG ((IN) - IN_REG (0)) : (IN))
581 /* Define this macro if the target machine has register windows. This
582 C expression returns true if the register is call-saved but is in the
585 #define LOCAL_REGNO(REGNO) \
586 (IN_REGNO_P (REGNO) || LOC_REGNO_P (REGNO))
588 /* Add any extra modes needed to represent the condition code.
590 CCImode is used to mark a single predicate register instead
591 of a register pair. This is currently only used in reg_raw_mode
592 so that flow doesn't do something stupid. */
594 #define EXTRA_CC_MODES CC(CCImode, "CCI")
596 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
597 return the mode to be used for the comparison. Must be defined if
598 EXTRA_CC_MODES is defined. */
600 #define SELECT_CC_MODE(OP,X,Y) CCmode
602 /* Order of allocation of registers */
604 /* If defined, an initializer for a vector of integers, containing the numbers
605 of hard registers in the order in which GNU CC should prefer to use them
606 (from most preferred to least).
608 If this macro is not defined, registers are used lowest numbered first (all
611 One use of this macro is on machines where the highest numbered registers
612 must always be saved and the save-multiple-registers instruction supports
613 only sequences of consecutive registers. On such machines, define
614 `REG_ALLOC_ORDER' to be an initializer that lists the highest numbered
615 allocatable register first. */
617 /* ??? Should the GR return value registers come before or after the rest
618 of the caller-save GRs? */
620 #define REG_ALLOC_ORDER \
622 /* Caller-saved general registers. */ \
623 R_GR (14), R_GR (15), R_GR (16), R_GR (17), \
624 R_GR (18), R_GR (19), R_GR (20), R_GR (21), R_GR (22), R_GR (23), \
625 R_GR (24), R_GR (25), R_GR (26), R_GR (27), R_GR (28), R_GR (29), \
626 R_GR (30), R_GR (31), \
627 /* Output registers. */ \
628 R_GR (120), R_GR (121), R_GR (122), R_GR (123), R_GR (124), R_GR (125), \
629 R_GR (126), R_GR (127), \
630 /* Caller-saved general registers, also used for return values. */ \
631 R_GR (8), R_GR (9), R_GR (10), R_GR (11), \
632 /* addl caller-saved general registers. */ \
633 R_GR (2), R_GR (3), \
634 /* Caller-saved FP registers. */ \
635 R_FR (6), R_FR (7), \
636 /* Caller-saved FP registers, used for parameters and return values. */ \
637 R_FR (8), R_FR (9), R_FR (10), R_FR (11), \
638 R_FR (12), R_FR (13), R_FR (14), R_FR (15), \
639 /* Rotating caller-saved FP registers. */ \
640 R_FR (32), R_FR (33), R_FR (34), R_FR (35), \
641 R_FR (36), R_FR (37), R_FR (38), R_FR (39), R_FR (40), R_FR (41), \
642 R_FR (42), R_FR (43), R_FR (44), R_FR (45), R_FR (46), R_FR (47), \
643 R_FR (48), R_FR (49), R_FR (50), R_FR (51), R_FR (52), R_FR (53), \
644 R_FR (54), R_FR (55), R_FR (56), R_FR (57), R_FR (58), R_FR (59), \
645 R_FR (60), R_FR (61), R_FR (62), R_FR (63), R_FR (64), R_FR (65), \
646 R_FR (66), R_FR (67), R_FR (68), R_FR (69), R_FR (70), R_FR (71), \
647 R_FR (72), R_FR (73), R_FR (74), R_FR (75), R_FR (76), R_FR (77), \
648 R_FR (78), R_FR (79), R_FR (80), R_FR (81), R_FR (82), R_FR (83), \
649 R_FR (84), R_FR (85), R_FR (86), R_FR (87), R_FR (88), R_FR (89), \
650 R_FR (90), R_FR (91), R_FR (92), R_FR (93), R_FR (94), R_FR (95), \
651 R_FR (96), R_FR (97), R_FR (98), R_FR (99), R_FR (100), R_FR (101), \
652 R_FR (102), R_FR (103), R_FR (104), R_FR (105), R_FR (106), R_FR (107), \
653 R_FR (108), R_FR (109), R_FR (110), R_FR (111), R_FR (112), R_FR (113), \
654 R_FR (114), R_FR (115), R_FR (116), R_FR (117), R_FR (118), R_FR (119), \
655 R_FR (120), R_FR (121), R_FR (122), R_FR (123), R_FR (124), R_FR (125), \
656 R_FR (126), R_FR (127), \
657 /* Caller-saved predicate registers. */ \
658 R_PR (6), R_PR (7), R_PR (8), R_PR (9), R_PR (10), R_PR (11), \
659 R_PR (12), R_PR (13), R_PR (14), R_PR (15), \
660 /* Rotating caller-saved predicate registers. */ \
661 R_PR (16), R_PR (17), \
662 R_PR (18), R_PR (19), R_PR (20), R_PR (21), R_PR (22), R_PR (23), \
663 R_PR (24), R_PR (25), R_PR (26), R_PR (27), R_PR (28), R_PR (29), \
664 R_PR (30), R_PR (31), R_PR (32), R_PR (33), R_PR (34), R_PR (35), \
665 R_PR (36), R_PR (37), R_PR (38), R_PR (39), R_PR (40), R_PR (41), \
666 R_PR (42), R_PR (43), R_PR (44), R_PR (45), R_PR (46), R_PR (47), \
667 R_PR (48), R_PR (49), R_PR (50), R_PR (51), R_PR (52), R_PR (53), \
668 R_PR (54), R_PR (55), R_PR (56), R_PR (57), R_PR (58), R_PR (59), \
669 R_PR (60), R_PR (61), R_PR (62), R_PR (63), \
670 /* Caller-saved branch registers. */ \
671 R_BR (6), R_BR (7), \
673 /* Stacked callee-saved general registers. */ \
674 R_GR (32), R_GR (33), R_GR (34), R_GR (35), \
675 R_GR (36), R_GR (37), R_GR (38), R_GR (39), R_GR (40), R_GR (41), \
676 R_GR (42), R_GR (43), R_GR (44), R_GR (45), R_GR (46), R_GR (47), \
677 R_GR (48), R_GR (49), R_GR (50), R_GR (51), R_GR (52), R_GR (53), \
678 R_GR (54), R_GR (55), R_GR (56), R_GR (57), R_GR (58), R_GR (59), \
679 R_GR (60), R_GR (61), R_GR (62), R_GR (63), R_GR (64), R_GR (65), \
680 R_GR (66), R_GR (67), R_GR (68), R_GR (69), R_GR (70), R_GR (71), \
681 R_GR (72), R_GR (73), R_GR (74), R_GR (75), R_GR (76), R_GR (77), \
682 R_GR (78), R_GR (79), R_GR (80), R_GR (81), R_GR (82), R_GR (83), \
683 R_GR (84), R_GR (85), R_GR (86), R_GR (87), R_GR (88), R_GR (89), \
684 R_GR (90), R_GR (91), R_GR (92), R_GR (93), R_GR (94), R_GR (95), \
685 R_GR (96), R_GR (97), R_GR (98), R_GR (99), R_GR (100), R_GR (101), \
686 R_GR (102), R_GR (103), R_GR (104), R_GR (105), R_GR (106), R_GR (107), \
688 /* Input registers. */ \
689 R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (116), R_GR (117), \
690 R_GR (118), R_GR (119), \
691 /* Callee-saved general registers. */ \
692 R_GR (4), R_GR (5), R_GR (6), R_GR (7), \
693 /* Callee-saved FP registers. */ \
694 R_FR (2), R_FR (3), R_FR (4), R_FR (5), R_FR (16), R_FR (17), \
695 R_FR (18), R_FR (19), R_FR (20), R_FR (21), R_FR (22), R_FR (23), \
696 R_FR (24), R_FR (25), R_FR (26), R_FR (27), R_FR (28), R_FR (29), \
697 R_FR (30), R_FR (31), \
698 /* Callee-saved predicate registers. */ \
699 R_PR (1), R_PR (2), R_PR (3), R_PR (4), R_PR (5), \
700 /* Callee-saved branch registers. */ \
701 R_BR (1), R_BR (2), R_BR (3), R_BR (4), R_BR (5), \
703 /* ??? Stacked registers reserved for fp, rp, and ar.pfs. */ \
704 R_GR (109), R_GR (110), R_GR (111), \
706 /* Special general registers. */ \
707 R_GR (0), R_GR (1), R_GR (12), R_GR (13), \
708 /* Special FP registers. */ \
709 R_FR (0), R_FR (1), \
710 /* Special predicate registers. */ \
712 /* Special branch registers. */ \
714 /* Other fixed registers. */ \
715 FRAME_POINTER_REGNUM, RETURN_ADDRESS_POINTER_REGNUM, \
716 AR_CCV_REGNUM, AR_UNAT_REGNUM, AR_PFS_REGNUM, AR_LC_REGNUM, \
720 /* How Values Fit in Registers */
722 /* A C expression for the number of consecutive hard registers, starting at
723 register number REGNO, required to hold a value of mode MODE. */
725 /* ??? We say that BImode PR values require two registers. This allows us to
726 easily store the normal and inverted values. We use CCImode to indicate
727 a single predicate register. */
729 #define HARD_REGNO_NREGS(REGNO, MODE) \
730 ((REGNO) == PR_REG (0) && (MODE) == DImode ? 64 \
731 : PR_REGNO_P (REGNO) && (MODE) == BImode ? 2 \
732 : PR_REGNO_P (REGNO) && (MODE) == CCImode ? 1 \
733 : FR_REGNO_P (REGNO) && (MODE) == TFmode && INTEL_EXTENDED_IEEE_FORMAT ? 1 \
734 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
736 /* A C expression that is nonzero if it is permissible to store a value of mode
737 MODE in hard register number REGNO (or in several registers starting with
740 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
741 (FR_REGNO_P (REGNO) ? \
742 GET_MODE_CLASS (MODE) != MODE_CC && \
743 (MODE) != TImode && \
744 (MODE) != BImode && \
745 ((MODE) != TFmode || INTEL_EXTENDED_IEEE_FORMAT) \
746 : PR_REGNO_P (REGNO) ? \
747 (MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \
748 : GR_REGNO_P (REGNO) ? (MODE) != CCImode && (MODE) != TFmode \
749 : AR_REGNO_P (REGNO) ? (MODE) == DImode \
750 : BR_REGNO_P (REGNO) ? (MODE) == DImode \
753 /* A C expression that is nonzero if it is desirable to choose register
754 allocation so as to avoid move instructions between a value of mode MODE1
755 and a value of mode MODE2.
757 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
758 ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
760 /* Don't tie integer and FP modes, as that causes us to get integer registers
761 allocated for FP instructions. TFmode only supported in FP registers so
762 we can't tie it with any other modes. */
763 #define MODES_TIEABLE_P(MODE1, MODE2) \
764 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
765 && (((MODE1) == TFmode) == ((MODE2) == TFmode)) \
766 && (((MODE1) == BImode) == ((MODE2) == BImode)))
768 /* Handling Leaf Functions */
770 /* A C initializer for a vector, indexed by hard register number, which
771 contains 1 for a register that is allowable in a candidate for leaf function
773 /* ??? This might be useful. */
774 /* #define LEAF_REGISTERS */
776 /* A C expression whose value is the register number to which REGNO should be
777 renumbered, when a function is treated as a leaf function. */
778 /* ??? This might be useful. */
779 /* #define LEAF_REG_REMAP(REGNO) */
782 /* Register Classes */
784 /* An enumeral type that must be defined with all the register class names as
785 enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last
786 register class, followed by one more enumeral value, `LIM_REG_CLASSES',
787 which is not a register class but rather tells how many classes there
789 /* ??? When compiling without optimization, it is possible for the only use of
790 a pseudo to be a parameter load from the stack with a REG_EQUIV note.
791 Regclass handles this case specially and does not assign any costs to the
792 pseudo. The pseudo then ends up using the last class before ALL_REGS.
793 Thus we must not let either PR_REGS or BR_REGS be the last class. The
794 testcase for this is gcc.c-torture/execute/va-arg-7.c. */
811 #define GENERAL_REGS GR_REGS
813 /* The number of distinct register classes. */
814 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
816 /* An initializer containing the names of the register classes as C string
817 constants. These names are used in writing some of the debugging dumps. */
818 #define REG_CLASS_NAMES \
819 { "NO_REGS", "PR_REGS", "BR_REGS", "AR_M_REGS", "AR_I_REGS", \
820 "ADDL_REGS", "GR_REGS", "FR_REGS", \
821 "GR_AND_BR_REGS", "GR_AND_FR_REGS", "ALL_REGS" }
823 /* An initializer containing the contents of the register classes, as integers
824 which are bit masks. The Nth integer specifies the contents of class N.
825 The way the integer MASK is interpreted is that register R is in the class
826 if `MASK & (1 << R)' is 1. */
827 #define REG_CLASS_CONTENTS \
830 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
831 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
832 0x00000000, 0x00000000, 0x0000 }, \
834 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
835 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
836 0xFFFFFFFF, 0xFFFFFFFF, 0x0000 }, \
838 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
839 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
840 0x00000000, 0x00000000, 0x00FF }, \
842 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
843 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
844 0x00000000, 0x00000000, 0x0C00 }, \
846 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
847 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
848 0x00000000, 0x00000000, 0x7000 }, \
850 { 0x0000000F, 0x00000000, 0x00000000, 0x00000000, \
851 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
852 0x00000000, 0x00000000, 0x0000 }, \
854 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
855 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
856 0x00000000, 0x00000000, 0x0300 }, \
858 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
859 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
860 0x00000000, 0x00000000, 0x0000 }, \
861 /* GR_AND_BR_REGS. */ \
862 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
863 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
864 0x00000000, 0x00000000, 0x03FF }, \
865 /* GR_AND_FR_REGS. */ \
866 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
867 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
868 0x00000000, 0x00000000, 0x0300 }, \
870 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
871 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
872 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFF }, \
875 /* A C expression whose value is a register class containing hard register
876 REGNO. In general there is more than one such class; choose a class which
877 is "minimal", meaning that no smaller class also contains the register. */
878 /* The NO_REGS case is primarily for the benefit of rws_access_reg, which
879 may call here with private (invalid) register numbers, such as
881 #define REGNO_REG_CLASS(REGNO) \
882 (ADDL_REGNO_P (REGNO) ? ADDL_REGS \
883 : GENERAL_REGNO_P (REGNO) ? GR_REGS \
884 : FR_REGNO_P (REGNO) ? FR_REGS \
885 : PR_REGNO_P (REGNO) ? PR_REGS \
886 : BR_REGNO_P (REGNO) ? BR_REGS \
887 : AR_M_REGNO_P (REGNO) ? AR_M_REGS \
888 : AR_I_REGNO_P (REGNO) ? AR_I_REGS \
891 /* A macro whose definition is the name of the class to which a valid base
892 register must belong. A base register is one used in an address which is
893 the register value plus a displacement. */
894 #define BASE_REG_CLASS GENERAL_REGS
896 /* A macro whose definition is the name of the class to which a valid index
897 register must belong. An index register is one used in an address where its
898 value is either multiplied by a scale factor or added to another register
899 (as well as added to a displacement). This is needed for POST_MODIFY. */
900 #define INDEX_REG_CLASS GENERAL_REGS
902 /* A C expression which defines the machine-dependent operand constraint
903 letters for register classes. If CHAR is such a letter, the value should be
904 the register class corresponding to it. Otherwise, the value should be
905 `NO_REGS'. The register letter `r', corresponding to class `GENERAL_REGS',
906 will not be passed to this macro; you do not need to handle it. */
908 #define REG_CLASS_FROM_LETTER(CHAR) \
909 ((CHAR) == 'f' ? FR_REGS \
910 : (CHAR) == 'a' ? ADDL_REGS \
911 : (CHAR) == 'b' ? BR_REGS \
912 : (CHAR) == 'c' ? PR_REGS \
913 : (CHAR) == 'd' ? AR_M_REGS \
914 : (CHAR) == 'e' ? AR_I_REGS \
917 /* A C expression which is nonzero if register number NUM is suitable for use
918 as a base register in operand addresses. It may be either a suitable hard
919 register or a pseudo register that has been allocated such a hard reg. */
920 #define REGNO_OK_FOR_BASE_P(REGNO) \
921 (GENERAL_REGNO_P (REGNO) || GENERAL_REGNO_P (reg_renumber[REGNO]))
923 /* A C expression which is nonzero if register number NUM is suitable for use
924 as an index register in operand addresses. It may be either a suitable hard
925 register or a pseudo register that has been allocated such a hard reg.
926 This is needed for POST_MODIFY. */
927 #define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM)
929 /* A C expression that places additional restrictions on the register class to
930 use when it is necessary to copy value X into a register in class CLASS.
931 The value is a register class; perhaps CLASS, or perhaps another, smaller
934 /* Don't allow volatile mem reloads into floating point registers. This
935 is defined to force reload to choose the r/m case instead of the f/f case
936 when reloading (set (reg fX) (mem/v)).
938 Do not reload expressions into AR regs. */
940 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
941 (CLASS == FR_REGS && GET_CODE (X) == MEM && MEM_VOLATILE_P (X) ? NO_REGS \
942 : CLASS == FR_REGS && GET_CODE (X) == CONST_DOUBLE ? NO_REGS \
943 : GET_RTX_CLASS (GET_CODE (X)) != 'o' \
944 && (CLASS == AR_M_REGS || CLASS == AR_I_REGS) ? NO_REGS \
947 /* You should define this macro to indicate to the reload phase that it may
948 need to allocate at least one register for a reload in addition to the
949 register to contain the data. Specifically, if copying X to a register
950 CLASS in MODE requires an intermediate register, you should define this
951 to return the largest register class all of whose registers can be used
952 as intermediate registers or scratch registers. */
954 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
955 ia64_secondary_reload_class (CLASS, MODE, X)
957 /* Certain machines have the property that some registers cannot be copied to
958 some other registers without using memory. Define this macro on those
959 machines to be a C expression that is non-zero if objects of mode M in
960 registers of CLASS1 can only be copied to registers of class CLASS2 by
961 storing a register of CLASS1 into memory and loading that memory location
962 into a register of CLASS2. */
965 /* ??? May need this, but since we've disallowed TFmode in GR_REGS,
966 I'm not quite sure how it could be invoked. The normal problems
967 with unions should be solved with the addressof fiddling done by
968 movtf and friends. */
969 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
970 ((MODE) == TFmode && (((CLASS1) == GR_REGS && (CLASS2) == FR_REGS) \
971 || ((CLASS1) == FR_REGS && (CLASS2) == GR_REGS)))
974 /* A C expression for the maximum number of consecutive registers of
975 class CLASS needed to hold a value of mode MODE.
976 This is closely related to the macro `HARD_REGNO_NREGS'. */
978 #define CLASS_MAX_NREGS(CLASS, MODE) \
979 ((MODE) == BImode && (CLASS) == PR_REGS ? 2 \
980 : ((CLASS) == FR_REGS && (MODE) == TFmode) ? 1 \
981 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
983 /* If defined, gives a class of registers that cannot be used as the
984 operand of a SUBREG that changes the mode of the object illegally. */
986 #define CLASS_CANNOT_CHANGE_MODE FR_REGS
988 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE.
989 In FP regs, we can't change FP values to integer values and vice
990 versa, but we can change e.g. DImode to SImode. */
992 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
993 (GET_MODE_CLASS (FROM) != GET_MODE_CLASS (TO))
995 /* A C expression that defines the machine-dependent operand constraint
996 letters (`I', `J', `K', .. 'P') that specify particular ranges of
999 /* 14 bit signed immediate for arithmetic instructions. */
1000 #define CONST_OK_FOR_I(VALUE) \
1001 ((unsigned HOST_WIDE_INT)(VALUE) + 0x2000 < 0x4000)
1002 /* 22 bit signed immediate for arith instructions with r0/r1/r2/r3 source. */
1003 #define CONST_OK_FOR_J(VALUE) \
1004 ((unsigned HOST_WIDE_INT)(VALUE) + 0x200000 < 0x400000)
1005 /* 8 bit signed immediate for logical instructions. */
1006 #define CONST_OK_FOR_K(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x80 < 0x100)
1007 /* 8 bit adjusted signed immediate for compare pseudo-ops. */
1008 #define CONST_OK_FOR_L(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x7F < 0x100)
1009 /* 6 bit unsigned immediate for shift counts. */
1010 #define CONST_OK_FOR_M(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) < 0x40)
1011 /* 9 bit signed immediate for load/store post-increments. */
1012 #define CONST_OK_FOR_N(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x100 < 0x200)
1013 /* 0 for r0. Used by Linux kernel, do not change. */
1014 #define CONST_OK_FOR_O(VALUE) ((VALUE) == 0)
1015 /* 0 or -1 for dep instruction. */
1016 #define CONST_OK_FOR_P(VALUE) ((VALUE) == 0 || (VALUE) == -1)
1018 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1019 ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
1020 : (C) == 'J' ? CONST_OK_FOR_J (VALUE) \
1021 : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
1022 : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
1023 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
1024 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
1025 : (C) == 'O' ? CONST_OK_FOR_O (VALUE) \
1026 : (C) == 'P' ? CONST_OK_FOR_P (VALUE) \
1029 /* A C expression that defines the machine-dependent operand constraint letters
1030 (`G', `H') that specify particular ranges of `const_double' values. */
1032 /* 0.0 and 1.0 for fr0 and fr1. */
1033 #define CONST_DOUBLE_OK_FOR_G(VALUE) \
1034 ((VALUE) == CONST0_RTX (GET_MODE (VALUE)) \
1035 || (VALUE) == CONST1_RTX (GET_MODE (VALUE)))
1037 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1038 ((C) == 'G' ? CONST_DOUBLE_OK_FOR_G (VALUE) : 0)
1040 /* A C expression that defines the optional machine-dependent constraint
1041 letters (`Q', `R', `S', `T', `U') that can be used to segregate specific
1042 types of operands, usually memory references, for the target machine. */
1044 /* Non-volatile memory for FP_REG loads/stores. */
1045 #define CONSTRAINT_OK_FOR_Q(VALUE) \
1046 (memory_operand((VALUE), VOIDmode) && ! MEM_VOLATILE_P (VALUE))
1047 /* 1..4 for shladd arguments. */
1048 #define CONSTRAINT_OK_FOR_R(VALUE) \
1049 (GET_CODE (VALUE) == CONST_INT && INTVAL (VALUE) >= 1 && INTVAL (VALUE) <= 4)
1050 /* Non-post-inc memory for asms and other unsavory creatures. */
1051 #define CONSTRAINT_OK_FOR_S(VALUE) \
1052 (GET_CODE (VALUE) == MEM \
1053 && GET_RTX_CLASS (GET_CODE (XEXP ((VALUE), 0))) != 'a' \
1054 && (reload_in_progress || memory_operand ((VALUE), VOIDmode)))
1056 #define EXTRA_CONSTRAINT(VALUE, C) \
1057 ((C) == 'Q' ? CONSTRAINT_OK_FOR_Q (VALUE) \
1058 : (C) == 'R' ? CONSTRAINT_OK_FOR_R (VALUE) \
1059 : (C) == 'S' ? CONSTRAINT_OK_FOR_S (VALUE) \
1062 /* Basic Stack Layout */
1064 /* Define this macro if pushing a word onto the stack moves the stack pointer
1065 to a smaller address. */
1066 #define STACK_GROWS_DOWNWARD 1
1068 /* Define this macro if the addresses of local variable slots are at negative
1069 offsets from the frame pointer. */
1070 /* #define FRAME_GROWS_DOWNWARD */
1072 /* Offset from the frame pointer to the first local variable slot to
1074 #define STARTING_FRAME_OFFSET 0
1076 /* Offset from the stack pointer register to the first location at which
1077 outgoing arguments are placed. If not specified, the default value of zero
1078 is used. This is the proper value for most machines. */
1079 /* IA64 has a 16 byte scratch area that is at the bottom of the stack. */
1080 #define STACK_POINTER_OFFSET 16
1082 /* Offset from the argument pointer register to the first argument's address.
1083 On some machines it may depend on the data type of the function. */
1084 #define FIRST_PARM_OFFSET(FUNDECL) 0
1086 /* A C expression whose value is RTL representing the value of the return
1087 address for the frame COUNT steps up from the current frame, after the
1090 /* ??? Frames other than zero would likely require interpreting the frame
1091 unwind info, so we don't try to support them. We would also need to define
1092 DYNAMIC_CHAIN_ADDRESS and SETUP_FRAME_ADDRESS (for the reg stack flush). */
1094 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1095 ((COUNT) == 0 ? return_address_pointer_rtx : const0_rtx)
1097 /* A C expression whose value is RTL representing the location of the incoming
1098 return address at the beginning of any function, before the prologue. This
1099 RTL is either a `REG', indicating that the return value is saved in `REG',
1100 or a `MEM' representing a location in the stack. This enables DWARF2
1101 unwind info for C++ EH. */
1102 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, BR_REG (0))
1104 /* ??? This is not defined because of three problems.
1105 1) dwarf2out.c assumes that DWARF_FRAME_RETURN_COLUMN fits in one byte.
1106 The default value is FIRST_PSEUDO_REGISTER which doesn't. This can be
1107 worked around by setting PC_REGNUM to FR_REG (0) which is an otherwise
1108 unused register number.
1109 2) dwarf2out_frame_debug core dumps while processing prologue insns. We
1110 need to refine which insns have RTX_FRAME_RELATED_P set and which don't.
1111 3) It isn't possible to turn off EH frame info by defining DWARF2_UNIND_INFO
1112 to zero, despite what the documentation implies, because it is tested in
1113 a few places with #ifdef instead of #if. */
1114 #undef INCOMING_RETURN_ADDR_RTX
1116 /* A C expression whose value is an integer giving the offset, in bytes, from
1117 the value of the stack pointer register to the top of the stack frame at the
1118 beginning of any function, before the prologue. The top of the frame is
1119 defined to be the value of the stack pointer in the previous frame, just
1120 before the call instruction. */
1121 #define INCOMING_FRAME_SP_OFFSET 0
1124 /* Register That Address the Stack Frame. */
1126 /* The register number of the stack pointer register, which must also be a
1127 fixed register according to `FIXED_REGISTERS'. On most machines, the
1128 hardware determines which register this is. */
1130 #define STACK_POINTER_REGNUM 12
1132 /* The register number of the frame pointer register, which is used to access
1133 automatic variables in the stack frame. On some machines, the hardware
1134 determines which register this is. On other machines, you can choose any
1135 register you wish for this purpose. */
1137 #define FRAME_POINTER_REGNUM 328
1139 /* Base register for access to local variables of the function. */
1140 #define HARD_FRAME_POINTER_REGNUM LOC_REG (79)
1142 /* The register number of the arg pointer register, which is used to access the
1143 function's argument list. */
1144 /* r0 won't otherwise be used, so put the always eliminated argument pointer
1146 #define ARG_POINTER_REGNUM R_GR(0)
1148 /* The register number for the return address register. For IA-64, this
1149 is not actually a pointer as the name suggests, but that's a name that
1150 gen_rtx_REG already takes care to keep unique. We modify
1151 return_address_pointer_rtx in ia64_expand_prologue to reference the
1152 final output regnum. */
1153 #define RETURN_ADDRESS_POINTER_REGNUM 329
1155 /* Register numbers used for passing a function's static chain pointer. */
1156 /* ??? The ABI sez the static chain should be passed as a normal parameter. */
1157 #define STATIC_CHAIN_REGNUM 15
1159 /* Eliminating the Frame Pointer and the Arg Pointer */
1161 /* A C expression which is nonzero if a function must have and use a frame
1162 pointer. This expression is evaluated in the reload pass. If its value is
1163 nonzero the function will have a frame pointer. */
1164 #define FRAME_POINTER_REQUIRED 0
1166 /* Show we can debug even without a frame pointer. */
1167 #define CAN_DEBUG_WITHOUT_FP
1169 /* If defined, this macro specifies a table of register pairs used to eliminate
1170 unneeded registers that point into the stack frame. */
1172 #define ELIMINABLE_REGS \
1174 {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1175 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1176 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1177 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1178 {RETURN_ADDRESS_POINTER_REGNUM, BR_REG (0)}, \
1181 /* A C expression that returns non-zero if the compiler is allowed to try to
1182 replace register number FROM with register number TO. The frame pointer
1183 is automatically handled. */
1185 #define CAN_ELIMINATE(FROM, TO) \
1186 (TO == BR_REG (0) ? current_function_is_leaf : 1)
1188 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
1189 specifies the initial difference between the specified pair of
1190 registers. This macro must be defined if `ELIMINABLE_REGS' is
1192 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1193 ((OFFSET) = ia64_initial_elimination_offset ((FROM), (TO)))
1195 /* Passing Function Arguments on the Stack */
1197 /* Define this macro if an argument declared in a prototype as an integral type
1198 smaller than `int' should actually be passed as an `int'. In addition to
1199 avoiding errors in certain cases of mismatch, it also makes for better code
1200 on certain machines. */
1201 /* ??? Investigate. */
1202 /* #define PROMOTE_PROTOTYPES */
1204 /* If defined, the maximum amount of space required for outgoing arguments will
1205 be computed and placed into the variable
1206 `current_function_outgoing_args_size'. */
1208 #define ACCUMULATE_OUTGOING_ARGS 1
1210 /* A C expression that should indicate the number of bytes of its own arguments
1211 that a function pops on returning, or 0 if the function pops no arguments
1212 and the caller must therefore pop them all after the function returns. */
1214 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
1217 /* Function Arguments in Registers */
1219 #define MAX_ARGUMENT_SLOTS 8
1220 #define MAX_INT_RETURN_SLOTS 4
1221 #define GR_ARG_FIRST IN_REG (0)
1222 #define GR_RET_FIRST GR_REG (8)
1223 #define GR_RET_LAST GR_REG (11)
1224 #define FR_ARG_FIRST FR_REG (8)
1225 #define FR_RET_FIRST FR_REG (8)
1226 #define FR_RET_LAST FR_REG (15)
1227 #define AR_ARG_FIRST OUT_REG (0)
1229 /* A C expression that controls whether a function argument is passed in a
1230 register, and which register. */
1232 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1233 ia64_function_arg (&CUM, MODE, TYPE, NAMED, 0)
1235 /* Define this macro if the target machine has "register windows", so that the
1236 register in which a function sees an arguments is not necessarily the same
1237 as the one in which the caller passed the argument. */
1239 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1240 ia64_function_arg (&CUM, MODE, TYPE, NAMED, 1)
1242 /* A C expression for the number of words, at the beginning of an argument,
1243 must be put in registers. The value must be zero for arguments that are
1244 passed entirely in registers or that are entirely pushed on the stack. */
1246 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1247 ia64_function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
1249 /* A C expression that indicates when an argument must be passed by reference.
1250 If nonzero for an argument, a copy of that argument is made in memory and a
1251 pointer to the argument is passed instead of the argument itself. The
1252 pointer is passed in whatever way is appropriate for passing a pointer to
1255 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) 0
1257 /* A C type for declaring a variable that is used as the first argument of
1258 `FUNCTION_ARG' and other related values. For some target machines, the type
1259 `int' suffices and can hold the number of bytes of argument so far. */
1261 typedef struct ia64_args
1263 int words; /* # words of arguments so far */
1264 int fp_regs; /* # FR registers used so far */
1265 int prototype; /* whether function prototyped */
1268 /* A C statement (sans semicolon) for initializing the variable CUM for the
1269 state at the beginning of the argument list. */
1271 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1274 (CUM).fp_regs = 0; \
1275 (CUM).prototype = ((FNTYPE) && TYPE_ARG_TYPES (FNTYPE)) || (LIBNAME); \
1278 /* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of finding the
1279 arguments for the function being compiled. If this macro is undefined,
1280 `INIT_CUMULATIVE_ARGS' is used instead. */
1282 /* We set prototype to true so that we never try to return a PARALLEL from
1284 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1287 (CUM).fp_regs = 0; \
1288 (CUM).prototype = 1; \
1291 /* A C statement (sans semicolon) to update the summarizer variable CUM to
1292 advance past an argument in the argument list. The values MODE, TYPE and
1293 NAMED describe that argument. Once this is done, the variable CUM is
1294 suitable for analyzing the *following* argument with `FUNCTION_ARG'. */
1296 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1297 ia64_function_arg_advance (&CUM, MODE, TYPE, NAMED)
1299 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1300 argument with the specified mode and type. */
1302 /* Arguments with alignment larger than 8 bytes start at the next even
1303 boundary. See ia64_function_arg. */
1305 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1306 (((TYPE) ? (TYPE_ALIGN (TYPE) > 8 * BITS_PER_UNIT) \
1307 : (((((MODE) == BLKmode \
1308 ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \
1309 + UNITS_PER_WORD - 1) / UNITS_PER_WORD) > 1)) \
1310 ? 128 : PARM_BOUNDARY)
1312 /* A C expression that is nonzero if REGNO is the number of a hard register in
1313 which function arguments are sometimes passed. This does *not* include
1314 implicit arguments such as the static chain and the structure-value address.
1315 On many machines, no registers can be used for this purpose since all
1316 function arguments are pushed on the stack. */
1317 #define FUNCTION_ARG_REGNO_P(REGNO) \
1318 (((REGNO) >= GR_ARG_FIRST && (REGNO) < (GR_ARG_FIRST + MAX_ARGUMENT_SLOTS)) \
1319 || ((REGNO) >= FR_ARG_FIRST && (REGNO) < (FR_ARG_FIRST + MAX_ARGUMENT_SLOTS)))
1321 /* Implement `va_start' for varargs and stdarg. */
1322 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1323 ia64_va_start (stdarg, valist, nextarg)
1325 /* Implement `va_arg'. */
1326 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1327 ia64_va_arg (valist, type)
1329 /* How Scalar Function Values are Returned */
1331 /* A C expression to create an RTX representing the place where a function
1332 returns a value of data type VALTYPE. */
1334 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1335 ia64_function_value (VALTYPE, FUNC)
1337 /* A C expression to create an RTX representing the place where a library
1338 function returns a value of mode MODE. */
1340 #define LIBCALL_VALUE(MODE) \
1341 gen_rtx_REG (MODE, \
1342 (((GET_MODE_CLASS (MODE) == MODE_FLOAT \
1343 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) && \
1344 ((MODE) != TFmode || INTEL_EXTENDED_IEEE_FORMAT)) \
1345 ? FR_RET_FIRST : GR_RET_FIRST))
1347 /* A C expression that is nonzero if REGNO is the number of a hard register in
1348 which the values of called function may come back. */
1350 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1351 (((REGNO) >= GR_RET_FIRST && (REGNO) <= GR_RET_LAST) \
1352 || ((REGNO) >= FR_RET_FIRST && (REGNO) <= FR_RET_LAST))
1355 /* How Large Values are Returned */
1357 /* A nonzero value says to return the function value in memory, just as large
1358 structures are always returned. */
1360 #define RETURN_IN_MEMORY(TYPE) \
1361 ia64_return_in_memory (TYPE)
1363 /* If you define this macro to be 0, then the conventions used for structure
1364 and union return values are decided by the `RETURN_IN_MEMORY' macro. */
1366 #define DEFAULT_PCC_STRUCT_RETURN 0
1368 /* If the structure value address is passed in a register, then
1369 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1371 #define STRUCT_VALUE_REGNUM GR_REG (8)
1374 /* Caller-Saves Register Allocation */
1376 /* A C expression to determine whether it is worthwhile to consider placing a
1377 pseudo-register in a call-clobbered hard register and saving and restoring
1378 it around each function call. The expression should be 1 when this is worth
1379 doing, and 0 otherwise.
1381 If you don't define this macro, a default is used which is good on most
1382 machines: `4 * CALLS < REFS'. */
1383 /* ??? Investigate. */
1384 /* #define CALLER_SAVE_PROFITABLE(REFS, CALLS) */
1387 /* Function Entry and Exit */
1389 /* Define this macro as a C expression that is nonzero if the return
1390 instruction or the function epilogue ignores the value of the stack pointer;
1391 in other words, if it is safe to delete an instruction to adjust the stack
1392 pointer before a return from the function. */
1394 #define EXIT_IGNORE_STACK 1
1396 /* Define this macro as a C expression that is nonzero for registers
1397 used by the epilogue or the `return' pattern. */
1399 #define EPILOGUE_USES(REGNO) ia64_epilogue_uses (REGNO)
1401 /* Output at beginning of assembler file. */
1403 #define ASM_FILE_START(FILE) \
1404 emit_safe_across_calls (FILE)
1406 /* A C compound statement that outputs the assembler code for a thunk function,
1407 used to implement C++ virtual function calls with multiple inheritance. */
1409 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
1411 if (CONST_OK_FOR_I (DELTA)) \
1413 fprintf (FILE, "\tadds r32 = "); \
1414 fprintf (FILE, HOST_WIDE_INT_PRINT_DEC, (DELTA)); \
1415 fprintf (FILE, ", r32\n"); \
1419 if (CONST_OK_FOR_J (DELTA)) \
1421 fprintf (FILE, "\taddl r2 = "); \
1422 fprintf (FILE, HOST_WIDE_INT_PRINT_DEC, (DELTA)); \
1423 fprintf (FILE, ", r0\n"); \
1427 fprintf (FILE, "\tmovl r2 = "); \
1428 fprintf (FILE, HOST_WIDE_INT_PRINT_DEC, (DELTA)); \
1429 fprintf (FILE, "\n"); \
1431 fprintf (FILE, "\t;;\n"); \
1432 fprintf (FILE, "\tadd r32 = r2, r32\n"); \
1434 fprintf (FILE, "\tbr "); \
1435 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
1436 fprintf (FILE, "\n"); \
1439 /* Output part N of a function descriptor for DECL. For ia64, both
1440 words are emitted with a single relocation, so ignore N > 0. */
1441 #define ASM_OUTPUT_FDESC(FILE, DECL, PART) \
1445 fputs ("\tdata16.ua @iplt(", FILE); \
1446 assemble_name (FILE, XSTR (XEXP (DECL_RTL (DECL), 0), 0)); \
1447 fputs (")\n", FILE); \
1451 /* Generating Code for Profiling. */
1453 /* A C statement or compound statement to output to FILE some assembler code to
1454 call the profiling subroutine `mcount'. */
1456 #undef FUNCTION_PROFILER
1457 #define FUNCTION_PROFILER(FILE, LABELNO) \
1460 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", LABELNO); \
1461 fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", FILE); \
1462 if (TARGET_AUTO_PIC) \
1463 fputs ("\tmovl out3 = @gprel(", FILE); \
1465 fputs ("\taddl out3 = @ltoff(", FILE); \
1466 assemble_name (FILE, buf); \
1467 if (TARGET_AUTO_PIC) \
1468 fputs (");;\n", FILE); \
1470 fputs ("), r1;;\n", FILE); \
1471 fputs ("\tmov out1 = r1\n", FILE); \
1472 fputs ("\tmov out2 = b0\n", FILE); \
1473 fputs ("\tbr.call.sptk.many b0 = _mcount;;\n", FILE); \
1476 /* Implementing the Varargs Macros. */
1478 /* Define this macro to store the anonymous register arguments into the stack
1479 so that all the arguments appear to have been passed consecutively on the
1482 #define SETUP_INCOMING_VARARGS(ARGS_SO_FAR, MODE, TYPE, PRETEND_ARGS_SIZE, SECOND_TIME) \
1483 ia64_setup_incoming_varargs (ARGS_SO_FAR, MODE, TYPE, & PRETEND_ARGS_SIZE, SECOND_TIME)
1485 /* Define this macro if the location where a function argument is passed
1486 depends on whether or not it is a named argument. */
1488 #define STRICT_ARGUMENT_NAMING 1
1491 /* Trampolines for Nested Functions. */
1493 /* We need 32 bytes, so we can save the sp, ar.rnat, ar.bsp, and ar.pfs of
1494 the function containing a non-local goto target. */
1496 #define STACK_SAVEAREA_MODE(LEVEL) \
1497 ((LEVEL) == SAVE_NONLOCAL ? OImode : Pmode)
1499 /* Output assembler code for a block containing the constant parts of
1500 a trampoline, leaving space for the variable parts.
1502 The trampoline should set the static chain pointer to value placed
1503 into the trampoline and should branch to the specified routine.
1504 To make the normal indirect-subroutine calling convention work,
1505 the trampoline must look like a function descriptor; the first
1506 word being the target address and the second being the target's
1509 We abuse the concept of a global pointer by arranging for it
1510 to point to the data we need to load. The complete trampoline
1511 has the following form:
1513 +-------------------+ \
1514 TRAMP: | __ia64_trampoline | |
1515 +-------------------+ > fake function descriptor
1517 +-------------------+ /
1518 | target descriptor |
1519 +-------------------+
1521 +-------------------+
1524 /* A C expression for the size in bytes of the trampoline, as an integer. */
1526 #define TRAMPOLINE_SIZE 32
1528 /* Alignment required for trampolines, in bits. */
1530 #define TRAMPOLINE_ALIGNMENT 64
1532 /* A C statement to initialize the variable parts of a trampoline. */
1534 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, STATIC_CHAIN) \
1535 ia64_initialize_trampoline((ADDR), (FNADDR), (STATIC_CHAIN))
1537 /* Implicit Calls to Library Routines */
1539 /* Define this macro if GNU CC should generate calls to the System V (and ANSI
1540 C) library functions `memcpy' and `memset' rather than the BSD functions
1541 `bcopy' and `bzero'. */
1543 #define TARGET_MEM_FUNCTIONS
1546 /* Addressing Modes */
1548 /* Define this macro if the machine supports post-increment addressing. */
1550 #define HAVE_POST_INCREMENT 1
1551 #define HAVE_POST_DECREMENT 1
1552 #define HAVE_POST_MODIFY_DISP 1
1553 #define HAVE_POST_MODIFY_REG 1
1555 /* A C expression that is 1 if the RTX X is a constant which is a valid
1558 #define CONSTANT_ADDRESS_P(X) 0
1560 /* The max number of registers that can appear in a valid memory address. */
1562 #define MAX_REGS_PER_ADDRESS 2
1564 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
1565 RTX) is a legitimate memory address on the target machine for a memory
1566 operand of mode MODE. */
1568 #define LEGITIMATE_ADDRESS_REG(X) \
1569 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1570 || (GET_CODE (X) == SUBREG && GET_CODE (XEXP (X, 0)) == REG \
1571 && REG_OK_FOR_BASE_P (XEXP (X, 0))))
1573 #define LEGITIMATE_ADDRESS_DISP(R, X) \
1574 (GET_CODE (X) == PLUS \
1575 && rtx_equal_p (R, XEXP (X, 0)) \
1576 && (LEGITIMATE_ADDRESS_REG (XEXP (X, 1)) \
1577 || (GET_CODE (XEXP (X, 1)) == CONST_INT \
1578 && INTVAL (XEXP (X, 1)) >= -256 \
1579 && INTVAL (XEXP (X, 1)) < 256)))
1581 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1583 if (LEGITIMATE_ADDRESS_REG (X)) \
1585 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
1586 && LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \
1587 && XEXP (X, 0) != arg_pointer_rtx) \
1589 else if (GET_CODE (X) == POST_MODIFY \
1590 && LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \
1591 && XEXP (X, 0) != arg_pointer_rtx \
1592 && LEGITIMATE_ADDRESS_DISP (XEXP (X, 0), XEXP (X, 1))) \
1596 /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
1597 use as a base register. */
1599 #ifdef REG_OK_STRICT
1600 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1602 #define REG_OK_FOR_BASE_P(X) \
1603 (GENERAL_REGNO_P (REGNO (X)) || (REGNO (X) >= FIRST_PSEUDO_REGISTER))
1606 /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
1607 use as an index register. This is needed for POST_MODIFY. */
1609 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1611 /* A C compound statement that attempts to replace X with a valid memory
1612 address for an operand of mode MODE.
1614 This must be present, but there is nothing useful to be done here. */
1616 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)
1618 /* A C statement or compound statement with a conditional `goto LABEL;'
1619 executed if memory address X (an RTX) can have different meanings depending
1620 on the machine mode of the memory reference it is used for or if the address
1621 is valid for some modes but not others. */
1623 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1624 if (GET_CODE (ADDR) == POST_DEC || GET_CODE (ADDR) == POST_INC) \
1627 /* A C expression that is nonzero if X is a legitimate constant for an
1628 immediate operand on the target machine. */
1630 #define LEGITIMATE_CONSTANT_P(X) \
1631 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode \
1632 || GET_MODE (X) == DImode || CONST_DOUBLE_OK_FOR_G (X)) \
1635 /* Condition Code Status */
1637 /* One some machines not all possible comparisons are defined, but you can
1638 convert an invalid comparison into a valid one. */
1639 /* ??? Investigate. See the alpha definition. */
1640 /* #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) */
1643 /* Describing Relative Costs of Operations */
1645 /* A part of a C `switch' statement that describes the relative costs of
1646 constant RTL expressions. */
1648 /* ??? This is incomplete. */
1650 #define CONST_COSTS(X, CODE, OUTER_CODE) \
1652 if ((X) == const0_rtx) \
1654 switch (OUTER_CODE) \
1657 return CONST_OK_FOR_J (INTVAL (X)) ? 0 : COSTS_N_INSNS (1); \
1659 if (CONST_OK_FOR_I (INTVAL (X))) \
1661 if (CONST_OK_FOR_J (INTVAL (X))) \
1663 return COSTS_N_INSNS (1); \
1665 if (CONST_OK_FOR_K (INTVAL (X)) || CONST_OK_FOR_L (INTVAL (X))) \
1667 return COSTS_N_INSNS (1); \
1669 case CONST_DOUBLE: \
1670 return COSTS_N_INSNS (1); \
1674 return COSTS_N_INSNS (3);
1676 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions. */
1678 #define RTX_COSTS(X, CODE, OUTER_CODE) \
1680 /* For multiplies wider than HImode, we have to go to the FPU, \
1681 which normally involves copies. Plus there's the latency \
1682 of the multiply itself, and the latency of the instructions to \
1683 transfer integer regs to FP regs. */ \
1684 if (GET_MODE_SIZE (GET_MODE (X)) > 2) \
1685 return COSTS_N_INSNS (10); \
1686 return COSTS_N_INSNS (2); \
1692 return COSTS_N_INSNS (1); \
1697 /* We make divide expensive, so that divide-by-constant will be \
1698 optimized to a multiply. */ \
1699 return COSTS_N_INSNS (60);
1701 /* An expression giving the cost of an addressing mode that contains ADDRESS.
1702 If not defined, the cost is computed from the ADDRESS expression and the
1703 `CONST_COSTS' values. */
1705 #define ADDRESS_COST(ADDRESS) 0
1707 /* A C expression for the cost of moving data from a register in class FROM to
1708 one in class TO, using MODE. */
1710 #define REGISTER_MOVE_COST ia64_register_move_cost
1712 /* A C expression for the cost of moving data of mode M between a
1713 register and memory. */
1714 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
1715 ((CLASS) == GENERAL_REGS || (CLASS) == FR_REGS \
1716 || (CLASS) == GR_AND_FR_REGS ? 4 : 10)
1718 /* A C expression for the cost of a branch instruction. A value of 1 is the
1719 default; other values are interpreted relative to that. Used by the
1720 if-conversion code as max instruction count. */
1721 /* ??? This requires investigation. The primary effect might be how
1722 many additional insn groups we run into, vs how good the dynamic
1723 branch predictor is. */
1725 #define BRANCH_COST 6
1727 /* Define this macro as a C expression which is nonzero if accessing less than
1728 a word of memory (i.e. a `char' or a `short') is no faster than accessing a
1731 #define SLOW_BYTE_ACCESS 1
1733 /* Define this macro if it is as good or better to call a constant function
1734 address than to call an address kept in a register.
1736 Indirect function calls are more expensive that direct function calls, so
1737 don't cse function addresses. */
1739 #define NO_FUNCTION_CSE
1742 /* Dividing the output into sections. */
1744 /* A C expression whose value is a string containing the assembler operation
1745 that should precede instructions and read-only data. */
1747 #define TEXT_SECTION_ASM_OP "\t.text"
1749 /* A C expression whose value is a string containing the assembler operation to
1750 identify the following data as writable initialized data. */
1752 #define DATA_SECTION_ASM_OP "\t.data"
1754 /* If defined, a C expression whose value is a string containing the assembler
1755 operation to identify the following data as uninitialized global data. */
1757 #define BSS_SECTION_ASM_OP "\t.bss"
1759 /* Define this macro if references to a symbol must be treated differently
1760 depending on something about the variable or function named by the symbol
1761 (such as what section it is in). */
1763 #define ENCODE_SECTION_INFO(DECL, FIRST) ia64_encode_section_info (DECL, FIRST)
1765 #define SDATA_NAME_FLAG_CHAR '@'
1767 #define IA64_DEFAULT_GVALUE 8
1769 /* Decode SYM_NAME and store the real name part in VAR, sans the characters
1770 that encode section info. */
1772 #define STRIP_NAME_ENCODING(VAR, SYMBOL_NAME) \
1774 (VAR) = (SYMBOL_NAME); \
1775 if ((VAR)[0] == SDATA_NAME_FLAG_CHAR) \
1777 if ((VAR)[0] == '*') \
1781 /* Position Independent Code. */
1783 /* The register number of the register used to address a table of static data
1784 addresses in memory. */
1786 /* ??? Should modify ia64.md to use pic_offset_table_rtx instead of
1787 gen_rtx_REG (DImode, 1). */
1789 /* ??? Should we set flag_pic? Probably need to define
1790 LEGITIMIZE_PIC_OPERAND_P to make that work. */
1792 #define PIC_OFFSET_TABLE_REGNUM GR_REG (1)
1794 /* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' is
1795 clobbered by calls. */
1797 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
1800 /* The Overall Framework of an Assembler File. */
1802 /* A C string constant describing how to begin a comment in the target
1803 assembler language. The compiler assumes that the comment will end at the
1806 #define ASM_COMMENT_START "//"
1808 /* A C string constant for text to be output before each `asm' statement or
1809 group of consecutive ones. */
1811 /* ??? This won't work with the Intel assembler, because it does not accept
1812 # as a comment start character. However, //APP does not work in gas, so we
1813 can't use that either. Same problem for ASM_APP_OFF below. */
1815 #define ASM_APP_ON "#APP\n"
1817 /* A C string constant for text to be output after each `asm' statement or
1818 group of consecutive ones. */
1820 #define ASM_APP_OFF "#NO_APP\n"
1823 /* Output of Data. */
1825 /* This is how to output an assembler line defining a `char' constant
1826 to an xdata segment. */
1828 #define ASM_OUTPUT_XDATA_CHAR(FILE, SECTION, VALUE) \
1830 fprintf (FILE, "\t.xdata1\t\"%s\", ", SECTION); \
1831 output_addr_const (FILE, (VALUE)); \
1832 fprintf (FILE, "\n"); \
1835 /* This is how to output an assembler line defining a `short' constant
1836 to an xdata segment. */
1838 #define ASM_OUTPUT_XDATA_SHORT(FILE, SECTION, VALUE) \
1840 fprintf (FILE, "\t.xdata2\t\"%s\", ", SECTION); \
1841 output_addr_const (FILE, (VALUE)); \
1842 fprintf (FILE, "\n"); \
1845 /* This is how to output an assembler line defining an `int' constant
1846 to an xdata segment. We also handle symbol output here. */
1848 /* ??? For ILP32, also need to handle function addresses here. */
1850 #define ASM_OUTPUT_XDATA_INT(FILE, SECTION, VALUE) \
1852 fprintf (FILE, "\t.xdata4\t\"%s\", ", SECTION); \
1853 output_addr_const (FILE, (VALUE)); \
1854 fprintf (FILE, "\n"); \
1857 /* This is how to output an assembler line defining a `long' constant
1858 to an xdata segment. We also handle symbol output here. */
1860 #define ASM_OUTPUT_XDATA_DOUBLE_INT(FILE, SECTION, VALUE) \
1862 int need_closing_paren = 0; \
1863 fprintf (FILE, "\t.xdata8\t\"%s\", ", SECTION); \
1864 if (!(TARGET_NO_PIC || TARGET_AUTO_PIC) \
1865 && GET_CODE (VALUE) == SYMBOL_REF) \
1867 fprintf (FILE, SYMBOL_REF_FLAG (VALUE) ? "@fptr(" : "@segrel("); \
1868 need_closing_paren = 1; \
1870 output_addr_const (FILE, VALUE); \
1871 if (need_closing_paren) \
1872 fprintf (FILE, ")"); \
1873 fprintf (FILE, "\n"); \
1878 /* Output of Uninitialized Variables. */
1880 /* This is all handled by svr4.h. */
1883 /* Output and Generation of Labels. */
1885 /* A C statement (sans semicolon) to output to the stdio stream STREAM the
1886 assembler definition of a label named NAME. */
1888 /* See the ASM_OUTPUT_LABELREF definition in sysv4.h for an explanation of
1889 why ia64_asm_output_label exists. */
1891 extern int ia64_asm_output_label;
1892 #define ASM_OUTPUT_LABEL(STREAM, NAME) \
1894 ia64_asm_output_label = 1; \
1895 assemble_name (STREAM, NAME); \
1896 fputs (":\n", STREAM); \
1897 ia64_asm_output_label = 0; \
1900 /* A C statement (sans semicolon) to output to the stdio stream STREAM some
1901 commands that will make the label NAME global; that is, available for
1902 reference from other files. */
1904 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
1906 fputs ("\t.global ", STREAM); \
1907 assemble_name (STREAM, NAME); \
1908 fputs ("\n", STREAM); \
1911 /* A C statement (sans semicolon) to output to the stdio stream STREAM any text
1912 necessary for declaring the name of an external symbol named NAME which is
1913 referenced in this compilation but not defined. */
1915 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
1916 ia64_asm_output_external (FILE, DECL, NAME)
1918 /* A C statement to store into the string STRING a label whose name is made
1919 from the string PREFIX and the number NUM. */
1921 #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \
1923 sprintf (LABEL, "*.%s%d", PREFIX, NUM); \
1926 /* A C expression to assign to OUTVAR (which is a variable of type `char *') a
1927 newly allocated string made from the string NAME and the number NUMBER, with
1928 some suitable punctuation added. */
1930 /* ??? Not sure if using a ? in the name for Intel as is safe. */
1932 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR, NAME, NUMBER) \
1934 (OUTVAR) = (char *) alloca (strlen (NAME) + 12); \
1935 sprintf (OUTVAR, "%s%c%ld", (NAME), (TARGET_GNU_AS ? '.' : '?'), \
1939 /* A C statement to output to the stdio stream STREAM assembler code which
1940 defines (equates) the symbol NAME to have the value VALUE. */
1942 #define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \
1944 assemble_name (STREAM, NAME); \
1945 fputs (" = ", STREAM); \
1946 assemble_name (STREAM, VALUE); \
1947 fputc ('\n', STREAM); \
1951 /* Macros Controlling Initialization Routines. */
1953 /* This is handled by svr4.h and sysv4.h. */
1956 /* Output of Assembler Instructions. */
1958 /* A C initializer containing the assembler's names for the machine registers,
1959 each one as a C string constant. */
1961 #define REGISTER_NAMES \
1963 /* General registers. */ \
1964 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \
1965 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \
1966 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \
1968 /* Local registers. */ \
1969 "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7", \
1970 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15", \
1971 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23", \
1972 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31", \
1973 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39", \
1974 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47", \
1975 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55", \
1976 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63", \
1977 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71", \
1978 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79", \
1979 /* Input registers. */ \
1980 "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7", \
1981 /* Output registers. */ \
1982 "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7", \
1983 /* Floating-point registers. */ \
1984 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", \
1985 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", \
1986 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", \
1987 "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", \
1988 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", \
1989 "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", \
1990 "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69", \
1991 "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79", \
1992 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89", \
1993 "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99", \
1994 "f100","f101","f102","f103","f104","f105","f106","f107","f108","f109",\
1995 "f110","f111","f112","f113","f114","f115","f116","f117","f118","f119",\
1996 "f120","f121","f122","f123","f124","f125","f126","f127", \
1997 /* Predicate registers. */ \
1998 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", \
1999 "p10", "p11", "p12", "p13", "p14", "p15", "p16", "p17", "p18", "p19", \
2000 "p20", "p21", "p22", "p23", "p24", "p25", "p26", "p27", "p28", "p29", \
2001 "p30", "p31", "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39", \
2002 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47", "p48", "p49", \
2003 "p50", "p51", "p52", "p53", "p54", "p55", "p56", "p57", "p58", "p59", \
2004 "p60", "p61", "p62", "p63", \
2005 /* Branch registers. */ \
2006 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", \
2007 /* Frame pointer. Return address. */ \
2008 "sfp", "retaddr", "ar.ccv", "ar.unat", "ar.pfs", "ar.lc", "ar.ec", \
2011 /* If defined, a C initializer for an array of structures containing a name and
2012 a register number. This macro defines additional names for hard registers,
2013 thus allowing the `asm' option in declarations to refer to registers using
2016 #define ADDITIONAL_REGISTER_NAMES \
2018 { "gp", R_GR (1) }, \
2019 { "sp", R_GR (12) }, \
2020 { "in0", IN_REG (0) }, \
2021 { "in1", IN_REG (1) }, \
2022 { "in2", IN_REG (2) }, \
2023 { "in3", IN_REG (3) }, \
2024 { "in4", IN_REG (4) }, \
2025 { "in5", IN_REG (5) }, \
2026 { "in6", IN_REG (6) }, \
2027 { "in7", IN_REG (7) }, \
2028 { "out0", OUT_REG (0) }, \
2029 { "out1", OUT_REG (1) }, \
2030 { "out2", OUT_REG (2) }, \
2031 { "out3", OUT_REG (3) }, \
2032 { "out4", OUT_REG (4) }, \
2033 { "out5", OUT_REG (5) }, \
2034 { "out6", OUT_REG (6) }, \
2035 { "out7", OUT_REG (7) }, \
2036 { "loc0", LOC_REG (0) }, \
2037 { "loc1", LOC_REG (1) }, \
2038 { "loc2", LOC_REG (2) }, \
2039 { "loc3", LOC_REG (3) }, \
2040 { "loc4", LOC_REG (4) }, \
2041 { "loc5", LOC_REG (5) }, \
2042 { "loc6", LOC_REG (6) }, \
2043 { "loc7", LOC_REG (7) }, \
2044 { "loc8", LOC_REG (8) }, \
2045 { "loc9", LOC_REG (9) }, \
2046 { "loc10", LOC_REG (10) }, \
2047 { "loc11", LOC_REG (11) }, \
2048 { "loc12", LOC_REG (12) }, \
2049 { "loc13", LOC_REG (13) }, \
2050 { "loc14", LOC_REG (14) }, \
2051 { "loc15", LOC_REG (15) }, \
2052 { "loc16", LOC_REG (16) }, \
2053 { "loc17", LOC_REG (17) }, \
2054 { "loc18", LOC_REG (18) }, \
2055 { "loc19", LOC_REG (19) }, \
2056 { "loc20", LOC_REG (20) }, \
2057 { "loc21", LOC_REG (21) }, \
2058 { "loc22", LOC_REG (22) }, \
2059 { "loc23", LOC_REG (23) }, \
2060 { "loc24", LOC_REG (24) }, \
2061 { "loc25", LOC_REG (25) }, \
2062 { "loc26", LOC_REG (26) }, \
2063 { "loc27", LOC_REG (27) }, \
2064 { "loc28", LOC_REG (28) }, \
2065 { "loc29", LOC_REG (29) }, \
2066 { "loc30", LOC_REG (30) }, \
2067 { "loc31", LOC_REG (31) }, \
2068 { "loc32", LOC_REG (32) }, \
2069 { "loc33", LOC_REG (33) }, \
2070 { "loc34", LOC_REG (34) }, \
2071 { "loc35", LOC_REG (35) }, \
2072 { "loc36", LOC_REG (36) }, \
2073 { "loc37", LOC_REG (37) }, \
2074 { "loc38", LOC_REG (38) }, \
2075 { "loc39", LOC_REG (39) }, \
2076 { "loc40", LOC_REG (40) }, \
2077 { "loc41", LOC_REG (41) }, \
2078 { "loc42", LOC_REG (42) }, \
2079 { "loc43", LOC_REG (43) }, \
2080 { "loc44", LOC_REG (44) }, \
2081 { "loc45", LOC_REG (45) }, \
2082 { "loc46", LOC_REG (46) }, \
2083 { "loc47", LOC_REG (47) }, \
2084 { "loc48", LOC_REG (48) }, \
2085 { "loc49", LOC_REG (49) }, \
2086 { "loc50", LOC_REG (50) }, \
2087 { "loc51", LOC_REG (51) }, \
2088 { "loc52", LOC_REG (52) }, \
2089 { "loc53", LOC_REG (53) }, \
2090 { "loc54", LOC_REG (54) }, \
2091 { "loc55", LOC_REG (55) }, \
2092 { "loc56", LOC_REG (56) }, \
2093 { "loc57", LOC_REG (57) }, \
2094 { "loc58", LOC_REG (58) }, \
2095 { "loc59", LOC_REG (59) }, \
2096 { "loc60", LOC_REG (60) }, \
2097 { "loc61", LOC_REG (61) }, \
2098 { "loc62", LOC_REG (62) }, \
2099 { "loc63", LOC_REG (63) }, \
2100 { "loc64", LOC_REG (64) }, \
2101 { "loc65", LOC_REG (65) }, \
2102 { "loc66", LOC_REG (66) }, \
2103 { "loc67", LOC_REG (67) }, \
2104 { "loc68", LOC_REG (68) }, \
2105 { "loc69", LOC_REG (69) }, \
2106 { "loc70", LOC_REG (70) }, \
2107 { "loc71", LOC_REG (71) }, \
2108 { "loc72", LOC_REG (72) }, \
2109 { "loc73", LOC_REG (73) }, \
2110 { "loc74", LOC_REG (74) }, \
2111 { "loc75", LOC_REG (75) }, \
2112 { "loc76", LOC_REG (76) }, \
2113 { "loc77", LOC_REG (77) }, \
2114 { "loc78", LOC_REG (78) }, \
2115 { "loc79", LOC_REG (79) }, \
2118 /* A C compound statement to output to stdio stream STREAM the assembler syntax
2119 for an instruction operand X. X is an RTL expression. */
2121 #define PRINT_OPERAND(STREAM, X, CODE) \
2122 ia64_print_operand (STREAM, X, CODE)
2124 /* A C expression which evaluates to true if CODE is a valid punctuation
2125 character for use in the `PRINT_OPERAND' macro. */
2127 /* ??? Keep this around for now, as we might need it later. */
2129 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2130 ((CODE) == '+' || (CODE) == ',')
2132 /* A C compound statement to output to stdio stream STREAM the assembler syntax
2133 for an instruction operand that is a memory reference whose address is X. X
2134 is an RTL expression. */
2136 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2137 ia64_print_operand_address (STREAM, X)
2139 /* If defined, C string expressions to be used for the `%R', `%L', `%U', and
2140 `%I' options of `asm_fprintf' (see `final.c'). */
2142 #define REGISTER_PREFIX ""
2143 #define LOCAL_LABEL_PREFIX "."
2144 #define USER_LABEL_PREFIX ""
2145 #define IMMEDIATE_PREFIX ""
2148 /* Output of dispatch tables. */
2150 /* This macro should be provided on machines where the addresses in a dispatch
2151 table are relative to the table's own address. */
2153 /* ??? Depends on the pointer size. */
2155 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2156 fprintf (STREAM, "\tdata8 @pcrel(.L%d)\n", VALUE)
2158 /* This is how to output an element of a case-vector that is absolute.
2159 (Ia64 does not use such vectors, but we must define this macro anyway.) */
2161 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) abort ()
2163 /* Jump tables only need 8 byte alignment. */
2165 #define ADDR_VEC_ALIGN(ADDR_VEC) 3
2168 /* Assembler Commands for Exception Regions. */
2170 /* Select a format to encode pointers in exception handling data. CODE
2171 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2172 true if the symbol may be affected by dynamic relocations. */
2173 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2174 (((CODE) == 1 ? DW_EH_PE_textrel : DW_EH_PE_datarel) \
2175 | ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_udata8)
2177 /* Handle special EH pointer encodings. Absolute, pc-relative, and
2178 indirect are handled automatically. */
2179 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
2181 const char *reltag = NULL; \
2182 if (((ENCODING) & 0xF0) == DW_EH_PE_textrel) \
2183 reltag = "@segrel("; \
2184 else if (((ENCODING) & 0xF0) == DW_EH_PE_datarel) \
2185 reltag = "@gprel("; \
2188 fputs (integer_asm_op (SIZE, FALSE), FILE); \
2189 fputs (reltag, FILE); \
2190 assemble_name (FILE, XSTR (ADDR, 0)); \
2191 fputc (')', FILE); \
2197 /* Assembler Commands for Alignment. */
2199 /* ??? Investigate. */
2201 /* The alignment (log base 2) to put in front of LABEL, which follows
2204 /* #define LABEL_ALIGN_AFTER_BARRIER(LABEL) */
2206 /* The desired alignment for the location counter at the beginning
2209 /* #define LOOP_ALIGN(LABEL) */
2211 /* Define this macro if `ASM_OUTPUT_SKIP' should not be used in the text
2212 section because it fails put zeros in the bytes that are skipped. */
2214 #define ASM_NO_SKIP_IN_TEXT 1
2216 /* A C statement to output to the stdio stream STREAM an assembler command to
2217 advance the location counter to a multiple of 2 to the POWER bytes. */
2219 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
2220 fprintf (STREAM, "\t.align %d\n", 1<<(POWER))
2223 /* Macros Affecting all Debug Formats. */
2225 /* This is handled in svr4.h and sysv4.h. */
2228 /* Specific Options for DBX Output. */
2230 /* This is handled by dbxelf.h which is included by svr4.h. */
2233 /* Open ended Hooks for DBX Output. */
2238 /* File names in DBX format. */
2243 /* Macros for SDB and Dwarf Output. */
2245 /* Define this macro if GNU CC should produce dwarf version 2 format debugging
2246 output in response to the `-g' option. */
2248 #define DWARF2_DEBUGGING_INFO
2250 #define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DWARF2_ASM)
2252 /* Use tags for debug info labels, so that they don't break instruction
2253 bundles. This also avoids getting spurious DV warnings from the
2254 assembler. This is similar to ASM_OUTPUT_INTERNAL_LABEL, except that we
2255 add brackets around the label. */
2257 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2258 fprintf (FILE, "[.%s%d:]\n", PREFIX, NUM)
2260 /* Use section-relative relocations for debugging offsets. Unlike other
2261 targets that fake this by putting the section VMA at 0, IA-64 has
2262 proper relocations for them. */
2263 #define ASM_OUTPUT_DWARF_OFFSET(FILE, SIZE, LABEL) \
2265 fputs (integer_asm_op (SIZE, FALSE), FILE); \
2266 fputs ("@secrel(", FILE); \
2267 assemble_name (FILE, LABEL); \
2268 fputc (')', FILE); \
2271 /* Emit a PC-relative relocation. */
2272 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
2274 fputs (integer_asm_op (SIZE, FALSE), FILE); \
2275 fputs ("@pcrel(", FILE); \
2276 assemble_name (FILE, LABEL); \
2277 fputc (')', FILE); \
2280 /* Cross Compilation and Floating Point. */
2282 /* Define to enable software floating point emulation. */
2283 #define REAL_ARITHMETIC
2286 /* Register Renaming Parameters. */
2288 /* A C expression that is nonzero if hard register number REGNO2 can be
2289 considered for use as a rename register for REGNO1 */
2291 #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \
2292 ia64_hard_regno_rename_ok((REGNO1), (REGNO2))
2295 /* Miscellaneous Parameters. */
2297 /* Define this if you have defined special-purpose predicates in the file
2298 `MACHINE.c'. For each predicate, list all rtl codes that can be in
2299 expressions matched by the predicate. */
2301 #define PREDICATE_CODES \
2302 { "call_operand", {SUBREG, REG, SYMBOL_REF}}, \
2303 { "got_symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2304 { "sdata_symbolic_operand", {SYMBOL_REF, CONST}}, \
2305 { "symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2306 { "function_operand", {SYMBOL_REF}}, \
2307 { "setjmp_operand", {SYMBOL_REF}}, \
2308 { "destination_operand", {SUBREG, REG, MEM}}, \
2309 { "not_postinc_memory_operand", {MEM}}, \
2310 { "move_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2311 CONSTANT_P_RTX, SYMBOL_REF, CONST, LABEL_REF}}, \
2312 { "gr_register_operand", {SUBREG, REG}}, \
2313 { "fr_register_operand", {SUBREG, REG}}, \
2314 { "grfr_register_operand", {SUBREG, REG}}, \
2315 { "gr_nonimmediate_operand", {SUBREG, REG, MEM}}, \
2316 { "fr_nonimmediate_operand", {SUBREG, REG, MEM}}, \
2317 { "grfr_nonimmediate_operand", {SUBREG, REG, MEM}}, \
2318 { "gr_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
2319 { "gr_reg_or_5bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2320 { "gr_reg_or_6bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2321 { "gr_reg_or_8bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2322 { "grfr_reg_or_8bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2323 { "gr_reg_or_8bit_adjusted_operand", {SUBREG, REG, CONST_INT, \
2325 { "gr_reg_or_8bit_and_adjusted_operand", {SUBREG, REG, CONST_INT, \
2327 { "gr_reg_or_14bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2328 { "gr_reg_or_22bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2329 { "shift_count_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2330 { "shift_32bit_count_operand", {SUBREG, REG, CONST_INT, \
2332 { "shladd_operand", {CONST_INT}}, \
2333 { "fetchadd_operand", {CONST_INT}}, \
2334 { "fr_reg_or_fp01_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2335 { "normal_comparison_operator", {EQ, NE, GT, LE, GTU, LEU}}, \
2336 { "adjusted_comparison_operator", {LT, GE, LTU, GEU}}, \
2337 { "signed_inequality_operator", {GE, GT, LE, LT}}, \
2338 { "predicate_operator", {NE, EQ}}, \
2339 { "condop_operator", {PLUS, MINUS, IOR, XOR, AND}}, \
2340 { "ar_lc_reg_operand", {REG}}, \
2341 { "ar_ccv_reg_operand", {REG}}, \
2342 { "ar_pfs_reg_operand", {REG}}, \
2343 { "general_tfmode_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2344 { "destination_tfmode_operand", {SUBREG, REG, MEM}}, \
2345 { "tfreg_or_fp01_operand", {REG, CONST_DOUBLE}},
2347 /* An alias for a machine mode name. This is the machine mode that elements of
2348 a jump-table should have. */
2350 #define CASE_VECTOR_MODE Pmode
2352 /* Define as C expression which evaluates to nonzero if the tablejump
2353 instruction expects the table to contain offsets from the address of the
2356 #define CASE_VECTOR_PC_RELATIVE 1
2358 /* Define this macro if operations between registers with integral mode smaller
2359 than a word are always performed on the entire register. */
2361 #define WORD_REGISTER_OPERATIONS
2363 /* Define this macro to be a C expression indicating when insns that read
2364 memory in MODE, an integral mode narrower than a word, set the bits outside
2365 of MODE to be either the sign-extension or the zero-extension of the data
2368 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2370 /* The maximum number of bytes that a single instruction can move quickly from
2371 memory to memory. */
2374 /* A C expression which is nonzero if on this machine it is safe to "convert"
2375 an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller
2376 than INPREC) by merely operating on it as if it had only OUTPREC bits. */
2378 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2380 /* A C expression describing the value returned by a comparison operator with
2381 an integral mode and stored by a store-flag instruction (`sCOND') when the
2382 condition is true. */
2384 /* ??? Investigate using -1 instead of 1. */
2386 #define STORE_FLAG_VALUE 1
2388 /* An alias for the machine mode for pointers. */
2390 /* ??? This would change if we had ILP32 support. */
2392 #define Pmode DImode
2394 /* An alias for the machine mode used for memory references to functions being
2395 called, in `call' RTL expressions. */
2397 #define FUNCTION_MODE Pmode
2399 /* Define this macro to handle System V style pragmas: #pragma pack and
2400 #pragma weak. Note, #pragma weak will only be supported if SUPPORT_WEAK is
2403 /* If this architecture supports prefetch, define this to be the number of
2404 prefetch commands that can be executed in parallel.
2406 ??? This number is bogus and needs to be replaced before the value is
2407 actually used in optimizations. */
2409 #define SIMULTANEOUS_PREFETCHES 6
2411 /* If this architecture supports prefetch, define this to be the size of
2412 the cache line that is prefetched. */
2414 #define PREFETCH_BLOCK 32
2416 #define HANDLE_SYSV_PRAGMA
2418 /* In rare cases, correct code generation requires extra machine dependent
2419 processing between the second jump optimization pass and delayed branch
2420 scheduling. On those machines, define this macro as a C statement to act on
2421 the code starting at INSN. */
2423 #define MACHINE_DEPENDENT_REORG(INSN) ia64_reorg (INSN)
2425 /* A C expression for the maximum number of instructions to execute via
2426 conditional execution instructions instead of a branch. A value of
2427 BRANCH_COST+1 is the default if the machine does not use
2428 cc0, and 1 if it does use cc0. */
2429 /* ??? Investigate. */
2430 #define MAX_CONDITIONAL_EXECUTE 12
2432 extern int ia64_final_schedule;
2434 #define IA64_UNWIND_INFO 1
2435 #define IA64_UNWIND_EMIT(f,i) process_for_unwind_directive (f,i)
2437 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 15 : INVALID_REGNUM)
2439 /* This function contains machine specific function data. */
2440 struct machine_function
2442 /* The new stack pointer when unwinding from EH. */
2443 struct rtx_def* ia64_eh_epilogue_sp;
2445 /* The new bsp value when unwinding from EH. */
2446 struct rtx_def* ia64_eh_epilogue_bsp;
2448 /* The GP value save register. */
2449 struct rtx_def* ia64_gp_save;
2451 /* The number of varargs registers to save. */
2458 IA64_BUILTIN_SYNCHRONIZE,
2460 IA64_BUILTIN_FETCH_AND_ADD_SI,
2461 IA64_BUILTIN_FETCH_AND_SUB_SI,
2462 IA64_BUILTIN_FETCH_AND_OR_SI,
2463 IA64_BUILTIN_FETCH_AND_AND_SI,
2464 IA64_BUILTIN_FETCH_AND_XOR_SI,
2465 IA64_BUILTIN_FETCH_AND_NAND_SI,
2467 IA64_BUILTIN_ADD_AND_FETCH_SI,
2468 IA64_BUILTIN_SUB_AND_FETCH_SI,
2469 IA64_BUILTIN_OR_AND_FETCH_SI,
2470 IA64_BUILTIN_AND_AND_FETCH_SI,
2471 IA64_BUILTIN_XOR_AND_FETCH_SI,
2472 IA64_BUILTIN_NAND_AND_FETCH_SI,
2474 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI,
2475 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI,
2477 IA64_BUILTIN_SYNCHRONIZE_SI,
2479 IA64_BUILTIN_LOCK_TEST_AND_SET_SI,
2481 IA64_BUILTIN_LOCK_RELEASE_SI,
2483 IA64_BUILTIN_FETCH_AND_ADD_DI,
2484 IA64_BUILTIN_FETCH_AND_SUB_DI,
2485 IA64_BUILTIN_FETCH_AND_OR_DI,
2486 IA64_BUILTIN_FETCH_AND_AND_DI,
2487 IA64_BUILTIN_FETCH_AND_XOR_DI,
2488 IA64_BUILTIN_FETCH_AND_NAND_DI,
2490 IA64_BUILTIN_ADD_AND_FETCH_DI,
2491 IA64_BUILTIN_SUB_AND_FETCH_DI,
2492 IA64_BUILTIN_OR_AND_FETCH_DI,
2493 IA64_BUILTIN_AND_AND_FETCH_DI,
2494 IA64_BUILTIN_XOR_AND_FETCH_DI,
2495 IA64_BUILTIN_NAND_AND_FETCH_DI,
2497 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI,
2498 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI,
2500 IA64_BUILTIN_SYNCHRONIZE_DI,
2502 IA64_BUILTIN_LOCK_TEST_AND_SET_DI,
2504 IA64_BUILTIN_LOCK_RELEASE_DI,
2507 IA64_BUILTIN_FLUSHRS
2510 /* Codes for expand_compare_and_swap and expand_swap_and_compare. */
2512 IA64_ADD_OP, IA64_SUB_OP, IA64_OR_OP, IA64_AND_OP, IA64_XOR_OP, IA64_NAND_OP
OSDN Git Service
