1 /* Definitions of target machine for GNU compiler.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
3 Free Software Foundation, Inc.
4 Contributed by James E. Wilson <wilson@cygnus.com> and
5 David Mosberger <davidm@hpl.hp.com>.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
22 Boston, MA 02110-1301, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
46 #include "sched-int.h"
49 #include "target-def.h"
52 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "tree-gimple.h"
59 /* This is used for communication between ASM_OUTPUT_LABEL and
60 ASM_OUTPUT_LABELREF. */
61 int ia64_asm_output_label = 0;
63 /* Define the information needed to generate branch and scc insns. This is
64 stored from the compare operation. */
65 struct rtx_def * ia64_compare_op0;
66 struct rtx_def * ia64_compare_op1;
68 /* Register names for ia64_expand_prologue. */
69 static const char * const ia64_reg_numbers[96] =
70 { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
71 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
72 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
73 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
74 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
75 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
76 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
77 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
78 "r96", "r97", "r98", "r99", "r100","r101","r102","r103",
79 "r104","r105","r106","r107","r108","r109","r110","r111",
80 "r112","r113","r114","r115","r116","r117","r118","r119",
81 "r120","r121","r122","r123","r124","r125","r126","r127"};
83 /* ??? These strings could be shared with REGISTER_NAMES. */
84 static const char * const ia64_input_reg_names[8] =
85 { "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7" };
87 /* ??? These strings could be shared with REGISTER_NAMES. */
88 static const char * const ia64_local_reg_names[80] =
89 { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7",
90 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15",
91 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23",
92 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31",
93 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39",
94 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47",
95 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55",
96 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63",
97 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71",
98 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" };
100 /* ??? These strings could be shared with REGISTER_NAMES. */
101 static const char * const ia64_output_reg_names[8] =
102 { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" };
104 /* Which cpu are we scheduling for. */
105 enum processor_type ia64_tune = PROCESSOR_ITANIUM2;
107 /* Determines whether we run our final scheduling pass or not. We always
108 avoid the normal second scheduling pass. */
109 static int ia64_flag_schedule_insns2;
111 /* Determines whether we run variable tracking in machine dependent
113 static int ia64_flag_var_tracking;
115 /* Variables which are this size or smaller are put in the sdata/sbss
118 unsigned int ia64_section_threshold;
120 /* The following variable is used by the DFA insn scheduler. The value is
121 TRUE if we do insn bundling instead of insn scheduling. */
124 /* Structure to be filled in by ia64_compute_frame_size with register
125 save masks and offsets for the current function. */
127 struct ia64_frame_info
129 HOST_WIDE_INT total_size; /* size of the stack frame, not including
130 the caller's scratch area. */
131 HOST_WIDE_INT spill_cfa_off; /* top of the reg spill area from the cfa. */
132 HOST_WIDE_INT spill_size; /* size of the gr/br/fr spill area. */
133 HOST_WIDE_INT extra_spill_size; /* size of spill area for others. */
134 HARD_REG_SET mask; /* mask of saved registers. */
135 unsigned int gr_used_mask; /* mask of registers in use as gr spill
136 registers or long-term scratches. */
137 int n_spilled; /* number of spilled registers. */
138 int reg_fp; /* register for fp. */
139 int reg_save_b0; /* save register for b0. */
140 int reg_save_pr; /* save register for prs. */
141 int reg_save_ar_pfs; /* save register for ar.pfs. */
142 int reg_save_ar_unat; /* save register for ar.unat. */
143 int reg_save_ar_lc; /* save register for ar.lc. */
144 int reg_save_gp; /* save register for gp. */
145 int n_input_regs; /* number of input registers used. */
146 int n_local_regs; /* number of local registers used. */
147 int n_output_regs; /* number of output registers used. */
148 int n_rotate_regs; /* number of rotating registers used. */
150 char need_regstk; /* true if a .regstk directive needed. */
151 char initialized; /* true if the data is finalized. */
154 /* Current frame information calculated by ia64_compute_frame_size. */
155 static struct ia64_frame_info current_frame_info;
157 static int ia64_first_cycle_multipass_dfa_lookahead (void);
158 static void ia64_dependencies_evaluation_hook (rtx, rtx);
159 static void ia64_init_dfa_pre_cycle_insn (void);
160 static rtx ia64_dfa_pre_cycle_insn (void);
161 static int ia64_first_cycle_multipass_dfa_lookahead_guard (rtx);
162 static bool ia64_first_cycle_multipass_dfa_lookahead_guard_spec (rtx);
163 static int ia64_dfa_new_cycle (FILE *, int, rtx, int, int, int *);
164 static void ia64_h_i_d_extended (void);
165 static int ia64_mode_to_int (enum machine_mode);
166 static void ia64_set_sched_flags (spec_info_t);
167 static int ia64_speculate_insn (rtx, ds_t, rtx *);
168 static rtx ia64_gen_spec_insn (rtx, ds_t, int, bool, bool);
169 static bool ia64_needs_block_p (rtx);
170 static rtx ia64_gen_check (rtx, rtx, bool);
171 static int ia64_spec_check_p (rtx);
172 static int ia64_spec_check_src_p (rtx);
173 static rtx gen_tls_get_addr (void);
174 static rtx gen_thread_pointer (void);
175 static int find_gr_spill (int);
176 static int next_scratch_gr_reg (void);
177 static void mark_reg_gr_used_mask (rtx, void *);
178 static void ia64_compute_frame_size (HOST_WIDE_INT);
179 static void setup_spill_pointers (int, rtx, HOST_WIDE_INT);
180 static void finish_spill_pointers (void);
181 static rtx spill_restore_mem (rtx, HOST_WIDE_INT);
182 static void do_spill (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT, rtx);
183 static void do_restore (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT);
184 static rtx gen_movdi_x (rtx, rtx, rtx);
185 static rtx gen_fr_spill_x (rtx, rtx, rtx);
186 static rtx gen_fr_restore_x (rtx, rtx, rtx);
188 static enum machine_mode hfa_element_mode (tree, bool);
189 static void ia64_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
191 static int ia64_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
193 static bool ia64_function_ok_for_sibcall (tree, tree);
194 static bool ia64_return_in_memory (tree, tree);
195 static bool ia64_rtx_costs (rtx, int, int, int *);
196 static void fix_range (const char *);
197 static bool ia64_handle_option (size_t, const char *, int);
198 static struct machine_function * ia64_init_machine_status (void);
199 static void emit_insn_group_barriers (FILE *);
200 static void emit_all_insn_group_barriers (FILE *);
201 static void final_emit_insn_group_barriers (FILE *);
202 static void emit_predicate_relation_info (void);
203 static void ia64_reorg (void);
204 static bool ia64_in_small_data_p (tree);
205 static void process_epilogue (FILE *, rtx, bool, bool);
206 static int process_set (FILE *, rtx, rtx, bool, bool);
208 static bool ia64_assemble_integer (rtx, unsigned int, int);
209 static void ia64_output_function_prologue (FILE *, HOST_WIDE_INT);
210 static void ia64_output_function_epilogue (FILE *, HOST_WIDE_INT);
211 static void ia64_output_function_end_prologue (FILE *);
213 static int ia64_issue_rate (void);
214 static int ia64_adjust_cost_2 (rtx, int, rtx, int);
215 static void ia64_sched_init (FILE *, int, int);
216 static void ia64_sched_init_global (FILE *, int, int);
217 static void ia64_sched_finish_global (FILE *, int);
218 static void ia64_sched_finish (FILE *, int);
219 static int ia64_dfa_sched_reorder (FILE *, int, rtx *, int *, int, int);
220 static int ia64_sched_reorder (FILE *, int, rtx *, int *, int);
221 static int ia64_sched_reorder2 (FILE *, int, rtx *, int *, int);
222 static int ia64_variable_issue (FILE *, int, rtx, int);
224 static struct bundle_state *get_free_bundle_state (void);
225 static void free_bundle_state (struct bundle_state *);
226 static void initiate_bundle_states (void);
227 static void finish_bundle_states (void);
228 static unsigned bundle_state_hash (const void *);
229 static int bundle_state_eq_p (const void *, const void *);
230 static int insert_bundle_state (struct bundle_state *);
231 static void initiate_bundle_state_table (void);
232 static void finish_bundle_state_table (void);
233 static int try_issue_nops (struct bundle_state *, int);
234 static int try_issue_insn (struct bundle_state *, rtx);
235 static void issue_nops_and_insn (struct bundle_state *, int, rtx, int, int);
236 static int get_max_pos (state_t);
237 static int get_template (state_t, int);
239 static rtx get_next_important_insn (rtx, rtx);
240 static void bundling (FILE *, int, rtx, rtx);
242 static void ia64_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
243 HOST_WIDE_INT, tree);
244 static void ia64_file_start (void);
245 static void ia64_globalize_decl_name (FILE *, tree);
247 static section *ia64_select_rtx_section (enum machine_mode, rtx,
248 unsigned HOST_WIDE_INT);
249 static void ia64_output_dwarf_dtprel (FILE *, int, rtx)
251 static section *ia64_rwreloc_select_section (tree, int, unsigned HOST_WIDE_INT)
253 static void ia64_rwreloc_unique_section (tree, int)
255 static section *ia64_rwreloc_select_rtx_section (enum machine_mode, rtx,
256 unsigned HOST_WIDE_INT)
258 static unsigned int ia64_section_type_flags (tree, const char *, int);
259 static void ia64_init_libfuncs (void)
261 static void ia64_hpux_init_libfuncs (void)
263 static void ia64_sysv4_init_libfuncs (void)
265 static void ia64_vms_init_libfuncs (void)
268 static tree ia64_handle_model_attribute (tree *, tree, tree, int, bool *);
269 static tree ia64_handle_version_id_attribute (tree *, tree, tree, int, bool *);
270 static void ia64_encode_section_info (tree, rtx, int);
271 static rtx ia64_struct_value_rtx (tree, int);
272 static tree ia64_gimplify_va_arg (tree, tree, tree *, tree *);
273 static bool ia64_scalar_mode_supported_p (enum machine_mode mode);
274 static bool ia64_vector_mode_supported_p (enum machine_mode mode);
275 static bool ia64_cannot_force_const_mem (rtx);
276 static const char *ia64_mangle_fundamental_type (tree);
277 static const char *ia64_invalid_conversion (tree, tree);
278 static const char *ia64_invalid_unary_op (int, tree);
279 static const char *ia64_invalid_binary_op (int, tree, tree);
281 /* Table of valid machine attributes. */
282 static const struct attribute_spec ia64_attribute_table[] =
284 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
285 { "syscall_linkage", 0, 0, false, true, true, NULL },
286 { "model", 1, 1, true, false, false, ia64_handle_model_attribute },
287 { "version_id", 1, 1, true, false, false,
288 ia64_handle_version_id_attribute },
289 { NULL, 0, 0, false, false, false, NULL }
292 /* Initialize the GCC target structure. */
293 #undef TARGET_ATTRIBUTE_TABLE
294 #define TARGET_ATTRIBUTE_TABLE ia64_attribute_table
296 #undef TARGET_INIT_BUILTINS
297 #define TARGET_INIT_BUILTINS ia64_init_builtins
299 #undef TARGET_EXPAND_BUILTIN
300 #define TARGET_EXPAND_BUILTIN ia64_expand_builtin
302 #undef TARGET_ASM_BYTE_OP
303 #define TARGET_ASM_BYTE_OP "\tdata1\t"
304 #undef TARGET_ASM_ALIGNED_HI_OP
305 #define TARGET_ASM_ALIGNED_HI_OP "\tdata2\t"
306 #undef TARGET_ASM_ALIGNED_SI_OP
307 #define TARGET_ASM_ALIGNED_SI_OP "\tdata4\t"
308 #undef TARGET_ASM_ALIGNED_DI_OP
309 #define TARGET_ASM_ALIGNED_DI_OP "\tdata8\t"
310 #undef TARGET_ASM_UNALIGNED_HI_OP
311 #define TARGET_ASM_UNALIGNED_HI_OP "\tdata2.ua\t"
312 #undef TARGET_ASM_UNALIGNED_SI_OP
313 #define TARGET_ASM_UNALIGNED_SI_OP "\tdata4.ua\t"
314 #undef TARGET_ASM_UNALIGNED_DI_OP
315 #define TARGET_ASM_UNALIGNED_DI_OP "\tdata8.ua\t"
316 #undef TARGET_ASM_INTEGER
317 #define TARGET_ASM_INTEGER ia64_assemble_integer
319 #undef TARGET_ASM_FUNCTION_PROLOGUE
320 #define TARGET_ASM_FUNCTION_PROLOGUE ia64_output_function_prologue
321 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
322 #define TARGET_ASM_FUNCTION_END_PROLOGUE ia64_output_function_end_prologue
323 #undef TARGET_ASM_FUNCTION_EPILOGUE
324 #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue
326 #undef TARGET_IN_SMALL_DATA_P
327 #define TARGET_IN_SMALL_DATA_P ia64_in_small_data_p
329 #undef TARGET_SCHED_ADJUST_COST_2
330 #define TARGET_SCHED_ADJUST_COST_2 ia64_adjust_cost_2
331 #undef TARGET_SCHED_ISSUE_RATE
332 #define TARGET_SCHED_ISSUE_RATE ia64_issue_rate
333 #undef TARGET_SCHED_VARIABLE_ISSUE
334 #define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue
335 #undef TARGET_SCHED_INIT
336 #define TARGET_SCHED_INIT ia64_sched_init
337 #undef TARGET_SCHED_FINISH
338 #define TARGET_SCHED_FINISH ia64_sched_finish
339 #undef TARGET_SCHED_INIT_GLOBAL
340 #define TARGET_SCHED_INIT_GLOBAL ia64_sched_init_global
341 #undef TARGET_SCHED_FINISH_GLOBAL
342 #define TARGET_SCHED_FINISH_GLOBAL ia64_sched_finish_global
343 #undef TARGET_SCHED_REORDER
344 #define TARGET_SCHED_REORDER ia64_sched_reorder
345 #undef TARGET_SCHED_REORDER2
346 #define TARGET_SCHED_REORDER2 ia64_sched_reorder2
348 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
349 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ia64_dependencies_evaluation_hook
351 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
352 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ia64_first_cycle_multipass_dfa_lookahead
354 #undef TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN
355 #define TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN ia64_init_dfa_pre_cycle_insn
356 #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN
357 #define TARGET_SCHED_DFA_PRE_CYCLE_INSN ia64_dfa_pre_cycle_insn
359 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
360 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD\
361 ia64_first_cycle_multipass_dfa_lookahead_guard
363 #undef TARGET_SCHED_DFA_NEW_CYCLE
364 #define TARGET_SCHED_DFA_NEW_CYCLE ia64_dfa_new_cycle
366 #undef TARGET_SCHED_H_I_D_EXTENDED
367 #define TARGET_SCHED_H_I_D_EXTENDED ia64_h_i_d_extended
369 #undef TARGET_SCHED_SET_SCHED_FLAGS
370 #define TARGET_SCHED_SET_SCHED_FLAGS ia64_set_sched_flags
372 #undef TARGET_SCHED_SPECULATE_INSN
373 #define TARGET_SCHED_SPECULATE_INSN ia64_speculate_insn
375 #undef TARGET_SCHED_NEEDS_BLOCK_P
376 #define TARGET_SCHED_NEEDS_BLOCK_P ia64_needs_block_p
378 #undef TARGET_SCHED_GEN_CHECK
379 #define TARGET_SCHED_GEN_CHECK ia64_gen_check
381 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD_SPEC
382 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD_SPEC\
383 ia64_first_cycle_multipass_dfa_lookahead_guard_spec
385 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
386 #define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall
387 #undef TARGET_ARG_PARTIAL_BYTES
388 #define TARGET_ARG_PARTIAL_BYTES ia64_arg_partial_bytes
390 #undef TARGET_ASM_OUTPUT_MI_THUNK
391 #define TARGET_ASM_OUTPUT_MI_THUNK ia64_output_mi_thunk
392 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
393 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
395 #undef TARGET_ASM_FILE_START
396 #define TARGET_ASM_FILE_START ia64_file_start
398 #undef TARGET_ASM_GLOBALIZE_DECL_NAME
399 #define TARGET_ASM_GLOBALIZE_DECL_NAME ia64_globalize_decl_name
401 #undef TARGET_RTX_COSTS
402 #define TARGET_RTX_COSTS ia64_rtx_costs
403 #undef TARGET_ADDRESS_COST
404 #define TARGET_ADDRESS_COST hook_int_rtx_0
406 #undef TARGET_MACHINE_DEPENDENT_REORG
407 #define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg
409 #undef TARGET_ENCODE_SECTION_INFO
410 #define TARGET_ENCODE_SECTION_INFO ia64_encode_section_info
412 #undef TARGET_SECTION_TYPE_FLAGS
413 #define TARGET_SECTION_TYPE_FLAGS ia64_section_type_flags
416 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
417 #define TARGET_ASM_OUTPUT_DWARF_DTPREL ia64_output_dwarf_dtprel
420 /* ??? ABI doesn't allow us to define this. */
422 #undef TARGET_PROMOTE_FUNCTION_ARGS
423 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
426 /* ??? ABI doesn't allow us to define this. */
428 #undef TARGET_PROMOTE_FUNCTION_RETURN
429 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
432 /* ??? Investigate. */
434 #undef TARGET_PROMOTE_PROTOTYPES
435 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
438 #undef TARGET_STRUCT_VALUE_RTX
439 #define TARGET_STRUCT_VALUE_RTX ia64_struct_value_rtx
440 #undef TARGET_RETURN_IN_MEMORY
441 #define TARGET_RETURN_IN_MEMORY ia64_return_in_memory
442 #undef TARGET_SETUP_INCOMING_VARARGS
443 #define TARGET_SETUP_INCOMING_VARARGS ia64_setup_incoming_varargs
444 #undef TARGET_STRICT_ARGUMENT_NAMING
445 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
446 #undef TARGET_MUST_PASS_IN_STACK
447 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
449 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
450 #define TARGET_GIMPLIFY_VA_ARG_EXPR ia64_gimplify_va_arg
452 #undef TARGET_UNWIND_EMIT
453 #define TARGET_UNWIND_EMIT process_for_unwind_directive
455 #undef TARGET_SCALAR_MODE_SUPPORTED_P
456 #define TARGET_SCALAR_MODE_SUPPORTED_P ia64_scalar_mode_supported_p
457 #undef TARGET_VECTOR_MODE_SUPPORTED_P
458 #define TARGET_VECTOR_MODE_SUPPORTED_P ia64_vector_mode_supported_p
460 /* ia64 architecture manual 4.4.7: ... reads, writes, and flushes may occur
461 in an order different from the specified program order. */
462 #undef TARGET_RELAXED_ORDERING
463 #define TARGET_RELAXED_ORDERING true
465 #undef TARGET_DEFAULT_TARGET_FLAGS
466 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | TARGET_CPU_DEFAULT)
467 #undef TARGET_HANDLE_OPTION
468 #define TARGET_HANDLE_OPTION ia64_handle_option
470 #undef TARGET_CANNOT_FORCE_CONST_MEM
471 #define TARGET_CANNOT_FORCE_CONST_MEM ia64_cannot_force_const_mem
473 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
474 #define TARGET_MANGLE_FUNDAMENTAL_TYPE ia64_mangle_fundamental_type
476 #undef TARGET_INVALID_CONVERSION
477 #define TARGET_INVALID_CONVERSION ia64_invalid_conversion
478 #undef TARGET_INVALID_UNARY_OP
479 #define TARGET_INVALID_UNARY_OP ia64_invalid_unary_op
480 #undef TARGET_INVALID_BINARY_OP
481 #define TARGET_INVALID_BINARY_OP ia64_invalid_binary_op
483 struct gcc_target targetm = TARGET_INITIALIZER;
487 ADDR_AREA_NORMAL, /* normal address area */
488 ADDR_AREA_SMALL /* addressable by "addl" (-2MB < addr < 2MB) */
492 static GTY(()) tree small_ident1;
493 static GTY(()) tree small_ident2;
498 if (small_ident1 == 0)
500 small_ident1 = get_identifier ("small");
501 small_ident2 = get_identifier ("__small__");
505 /* Retrieve the address area that has been chosen for the given decl. */
507 static ia64_addr_area
508 ia64_get_addr_area (tree decl)
512 model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
518 id = TREE_VALUE (TREE_VALUE (model_attr));
519 if (id == small_ident1 || id == small_ident2)
520 return ADDR_AREA_SMALL;
522 return ADDR_AREA_NORMAL;
526 ia64_handle_model_attribute (tree *node, tree name, tree args,
527 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
529 ia64_addr_area addr_area = ADDR_AREA_NORMAL;
531 tree arg, decl = *node;
534 arg = TREE_VALUE (args);
535 if (arg == small_ident1 || arg == small_ident2)
537 addr_area = ADDR_AREA_SMALL;
541 warning (OPT_Wattributes, "invalid argument of %qs attribute",
542 IDENTIFIER_POINTER (name));
543 *no_add_attrs = true;
546 switch (TREE_CODE (decl))
549 if ((DECL_CONTEXT (decl) && TREE_CODE (DECL_CONTEXT (decl))
551 && !TREE_STATIC (decl))
553 error ("%Jan address area attribute cannot be specified for "
554 "local variables", decl);
555 *no_add_attrs = true;
557 area = ia64_get_addr_area (decl);
558 if (area != ADDR_AREA_NORMAL && addr_area != area)
560 error ("address area of %q+D conflicts with previous "
561 "declaration", decl);
562 *no_add_attrs = true;
567 error ("%Jaddress area attribute cannot be specified for functions",
569 *no_add_attrs = true;
573 warning (OPT_Wattributes, "%qs attribute ignored",
574 IDENTIFIER_POINTER (name));
575 *no_add_attrs = true;
583 ia64_encode_addr_area (tree decl, rtx symbol)
587 flags = SYMBOL_REF_FLAGS (symbol);
588 switch (ia64_get_addr_area (decl))
590 case ADDR_AREA_NORMAL: break;
591 case ADDR_AREA_SMALL: flags |= SYMBOL_FLAG_SMALL_ADDR; break;
592 default: gcc_unreachable ();
594 SYMBOL_REF_FLAGS (symbol) = flags;
598 ia64_encode_section_info (tree decl, rtx rtl, int first)
600 default_encode_section_info (decl, rtl, first);
602 /* Careful not to prod global register variables. */
603 if (TREE_CODE (decl) == VAR_DECL
604 && GET_CODE (DECL_RTL (decl)) == MEM
605 && GET_CODE (XEXP (DECL_RTL (decl), 0)) == SYMBOL_REF
606 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
607 ia64_encode_addr_area (decl, XEXP (rtl, 0));
610 /* Implement CONST_OK_FOR_LETTER_P. */
613 ia64_const_ok_for_letter_p (HOST_WIDE_INT value, char c)
618 return CONST_OK_FOR_I (value);
620 return CONST_OK_FOR_J (value);
622 return CONST_OK_FOR_K (value);
624 return CONST_OK_FOR_L (value);
626 return CONST_OK_FOR_M (value);
628 return CONST_OK_FOR_N (value);
630 return CONST_OK_FOR_O (value);
632 return CONST_OK_FOR_P (value);
638 /* Implement CONST_DOUBLE_OK_FOR_LETTER_P. */
641 ia64_const_double_ok_for_letter_p (rtx value, char c)
646 return CONST_DOUBLE_OK_FOR_G (value);
652 /* Implement EXTRA_CONSTRAINT. */
655 ia64_extra_constraint (rtx value, char c)
660 /* Non-volatile memory for FP_REG loads/stores. */
661 return memory_operand(value, VOIDmode) && !MEM_VOLATILE_P (value);
664 /* 1..4 for shladd arguments. */
665 return (GET_CODE (value) == CONST_INT
666 && INTVAL (value) >= 1 && INTVAL (value) <= 4);
669 /* Non-post-inc memory for asms and other unsavory creatures. */
670 return (GET_CODE (value) == MEM
671 && GET_RTX_CLASS (GET_CODE (XEXP (value, 0))) != RTX_AUTOINC
672 && (reload_in_progress || memory_operand (value, VOIDmode)));
675 /* Symbol ref to small-address-area. */
676 return small_addr_symbolic_operand (value, VOIDmode);
680 return value == CONST0_RTX (GET_MODE (value));
683 /* An integer vector, such that conversion to an integer yields a
684 value appropriate for an integer 'J' constraint. */
685 if (GET_CODE (value) == CONST_VECTOR
686 && GET_MODE_CLASS (GET_MODE (value)) == MODE_VECTOR_INT)
688 value = simplify_subreg (DImode, value, GET_MODE (value), 0);
689 return ia64_const_ok_for_letter_p (INTVAL (value), 'J');
694 /* A V2SF vector containing elements that satisfy 'G'. */
696 (GET_CODE (value) == CONST_VECTOR
697 && GET_MODE (value) == V2SFmode
698 && ia64_const_double_ok_for_letter_p (XVECEXP (value, 0, 0), 'G')
699 && ia64_const_double_ok_for_letter_p (XVECEXP (value, 0, 1), 'G'));
706 /* Return 1 if the operands of a move are ok. */
709 ia64_move_ok (rtx dst, rtx src)
711 /* If we're under init_recog_no_volatile, we'll not be able to use
712 memory_operand. So check the code directly and don't worry about
713 the validity of the underlying address, which should have been
714 checked elsewhere anyway. */
715 if (GET_CODE (dst) != MEM)
717 if (GET_CODE (src) == MEM)
719 if (register_operand (src, VOIDmode))
722 /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0. */
723 if (INTEGRAL_MODE_P (GET_MODE (dst)))
724 return src == const0_rtx;
726 return GET_CODE (src) == CONST_DOUBLE && CONST_DOUBLE_OK_FOR_G (src);
729 /* Return 1 if the operands are ok for a floating point load pair. */
732 ia64_load_pair_ok (rtx dst, rtx src)
734 if (GET_CODE (dst) != REG || !FP_REGNO_P (REGNO (dst)))
736 if (GET_CODE (src) != MEM || MEM_VOLATILE_P (src))
738 switch (GET_CODE (XEXP (src, 0)))
747 rtx adjust = XEXP (XEXP (XEXP (src, 0), 1), 1);
749 if (GET_CODE (adjust) != CONST_INT
750 || INTVAL (adjust) != GET_MODE_SIZE (GET_MODE (src)))
761 addp4_optimize_ok (rtx op1, rtx op2)
763 return (basereg_operand (op1, GET_MODE(op1)) !=
764 basereg_operand (op2, GET_MODE(op2)));
767 /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction.
768 Return the length of the field, or <= 0 on failure. */
771 ia64_depz_field_mask (rtx rop, rtx rshift)
773 unsigned HOST_WIDE_INT op = INTVAL (rop);
774 unsigned HOST_WIDE_INT shift = INTVAL (rshift);
776 /* Get rid of the zero bits we're shifting in. */
779 /* We must now have a solid block of 1's at bit 0. */
780 return exact_log2 (op + 1);
783 /* Return the TLS model to use for ADDR. */
785 static enum tls_model
786 tls_symbolic_operand_type (rtx addr)
788 enum tls_model tls_kind = 0;
790 if (GET_CODE (addr) == CONST)
792 if (GET_CODE (XEXP (addr, 0)) == PLUS
793 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF)
794 tls_kind = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (addr, 0), 0));
796 else if (GET_CODE (addr) == SYMBOL_REF)
797 tls_kind = SYMBOL_REF_TLS_MODEL (addr);
802 /* Return true if X is a constant that is valid for some immediate
803 field in an instruction. */
806 ia64_legitimate_constant_p (rtx x)
808 switch (GET_CODE (x))
815 if (GET_MODE (x) == VOIDmode)
817 return CONST_DOUBLE_OK_FOR_G (x);
821 /* ??? Short term workaround for PR 28490. We must make the code here
822 match the code in ia64_expand_move and move_operand, even though they
823 are both technically wrong. */
824 if (tls_symbolic_operand_type (x) == 0)
826 HOST_WIDE_INT addend = 0;
829 if (GET_CODE (op) == CONST
830 && GET_CODE (XEXP (op, 0)) == PLUS
831 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
833 addend = INTVAL (XEXP (XEXP (op, 0), 1));
834 op = XEXP (XEXP (op, 0), 0);
837 if (any_offset_symbol_operand (op, GET_MODE (op))
838 || function_operand (op, GET_MODE (op)))
840 if (aligned_offset_symbol_operand (op, GET_MODE (op)))
841 return (addend & 0x3fff) == 0;
848 enum machine_mode mode = GET_MODE (x);
850 if (mode == V2SFmode)
851 return ia64_extra_constraint (x, 'Y');
853 return (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
854 && GET_MODE_SIZE (mode) <= 8);
862 /* Don't allow TLS addresses to get spilled to memory. */
865 ia64_cannot_force_const_mem (rtx x)
867 return tls_symbolic_operand_type (x) != 0;
870 /* Expand a symbolic constant load. */
873 ia64_expand_load_address (rtx dest, rtx src)
875 gcc_assert (GET_CODE (dest) == REG);
877 /* ILP32 mode still loads 64-bits of data from the GOT. This avoids
878 having to pointer-extend the value afterward. Other forms of address
879 computation below are also more natural to compute as 64-bit quantities.
880 If we've been given an SImode destination register, change it. */
881 if (GET_MODE (dest) != Pmode)
882 dest = gen_rtx_REG_offset (dest, Pmode, REGNO (dest), 0);
886 if (small_addr_symbolic_operand (src, VOIDmode))
890 emit_insn (gen_load_gprel64 (dest, src));
891 else if (GET_CODE (src) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (src))
892 emit_insn (gen_load_fptr (dest, src));
893 else if (sdata_symbolic_operand (src, VOIDmode))
894 emit_insn (gen_load_gprel (dest, src));
897 HOST_WIDE_INT addend = 0;
900 /* We did split constant offsets in ia64_expand_move, and we did try
901 to keep them split in move_operand, but we also allowed reload to
902 rematerialize arbitrary constants rather than spill the value to
903 the stack and reload it. So we have to be prepared here to split
905 if (GET_CODE (src) == CONST)
907 HOST_WIDE_INT hi, lo;
909 hi = INTVAL (XEXP (XEXP (src, 0), 1));
910 lo = ((hi & 0x3fff) ^ 0x2000) - 0x2000;
916 src = plus_constant (XEXP (XEXP (src, 0), 0), hi);
920 tmp = gen_rtx_HIGH (Pmode, src);
921 tmp = gen_rtx_PLUS (Pmode, tmp, pic_offset_table_rtx);
922 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
924 tmp = gen_rtx_LO_SUM (Pmode, dest, src);
925 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
929 tmp = gen_rtx_PLUS (Pmode, dest, GEN_INT (addend));
930 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
937 static GTY(()) rtx gen_tls_tga;
939 gen_tls_get_addr (void)
942 gen_tls_tga = init_one_libfunc ("__tls_get_addr");
946 static GTY(()) rtx thread_pointer_rtx;
948 gen_thread_pointer (void)
950 if (!thread_pointer_rtx)
951 thread_pointer_rtx = gen_rtx_REG (Pmode, 13);
952 return thread_pointer_rtx;
956 ia64_expand_tls_address (enum tls_model tls_kind, rtx op0, rtx op1,
957 rtx orig_op1, HOST_WIDE_INT addend)
959 rtx tga_op1, tga_op2, tga_ret, tga_eqv, tmp, insns;
961 HOST_WIDE_INT addend_lo, addend_hi;
965 case TLS_MODEL_GLOBAL_DYNAMIC:
968 tga_op1 = gen_reg_rtx (Pmode);
969 emit_insn (gen_load_dtpmod (tga_op1, op1));
971 tga_op2 = gen_reg_rtx (Pmode);
972 emit_insn (gen_load_dtprel (tga_op2, op1));
974 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
975 LCT_CONST, Pmode, 2, tga_op1,
976 Pmode, tga_op2, Pmode);
978 insns = get_insns ();
981 if (GET_MODE (op0) != Pmode)
983 emit_libcall_block (insns, op0, tga_ret, op1);
986 case TLS_MODEL_LOCAL_DYNAMIC:
987 /* ??? This isn't the completely proper way to do local-dynamic
988 If the call to __tls_get_addr is used only by a single symbol,
989 then we should (somehow) move the dtprel to the second arg
990 to avoid the extra add. */
993 tga_op1 = gen_reg_rtx (Pmode);
994 emit_insn (gen_load_dtpmod (tga_op1, op1));
996 tga_op2 = const0_rtx;
998 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
999 LCT_CONST, Pmode, 2, tga_op1,
1000 Pmode, tga_op2, Pmode);
1002 insns = get_insns ();
1005 tga_eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
1007 tmp = gen_reg_rtx (Pmode);
1008 emit_libcall_block (insns, tmp, tga_ret, tga_eqv);
1010 if (!register_operand (op0, Pmode))
1011 op0 = gen_reg_rtx (Pmode);
1014 emit_insn (gen_load_dtprel (op0, op1));
1015 emit_insn (gen_adddi3 (op0, tmp, op0));
1018 emit_insn (gen_add_dtprel (op0, op1, tmp));
1021 case TLS_MODEL_INITIAL_EXEC:
1022 addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000;
1023 addend_hi = addend - addend_lo;
1025 op1 = plus_constant (op1, addend_hi);
1028 tmp = gen_reg_rtx (Pmode);
1029 emit_insn (gen_load_tprel (tmp, op1));
1031 if (!register_operand (op0, Pmode))
1032 op0 = gen_reg_rtx (Pmode);
1033 emit_insn (gen_adddi3 (op0, tmp, gen_thread_pointer ()));
1036 case TLS_MODEL_LOCAL_EXEC:
1037 if (!register_operand (op0, Pmode))
1038 op0 = gen_reg_rtx (Pmode);
1044 emit_insn (gen_load_tprel (op0, op1));
1045 emit_insn (gen_adddi3 (op0, op0, gen_thread_pointer ()));
1048 emit_insn (gen_add_tprel (op0, op1, gen_thread_pointer ()));
1056 op0 = expand_simple_binop (Pmode, PLUS, op0, GEN_INT (addend),
1057 orig_op0, 1, OPTAB_DIRECT);
1058 if (orig_op0 == op0)
1060 if (GET_MODE (orig_op0) == Pmode)
1062 return gen_lowpart (GET_MODE (orig_op0), op0);
1066 ia64_expand_move (rtx op0, rtx op1)
1068 enum machine_mode mode = GET_MODE (op0);
1070 if (!reload_in_progress && !reload_completed && !ia64_move_ok (op0, op1))
1071 op1 = force_reg (mode, op1);
1073 if ((mode == Pmode || mode == ptr_mode) && symbolic_operand (op1, VOIDmode))
1075 HOST_WIDE_INT addend = 0;
1076 enum tls_model tls_kind;
1079 if (GET_CODE (op1) == CONST
1080 && GET_CODE (XEXP (op1, 0)) == PLUS
1081 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT)
1083 addend = INTVAL (XEXP (XEXP (op1, 0), 1));
1084 sym = XEXP (XEXP (op1, 0), 0);
1087 tls_kind = tls_symbolic_operand_type (sym);
1089 return ia64_expand_tls_address (tls_kind, op0, sym, op1, addend);
1091 if (any_offset_symbol_operand (sym, mode))
1093 else if (aligned_offset_symbol_operand (sym, mode))
1095 HOST_WIDE_INT addend_lo, addend_hi;
1097 addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000;
1098 addend_hi = addend - addend_lo;
1102 op1 = plus_constant (sym, addend_hi);
1111 if (reload_completed)
1113 /* We really should have taken care of this offset earlier. */
1114 gcc_assert (addend == 0);
1115 if (ia64_expand_load_address (op0, op1))
1121 rtx subtarget = no_new_pseudos ? op0 : gen_reg_rtx (mode);
1123 emit_insn (gen_rtx_SET (VOIDmode, subtarget, op1));
1125 op1 = expand_simple_binop (mode, PLUS, subtarget,
1126 GEN_INT (addend), op0, 1, OPTAB_DIRECT);
1135 /* Split a move from OP1 to OP0 conditional on COND. */
1138 ia64_emit_cond_move (rtx op0, rtx op1, rtx cond)
1140 rtx insn, first = get_last_insn ();
1142 emit_move_insn (op0, op1);
1144 for (insn = get_last_insn (); insn != first; insn = PREV_INSN (insn))
1146 PATTERN (insn) = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond),
1150 /* Split a post-reload TImode or TFmode reference into two DImode
1151 components. This is made extra difficult by the fact that we do
1152 not get any scratch registers to work with, because reload cannot
1153 be prevented from giving us a scratch that overlaps the register
1154 pair involved. So instead, when addressing memory, we tweak the
1155 pointer register up and back down with POST_INCs. Or up and not
1156 back down when we can get away with it.
1158 REVERSED is true when the loads must be done in reversed order
1159 (high word first) for correctness. DEAD is true when the pointer
1160 dies with the second insn we generate and therefore the second
1161 address must not carry a postmodify.
1163 May return an insn which is to be emitted after the moves. */
1166 ia64_split_tmode (rtx out[2], rtx in, bool reversed, bool dead)
1170 switch (GET_CODE (in))
1173 out[reversed] = gen_rtx_REG (DImode, REGNO (in));
1174 out[!reversed] = gen_rtx_REG (DImode, REGNO (in) + 1);
1179 /* Cannot occur reversed. */
1180 gcc_assert (!reversed);
1182 if (GET_MODE (in) != TFmode)
1183 split_double (in, &out[0], &out[1]);
1185 /* split_double does not understand how to split a TFmode
1186 quantity into a pair of DImode constants. */
1189 unsigned HOST_WIDE_INT p[2];
1190 long l[4]; /* TFmode is 128 bits */
1192 REAL_VALUE_FROM_CONST_DOUBLE (r, in);
1193 real_to_target (l, &r, TFmode);
1195 if (FLOAT_WORDS_BIG_ENDIAN)
1197 p[0] = (((unsigned HOST_WIDE_INT) l[0]) << 32) + l[1];
1198 p[1] = (((unsigned HOST_WIDE_INT) l[2]) << 32) + l[3];
1202 p[0] = (((unsigned HOST_WIDE_INT) l[3]) << 32) + l[2];
1203 p[1] = (((unsigned HOST_WIDE_INT) l[1]) << 32) + l[0];
1205 out[0] = GEN_INT (p[0]);
1206 out[1] = GEN_INT (p[1]);
1212 rtx base = XEXP (in, 0);
1215 switch (GET_CODE (base))
1220 out[0] = adjust_automodify_address
1221 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1222 out[1] = adjust_automodify_address
1223 (in, DImode, dead ? 0 : gen_rtx_POST_DEC (Pmode, base), 8);
1227 /* Reversal requires a pre-increment, which can only
1228 be done as a separate insn. */
1229 emit_insn (gen_adddi3 (base, base, GEN_INT (8)));
1230 out[0] = adjust_automodify_address
1231 (in, DImode, gen_rtx_POST_DEC (Pmode, base), 8);
1232 out[1] = adjust_address (in, DImode, 0);
1237 gcc_assert (!reversed && !dead);
1239 /* Just do the increment in two steps. */
1240 out[0] = adjust_automodify_address (in, DImode, 0, 0);
1241 out[1] = adjust_automodify_address (in, DImode, 0, 8);
1245 gcc_assert (!reversed && !dead);
1247 /* Add 8, subtract 24. */
1248 base = XEXP (base, 0);
1249 out[0] = adjust_automodify_address
1250 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1251 out[1] = adjust_automodify_address
1253 gen_rtx_POST_MODIFY (Pmode, base, plus_constant (base, -24)),
1258 gcc_assert (!reversed && !dead);
1260 /* Extract and adjust the modification. This case is
1261 trickier than the others, because we might have an
1262 index register, or we might have a combined offset that
1263 doesn't fit a signed 9-bit displacement field. We can
1264 assume the incoming expression is already legitimate. */
1265 offset = XEXP (base, 1);
1266 base = XEXP (base, 0);
1268 out[0] = adjust_automodify_address
1269 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1271 if (GET_CODE (XEXP (offset, 1)) == REG)
1273 /* Can't adjust the postmodify to match. Emit the
1274 original, then a separate addition insn. */
1275 out[1] = adjust_automodify_address (in, DImode, 0, 8);
1276 fixup = gen_adddi3 (base, base, GEN_INT (-8));
1280 gcc_assert (GET_CODE (XEXP (offset, 1)) == CONST_INT);
1281 if (INTVAL (XEXP (offset, 1)) < -256 + 8)
1283 /* Again the postmodify cannot be made to match,
1284 but in this case it's more efficient to get rid
1285 of the postmodify entirely and fix up with an
1287 out[1] = adjust_automodify_address (in, DImode, base, 8);
1289 (base, base, GEN_INT (INTVAL (XEXP (offset, 1)) - 8));
1293 /* Combined offset still fits in the displacement field.
1294 (We cannot overflow it at the high end.) */
1295 out[1] = adjust_automodify_address
1296 (in, DImode, gen_rtx_POST_MODIFY
1297 (Pmode, base, gen_rtx_PLUS
1299 GEN_INT (INTVAL (XEXP (offset, 1)) - 8))),
1318 /* Split a TImode or TFmode move instruction after reload.
1319 This is used by *movtf_internal and *movti_internal. */
1321 ia64_split_tmode_move (rtx operands[])
1323 rtx in[2], out[2], insn;
1326 bool reversed = false;
1328 /* It is possible for reload to decide to overwrite a pointer with
1329 the value it points to. In that case we have to do the loads in
1330 the appropriate order so that the pointer is not destroyed too
1331 early. Also we must not generate a postmodify for that second
1332 load, or rws_access_regno will die. */
1333 if (GET_CODE (operands[1]) == MEM
1334 && reg_overlap_mentioned_p (operands[0], operands[1]))
1336 rtx base = XEXP (operands[1], 0);
1337 while (GET_CODE (base) != REG)
1338 base = XEXP (base, 0);
1340 if (REGNO (base) == REGNO (operands[0]))
1344 /* Another reason to do the moves in reversed order is if the first
1345 element of the target register pair is also the second element of
1346 the source register pair. */
1347 if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
1348 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
1351 fixup[0] = ia64_split_tmode (in, operands[1], reversed, dead);
1352 fixup[1] = ia64_split_tmode (out, operands[0], reversed, dead);
1354 #define MAYBE_ADD_REG_INC_NOTE(INSN, EXP) \
1355 if (GET_CODE (EXP) == MEM \
1356 && (GET_CODE (XEXP (EXP, 0)) == POST_MODIFY \
1357 || GET_CODE (XEXP (EXP, 0)) == POST_INC \
1358 || GET_CODE (XEXP (EXP, 0)) == POST_DEC)) \
1359 REG_NOTES (INSN) = gen_rtx_EXPR_LIST (REG_INC, \
1360 XEXP (XEXP (EXP, 0), 0), \
1363 insn = emit_insn (gen_rtx_SET (VOIDmode, out[0], in[0]));
1364 MAYBE_ADD_REG_INC_NOTE (insn, in[0]);
1365 MAYBE_ADD_REG_INC_NOTE (insn, out[0]);
1367 insn = emit_insn (gen_rtx_SET (VOIDmode, out[1], in[1]));
1368 MAYBE_ADD_REG_INC_NOTE (insn, in[1]);
1369 MAYBE_ADD_REG_INC_NOTE (insn, out[1]);
1372 emit_insn (fixup[0]);
1374 emit_insn (fixup[1]);
1376 #undef MAYBE_ADD_REG_INC_NOTE
1379 /* ??? Fixing GR->FR XFmode moves during reload is hard. You need to go
1380 through memory plus an extra GR scratch register. Except that you can
1381 either get the first from SECONDARY_MEMORY_NEEDED or the second from
1382 SECONDARY_RELOAD_CLASS, but not both.
1384 We got into problems in the first place by allowing a construct like
1385 (subreg:XF (reg:TI)), which we got from a union containing a long double.
1386 This solution attempts to prevent this situation from occurring. When
1387 we see something like the above, we spill the inner register to memory. */
1390 spill_xfmode_rfmode_operand (rtx in, int force, enum machine_mode mode)
1392 if (GET_CODE (in) == SUBREG
1393 && GET_MODE (SUBREG_REG (in)) == TImode
1394 && GET_CODE (SUBREG_REG (in)) == REG)
1396 rtx memt = assign_stack_temp (TImode, 16, 0);
1397 emit_move_insn (memt, SUBREG_REG (in));
1398 return adjust_address (memt, mode, 0);
1400 else if (force && GET_CODE (in) == REG)
1402 rtx memx = assign_stack_temp (mode, 16, 0);
1403 emit_move_insn (memx, in);
1410 /* Expand the movxf or movrf pattern (MODE says which) with the given
1411 OPERANDS, returning true if the pattern should then invoke
1415 ia64_expand_movxf_movrf (enum machine_mode mode, rtx operands[])
1417 rtx op0 = operands[0];
1419 if (GET_CODE (op0) == SUBREG)
1420 op0 = SUBREG_REG (op0);
1422 /* We must support XFmode loads into general registers for stdarg/vararg,
1423 unprototyped calls, and a rare case where a long double is passed as
1424 an argument after a float HFA fills the FP registers. We split them into
1425 DImode loads for convenience. We also need to support XFmode stores
1426 for the last case. This case does not happen for stdarg/vararg routines,
1427 because we do a block store to memory of unnamed arguments. */
1429 if (GET_CODE (op0) == REG && GR_REGNO_P (REGNO (op0)))
1433 /* We're hoping to transform everything that deals with XFmode
1434 quantities and GR registers early in the compiler. */
1435 gcc_assert (!no_new_pseudos);
1437 /* Struct to register can just use TImode instead. */
1438 if ((GET_CODE (operands[1]) == SUBREG
1439 && GET_MODE (SUBREG_REG (operands[1])) == TImode)
1440 || (GET_CODE (operands[1]) == REG
1441 && GR_REGNO_P (REGNO (operands[1]))))
1443 rtx op1 = operands[1];
1445 if (GET_CODE (op1) == SUBREG)
1446 op1 = SUBREG_REG (op1);
1448 op1 = gen_rtx_REG (TImode, REGNO (op1));
1450 emit_move_insn (gen_rtx_REG (TImode, REGNO (op0)), op1);
1454 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1456 /* Don't word-swap when reading in the constant. */
1457 emit_move_insn (gen_rtx_REG (DImode, REGNO (op0)),
1458 operand_subword (operands[1], WORDS_BIG_ENDIAN,
1460 emit_move_insn (gen_rtx_REG (DImode, REGNO (op0) + 1),
1461 operand_subword (operands[1], !WORDS_BIG_ENDIAN,
1466 /* If the quantity is in a register not known to be GR, spill it. */
1467 if (register_operand (operands[1], mode))
1468 operands[1] = spill_xfmode_rfmode_operand (operands[1], 1, mode);
1470 gcc_assert (GET_CODE (operands[1]) == MEM);
1472 /* Don't word-swap when reading in the value. */
1473 out[0] = gen_rtx_REG (DImode, REGNO (op0));
1474 out[1] = gen_rtx_REG (DImode, REGNO (op0) + 1);
1476 emit_move_insn (out[0], adjust_address (operands[1], DImode, 0));
1477 emit_move_insn (out[1], adjust_address (operands[1], DImode, 8));
1481 if (GET_CODE (operands[1]) == REG && GR_REGNO_P (REGNO (operands[1])))
1483 /* We're hoping to transform everything that deals with XFmode
1484 quantities and GR registers early in the compiler. */
1485 gcc_assert (!no_new_pseudos);
1487 /* Op0 can't be a GR_REG here, as that case is handled above.
1488 If op0 is a register, then we spill op1, so that we now have a
1489 MEM operand. This requires creating an XFmode subreg of a TImode reg
1490 to force the spill. */
1491 if (register_operand (operands[0], mode))
1493 rtx op1 = gen_rtx_REG (TImode, REGNO (operands[1]));
1494 op1 = gen_rtx_SUBREG (mode, op1, 0);
1495 operands[1] = spill_xfmode_rfmode_operand (op1, 0, mode);
1502 gcc_assert (GET_CODE (operands[0]) == MEM);
1504 /* Don't word-swap when writing out the value. */
1505 in[0] = gen_rtx_REG (DImode, REGNO (operands[1]));
1506 in[1] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1);
1508 emit_move_insn (adjust_address (operands[0], DImode, 0), in[0]);
1509 emit_move_insn (adjust_address (operands[0], DImode, 8), in[1]);
1514 if (!reload_in_progress && !reload_completed)
1516 operands[1] = spill_xfmode_rfmode_operand (operands[1], 0, mode);
1518 if (GET_MODE (op0) == TImode && GET_CODE (op0) == REG)
1520 rtx memt, memx, in = operands[1];
1521 if (CONSTANT_P (in))
1522 in = validize_mem (force_const_mem (mode, in));
1523 if (GET_CODE (in) == MEM)
1524 memt = adjust_address (in, TImode, 0);
1527 memt = assign_stack_temp (TImode, 16, 0);
1528 memx = adjust_address (memt, mode, 0);
1529 emit_move_insn (memx, in);
1531 emit_move_insn (op0, memt);
1535 if (!ia64_move_ok (operands[0], operands[1]))
1536 operands[1] = force_reg (mode, operands[1]);
1542 /* Emit comparison instruction if necessary, returning the expression
1543 that holds the compare result in the proper mode. */
1545 static GTY(()) rtx cmptf_libfunc;
1548 ia64_expand_compare (enum rtx_code code, enum machine_mode mode)
1550 rtx op0 = ia64_compare_op0, op1 = ia64_compare_op1;
1553 /* If we have a BImode input, then we already have a compare result, and
1554 do not need to emit another comparison. */
1555 if (GET_MODE (op0) == BImode)
1557 gcc_assert ((code == NE || code == EQ) && op1 == const0_rtx);
1560 /* HPUX TFmode compare requires a library call to _U_Qfcmp, which takes a
1561 magic number as its third argument, that indicates what to do.
1562 The return value is an integer to be compared against zero. */
1563 else if (GET_MODE (op0) == TFmode)
1566 QCMP_INV = 1, /* Raise FP_INVALID on SNaN as a side effect. */
1572 enum rtx_code ncode;
1575 gcc_assert (cmptf_libfunc && GET_MODE (op1) == TFmode);
1578 /* 1 = equal, 0 = not equal. Equality operators do
1579 not raise FP_INVALID when given an SNaN operand. */
1580 case EQ: magic = QCMP_EQ; ncode = NE; break;
1581 case NE: magic = QCMP_EQ; ncode = EQ; break;
1582 /* isunordered() from C99. */
1583 case UNORDERED: magic = QCMP_UNORD; ncode = NE; break;
1584 case ORDERED: magic = QCMP_UNORD; ncode = EQ; break;
1585 /* Relational operators raise FP_INVALID when given
1587 case LT: magic = QCMP_LT |QCMP_INV; ncode = NE; break;
1588 case LE: magic = QCMP_LT|QCMP_EQ|QCMP_INV; ncode = NE; break;
1589 case GT: magic = QCMP_GT |QCMP_INV; ncode = NE; break;
1590 case GE: magic = QCMP_GT|QCMP_EQ|QCMP_INV; ncode = NE; break;
1591 /* FUTURE: Implement UNEQ, UNLT, UNLE, UNGT, UNGE, LTGT.
1592 Expanders for buneq etc. weuld have to be added to ia64.md
1593 for this to be useful. */
1594 default: gcc_unreachable ();
1599 ret = emit_library_call_value (cmptf_libfunc, 0, LCT_CONST, DImode, 3,
1600 op0, TFmode, op1, TFmode,
1601 GEN_INT (magic), DImode);
1602 cmp = gen_reg_rtx (BImode);
1603 emit_insn (gen_rtx_SET (VOIDmode, cmp,
1604 gen_rtx_fmt_ee (ncode, BImode,
1607 insns = get_insns ();
1610 emit_libcall_block (insns, cmp, cmp,
1611 gen_rtx_fmt_ee (code, BImode, op0, op1));
1616 cmp = gen_reg_rtx (BImode);
1617 emit_insn (gen_rtx_SET (VOIDmode, cmp,
1618 gen_rtx_fmt_ee (code, BImode, op0, op1)));
1622 return gen_rtx_fmt_ee (code, mode, cmp, const0_rtx);
1625 /* Generate an integral vector comparison. Return true if the condition has
1626 been reversed, and so the sense of the comparison should be inverted. */
1629 ia64_expand_vecint_compare (enum rtx_code code, enum machine_mode mode,
1630 rtx dest, rtx op0, rtx op1)
1632 bool negate = false;
1635 /* Canonicalize the comparison to EQ, GT, GTU. */
1646 code = reverse_condition (code);
1652 code = reverse_condition (code);
1658 code = swap_condition (code);
1659 x = op0, op0 = op1, op1 = x;
1666 /* Unsigned parallel compare is not supported by the hardware. Play some
1667 tricks to turn this into a signed comparison against 0. */
1676 /* Perform a parallel modulo subtraction. */
1677 t1 = gen_reg_rtx (V2SImode);
1678 emit_insn (gen_subv2si3 (t1, op0, op1));
1680 /* Extract the original sign bit of op0. */
1681 mask = GEN_INT (-0x80000000);
1682 mask = gen_rtx_CONST_VECTOR (V2SImode, gen_rtvec (2, mask, mask));
1683 mask = force_reg (V2SImode, mask);
1684 t2 = gen_reg_rtx (V2SImode);
1685 emit_insn (gen_andv2si3 (t2, op0, mask));
1687 /* XOR it back into the result of the subtraction. This results
1688 in the sign bit set iff we saw unsigned underflow. */
1689 x = gen_reg_rtx (V2SImode);
1690 emit_insn (gen_xorv2si3 (x, t1, t2));
1694 op1 = CONST0_RTX (mode);
1700 /* Perform a parallel unsigned saturating subtraction. */
1701 x = gen_reg_rtx (mode);
1702 emit_insn (gen_rtx_SET (VOIDmode, x,
1703 gen_rtx_US_MINUS (mode, op0, op1)));
1707 op1 = CONST0_RTX (mode);
1716 x = gen_rtx_fmt_ee (code, mode, op0, op1);
1717 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
1722 /* Emit an integral vector conditional move. */
1725 ia64_expand_vecint_cmov (rtx operands[])
1727 enum machine_mode mode = GET_MODE (operands[0]);
1728 enum rtx_code code = GET_CODE (operands[3]);
1732 cmp = gen_reg_rtx (mode);
1733 negate = ia64_expand_vecint_compare (code, mode, cmp,
1734 operands[4], operands[5]);
1736 ot = operands[1+negate];
1737 of = operands[2-negate];
1739 if (ot == CONST0_RTX (mode))
1741 if (of == CONST0_RTX (mode))
1743 emit_move_insn (operands[0], ot);
1747 x = gen_rtx_NOT (mode, cmp);
1748 x = gen_rtx_AND (mode, x, of);
1749 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1751 else if (of == CONST0_RTX (mode))
1753 x = gen_rtx_AND (mode, cmp, ot);
1754 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1760 t = gen_reg_rtx (mode);
1761 x = gen_rtx_AND (mode, cmp, operands[1+negate]);
1762 emit_insn (gen_rtx_SET (VOIDmode, t, x));
1764 f = gen_reg_rtx (mode);
1765 x = gen_rtx_NOT (mode, cmp);
1766 x = gen_rtx_AND (mode, x, operands[2-negate]);
1767 emit_insn (gen_rtx_SET (VOIDmode, f, x));
1769 x = gen_rtx_IOR (mode, t, f);
1770 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1774 /* Emit an integral vector min or max operation. Return true if all done. */
1777 ia64_expand_vecint_minmax (enum rtx_code code, enum machine_mode mode,
1782 /* These four combinations are supported directly. */
1783 if (mode == V8QImode && (code == UMIN || code == UMAX))
1785 if (mode == V4HImode && (code == SMIN || code == SMAX))
1788 /* This combination can be implemented with only saturating subtraction. */
1789 if (mode == V4HImode && code == UMAX)
1791 rtx x, tmp = gen_reg_rtx (mode);
1793 x = gen_rtx_US_MINUS (mode, operands[1], operands[2]);
1794 emit_insn (gen_rtx_SET (VOIDmode, tmp, x));
1796 emit_insn (gen_addv4hi3 (operands[0], tmp, operands[2]));
1800 /* Everything else implemented via vector comparisons. */
1801 xops[0] = operands[0];
1802 xops[4] = xops[1] = operands[1];
1803 xops[5] = xops[2] = operands[2];
1822 xops[3] = gen_rtx_fmt_ee (code, VOIDmode, operands[1], operands[2]);
1824 ia64_expand_vecint_cmov (xops);
1828 /* Emit an integral vector widening sum operations. */
1831 ia64_expand_widen_sum (rtx operands[3], bool unsignedp)
1834 enum machine_mode wmode, mode;
1835 rtx (*unpack_l) (rtx, rtx, rtx);
1836 rtx (*unpack_h) (rtx, rtx, rtx);
1837 rtx (*plus) (rtx, rtx, rtx);
1839 wmode = GET_MODE (operands[0]);
1840 mode = GET_MODE (operands[1]);
1845 unpack_l = gen_unpack1_l;
1846 unpack_h = gen_unpack1_h;
1847 plus = gen_addv4hi3;
1850 unpack_l = gen_unpack2_l;
1851 unpack_h = gen_unpack2_h;
1852 plus = gen_addv2si3;
1858 /* Fill in x with the sign extension of each element in op1. */
1860 x = CONST0_RTX (mode);
1865 x = gen_reg_rtx (mode);
1867 neg = ia64_expand_vecint_compare (LT, mode, x, operands[1],
1872 l = gen_reg_rtx (wmode);
1873 h = gen_reg_rtx (wmode);
1874 s = gen_reg_rtx (wmode);
1876 emit_insn (unpack_l (gen_lowpart (mode, l), operands[1], x));
1877 emit_insn (unpack_h (gen_lowpart (mode, h), operands[1], x));
1878 emit_insn (plus (s, l, operands[2]));
1879 emit_insn (plus (operands[0], h, s));
1882 /* Emit a signed or unsigned V8QI dot product operation. */
1885 ia64_expand_dot_prod_v8qi (rtx operands[4], bool unsignedp)
1887 rtx l1, l2, h1, h2, x1, x2, p1, p2, p3, p4, s1, s2, s3;
1889 /* Fill in x1 and x2 with the sign extension of each element. */
1891 x1 = x2 = CONST0_RTX (V8QImode);
1896 x1 = gen_reg_rtx (V8QImode);
1897 x2 = gen_reg_rtx (V8QImode);
1899 neg = ia64_expand_vecint_compare (LT, V8QImode, x1, operands[1],
1900 CONST0_RTX (V8QImode));
1902 neg = ia64_expand_vecint_compare (LT, V8QImode, x2, operands[2],
1903 CONST0_RTX (V8QImode));
1907 l1 = gen_reg_rtx (V4HImode);
1908 l2 = gen_reg_rtx (V4HImode);
1909 h1 = gen_reg_rtx (V4HImode);
1910 h2 = gen_reg_rtx (V4HImode);
1912 emit_insn (gen_unpack1_l (gen_lowpart (V8QImode, l1), operands[1], x1));
1913 emit_insn (gen_unpack1_l (gen_lowpart (V8QImode, l2), operands[2], x2));
1914 emit_insn (gen_unpack1_h (gen_lowpart (V8QImode, h1), operands[1], x1));
1915 emit_insn (gen_unpack1_h (gen_lowpart (V8QImode, h2), operands[2], x2));
1917 p1 = gen_reg_rtx (V2SImode);
1918 p2 = gen_reg_rtx (V2SImode);
1919 p3 = gen_reg_rtx (V2SImode);
1920 p4 = gen_reg_rtx (V2SImode);
1921 emit_insn (gen_pmpy2_r (p1, l1, l2));
1922 emit_insn (gen_pmpy2_l (p2, l1, l2));
1923 emit_insn (gen_pmpy2_r (p3, h1, h2));
1924 emit_insn (gen_pmpy2_l (p4, h1, h2));
1926 s1 = gen_reg_rtx (V2SImode);
1927 s2 = gen_reg_rtx (V2SImode);
1928 s3 = gen_reg_rtx (V2SImode);
1929 emit_insn (gen_addv2si3 (s1, p1, p2));
1930 emit_insn (gen_addv2si3 (s2, p3, p4));
1931 emit_insn (gen_addv2si3 (s3, s1, operands[3]));
1932 emit_insn (gen_addv2si3 (operands[0], s2, s3));
1935 /* Emit the appropriate sequence for a call. */
1938 ia64_expand_call (rtx retval, rtx addr, rtx nextarg ATTRIBUTE_UNUSED,
1943 addr = XEXP (addr, 0);
1944 addr = convert_memory_address (DImode, addr);
1945 b0 = gen_rtx_REG (DImode, R_BR (0));
1947 /* ??? Should do this for functions known to bind local too. */
1948 if (TARGET_NO_PIC || TARGET_AUTO_PIC)
1951 insn = gen_sibcall_nogp (addr);
1953 insn = gen_call_nogp (addr, b0);
1955 insn = gen_call_value_nogp (retval, addr, b0);
1956 insn = emit_call_insn (insn);
1961 insn = gen_sibcall_gp (addr);
1963 insn = gen_call_gp (addr, b0);
1965 insn = gen_call_value_gp (retval, addr, b0);
1966 insn = emit_call_insn (insn);
1968 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
1972 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), b0);
1976 ia64_reload_gp (void)
1980 if (current_frame_info.reg_save_gp)
1981 tmp = gen_rtx_REG (DImode, current_frame_info.reg_save_gp);
1984 HOST_WIDE_INT offset;
1986 offset = (current_frame_info.spill_cfa_off
1987 + current_frame_info.spill_size);
1988 if (frame_pointer_needed)
1990 tmp = hard_frame_pointer_rtx;
1995 tmp = stack_pointer_rtx;
1996 offset = current_frame_info.total_size - offset;
1999 if (CONST_OK_FOR_I (offset))
2000 emit_insn (gen_adddi3 (pic_offset_table_rtx,
2001 tmp, GEN_INT (offset)));
2004 emit_move_insn (pic_offset_table_rtx, GEN_INT (offset));
2005 emit_insn (gen_adddi3 (pic_offset_table_rtx,
2006 pic_offset_table_rtx, tmp));
2009 tmp = gen_rtx_MEM (DImode, pic_offset_table_rtx);
2012 emit_move_insn (pic_offset_table_rtx, tmp);
2016 ia64_split_call (rtx retval, rtx addr, rtx retaddr, rtx scratch_r,
2017 rtx scratch_b, int noreturn_p, int sibcall_p)
2020 bool is_desc = false;
2022 /* If we find we're calling through a register, then we're actually
2023 calling through a descriptor, so load up the values. */
2024 if (REG_P (addr) && GR_REGNO_P (REGNO (addr)))
2029 /* ??? We are currently constrained to *not* use peep2, because
2030 we can legitimately change the global lifetime of the GP
2031 (in the form of killing where previously live). This is
2032 because a call through a descriptor doesn't use the previous
2033 value of the GP, while a direct call does, and we do not
2034 commit to either form until the split here.
2036 That said, this means that we lack precise life info for
2037 whether ADDR is dead after this call. This is not terribly
2038 important, since we can fix things up essentially for free
2039 with the POST_DEC below, but it's nice to not use it when we
2040 can immediately tell it's not necessary. */
2041 addr_dead_p = ((noreturn_p || sibcall_p
2042 || TEST_HARD_REG_BIT (regs_invalidated_by_call,
2044 && !FUNCTION_ARG_REGNO_P (REGNO (addr)));
2046 /* Load the code address into scratch_b. */
2047 tmp = gen_rtx_POST_INC (Pmode, addr);
2048 tmp = gen_rtx_MEM (Pmode, tmp);
2049 emit_move_insn (scratch_r, tmp);
2050 emit_move_insn (scratch_b, scratch_r);
2052 /* Load the GP address. If ADDR is not dead here, then we must
2053 revert the change made above via the POST_INCREMENT. */
2055 tmp = gen_rtx_POST_DEC (Pmode, addr);
2058 tmp = gen_rtx_MEM (Pmode, tmp);
2059 emit_move_insn (pic_offset_table_rtx, tmp);
2066 insn = gen_sibcall_nogp (addr);
2068 insn = gen_call_value_nogp (retval, addr, retaddr);
2070 insn = gen_call_nogp (addr, retaddr);
2071 emit_call_insn (insn);
2073 if ((!TARGET_CONST_GP || is_desc) && !noreturn_p && !sibcall_p)
2077 /* Expand an atomic operation. We want to perform MEM <CODE>= VAL atomically.
2079 This differs from the generic code in that we know about the zero-extending
2080 properties of cmpxchg, and the zero-extending requirements of ar.ccv. We
2081 also know that ld.acq+cmpxchg.rel equals a full barrier.
2083 The loop we want to generate looks like
2088 new_reg = cmp_reg op val;
2089 cmp_reg = compare-and-swap(mem, old_reg, new_reg)
2090 if (cmp_reg != old_reg)
2093 Note that we only do the plain load from memory once. Subsequent
2094 iterations use the value loaded by the compare-and-swap pattern. */
2097 ia64_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
2098 rtx old_dst, rtx new_dst)
2100 enum machine_mode mode = GET_MODE (mem);
2101 rtx old_reg, new_reg, cmp_reg, ar_ccv, label;
2102 enum insn_code icode;
2104 /* Special case for using fetchadd. */
2105 if ((mode == SImode || mode == DImode)
2106 && (code == PLUS || code == MINUS)
2107 && fetchadd_operand (val, mode))
2110 val = GEN_INT (-INTVAL (val));
2113 old_dst = gen_reg_rtx (mode);
2115 emit_insn (gen_memory_barrier ());
2118 icode = CODE_FOR_fetchadd_acq_si;
2120 icode = CODE_FOR_fetchadd_acq_di;
2121 emit_insn (GEN_FCN (icode) (old_dst, mem, val));
2125 new_reg = expand_simple_binop (mode, PLUS, old_dst, val, new_dst,
2127 if (new_reg != new_dst)
2128 emit_move_insn (new_dst, new_reg);
2133 /* Because of the volatile mem read, we get an ld.acq, which is the
2134 front half of the full barrier. The end half is the cmpxchg.rel. */
2135 gcc_assert (MEM_VOLATILE_P (mem));
2137 old_reg = gen_reg_rtx (DImode);
2138 cmp_reg = gen_reg_rtx (DImode);
2139 label = gen_label_rtx ();
2143 val = simplify_gen_subreg (DImode, val, mode, 0);
2144 emit_insn (gen_extend_insn (cmp_reg, mem, DImode, mode, 1));
2147 emit_move_insn (cmp_reg, mem);
2151 ar_ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
2152 emit_move_insn (old_reg, cmp_reg);
2153 emit_move_insn (ar_ccv, cmp_reg);
2156 emit_move_insn (old_dst, gen_lowpart (mode, cmp_reg));
2161 new_reg = expand_simple_unop (DImode, NOT, new_reg, NULL_RTX, true);
2164 new_reg = expand_simple_binop (DImode, code, new_reg, val, NULL_RTX,
2165 true, OPTAB_DIRECT);
2168 new_reg = gen_lowpart (mode, new_reg);
2170 emit_move_insn (new_dst, new_reg);
2174 case QImode: icode = CODE_FOR_cmpxchg_rel_qi; break;
2175 case HImode: icode = CODE_FOR_cmpxchg_rel_hi; break;
2176 case SImode: icode = CODE_FOR_cmpxchg_rel_si; break;
2177 case DImode: icode = CODE_FOR_cmpxchg_rel_di; break;
2182 emit_insn (GEN_FCN (icode) (cmp_reg, mem, ar_ccv, new_reg));
2184 emit_cmp_and_jump_insns (cmp_reg, old_reg, NE, NULL, DImode, true, label);
2187 /* Begin the assembly file. */
2190 ia64_file_start (void)
2192 /* Variable tracking should be run after all optimizations which change order
2193 of insns. It also needs a valid CFG. This can't be done in
2194 ia64_override_options, because flag_var_tracking is finalized after
2196 ia64_flag_var_tracking = flag_var_tracking;
2197 flag_var_tracking = 0;
2199 default_file_start ();
2200 emit_safe_across_calls ();
2204 emit_safe_across_calls (void)
2206 unsigned int rs, re;
2213 while (rs < 64 && call_used_regs[PR_REG (rs)])
2217 for (re = rs + 1; re < 64 && ! call_used_regs[PR_REG (re)]; re++)
2221 fputs ("\t.pred.safe_across_calls ", asm_out_file);
2225 fputc (',', asm_out_file);
2227 fprintf (asm_out_file, "p%u", rs);
2229 fprintf (asm_out_file, "p%u-p%u", rs, re - 1);
2233 fputc ('\n', asm_out_file);
2236 /* Globalize a declaration. */
2239 ia64_globalize_decl_name (FILE * stream, tree decl)
2241 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2242 tree version_attr = lookup_attribute ("version_id", DECL_ATTRIBUTES (decl));
2245 tree v = TREE_VALUE (TREE_VALUE (version_attr));
2246 const char *p = TREE_STRING_POINTER (v);
2247 fprintf (stream, "\t.alias %s#, \"%s{%s}\"\n", name, name, p);
2249 targetm.asm_out.globalize_label (stream, name);
2250 if (TREE_CODE (decl) == FUNCTION_DECL)
2251 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "function");
2254 /* Helper function for ia64_compute_frame_size: find an appropriate general
2255 register to spill some special register to. SPECIAL_SPILL_MASK contains
2256 bits in GR0 to GR31 that have already been allocated by this routine.
2257 TRY_LOCALS is true if we should attempt to locate a local regnum. */
2260 find_gr_spill (int try_locals)
2264 /* If this is a leaf function, first try an otherwise unused
2265 call-clobbered register. */
2266 if (current_function_is_leaf)
2268 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
2269 if (! regs_ever_live[regno]
2270 && call_used_regs[regno]
2271 && ! fixed_regs[regno]
2272 && ! global_regs[regno]
2273 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0)
2275 current_frame_info.gr_used_mask |= 1 << regno;
2282 regno = current_frame_info.n_local_regs;
2283 /* If there is a frame pointer, then we can't use loc79, because
2284 that is HARD_FRAME_POINTER_REGNUM. In particular, see the
2285 reg_name switching code in ia64_expand_prologue. */
2286 if (regno < (80 - frame_pointer_needed))
2288 current_frame_info.n_local_regs = regno + 1;
2289 return LOC_REG (0) + regno;
2293 /* Failed to find a general register to spill to. Must use stack. */
2297 /* In order to make for nice schedules, we try to allocate every temporary
2298 to a different register. We must of course stay away from call-saved,
2299 fixed, and global registers. We must also stay away from registers
2300 allocated in current_frame_info.gr_used_mask, since those include regs
2301 used all through the prologue.
2303 Any register allocated here must be used immediately. The idea is to
2304 aid scheduling, not to solve data flow problems. */
2306 static int last_scratch_gr_reg;
2309 next_scratch_gr_reg (void)
2313 for (i = 0; i < 32; ++i)
2315 regno = (last_scratch_gr_reg + i + 1) & 31;
2316 if (call_used_regs[regno]
2317 && ! fixed_regs[regno]
2318 && ! global_regs[regno]
2319 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0)
2321 last_scratch_gr_reg = regno;
2326 /* There must be _something_ available. */
2330 /* Helper function for ia64_compute_frame_size, called through
2331 diddle_return_value. Mark REG in current_frame_info.gr_used_mask. */
2334 mark_reg_gr_used_mask (rtx reg, void *data ATTRIBUTE_UNUSED)
2336 unsigned int regno = REGNO (reg);
2339 unsigned int i, n = hard_regno_nregs[regno][GET_MODE (reg)];
2340 for (i = 0; i < n; ++i)
2341 current_frame_info.gr_used_mask |= 1 << (regno + i);
2345 /* Returns the number of bytes offset between the frame pointer and the stack
2346 pointer for the current function. SIZE is the number of bytes of space
2347 needed for local variables. */
2350 ia64_compute_frame_size (HOST_WIDE_INT size)
2352 HOST_WIDE_INT total_size;
2353 HOST_WIDE_INT spill_size = 0;
2354 HOST_WIDE_INT extra_spill_size = 0;
2355 HOST_WIDE_INT pretend_args_size;
2358 int spilled_gr_p = 0;
2359 int spilled_fr_p = 0;
2363 if (current_frame_info.initialized)
2366 memset (¤t_frame_info, 0, sizeof current_frame_info);
2367 CLEAR_HARD_REG_SET (mask);
2369 /* Don't allocate scratches to the return register. */
2370 diddle_return_value (mark_reg_gr_used_mask, NULL);
2372 /* Don't allocate scratches to the EH scratch registers. */
2373 if (cfun->machine->ia64_eh_epilogue_sp)
2374 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_sp, NULL);
2375 if (cfun->machine->ia64_eh_epilogue_bsp)
2376 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_bsp, NULL);
2378 /* Find the size of the register stack frame. We have only 80 local
2379 registers, because we reserve 8 for the inputs and 8 for the
2382 /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed,
2383 since we'll be adjusting that down later. */
2384 regno = LOC_REG (78) + ! frame_pointer_needed;
2385 for (; regno >= LOC_REG (0); regno--)
2386 if (regs_ever_live[regno])
2388 current_frame_info.n_local_regs = regno - LOC_REG (0) + 1;
2390 /* For functions marked with the syscall_linkage attribute, we must mark
2391 all eight input registers as in use, so that locals aren't visible to
2394 if (cfun->machine->n_varargs > 0
2395 || lookup_attribute ("syscall_linkage",
2396 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
2397 current_frame_info.n_input_regs = 8;
2400 for (regno = IN_REG (7); regno >= IN_REG (0); regno--)
2401 if (regs_ever_live[regno])
2403 current_frame_info.n_input_regs = regno - IN_REG (0) + 1;
2406 for (regno = OUT_REG (7); regno >= OUT_REG (0); regno--)
2407 if (regs_ever_live[regno])
2409 i = regno - OUT_REG (0) + 1;
2411 #ifndef PROFILE_HOOK
2412 /* When -p profiling, we need one output register for the mcount argument.
2413 Likewise for -a profiling for the bb_init_func argument. For -ax
2414 profiling, we need two output registers for the two bb_init_trace_func
2416 if (current_function_profile)
2419 current_frame_info.n_output_regs = i;
2421 /* ??? No rotating register support yet. */
2422 current_frame_info.n_rotate_regs = 0;
2424 /* Discover which registers need spilling, and how much room that
2425 will take. Begin with floating point and general registers,
2426 which will always wind up on the stack. */
2428 for (regno = FR_REG (2); regno <= FR_REG (127); regno++)
2429 if (regs_ever_live[regno] && ! call_used_regs[regno])
2431 SET_HARD_REG_BIT (mask, regno);
2437 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
2438 if (regs_ever_live[regno] && ! call_used_regs[regno])
2440 SET_HARD_REG_BIT (mask, regno);
2446 for (regno = BR_REG (1); regno <= BR_REG (7); regno++)
2447 if (regs_ever_live[regno] && ! call_used_regs[regno])
2449 SET_HARD_REG_BIT (mask, regno);
2454 /* Now come all special registers that might get saved in other
2455 general registers. */
2457 if (frame_pointer_needed)
2459 current_frame_info.reg_fp = find_gr_spill (1);
2460 /* If we did not get a register, then we take LOC79. This is guaranteed
2461 to be free, even if regs_ever_live is already set, because this is
2462 HARD_FRAME_POINTER_REGNUM. This requires incrementing n_local_regs,
2463 as we don't count loc79 above. */
2464 if (current_frame_info.reg_fp == 0)
2466 current_frame_info.reg_fp = LOC_REG (79);
2467 current_frame_info.n_local_regs++;
2471 if (! current_function_is_leaf)
2473 /* Emit a save of BR0 if we call other functions. Do this even
2474 if this function doesn't return, as EH depends on this to be
2475 able to unwind the stack. */
2476 SET_HARD_REG_BIT (mask, BR_REG (0));
2478 current_frame_info.reg_save_b0 = find_gr_spill (1);
2479 if (current_frame_info.reg_save_b0 == 0)
2481 extra_spill_size += 8;
2485 /* Similarly for ar.pfs. */
2486 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
2487 current_frame_info.reg_save_ar_pfs = find_gr_spill (1);
2488 if (current_frame_info.reg_save_ar_pfs == 0)
2490 extra_spill_size += 8;
2494 /* Similarly for gp. Note that if we're calling setjmp, the stacked
2495 registers are clobbered, so we fall back to the stack. */
2496 current_frame_info.reg_save_gp
2497 = (current_function_calls_setjmp ? 0 : find_gr_spill (1));
2498 if (current_frame_info.reg_save_gp == 0)
2500 SET_HARD_REG_BIT (mask, GR_REG (1));
2507 if (regs_ever_live[BR_REG (0)] && ! call_used_regs[BR_REG (0)])
2509 SET_HARD_REG_BIT (mask, BR_REG (0));
2510 extra_spill_size += 8;
2514 if (regs_ever_live[AR_PFS_REGNUM])
2516 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
2517 current_frame_info.reg_save_ar_pfs = find_gr_spill (1);
2518 if (current_frame_info.reg_save_ar_pfs == 0)
2520 extra_spill_size += 8;
2526 /* Unwind descriptor hackery: things are most efficient if we allocate
2527 consecutive GR save registers for RP, PFS, FP in that order. However,
2528 it is absolutely critical that FP get the only hard register that's
2529 guaranteed to be free, so we allocated it first. If all three did
2530 happen to be allocated hard regs, and are consecutive, rearrange them
2531 into the preferred order now. */
2532 if (current_frame_info.reg_fp != 0
2533 && current_frame_info.reg_save_b0 == current_frame_info.reg_fp + 1
2534 && current_frame_info.reg_save_ar_pfs == current_frame_info.reg_fp + 2)
2536 current_frame_info.reg_save_b0 = current_frame_info.reg_fp;
2537 current_frame_info.reg_save_ar_pfs = current_frame_info.reg_fp + 1;
2538 current_frame_info.reg_fp = current_frame_info.reg_fp + 2;
2541 /* See if we need to store the predicate register block. */
2542 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
2543 if (regs_ever_live[regno] && ! call_used_regs[regno])
2545 if (regno <= PR_REG (63))
2547 SET_HARD_REG_BIT (mask, PR_REG (0));
2548 current_frame_info.reg_save_pr = find_gr_spill (1);
2549 if (current_frame_info.reg_save_pr == 0)
2551 extra_spill_size += 8;
2555 /* ??? Mark them all as used so that register renaming and such
2556 are free to use them. */
2557 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
2558 regs_ever_live[regno] = 1;
2561 /* If we're forced to use st8.spill, we're forced to save and restore
2562 ar.unat as well. The check for existing liveness allows inline asm
2563 to touch ar.unat. */
2564 if (spilled_gr_p || cfun->machine->n_varargs
2565 || regs_ever_live[AR_UNAT_REGNUM])
2567 regs_ever_live[AR_UNAT_REGNUM] = 1;
2568 SET_HARD_REG_BIT (mask, AR_UNAT_REGNUM);
2569 current_frame_info.reg_save_ar_unat = find_gr_spill (spill_size == 0);
2570 if (current_frame_info.reg_save_ar_unat == 0)
2572 extra_spill_size += 8;
2577 if (regs_ever_live[AR_LC_REGNUM])
2579 SET_HARD_REG_BIT (mask, AR_LC_REGNUM);
2580 current_frame_info.reg_save_ar_lc = find_gr_spill (spill_size == 0);
2581 if (current_frame_info.reg_save_ar_lc == 0)
2583 extra_spill_size += 8;
2588 /* If we have an odd number of words of pretend arguments written to
2589 the stack, then the FR save area will be unaligned. We round the
2590 size of this area up to keep things 16 byte aligned. */
2592 pretend_args_size = IA64_STACK_ALIGN (current_function_pretend_args_size);
2594 pretend_args_size = current_function_pretend_args_size;
2596 total_size = (spill_size + extra_spill_size + size + pretend_args_size
2597 + current_function_outgoing_args_size);
2598 total_size = IA64_STACK_ALIGN (total_size);
2600 /* We always use the 16-byte scratch area provided by the caller, but
2601 if we are a leaf function, there's no one to which we need to provide
2603 if (current_function_is_leaf)
2604 total_size = MAX (0, total_size - 16);
2606 current_frame_info.total_size = total_size;
2607 current_frame_info.spill_cfa_off = pretend_args_size - 16;
2608 current_frame_info.spill_size = spill_size;
2609 current_frame_info.extra_spill_size = extra_spill_size;
2610 COPY_HARD_REG_SET (current_frame_info.mask, mask);
2611 current_frame_info.n_spilled = n_spilled;
2612 current_frame_info.initialized = reload_completed;
2615 /* Compute the initial difference between the specified pair of registers. */
2618 ia64_initial_elimination_offset (int from, int to)
2620 HOST_WIDE_INT offset;
2622 ia64_compute_frame_size (get_frame_size ());
2625 case FRAME_POINTER_REGNUM:
2628 case HARD_FRAME_POINTER_REGNUM:
2629 if (current_function_is_leaf)
2630 offset = -current_frame_info.total_size;
2632 offset = -(current_frame_info.total_size
2633 - current_function_outgoing_args_size - 16);
2636 case STACK_POINTER_REGNUM:
2637 if (current_function_is_leaf)
2640 offset = 16 + current_function_outgoing_args_size;
2648 case ARG_POINTER_REGNUM:
2649 /* Arguments start above the 16 byte save area, unless stdarg
2650 in which case we store through the 16 byte save area. */
2653 case HARD_FRAME_POINTER_REGNUM:
2654 offset = 16 - current_function_pretend_args_size;
2657 case STACK_POINTER_REGNUM:
2658 offset = (current_frame_info.total_size
2659 + 16 - current_function_pretend_args_size);
2674 /* If there are more than a trivial number of register spills, we use
2675 two interleaved iterators so that we can get two memory references
2678 In order to simplify things in the prologue and epilogue expanders,
2679 we use helper functions to fix up the memory references after the
2680 fact with the appropriate offsets to a POST_MODIFY memory mode.
2681 The following data structure tracks the state of the two iterators
2682 while insns are being emitted. */
2684 struct spill_fill_data
2686 rtx init_after; /* point at which to emit initializations */
2687 rtx init_reg[2]; /* initial base register */
2688 rtx iter_reg[2]; /* the iterator registers */
2689 rtx *prev_addr[2]; /* address of last memory use */
2690 rtx prev_insn[2]; /* the insn corresponding to prev_addr */
2691 HOST_WIDE_INT prev_off[2]; /* last offset */
2692 int n_iter; /* number of iterators in use */
2693 int next_iter; /* next iterator to use */
2694 unsigned int save_gr_used_mask;
2697 static struct spill_fill_data spill_fill_data;
2700 setup_spill_pointers (int n_spills, rtx init_reg, HOST_WIDE_INT cfa_off)
2704 spill_fill_data.init_after = get_last_insn ();
2705 spill_fill_data.init_reg[0] = init_reg;
2706 spill_fill_data.init_reg[1] = init_reg;
2707 spill_fill_data.prev_addr[0] = NULL;
2708 spill_fill_data.prev_addr[1] = NULL;
2709 spill_fill_data.prev_insn[0] = NULL;
2710 spill_fill_data.prev_insn[1] = NULL;
2711 spill_fill_data.prev_off[0] = cfa_off;
2712 spill_fill_data.prev_off[1] = cfa_off;
2713 spill_fill_data.next_iter = 0;
2714 spill_fill_data.save_gr_used_mask = current_frame_info.gr_used_mask;
2716 spill_fill_data.n_iter = 1 + (n_spills > 2);
2717 for (i = 0; i < spill_fill_data.n_iter; ++i)
2719 int regno = next_scratch_gr_reg ();
2720 spill_fill_data.iter_reg[i] = gen_rtx_REG (DImode, regno);
2721 current_frame_info.gr_used_mask |= 1 << regno;
2726 finish_spill_pointers (void)
2728 current_frame_info.gr_used_mask = spill_fill_data.save_gr_used_mask;
2732 spill_restore_mem (rtx reg, HOST_WIDE_INT cfa_off)
2734 int iter = spill_fill_data.next_iter;
2735 HOST_WIDE_INT disp = spill_fill_data.prev_off[iter] - cfa_off;
2736 rtx disp_rtx = GEN_INT (disp);
2739 if (spill_fill_data.prev_addr[iter])
2741 if (CONST_OK_FOR_N (disp))
2743 *spill_fill_data.prev_addr[iter]
2744 = gen_rtx_POST_MODIFY (DImode, spill_fill_data.iter_reg[iter],
2745 gen_rtx_PLUS (DImode,
2746 spill_fill_data.iter_reg[iter],
2748 REG_NOTES (spill_fill_data.prev_insn[iter])
2749 = gen_rtx_EXPR_LIST (REG_INC, spill_fill_data.iter_reg[iter],
2750 REG_NOTES (spill_fill_data.prev_insn[iter]));
2754 /* ??? Could use register post_modify for loads. */
2755 if (! CONST_OK_FOR_I (disp))
2757 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
2758 emit_move_insn (tmp, disp_rtx);
2761 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
2762 spill_fill_data.iter_reg[iter], disp_rtx));
2765 /* Micro-optimization: if we've created a frame pointer, it's at
2766 CFA 0, which may allow the real iterator to be initialized lower,
2767 slightly increasing parallelism. Also, if there are few saves
2768 it may eliminate the iterator entirely. */
2770 && spill_fill_data.init_reg[iter] == stack_pointer_rtx
2771 && frame_pointer_needed)
2773 mem = gen_rtx_MEM (GET_MODE (reg), hard_frame_pointer_rtx);
2774 set_mem_alias_set (mem, get_varargs_alias_set ());
2782 seq = gen_movdi (spill_fill_data.iter_reg[iter],
2783 spill_fill_data.init_reg[iter]);
2788 if (! CONST_OK_FOR_I (disp))
2790 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
2791 emit_move_insn (tmp, disp_rtx);
2795 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
2796 spill_fill_data.init_reg[iter],
2803 /* Careful for being the first insn in a sequence. */
2804 if (spill_fill_data.init_after)
2805 insn = emit_insn_after (seq, spill_fill_data.init_after);
2808 rtx first = get_insns ();
2810 insn = emit_insn_before (seq, first);
2812 insn = emit_insn (seq);
2814 spill_fill_data.init_after = insn;
2816 /* If DISP is 0, we may or may not have a further adjustment
2817 afterward. If we do, then the load/store insn may be modified
2818 to be a post-modify. If we don't, then this copy may be
2819 eliminated by copyprop_hardreg_forward, which makes this
2820 insn garbage, which runs afoul of the sanity check in
2821 propagate_one_insn. So mark this insn as legal to delete. */
2823 REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx,
2827 mem = gen_rtx_MEM (GET_MODE (reg), spill_fill_data.iter_reg[iter]);
2829 /* ??? Not all of the spills are for varargs, but some of them are.
2830 The rest of the spills belong in an alias set of their own. But
2831 it doesn't actually hurt to include them here. */
2832 set_mem_alias_set (mem, get_varargs_alias_set ());
2834 spill_fill_data.prev_addr[iter] = &XEXP (mem, 0);
2835 spill_fill_data.prev_off[iter] = cfa_off;
2837 if (++iter >= spill_fill_data.n_iter)
2839 spill_fill_data.next_iter = iter;
2845 do_spill (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off,
2848 int iter = spill_fill_data.next_iter;
2851 mem = spill_restore_mem (reg, cfa_off);
2852 insn = emit_insn ((*move_fn) (mem, reg, GEN_INT (cfa_off)));
2853 spill_fill_data.prev_insn[iter] = insn;
2860 RTX_FRAME_RELATED_P (insn) = 1;
2862 /* Don't even pretend that the unwind code can intuit its way
2863 through a pair of interleaved post_modify iterators. Just
2864 provide the correct answer. */
2866 if (frame_pointer_needed)
2868 base = hard_frame_pointer_rtx;
2873 base = stack_pointer_rtx;
2874 off = current_frame_info.total_size - cfa_off;
2878 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2879 gen_rtx_SET (VOIDmode,
2880 gen_rtx_MEM (GET_MODE (reg),
2881 plus_constant (base, off)),
2888 do_restore (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off)
2890 int iter = spill_fill_data.next_iter;
2893 insn = emit_insn ((*move_fn) (reg, spill_restore_mem (reg, cfa_off),
2894 GEN_INT (cfa_off)));
2895 spill_fill_data.prev_insn[iter] = insn;
2898 /* Wrapper functions that discards the CONST_INT spill offset. These
2899 exist so that we can give gr_spill/gr_fill the offset they need and
2900 use a consistent function interface. */
2903 gen_movdi_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
2905 return gen_movdi (dest, src);
2909 gen_fr_spill_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
2911 return gen_fr_spill (dest, src);
2915 gen_fr_restore_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
2917 return gen_fr_restore (dest, src);
2920 /* Called after register allocation to add any instructions needed for the
2921 prologue. Using a prologue insn is favored compared to putting all of the
2922 instructions in output_function_prologue(), since it allows the scheduler
2923 to intermix instructions with the saves of the caller saved registers. In
2924 some cases, it might be necessary to emit a barrier instruction as the last
2925 insn to prevent such scheduling.
2927 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
2928 so that the debug info generation code can handle them properly.
2930 The register save area is layed out like so:
2932 [ varargs spill area ]
2933 [ fr register spill area ]
2934 [ br register spill area ]
2935 [ ar register spill area ]
2936 [ pr register spill area ]
2937 [ gr register spill area ] */
2939 /* ??? Get inefficient code when the frame size is larger than can fit in an
2940 adds instruction. */
2943 ia64_expand_prologue (void)
2945 rtx insn, ar_pfs_save_reg, ar_unat_save_reg;
2946 int i, epilogue_p, regno, alt_regno, cfa_off, n_varargs;
2949 ia64_compute_frame_size (get_frame_size ());
2950 last_scratch_gr_reg = 15;
2952 /* If there is no epilogue, then we don't need some prologue insns.
2953 We need to avoid emitting the dead prologue insns, because flow
2954 will complain about them. */
2960 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
2961 if ((e->flags & EDGE_FAKE) == 0
2962 && (e->flags & EDGE_FALLTHRU) != 0)
2964 epilogue_p = (e != NULL);
2969 /* Set the local, input, and output register names. We need to do this
2970 for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in
2971 half. If we use in/loc/out register names, then we get assembler errors
2972 in crtn.S because there is no alloc insn or regstk directive in there. */
2973 if (! TARGET_REG_NAMES)
2975 int inputs = current_frame_info.n_input_regs;
2976 int locals = current_frame_info.n_local_regs;
2977 int outputs = current_frame_info.n_output_regs;
2979 for (i = 0; i < inputs; i++)
2980 reg_names[IN_REG (i)] = ia64_reg_numbers[i];
2981 for (i = 0; i < locals; i++)
2982 reg_names[LOC_REG (i)] = ia64_reg_numbers[inputs + i];
2983 for (i = 0; i < outputs; i++)
2984 reg_names[OUT_REG (i)] = ia64_reg_numbers[inputs + locals + i];
2987 /* Set the frame pointer register name. The regnum is logically loc79,
2988 but of course we'll not have allocated that many locals. Rather than
2989 worrying about renumbering the existing rtxs, we adjust the name. */
2990 /* ??? This code means that we can never use one local register when
2991 there is a frame pointer. loc79 gets wasted in this case, as it is
2992 renamed to a register that will never be used. See also the try_locals
2993 code in find_gr_spill. */
2994 if (current_frame_info.reg_fp)
2996 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
2997 reg_names[HARD_FRAME_POINTER_REGNUM]
2998 = reg_names[current_frame_info.reg_fp];
2999 reg_names[current_frame_info.reg_fp] = tmp;
3002 /* We don't need an alloc instruction if we've used no outputs or locals. */
3003 if (current_frame_info.n_local_regs == 0
3004 && current_frame_info.n_output_regs == 0
3005 && current_frame_info.n_input_regs <= current_function_args_info.int_regs
3006 && !TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM))
3008 /* If there is no alloc, but there are input registers used, then we
3009 need a .regstk directive. */
3010 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
3011 ar_pfs_save_reg = NULL_RTX;
3015 current_frame_info.need_regstk = 0;
3017 if (current_frame_info.reg_save_ar_pfs)
3018 regno = current_frame_info.reg_save_ar_pfs;
3020 regno = next_scratch_gr_reg ();
3021 ar_pfs_save_reg = gen_rtx_REG (DImode, regno);
3023 insn = emit_insn (gen_alloc (ar_pfs_save_reg,
3024 GEN_INT (current_frame_info.n_input_regs),
3025 GEN_INT (current_frame_info.n_local_regs),
3026 GEN_INT (current_frame_info.n_output_regs),
3027 GEN_INT (current_frame_info.n_rotate_regs)));
3028 RTX_FRAME_RELATED_P (insn) = (current_frame_info.reg_save_ar_pfs != 0);
3031 /* Set up frame pointer, stack pointer, and spill iterators. */
3033 n_varargs = cfun->machine->n_varargs;
3034 setup_spill_pointers (current_frame_info.n_spilled + n_varargs,
3035 stack_pointer_rtx, 0);
3037 if (frame_pointer_needed)
3039 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
3040 RTX_FRAME_RELATED_P (insn) = 1;
3043 if (current_frame_info.total_size != 0)
3045 rtx frame_size_rtx = GEN_INT (- current_frame_info.total_size);
3048 if (CONST_OK_FOR_I (- current_frame_info.total_size))
3049 offset = frame_size_rtx;
3052 regno = next_scratch_gr_reg ();
3053 offset = gen_rtx_REG (DImode, regno);
3054 emit_move_insn (offset, frame_size_rtx);
3057 insn = emit_insn (gen_adddi3 (stack_pointer_rtx,
3058 stack_pointer_rtx, offset));
3060 if (! frame_pointer_needed)
3062 RTX_FRAME_RELATED_P (insn) = 1;
3063 if (GET_CODE (offset) != CONST_INT)
3066 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3067 gen_rtx_SET (VOIDmode,
3069 gen_rtx_PLUS (DImode,
3076 /* ??? At this point we must generate a magic insn that appears to
3077 modify the stack pointer, the frame pointer, and all spill
3078 iterators. This would allow the most scheduling freedom. For
3079 now, just hard stop. */
3080 emit_insn (gen_blockage ());
3083 /* Must copy out ar.unat before doing any integer spills. */
3084 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
3086 if (current_frame_info.reg_save_ar_unat)
3088 = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_unat);
3091 alt_regno = next_scratch_gr_reg ();
3092 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
3093 current_frame_info.gr_used_mask |= 1 << alt_regno;
3096 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3097 insn = emit_move_insn (ar_unat_save_reg, reg);
3098 RTX_FRAME_RELATED_P (insn) = (current_frame_info.reg_save_ar_unat != 0);
3100 /* Even if we're not going to generate an epilogue, we still
3101 need to save the register so that EH works. */
3102 if (! epilogue_p && current_frame_info.reg_save_ar_unat)
3103 emit_insn (gen_prologue_use (ar_unat_save_reg));
3106 ar_unat_save_reg = NULL_RTX;
3108 /* Spill all varargs registers. Do this before spilling any GR registers,
3109 since we want the UNAT bits for the GR registers to override the UNAT
3110 bits from varargs, which we don't care about. */
3113 for (regno = GR_ARG_FIRST + 7; n_varargs > 0; --n_varargs, --regno)
3115 reg = gen_rtx_REG (DImode, regno);
3116 do_spill (gen_gr_spill, reg, cfa_off += 8, NULL_RTX);
3119 /* Locate the bottom of the register save area. */
3120 cfa_off = (current_frame_info.spill_cfa_off
3121 + current_frame_info.spill_size
3122 + current_frame_info.extra_spill_size);
3124 /* Save the predicate register block either in a register or in memory. */
3125 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
3127 reg = gen_rtx_REG (DImode, PR_REG (0));
3128 if (current_frame_info.reg_save_pr != 0)
3130 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_pr);
3131 insn = emit_move_insn (alt_reg, reg);
3133 /* ??? Denote pr spill/fill by a DImode move that modifies all
3134 64 hard registers. */
3135 RTX_FRAME_RELATED_P (insn) = 1;
3137 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3138 gen_rtx_SET (VOIDmode, alt_reg, reg),
3141 /* Even if we're not going to generate an epilogue, we still
3142 need to save the register so that EH works. */
3144 emit_insn (gen_prologue_use (alt_reg));
3148 alt_regno = next_scratch_gr_reg ();
3149 alt_reg = gen_rtx_REG (DImode, alt_regno);
3150 insn = emit_move_insn (alt_reg, reg);
3151 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3156 /* Handle AR regs in numerical order. All of them get special handling. */
3157 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM)
3158 && current_frame_info.reg_save_ar_unat == 0)
3160 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3161 do_spill (gen_movdi_x, ar_unat_save_reg, cfa_off, reg);
3165 /* The alloc insn already copied ar.pfs into a general register. The
3166 only thing we have to do now is copy that register to a stack slot
3167 if we'd not allocated a local register for the job. */
3168 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM)
3169 && current_frame_info.reg_save_ar_pfs == 0)
3171 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3172 do_spill (gen_movdi_x, ar_pfs_save_reg, cfa_off, reg);
3176 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
3178 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
3179 if (current_frame_info.reg_save_ar_lc != 0)
3181 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_lc);
3182 insn = emit_move_insn (alt_reg, reg);
3183 RTX_FRAME_RELATED_P (insn) = 1;
3185 /* Even if we're not going to generate an epilogue, we still
3186 need to save the register so that EH works. */
3188 emit_insn (gen_prologue_use (alt_reg));
3192 alt_regno = next_scratch_gr_reg ();
3193 alt_reg = gen_rtx_REG (DImode, alt_regno);
3194 emit_move_insn (alt_reg, reg);
3195 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3200 /* Save the return pointer. */
3201 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3203 reg = gen_rtx_REG (DImode, BR_REG (0));
3204 if (current_frame_info.reg_save_b0 != 0)
3206 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
3207 insn = emit_move_insn (alt_reg, reg);
3208 RTX_FRAME_RELATED_P (insn) = 1;
3210 /* Even if we're not going to generate an epilogue, we still
3211 need to save the register so that EH works. */
3213 emit_insn (gen_prologue_use (alt_reg));
3217 alt_regno = next_scratch_gr_reg ();
3218 alt_reg = gen_rtx_REG (DImode, alt_regno);
3219 emit_move_insn (alt_reg, reg);
3220 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3225 if (current_frame_info.reg_save_gp)
3227 insn = emit_move_insn (gen_rtx_REG (DImode,
3228 current_frame_info.reg_save_gp),
3229 pic_offset_table_rtx);
3230 /* We don't know for sure yet if this is actually needed, since
3231 we've not split the PIC call patterns. If all of the calls
3232 are indirect, and not followed by any uses of the gp, then
3233 this save is dead. Allow it to go away. */
3235 = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx, REG_NOTES (insn));
3238 /* We should now be at the base of the gr/br/fr spill area. */
3239 gcc_assert (cfa_off == (current_frame_info.spill_cfa_off
3240 + current_frame_info.spill_size));
3242 /* Spill all general registers. */
3243 for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
3244 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3246 reg = gen_rtx_REG (DImode, regno);
3247 do_spill (gen_gr_spill, reg, cfa_off, reg);
3251 /* Spill the rest of the BR registers. */
3252 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
3253 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3255 alt_regno = next_scratch_gr_reg ();
3256 alt_reg = gen_rtx_REG (DImode, alt_regno);
3257 reg = gen_rtx_REG (DImode, regno);
3258 emit_move_insn (alt_reg, reg);
3259 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3263 /* Align the frame and spill all FR registers. */
3264 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
3265 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3267 gcc_assert (!(cfa_off & 15));
3268 reg = gen_rtx_REG (XFmode, regno);
3269 do_spill (gen_fr_spill_x, reg, cfa_off, reg);
3273 gcc_assert (cfa_off == current_frame_info.spill_cfa_off);
3275 finish_spill_pointers ();
3278 /* Called after register allocation to add any instructions needed for the
3279 epilogue. Using an epilogue insn is favored compared to putting all of the
3280 instructions in output_function_prologue(), since it allows the scheduler
3281 to intermix instructions with the saves of the caller saved registers. In
3282 some cases, it might be necessary to emit a barrier instruction as the last
3283 insn to prevent such scheduling. */
3286 ia64_expand_epilogue (int sibcall_p)
3288 rtx insn, reg, alt_reg, ar_unat_save_reg;
3289 int regno, alt_regno, cfa_off;
3291 ia64_compute_frame_size (get_frame_size ());
3293 /* If there is a frame pointer, then we use it instead of the stack
3294 pointer, so that the stack pointer does not need to be valid when
3295 the epilogue starts. See EXIT_IGNORE_STACK. */
3296 if (frame_pointer_needed)
3297 setup_spill_pointers (current_frame_info.n_spilled,
3298 hard_frame_pointer_rtx, 0);
3300 setup_spill_pointers (current_frame_info.n_spilled, stack_pointer_rtx,
3301 current_frame_info.total_size);
3303 if (current_frame_info.total_size != 0)
3305 /* ??? At this point we must generate a magic insn that appears to
3306 modify the spill iterators and the frame pointer. This would
3307 allow the most scheduling freedom. For now, just hard stop. */
3308 emit_insn (gen_blockage ());
3311 /* Locate the bottom of the register save area. */
3312 cfa_off = (current_frame_info.spill_cfa_off
3313 + current_frame_info.spill_size
3314 + current_frame_info.extra_spill_size);
3316 /* Restore the predicate registers. */
3317 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
3319 if (current_frame_info.reg_save_pr != 0)
3320 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_pr);
3323 alt_regno = next_scratch_gr_reg ();
3324 alt_reg = gen_rtx_REG (DImode, alt_regno);
3325 do_restore (gen_movdi_x, alt_reg, cfa_off);
3328 reg = gen_rtx_REG (DImode, PR_REG (0));
3329 emit_move_insn (reg, alt_reg);
3332 /* Restore the application registers. */
3334 /* Load the saved unat from the stack, but do not restore it until
3335 after the GRs have been restored. */
3336 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
3338 if (current_frame_info.reg_save_ar_unat != 0)
3340 = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_unat);
3343 alt_regno = next_scratch_gr_reg ();
3344 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
3345 current_frame_info.gr_used_mask |= 1 << alt_regno;
3346 do_restore (gen_movdi_x, ar_unat_save_reg, cfa_off);
3351 ar_unat_save_reg = NULL_RTX;
3353 if (current_frame_info.reg_save_ar_pfs != 0)
3355 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_pfs);
3356 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3357 emit_move_insn (reg, alt_reg);
3359 else if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM))
3361 alt_regno = next_scratch_gr_reg ();
3362 alt_reg = gen_rtx_REG (DImode, alt_regno);
3363 do_restore (gen_movdi_x, alt_reg, cfa_off);
3365 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3366 emit_move_insn (reg, alt_reg);
3369 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
3371 if (current_frame_info.reg_save_ar_lc != 0)
3372 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_lc);
3375 alt_regno = next_scratch_gr_reg ();
3376 alt_reg = gen_rtx_REG (DImode, alt_regno);
3377 do_restore (gen_movdi_x, alt_reg, cfa_off);
3380 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
3381 emit_move_insn (reg, alt_reg);
3384 /* Restore the return pointer. */
3385 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3387 if (current_frame_info.reg_save_b0 != 0)
3388 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
3391 alt_regno = next_scratch_gr_reg ();
3392 alt_reg = gen_rtx_REG (DImode, alt_regno);
3393 do_restore (gen_movdi_x, alt_reg, cfa_off);
3396 reg = gen_rtx_REG (DImode, BR_REG (0));
3397 emit_move_insn (reg, alt_reg);
3400 /* We should now be at the base of the gr/br/fr spill area. */
3401 gcc_assert (cfa_off == (current_frame_info.spill_cfa_off
3402 + current_frame_info.spill_size));
3404 /* The GP may be stored on the stack in the prologue, but it's
3405 never restored in the epilogue. Skip the stack slot. */
3406 if (TEST_HARD_REG_BIT (current_frame_info.mask, GR_REG (1)))
3409 /* Restore all general registers. */
3410 for (regno = GR_REG (2); regno <= GR_REG (31); ++regno)
3411 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3413 reg = gen_rtx_REG (DImode, regno);
3414 do_restore (gen_gr_restore, reg, cfa_off);
3418 /* Restore the branch registers. */
3419 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
3420 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3422 alt_regno = next_scratch_gr_reg ();
3423 alt_reg = gen_rtx_REG (DImode, alt_regno);
3424 do_restore (gen_movdi_x, alt_reg, cfa_off);
3426 reg = gen_rtx_REG (DImode, regno);
3427 emit_move_insn (reg, alt_reg);
3430 /* Restore floating point registers. */
3431 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
3432 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3434 gcc_assert (!(cfa_off & 15));
3435 reg = gen_rtx_REG (XFmode, regno);
3436 do_restore (gen_fr_restore_x, reg, cfa_off);
3440 /* Restore ar.unat for real. */
3441 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
3443 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3444 emit_move_insn (reg, ar_unat_save_reg);
3447 gcc_assert (cfa_off == current_frame_info.spill_cfa_off);
3449 finish_spill_pointers ();
3451 if (current_frame_info.total_size || cfun->machine->ia64_eh_epilogue_sp)
3453 /* ??? At this point we must generate a magic insn that appears to
3454 modify the spill iterators, the stack pointer, and the frame
3455 pointer. This would allow the most scheduling freedom. For now,
3457 emit_insn (gen_blockage ());
3460 if (cfun->machine->ia64_eh_epilogue_sp)
3461 emit_move_insn (stack_pointer_rtx, cfun->machine->ia64_eh_epilogue_sp);
3462 else if (frame_pointer_needed)
3464 insn = emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
3465 RTX_FRAME_RELATED_P (insn) = 1;
3467 else if (current_frame_info.total_size)
3469 rtx offset, frame_size_rtx;
3471 frame_size_rtx = GEN_INT (current_frame_info.total_size);
3472 if (CONST_OK_FOR_I (current_frame_info.total_size))
3473 offset = frame_size_rtx;
3476 regno = next_scratch_gr_reg ();
3477 offset = gen_rtx_REG (DImode, regno);
3478 emit_move_insn (offset, frame_size_rtx);
3481 insn = emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
3484 RTX_FRAME_RELATED_P (insn) = 1;
3485 if (GET_CODE (offset) != CONST_INT)
3488 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3489 gen_rtx_SET (VOIDmode,
3491 gen_rtx_PLUS (DImode,
3498 if (cfun->machine->ia64_eh_epilogue_bsp)
3499 emit_insn (gen_set_bsp (cfun->machine->ia64_eh_epilogue_bsp));
3502 emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode, BR_REG (0))));
3505 int fp = GR_REG (2);
3506 /* We need a throw away register here, r0 and r1 are reserved, so r2 is the
3507 first available call clobbered register. If there was a frame_pointer
3508 register, we may have swapped the names of r2 and HARD_FRAME_POINTER_REGNUM,
3509 so we have to make sure we're using the string "r2" when emitting
3510 the register name for the assembler. */
3511 if (current_frame_info.reg_fp && current_frame_info.reg_fp == GR_REG (2))
3512 fp = HARD_FRAME_POINTER_REGNUM;
3514 /* We must emit an alloc to force the input registers to become output
3515 registers. Otherwise, if the callee tries to pass its parameters
3516 through to another call without an intervening alloc, then these
3518 /* ??? We don't need to preserve all input registers. We only need to
3519 preserve those input registers used as arguments to the sibling call.
3520 It is unclear how to compute that number here. */
3521 if (current_frame_info.n_input_regs != 0)
3523 rtx n_inputs = GEN_INT (current_frame_info.n_input_regs);
3524 insn = emit_insn (gen_alloc (gen_rtx_REG (DImode, fp),
3525 const0_rtx, const0_rtx,
3526 n_inputs, const0_rtx));
3527 RTX_FRAME_RELATED_P (insn) = 1;
3532 /* Return 1 if br.ret can do all the work required to return from a
3536 ia64_direct_return (void)
3538 if (reload_completed && ! frame_pointer_needed)
3540 ia64_compute_frame_size (get_frame_size ());
3542 return (current_frame_info.total_size == 0
3543 && current_frame_info.n_spilled == 0
3544 && current_frame_info.reg_save_b0 == 0
3545 && current_frame_info.reg_save_pr == 0
3546 && current_frame_info.reg_save_ar_pfs == 0
3547 && current_frame_info.reg_save_ar_unat == 0
3548 && current_frame_info.reg_save_ar_lc == 0);
3553 /* Return the magic cookie that we use to hold the return address
3554 during early compilation. */
3557 ia64_return_addr_rtx (HOST_WIDE_INT count, rtx frame ATTRIBUTE_UNUSED)
3561 return gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_RET_ADDR);
3564 /* Split this value after reload, now that we know where the return
3565 address is saved. */
3568 ia64_split_return_addr_rtx (rtx dest)
3572 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3574 if (current_frame_info.reg_save_b0 != 0)
3575 src = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
3581 /* Compute offset from CFA for BR0. */
3582 /* ??? Must be kept in sync with ia64_expand_prologue. */
3583 off = (current_frame_info.spill_cfa_off
3584 + current_frame_info.spill_size);
3585 for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
3586 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3589 /* Convert CFA offset to a register based offset. */
3590 if (frame_pointer_needed)
3591 src = hard_frame_pointer_rtx;
3594 src = stack_pointer_rtx;
3595 off += current_frame_info.total_size;
3598 /* Load address into scratch register. */
3599 if (CONST_OK_FOR_I (off))
3600 emit_insn (gen_adddi3 (dest, src, GEN_INT (off)));
3603 emit_move_insn (dest, GEN_INT (off));
3604 emit_insn (gen_adddi3 (dest, src, dest));
3607 src = gen_rtx_MEM (Pmode, dest);
3611 src = gen_rtx_REG (DImode, BR_REG (0));
3613 emit_move_insn (dest, src);
3617 ia64_hard_regno_rename_ok (int from, int to)
3619 /* Don't clobber any of the registers we reserved for the prologue. */
3620 if (to == current_frame_info.reg_fp
3621 || to == current_frame_info.reg_save_b0
3622 || to == current_frame_info.reg_save_pr
3623 || to == current_frame_info.reg_save_ar_pfs
3624 || to == current_frame_info.reg_save_ar_unat
3625 || to == current_frame_info.reg_save_ar_lc)
3628 if (from == current_frame_info.reg_fp
3629 || from == current_frame_info.reg_save_b0
3630 || from == current_frame_info.reg_save_pr
3631 || from == current_frame_info.reg_save_ar_pfs
3632 || from == current_frame_info.reg_save_ar_unat
3633 || from == current_frame_info.reg_save_ar_lc)
3636 /* Don't use output registers outside the register frame. */
3637 if (OUT_REGNO_P (to) && to >= OUT_REG (current_frame_info.n_output_regs))
3640 /* Retain even/oddness on predicate register pairs. */
3641 if (PR_REGNO_P (from) && PR_REGNO_P (to))
3642 return (from & 1) == (to & 1);
3647 /* Target hook for assembling integer objects. Handle word-sized
3648 aligned objects and detect the cases when @fptr is needed. */
3651 ia64_assemble_integer (rtx x, unsigned int size, int aligned_p)
3653 if (size == POINTER_SIZE / BITS_PER_UNIT
3654 && !(TARGET_NO_PIC || TARGET_AUTO_PIC)
3655 && GET_CODE (x) == SYMBOL_REF
3656 && SYMBOL_REF_FUNCTION_P (x))
3658 static const char * const directive[2][2] = {
3659 /* 64-bit pointer */ /* 32-bit pointer */
3660 { "\tdata8.ua\t@fptr(", "\tdata4.ua\t@fptr("}, /* unaligned */
3661 { "\tdata8\t@fptr(", "\tdata4\t@fptr("} /* aligned */
3663 fputs (directive[(aligned_p != 0)][POINTER_SIZE == 32], asm_out_file);
3664 output_addr_const (asm_out_file, x);
3665 fputs (")\n", asm_out_file);
3668 return default_assemble_integer (x, size, aligned_p);
3671 /* Emit the function prologue. */
3674 ia64_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3676 int mask, grsave, grsave_prev;
3678 if (current_frame_info.need_regstk)
3679 fprintf (file, "\t.regstk %d, %d, %d, %d\n",
3680 current_frame_info.n_input_regs,
3681 current_frame_info.n_local_regs,
3682 current_frame_info.n_output_regs,
3683 current_frame_info.n_rotate_regs);
3685 if (!flag_unwind_tables && (!flag_exceptions || USING_SJLJ_EXCEPTIONS))
3688 /* Emit the .prologue directive. */
3691 grsave = grsave_prev = 0;
3692 if (current_frame_info.reg_save_b0 != 0)
3695 grsave = grsave_prev = current_frame_info.reg_save_b0;
3697 if (current_frame_info.reg_save_ar_pfs != 0
3698 && (grsave_prev == 0
3699 || current_frame_info.reg_save_ar_pfs == grsave_prev + 1))
3702 if (grsave_prev == 0)
3703 grsave = current_frame_info.reg_save_ar_pfs;
3704 grsave_prev = current_frame_info.reg_save_ar_pfs;
3706 if (current_frame_info.reg_fp != 0
3707 && (grsave_prev == 0
3708 || current_frame_info.reg_fp == grsave_prev + 1))
3711 if (grsave_prev == 0)
3712 grsave = HARD_FRAME_POINTER_REGNUM;
3713 grsave_prev = current_frame_info.reg_fp;
3715 if (current_frame_info.reg_save_pr != 0
3716 && (grsave_prev == 0
3717 || current_frame_info.reg_save_pr == grsave_prev + 1))
3720 if (grsave_prev == 0)
3721 grsave = current_frame_info.reg_save_pr;
3724 if (mask && TARGET_GNU_AS)
3725 fprintf (file, "\t.prologue %d, %d\n", mask,
3726 ia64_dbx_register_number (grsave));
3728 fputs ("\t.prologue\n", file);
3730 /* Emit a .spill directive, if necessary, to relocate the base of
3731 the register spill area. */
3732 if (current_frame_info.spill_cfa_off != -16)
3733 fprintf (file, "\t.spill %ld\n",
3734 (long) (current_frame_info.spill_cfa_off
3735 + current_frame_info.spill_size));
3738 /* Emit the .body directive at the scheduled end of the prologue. */
3741 ia64_output_function_end_prologue (FILE *file)
3743 if (!flag_unwind_tables && (!flag_exceptions || USING_SJLJ_EXCEPTIONS))
3746 fputs ("\t.body\n", file);
3749 /* Emit the function epilogue. */
3752 ia64_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
3753 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3757 if (current_frame_info.reg_fp)
3759 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
3760 reg_names[HARD_FRAME_POINTER_REGNUM]
3761 = reg_names[current_frame_info.reg_fp];
3762 reg_names[current_frame_info.reg_fp] = tmp;
3764 if (! TARGET_REG_NAMES)
3766 for (i = 0; i < current_frame_info.n_input_regs; i++)
3767 reg_names[IN_REG (i)] = ia64_input_reg_names[i];
3768 for (i = 0; i < current_frame_info.n_local_regs; i++)
3769 reg_names[LOC_REG (i)] = ia64_local_reg_names[i];
3770 for (i = 0; i < current_frame_info.n_output_regs; i++)
3771 reg_names[OUT_REG (i)] = ia64_output_reg_names[i];
3774 current_frame_info.initialized = 0;
3778 ia64_dbx_register_number (int regno)
3780 /* In ia64_expand_prologue we quite literally renamed the frame pointer
3781 from its home at loc79 to something inside the register frame. We
3782 must perform the same renumbering here for the debug info. */
3783 if (current_frame_info.reg_fp)
3785 if (regno == HARD_FRAME_POINTER_REGNUM)
3786 regno = current_frame_info.reg_fp;
3787 else if (regno == current_frame_info.reg_fp)
3788 regno = HARD_FRAME_POINTER_REGNUM;
3791 if (IN_REGNO_P (regno))
3792 return 32 + regno - IN_REG (0);
3793 else if (LOC_REGNO_P (regno))
3794 return 32 + current_frame_info.n_input_regs + regno - LOC_REG (0);
3795 else if (OUT_REGNO_P (regno))
3796 return (32 + current_frame_info.n_input_regs
3797 + current_frame_info.n_local_regs + regno - OUT_REG (0));
3803 ia64_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
3805 rtx addr_reg, eight = GEN_INT (8);
3807 /* The Intel assembler requires that the global __ia64_trampoline symbol
3808 be declared explicitly */
3811 static bool declared_ia64_trampoline = false;
3813 if (!declared_ia64_trampoline)
3815 declared_ia64_trampoline = true;
3816 (*targetm.asm_out.globalize_label) (asm_out_file,
3817 "__ia64_trampoline");
3821 /* Make sure addresses are Pmode even if we are in ILP32 mode. */
3822 addr = convert_memory_address (Pmode, addr);
3823 fnaddr = convert_memory_address (Pmode, fnaddr);
3824 static_chain = convert_memory_address (Pmode, static_chain);
3826 /* Load up our iterator. */
3827 addr_reg = gen_reg_rtx (Pmode);
3828 emit_move_insn (addr_reg, addr);
3830 /* The first two words are the fake descriptor:
3831 __ia64_trampoline, ADDR+16. */
3832 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg),
3833 gen_rtx_SYMBOL_REF (Pmode, "__ia64_trampoline"));
3834 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
3836 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg),
3837 copy_to_reg (plus_constant (addr, 16)));
3838 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
3840 /* The third word is the target descriptor. */
3841 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg), fnaddr);
3842 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
3844 /* The fourth word is the static chain. */
3845 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg), static_chain);
3848 /* Do any needed setup for a variadic function. CUM has not been updated
3849 for the last named argument which has type TYPE and mode MODE.
3851 We generate the actual spill instructions during prologue generation. */
3854 ia64_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3855 tree type, int * pretend_size,
3856 int second_time ATTRIBUTE_UNUSED)
3858 CUMULATIVE_ARGS next_cum = *cum;
3860 /* Skip the current argument. */
3861 ia64_function_arg_advance (&next_cum, mode, type, 1);
3863 if (next_cum.words < MAX_ARGUMENT_SLOTS)
3865 int n = MAX_ARGUMENT_SLOTS - next_cum.words;
3866 *pretend_size = n * UNITS_PER_WORD;
3867 cfun->machine->n_varargs = n;
3871 /* Check whether TYPE is a homogeneous floating point aggregate. If
3872 it is, return the mode of the floating point type that appears
3873 in all leafs. If it is not, return VOIDmode.
3875 An aggregate is a homogeneous floating point aggregate is if all
3876 fields/elements in it have the same floating point type (e.g,
3877 SFmode). 128-bit quad-precision floats are excluded.
3879 Variable sized aggregates should never arrive here, since we should
3880 have already decided to pass them by reference. Top-level zero-sized
3881 aggregates are excluded because our parallels crash the middle-end. */
3883 static enum machine_mode
3884 hfa_element_mode (tree type, bool nested)
3886 enum machine_mode element_mode = VOIDmode;
3887 enum machine_mode mode;
3888 enum tree_code code = TREE_CODE (type);
3889 int know_element_mode = 0;
3892 if (!nested && (!TYPE_SIZE (type) || integer_zerop (TYPE_SIZE (type))))
3897 case VOID_TYPE: case INTEGER_TYPE: case ENUMERAL_TYPE:
3898 case BOOLEAN_TYPE: case POINTER_TYPE:
3899 case OFFSET_TYPE: case REFERENCE_TYPE: case METHOD_TYPE:
3900 case LANG_TYPE: case FUNCTION_TYPE:
3903 /* Fortran complex types are supposed to be HFAs, so we need to handle
3904 gcc's COMPLEX_TYPEs as HFAs. We need to exclude the integral complex
3907 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_FLOAT
3908 && TYPE_MODE (type) != TCmode)
3909 return GET_MODE_INNER (TYPE_MODE (type));
3914 /* We want to return VOIDmode for raw REAL_TYPEs, but the actual
3915 mode if this is contained within an aggregate. */
3916 if (nested && TYPE_MODE (type) != TFmode)
3917 return TYPE_MODE (type);
3922 return hfa_element_mode (TREE_TYPE (type), 1);
3926 case QUAL_UNION_TYPE:
3927 for (t = TYPE_FIELDS (type); t; t = TREE_CHAIN (t))
3929 if (TREE_CODE (t) != FIELD_DECL)
3932 mode = hfa_element_mode (TREE_TYPE (t), 1);
3933 if (know_element_mode)
3935 if (mode != element_mode)
3938 else if (GET_MODE_CLASS (mode) != MODE_FLOAT)
3942 know_element_mode = 1;
3943 element_mode = mode;
3946 return element_mode;
3949 /* If we reach here, we probably have some front-end specific type
3950 that the backend doesn't know about. This can happen via the
3951 aggregate_value_p call in init_function_start. All we can do is
3952 ignore unknown tree types. */
3959 /* Return the number of words required to hold a quantity of TYPE and MODE
3960 when passed as an argument. */
3962 ia64_function_arg_words (tree type, enum machine_mode mode)
3966 if (mode == BLKmode)
3967 words = int_size_in_bytes (type);
3969 words = GET_MODE_SIZE (mode);
3971 return (words + UNITS_PER_WORD - 1) / UNITS_PER_WORD; /* round up */
3974 /* Return the number of registers that should be skipped so the current
3975 argument (described by TYPE and WORDS) will be properly aligned.
3977 Integer and float arguments larger than 8 bytes start at the next
3978 even boundary. Aggregates larger than 8 bytes start at the next
3979 even boundary if the aggregate has 16 byte alignment. Note that
3980 in the 32-bit ABI, TImode and TFmode have only 8-byte alignment
3981 but are still to be aligned in registers.
3983 ??? The ABI does not specify how to handle aggregates with
3984 alignment from 9 to 15 bytes, or greater than 16. We handle them
3985 all as if they had 16 byte alignment. Such aggregates can occur
3986 only if gcc extensions are used. */
3988 ia64_function_arg_offset (CUMULATIVE_ARGS *cum, tree type, int words)
3990 if ((cum->words & 1) == 0)
3994 && TREE_CODE (type) != INTEGER_TYPE
3995 && TREE_CODE (type) != REAL_TYPE)
3996 return TYPE_ALIGN (type) > 8 * BITS_PER_UNIT;
4001 /* Return rtx for register where argument is passed, or zero if it is passed
4003 /* ??? 128-bit quad-precision floats are always passed in general
4007 ia64_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
4008 int named, int incoming)
4010 int basereg = (incoming ? GR_ARG_FIRST : AR_ARG_FIRST);
4011 int words = ia64_function_arg_words (type, mode);
4012 int offset = ia64_function_arg_offset (cum, type, words);
4013 enum machine_mode hfa_mode = VOIDmode;
4015 /* If all argument slots are used, then it must go on the stack. */
4016 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
4019 /* Check for and handle homogeneous FP aggregates. */
4021 hfa_mode = hfa_element_mode (type, 0);
4023 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
4024 and unprototyped hfas are passed specially. */
4025 if (hfa_mode != VOIDmode && (! cum->prototype || named))
4029 int fp_regs = cum->fp_regs;
4030 int int_regs = cum->words + offset;
4031 int hfa_size = GET_MODE_SIZE (hfa_mode);
4035 /* If prototyped, pass it in FR regs then GR regs.
4036 If not prototyped, pass it in both FR and GR regs.
4038 If this is an SFmode aggregate, then it is possible to run out of
4039 FR regs while GR regs are still left. In that case, we pass the
4040 remaining part in the GR regs. */
4042 /* Fill the FP regs. We do this always. We stop if we reach the end
4043 of the argument, the last FP register, or the last argument slot. */
4045 byte_size = ((mode == BLKmode)
4046 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4047 args_byte_size = int_regs * UNITS_PER_WORD;
4049 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
4050 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD)); i++)
4052 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4053 gen_rtx_REG (hfa_mode, (FR_ARG_FIRST
4057 args_byte_size += hfa_size;
4061 /* If no prototype, then the whole thing must go in GR regs. */
4062 if (! cum->prototype)
4064 /* If this is an SFmode aggregate, then we might have some left over
4065 that needs to go in GR regs. */
4066 else if (byte_size != offset)
4067 int_regs += offset / UNITS_PER_WORD;
4069 /* Fill in the GR regs. We must use DImode here, not the hfa mode. */
4071 for (; offset < byte_size && int_regs < MAX_ARGUMENT_SLOTS; i++)
4073 enum machine_mode gr_mode = DImode;
4074 unsigned int gr_size;
4076 /* If we have an odd 4 byte hunk because we ran out of FR regs,
4077 then this goes in a GR reg left adjusted/little endian, right
4078 adjusted/big endian. */
4079 /* ??? Currently this is handled wrong, because 4-byte hunks are
4080 always right adjusted/little endian. */
4083 /* If we have an even 4 byte hunk because the aggregate is a
4084 multiple of 4 bytes in size, then this goes in a GR reg right
4085 adjusted/little endian. */
4086 else if (byte_size - offset == 4)
4089 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4090 gen_rtx_REG (gr_mode, (basereg
4094 gr_size = GET_MODE_SIZE (gr_mode);
4096 if (gr_size == UNITS_PER_WORD
4097 || (gr_size < UNITS_PER_WORD && offset % UNITS_PER_WORD == 0))
4099 else if (gr_size > UNITS_PER_WORD)
4100 int_regs += gr_size / UNITS_PER_WORD;
4102 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4105 /* Integral and aggregates go in general registers. If we have run out of
4106 FR registers, then FP values must also go in general registers. This can
4107 happen when we have a SFmode HFA. */
4108 else if (mode == TFmode || mode == TCmode
4109 || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
4111 int byte_size = ((mode == BLKmode)
4112 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4113 if (BYTES_BIG_ENDIAN
4114 && (mode == BLKmode || (type && AGGREGATE_TYPE_P (type)))
4115 && byte_size < UNITS_PER_WORD
4118 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
4119 gen_rtx_REG (DImode,
4120 (basereg + cum->words
4123 return gen_rtx_PARALLEL (mode, gen_rtvec (1, gr_reg));
4126 return gen_rtx_REG (mode, basereg + cum->words + offset);
4130 /* If there is a prototype, then FP values go in a FR register when
4131 named, and in a GR register when unnamed. */
4132 else if (cum->prototype)
4135 return gen_rtx_REG (mode, FR_ARG_FIRST + cum->fp_regs);
4136 /* In big-endian mode, an anonymous SFmode value must be represented
4137 as (parallel:SF [(expr_list (reg:DI n) (const_int 0))]) to force
4138 the value into the high half of the general register. */
4139 else if (BYTES_BIG_ENDIAN && mode == SFmode)
4140 return gen_rtx_PARALLEL (mode,
4142 gen_rtx_EXPR_LIST (VOIDmode,
4143 gen_rtx_REG (DImode, basereg + cum->words + offset),
4146 return gen_rtx_REG (mode, basereg + cum->words + offset);
4148 /* If there is no prototype, then FP values go in both FR and GR
4152 /* See comment above. */
4153 enum machine_mode inner_mode =
4154 (BYTES_BIG_ENDIAN && mode == SFmode) ? DImode : mode;
4156 rtx fp_reg = gen_rtx_EXPR_LIST (VOIDmode,
4157 gen_rtx_REG (mode, (FR_ARG_FIRST
4160 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
4161 gen_rtx_REG (inner_mode,
4162 (basereg + cum->words
4166 return gen_rtx_PARALLEL (mode, gen_rtvec (2, fp_reg, gr_reg));
4170 /* Return number of bytes, at the beginning of the argument, that must be
4171 put in registers. 0 is the argument is entirely in registers or entirely
4175 ia64_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4176 tree type, bool named ATTRIBUTE_UNUSED)
4178 int words = ia64_function_arg_words (type, mode);
4179 int offset = ia64_function_arg_offset (cum, type, words);
4181 /* If all argument slots are used, then it must go on the stack. */
4182 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
4185 /* It doesn't matter whether the argument goes in FR or GR regs. If
4186 it fits within the 8 argument slots, then it goes entirely in
4187 registers. If it extends past the last argument slot, then the rest
4188 goes on the stack. */
4190 if (words + cum->words + offset <= MAX_ARGUMENT_SLOTS)
4193 return (MAX_ARGUMENT_SLOTS - cum->words - offset) * UNITS_PER_WORD;
4196 /* Update CUM to point after this argument. This is patterned after
4197 ia64_function_arg. */
4200 ia64_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4201 tree type, int named)
4203 int words = ia64_function_arg_words (type, mode);
4204 int offset = ia64_function_arg_offset (cum, type, words);
4205 enum machine_mode hfa_mode = VOIDmode;
4207 /* If all arg slots are already full, then there is nothing to do. */
4208 if (cum->words >= MAX_ARGUMENT_SLOTS)
4211 cum->words += words + offset;
4213 /* Check for and handle homogeneous FP aggregates. */
4215 hfa_mode = hfa_element_mode (type, 0);
4217 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
4218 and unprototyped hfas are passed specially. */
4219 if (hfa_mode != VOIDmode && (! cum->prototype || named))
4221 int fp_regs = cum->fp_regs;
4222 /* This is the original value of cum->words + offset. */
4223 int int_regs = cum->words - words;
4224 int hfa_size = GET_MODE_SIZE (hfa_mode);
4228 /* If prototyped, pass it in FR regs then GR regs.
4229 If not prototyped, pass it in both FR and GR regs.
4231 If this is an SFmode aggregate, then it is possible to run out of
4232 FR regs while GR regs are still left. In that case, we pass the
4233 remaining part in the GR regs. */
4235 /* Fill the FP regs. We do this always. We stop if we reach the end
4236 of the argument, the last FP register, or the last argument slot. */
4238 byte_size = ((mode == BLKmode)
4239 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4240 args_byte_size = int_regs * UNITS_PER_WORD;
4242 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
4243 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD));)
4246 args_byte_size += hfa_size;
4250 cum->fp_regs = fp_regs;
4253 /* Integral and aggregates go in general registers. So do TFmode FP values.
4254 If we have run out of FR registers, then other FP values must also go in
4255 general registers. This can happen when we have a SFmode HFA. */
4256 else if (mode == TFmode || mode == TCmode
4257 || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
4258 cum->int_regs = cum->words;
4260 /* If there is a prototype, then FP values go in a FR register when
4261 named, and in a GR register when unnamed. */
4262 else if (cum->prototype)
4265 cum->int_regs = cum->words;
4267 /* ??? Complex types should not reach here. */
4268 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
4270 /* If there is no prototype, then FP values go in both FR and GR
4274 /* ??? Complex types should not reach here. */
4275 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
4276 cum->int_regs = cum->words;
4280 /* Arguments with alignment larger than 8 bytes start at the next even
4281 boundary. On ILP32 HPUX, TFmode arguments start on next even boundary
4282 even though their normal alignment is 8 bytes. See ia64_function_arg. */
4285 ia64_function_arg_boundary (enum machine_mode mode, tree type)
4288 if (mode == TFmode && TARGET_HPUX && TARGET_ILP32)
4289 return PARM_BOUNDARY * 2;
4293 if (TYPE_ALIGN (type) > PARM_BOUNDARY)
4294 return PARM_BOUNDARY * 2;
4296 return PARM_BOUNDARY;
4299 if (GET_MODE_BITSIZE (mode) > PARM_BOUNDARY)
4300 return PARM_BOUNDARY * 2;
4302 return PARM_BOUNDARY;
4305 /* True if it is OK to do sibling call optimization for the specified
4306 call expression EXP. DECL will be the called function, or NULL if
4307 this is an indirect call. */
4309 ia64_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
4311 /* We can't perform a sibcall if the current function has the syscall_linkage
4313 if (lookup_attribute ("syscall_linkage",
4314 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
4317 /* We must always return with our current GP. This means we can
4318 only sibcall to functions defined in the current module. */
4319 return decl && (*targetm.binds_local_p) (decl);
4323 /* Implement va_arg. */
4326 ia64_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
4328 /* Variable sized types are passed by reference. */
4329 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
4331 tree ptrtype = build_pointer_type (type);
4332 tree addr = std_gimplify_va_arg_expr (valist, ptrtype, pre_p, post_p);
4333 return build_va_arg_indirect_ref (addr);
4336 /* Aggregate arguments with alignment larger than 8 bytes start at
4337 the next even boundary. Integer and floating point arguments
4338 do so if they are larger than 8 bytes, whether or not they are
4339 also aligned larger than 8 bytes. */
4340 if ((TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == INTEGER_TYPE)
4341 ? int_size_in_bytes (type) > 8 : TYPE_ALIGN (type) > 8 * BITS_PER_UNIT)
4343 tree t = build2 (PLUS_EXPR, TREE_TYPE (valist), valist,
4344 build_int_cst (NULL_TREE, 2 * UNITS_PER_WORD - 1));
4345 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
4346 build_int_cst (NULL_TREE, -2 * UNITS_PER_WORD));
4347 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (valist), valist, t);
4348 gimplify_and_add (t, pre_p);
4351 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4354 /* Return 1 if function return value returned in memory. Return 0 if it is
4358 ia64_return_in_memory (tree valtype, tree fntype ATTRIBUTE_UNUSED)
4360 enum machine_mode mode;
4361 enum machine_mode hfa_mode;
4362 HOST_WIDE_INT byte_size;
4364 mode = TYPE_MODE (valtype);
4365 byte_size = GET_MODE_SIZE (mode);
4366 if (mode == BLKmode)
4368 byte_size = int_size_in_bytes (valtype);
4373 /* Hfa's with up to 8 elements are returned in the FP argument registers. */
4375 hfa_mode = hfa_element_mode (valtype, 0);
4376 if (hfa_mode != VOIDmode)
4378 int hfa_size = GET_MODE_SIZE (hfa_mode);
4380 if (byte_size / hfa_size > MAX_ARGUMENT_SLOTS)
4385 else if (byte_size > UNITS_PER_WORD * MAX_INT_RETURN_SLOTS)
4391 /* Return rtx for register that holds the function return value. */
4394 ia64_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
4396 enum machine_mode mode;
4397 enum machine_mode hfa_mode;
4399 mode = TYPE_MODE (valtype);
4400 hfa_mode = hfa_element_mode (valtype, 0);
4402 if (hfa_mode != VOIDmode)
4410 hfa_size = GET_MODE_SIZE (hfa_mode);
4411 byte_size = ((mode == BLKmode)
4412 ? int_size_in_bytes (valtype) : GET_MODE_SIZE (mode));
4414 for (i = 0; offset < byte_size; i++)
4416 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4417 gen_rtx_REG (hfa_mode, FR_ARG_FIRST + i),
4421 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4423 else if (FLOAT_TYPE_P (valtype) && mode != TFmode && mode != TCmode)
4424 return gen_rtx_REG (mode, FR_ARG_FIRST);
4427 bool need_parallel = false;
4429 /* In big-endian mode, we need to manage the layout of aggregates
4430 in the registers so that we get the bits properly aligned in
4431 the highpart of the registers. */
4432 if (BYTES_BIG_ENDIAN
4433 && (mode == BLKmode || (valtype && AGGREGATE_TYPE_P (valtype))))
4434 need_parallel = true;
4436 /* Something like struct S { long double x; char a[0] } is not an
4437 HFA structure, and therefore doesn't go in fp registers. But
4438 the middle-end will give it XFmode anyway, and XFmode values
4439 don't normally fit in integer registers. So we need to smuggle
4440 the value inside a parallel. */
4441 else if (mode == XFmode || mode == XCmode || mode == RFmode)
4442 need_parallel = true;
4452 bytesize = int_size_in_bytes (valtype);
4453 /* An empty PARALLEL is invalid here, but the return value
4454 doesn't matter for empty structs. */
4456 return gen_rtx_REG (mode, GR_RET_FIRST);
4457 for (i = 0; offset < bytesize; i++)
4459 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4460 gen_rtx_REG (DImode,
4463 offset += UNITS_PER_WORD;
4465 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4468 return gen_rtx_REG (mode, GR_RET_FIRST);
4472 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4473 We need to emit DTP-relative relocations. */
4476 ia64_output_dwarf_dtprel (FILE *file, int size, rtx x)
4478 gcc_assert (size == 4 || size == 8);
4480 fputs ("\tdata4.ua\t@dtprel(", file);
4482 fputs ("\tdata8.ua\t@dtprel(", file);
4483 output_addr_const (file, x);
4487 /* Print a memory address as an operand to reference that memory location. */
4489 /* ??? Do we need this? It gets used only for 'a' operands. We could perhaps
4490 also call this from ia64_print_operand for memory addresses. */
4493 ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED,
4494 rtx address ATTRIBUTE_UNUSED)
4498 /* Print an operand to an assembler instruction.
4499 C Swap and print a comparison operator.
4500 D Print an FP comparison operator.
4501 E Print 32 - constant, for SImode shifts as extract.
4502 e Print 64 - constant, for DImode rotates.
4503 F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
4504 a floating point register emitted normally.
4505 I Invert a predicate register by adding 1.
4506 J Select the proper predicate register for a condition.
4507 j Select the inverse predicate register for a condition.
4508 O Append .acq for volatile load.
4509 P Postincrement of a MEM.
4510 Q Append .rel for volatile store.
4511 S Shift amount for shladd instruction.
4512 T Print an 8-bit sign extended number (K) as a 32-bit unsigned number
4513 for Intel assembler.
4514 U Print an 8-bit sign extended number (K) as a 64-bit unsigned number
4515 for Intel assembler.
4516 X A pair of floating point registers.
4517 r Print register name, or constant 0 as r0. HP compatibility for
4519 v Print vector constant value as an 8-byte integer value. */
4522 ia64_print_operand (FILE * file, rtx x, int code)
4529 /* Handled below. */
4534 enum rtx_code c = swap_condition (GET_CODE (x));
4535 fputs (GET_RTX_NAME (c), file);
4540 switch (GET_CODE (x))
4552 str = GET_RTX_NAME (GET_CODE (x));
4559 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - INTVAL (x));
4563 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - INTVAL (x));
4567 if (x == CONST0_RTX (GET_MODE (x)))
4568 str = reg_names [FR_REG (0)];
4569 else if (x == CONST1_RTX (GET_MODE (x)))
4570 str = reg_names [FR_REG (1)];
4573 gcc_assert (GET_CODE (x) == REG);
4574 str = reg_names [REGNO (x)];
4580 fputs (reg_names [REGNO (x) + 1], file);
4586 unsigned int regno = REGNO (XEXP (x, 0));
4587 if (GET_CODE (x) == EQ)
4591 fputs (reg_names [regno], file);
4596 if (MEM_VOLATILE_P (x))
4597 fputs(".acq", file);
4602 HOST_WIDE_INT value;
4604 switch (GET_CODE (XEXP (x, 0)))
4610 x = XEXP (XEXP (XEXP (x, 0), 1), 1);
4611 if (GET_CODE (x) == CONST_INT)
4615 gcc_assert (GET_CODE (x) == REG);
4616 fprintf (file, ", %s", reg_names[REGNO (x)]);
4622 value = GET_MODE_SIZE (GET_MODE (x));
4626 value = - (HOST_WIDE_INT) GET_MODE_SIZE (GET_MODE (x));
4630 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC, value);
4635 if (MEM_VOLATILE_P (x))
4636 fputs(".rel", file);
4640 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4644 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
4646 fprintf (file, "0x%x", (int) INTVAL (x) & 0xffffffff);
4652 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
4654 const char *prefix = "0x";
4655 if (INTVAL (x) & 0x80000000)
4657 fprintf (file, "0xffffffff");
4660 fprintf (file, "%s%x", prefix, (int) INTVAL (x) & 0xffffffff);
4667 unsigned int regno = REGNO (x);
4668 fprintf (file, "%s, %s", reg_names [regno], reg_names [regno + 1]);
4673 /* If this operand is the constant zero, write it as register zero.
4674 Any register, zero, or CONST_INT value is OK here. */
4675 if (GET_CODE (x) == REG)
4676 fputs (reg_names[REGNO (x)], file);
4677 else if (x == CONST0_RTX (GET_MODE (x)))
4679 else if (GET_CODE (x) == CONST_INT)
4680 output_addr_const (file, x);
4682 output_operand_lossage ("invalid %%r value");
4686 gcc_assert (GET_CODE (x) == CONST_VECTOR);
4687 x = simplify_subreg (DImode, x, GET_MODE (x), 0);
4694 /* For conditional branches, returns or calls, substitute
4695 sptk, dptk, dpnt, or spnt for %s. */
4696 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
4699 int pred_val = INTVAL (XEXP (x, 0));
4701 /* Guess top and bottom 10% statically predicted. */
4702 if (pred_val < REG_BR_PROB_BASE / 50
4703 && br_prob_note_reliable_p (x))
4705 else if (pred_val < REG_BR_PROB_BASE / 2)
4707 else if (pred_val < REG_BR_PROB_BASE / 100 * 98
4708 || !br_prob_note_reliable_p (x))
4713 else if (GET_CODE (current_output_insn) == CALL_INSN)
4718 fputs (which, file);
4723 x = current_insn_predicate;
4726 unsigned int regno = REGNO (XEXP (x, 0));
4727 if (GET_CODE (x) == EQ)
4729 fprintf (file, "(%s) ", reg_names [regno]);
4734 output_operand_lossage ("ia64_print_operand: unknown code");
4738 switch (GET_CODE (x))
4740 /* This happens for the spill/restore instructions. */
4745 /* ... fall through ... */
4748 fputs (reg_names [REGNO (x)], file);
4753 rtx addr = XEXP (x, 0);
4754 if (GET_RTX_CLASS (GET_CODE (addr)) == RTX_AUTOINC)
4755 addr = XEXP (addr, 0);
4756 fprintf (file, "[%s]", reg_names [REGNO (addr)]);
4761 output_addr_const (file, x);
4768 /* Compute a (partial) cost for rtx X. Return true if the complete
4769 cost has been computed, and false if subexpressions should be
4770 scanned. In either case, *TOTAL contains the cost result. */
4771 /* ??? This is incomplete. */
4774 ia64_rtx_costs (rtx x, int code, int outer_code, int *total)
4782 *total = CONST_OK_FOR_J (INTVAL (x)) ? 0 : COSTS_N_INSNS (1);
4785 if (CONST_OK_FOR_I (INTVAL (x)))
4787 else if (CONST_OK_FOR_J (INTVAL (x)))
4790 *total = COSTS_N_INSNS (1);
4793 if (CONST_OK_FOR_K (INTVAL (x)) || CONST_OK_FOR_L (INTVAL (x)))
4796 *total = COSTS_N_INSNS (1);
4801 *total = COSTS_N_INSNS (1);
4807 *total = COSTS_N_INSNS (3);
4811 /* For multiplies wider than HImode, we have to go to the FPU,
4812 which normally involves copies. Plus there's the latency
4813 of the multiply itself, and the latency of the instructions to
4814 transfer integer regs to FP regs. */
4815 /* ??? Check for FP mode. */
4816 if (GET_MODE_SIZE (GET_MODE (x)) > 2)
4817 *total = COSTS_N_INSNS (10);
4819 *total = COSTS_N_INSNS (2);
4827 *total = COSTS_N_INSNS (1);
4834 /* We make divide expensive, so that divide-by-constant will be
4835 optimized to a multiply. */
4836 *total = COSTS_N_INSNS (60);
4844 /* Calculate the cost of moving data from a register in class FROM to
4845 one in class TO, using MODE. */
4848 ia64_register_move_cost (enum machine_mode mode, enum reg_class from,
4851 /* ADDL_REGS is the same as GR_REGS for movement purposes. */
4852 if (to == ADDL_REGS)
4854 if (from == ADDL_REGS)
4857 /* All costs are symmetric, so reduce cases by putting the
4858 lower number class as the destination. */
4861 enum reg_class tmp = to;
4862 to = from, from = tmp;
4865 /* Moving from FR<->GR in XFmode must be more expensive than 2,
4866 so that we get secondary memory reloads. Between FR_REGS,
4867 we have to make this at least as expensive as MEMORY_MOVE_COST
4868 to avoid spectacularly poor register class preferencing. */
4869 if (mode == XFmode || mode == RFmode)
4871 if (to != GR_REGS || from != GR_REGS)
4872 return MEMORY_MOVE_COST (mode, to, 0);
4880 /* Moving between PR registers takes two insns. */
4881 if (from == PR_REGS)
4883 /* Moving between PR and anything but GR is impossible. */
4884 if (from != GR_REGS)
4885 return MEMORY_MOVE_COST (mode, to, 0);
4889 /* Moving between BR and anything but GR is impossible. */
4890 if (from != GR_REGS && from != GR_AND_BR_REGS)
4891 return MEMORY_MOVE_COST (mode, to, 0);
4896 /* Moving between AR and anything but GR is impossible. */
4897 if (from != GR_REGS)
4898 return MEMORY_MOVE_COST (mode, to, 0);
4904 case GR_AND_FR_REGS:
4905 case GR_AND_BR_REGS:
4916 /* Implement PREFERRED_RELOAD_CLASS. Place additional restrictions on CLASS
4917 to use when copying X into that class. */
4920 ia64_preferred_reload_class (rtx x, enum reg_class class)
4926 /* Don't allow volatile mem reloads into floating point registers.
4927 This is defined to force reload to choose the r/m case instead
4928 of the f/f case when reloading (set (reg fX) (mem/v)). */
4929 if (MEM_P (x) && MEM_VOLATILE_P (x))
4932 /* Force all unrecognized constants into the constant pool. */
4950 /* This function returns the register class required for a secondary
4951 register when copying between one of the registers in CLASS, and X,
4952 using MODE. A return value of NO_REGS means that no secondary register
4956 ia64_secondary_reload_class (enum reg_class class,
4957 enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
4961 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
4962 regno = true_regnum (x);
4969 /* ??? BR<->BR register copies can happen due to a bad gcse/cse/global
4970 interaction. We end up with two pseudos with overlapping lifetimes
4971 both of which are equiv to the same constant, and both which need
4972 to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end
4973 changes depending on the path length, which means the qty_first_reg
4974 check in make_regs_eqv can give different answers at different times.
4975 At some point I'll probably need a reload_indi pattern to handle
4978 We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we
4979 wound up with a FP register from GR_AND_FR_REGS. Extend that to all
4980 non-general registers for good measure. */
4981 if (regno >= 0 && ! GENERAL_REGNO_P (regno))
4984 /* This is needed if a pseudo used as a call_operand gets spilled to a
4986 if (GET_CODE (x) == MEM)
4992 /* Need to go through general registers to get to other class regs. */
4993 if (regno >= 0 && ! (FR_REGNO_P (regno) || GENERAL_REGNO_P (regno)))
4996 /* This can happen when a paradoxical subreg is an operand to the
4998 /* ??? This shouldn't be necessary after instruction scheduling is
4999 enabled, because paradoxical subregs are not accepted by
5000 register_operand when INSN_SCHEDULING is defined. Or alternatively,
5001 stop the paradoxical subreg stupidity in the *_operand functions
5003 if (GET_CODE (x) == MEM
5004 && (GET_MODE (x) == SImode || GET_MODE (x) == HImode
5005 || GET_MODE (x) == QImode))
5008 /* This can happen because of the ior/and/etc patterns that accept FP
5009 registers as operands. If the third operand is a constant, then it
5010 needs to be reloaded into a FP register. */
5011 if (GET_CODE (x) == CONST_INT)
5014 /* This can happen because of register elimination in a muldi3 insn.
5015 E.g. `26107 * (unsigned long)&u'. */
5016 if (GET_CODE (x) == PLUS)
5021 /* ??? This happens if we cse/gcse a BImode value across a call,
5022 and the function has a nonlocal goto. This is because global
5023 does not allocate call crossing pseudos to hard registers when
5024 current_function_has_nonlocal_goto is true. This is relatively
5025 common for C++ programs that use exceptions. To reproduce,
5026 return NO_REGS and compile libstdc++. */
5027 if (GET_CODE (x) == MEM)
5030 /* This can happen when we take a BImode subreg of a DImode value,
5031 and that DImode value winds up in some non-GR register. */
5032 if (regno >= 0 && ! GENERAL_REGNO_P (regno) && ! PR_REGNO_P (regno))
5044 /* Parse the -mfixed-range= option string. */
5047 fix_range (const char *const_str)
5050 char *str, *dash, *comma;
5052 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
5053 REG2 are either register names or register numbers. The effect
5054 of this option is to mark the registers in the range from REG1 to
5055 REG2 as ``fixed'' so they won't be used by the compiler. This is
5056 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
5058 i = strlen (const_str);
5059 str = (char *) alloca (i + 1);
5060 memcpy (str, const_str, i + 1);
5064 dash = strchr (str, '-');
5067 warning (0, "value of -mfixed-range must have form REG1-REG2");
5072 comma = strchr (dash + 1, ',');
5076 first = decode_reg_name (str);
5079 warning (0, "unknown register name: %s", str);
5083 last = decode_reg_name (dash + 1);
5086 warning (0, "unknown register name: %s", dash + 1);
5094 warning (0, "%s-%s is an empty range", str, dash + 1);
5098 for (i = first; i <= last; ++i)
5099 fixed_regs[i] = call_used_regs[i] = 1;
5109 /* Implement TARGET_HANDLE_OPTION. */
5112 ia64_handle_option (size_t code, const char *arg, int value)
5116 case OPT_mfixed_range_:
5120 case OPT_mtls_size_:
5121 if (value != 14 && value != 22 && value != 64)
5122 error ("bad value %<%s%> for -mtls-size= switch", arg);
5129 const char *name; /* processor name or nickname. */
5130 enum processor_type processor;
5132 const processor_alias_table[] =
5134 {"itanium", PROCESSOR_ITANIUM},
5135 {"itanium1", PROCESSOR_ITANIUM},
5136 {"merced", PROCESSOR_ITANIUM},
5137 {"itanium2", PROCESSOR_ITANIUM2},
5138 {"mckinley", PROCESSOR_ITANIUM2},
5140 int const pta_size = ARRAY_SIZE (processor_alias_table);
5143 for (i = 0; i < pta_size; i++)
5144 if (!strcmp (arg, processor_alias_table[i].name))
5146 ia64_tune = processor_alias_table[i].processor;
5150 error ("bad value %<%s%> for -mtune= switch", arg);
5159 /* Implement OVERRIDE_OPTIONS. */
5162 ia64_override_options (void)
5164 if (TARGET_AUTO_PIC)
5165 target_flags |= MASK_CONST_GP;
5167 if (TARGET_INLINE_SQRT == INL_MIN_LAT)
5169 warning (0, "not yet implemented: latency-optimized inline square root");
5170 TARGET_INLINE_SQRT = INL_MAX_THR;
5173 ia64_flag_schedule_insns2 = flag_schedule_insns_after_reload;
5174 flag_schedule_insns_after_reload = 0;
5176 ia64_section_threshold = g_switch_set ? g_switch_value : IA64_DEFAULT_GVALUE;
5178 init_machine_status = ia64_init_machine_status;
5181 static struct machine_function *
5182 ia64_init_machine_status (void)
5184 return ggc_alloc_cleared (sizeof (struct machine_function));
5187 static enum attr_itanium_class ia64_safe_itanium_class (rtx);
5188 static enum attr_type ia64_safe_type (rtx);
5190 static enum attr_itanium_class
5191 ia64_safe_itanium_class (rtx insn)
5193 if (recog_memoized (insn) >= 0)
5194 return get_attr_itanium_class (insn);
5196 return ITANIUM_CLASS_UNKNOWN;
5199 static enum attr_type
5200 ia64_safe_type (rtx insn)
5202 if (recog_memoized (insn) >= 0)
5203 return get_attr_type (insn);
5205 return TYPE_UNKNOWN;
5208 /* The following collection of routines emit instruction group stop bits as
5209 necessary to avoid dependencies. */
5211 /* Need to track some additional registers as far as serialization is
5212 concerned so we can properly handle br.call and br.ret. We could
5213 make these registers visible to gcc, but since these registers are
5214 never explicitly used in gcc generated code, it seems wasteful to
5215 do so (plus it would make the call and return patterns needlessly
5217 #define REG_RP (BR_REG (0))
5218 #define REG_AR_CFM (FIRST_PSEUDO_REGISTER + 1)
5219 /* This is used for volatile asms which may require a stop bit immediately
5220 before and after them. */
5221 #define REG_VOLATILE (FIRST_PSEUDO_REGISTER + 2)
5222 #define AR_UNAT_BIT_0 (FIRST_PSEUDO_REGISTER + 3)
5223 #define NUM_REGS (AR_UNAT_BIT_0 + 64)
5225 /* For each register, we keep track of how it has been written in the
5226 current instruction group.
5228 If a register is written unconditionally (no qualifying predicate),
5229 WRITE_COUNT is set to 2 and FIRST_PRED is ignored.
5231 If a register is written if its qualifying predicate P is true, we
5232 set WRITE_COUNT to 1 and FIRST_PRED to P. Later on, the same register
5233 may be written again by the complement of P (P^1) and when this happens,
5234 WRITE_COUNT gets set to 2.
5236 The result of this is that whenever an insn attempts to write a register
5237 whose WRITE_COUNT is two, we need to issue an insn group barrier first.
5239 If a predicate register is written by a floating-point insn, we set
5240 WRITTEN_BY_FP to true.
5242 If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND
5243 to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true. */
5245 struct reg_write_state
5247 unsigned int write_count : 2;
5248 unsigned int first_pred : 16;
5249 unsigned int written_by_fp : 1;
5250 unsigned int written_by_and : 1;
5251 unsigned int written_by_or : 1;
5254 /* Cumulative info for the current instruction group. */
5255 struct reg_write_state rws_sum[NUM_REGS];
5256 /* Info for the current instruction. This gets copied to rws_sum after a
5257 stop bit is emitted. */
5258 struct reg_write_state rws_insn[NUM_REGS];
5260 /* Indicates whether this is the first instruction after a stop bit,
5261 in which case we don't need another stop bit. Without this,
5262 ia64_variable_issue will die when scheduling an alloc. */
5263 static int first_instruction;
5265 /* Misc flags needed to compute RAW/WAW dependencies while we are traversing
5266 RTL for one instruction. */
5269 unsigned int is_write : 1; /* Is register being written? */
5270 unsigned int is_fp : 1; /* Is register used as part of an fp op? */
5271 unsigned int is_branch : 1; /* Is register used as part of a branch? */
5272 unsigned int is_and : 1; /* Is register used as part of and.orcm? */
5273 unsigned int is_or : 1; /* Is register used as part of or.andcm? */
5274 unsigned int is_sibcall : 1; /* Is this a sibling or normal call? */
5277 static void rws_update (struct reg_write_state *, int, struct reg_flags, int);
5278 static int rws_access_regno (int, struct reg_flags, int);
5279 static int rws_access_reg (rtx, struct reg_flags, int);
5280 static void update_set_flags (rtx, struct reg_flags *);
5281 static int set_src_needs_barrier (rtx, struct reg_flags, int);
5282 static int rtx_needs_barrier (rtx, struct reg_flags, int);
5283 static void init_insn_group_barriers (void);
5284 static int group_barrier_needed (rtx);
5285 static int safe_group_barrier_needed (rtx);
5287 /* Update *RWS for REGNO, which is being written by the current instruction,
5288 with predicate PRED, and associated register flags in FLAGS. */
5291 rws_update (struct reg_write_state *rws, int regno, struct reg_flags flags, int pred)
5294 rws[regno].write_count++;
5296 rws[regno].write_count = 2;
5297 rws[regno].written_by_fp |= flags.is_fp;
5298 /* ??? Not tracking and/or across differing predicates. */
5299 rws[regno].written_by_and = flags.is_and;
5300 rws[regno].written_by_or = flags.is_or;
5301 rws[regno].first_pred = pred;
5304 /* Handle an access to register REGNO of type FLAGS using predicate register
5305 PRED. Update rws_insn and rws_sum arrays. Return 1 if this access creates
5306 a dependency with an earlier instruction in the same group. */
5309 rws_access_regno (int regno, struct reg_flags flags, int pred)
5311 int need_barrier = 0;
5313 gcc_assert (regno < NUM_REGS);
5315 if (! PR_REGNO_P (regno))
5316 flags.is_and = flags.is_or = 0;
5322 /* One insn writes same reg multiple times? */
5323 gcc_assert (!rws_insn[regno].write_count);
5325 /* Update info for current instruction. */
5326 rws_update (rws_insn, regno, flags, pred);
5327 write_count = rws_sum[regno].write_count;
5329 switch (write_count)
5332 /* The register has not been written yet. */
5333 rws_update (rws_sum, regno, flags, pred);
5337 /* The register has been written via a predicate. If this is
5338 not a complementary predicate, then we need a barrier. */
5339 /* ??? This assumes that P and P+1 are always complementary
5340 predicates for P even. */
5341 if (flags.is_and && rws_sum[regno].written_by_and)
5343 else if (flags.is_or && rws_sum[regno].written_by_or)
5345 else if ((rws_sum[regno].first_pred ^ 1) != pred)
5347 rws_update (rws_sum, regno, flags, pred);
5351 /* The register has been unconditionally written already. We
5353 if (flags.is_and && rws_sum[regno].written_by_and)
5355 else if (flags.is_or && rws_sum[regno].written_by_or)
5359 rws_sum[regno].written_by_and = flags.is_and;
5360 rws_sum[regno].written_by_or = flags.is_or;
5369 if (flags.is_branch)
5371 /* Branches have several RAW exceptions that allow to avoid
5374 if (REGNO_REG_CLASS (regno) == BR_REGS || regno == AR_PFS_REGNUM)
5375 /* RAW dependencies on branch regs are permissible as long
5376 as the writer is a non-branch instruction. Since we
5377 never generate code that uses a branch register written
5378 by a branch instruction, handling this case is
5382 if (REGNO_REG_CLASS (regno) == PR_REGS
5383 && ! rws_sum[regno].written_by_fp)
5384 /* The predicates of a branch are available within the
5385 same insn group as long as the predicate was written by
5386 something other than a floating-point instruction. */
5390 if (flags.is_and && rws_sum[regno].written_by_and)
5392 if (flags.is_or && rws_sum[regno].written_by_or)
5395 switch (rws_sum[regno].write_count)
5398 /* The register has not been written yet. */
5402 /* The register has been written via a predicate. If this is
5403 not a complementary predicate, then we need a barrier. */
5404 /* ??? This assumes that P and P+1 are always complementary
5405 predicates for P even. */
5406 if ((rws_sum[regno].first_pred ^ 1) != pred)
5411 /* The register has been unconditionally written already. We
5421 return need_barrier;
5425 rws_access_reg (rtx reg, struct reg_flags flags, int pred)
5427 int regno = REGNO (reg);
5428 int n = HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg));
5431 return rws_access_regno (regno, flags, pred);
5434 int need_barrier = 0;
5436 need_barrier |= rws_access_regno (regno + n, flags, pred);
5437 return need_barrier;
5441 /* Examine X, which is a SET rtx, and update the flags, the predicate, and
5442 the condition, stored in *PFLAGS, *PPRED and *PCOND. */
5445 update_set_flags (rtx x, struct reg_flags *pflags)
5447 rtx src = SET_SRC (x);
5449 switch (GET_CODE (src))
5455 /* There are four cases here:
5456 (1) The destination is (pc), in which case this is a branch,
5457 nothing here applies.
5458 (2) The destination is ar.lc, in which case this is a
5459 doloop_end_internal,
5460 (3) The destination is an fp register, in which case this is
5461 an fselect instruction.
5462 (4) The condition has (unspec [(reg)] UNSPEC_LDC), in which case
5463 this is a check load.
5464 In all cases, nothing we do in this function applies. */
5468 if (COMPARISON_P (src)
5469 && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (src, 0))))
5470 /* Set pflags->is_fp to 1 so that we know we're dealing
5471 with a floating point comparison when processing the
5472 destination of the SET. */
5475 /* Discover if this is a parallel comparison. We only handle
5476 and.orcm and or.andcm at present, since we must retain a
5477 strict inverse on the predicate pair. */
5478 else if (GET_CODE (src) == AND)
5480 else if (GET_CODE (src) == IOR)
5487 /* Subroutine of rtx_needs_barrier; this function determines whether the
5488 source of a given SET rtx found in X needs a barrier. FLAGS and PRED
5489 are as in rtx_needs_barrier. COND is an rtx that holds the condition
5493 set_src_needs_barrier (rtx x, struct reg_flags flags, int pred)
5495 int need_barrier = 0;
5497 rtx src = SET_SRC (x);
5499 if (GET_CODE (src) == CALL)
5500 /* We don't need to worry about the result registers that
5501 get written by subroutine call. */
5502 return rtx_needs_barrier (src, flags, pred);
5503 else if (SET_DEST (x) == pc_rtx)
5505 /* X is a conditional branch. */
5506 /* ??? This seems redundant, as the caller sets this bit for
5508 if (!ia64_spec_check_src_p (src))
5509 flags.is_branch = 1;
5510 return rtx_needs_barrier (src, flags, pred);
5513 if (ia64_spec_check_src_p (src))
5514 /* Avoid checking one register twice (in condition
5515 and in 'then' section) for ldc pattern. */
5517 gcc_assert (REG_P (XEXP (src, 2)));
5518 need_barrier = rtx_needs_barrier (XEXP (src, 2), flags, pred);
5520 /* We process MEM below. */
5521 src = XEXP (src, 1);
5524 need_barrier |= rtx_needs_barrier (src, flags, pred);
5527 if (GET_CODE (dst) == ZERO_EXTRACT)
5529 need_barrier |= rtx_needs_barrier (XEXP (dst, 1), flags, pred);
5530 need_barrier |= rtx_needs_barrier (XEXP (dst, 2), flags, pred);
5532 return need_barrier;
5535 /* Handle an access to rtx X of type FLAGS using predicate register
5536 PRED. Return 1 if this access creates a dependency with an earlier
5537 instruction in the same group. */
5540 rtx_needs_barrier (rtx x, struct reg_flags flags, int pred)
5543 int is_complemented = 0;
5544 int need_barrier = 0;
5545 const char *format_ptr;
5546 struct reg_flags new_flags;
5554 switch (GET_CODE (x))
5557 update_set_flags (x, &new_flags);
5558 need_barrier = set_src_needs_barrier (x, new_flags, pred);
5559 if (GET_CODE (SET_SRC (x)) != CALL)
5561 new_flags.is_write = 1;
5562 need_barrier |= rtx_needs_barrier (SET_DEST (x), new_flags, pred);
5567 new_flags.is_write = 0;
5568 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
5570 /* Avoid multiple register writes, in case this is a pattern with
5571 multiple CALL rtx. This avoids a failure in rws_access_reg. */
5572 if (! flags.is_sibcall && ! rws_insn[REG_AR_CFM].write_count)
5574 new_flags.is_write = 1;
5575 need_barrier |= rws_access_regno (REG_RP, new_flags, pred);
5576 need_barrier |= rws_access_regno (AR_PFS_REGNUM, new_flags, pred);
5577 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
5582 /* X is a predicated instruction. */
5584 cond = COND_EXEC_TEST (x);
5586 need_barrier = rtx_needs_barrier (cond, flags, 0);
5588 if (GET_CODE (cond) == EQ)
5589 is_complemented = 1;
5590 cond = XEXP (cond, 0);
5591 gcc_assert (GET_CODE (cond) == REG
5592 && REGNO_REG_CLASS (REGNO (cond)) == PR_REGS);
5593 pred = REGNO (cond);
5594 if (is_complemented)
5597 need_barrier |= rtx_needs_barrier (COND_EXEC_CODE (x), flags, pred);
5598 return need_barrier;
5602 /* Clobber & use are for earlier compiler-phases only. */
5607 /* We always emit stop bits for traditional asms. We emit stop bits
5608 for volatile extended asms if TARGET_VOL_ASM_STOP is true. */
5609 if (GET_CODE (x) != ASM_OPERANDS
5610 || (MEM_VOLATILE_P (x) && TARGET_VOL_ASM_STOP))
5612 /* Avoid writing the register multiple times if we have multiple
5613 asm outputs. This avoids a failure in rws_access_reg. */
5614 if (! rws_insn[REG_VOLATILE].write_count)
5616 new_flags.is_write = 1;
5617 rws_access_regno (REG_VOLATILE, new_flags, pred);
5622 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
5623 We cannot just fall through here since then we would be confused
5624 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
5625 traditional asms unlike their normal usage. */
5627 for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; --i)
5628 if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x, i), flags, pred))
5633 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
5635 rtx pat = XVECEXP (x, 0, i);
5636 switch (GET_CODE (pat))
5639 update_set_flags (pat, &new_flags);
5640 need_barrier |= set_src_needs_barrier (pat, new_flags, pred);
5646 need_barrier |= rtx_needs_barrier (pat, flags, pred);
5657 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
5659 rtx pat = XVECEXP (x, 0, i);
5660 if (GET_CODE (pat) == SET)
5662 if (GET_CODE (SET_SRC (pat)) != CALL)
5664 new_flags.is_write = 1;
5665 need_barrier |= rtx_needs_barrier (SET_DEST (pat), new_flags,
5669 else if (GET_CODE (pat) == CLOBBER || GET_CODE (pat) == RETURN)
5670 need_barrier |= rtx_needs_barrier (pat, flags, pred);
5675 need_barrier |= rtx_needs_barrier (SUBREG_REG (x), flags, pred);
5678 if (REGNO (x) == AR_UNAT_REGNUM)
5680 for (i = 0; i < 64; ++i)
5681 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + i, flags, pred);
5684 need_barrier = rws_access_reg (x, flags, pred);
5688 /* Find the regs used in memory address computation. */
5689 new_flags.is_write = 0;
5690 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
5693 case CONST_INT: case CONST_DOUBLE: case CONST_VECTOR:
5694 case SYMBOL_REF: case LABEL_REF: case CONST:
5697 /* Operators with side-effects. */
5698 case POST_INC: case POST_DEC:
5699 gcc_assert (GET_CODE (XEXP (x, 0)) == REG);
5701 new_flags.is_write = 0;
5702 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
5703 new_flags.is_write = 1;
5704 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
5708 gcc_assert (GET_CODE (XEXP (x, 0)) == REG);
5710 new_flags.is_write = 0;
5711 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
5712 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
5713 new_flags.is_write = 1;
5714 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
5717 /* Handle common unary and binary ops for efficiency. */
5718 case COMPARE: case PLUS: case MINUS: case MULT: case DIV:
5719 case MOD: case UDIV: case UMOD: case AND: case IOR:
5720 case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT:
5721 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
5722 case NE: case EQ: case GE: case GT: case LE:
5723 case LT: case GEU: case GTU: case LEU: case LTU:
5724 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
5725 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
5728 case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND:
5729 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT:
5730 case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS:
5731 case SQRT: case FFS: case POPCOUNT:
5732 need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred);
5736 /* VEC_SELECT's second argument is a PARALLEL with integers that
5737 describe the elements selected. On ia64, those integers are
5738 always constants. Avoid walking the PARALLEL so that we don't
5739 get confused with "normal" parallels and then die. */
5740 need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred);
5744 switch (XINT (x, 1))
5746 case UNSPEC_LTOFF_DTPMOD:
5747 case UNSPEC_LTOFF_DTPREL:
5749 case UNSPEC_LTOFF_TPREL:
5751 case UNSPEC_PRED_REL_MUTEX:
5752 case UNSPEC_PIC_CALL:
5754 case UNSPEC_FETCHADD_ACQ:
5755 case UNSPEC_BSP_VALUE:
5756 case UNSPEC_FLUSHRS:
5757 case UNSPEC_BUNDLE_SELECTOR:
5760 case UNSPEC_GR_SPILL:
5761 case UNSPEC_GR_RESTORE:
5763 HOST_WIDE_INT offset = INTVAL (XVECEXP (x, 0, 1));
5764 HOST_WIDE_INT bit = (offset >> 3) & 63;
5766 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
5767 new_flags.is_write = (XINT (x, 1) == UNSPEC_GR_SPILL);
5768 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + bit,
5773 case UNSPEC_FR_SPILL:
5774 case UNSPEC_FR_RESTORE:
5775 case UNSPEC_GETF_EXP:
5776 case UNSPEC_SETF_EXP:
5778 case UNSPEC_FR_SQRT_RECIP_APPROX:
5782 case UNSPEC_CHKACLR:
5784 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
5787 case UNSPEC_FR_RECIP_APPROX:
5789 case UNSPEC_COPYSIGN:
5790 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
5791 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
5794 case UNSPEC_CMPXCHG_ACQ:
5795 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
5796 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 2), flags, pred);
5804 case UNSPEC_VOLATILE:
5805 switch (XINT (x, 1))
5808 /* Alloc must always be the first instruction of a group.
5809 We force this by always returning true. */
5810 /* ??? We might get better scheduling if we explicitly check for
5811 input/local/output register dependencies, and modify the
5812 scheduler so that alloc is always reordered to the start of
5813 the current group. We could then eliminate all of the
5814 first_instruction code. */
5815 rws_access_regno (AR_PFS_REGNUM, flags, pred);
5817 new_flags.is_write = 1;
5818 rws_access_regno (REG_AR_CFM, new_flags, pred);
5821 case UNSPECV_SET_BSP:
5825 case UNSPECV_BLOCKAGE:
5826 case UNSPECV_INSN_GROUP_BARRIER:
5828 case UNSPECV_PSAC_ALL:
5829 case UNSPECV_PSAC_NORMAL:
5838 new_flags.is_write = 0;
5839 need_barrier = rws_access_regno (REG_RP, flags, pred);
5840 need_barrier |= rws_access_regno (AR_PFS_REGNUM, flags, pred);
5842 new_flags.is_write = 1;
5843 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
5844 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
5848 format_ptr = GET_RTX_FORMAT (GET_CODE (x));
5849 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5850 switch (format_ptr[i])
5852 case '0': /* unused field */
5853 case 'i': /* integer */
5854 case 'n': /* note */
5855 case 'w': /* wide integer */
5856 case 's': /* pointer to string */
5857 case 'S': /* optional pointer to string */
5861 if (rtx_needs_barrier (XEXP (x, i), flags, pred))
5866 for (j = XVECLEN (x, i) - 1; j >= 0; --j)
5867 if (rtx_needs_barrier (XVECEXP (x, i, j), flags, pred))
5876 return need_barrier;
5879 /* Clear out the state for group_barrier_needed at the start of a
5880 sequence of insns. */
5883 init_insn_group_barriers (void)
5885 memset (rws_sum, 0, sizeof (rws_sum));
5886 first_instruction = 1;
5889 /* Given the current state, determine whether a group barrier (a stop bit) is
5890 necessary before INSN. Return nonzero if so. This modifies the state to
5891 include the effects of INSN as a side-effect. */
5894 group_barrier_needed (rtx insn)
5897 int need_barrier = 0;
5898 struct reg_flags flags;
5900 memset (&flags, 0, sizeof (flags));
5901 switch (GET_CODE (insn))
5907 /* A barrier doesn't imply an instruction group boundary. */
5911 memset (rws_insn, 0, sizeof (rws_insn));
5915 flags.is_branch = 1;
5916 flags.is_sibcall = SIBLING_CALL_P (insn);
5917 memset (rws_insn, 0, sizeof (rws_insn));
5919 /* Don't bundle a call following another call. */
5920 if ((pat = prev_active_insn (insn))
5921 && GET_CODE (pat) == CALL_INSN)
5927 need_barrier = rtx_needs_barrier (PATTERN (insn), flags, 0);
5931 if (!ia64_spec_check_p (insn))
5932 flags.is_branch = 1;
5934 /* Don't bundle a jump following a call. */
5935 if ((pat = prev_active_insn (insn))
5936 && GET_CODE (pat) == CALL_INSN)
5944 if (GET_CODE (PATTERN (insn)) == USE
5945 || GET_CODE (PATTERN (insn)) == CLOBBER)
5946 /* Don't care about USE and CLOBBER "insns"---those are used to
5947 indicate to the optimizer that it shouldn't get rid of
5948 certain operations. */
5951 pat = PATTERN (insn);
5953 /* Ug. Hack hacks hacked elsewhere. */
5954 switch (recog_memoized (insn))
5956 /* We play dependency tricks with the epilogue in order
5957 to get proper schedules. Undo this for dv analysis. */
5958 case CODE_FOR_epilogue_deallocate_stack:
5959 case CODE_FOR_prologue_allocate_stack:
5960 pat = XVECEXP (pat, 0, 0);
5963 /* The pattern we use for br.cloop confuses the code above.
5964 The second element of the vector is representative. */
5965 case CODE_FOR_doloop_end_internal:
5966 pat = XVECEXP (pat, 0, 1);
5969 /* Doesn't generate code. */
5970 case CODE_FOR_pred_rel_mutex:
5971 case CODE_FOR_prologue_use:
5978 memset (rws_insn, 0, sizeof (rws_insn));
5979 need_barrier = rtx_needs_barrier (pat, flags, 0);
5981 /* Check to see if the previous instruction was a volatile
5984 need_barrier = rws_access_regno (REG_VOLATILE, flags, 0);
5991 if (first_instruction && INSN_P (insn)
5992 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
5993 && GET_CODE (PATTERN (insn)) != USE
5994 && GET_CODE (PATTERN (insn)) != CLOBBER)
5997 first_instruction = 0;
6000 return need_barrier;
6003 /* Like group_barrier_needed, but do not clobber the current state. */
6006 safe_group_barrier_needed (rtx insn)
6008 struct reg_write_state rws_saved[NUM_REGS];
6009 int saved_first_instruction;
6012 memcpy (rws_saved, rws_sum, NUM_REGS * sizeof *rws_saved);
6013 saved_first_instruction = first_instruction;
6015 t = group_barrier_needed (insn);
6017 memcpy (rws_sum, rws_saved, NUM_REGS * sizeof *rws_saved);
6018 first_instruction = saved_first_instruction;
6023 /* Scan the current function and insert stop bits as necessary to
6024 eliminate dependencies. This function assumes that a final
6025 instruction scheduling pass has been run which has already
6026 inserted most of the necessary stop bits. This function only
6027 inserts new ones at basic block boundaries, since these are
6028 invisible to the scheduler. */
6031 emit_insn_group_barriers (FILE *dump)
6035 int insns_since_last_label = 0;
6037 init_insn_group_barriers ();
6039 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6041 if (GET_CODE (insn) == CODE_LABEL)
6043 if (insns_since_last_label)
6045 insns_since_last_label = 0;
6047 else if (GET_CODE (insn) == NOTE
6048 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_BASIC_BLOCK)
6050 if (insns_since_last_label)
6052 insns_since_last_label = 0;
6054 else if (GET_CODE (insn) == INSN
6055 && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
6056 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
6058 init_insn_group_barriers ();
6061 else if (INSN_P (insn))
6063 insns_since_last_label = 1;
6065 if (group_barrier_needed (insn))
6070 fprintf (dump, "Emitting stop before label %d\n",
6071 INSN_UID (last_label));
6072 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), last_label);
6075 init_insn_group_barriers ();
6083 /* Like emit_insn_group_barriers, but run if no final scheduling pass was run.
6084 This function has to emit all necessary group barriers. */
6087 emit_all_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED)
6091 init_insn_group_barriers ();
6093 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6095 if (GET_CODE (insn) == BARRIER)
6097 rtx last = prev_active_insn (insn);
6101 if (GET_CODE (last) == JUMP_INSN
6102 && GET_CODE (PATTERN (last)) == ADDR_DIFF_VEC)
6103 last = prev_active_insn (last);
6104 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
6105 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
6107 init_insn_group_barriers ();
6109 else if (INSN_P (insn))
6111 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
6112 init_insn_group_barriers ();
6113 else if (group_barrier_needed (insn))
6115 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn);
6116 init_insn_group_barriers ();
6117 group_barrier_needed (insn);
6125 /* Instruction scheduling support. */
6127 #define NR_BUNDLES 10
6129 /* A list of names of all available bundles. */
6131 static const char *bundle_name [NR_BUNDLES] =
6137 #if NR_BUNDLES == 10
6147 /* Nonzero if we should insert stop bits into the schedule. */
6149 int ia64_final_schedule = 0;
6151 /* Codes of the corresponding queried units: */
6153 static int _0mii_, _0mmi_, _0mfi_, _0mmf_;
6154 static int _0bbb_, _0mbb_, _0mib_, _0mmb_, _0mfb_, _0mlx_;
6156 static int _1mii_, _1mmi_, _1mfi_, _1mmf_;
6157 static int _1bbb_, _1mbb_, _1mib_, _1mmb_, _1mfb_, _1mlx_;
6159 static int pos_1, pos_2, pos_3, pos_4, pos_5, pos_6;
6161 /* The following variable value is an insn group barrier. */
6163 static rtx dfa_stop_insn;
6165 /* The following variable value is the last issued insn. */
6167 static rtx last_scheduled_insn;
6169 /* The following variable value is size of the DFA state. */
6171 static size_t dfa_state_size;
6173 /* The following variable value is pointer to a DFA state used as
6174 temporary variable. */
6176 static state_t temp_dfa_state = NULL;
6178 /* The following variable value is DFA state after issuing the last
6181 static state_t prev_cycle_state = NULL;
6183 /* The following array element values are TRUE if the corresponding
6184 insn requires to add stop bits before it. */
6186 static char *stops_p = NULL;
6188 /* The following array element values are ZERO for non-speculative
6189 instructions and hold corresponding speculation check number for
6190 speculative instructions. */
6191 static int *spec_check_no = NULL;
6193 /* Size of spec_check_no array. */
6194 static int max_uid = 0;
6196 /* The following variable is used to set up the mentioned above array. */
6198 static int stop_before_p = 0;
6200 /* The following variable value is length of the arrays `clocks' and
6203 static int clocks_length;
6205 /* The following array element values are cycles on which the
6206 corresponding insn will be issued. The array is used only for
6211 /* The following array element values are numbers of cycles should be
6212 added to improve insn scheduling for MM_insns for Itanium1. */
6214 static int *add_cycles;
6216 /* The following variable value is number of data speculations in progress. */
6217 static int pending_data_specs = 0;
6219 static rtx ia64_single_set (rtx);
6220 static void ia64_emit_insn_before (rtx, rtx);
6222 /* Map a bundle number to its pseudo-op. */
6225 get_bundle_name (int b)
6227 return bundle_name[b];
6231 /* Return the maximum number of instructions a cpu can issue. */
6234 ia64_issue_rate (void)
6239 /* Helper function - like single_set, but look inside COND_EXEC. */
6242 ia64_single_set (rtx insn)
6244 rtx x = PATTERN (insn), ret;
6245 if (GET_CODE (x) == COND_EXEC)
6246 x = COND_EXEC_CODE (x);
6247 if (GET_CODE (x) == SET)
6250 /* Special case here prologue_allocate_stack and epilogue_deallocate_stack.
6251 Although they are not classical single set, the second set is there just
6252 to protect it from moving past FP-relative stack accesses. */
6253 switch (recog_memoized (insn))
6255 case CODE_FOR_prologue_allocate_stack:
6256 case CODE_FOR_epilogue_deallocate_stack:
6257 ret = XVECEXP (x, 0, 0);
6261 ret = single_set_2 (insn, x);
6268 /* Adjust the cost of a scheduling dependency.
6269 Return the new cost of a dependency of type DEP_TYPE or INSN on DEP_INSN.
6270 COST is the current cost. */
6273 ia64_adjust_cost_2 (rtx insn, int dep_type1, rtx dep_insn, int cost)
6275 enum reg_note dep_type = (enum reg_note) dep_type1;
6276 enum attr_itanium_class dep_class;
6277 enum attr_itanium_class insn_class;
6279 if (dep_type != REG_DEP_OUTPUT)
6282 insn_class = ia64_safe_itanium_class (insn);
6283 dep_class = ia64_safe_itanium_class (dep_insn);
6284 if (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF
6285 || insn_class == ITANIUM_CLASS_ST || insn_class == ITANIUM_CLASS_STF)
6291 /* Like emit_insn_before, but skip cycle_display notes.
6292 ??? When cycle display notes are implemented, update this. */
6295 ia64_emit_insn_before (rtx insn, rtx before)
6297 emit_insn_before (insn, before);
6300 /* The following function marks insns who produce addresses for load
6301 and store insns. Such insns will be placed into M slots because it
6302 decrease latency time for Itanium1 (see function
6303 `ia64_produce_address_p' and the DFA descriptions). */
6306 ia64_dependencies_evaluation_hook (rtx head, rtx tail)
6308 rtx insn, link, next, next_tail;
6310 /* Before reload, which_alternative is not set, which means that
6311 ia64_safe_itanium_class will produce wrong results for (at least)
6312 move instructions. */
6313 if (!reload_completed)
6316 next_tail = NEXT_INSN (tail);
6317 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
6320 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
6322 && ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IALU)
6324 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
6326 enum attr_itanium_class c;
6328 if (REG_NOTE_KIND (link) != REG_DEP_TRUE)
6330 next = XEXP (link, 0);
6331 c = ia64_safe_itanium_class (next);
6332 if ((c == ITANIUM_CLASS_ST
6333 || c == ITANIUM_CLASS_STF)
6334 && ia64_st_address_bypass_p (insn, next))
6336 else if ((c == ITANIUM_CLASS_LD
6337 || c == ITANIUM_CLASS_FLD
6338 || c == ITANIUM_CLASS_FLDP)
6339 && ia64_ld_address_bypass_p (insn, next))
6342 insn->call = link != 0;
6346 /* We're beginning a new block. Initialize data structures as necessary. */
6349 ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED,
6350 int sched_verbose ATTRIBUTE_UNUSED,
6351 int max_ready ATTRIBUTE_UNUSED)
6353 #ifdef ENABLE_CHECKING
6356 if (reload_completed)
6357 for (insn = NEXT_INSN (current_sched_info->prev_head);
6358 insn != current_sched_info->next_tail;
6359 insn = NEXT_INSN (insn))
6360 gcc_assert (!SCHED_GROUP_P (insn));
6362 last_scheduled_insn = NULL_RTX;
6363 init_insn_group_barriers ();
6366 /* We're beginning a scheduling pass. Check assertion. */
6369 ia64_sched_init_global (FILE *dump ATTRIBUTE_UNUSED,
6370 int sched_verbose ATTRIBUTE_UNUSED,
6371 int max_ready ATTRIBUTE_UNUSED)
6373 gcc_assert (!pending_data_specs);
6376 /* Scheduling pass is now finished. Free/reset static variable. */
6378 ia64_sched_finish_global (FILE *dump ATTRIBUTE_UNUSED,
6379 int sched_verbose ATTRIBUTE_UNUSED)
6381 free (spec_check_no);
6386 /* We are about to being issuing insns for this clock cycle.
6387 Override the default sort algorithm to better slot instructions. */
6390 ia64_dfa_sched_reorder (FILE *dump, int sched_verbose, rtx *ready,
6391 int *pn_ready, int clock_var ATTRIBUTE_UNUSED,
6395 int n_ready = *pn_ready;
6396 rtx *e_ready = ready + n_ready;
6400 fprintf (dump, "// ia64_dfa_sched_reorder (type %d):\n", reorder_type);
6402 if (reorder_type == 0)
6404 /* First, move all USEs, CLOBBERs and other crud out of the way. */
6406 for (insnp = ready; insnp < e_ready; insnp++)
6407 if (insnp < e_ready)
6410 enum attr_type t = ia64_safe_type (insn);
6411 if (t == TYPE_UNKNOWN)
6413 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
6414 || asm_noperands (PATTERN (insn)) >= 0)
6416 rtx lowest = ready[n_asms];
6417 ready[n_asms] = insn;
6423 rtx highest = ready[n_ready - 1];
6424 ready[n_ready - 1] = insn;
6431 if (n_asms < n_ready)
6433 /* Some normal insns to process. Skip the asms. */
6437 else if (n_ready > 0)
6441 if (ia64_final_schedule)
6444 int nr_need_stop = 0;
6446 for (insnp = ready; insnp < e_ready; insnp++)
6447 if (safe_group_barrier_needed (*insnp))
6450 if (reorder_type == 1 && n_ready == nr_need_stop)
6452 if (reorder_type == 0)
6455 /* Move down everything that needs a stop bit, preserving
6457 while (insnp-- > ready + deleted)
6458 while (insnp >= ready + deleted)
6461 if (! safe_group_barrier_needed (insn))
6463 memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx));
6474 /* We are about to being issuing insns for this clock cycle. Override
6475 the default sort algorithm to better slot instructions. */
6478 ia64_sched_reorder (FILE *dump, int sched_verbose, rtx *ready, int *pn_ready,
6481 return ia64_dfa_sched_reorder (dump, sched_verbose, ready,
6482 pn_ready, clock_var, 0);
6485 /* Like ia64_sched_reorder, but called after issuing each insn.
6486 Override the default sort algorithm to better slot instructions. */
6489 ia64_sched_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
6490 int sched_verbose ATTRIBUTE_UNUSED, rtx *ready,
6491 int *pn_ready, int clock_var)
6493 if (ia64_tune == PROCESSOR_ITANIUM && reload_completed && last_scheduled_insn)
6494 clocks [INSN_UID (last_scheduled_insn)] = clock_var;
6495 return ia64_dfa_sched_reorder (dump, sched_verbose, ready, pn_ready,
6499 /* We are about to issue INSN. Return the number of insns left on the
6500 ready queue that can be issued this cycle. */
6503 ia64_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
6504 int sched_verbose ATTRIBUTE_UNUSED,
6505 rtx insn ATTRIBUTE_UNUSED,
6506 int can_issue_more ATTRIBUTE_UNUSED)
6508 if (current_sched_info->flags & DO_SPECULATION)
6509 /* Modulo scheduling does not extend h_i_d when emitting
6510 new instructions. Deal with it. */
6512 if (DONE_SPEC (insn) & BEGIN_DATA)
6513 pending_data_specs++;
6514 if (CHECK_SPEC (insn) & BEGIN_DATA)
6515 pending_data_specs--;
6518 last_scheduled_insn = insn;
6519 memcpy (prev_cycle_state, curr_state, dfa_state_size);
6520 if (reload_completed)
6522 int needed = group_barrier_needed (insn);
6524 gcc_assert (!needed);
6525 if (GET_CODE (insn) == CALL_INSN)
6526 init_insn_group_barriers ();
6527 stops_p [INSN_UID (insn)] = stop_before_p;
6533 /* We are choosing insn from the ready queue. Return nonzero if INSN
6537 ia64_first_cycle_multipass_dfa_lookahead_guard (rtx insn)
6539 gcc_assert (insn && INSN_P (insn));
6540 return ((!reload_completed
6541 || !safe_group_barrier_needed (insn))
6542 && ia64_first_cycle_multipass_dfa_lookahead_guard_spec (insn));
6545 /* We are choosing insn from the ready queue. Return nonzero if INSN
6549 ia64_first_cycle_multipass_dfa_lookahead_guard_spec (rtx insn)
6551 gcc_assert (insn && INSN_P (insn));
6552 /* Size of ALAT is 32. As far as we perform conservative data speculation,
6553 we keep ALAT half-empty. */
6554 return (pending_data_specs < 16
6555 || !(TODO_SPEC (insn) & BEGIN_DATA));
6558 /* The following variable value is pseudo-insn used by the DFA insn
6559 scheduler to change the DFA state when the simulated clock is
6562 static rtx dfa_pre_cycle_insn;
6564 /* We are about to being issuing INSN. Return nonzero if we cannot
6565 issue it on given cycle CLOCK and return zero if we should not sort
6566 the ready queue on the next clock start. */
6569 ia64_dfa_new_cycle (FILE *dump, int verbose, rtx insn, int last_clock,
6570 int clock, int *sort_p)
6572 int setup_clocks_p = FALSE;
6574 gcc_assert (insn && INSN_P (insn));
6575 if ((reload_completed && safe_group_barrier_needed (insn))
6576 || (last_scheduled_insn
6577 && (GET_CODE (last_scheduled_insn) == CALL_INSN
6578 || GET_CODE (PATTERN (last_scheduled_insn)) == ASM_INPUT
6579 || asm_noperands (PATTERN (last_scheduled_insn)) >= 0)))
6581 init_insn_group_barriers ();
6582 if (verbose && dump)
6583 fprintf (dump, "// Stop should be before %d%s\n", INSN_UID (insn),
6584 last_clock == clock ? " + cycle advance" : "");
6586 if (last_clock == clock)
6588 state_transition (curr_state, dfa_stop_insn);
6589 if (TARGET_EARLY_STOP_BITS)
6590 *sort_p = (last_scheduled_insn == NULL_RTX
6591 || GET_CODE (last_scheduled_insn) != CALL_INSN);
6596 else if (reload_completed)
6597 setup_clocks_p = TRUE;
6598 if (GET_CODE (PATTERN (last_scheduled_insn)) == ASM_INPUT
6599 || asm_noperands (PATTERN (last_scheduled_insn)) >= 0)
6600 state_reset (curr_state);
6603 memcpy (curr_state, prev_cycle_state, dfa_state_size);
6604 state_transition (curr_state, dfa_stop_insn);
6605 state_transition (curr_state, dfa_pre_cycle_insn);
6606 state_transition (curr_state, NULL);
6609 else if (reload_completed)
6610 setup_clocks_p = TRUE;
6611 if (setup_clocks_p && ia64_tune == PROCESSOR_ITANIUM
6612 && GET_CODE (PATTERN (insn)) != ASM_INPUT
6613 && asm_noperands (PATTERN (insn)) < 0)
6615 enum attr_itanium_class c = ia64_safe_itanium_class (insn);
6617 if (c != ITANIUM_CLASS_MMMUL && c != ITANIUM_CLASS_MMSHF)
6622 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
6623 if (REG_NOTE_KIND (link) == 0)
6625 enum attr_itanium_class dep_class;
6626 rtx dep_insn = XEXP (link, 0);
6628 dep_class = ia64_safe_itanium_class (dep_insn);
6629 if ((dep_class == ITANIUM_CLASS_MMMUL
6630 || dep_class == ITANIUM_CLASS_MMSHF)
6631 && last_clock - clocks [INSN_UID (dep_insn)] < 4
6633 || last_clock - clocks [INSN_UID (dep_insn)] < d))
6634 d = last_clock - clocks [INSN_UID (dep_insn)];
6637 add_cycles [INSN_UID (insn)] = 3 - d;
6643 /* Implement targetm.sched.h_i_d_extended hook.
6644 Extend internal data structures. */
6646 ia64_h_i_d_extended (void)
6648 if (current_sched_info->flags & DO_SPECULATION)
6650 int new_max_uid = get_max_uid () + 1;
6652 spec_check_no = xrecalloc (spec_check_no, new_max_uid,
6653 max_uid, sizeof (*spec_check_no));
6654 max_uid = new_max_uid;
6657 if (stops_p != NULL)
6659 int new_clocks_length = get_max_uid () + 1;
6661 stops_p = xrecalloc (stops_p, new_clocks_length, clocks_length, 1);
6663 if (ia64_tune == PROCESSOR_ITANIUM)
6665 clocks = xrecalloc (clocks, new_clocks_length, clocks_length,
6667 add_cycles = xrecalloc (add_cycles, new_clocks_length, clocks_length,
6671 clocks_length = new_clocks_length;
6675 /* Constants that help mapping 'enum machine_mode' to int. */
6678 SPEC_MODE_INVALID = -1,
6679 SPEC_MODE_FIRST = 0,
6680 SPEC_MODE_FOR_EXTEND_FIRST = 1,
6681 SPEC_MODE_FOR_EXTEND_LAST = 3,
6685 /* Return index of the MODE. */
6687 ia64_mode_to_int (enum machine_mode mode)
6691 case BImode: return 0; /* SPEC_MODE_FIRST */
6692 case QImode: return 1; /* SPEC_MODE_FOR_EXTEND_FIRST */
6693 case HImode: return 2;
6694 case SImode: return 3; /* SPEC_MODE_FOR_EXTEND_LAST */
6695 case DImode: return 4;
6696 case SFmode: return 5;
6697 case DFmode: return 6;
6698 case XFmode: return 7;
6700 /* ??? This mode needs testing. Bypasses for ldfp8 instruction are not
6701 mentioned in itanium[12].md. Predicate fp_register_operand also
6702 needs to be defined. Bottom line: better disable for now. */
6703 return SPEC_MODE_INVALID;
6704 default: return SPEC_MODE_INVALID;
6708 /* Provide information about speculation capabilities. */
6710 ia64_set_sched_flags (spec_info_t spec_info)
6712 unsigned int *flags = &(current_sched_info->flags);
6714 if (*flags & SCHED_RGN
6715 || *flags & SCHED_EBB)
6719 if ((mflag_sched_br_data_spec && !reload_completed && optimize > 0)
6720 || (mflag_sched_ar_data_spec && reload_completed))
6724 if ((mflag_sched_br_in_data_spec && !reload_completed)
6725 || (mflag_sched_ar_in_data_spec && reload_completed))
6729 if (mflag_sched_control_spec)
6731 mask |= BEGIN_CONTROL;
6733 if (mflag_sched_in_control_spec)
6734 mask |= BE_IN_CONTROL;
6737 gcc_assert (*flags & USE_GLAT);
6741 *flags |= USE_DEPS_LIST | DETACH_LIFE_INFO | DO_SPECULATION;
6743 spec_info->mask = mask;
6744 spec_info->flags = 0;
6746 if ((mask & DATA_SPEC) && mflag_sched_prefer_non_data_spec_insns)
6747 spec_info->flags |= PREFER_NON_DATA_SPEC;
6749 if ((mask & CONTROL_SPEC)
6750 && mflag_sched_prefer_non_control_spec_insns)
6751 spec_info->flags |= PREFER_NON_CONTROL_SPEC;
6753 if (mflag_sched_spec_verbose)
6755 if (sched_verbose >= 1)
6756 spec_info->dump = sched_dump;
6758 spec_info->dump = stderr;
6761 spec_info->dump = 0;
6763 if (mflag_sched_count_spec_in_critical_path)
6764 spec_info->flags |= COUNT_SPEC_IN_CRITICAL_PATH;
6769 /* Implement targetm.sched.speculate_insn hook.
6770 Check if the INSN can be TS speculative.
6771 If 'no' - return -1.
6772 If 'yes' - generate speculative pattern in the NEW_PAT and return 1.
6773 If current pattern of the INSN already provides TS speculation, return 0. */
6775 ia64_speculate_insn (rtx insn, ds_t ts, rtx *new_pat)
6777 rtx pat, reg, mem, mem_reg;
6778 int mode_no, gen_p = 1;
6781 gcc_assert (!(ts & ~BEGIN_SPEC) && ts);
6783 pat = PATTERN (insn);
6785 if (GET_CODE (pat) == COND_EXEC)
6786 pat = COND_EXEC_CODE (pat);
6788 if (GET_CODE (pat) != SET)
6790 reg = SET_DEST (pat);
6794 mem = SET_SRC (pat);
6795 if (GET_CODE (mem) == ZERO_EXTEND)
6797 mem = XEXP (mem, 0);
6803 if (GET_CODE (mem) == UNSPEC)
6807 code = XINT (mem, 1);
6808 if (code != UNSPEC_LDA && code != UNSPEC_LDS && code != UNSPEC_LDSA)
6811 if ((code == UNSPEC_LDA && !(ts & BEGIN_CONTROL))
6812 || (code == UNSPEC_LDS && !(ts & BEGIN_DATA))
6813 || code == UNSPEC_LDSA)
6816 mem = XVECEXP (mem, 0, 0);
6817 gcc_assert (MEM_P (mem));
6821 mem_reg = XEXP (mem, 0);
6822 if (!REG_P (mem_reg))
6825 /* We should use MEM's mode since REG's mode in presence of ZERO_EXTEND
6826 will always be DImode. */
6827 mode_no = ia64_mode_to_int (GET_MODE (mem));
6829 if (mode_no == SPEC_MODE_INVALID
6831 && !(SPEC_MODE_FOR_EXTEND_FIRST <= mode_no
6832 && mode_no <= SPEC_MODE_FOR_EXTEND_LAST)))
6835 extract_insn_cached (insn);
6836 gcc_assert (reg == recog_data.operand[0] && mem == recog_data.operand[1]);
6837 *new_pat = ia64_gen_spec_insn (insn, ts, mode_no, gen_p != 0, extend_p);
6844 /* Offset to reach ZERO_EXTEND patterns. */
6845 SPEC_GEN_EXTEND_OFFSET = SPEC_MODE_LAST - SPEC_MODE_FOR_EXTEND_FIRST + 1,
6846 /* Number of patterns for each speculation mode. */
6847 SPEC_N = (SPEC_MODE_LAST
6848 + SPEC_MODE_FOR_EXTEND_LAST - SPEC_MODE_FOR_EXTEND_FIRST + 2)
6851 enum SPEC_GEN_LD_MAP
6853 /* Offset to ld.a patterns. */
6854 SPEC_GEN_A = 0 * SPEC_N,
6855 /* Offset to ld.s patterns. */
6856 SPEC_GEN_S = 1 * SPEC_N,
6857 /* Offset to ld.sa patterns. */
6858 SPEC_GEN_SA = 2 * SPEC_N,
6859 /* Offset to ld.sa patterns. For this patterns corresponding ld.c will
6861 SPEC_GEN_SA_FOR_S = 3 * SPEC_N
6864 /* These offsets are used to get (4 * SPEC_N). */
6865 enum SPEC_GEN_CHECK_OFFSET
6867 SPEC_GEN_CHKA_FOR_A_OFFSET = 4 * SPEC_N - SPEC_GEN_A,
6868 SPEC_GEN_CHKA_FOR_SA_OFFSET = 4 * SPEC_N - SPEC_GEN_SA
6871 /* If GEN_P is true, calculate the index of needed speculation check and return
6872 speculative pattern for INSN with speculative mode TS, machine mode
6873 MODE_NO and with ZERO_EXTEND (if EXTEND_P is true).
6874 If GEN_P is false, just calculate the index of needed speculation check. */
6876 ia64_gen_spec_insn (rtx insn, ds_t ts, int mode_no, bool gen_p, bool extend_p)
6882 static rtx (* const gen_load[]) (rtx, rtx) = {
6892 gen_zero_extendqidi2_advanced,
6893 gen_zero_extendhidi2_advanced,
6894 gen_zero_extendsidi2_advanced,
6896 gen_movbi_speculative,
6897 gen_movqi_speculative,
6898 gen_movhi_speculative,
6899 gen_movsi_speculative,
6900 gen_movdi_speculative,
6901 gen_movsf_speculative,
6902 gen_movdf_speculative,
6903 gen_movxf_speculative,
6904 gen_movti_speculative,
6905 gen_zero_extendqidi2_speculative,
6906 gen_zero_extendhidi2_speculative,
6907 gen_zero_extendsidi2_speculative,
6909 gen_movbi_speculative_advanced,
6910 gen_movqi_speculative_advanced,
6911 gen_movhi_speculative_advanced,
6912 gen_movsi_speculative_advanced,
6913 gen_movdi_speculative_advanced,
6914 gen_movsf_speculative_advanced,
6915 gen_movdf_speculative_advanced,
6916 gen_movxf_speculative_advanced,
6917 gen_movti_speculative_advanced,
6918 gen_zero_extendqidi2_speculative_advanced,
6919 gen_zero_extendhidi2_speculative_advanced,
6920 gen_zero_extendsidi2_speculative_advanced,
6922 gen_movbi_speculative_advanced,
6923 gen_movqi_speculative_advanced,
6924 gen_movhi_speculative_advanced,
6925 gen_movsi_speculative_advanced,
6926 gen_movdi_speculative_advanced,
6927 gen_movsf_speculative_advanced,
6928 gen_movdf_speculative_advanced,
6929 gen_movxf_speculative_advanced,
6930 gen_movti_speculative_advanced,
6931 gen_zero_extendqidi2_speculative_advanced,
6932 gen_zero_extendhidi2_speculative_advanced,
6933 gen_zero_extendsidi2_speculative_advanced
6936 load_no = extend_p ? mode_no + SPEC_GEN_EXTEND_OFFSET : mode_no;
6938 if (ts & BEGIN_DATA)
6940 /* We don't need recovery because even if this is ld.sa
6941 ALAT entry will be allocated only if NAT bit is set to zero.
6942 So it is enough to use ld.c here. */
6944 if (ts & BEGIN_CONTROL)
6946 load_no += SPEC_GEN_SA;
6948 if (!mflag_sched_ldc)
6949 shift = SPEC_GEN_CHKA_FOR_SA_OFFSET;
6953 load_no += SPEC_GEN_A;
6955 if (!mflag_sched_ldc)
6956 shift = SPEC_GEN_CHKA_FOR_A_OFFSET;
6959 else if (ts & BEGIN_CONTROL)
6961 /* ld.sa can be used instead of ld.s to avoid basic block splitting. */
6962 if (!mflag_control_ldc)
6963 load_no += SPEC_GEN_S;
6966 gcc_assert (mflag_sched_ldc);
6967 load_no += SPEC_GEN_SA_FOR_S;
6973 /* Set the desired check index. We add '1', because zero element in this
6974 array means, that instruction with such uid is non-speculative. */
6975 spec_check_no[INSN_UID (insn)] = load_no + shift + 1;
6980 new_pat = gen_load[load_no] (copy_rtx (recog_data.operand[0]),
6981 copy_rtx (recog_data.operand[1]));
6983 pat = PATTERN (insn);
6984 if (GET_CODE (pat) == COND_EXEC)
6985 new_pat = gen_rtx_COND_EXEC (VOIDmode, copy_rtx
6986 (COND_EXEC_TEST (pat)), new_pat);
6991 /* Offset to branchy checks. */
6992 enum { SPEC_GEN_CHECK_MUTATION_OFFSET = 5 * SPEC_N };
6994 /* Return nonzero, if INSN needs branchy recovery check. */
6996 ia64_needs_block_p (rtx insn)
7000 check_no = spec_check_no[INSN_UID(insn)] - 1;
7001 gcc_assert (0 <= check_no && check_no < SPEC_GEN_CHECK_MUTATION_OFFSET);
7003 return ((SPEC_GEN_S <= check_no && check_no < SPEC_GEN_S + SPEC_N)
7004 || (4 * SPEC_N <= check_no && check_no < 4 * SPEC_N + SPEC_N));
7007 /* Generate (or regenerate, if (MUTATE_P)) recovery check for INSN.
7008 If (LABEL != 0 || MUTATE_P), generate branchy recovery check.
7009 Otherwise, generate a simple check. */
7011 ia64_gen_check (rtx insn, rtx label, bool mutate_p)
7013 rtx op1, pat, check_pat;
7015 static rtx (* const gen_check[]) (rtx, rtx) = {
7025 gen_zero_extendqidi2_clr,
7026 gen_zero_extendhidi2_clr,
7027 gen_zero_extendsidi2_clr,
7029 gen_speculation_check_bi,
7030 gen_speculation_check_qi,
7031 gen_speculation_check_hi,
7032 gen_speculation_check_si,
7033 gen_speculation_check_di,
7034 gen_speculation_check_sf,
7035 gen_speculation_check_df,
7036 gen_speculation_check_xf,
7037 gen_speculation_check_ti,
7038 gen_speculation_check_di,
7039 gen_speculation_check_di,
7040 gen_speculation_check_di,
7051 gen_zero_extendqidi2_clr,
7052 gen_zero_extendhidi2_clr,
7053 gen_zero_extendsidi2_clr,
7064 gen_zero_extendqidi2_clr,
7065 gen_zero_extendhidi2_clr,
7066 gen_zero_extendsidi2_clr,
7068 gen_advanced_load_check_clr_bi,
7069 gen_advanced_load_check_clr_qi,
7070 gen_advanced_load_check_clr_hi,
7071 gen_advanced_load_check_clr_si,
7072 gen_advanced_load_check_clr_di,
7073 gen_advanced_load_check_clr_sf,
7074 gen_advanced_load_check_clr_df,
7075 gen_advanced_load_check_clr_xf,
7076 gen_advanced_load_check_clr_ti,
7077 gen_advanced_load_check_clr_di,
7078 gen_advanced_load_check_clr_di,
7079 gen_advanced_load_check_clr_di,
7081 /* Following checks are generated during mutation. */
7082 gen_advanced_load_check_clr_bi,
7083 gen_advanced_load_check_clr_qi,
7084 gen_advanced_load_check_clr_hi,
7085 gen_advanced_load_check_clr_si,
7086 gen_advanced_load_check_clr_di,
7087 gen_advanced_load_check_clr_sf,
7088 gen_advanced_load_check_clr_df,
7089 gen_advanced_load_check_clr_xf,
7090 gen_advanced_load_check_clr_ti,
7091 gen_advanced_load_check_clr_di,
7092 gen_advanced_load_check_clr_di,
7093 gen_advanced_load_check_clr_di,
7095 0,0,0,0,0,0,0,0,0,0,0,0,
7097 gen_advanced_load_check_clr_bi,
7098 gen_advanced_load_check_clr_qi,
7099 gen_advanced_load_check_clr_hi,
7100 gen_advanced_load_check_clr_si,
7101 gen_advanced_load_check_clr_di,
7102 gen_advanced_load_check_clr_sf,
7103 gen_advanced_load_check_clr_df,
7104 gen_advanced_load_check_clr_xf,
7105 gen_advanced_load_check_clr_ti,
7106 gen_advanced_load_check_clr_di,
7107 gen_advanced_load_check_clr_di,
7108 gen_advanced_load_check_clr_di,
7110 gen_speculation_check_bi,
7111 gen_speculation_check_qi,
7112 gen_speculation_check_hi,
7113 gen_speculation_check_si,
7114 gen_speculation_check_di,
7115 gen_speculation_check_sf,
7116 gen_speculation_check_df,
7117 gen_speculation_check_xf,
7118 gen_speculation_check_ti,
7119 gen_speculation_check_di,
7120 gen_speculation_check_di,
7121 gen_speculation_check_di
7124 extract_insn_cached (insn);
7128 gcc_assert (mutate_p || ia64_needs_block_p (insn));
7133 gcc_assert (!mutate_p && !ia64_needs_block_p (insn));
7134 op1 = copy_rtx (recog_data.operand[1]);
7139 Find the speculation check number by searching for original
7140 speculative load in the RESOLVED_DEPS list of INSN.
7141 As long as patterns are unique for each instruction, this can be
7142 accomplished by matching ORIG_PAT fields. */
7146 rtx orig_pat = ORIG_PAT (insn);
7148 for (link = RESOLVED_DEPS (insn); link; link = XEXP (link, 1))
7150 rtx x = XEXP (link, 0);
7152 if (ORIG_PAT (x) == orig_pat)
7153 check_no = spec_check_no[INSN_UID (x)];
7155 gcc_assert (check_no);
7157 spec_check_no[INSN_UID (insn)] = (check_no
7158 + SPEC_GEN_CHECK_MUTATION_OFFSET);
7161 check_pat = (gen_check[spec_check_no[INSN_UID (insn)] - 1]
7162 (copy_rtx (recog_data.operand[0]), op1));
7164 pat = PATTERN (insn);
7165 if (GET_CODE (pat) == COND_EXEC)
7166 check_pat = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (COND_EXEC_TEST (pat)),
7172 /* Return nonzero, if X is branchy recovery check. */
7174 ia64_spec_check_p (rtx x)
7177 if (GET_CODE (x) == COND_EXEC)
7178 x = COND_EXEC_CODE (x);
7179 if (GET_CODE (x) == SET)
7180 return ia64_spec_check_src_p (SET_SRC (x));
7184 /* Return nonzero, if SRC belongs to recovery check. */
7186 ia64_spec_check_src_p (rtx src)
7188 if (GET_CODE (src) == IF_THEN_ELSE)
7193 if (GET_CODE (t) == NE)
7197 if (GET_CODE (t) == UNSPEC)
7203 if (code == UNSPEC_CHKACLR
7204 || code == UNSPEC_CHKS
7205 || code == UNSPEC_LDCCLR)
7207 gcc_assert (code != 0);
7217 /* The following page contains abstract data `bundle states' which are
7218 used for bundling insns (inserting nops and template generation). */
7220 /* The following describes state of insn bundling. */
7224 /* Unique bundle state number to identify them in the debugging
7227 rtx insn; /* corresponding insn, NULL for the 1st and the last state */
7228 /* number nops before and after the insn */
7229 short before_nops_num, after_nops_num;
7230 int insn_num; /* insn number (0 - for initial state, 1 - for the 1st
7232 int cost; /* cost of the state in cycles */
7233 int accumulated_insns_num; /* number of all previous insns including
7234 nops. L is considered as 2 insns */
7235 int branch_deviation; /* deviation of previous branches from 3rd slots */
7236 struct bundle_state *next; /* next state with the same insn_num */
7237 struct bundle_state *originator; /* originator (previous insn state) */
7238 /* All bundle states are in the following chain. */
7239 struct bundle_state *allocated_states_chain;
7240 /* The DFA State after issuing the insn and the nops. */
7244 /* The following is map insn number to the corresponding bundle state. */
7246 static struct bundle_state **index_to_bundle_states;
7248 /* The unique number of next bundle state. */
7250 static int bundle_states_num;
7252 /* All allocated bundle states are in the following chain. */
7254 static struct bundle_state *allocated_bundle_states_chain;
7256 /* All allocated but not used bundle states are in the following
7259 static struct bundle_state *free_bundle_state_chain;
7262 /* The following function returns a free bundle state. */
7264 static struct bundle_state *
7265 get_free_bundle_state (void)
7267 struct bundle_state *result;
7269 if (free_bundle_state_chain != NULL)
7271 result = free_bundle_state_chain;
7272 free_bundle_state_chain = result->next;
7276 result = xmalloc (sizeof (struct bundle_state));
7277 result->dfa_state = xmalloc (dfa_state_size);
7278 result->allocated_states_chain = allocated_bundle_states_chain;
7279 allocated_bundle_states_chain = result;
7281 result->unique_num = bundle_states_num++;
7286 /* The following function frees given bundle state. */
7289 free_bundle_state (struct bundle_state *state)
7291 state->next = free_bundle_state_chain;
7292 free_bundle_state_chain = state;
7295 /* Start work with abstract data `bundle states'. */
7298 initiate_bundle_states (void)
7300 bundle_states_num = 0;
7301 free_bundle_state_chain = NULL;
7302 allocated_bundle_states_chain = NULL;
7305 /* Finish work with abstract data `bundle states'. */
7308 finish_bundle_states (void)
7310 struct bundle_state *curr_state, *next_state;
7312 for (curr_state = allocated_bundle_states_chain;
7314 curr_state = next_state)
7316 next_state = curr_state->allocated_states_chain;
7317 free (curr_state->dfa_state);
7322 /* Hash table of the bundle states. The key is dfa_state and insn_num
7323 of the bundle states. */
7325 static htab_t bundle_state_table;
7327 /* The function returns hash of BUNDLE_STATE. */
7330 bundle_state_hash (const void *bundle_state)
7332 const struct bundle_state *state = (struct bundle_state *) bundle_state;
7335 for (result = i = 0; i < dfa_state_size; i++)
7336 result += (((unsigned char *) state->dfa_state) [i]
7337 << ((i % CHAR_BIT) * 3 + CHAR_BIT));
7338 return result + state->insn_num;
7341 /* The function returns nonzero if the bundle state keys are equal. */
7344 bundle_state_eq_p (const void *bundle_state_1, const void *bundle_state_2)
7346 const struct bundle_state * state1 = (struct bundle_state *) bundle_state_1;
7347 const struct bundle_state * state2 = (struct bundle_state *) bundle_state_2;
7349 return (state1->insn_num == state2->insn_num
7350 && memcmp (state1->dfa_state, state2->dfa_state,
7351 dfa_state_size) == 0);
7354 /* The function inserts the BUNDLE_STATE into the hash table. The
7355 function returns nonzero if the bundle has been inserted into the
7356 table. The table contains the best bundle state with given key. */
7359 insert_bundle_state (struct bundle_state *bundle_state)
7363 entry_ptr = htab_find_slot (bundle_state_table, bundle_state, 1);
7364 if (*entry_ptr == NULL)
7366 bundle_state->next = index_to_bundle_states [bundle_state->insn_num];
7367 index_to_bundle_states [bundle_state->insn_num] = bundle_state;
7368 *entry_ptr = (void *) bundle_state;
7371 else if (bundle_state->cost < ((struct bundle_state *) *entry_ptr)->cost
7372 || (bundle_state->cost == ((struct bundle_state *) *entry_ptr)->cost
7373 && (((struct bundle_state *)*entry_ptr)->accumulated_insns_num
7374 > bundle_state->accumulated_insns_num
7375 || (((struct bundle_state *)
7376 *entry_ptr)->accumulated_insns_num
7377 == bundle_state->accumulated_insns_num
7378 && ((struct bundle_state *)
7379 *entry_ptr)->branch_deviation
7380 > bundle_state->branch_deviation))))
7383 struct bundle_state temp;
7385 temp = *(struct bundle_state *) *entry_ptr;
7386 *(struct bundle_state *) *entry_ptr = *bundle_state;
7387 ((struct bundle_state *) *entry_ptr)->next = temp.next;
7388 *bundle_state = temp;
7393 /* Start work with the hash table. */
7396 initiate_bundle_state_table (void)
7398 bundle_state_table = htab_create (50, bundle_state_hash, bundle_state_eq_p,
7402 /* Finish work with the hash table. */
7405 finish_bundle_state_table (void)
7407 htab_delete (bundle_state_table);
7412 /* The following variable is a insn `nop' used to check bundle states
7413 with different number of inserted nops. */
7415 static rtx ia64_nop;
7417 /* The following function tries to issue NOPS_NUM nops for the current
7418 state without advancing processor cycle. If it failed, the
7419 function returns FALSE and frees the current state. */
7422 try_issue_nops (struct bundle_state *curr_state, int nops_num)
7426 for (i = 0; i < nops_num; i++)
7427 if (state_transition (curr_state->dfa_state, ia64_nop) >= 0)
7429 free_bundle_state (curr_state);
7435 /* The following function tries to issue INSN for the current
7436 state without advancing processor cycle. If it failed, the
7437 function returns FALSE and frees the current state. */
7440 try_issue_insn (struct bundle_state *curr_state, rtx insn)
7442 if (insn && state_transition (curr_state->dfa_state, insn) >= 0)
7444 free_bundle_state (curr_state);
7450 /* The following function tries to issue BEFORE_NOPS_NUM nops and INSN
7451 starting with ORIGINATOR without advancing processor cycle. If
7452 TRY_BUNDLE_END_P is TRUE, the function also/only (if
7453 ONLY_BUNDLE_END_P is TRUE) tries to issue nops to fill all bundle.
7454 If it was successful, the function creates new bundle state and
7455 insert into the hash table and into `index_to_bundle_states'. */
7458 issue_nops_and_insn (struct bundle_state *originator, int before_nops_num,
7459 rtx insn, int try_bundle_end_p, int only_bundle_end_p)
7461 struct bundle_state *curr_state;
7463 curr_state = get_free_bundle_state ();
7464 memcpy (curr_state->dfa_state, originator->dfa_state, dfa_state_size);
7465 curr_state->insn = insn;
7466 curr_state->insn_num = originator->insn_num + 1;
7467 curr_state->cost = originator->cost;
7468 curr_state->originator = originator;
7469 curr_state->before_nops_num = before_nops_num;
7470 curr_state->after_nops_num = 0;
7471 curr_state->accumulated_insns_num
7472 = originator->accumulated_insns_num + before_nops_num;
7473 curr_state->branch_deviation = originator->branch_deviation;
7475 if (INSN_CODE (insn) == CODE_FOR_insn_group_barrier)
7477 gcc_assert (GET_MODE (insn) != TImode);
7478 if (!try_issue_nops (curr_state, before_nops_num))
7480 if (!try_issue_insn (curr_state, insn))
7482 memcpy (temp_dfa_state, curr_state->dfa_state, dfa_state_size);
7483 if (state_transition (temp_dfa_state, dfa_pre_cycle_insn) >= 0
7484 && curr_state->accumulated_insns_num % 3 != 0)
7486 free_bundle_state (curr_state);
7490 else if (GET_MODE (insn) != TImode)
7492 if (!try_issue_nops (curr_state, before_nops_num))
7494 if (!try_issue_insn (curr_state, insn))
7496 curr_state->accumulated_insns_num++;
7497 gcc_assert (GET_CODE (PATTERN (insn)) != ASM_INPUT
7498 && asm_noperands (PATTERN (insn)) < 0);
7500 if (ia64_safe_type (insn) == TYPE_L)
7501 curr_state->accumulated_insns_num++;
7505 /* If this is an insn that must be first in a group, then don't allow
7506 nops to be emitted before it. Currently, alloc is the only such
7507 supported instruction. */
7508 /* ??? The bundling automatons should handle this for us, but they do
7509 not yet have support for the first_insn attribute. */
7510 if (before_nops_num > 0 && get_attr_first_insn (insn) == FIRST_INSN_YES)
7512 free_bundle_state (curr_state);
7516 state_transition (curr_state->dfa_state, dfa_pre_cycle_insn);
7517 state_transition (curr_state->dfa_state, NULL);
7519 if (!try_issue_nops (curr_state, before_nops_num))
7521 if (!try_issue_insn (curr_state, insn))
7523 curr_state->accumulated_insns_num++;
7524 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
7525 || asm_noperands (PATTERN (insn)) >= 0)
7527 /* Finish bundle containing asm insn. */
7528 curr_state->after_nops_num
7529 = 3 - curr_state->accumulated_insns_num % 3;
7530 curr_state->accumulated_insns_num
7531 += 3 - curr_state->accumulated_insns_num % 3;
7533 else if (ia64_safe_type (insn) == TYPE_L)
7534 curr_state->accumulated_insns_num++;
7536 if (ia64_safe_type (insn) == TYPE_B)
7537 curr_state->branch_deviation
7538 += 2 - (curr_state->accumulated_insns_num - 1) % 3;
7539 if (try_bundle_end_p && curr_state->accumulated_insns_num % 3 != 0)
7541 if (!only_bundle_end_p && insert_bundle_state (curr_state))
7544 struct bundle_state *curr_state1;
7545 struct bundle_state *allocated_states_chain;
7547 curr_state1 = get_free_bundle_state ();
7548 dfa_state = curr_state1->dfa_state;
7549 allocated_states_chain = curr_state1->allocated_states_chain;
7550 *curr_state1 = *curr_state;
7551 curr_state1->dfa_state = dfa_state;
7552 curr_state1->allocated_states_chain = allocated_states_chain;
7553 memcpy (curr_state1->dfa_state, curr_state->dfa_state,
7555 curr_state = curr_state1;
7557 if (!try_issue_nops (curr_state,
7558 3 - curr_state->accumulated_insns_num % 3))
7560 curr_state->after_nops_num
7561 = 3 - curr_state->accumulated_insns_num % 3;
7562 curr_state->accumulated_insns_num
7563 += 3 - curr_state->accumulated_insns_num % 3;
7565 if (!insert_bundle_state (curr_state))
7566 free_bundle_state (curr_state);
7570 /* The following function returns position in the two window bundle
7574 get_max_pos (state_t state)
7576 if (cpu_unit_reservation_p (state, pos_6))
7578 else if (cpu_unit_reservation_p (state, pos_5))
7580 else if (cpu_unit_reservation_p (state, pos_4))
7582 else if (cpu_unit_reservation_p (state, pos_3))
7584 else if (cpu_unit_reservation_p (state, pos_2))
7586 else if (cpu_unit_reservation_p (state, pos_1))
7592 /* The function returns code of a possible template for given position
7593 and state. The function should be called only with 2 values of
7594 position equal to 3 or 6. We avoid generating F NOPs by putting
7595 templates containing F insns at the end of the template search
7596 because undocumented anomaly in McKinley derived cores which can
7597 cause stalls if an F-unit insn (including a NOP) is issued within a
7598 six-cycle window after reading certain application registers (such
7599 as ar.bsp). Furthermore, power-considerations also argue against
7600 the use of F-unit instructions unless they're really needed. */
7603 get_template (state_t state, int pos)
7608 if (cpu_unit_reservation_p (state, _0mmi_))
7610 else if (cpu_unit_reservation_p (state, _0mii_))
7612 else if (cpu_unit_reservation_p (state, _0mmb_))
7614 else if (cpu_unit_reservation_p (state, _0mib_))
7616 else if (cpu_unit_reservation_p (state, _0mbb_))
7618 else if (cpu_unit_reservation_p (state, _0bbb_))
7620 else if (cpu_unit_reservation_p (state, _0mmf_))
7622 else if (cpu_unit_reservation_p (state, _0mfi_))
7624 else if (cpu_unit_reservation_p (state, _0mfb_))
7626 else if (cpu_unit_reservation_p (state, _0mlx_))
7631 if (cpu_unit_reservation_p (state, _1mmi_))
7633 else if (cpu_unit_reservation_p (state, _1mii_))
7635 else if (cpu_unit_reservation_p (state, _1mmb_))
7637 else if (cpu_unit_reservation_p (state, _1mib_))
7639 else if (cpu_unit_reservation_p (state, _1mbb_))
7641 else if (cpu_unit_reservation_p (state, _1bbb_))
7643 else if (_1mmf_ >= 0 && cpu_unit_reservation_p (state, _1mmf_))
7645 else if (cpu_unit_reservation_p (state, _1mfi_))
7647 else if (cpu_unit_reservation_p (state, _1mfb_))
7649 else if (cpu_unit_reservation_p (state, _1mlx_))
7658 /* The following function returns an insn important for insn bundling
7659 followed by INSN and before TAIL. */
7662 get_next_important_insn (rtx insn, rtx tail)
7664 for (; insn && insn != tail; insn = NEXT_INSN (insn))
7666 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
7667 && GET_CODE (PATTERN (insn)) != USE
7668 && GET_CODE (PATTERN (insn)) != CLOBBER)
7673 /* Add a bundle selector TEMPLATE0 before INSN. */
7676 ia64_add_bundle_selector_before (int template0, rtx insn)
7678 rtx b = gen_bundle_selector (GEN_INT (template0));
7680 ia64_emit_insn_before (b, insn);
7681 #if NR_BUNDLES == 10
7682 if ((template0 == 4 || template0 == 5)
7683 && (flag_unwind_tables || (flag_exceptions && !USING_SJLJ_EXCEPTIONS)))
7686 rtx note = NULL_RTX;
7688 /* In .mbb and .bbb bundles, check if CALL_INSN isn't in the
7689 first or second slot. If it is and has REG_EH_NOTE set, copy it
7690 to following nops, as br.call sets rp to the address of following
7691 bundle and therefore an EH region end must be on a bundle
7693 insn = PREV_INSN (insn);
7694 for (i = 0; i < 3; i++)
7697 insn = next_active_insn (insn);
7698 while (GET_CODE (insn) == INSN
7699 && get_attr_empty (insn) == EMPTY_YES);
7700 if (GET_CODE (insn) == CALL_INSN)
7701 note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
7706 gcc_assert ((code = recog_memoized (insn)) == CODE_FOR_nop
7707 || code == CODE_FOR_nop_b);
7708 if (find_reg_note (insn, REG_EH_REGION, NULL_RTX))
7712 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0),
7720 /* The following function does insn bundling. Bundling means
7721 inserting templates and nop insns to fit insn groups into permitted
7722 templates. Instruction scheduling uses NDFA (non-deterministic
7723 finite automata) encoding informations about the templates and the
7724 inserted nops. Nondeterminism of the automata permits follows
7725 all possible insn sequences very fast.
7727 Unfortunately it is not possible to get information about inserting
7728 nop insns and used templates from the automata states. The
7729 automata only says that we can issue an insn possibly inserting
7730 some nops before it and using some template. Therefore insn
7731 bundling in this function is implemented by using DFA
7732 (deterministic finite automata). We follow all possible insn
7733 sequences by inserting 0-2 nops (that is what the NDFA describe for
7734 insn scheduling) before/after each insn being bundled. We know the
7735 start of simulated processor cycle from insn scheduling (insn
7736 starting a new cycle has TImode).
7738 Simple implementation of insn bundling would create enormous
7739 number of possible insn sequences satisfying information about new
7740 cycle ticks taken from the insn scheduling. To make the algorithm
7741 practical we use dynamic programming. Each decision (about
7742 inserting nops and implicitly about previous decisions) is described
7743 by structure bundle_state (see above). If we generate the same
7744 bundle state (key is automaton state after issuing the insns and
7745 nops for it), we reuse already generated one. As consequence we
7746 reject some decisions which cannot improve the solution and
7747 reduce memory for the algorithm.
7749 When we reach the end of EBB (extended basic block), we choose the
7750 best sequence and then, moving back in EBB, insert templates for
7751 the best alternative. The templates are taken from querying
7752 automaton state for each insn in chosen bundle states.
7754 So the algorithm makes two (forward and backward) passes through
7755 EBB. There is an additional forward pass through EBB for Itanium1
7756 processor. This pass inserts more nops to make dependency between
7757 a producer insn and MMMUL/MMSHF at least 4 cycles long. */
7760 bundling (FILE *dump, int verbose, rtx prev_head_insn, rtx tail)
7762 struct bundle_state *curr_state, *next_state, *best_state;
7763 rtx insn, next_insn;
7765 int i, bundle_end_p, only_bundle_end_p, asm_p;
7766 int pos = 0, max_pos, template0, template1;
7769 enum attr_type type;
7772 /* Count insns in the EBB. */
7773 for (insn = NEXT_INSN (prev_head_insn);
7774 insn && insn != tail;
7775 insn = NEXT_INSN (insn))
7781 dfa_clean_insn_cache ();
7782 initiate_bundle_state_table ();
7783 index_to_bundle_states = xmalloc ((insn_num + 2)
7784 * sizeof (struct bundle_state *));
7785 /* First (forward) pass -- generation of bundle states. */
7786 curr_state = get_free_bundle_state ();
7787 curr_state->insn = NULL;
7788 curr_state->before_nops_num = 0;
7789 curr_state->after_nops_num = 0;
7790 curr_state->insn_num = 0;
7791 curr_state->cost = 0;
7792 curr_state->accumulated_insns_num = 0;
7793 curr_state->branch_deviation = 0;
7794 curr_state->next = NULL;
7795 curr_state->originator = NULL;
7796 state_reset (curr_state->dfa_state);
7797 index_to_bundle_states [0] = curr_state;
7799 /* Shift cycle mark if it is put on insn which could be ignored. */
7800 for (insn = NEXT_INSN (prev_head_insn);
7802 insn = NEXT_INSN (insn))
7804 && (ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IGNORE
7805 || GET_CODE (PATTERN (insn)) == USE
7806 || GET_CODE (PATTERN (insn)) == CLOBBER)
7807 && GET_MODE (insn) == TImode)
7809 PUT_MODE (insn, VOIDmode);
7810 for (next_insn = NEXT_INSN (insn);
7812 next_insn = NEXT_INSN (next_insn))
7813 if (INSN_P (next_insn)
7814 && ia64_safe_itanium_class (next_insn) != ITANIUM_CLASS_IGNORE
7815 && GET_CODE (PATTERN (next_insn)) != USE
7816 && GET_CODE (PATTERN (next_insn)) != CLOBBER)
7818 PUT_MODE (next_insn, TImode);
7822 /* Forward pass: generation of bundle states. */
7823 for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail);
7827 gcc_assert (INSN_P (insn)
7828 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
7829 && GET_CODE (PATTERN (insn)) != USE
7830 && GET_CODE (PATTERN (insn)) != CLOBBER);
7831 type = ia64_safe_type (insn);
7832 next_insn = get_next_important_insn (NEXT_INSN (insn), tail);
7834 index_to_bundle_states [insn_num] = NULL;
7835 for (curr_state = index_to_bundle_states [insn_num - 1];
7837 curr_state = next_state)
7839 pos = curr_state->accumulated_insns_num % 3;
7840 next_state = curr_state->next;
7841 /* We must fill up the current bundle in order to start a
7842 subsequent asm insn in a new bundle. Asm insn is always
7843 placed in a separate bundle. */
7845 = (next_insn != NULL_RTX
7846 && INSN_CODE (insn) == CODE_FOR_insn_group_barrier
7847 && ia64_safe_type (next_insn) == TYPE_UNKNOWN);
7848 /* We may fill up the current bundle if it is the cycle end
7849 without a group barrier. */
7851 = (only_bundle_end_p || next_insn == NULL_RTX
7852 || (GET_MODE (next_insn) == TImode
7853 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier));
7854 if (type == TYPE_F || type == TYPE_B || type == TYPE_L
7856 /* We need to insert 2 nops for cases like M_MII. To
7857 guarantee issuing all insns on the same cycle for
7858 Itanium 1, we need to issue 2 nops after the first M
7859 insn (MnnMII where n is a nop insn). */
7860 || ((type == TYPE_M || type == TYPE_A)
7861 && ia64_tune == PROCESSOR_ITANIUM
7862 && !bundle_end_p && pos == 1))
7863 issue_nops_and_insn (curr_state, 2, insn, bundle_end_p,
7865 issue_nops_and_insn (curr_state, 1, insn, bundle_end_p,
7867 issue_nops_and_insn (curr_state, 0, insn, bundle_end_p,
7870 gcc_assert (index_to_bundle_states [insn_num]);
7871 for (curr_state = index_to_bundle_states [insn_num];
7873 curr_state = curr_state->next)
7874 if (verbose >= 2 && dump)
7876 /* This structure is taken from generated code of the
7877 pipeline hazard recognizer (see file insn-attrtab.c).
7878 Please don't forget to change the structure if a new
7879 automaton is added to .md file. */
7882 unsigned short one_automaton_state;
7883 unsigned short oneb_automaton_state;
7884 unsigned short two_automaton_state;
7885 unsigned short twob_automaton_state;
7890 "// Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
7891 curr_state->unique_num,
7892 (curr_state->originator == NULL
7893 ? -1 : curr_state->originator->unique_num),
7895 curr_state->before_nops_num, curr_state->after_nops_num,
7896 curr_state->accumulated_insns_num, curr_state->branch_deviation,
7897 (ia64_tune == PROCESSOR_ITANIUM
7898 ? ((struct DFA_chip *) curr_state->dfa_state)->oneb_automaton_state
7899 : ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state),
7904 /* We should find a solution because the 2nd insn scheduling has
7906 gcc_assert (index_to_bundle_states [insn_num]);
7907 /* Find a state corresponding to the best insn sequence. */
7909 for (curr_state = index_to_bundle_states [insn_num];
7911 curr_state = curr_state->next)
7912 /* We are just looking at the states with fully filled up last
7913 bundle. The first we prefer insn sequences with minimal cost
7914 then with minimal inserted nops and finally with branch insns
7915 placed in the 3rd slots. */
7916 if (curr_state->accumulated_insns_num % 3 == 0
7917 && (best_state == NULL || best_state->cost > curr_state->cost
7918 || (best_state->cost == curr_state->cost
7919 && (curr_state->accumulated_insns_num
7920 < best_state->accumulated_insns_num
7921 || (curr_state->accumulated_insns_num
7922 == best_state->accumulated_insns_num
7923 && curr_state->branch_deviation
7924 < best_state->branch_deviation)))))
7925 best_state = curr_state;
7926 /* Second (backward) pass: adding nops and templates. */
7927 insn_num = best_state->before_nops_num;
7928 template0 = template1 = -1;
7929 for (curr_state = best_state;
7930 curr_state->originator != NULL;
7931 curr_state = curr_state->originator)
7933 insn = curr_state->insn;
7934 asm_p = (GET_CODE (PATTERN (insn)) == ASM_INPUT
7935 || asm_noperands (PATTERN (insn)) >= 0);
7937 if (verbose >= 2 && dump)
7941 unsigned short one_automaton_state;
7942 unsigned short oneb_automaton_state;
7943 unsigned short two_automaton_state;
7944 unsigned short twob_automaton_state;
7949 "// Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
7950 curr_state->unique_num,
7951 (curr_state->originator == NULL
7952 ? -1 : curr_state->originator->unique_num),
7954 curr_state->before_nops_num, curr_state->after_nops_num,
7955 curr_state->accumulated_insns_num, curr_state->branch_deviation,
7956 (ia64_tune == PROCESSOR_ITANIUM
7957 ? ((struct DFA_chip *) curr_state->dfa_state)->oneb_automaton_state
7958 : ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state),
7961 /* Find the position in the current bundle window. The window can
7962 contain at most two bundles. Two bundle window means that
7963 the processor will make two bundle rotation. */
7964 max_pos = get_max_pos (curr_state->dfa_state);
7966 /* The following (negative template number) means that the
7967 processor did one bundle rotation. */
7968 || (max_pos == 3 && template0 < 0))
7970 /* We are at the end of the window -- find template(s) for
7974 template0 = get_template (curr_state->dfa_state, 3);
7977 template1 = get_template (curr_state->dfa_state, 3);
7978 template0 = get_template (curr_state->dfa_state, 6);
7981 if (max_pos > 3 && template1 < 0)
7982 /* It may happen when we have the stop inside a bundle. */
7984 gcc_assert (pos <= 3);
7985 template1 = get_template (curr_state->dfa_state, 3);
7989 /* Emit nops after the current insn. */
7990 for (i = 0; i < curr_state->after_nops_num; i++)
7993 emit_insn_after (nop, insn);
7995 gcc_assert (pos >= 0);
7998 /* We are at the start of a bundle: emit the template
7999 (it should be defined). */
8000 gcc_assert (template0 >= 0);
8001 ia64_add_bundle_selector_before (template0, nop);
8002 /* If we have two bundle window, we make one bundle
8003 rotation. Otherwise template0 will be undefined
8004 (negative value). */
8005 template0 = template1;
8009 /* Move the position backward in the window. Group barrier has
8010 no slot. Asm insn takes all bundle. */
8011 if (INSN_CODE (insn) != CODE_FOR_insn_group_barrier
8012 && GET_CODE (PATTERN (insn)) != ASM_INPUT
8013 && asm_noperands (PATTERN (insn)) < 0)
8015 /* Long insn takes 2 slots. */
8016 if (ia64_safe_type (insn) == TYPE_L)
8018 gcc_assert (pos >= 0);
8020 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier
8021 && GET_CODE (PATTERN (insn)) != ASM_INPUT
8022 && asm_noperands (PATTERN (insn)) < 0)
8024 /* The current insn is at the bundle start: emit the
8026 gcc_assert (template0 >= 0);
8027 ia64_add_bundle_selector_before (template0, insn);
8028 b = PREV_INSN (insn);
8030 /* See comment above in analogous place for emitting nops
8032 template0 = template1;
8035 /* Emit nops after the current insn. */
8036 for (i = 0; i < curr_state->before_nops_num; i++)
8039 ia64_emit_insn_before (nop, insn);
8040 nop = PREV_INSN (insn);
8043 gcc_assert (pos >= 0);
8046 /* See comment above in analogous place for emitting nops
8048 gcc_assert (template0 >= 0);
8049 ia64_add_bundle_selector_before (template0, insn);
8050 b = PREV_INSN (insn);
8052 template0 = template1;
8057 if (ia64_tune == PROCESSOR_ITANIUM)
8058 /* Insert additional cycles for MM-insns (MMMUL and MMSHF).
8059 Itanium1 has a strange design, if the distance between an insn
8060 and dependent MM-insn is less 4 then we have a 6 additional
8061 cycles stall. So we make the distance equal to 4 cycles if it
8063 for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail);
8067 gcc_assert (INSN_P (insn)
8068 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
8069 && GET_CODE (PATTERN (insn)) != USE
8070 && GET_CODE (PATTERN (insn)) != CLOBBER);
8071 next_insn = get_next_important_insn (NEXT_INSN (insn), tail);
8072 if (INSN_UID (insn) < clocks_length && add_cycles [INSN_UID (insn)])
8073 /* We found a MM-insn which needs additional cycles. */
8079 /* Now we are searching for a template of the bundle in
8080 which the MM-insn is placed and the position of the
8081 insn in the bundle (0, 1, 2). Also we are searching
8082 for that there is a stop before the insn. */
8083 last = prev_active_insn (insn);
8084 pred_stop_p = recog_memoized (last) == CODE_FOR_insn_group_barrier;
8086 last = prev_active_insn (last);
8088 for (;; last = prev_active_insn (last))
8089 if (recog_memoized (last) == CODE_FOR_bundle_selector)
8091 template0 = XINT (XVECEXP (PATTERN (last), 0, 0), 0);
8093 /* The insn is in MLX bundle. Change the template
8094 onto MFI because we will add nops before the
8095 insn. It simplifies subsequent code a lot. */
8097 = gen_bundle_selector (const2_rtx); /* -> MFI */
8100 else if (recog_memoized (last) != CODE_FOR_insn_group_barrier
8101 && (ia64_safe_itanium_class (last)
8102 != ITANIUM_CLASS_IGNORE))
8104 /* Some check of correctness: the stop is not at the
8105 bundle start, there are no more 3 insns in the bundle,
8106 and the MM-insn is not at the start of bundle with
8108 gcc_assert ((!pred_stop_p || n)
8110 && (template0 != 9 || !n));
8111 /* Put nops after the insn in the bundle. */
8112 for (j = 3 - n; j > 0; j --)
8113 ia64_emit_insn_before (gen_nop (), insn);
8114 /* It takes into account that we will add more N nops
8115 before the insn lately -- please see code below. */
8116 add_cycles [INSN_UID (insn)]--;
8117 if (!pred_stop_p || add_cycles [INSN_UID (insn)])
8118 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
8121 add_cycles [INSN_UID (insn)]--;
8122 for (i = add_cycles [INSN_UID (insn)]; i > 0; i--)
8124 /* Insert "MII;" template. */
8125 ia64_emit_insn_before (gen_bundle_selector (const0_rtx),
8127 ia64_emit_insn_before (gen_nop (), insn);
8128 ia64_emit_insn_before (gen_nop (), insn);
8131 /* To decrease code size, we use "MI;I;"
8133 ia64_emit_insn_before
8134 (gen_insn_group_barrier (GEN_INT (3)), insn);
8137 ia64_emit_insn_before (gen_nop (), insn);
8138 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
8141 /* Put the MM-insn in the same slot of a bundle with the
8142 same template as the original one. */
8143 ia64_add_bundle_selector_before (template0, insn);
8144 /* To put the insn in the same slot, add necessary number
8146 for (j = n; j > 0; j --)
8147 ia64_emit_insn_before (gen_nop (), insn);
8148 /* Put the stop if the original bundle had it. */
8150 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
8154 free (index_to_bundle_states);
8155 finish_bundle_state_table ();
8157 dfa_clean_insn_cache ();
8160 /* The following function is called at the end of scheduling BB or
8161 EBB. After reload, it inserts stop bits and does insn bundling. */
8164 ia64_sched_finish (FILE *dump, int sched_verbose)
8167 fprintf (dump, "// Finishing schedule.\n");
8168 if (!reload_completed)
8170 if (reload_completed)
8172 final_emit_insn_group_barriers (dump);
8173 bundling (dump, sched_verbose, current_sched_info->prev_head,
8174 current_sched_info->next_tail);
8175 if (sched_verbose && dump)
8176 fprintf (dump, "// finishing %d-%d\n",
8177 INSN_UID (NEXT_INSN (current_sched_info->prev_head)),
8178 INSN_UID (PREV_INSN (current_sched_info->next_tail)));
8184 /* The following function inserts stop bits in scheduled BB or EBB. */
8187 final_emit_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED)
8190 int need_barrier_p = 0;
8191 rtx prev_insn = NULL_RTX;
8193 init_insn_group_barriers ();
8195 for (insn = NEXT_INSN (current_sched_info->prev_head);
8196 insn != current_sched_info->next_tail;
8197 insn = NEXT_INSN (insn))
8199 if (GET_CODE (insn) == BARRIER)
8201 rtx last = prev_active_insn (insn);
8205 if (GET_CODE (last) == JUMP_INSN
8206 && GET_CODE (PATTERN (last)) == ADDR_DIFF_VEC)
8207 last = prev_active_insn (last);
8208 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
8209 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
8211 init_insn_group_barriers ();
8213 prev_insn = NULL_RTX;
8215 else if (INSN_P (insn))
8217 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
8219 init_insn_group_barriers ();
8221 prev_insn = NULL_RTX;
8223 else if (need_barrier_p || group_barrier_needed (insn))
8225 if (TARGET_EARLY_STOP_BITS)
8230 last != current_sched_info->prev_head;
8231 last = PREV_INSN (last))
8232 if (INSN_P (last) && GET_MODE (last) == TImode
8233 && stops_p [INSN_UID (last)])
8235 if (last == current_sched_info->prev_head)
8237 last = prev_active_insn (last);
8239 && recog_memoized (last) != CODE_FOR_insn_group_barrier)
8240 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)),
8242 init_insn_group_barriers ();
8243 for (last = NEXT_INSN (last);
8245 last = NEXT_INSN (last))
8247 group_barrier_needed (last);
8251 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
8253 init_insn_group_barriers ();
8255 group_barrier_needed (insn);
8256 prev_insn = NULL_RTX;
8258 else if (recog_memoized (insn) >= 0)
8260 need_barrier_p = (GET_CODE (insn) == CALL_INSN
8261 || GET_CODE (PATTERN (insn)) == ASM_INPUT
8262 || asm_noperands (PATTERN (insn)) >= 0);
8269 /* If the following function returns TRUE, we will use the DFA
8273 ia64_first_cycle_multipass_dfa_lookahead (void)
8275 return (reload_completed ? 6 : 4);
8278 /* The following function initiates variable `dfa_pre_cycle_insn'. */
8281 ia64_init_dfa_pre_cycle_insn (void)
8283 if (temp_dfa_state == NULL)
8285 dfa_state_size = state_size ();
8286 temp_dfa_state = xmalloc (dfa_state_size);
8287 prev_cycle_state = xmalloc (dfa_state_size);
8289 dfa_pre_cycle_insn = make_insn_raw (gen_pre_cycle ());
8290 PREV_INSN (dfa_pre_cycle_insn) = NEXT_INSN (dfa_pre_cycle_insn) = NULL_RTX;
8291 recog_memoized (dfa_pre_cycle_insn);
8292 dfa_stop_insn = make_insn_raw (gen_insn_group_barrier (GEN_INT (3)));
8293 PREV_INSN (dfa_stop_insn) = NEXT_INSN (dfa_stop_insn) = NULL_RTX;
8294 recog_memoized (dfa_stop_insn);
8297 /* The following function returns the pseudo insn DFA_PRE_CYCLE_INSN
8298 used by the DFA insn scheduler. */
8301 ia64_dfa_pre_cycle_insn (void)
8303 return dfa_pre_cycle_insn;
8306 /* The following function returns TRUE if PRODUCER (of type ilog or
8307 ld) produces address for CONSUMER (of type st or stf). */
8310 ia64_st_address_bypass_p (rtx producer, rtx consumer)
8314 gcc_assert (producer && consumer);
8315 dest = ia64_single_set (producer);
8317 reg = SET_DEST (dest);
8319 if (GET_CODE (reg) == SUBREG)
8320 reg = SUBREG_REG (reg);
8321 gcc_assert (GET_CODE (reg) == REG);
8323 dest = ia64_single_set (consumer);
8325 mem = SET_DEST (dest);
8326 gcc_assert (mem && GET_CODE (mem) == MEM);
8327 return reg_mentioned_p (reg, mem);
8330 /* The following function returns TRUE if PRODUCER (of type ilog or
8331 ld) produces address for CONSUMER (of type ld or fld). */
8334 ia64_ld_address_bypass_p (rtx producer, rtx consumer)
8336 rtx dest, src, reg, mem;
8338 gcc_assert (producer && consumer);
8339 dest = ia64_single_set (producer);
8341 reg = SET_DEST (dest);
8343 if (GET_CODE (reg) == SUBREG)
8344 reg = SUBREG_REG (reg);
8345 gcc_assert (GET_CODE (reg) == REG);
8347 src = ia64_single_set (consumer);
8349 mem = SET_SRC (src);
8352 if (GET_CODE (mem) == UNSPEC && XVECLEN (mem, 0) > 0)
8353 mem = XVECEXP (mem, 0, 0);
8354 else if (GET_CODE (mem) == IF_THEN_ELSE)
8355 /* ??? Is this bypass necessary for ld.c? */
8357 gcc_assert (XINT (XEXP (XEXP (mem, 0), 0), 1) == UNSPEC_LDCCLR);
8358 mem = XEXP (mem, 1);
8361 while (GET_CODE (mem) == SUBREG || GET_CODE (mem) == ZERO_EXTEND)
8362 mem = XEXP (mem, 0);
8364 if (GET_CODE (mem) == UNSPEC)
8366 int c = XINT (mem, 1);
8368 gcc_assert (c == UNSPEC_LDA || c == UNSPEC_LDS || c == UNSPEC_LDSA);
8369 mem = XVECEXP (mem, 0, 0);
8372 /* Note that LO_SUM is used for GOT loads. */
8373 gcc_assert (GET_CODE (mem) == LO_SUM || GET_CODE (mem) == MEM);
8375 return reg_mentioned_p (reg, mem);
8378 /* The following function returns TRUE if INSN produces address for a
8379 load/store insn. We will place such insns into M slot because it
8380 decreases its latency time. */
8383 ia64_produce_address_p (rtx insn)
8389 /* Emit pseudo-ops for the assembler to describe predicate relations.
8390 At present this assumes that we only consider predicate pairs to
8391 be mutex, and that the assembler can deduce proper values from
8392 straight-line code. */
8395 emit_predicate_relation_info (void)
8399 FOR_EACH_BB_REVERSE (bb)
8402 rtx head = BB_HEAD (bb);
8404 /* We only need such notes at code labels. */
8405 if (GET_CODE (head) != CODE_LABEL)
8407 if (GET_CODE (NEXT_INSN (head)) == NOTE
8408 && NOTE_LINE_NUMBER (NEXT_INSN (head)) == NOTE_INSN_BASIC_BLOCK)
8409 head = NEXT_INSN (head);
8411 /* Skip p0, which may be thought to be live due to (reg:DI p0)
8412 grabbing the entire block of predicate registers. */
8413 for (r = PR_REG (2); r < PR_REG (64); r += 2)
8414 if (REGNO_REG_SET_P (bb->il.rtl->global_live_at_start, r))
8416 rtx p = gen_rtx_REG (BImode, r);
8417 rtx n = emit_insn_after (gen_pred_rel_mutex (p), head);
8418 if (head == BB_END (bb))
8424 /* Look for conditional calls that do not return, and protect predicate
8425 relations around them. Otherwise the assembler will assume the call
8426 returns, and complain about uses of call-clobbered predicates after
8428 FOR_EACH_BB_REVERSE (bb)
8430 rtx insn = BB_HEAD (bb);
8434 if (GET_CODE (insn) == CALL_INSN
8435 && GET_CODE (PATTERN (insn)) == COND_EXEC
8436 && find_reg_note (insn, REG_NORETURN, NULL_RTX))
8438 rtx b = emit_insn_before (gen_safe_across_calls_all (), insn);
8439 rtx a = emit_insn_after (gen_safe_across_calls_normal (), insn);
8440 if (BB_HEAD (bb) == insn)
8442 if (BB_END (bb) == insn)
8446 if (insn == BB_END (bb))
8448 insn = NEXT_INSN (insn);
8453 /* Perform machine dependent operations on the rtl chain INSNS. */
8458 /* We are freeing block_for_insn in the toplev to keep compatibility
8459 with old MDEP_REORGS that are not CFG based. Recompute it now. */
8460 compute_bb_for_insn ();
8462 /* If optimizing, we'll have split before scheduling. */
8464 split_all_insns (0);
8466 /* ??? update_life_info_in_dirty_blocks fails to terminate during
8467 non-optimizing bootstrap. */
8468 update_life_info (NULL, UPDATE_LIFE_GLOBAL_RM_NOTES, PROP_DEATH_NOTES);
8470 if (optimize && ia64_flag_schedule_insns2)
8472 timevar_push (TV_SCHED2);
8473 ia64_final_schedule = 1;
8475 initiate_bundle_states ();
8476 ia64_nop = make_insn_raw (gen_nop ());
8477 PREV_INSN (ia64_nop) = NEXT_INSN (ia64_nop) = NULL_RTX;
8478 recog_memoized (ia64_nop);
8479 clocks_length = get_max_uid () + 1;
8480 stops_p = xcalloc (1, clocks_length);
8481 if (ia64_tune == PROCESSOR_ITANIUM)
8483 clocks = xcalloc (clocks_length, sizeof (int));
8484 add_cycles = xcalloc (clocks_length, sizeof (int));
8486 if (ia64_tune == PROCESSOR_ITANIUM2)
8488 pos_1 = get_cpu_unit_code ("2_1");
8489 pos_2 = get_cpu_unit_code ("2_2");
8490 pos_3 = get_cpu_unit_code ("2_3");
8491 pos_4 = get_cpu_unit_code ("2_4");
8492 pos_5 = get_cpu_unit_code ("2_5");
8493 pos_6 = get_cpu_unit_code ("2_6");
8494 _0mii_ = get_cpu_unit_code ("2b_0mii.");
8495 _0mmi_ = get_cpu_unit_code ("2b_0mmi.");
8496 _0mfi_ = get_cpu_unit_code ("2b_0mfi.");
8497 _0mmf_ = get_cpu_unit_code ("2b_0mmf.");
8498 _0bbb_ = get_cpu_unit_code ("2b_0bbb.");
8499 _0mbb_ = get_cpu_unit_code ("2b_0mbb.");
8500 _0mib_ = get_cpu_unit_code ("2b_0mib.");
8501 _0mmb_ = get_cpu_unit_code ("2b_0mmb.");
8502 _0mfb_ = get_cpu_unit_code ("2b_0mfb.");
8503 _0mlx_ = get_cpu_unit_code ("2b_0mlx.");
8504 _1mii_ = get_cpu_unit_code ("2b_1mii.");
8505 _1mmi_ = get_cpu_unit_code ("2b_1mmi.");
8506 _1mfi_ = get_cpu_unit_code ("2b_1mfi.");
8507 _1mmf_ = get_cpu_unit_code ("2b_1mmf.");
8508 _1bbb_ = get_cpu_unit_code ("2b_1bbb.");
8509 _1mbb_ = get_cpu_unit_code ("2b_1mbb.");
8510 _1mib_ = get_cpu_unit_code ("2b_1mib.");
8511 _1mmb_ = get_cpu_unit_code ("2b_1mmb.");
8512 _1mfb_ = get_cpu_unit_code ("2b_1mfb.");
8513 _1mlx_ = get_cpu_unit_code ("2b_1mlx.");
8517 pos_1 = get_cpu_unit_code ("1_1");
8518 pos_2 = get_cpu_unit_code ("1_2");
8519 pos_3 = get_cpu_unit_code ("1_3");
8520 pos_4 = get_cpu_unit_code ("1_4");
8521 pos_5 = get_cpu_unit_code ("1_5");
8522 pos_6 = get_cpu_unit_code ("1_6");
8523 _0mii_ = get_cpu_unit_code ("1b_0mii.");
8524 _0mmi_ = get_cpu_unit_code ("1b_0mmi.");
8525 _0mfi_ = get_cpu_unit_code ("1b_0mfi.");
8526 _0mmf_ = get_cpu_unit_code ("1b_0mmf.");
8527 _0bbb_ = get_cpu_unit_code ("1b_0bbb.");
8528 _0mbb_ = get_cpu_unit_code ("1b_0mbb.");
8529 _0mib_ = get_cpu_unit_code ("1b_0mib.");
8530 _0mmb_ = get_cpu_unit_code ("1b_0mmb.");
8531 _0mfb_ = get_cpu_unit_code ("1b_0mfb.");
8532 _0mlx_ = get_cpu_unit_code ("1b_0mlx.");
8533 _1mii_ = get_cpu_unit_code ("1b_1mii.");
8534 _1mmi_ = get_cpu_unit_code ("1b_1mmi.");
8535 _1mfi_ = get_cpu_unit_code ("1b_1mfi.");
8536 _1mmf_ = get_cpu_unit_code ("1b_1mmf.");
8537 _1bbb_ = get_cpu_unit_code ("1b_1bbb.");
8538 _1mbb_ = get_cpu_unit_code ("1b_1mbb.");
8539 _1mib_ = get_cpu_unit_code ("1b_1mib.");
8540 _1mmb_ = get_cpu_unit_code ("1b_1mmb.");
8541 _1mfb_ = get_cpu_unit_code ("1b_1mfb.");
8542 _1mlx_ = get_cpu_unit_code ("1b_1mlx.");
8545 finish_bundle_states ();
8546 if (ia64_tune == PROCESSOR_ITANIUM)
8553 emit_insn_group_barriers (dump_file);
8555 ia64_final_schedule = 0;
8556 timevar_pop (TV_SCHED2);
8559 emit_all_insn_group_barriers (dump_file);
8561 /* A call must not be the last instruction in a function, so that the
8562 return address is still within the function, so that unwinding works
8563 properly. Note that IA-64 differs from dwarf2 on this point. */
8564 if (flag_unwind_tables || (flag_exceptions && !USING_SJLJ_EXCEPTIONS))
8569 insn = get_last_insn ();
8570 if (! INSN_P (insn))
8571 insn = prev_active_insn (insn);
8572 /* Skip over insns that expand to nothing. */
8573 while (GET_CODE (insn) == INSN && get_attr_empty (insn) == EMPTY_YES)
8575 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
8576 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
8578 insn = prev_active_insn (insn);
8580 if (GET_CODE (insn) == CALL_INSN)
8583 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
8584 emit_insn (gen_break_f ());
8585 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
8589 emit_predicate_relation_info ();
8591 if (ia64_flag_var_tracking)
8593 timevar_push (TV_VAR_TRACKING);
8594 variable_tracking_main ();
8595 timevar_pop (TV_VAR_TRACKING);
8599 /* Return true if REGNO is used by the epilogue. */
8602 ia64_epilogue_uses (int regno)
8607 /* With a call to a function in another module, we will write a new
8608 value to "gp". After returning from such a call, we need to make
8609 sure the function restores the original gp-value, even if the
8610 function itself does not use the gp anymore. */
8611 return !(TARGET_AUTO_PIC || TARGET_NO_PIC);
8613 case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3):
8614 case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7):
8615 /* For functions defined with the syscall_linkage attribute, all
8616 input registers are marked as live at all function exits. This
8617 prevents the register allocator from using the input registers,
8618 which in turn makes it possible to restart a system call after
8619 an interrupt without having to save/restore the input registers.
8620 This also prevents kernel data from leaking to application code. */
8621 return lookup_attribute ("syscall_linkage",
8622 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))) != NULL;
8625 /* Conditional return patterns can't represent the use of `b0' as
8626 the return address, so we force the value live this way. */
8630 /* Likewise for ar.pfs, which is used by br.ret. */
8638 /* Return true if REGNO is used by the frame unwinder. */
8641 ia64_eh_uses (int regno)
8643 if (! reload_completed)
8646 if (current_frame_info.reg_save_b0
8647 && regno == current_frame_info.reg_save_b0)
8649 if (current_frame_info.reg_save_pr
8650 && regno == current_frame_info.reg_save_pr)
8652 if (current_frame_info.reg_save_ar_pfs
8653 && regno == current_frame_info.reg_save_ar_pfs)
8655 if (current_frame_info.reg_save_ar_unat
8656 && regno == current_frame_info.reg_save_ar_unat)
8658 if (current_frame_info.reg_save_ar_lc
8659 && regno == current_frame_info.reg_save_ar_lc)
8665 /* Return true if this goes in small data/bss. */
8667 /* ??? We could also support own long data here. Generating movl/add/ld8
8668 instead of addl,ld8/ld8. This makes the code bigger, but should make the
8669 code faster because there is one less load. This also includes incomplete
8670 types which can't go in sdata/sbss. */
8673 ia64_in_small_data_p (tree exp)
8675 if (TARGET_NO_SDATA)
8678 /* We want to merge strings, so we never consider them small data. */
8679 if (TREE_CODE (exp) == STRING_CST)
8682 /* Functions are never small data. */
8683 if (TREE_CODE (exp) == FUNCTION_DECL)
8686 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
8688 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
8690 if (strcmp (section, ".sdata") == 0
8691 || strncmp (section, ".sdata.", 7) == 0
8692 || strncmp (section, ".gnu.linkonce.s.", 16) == 0
8693 || strcmp (section, ".sbss") == 0
8694 || strncmp (section, ".sbss.", 6) == 0
8695 || strncmp (section, ".gnu.linkonce.sb.", 17) == 0)
8700 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
8702 /* If this is an incomplete type with size 0, then we can't put it
8703 in sdata because it might be too big when completed. */
8704 if (size > 0 && size <= ia64_section_threshold)
8711 /* Output assembly directives for prologue regions. */
8713 /* The current basic block number. */
8715 static bool last_block;
8717 /* True if we need a copy_state command at the start of the next block. */
8719 static bool need_copy_state;
8721 #ifndef MAX_ARTIFICIAL_LABEL_BYTES
8722 # define MAX_ARTIFICIAL_LABEL_BYTES 30
8725 /* Emit a debugging label after a call-frame-related insn. We'd
8726 rather output the label right away, but we'd have to output it
8727 after, not before, the instruction, and the instruction has not
8728 been output yet. So we emit the label after the insn, delete it to
8729 avoid introducing basic blocks, and mark it as preserved, such that
8730 it is still output, given that it is referenced in debug info. */
8733 ia64_emit_deleted_label_after_insn (rtx insn)
8735 char label[MAX_ARTIFICIAL_LABEL_BYTES];
8736 rtx lb = gen_label_rtx ();
8737 rtx label_insn = emit_label_after (lb, insn);
8739 LABEL_PRESERVE_P (lb) = 1;
8741 delete_insn (label_insn);
8743 ASM_GENERATE_INTERNAL_LABEL (label, "L", CODE_LABEL_NUMBER (label_insn));
8745 return xstrdup (label);
8748 /* Define the CFA after INSN with the steady-state definition. */
8751 ia64_dwarf2out_def_steady_cfa (rtx insn)
8753 rtx fp = frame_pointer_needed
8754 ? hard_frame_pointer_rtx
8755 : stack_pointer_rtx;
8758 (ia64_emit_deleted_label_after_insn (insn),
8760 ia64_initial_elimination_offset
8761 (REGNO (arg_pointer_rtx), REGNO (fp))
8762 + ARG_POINTER_CFA_OFFSET (current_function_decl));
8765 /* The generic dwarf2 frame debug info generator does not define a
8766 separate region for the very end of the epilogue, so refrain from
8767 doing so in the IA64-specific code as well. */
8769 #define IA64_CHANGE_CFA_IN_EPILOGUE 0
8771 /* The function emits unwind directives for the start of an epilogue. */
8774 process_epilogue (FILE *asm_out_file, rtx insn, bool unwind, bool frame)
8776 /* If this isn't the last block of the function, then we need to label the
8777 current state, and copy it back in at the start of the next block. */
8782 fprintf (asm_out_file, "\t.label_state %d\n",
8783 ++cfun->machine->state_num);
8784 need_copy_state = true;
8788 fprintf (asm_out_file, "\t.restore sp\n");
8789 if (IA64_CHANGE_CFA_IN_EPILOGUE && frame)
8790 dwarf2out_def_cfa (ia64_emit_deleted_label_after_insn (insn),
8791 STACK_POINTER_REGNUM, INCOMING_FRAME_SP_OFFSET);
8794 /* This function processes a SET pattern looking for specific patterns
8795 which result in emitting an assembly directive required for unwinding. */
8798 process_set (FILE *asm_out_file, rtx pat, rtx insn, bool unwind, bool frame)
8800 rtx src = SET_SRC (pat);
8801 rtx dest = SET_DEST (pat);
8802 int src_regno, dest_regno;
8804 /* Look for the ALLOC insn. */
8805 if (GET_CODE (src) == UNSPEC_VOLATILE
8806 && XINT (src, 1) == UNSPECV_ALLOC
8807 && GET_CODE (dest) == REG)
8809 dest_regno = REGNO (dest);
8811 /* If this is the final destination for ar.pfs, then this must
8812 be the alloc in the prologue. */
8813 if (dest_regno == current_frame_info.reg_save_ar_pfs)
8816 fprintf (asm_out_file, "\t.save ar.pfs, r%d\n",
8817 ia64_dbx_register_number (dest_regno));
8821 /* This must be an alloc before a sibcall. We must drop the
8822 old frame info. The easiest way to drop the old frame
8823 info is to ensure we had a ".restore sp" directive
8824 followed by a new prologue. If the procedure doesn't
8825 have a memory-stack frame, we'll issue a dummy ".restore
8827 if (current_frame_info.total_size == 0 && !frame_pointer_needed)
8828 /* if haven't done process_epilogue() yet, do it now */
8829 process_epilogue (asm_out_file, insn, unwind, frame);
8831 fprintf (asm_out_file, "\t.prologue\n");
8836 /* Look for SP = .... */
8837 if (GET_CODE (dest) == REG && REGNO (dest) == STACK_POINTER_REGNUM)
8839 if (GET_CODE (src) == PLUS)
8841 rtx op0 = XEXP (src, 0);
8842 rtx op1 = XEXP (src, 1);
8844 gcc_assert (op0 == dest && GET_CODE (op1) == CONST_INT);
8846 if (INTVAL (op1) < 0)
8848 gcc_assert (!frame_pointer_needed);
8850 fprintf (asm_out_file, "\t.fframe "HOST_WIDE_INT_PRINT_DEC"\n",
8853 ia64_dwarf2out_def_steady_cfa (insn);
8856 process_epilogue (asm_out_file, insn, unwind, frame);
8860 gcc_assert (GET_CODE (src) == REG
8861 && REGNO (src) == HARD_FRAME_POINTER_REGNUM);
8862 process_epilogue (asm_out_file, insn, unwind, frame);
8868 /* Register move we need to look at. */
8869 if (GET_CODE (dest) == REG && GET_CODE (src) == REG)
8871 src_regno = REGNO (src);
8872 dest_regno = REGNO (dest);
8877 /* Saving return address pointer. */
8878 gcc_assert (dest_regno == current_frame_info.reg_save_b0);
8880 fprintf (asm_out_file, "\t.save rp, r%d\n",
8881 ia64_dbx_register_number (dest_regno));
8885 gcc_assert (dest_regno == current_frame_info.reg_save_pr);
8887 fprintf (asm_out_file, "\t.save pr, r%d\n",
8888 ia64_dbx_register_number (dest_regno));
8891 case AR_UNAT_REGNUM:
8892 gcc_assert (dest_regno == current_frame_info.reg_save_ar_unat);
8894 fprintf (asm_out_file, "\t.save ar.unat, r%d\n",
8895 ia64_dbx_register_number (dest_regno));
8899 gcc_assert (dest_regno == current_frame_info.reg_save_ar_lc);
8901 fprintf (asm_out_file, "\t.save ar.lc, r%d\n",
8902 ia64_dbx_register_number (dest_regno));
8905 case STACK_POINTER_REGNUM:
8906 gcc_assert (dest_regno == HARD_FRAME_POINTER_REGNUM
8907 && frame_pointer_needed);
8909 fprintf (asm_out_file, "\t.vframe r%d\n",
8910 ia64_dbx_register_number (dest_regno));
8912 ia64_dwarf2out_def_steady_cfa (insn);
8916 /* Everything else should indicate being stored to memory. */
8921 /* Memory store we need to look at. */
8922 if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
8928 if (GET_CODE (XEXP (dest, 0)) == REG)
8930 base = XEXP (dest, 0);
8935 gcc_assert (GET_CODE (XEXP (dest, 0)) == PLUS
8936 && GET_CODE (XEXP (XEXP (dest, 0), 1)) == CONST_INT);
8937 base = XEXP (XEXP (dest, 0), 0);
8938 off = INTVAL (XEXP (XEXP (dest, 0), 1));
8941 if (base == hard_frame_pointer_rtx)
8943 saveop = ".savepsp";
8948 gcc_assert (base == stack_pointer_rtx);
8952 src_regno = REGNO (src);
8956 gcc_assert (!current_frame_info.reg_save_b0);
8958 fprintf (asm_out_file, "\t%s rp, %ld\n", saveop, off);
8962 gcc_assert (!current_frame_info.reg_save_pr);
8964 fprintf (asm_out_file, "\t%s pr, %ld\n", saveop, off);
8968 gcc_assert (!current_frame_info.reg_save_ar_lc);
8970 fprintf (asm_out_file, "\t%s ar.lc, %ld\n", saveop, off);
8974 gcc_assert (!current_frame_info.reg_save_ar_pfs);
8976 fprintf (asm_out_file, "\t%s ar.pfs, %ld\n", saveop, off);
8979 case AR_UNAT_REGNUM:
8980 gcc_assert (!current_frame_info.reg_save_ar_unat);
8982 fprintf (asm_out_file, "\t%s ar.unat, %ld\n", saveop, off);
8990 fprintf (asm_out_file, "\t.save.g 0x%x\n",
8991 1 << (src_regno - GR_REG (4)));
9000 fprintf (asm_out_file, "\t.save.b 0x%x\n",
9001 1 << (src_regno - BR_REG (1)));
9009 fprintf (asm_out_file, "\t.save.f 0x%x\n",
9010 1 << (src_regno - FR_REG (2)));
9013 case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19):
9014 case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23):
9015 case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27):
9016 case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31):
9018 fprintf (asm_out_file, "\t.save.gf 0x0, 0x%x\n",
9019 1 << (src_regno - FR_REG (12)));
9031 /* This function looks at a single insn and emits any directives
9032 required to unwind this insn. */
9034 process_for_unwind_directive (FILE *asm_out_file, rtx insn)
9036 bool unwind = (flag_unwind_tables
9037 || (flag_exceptions && !USING_SJLJ_EXCEPTIONS));
9038 bool frame = dwarf2out_do_frame ();
9040 if (unwind || frame)
9044 if (GET_CODE (insn) == NOTE
9045 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_BASIC_BLOCK)
9047 last_block = NOTE_BASIC_BLOCK (insn)->next_bb == EXIT_BLOCK_PTR;
9049 /* Restore unwind state from immediately before the epilogue. */
9050 if (need_copy_state)
9054 fprintf (asm_out_file, "\t.body\n");
9055 fprintf (asm_out_file, "\t.copy_state %d\n",
9056 cfun->machine->state_num);
9058 if (IA64_CHANGE_CFA_IN_EPILOGUE && frame)
9059 ia64_dwarf2out_def_steady_cfa (insn);
9060 need_copy_state = false;
9064 if (GET_CODE (insn) == NOTE || ! RTX_FRAME_RELATED_P (insn))
9067 pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX);
9069 pat = XEXP (pat, 0);
9071 pat = PATTERN (insn);
9073 switch (GET_CODE (pat))
9076 process_set (asm_out_file, pat, insn, unwind, frame);
9082 int limit = XVECLEN (pat, 0);
9083 for (par_index = 0; par_index < limit; par_index++)
9085 rtx x = XVECEXP (pat, 0, par_index);
9086 if (GET_CODE (x) == SET)
9087 process_set (asm_out_file, x, insn, unwind, frame);
9102 IA64_BUILTIN_FLUSHRS
9106 ia64_init_builtins (void)
9111 /* The __fpreg type. */
9112 fpreg_type = make_node (REAL_TYPE);
9113 TYPE_PRECISION (fpreg_type) = 82;
9114 layout_type (fpreg_type);
9115 (*lang_hooks.types.register_builtin_type) (fpreg_type, "__fpreg");
9117 /* The __float80 type. */
9118 float80_type = make_node (REAL_TYPE);
9119 TYPE_PRECISION (float80_type) = 80;
9120 layout_type (float80_type);
9121 (*lang_hooks.types.register_builtin_type) (float80_type, "__float80");
9123 /* The __float128 type. */
9126 tree float128_type = make_node (REAL_TYPE);
9127 TYPE_PRECISION (float128_type) = 128;
9128 layout_type (float128_type);
9129 (*lang_hooks.types.register_builtin_type) (float128_type, "__float128");
9132 /* Under HPUX, this is a synonym for "long double". */
9133 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
9136 #define def_builtin(name, type, code) \
9137 add_builtin_function ((name), (type), (code), BUILT_IN_MD, \
9140 def_builtin ("__builtin_ia64_bsp",
9141 build_function_type (ptr_type_node, void_list_node),
9144 def_builtin ("__builtin_ia64_flushrs",
9145 build_function_type (void_type_node, void_list_node),
9146 IA64_BUILTIN_FLUSHRS);
9152 ia64_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
9153 enum machine_mode mode ATTRIBUTE_UNUSED,
9154 int ignore ATTRIBUTE_UNUSED)
9156 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
9157 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
9161 case IA64_BUILTIN_BSP:
9162 if (! target || ! register_operand (target, DImode))
9163 target = gen_reg_rtx (DImode);
9164 emit_insn (gen_bsp_value (target));
9165 #ifdef POINTERS_EXTEND_UNSIGNED
9166 target = convert_memory_address (ptr_mode, target);
9170 case IA64_BUILTIN_FLUSHRS:
9171 emit_insn (gen_flushrs ());
9181 /* For the HP-UX IA64 aggregate parameters are passed stored in the
9182 most significant bits of the stack slot. */
9185 ia64_hpux_function_arg_padding (enum machine_mode mode, tree type)
9187 /* Exception to normal case for structures/unions/etc. */
9189 if (type && AGGREGATE_TYPE_P (type)
9190 && int_size_in_bytes (type) < UNITS_PER_WORD)
9193 /* Fall back to the default. */
9194 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
9197 /* Emit text to declare externally defined variables and functions, because
9198 the Intel assembler does not support undefined externals. */
9201 ia64_asm_output_external (FILE *file, tree decl, const char *name)
9203 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
9204 set in order to avoid putting out names that are never really
9206 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
9208 /* maybe_assemble_visibility will return 1 if the assembler
9209 visibility directive is output. */
9210 int need_visibility = ((*targetm.binds_local_p) (decl)
9211 && maybe_assemble_visibility (decl));
9213 /* GNU as does not need anything here, but the HP linker does
9214 need something for external functions. */
9215 if ((TARGET_HPUX_LD || !TARGET_GNU_AS)
9216 && TREE_CODE (decl) == FUNCTION_DECL)
9217 (*targetm.asm_out.globalize_decl_name) (file, decl);
9218 else if (need_visibility && !TARGET_GNU_AS)
9219 (*targetm.asm_out.globalize_label) (file, name);
9223 /* Set SImode div/mod functions, init_integral_libfuncs only initializes
9224 modes of word_mode and larger. Rename the TFmode libfuncs using the
9225 HPUX conventions. __divtf3 is used for XFmode. We need to keep it for
9226 backward compatibility. */
9229 ia64_init_libfuncs (void)
9231 set_optab_libfunc (sdiv_optab, SImode, "__divsi3");
9232 set_optab_libfunc (udiv_optab, SImode, "__udivsi3");
9233 set_optab_libfunc (smod_optab, SImode, "__modsi3");
9234 set_optab_libfunc (umod_optab, SImode, "__umodsi3");
9236 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
9237 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
9238 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
9239 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
9240 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
9242 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
9243 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
9244 set_conv_libfunc (sext_optab, TFmode, XFmode, "_U_Qfcnvff_f80_to_quad");
9245 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
9246 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
9247 set_conv_libfunc (trunc_optab, XFmode, TFmode, "_U_Qfcnvff_quad_to_f80");
9249 set_conv_libfunc (sfix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_sgl");
9250 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
9251 set_conv_libfunc (sfix_optab, TImode, TFmode, "_U_Qfcnvfxt_quad_to_quad");
9252 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxut_quad_to_sgl");
9253 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxut_quad_to_dbl");
9255 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
9256 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
9257 set_conv_libfunc (sfloat_optab, TFmode, TImode, "_U_Qfcnvxf_quad_to_quad");
9258 /* HP-UX 11.23 libc does not have a function for unsigned
9259 SImode-to-TFmode conversion. */
9260 set_conv_libfunc (ufloat_optab, TFmode, DImode, "_U_Qfcnvxuf_dbl_to_quad");
9263 /* Rename all the TFmode libfuncs using the HPUX conventions. */
9266 ia64_hpux_init_libfuncs (void)
9268 ia64_init_libfuncs ();
9270 /* The HP SI millicode division and mod functions expect DI arguments.
9271 By turning them off completely we avoid using both libgcc and the
9272 non-standard millicode routines and use the HP DI millicode routines
9275 set_optab_libfunc (sdiv_optab, SImode, 0);
9276 set_optab_libfunc (udiv_optab, SImode, 0);
9277 set_optab_libfunc (smod_optab, SImode, 0);
9278 set_optab_libfunc (umod_optab, SImode, 0);
9280 set_optab_libfunc (sdiv_optab, DImode, "__milli_divI");
9281 set_optab_libfunc (udiv_optab, DImode, "__milli_divU");
9282 set_optab_libfunc (smod_optab, DImode, "__milli_remI");
9283 set_optab_libfunc (umod_optab, DImode, "__milli_remU");
9285 /* HP-UX libc has TF min/max/abs routines in it. */
9286 set_optab_libfunc (smin_optab, TFmode, "_U_Qfmin");
9287 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
9288 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
9290 /* ia64_expand_compare uses this. */
9291 cmptf_libfunc = init_one_libfunc ("_U_Qfcmp");
9293 /* These should never be used. */
9294 set_optab_libfunc (eq_optab, TFmode, 0);
9295 set_optab_libfunc (ne_optab, TFmode, 0);
9296 set_optab_libfunc (gt_optab, TFmode, 0);
9297 set_optab_libfunc (ge_optab, TFmode, 0);
9298 set_optab_libfunc (lt_optab, TFmode, 0);
9299 set_optab_libfunc (le_optab, TFmode, 0);
9302 /* Rename the division and modulus functions in VMS. */
9305 ia64_vms_init_libfuncs (void)
9307 set_optab_libfunc (sdiv_optab, SImode, "OTS$DIV_I");
9308 set_optab_libfunc (sdiv_optab, DImode, "OTS$DIV_L");
9309 set_optab_libfunc (udiv_optab, SImode, "OTS$DIV_UI");
9310 set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL");
9311 set_optab_libfunc (smod_optab, SImode, "OTS$REM_I");
9312 set_optab_libfunc (smod_optab, DImode, "OTS$REM_L");
9313 set_optab_libfunc (umod_optab, SImode, "OTS$REM_UI");
9314 set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL");
9317 /* Rename the TFmode libfuncs available from soft-fp in glibc using
9318 the HPUX conventions. */
9321 ia64_sysv4_init_libfuncs (void)
9323 ia64_init_libfuncs ();
9325 /* These functions are not part of the HPUX TFmode interface. We
9326 use them instead of _U_Qfcmp, which doesn't work the way we
9328 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
9329 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
9330 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
9331 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
9332 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
9333 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
9335 /* We leave out _U_Qfmin, _U_Qfmax and _U_Qfabs since soft-fp in
9336 glibc doesn't have them. */
9339 /* Return the section to use for X. The only special thing we do here
9340 is to honor small data. */
9343 ia64_select_rtx_section (enum machine_mode mode, rtx x,
9344 unsigned HOST_WIDE_INT align)
9346 if (GET_MODE_SIZE (mode) > 0
9347 && GET_MODE_SIZE (mode) <= ia64_section_threshold
9348 && !TARGET_NO_SDATA)
9349 return sdata_section;
9351 return default_elf_select_rtx_section (mode, x, align);
9354 /* It is illegal to have relocations in shared segments on AIX and HPUX.
9355 Pretend flag_pic is always set. */
9358 ia64_rwreloc_select_section (tree exp, int reloc, unsigned HOST_WIDE_INT align)
9360 return default_elf_select_section_1 (exp, reloc, align, true);
9364 ia64_rwreloc_unique_section (tree decl, int reloc)
9366 default_unique_section_1 (decl, reloc, true);
9370 ia64_rwreloc_select_rtx_section (enum machine_mode mode, rtx x,
9371 unsigned HOST_WIDE_INT align)
9374 int save_pic = flag_pic;
9376 sect = ia64_select_rtx_section (mode, x, align);
9377 flag_pic = save_pic;
9381 #ifndef TARGET_RWRELOC
9382 #define TARGET_RWRELOC flag_pic
9386 ia64_section_type_flags (tree decl, const char *name, int reloc)
9388 unsigned int flags = 0;
9390 if (strcmp (name, ".sdata") == 0
9391 || strncmp (name, ".sdata.", 7) == 0
9392 || strncmp (name, ".gnu.linkonce.s.", 16) == 0
9393 || strncmp (name, ".sdata2.", 8) == 0
9394 || strncmp (name, ".gnu.linkonce.s2.", 17) == 0
9395 || strcmp (name, ".sbss") == 0
9396 || strncmp (name, ".sbss.", 6) == 0
9397 || strncmp (name, ".gnu.linkonce.sb.", 17) == 0)
9398 flags = SECTION_SMALL;
9400 flags |= default_section_type_flags_1 (decl, name, reloc, TARGET_RWRELOC);
9404 /* Returns true if FNTYPE (a FUNCTION_TYPE or a METHOD_TYPE) returns a
9405 structure type and that the address of that type should be passed
9406 in out0, rather than in r8. */
9409 ia64_struct_retval_addr_is_first_parm_p (tree fntype)
9411 tree ret_type = TREE_TYPE (fntype);
9413 /* The Itanium C++ ABI requires that out0, rather than r8, be used
9414 as the structure return address parameter, if the return value
9415 type has a non-trivial copy constructor or destructor. It is not
9416 clear if this same convention should be used for other
9417 programming languages. Until G++ 3.4, we incorrectly used r8 for
9418 these return values. */
9419 return (abi_version_at_least (2)
9421 && TYPE_MODE (ret_type) == BLKmode
9422 && TREE_ADDRESSABLE (ret_type)
9423 && strcmp (lang_hooks.name, "GNU C++") == 0);
9426 /* Output the assembler code for a thunk function. THUNK_DECL is the
9427 declaration for the thunk function itself, FUNCTION is the decl for
9428 the target function. DELTA is an immediate constant offset to be
9429 added to THIS. If VCALL_OFFSET is nonzero, the word at
9430 *(*this + vcall_offset) should be added to THIS. */
9433 ia64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
9434 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
9437 rtx this, insn, funexp;
9438 unsigned int this_parmno;
9439 unsigned int this_regno;
9441 reload_completed = 1;
9442 epilogue_completed = 1;
9444 reset_block_changes ();
9446 /* Set things up as ia64_expand_prologue might. */
9447 last_scratch_gr_reg = 15;
9449 memset (¤t_frame_info, 0, sizeof (current_frame_info));
9450 current_frame_info.spill_cfa_off = -16;
9451 current_frame_info.n_input_regs = 1;
9452 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
9454 /* Mark the end of the (empty) prologue. */
9455 emit_note (NOTE_INSN_PROLOGUE_END);
9457 /* Figure out whether "this" will be the first parameter (the
9458 typical case) or the second parameter (as happens when the
9459 virtual function returns certain class objects). */
9461 = (ia64_struct_retval_addr_is_first_parm_p (TREE_TYPE (thunk))
9463 this_regno = IN_REG (this_parmno);
9464 if (!TARGET_REG_NAMES)
9465 reg_names[this_regno] = ia64_reg_numbers[this_parmno];
9467 this = gen_rtx_REG (Pmode, this_regno);
9470 rtx tmp = gen_rtx_REG (ptr_mode, this_regno);
9471 REG_POINTER (tmp) = 1;
9472 if (delta && CONST_OK_FOR_I (delta))
9474 emit_insn (gen_ptr_extend_plus_imm (this, tmp, GEN_INT (delta)));
9478 emit_insn (gen_ptr_extend (this, tmp));
9481 /* Apply the constant offset, if required. */
9484 rtx delta_rtx = GEN_INT (delta);
9486 if (!CONST_OK_FOR_I (delta))
9488 rtx tmp = gen_rtx_REG (Pmode, 2);
9489 emit_move_insn (tmp, delta_rtx);
9492 emit_insn (gen_adddi3 (this, this, delta_rtx));
9495 /* Apply the offset from the vtable, if required. */
9498 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
9499 rtx tmp = gen_rtx_REG (Pmode, 2);
9503 rtx t = gen_rtx_REG (ptr_mode, 2);
9504 REG_POINTER (t) = 1;
9505 emit_move_insn (t, gen_rtx_MEM (ptr_mode, this));
9506 if (CONST_OK_FOR_I (vcall_offset))
9508 emit_insn (gen_ptr_extend_plus_imm (tmp, t,
9513 emit_insn (gen_ptr_extend (tmp, t));
9516 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
9520 if (!CONST_OK_FOR_J (vcall_offset))
9522 rtx tmp2 = gen_rtx_REG (Pmode, next_scratch_gr_reg ());
9523 emit_move_insn (tmp2, vcall_offset_rtx);
9524 vcall_offset_rtx = tmp2;
9526 emit_insn (gen_adddi3 (tmp, tmp, vcall_offset_rtx));
9530 emit_move_insn (gen_rtx_REG (ptr_mode, 2),
9531 gen_rtx_MEM (ptr_mode, tmp));
9533 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
9535 emit_insn (gen_adddi3 (this, this, tmp));
9538 /* Generate a tail call to the target function. */
9539 if (! TREE_USED (function))
9541 assemble_external (function);
9542 TREE_USED (function) = 1;
9544 funexp = XEXP (DECL_RTL (function), 0);
9545 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
9546 ia64_expand_call (NULL_RTX, funexp, NULL_RTX, 1);
9547 insn = get_last_insn ();
9548 SIBLING_CALL_P (insn) = 1;
9550 /* Code generation for calls relies on splitting. */
9551 reload_completed = 1;
9552 epilogue_completed = 1;
9553 try_split (PATTERN (insn), insn, 0);
9557 /* Run just enough of rest_of_compilation to get the insns emitted.
9558 There's not really enough bulk here to make other passes such as
9559 instruction scheduling worth while. Note that use_thunk calls
9560 assemble_start_function and assemble_end_function. */
9562 insn_locators_initialize ();
9563 emit_all_insn_group_barriers (NULL);
9564 insn = get_insns ();
9565 shorten_branches (insn);
9566 final_start_function (insn, file, 1);
9567 final (insn, file, 1);
9568 final_end_function ();
9570 reload_completed = 0;
9571 epilogue_completed = 0;
9575 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9578 ia64_struct_value_rtx (tree fntype,
9579 int incoming ATTRIBUTE_UNUSED)
9581 if (fntype && ia64_struct_retval_addr_is_first_parm_p (fntype))
9583 return gen_rtx_REG (Pmode, GR_REG (8));
9587 ia64_scalar_mode_supported_p (enum machine_mode mode)
9613 ia64_vector_mode_supported_p (enum machine_mode mode)
9630 /* Implement the FUNCTION_PROFILER macro. */
9633 ia64_output_function_profiler (FILE *file, int labelno)
9637 /* If the function needs a static chain and the static chain
9638 register is r15, we use an indirect call so as to bypass
9639 the PLT stub in case the executable is dynamically linked,
9640 because the stub clobbers r15 as per 5.3.6 of the psABI.
9641 We don't need to do that in non canonical PIC mode. */
9643 if (cfun->static_chain_decl && !TARGET_NO_PIC && !TARGET_AUTO_PIC)
9645 gcc_assert (STATIC_CHAIN_REGNUM == 15);
9646 indirect_call = true;
9649 indirect_call = false;
9652 fputs ("\t.prologue 4, r40\n", file);
9654 fputs ("\t.prologue\n\t.save ar.pfs, r40\n", file);
9655 fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", file);
9657 if (NO_PROFILE_COUNTERS)
9658 fputs ("\tmov out3 = r0\n", file);
9662 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
9664 if (TARGET_AUTO_PIC)
9665 fputs ("\tmovl out3 = @gprel(", file);
9667 fputs ("\taddl out3 = @ltoff(", file);
9668 assemble_name (file, buf);
9669 if (TARGET_AUTO_PIC)
9670 fputs (")\n", file);
9672 fputs ("), r1\n", file);
9676 fputs ("\taddl r14 = @ltoff(@fptr(_mcount)), r1\n", file);
9677 fputs ("\t;;\n", file);
9679 fputs ("\t.save rp, r42\n", file);
9680 fputs ("\tmov out2 = b0\n", file);
9682 fputs ("\tld8 r14 = [r14]\n\t;;\n", file);
9683 fputs ("\t.body\n", file);
9684 fputs ("\tmov out1 = r1\n", file);
9687 fputs ("\tld8 r16 = [r14], 8\n\t;;\n", file);
9688 fputs ("\tmov b6 = r16\n", file);
9689 fputs ("\tld8 r1 = [r14]\n", file);
9690 fputs ("\tbr.call.sptk.many b0 = b6\n\t;;\n", file);
9693 fputs ("\tbr.call.sptk.many b0 = _mcount\n\t;;\n", file);
9696 static GTY(()) rtx mcount_func_rtx;
9698 gen_mcount_func_rtx (void)
9700 if (!mcount_func_rtx)
9701 mcount_func_rtx = init_one_libfunc ("_mcount");
9702 return mcount_func_rtx;
9706 ia64_profile_hook (int labelno)
9710 if (NO_PROFILE_COUNTERS)
9715 const char *label_name;
9716 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
9717 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
9718 label = gen_rtx_SYMBOL_REF (Pmode, label_name);
9719 SYMBOL_REF_FLAGS (label) = SYMBOL_FLAG_LOCAL;
9721 ip = gen_reg_rtx (Pmode);
9722 emit_insn (gen_ip_value (ip));
9723 emit_library_call (gen_mcount_func_rtx (), LCT_NORMAL,
9725 gen_rtx_REG (Pmode, BR_REG (0)), Pmode,
9730 /* Return the mangling of TYPE if it is an extended fundamental type. */
9733 ia64_mangle_fundamental_type (tree type)
9735 /* On HP-UX, "long double" is mangled as "e" so __float128 is
9737 if (!TARGET_HPUX && TYPE_MODE (type) == TFmode)
9739 /* On HP-UX, "e" is not available as a mangling of __float80 so use
9740 an extended mangling. Elsewhere, "e" is available since long
9741 double is 80 bits. */
9742 if (TYPE_MODE (type) == XFmode)
9743 return TARGET_HPUX ? "u9__float80" : "e";
9744 if (TYPE_MODE (type) == RFmode)
9749 /* Return the diagnostic message string if conversion from FROMTYPE to
9750 TOTYPE is not allowed, NULL otherwise. */
9752 ia64_invalid_conversion (tree fromtype, tree totype)
9754 /* Reject nontrivial conversion to or from __fpreg. */
9755 if (TYPE_MODE (fromtype) == RFmode
9756 && TYPE_MODE (totype) != RFmode
9757 && TYPE_MODE (totype) != VOIDmode)
9758 return N_("invalid conversion from %<__fpreg%>");
9759 if (TYPE_MODE (totype) == RFmode
9760 && TYPE_MODE (fromtype) != RFmode)
9761 return N_("invalid conversion to %<__fpreg%>");
9765 /* Return the diagnostic message string if the unary operation OP is
9766 not permitted on TYPE, NULL otherwise. */
9768 ia64_invalid_unary_op (int op, tree type)
9770 /* Reject operations on __fpreg other than unary + or &. */
9771 if (TYPE_MODE (type) == RFmode
9772 && op != CONVERT_EXPR
9774 return N_("invalid operation on %<__fpreg%>");
9778 /* Return the diagnostic message string if the binary operation OP is
9779 not permitted on TYPE1 and TYPE2, NULL otherwise. */
9781 ia64_invalid_binary_op (int op ATTRIBUTE_UNUSED, tree type1, tree type2)
9783 /* Reject operations on __fpreg. */
9784 if (TYPE_MODE (type1) == RFmode || TYPE_MODE (type2) == RFmode)
9785 return N_("invalid operation on %<__fpreg%>");
9789 /* Implement overriding of the optimization options. */
9791 ia64_optimization_options (int level ATTRIBUTE_UNUSED,
9792 int size ATTRIBUTE_UNUSED)
9794 /* Let the scheduler form additional regions. */
9795 set_param_value ("max-sched-extend-regions-iters", 2);
9797 /* Set the default values for cache-related parameters. */
9798 set_param_value ("simultaneous-prefetches", 6);
9799 set_param_value ("l1-cache-line-size", 32);
9803 /* HP-UX version_id attribute.
9804 For object foo, if the version_id is set to 1234 put out an alias
9805 of '.alias foo "foo{1234}" We can't use "foo{1234}" in anything
9806 other than an alias statement because it is an illegal symbol name. */
9809 ia64_handle_version_id_attribute (tree *node ATTRIBUTE_UNUSED,
9810 tree name ATTRIBUTE_UNUSED,
9812 int flags ATTRIBUTE_UNUSED,
9815 tree arg = TREE_VALUE (args);
9817 if (TREE_CODE (arg) != STRING_CST)
9819 error("version attribute is not a string");
9820 *no_add_attrs = true;
9826 #include "gt-ia64.h"