1 /* Definitions of target machine for GNU compiler.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
3 Free Software Foundation, Inc.
4 Contributed by James E. Wilson <wilson@cygnus.com> and
5 David Mosberger <davidm@hpl.hp.com>.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
22 Boston, MA 02110-1301, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
46 #include "sched-int.h"
49 #include "target-def.h"
52 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "tree-gimple.h"
59 /* This is used for communication between ASM_OUTPUT_LABEL and
60 ASM_OUTPUT_LABELREF. */
61 int ia64_asm_output_label = 0;
63 /* Define the information needed to generate branch and scc insns. This is
64 stored from the compare operation. */
65 struct rtx_def * ia64_compare_op0;
66 struct rtx_def * ia64_compare_op1;
68 /* Register names for ia64_expand_prologue. */
69 static const char * const ia64_reg_numbers[96] =
70 { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
71 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
72 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
73 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
74 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
75 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
76 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
77 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
78 "r96", "r97", "r98", "r99", "r100","r101","r102","r103",
79 "r104","r105","r106","r107","r108","r109","r110","r111",
80 "r112","r113","r114","r115","r116","r117","r118","r119",
81 "r120","r121","r122","r123","r124","r125","r126","r127"};
83 /* ??? These strings could be shared with REGISTER_NAMES. */
84 static const char * const ia64_input_reg_names[8] =
85 { "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7" };
87 /* ??? These strings could be shared with REGISTER_NAMES. */
88 static const char * const ia64_local_reg_names[80] =
89 { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7",
90 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15",
91 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23",
92 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31",
93 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39",
94 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47",
95 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55",
96 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63",
97 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71",
98 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" };
100 /* ??? These strings could be shared with REGISTER_NAMES. */
101 static const char * const ia64_output_reg_names[8] =
102 { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" };
104 /* Which cpu are we scheduling for. */
105 enum processor_type ia64_tune = PROCESSOR_ITANIUM2;
107 /* Determines whether we run our final scheduling pass or not. We always
108 avoid the normal second scheduling pass. */
109 static int ia64_flag_schedule_insns2;
111 /* Determines whether we run variable tracking in machine dependent
113 static int ia64_flag_var_tracking;
115 /* Variables which are this size or smaller are put in the sdata/sbss
118 unsigned int ia64_section_threshold;
120 /* The following variable is used by the DFA insn scheduler. The value is
121 TRUE if we do insn bundling instead of insn scheduling. */
124 /* Structure to be filled in by ia64_compute_frame_size with register
125 save masks and offsets for the current function. */
127 struct ia64_frame_info
129 HOST_WIDE_INT total_size; /* size of the stack frame, not including
130 the caller's scratch area. */
131 HOST_WIDE_INT spill_cfa_off; /* top of the reg spill area from the cfa. */
132 HOST_WIDE_INT spill_size; /* size of the gr/br/fr spill area. */
133 HOST_WIDE_INT extra_spill_size; /* size of spill area for others. */
134 HARD_REG_SET mask; /* mask of saved registers. */
135 unsigned int gr_used_mask; /* mask of registers in use as gr spill
136 registers or long-term scratches. */
137 int n_spilled; /* number of spilled registers. */
138 int reg_fp; /* register for fp. */
139 int reg_save_b0; /* save register for b0. */
140 int reg_save_pr; /* save register for prs. */
141 int reg_save_ar_pfs; /* save register for ar.pfs. */
142 int reg_save_ar_unat; /* save register for ar.unat. */
143 int reg_save_ar_lc; /* save register for ar.lc. */
144 int reg_save_gp; /* save register for gp. */
145 int n_input_regs; /* number of input registers used. */
146 int n_local_regs; /* number of local registers used. */
147 int n_output_regs; /* number of output registers used. */
148 int n_rotate_regs; /* number of rotating registers used. */
150 char need_regstk; /* true if a .regstk directive needed. */
151 char initialized; /* true if the data is finalized. */
154 /* Current frame information calculated by ia64_compute_frame_size. */
155 static struct ia64_frame_info current_frame_info;
157 static int ia64_first_cycle_multipass_dfa_lookahead (void);
158 static void ia64_dependencies_evaluation_hook (rtx, rtx);
159 static void ia64_init_dfa_pre_cycle_insn (void);
160 static rtx ia64_dfa_pre_cycle_insn (void);
161 static int ia64_first_cycle_multipass_dfa_lookahead_guard (rtx);
162 static bool ia64_first_cycle_multipass_dfa_lookahead_guard_spec (rtx);
163 static int ia64_dfa_new_cycle (FILE *, int, rtx, int, int, int *);
164 static void ia64_h_i_d_extended (void);
165 static int ia64_mode_to_int (enum machine_mode);
166 static void ia64_set_sched_flags (spec_info_t);
167 static int ia64_speculate_insn (rtx, ds_t, rtx *);
168 static rtx ia64_gen_spec_insn (rtx, ds_t, int, bool, bool);
169 static bool ia64_needs_block_p (rtx);
170 static rtx ia64_gen_check (rtx, rtx, bool);
171 static int ia64_spec_check_p (rtx);
172 static int ia64_spec_check_src_p (rtx);
173 static rtx gen_tls_get_addr (void);
174 static rtx gen_thread_pointer (void);
175 static int find_gr_spill (int);
176 static int next_scratch_gr_reg (void);
177 static void mark_reg_gr_used_mask (rtx, void *);
178 static void ia64_compute_frame_size (HOST_WIDE_INT);
179 static void setup_spill_pointers (int, rtx, HOST_WIDE_INT);
180 static void finish_spill_pointers (void);
181 static rtx spill_restore_mem (rtx, HOST_WIDE_INT);
182 static void do_spill (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT, rtx);
183 static void do_restore (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT);
184 static rtx gen_movdi_x (rtx, rtx, rtx);
185 static rtx gen_fr_spill_x (rtx, rtx, rtx);
186 static rtx gen_fr_restore_x (rtx, rtx, rtx);
188 static enum machine_mode hfa_element_mode (tree, bool);
189 static void ia64_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
191 static int ia64_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
193 static bool ia64_function_ok_for_sibcall (tree, tree);
194 static bool ia64_return_in_memory (tree, tree);
195 static bool ia64_rtx_costs (rtx, int, int, int *);
196 static void fix_range (const char *);
197 static bool ia64_handle_option (size_t, const char *, int);
198 static struct machine_function * ia64_init_machine_status (void);
199 static void emit_insn_group_barriers (FILE *);
200 static void emit_all_insn_group_barriers (FILE *);
201 static void final_emit_insn_group_barriers (FILE *);
202 static void emit_predicate_relation_info (void);
203 static void ia64_reorg (void);
204 static bool ia64_in_small_data_p (tree);
205 static void process_epilogue (FILE *, rtx, bool, bool);
206 static int process_set (FILE *, rtx, rtx, bool, bool);
208 static bool ia64_assemble_integer (rtx, unsigned int, int);
209 static void ia64_output_function_prologue (FILE *, HOST_WIDE_INT);
210 static void ia64_output_function_epilogue (FILE *, HOST_WIDE_INT);
211 static void ia64_output_function_end_prologue (FILE *);
213 static int ia64_issue_rate (void);
214 static int ia64_adjust_cost_2 (rtx, int, rtx, int);
215 static void ia64_sched_init (FILE *, int, int);
216 static void ia64_sched_init_global (FILE *, int, int);
217 static void ia64_sched_finish_global (FILE *, int);
218 static void ia64_sched_finish (FILE *, int);
219 static int ia64_dfa_sched_reorder (FILE *, int, rtx *, int *, int, int);
220 static int ia64_sched_reorder (FILE *, int, rtx *, int *, int);
221 static int ia64_sched_reorder2 (FILE *, int, rtx *, int *, int);
222 static int ia64_variable_issue (FILE *, int, rtx, int);
224 static struct bundle_state *get_free_bundle_state (void);
225 static void free_bundle_state (struct bundle_state *);
226 static void initiate_bundle_states (void);
227 static void finish_bundle_states (void);
228 static unsigned bundle_state_hash (const void *);
229 static int bundle_state_eq_p (const void *, const void *);
230 static int insert_bundle_state (struct bundle_state *);
231 static void initiate_bundle_state_table (void);
232 static void finish_bundle_state_table (void);
233 static int try_issue_nops (struct bundle_state *, int);
234 static int try_issue_insn (struct bundle_state *, rtx);
235 static void issue_nops_and_insn (struct bundle_state *, int, rtx, int, int);
236 static int get_max_pos (state_t);
237 static int get_template (state_t, int);
239 static rtx get_next_important_insn (rtx, rtx);
240 static void bundling (FILE *, int, rtx, rtx);
242 static void ia64_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
243 HOST_WIDE_INT, tree);
244 static void ia64_file_start (void);
246 static section *ia64_select_rtx_section (enum machine_mode, rtx,
247 unsigned HOST_WIDE_INT);
248 static void ia64_output_dwarf_dtprel (FILE *, int, rtx)
250 static section *ia64_rwreloc_select_section (tree, int, unsigned HOST_WIDE_INT)
252 static void ia64_rwreloc_unique_section (tree, int)
254 static section *ia64_rwreloc_select_rtx_section (enum machine_mode, rtx,
255 unsigned HOST_WIDE_INT)
257 static unsigned int ia64_section_type_flags (tree, const char *, int);
258 static void ia64_init_libfuncs (void)
260 static void ia64_hpux_init_libfuncs (void)
262 static void ia64_sysv4_init_libfuncs (void)
264 static void ia64_vms_init_libfuncs (void)
267 static tree ia64_handle_model_attribute (tree *, tree, tree, int, bool *);
268 static void ia64_encode_section_info (tree, rtx, int);
269 static rtx ia64_struct_value_rtx (tree, int);
270 static tree ia64_gimplify_va_arg (tree, tree, tree *, tree *);
271 static bool ia64_scalar_mode_supported_p (enum machine_mode mode);
272 static bool ia64_vector_mode_supported_p (enum machine_mode mode);
273 static bool ia64_cannot_force_const_mem (rtx);
274 static const char *ia64_mangle_fundamental_type (tree);
275 static const char *ia64_invalid_conversion (tree, tree);
276 static const char *ia64_invalid_unary_op (int, tree);
277 static const char *ia64_invalid_binary_op (int, tree, tree);
279 /* Table of valid machine attributes. */
280 static const struct attribute_spec ia64_attribute_table[] =
282 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
283 { "syscall_linkage", 0, 0, false, true, true, NULL },
284 { "model", 1, 1, true, false, false, ia64_handle_model_attribute },
285 { NULL, 0, 0, false, false, false, NULL }
288 /* Initialize the GCC target structure. */
289 #undef TARGET_ATTRIBUTE_TABLE
290 #define TARGET_ATTRIBUTE_TABLE ia64_attribute_table
292 #undef TARGET_INIT_BUILTINS
293 #define TARGET_INIT_BUILTINS ia64_init_builtins
295 #undef TARGET_EXPAND_BUILTIN
296 #define TARGET_EXPAND_BUILTIN ia64_expand_builtin
298 #undef TARGET_ASM_BYTE_OP
299 #define TARGET_ASM_BYTE_OP "\tdata1\t"
300 #undef TARGET_ASM_ALIGNED_HI_OP
301 #define TARGET_ASM_ALIGNED_HI_OP "\tdata2\t"
302 #undef TARGET_ASM_ALIGNED_SI_OP
303 #define TARGET_ASM_ALIGNED_SI_OP "\tdata4\t"
304 #undef TARGET_ASM_ALIGNED_DI_OP
305 #define TARGET_ASM_ALIGNED_DI_OP "\tdata8\t"
306 #undef TARGET_ASM_UNALIGNED_HI_OP
307 #define TARGET_ASM_UNALIGNED_HI_OP "\tdata2.ua\t"
308 #undef TARGET_ASM_UNALIGNED_SI_OP
309 #define TARGET_ASM_UNALIGNED_SI_OP "\tdata4.ua\t"
310 #undef TARGET_ASM_UNALIGNED_DI_OP
311 #define TARGET_ASM_UNALIGNED_DI_OP "\tdata8.ua\t"
312 #undef TARGET_ASM_INTEGER
313 #define TARGET_ASM_INTEGER ia64_assemble_integer
315 #undef TARGET_ASM_FUNCTION_PROLOGUE
316 #define TARGET_ASM_FUNCTION_PROLOGUE ia64_output_function_prologue
317 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
318 #define TARGET_ASM_FUNCTION_END_PROLOGUE ia64_output_function_end_prologue
319 #undef TARGET_ASM_FUNCTION_EPILOGUE
320 #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue
322 #undef TARGET_IN_SMALL_DATA_P
323 #define TARGET_IN_SMALL_DATA_P ia64_in_small_data_p
325 #undef TARGET_SCHED_ADJUST_COST_2
326 #define TARGET_SCHED_ADJUST_COST_2 ia64_adjust_cost_2
327 #undef TARGET_SCHED_ISSUE_RATE
328 #define TARGET_SCHED_ISSUE_RATE ia64_issue_rate
329 #undef TARGET_SCHED_VARIABLE_ISSUE
330 #define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue
331 #undef TARGET_SCHED_INIT
332 #define TARGET_SCHED_INIT ia64_sched_init
333 #undef TARGET_SCHED_FINISH
334 #define TARGET_SCHED_FINISH ia64_sched_finish
335 #undef TARGET_SCHED_INIT_GLOBAL
336 #define TARGET_SCHED_INIT_GLOBAL ia64_sched_init_global
337 #undef TARGET_SCHED_FINISH_GLOBAL
338 #define TARGET_SCHED_FINISH_GLOBAL ia64_sched_finish_global
339 #undef TARGET_SCHED_REORDER
340 #define TARGET_SCHED_REORDER ia64_sched_reorder
341 #undef TARGET_SCHED_REORDER2
342 #define TARGET_SCHED_REORDER2 ia64_sched_reorder2
344 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
345 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ia64_dependencies_evaluation_hook
347 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
348 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ia64_first_cycle_multipass_dfa_lookahead
350 #undef TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN
351 #define TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN ia64_init_dfa_pre_cycle_insn
352 #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN
353 #define TARGET_SCHED_DFA_PRE_CYCLE_INSN ia64_dfa_pre_cycle_insn
355 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
356 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD\
357 ia64_first_cycle_multipass_dfa_lookahead_guard
359 #undef TARGET_SCHED_DFA_NEW_CYCLE
360 #define TARGET_SCHED_DFA_NEW_CYCLE ia64_dfa_new_cycle
362 #undef TARGET_SCHED_H_I_D_EXTENDED
363 #define TARGET_SCHED_H_I_D_EXTENDED ia64_h_i_d_extended
365 #undef TARGET_SCHED_SET_SCHED_FLAGS
366 #define TARGET_SCHED_SET_SCHED_FLAGS ia64_set_sched_flags
368 #undef TARGET_SCHED_SPECULATE_INSN
369 #define TARGET_SCHED_SPECULATE_INSN ia64_speculate_insn
371 #undef TARGET_SCHED_NEEDS_BLOCK_P
372 #define TARGET_SCHED_NEEDS_BLOCK_P ia64_needs_block_p
374 #undef TARGET_SCHED_GEN_CHECK
375 #define TARGET_SCHED_GEN_CHECK ia64_gen_check
377 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD_SPEC
378 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD_SPEC\
379 ia64_first_cycle_multipass_dfa_lookahead_guard_spec
381 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
382 #define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall
383 #undef TARGET_ARG_PARTIAL_BYTES
384 #define TARGET_ARG_PARTIAL_BYTES ia64_arg_partial_bytes
386 #undef TARGET_ASM_OUTPUT_MI_THUNK
387 #define TARGET_ASM_OUTPUT_MI_THUNK ia64_output_mi_thunk
388 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
389 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
391 #undef TARGET_ASM_FILE_START
392 #define TARGET_ASM_FILE_START ia64_file_start
394 #undef TARGET_RTX_COSTS
395 #define TARGET_RTX_COSTS ia64_rtx_costs
396 #undef TARGET_ADDRESS_COST
397 #define TARGET_ADDRESS_COST hook_int_rtx_0
399 #undef TARGET_MACHINE_DEPENDENT_REORG
400 #define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg
402 #undef TARGET_ENCODE_SECTION_INFO
403 #define TARGET_ENCODE_SECTION_INFO ia64_encode_section_info
405 #undef TARGET_SECTION_TYPE_FLAGS
406 #define TARGET_SECTION_TYPE_FLAGS ia64_section_type_flags
409 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
410 #define TARGET_ASM_OUTPUT_DWARF_DTPREL ia64_output_dwarf_dtprel
413 /* ??? ABI doesn't allow us to define this. */
415 #undef TARGET_PROMOTE_FUNCTION_ARGS
416 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
419 /* ??? ABI doesn't allow us to define this. */
421 #undef TARGET_PROMOTE_FUNCTION_RETURN
422 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
425 /* ??? Investigate. */
427 #undef TARGET_PROMOTE_PROTOTYPES
428 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
431 #undef TARGET_STRUCT_VALUE_RTX
432 #define TARGET_STRUCT_VALUE_RTX ia64_struct_value_rtx
433 #undef TARGET_RETURN_IN_MEMORY
434 #define TARGET_RETURN_IN_MEMORY ia64_return_in_memory
435 #undef TARGET_SETUP_INCOMING_VARARGS
436 #define TARGET_SETUP_INCOMING_VARARGS ia64_setup_incoming_varargs
437 #undef TARGET_STRICT_ARGUMENT_NAMING
438 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
439 #undef TARGET_MUST_PASS_IN_STACK
440 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
442 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
443 #define TARGET_GIMPLIFY_VA_ARG_EXPR ia64_gimplify_va_arg
445 #undef TARGET_UNWIND_EMIT
446 #define TARGET_UNWIND_EMIT process_for_unwind_directive
448 #undef TARGET_SCALAR_MODE_SUPPORTED_P
449 #define TARGET_SCALAR_MODE_SUPPORTED_P ia64_scalar_mode_supported_p
450 #undef TARGET_VECTOR_MODE_SUPPORTED_P
451 #define TARGET_VECTOR_MODE_SUPPORTED_P ia64_vector_mode_supported_p
453 /* ia64 architecture manual 4.4.7: ... reads, writes, and flushes may occur
454 in an order different from the specified program order. */
455 #undef TARGET_RELAXED_ORDERING
456 #define TARGET_RELAXED_ORDERING true
458 #undef TARGET_DEFAULT_TARGET_FLAGS
459 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | TARGET_CPU_DEFAULT)
460 #undef TARGET_HANDLE_OPTION
461 #define TARGET_HANDLE_OPTION ia64_handle_option
463 #undef TARGET_CANNOT_FORCE_CONST_MEM
464 #define TARGET_CANNOT_FORCE_CONST_MEM ia64_cannot_force_const_mem
466 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
467 #define TARGET_MANGLE_FUNDAMENTAL_TYPE ia64_mangle_fundamental_type
469 #undef TARGET_INVALID_CONVERSION
470 #define TARGET_INVALID_CONVERSION ia64_invalid_conversion
471 #undef TARGET_INVALID_UNARY_OP
472 #define TARGET_INVALID_UNARY_OP ia64_invalid_unary_op
473 #undef TARGET_INVALID_BINARY_OP
474 #define TARGET_INVALID_BINARY_OP ia64_invalid_binary_op
476 struct gcc_target targetm = TARGET_INITIALIZER;
480 ADDR_AREA_NORMAL, /* normal address area */
481 ADDR_AREA_SMALL /* addressable by "addl" (-2MB < addr < 2MB) */
485 static GTY(()) tree small_ident1;
486 static GTY(()) tree small_ident2;
491 if (small_ident1 == 0)
493 small_ident1 = get_identifier ("small");
494 small_ident2 = get_identifier ("__small__");
498 /* Retrieve the address area that has been chosen for the given decl. */
500 static ia64_addr_area
501 ia64_get_addr_area (tree decl)
505 model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
511 id = TREE_VALUE (TREE_VALUE (model_attr));
512 if (id == small_ident1 || id == small_ident2)
513 return ADDR_AREA_SMALL;
515 return ADDR_AREA_NORMAL;
519 ia64_handle_model_attribute (tree *node, tree name, tree args,
520 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
522 ia64_addr_area addr_area = ADDR_AREA_NORMAL;
524 tree arg, decl = *node;
527 arg = TREE_VALUE (args);
528 if (arg == small_ident1 || arg == small_ident2)
530 addr_area = ADDR_AREA_SMALL;
534 warning (OPT_Wattributes, "invalid argument of %qs attribute",
535 IDENTIFIER_POINTER (name));
536 *no_add_attrs = true;
539 switch (TREE_CODE (decl))
542 if ((DECL_CONTEXT (decl) && TREE_CODE (DECL_CONTEXT (decl))
544 && !TREE_STATIC (decl))
546 error ("%Jan address area attribute cannot be specified for "
547 "local variables", decl);
548 *no_add_attrs = true;
550 area = ia64_get_addr_area (decl);
551 if (area != ADDR_AREA_NORMAL && addr_area != area)
553 error ("address area of %q+D conflicts with previous "
554 "declaration", decl);
555 *no_add_attrs = true;
560 error ("%Jaddress area attribute cannot be specified for functions",
562 *no_add_attrs = true;
566 warning (OPT_Wattributes, "%qs attribute ignored",
567 IDENTIFIER_POINTER (name));
568 *no_add_attrs = true;
576 ia64_encode_addr_area (tree decl, rtx symbol)
580 flags = SYMBOL_REF_FLAGS (symbol);
581 switch (ia64_get_addr_area (decl))
583 case ADDR_AREA_NORMAL: break;
584 case ADDR_AREA_SMALL: flags |= SYMBOL_FLAG_SMALL_ADDR; break;
585 default: gcc_unreachable ();
587 SYMBOL_REF_FLAGS (symbol) = flags;
591 ia64_encode_section_info (tree decl, rtx rtl, int first)
593 default_encode_section_info (decl, rtl, first);
595 /* Careful not to prod global register variables. */
596 if (TREE_CODE (decl) == VAR_DECL
597 && GET_CODE (DECL_RTL (decl)) == MEM
598 && GET_CODE (XEXP (DECL_RTL (decl), 0)) == SYMBOL_REF
599 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
600 ia64_encode_addr_area (decl, XEXP (rtl, 0));
603 /* Implement CONST_OK_FOR_LETTER_P. */
606 ia64_const_ok_for_letter_p (HOST_WIDE_INT value, char c)
611 return CONST_OK_FOR_I (value);
613 return CONST_OK_FOR_J (value);
615 return CONST_OK_FOR_K (value);
617 return CONST_OK_FOR_L (value);
619 return CONST_OK_FOR_M (value);
621 return CONST_OK_FOR_N (value);
623 return CONST_OK_FOR_O (value);
625 return CONST_OK_FOR_P (value);
631 /* Implement CONST_DOUBLE_OK_FOR_LETTER_P. */
634 ia64_const_double_ok_for_letter_p (rtx value, char c)
639 return CONST_DOUBLE_OK_FOR_G (value);
645 /* Implement EXTRA_CONSTRAINT. */
648 ia64_extra_constraint (rtx value, char c)
653 /* Non-volatile memory for FP_REG loads/stores. */
654 return memory_operand(value, VOIDmode) && !MEM_VOLATILE_P (value);
657 /* 1..4 for shladd arguments. */
658 return (GET_CODE (value) == CONST_INT
659 && INTVAL (value) >= 1 && INTVAL (value) <= 4);
662 /* Non-post-inc memory for asms and other unsavory creatures. */
663 return (GET_CODE (value) == MEM
664 && GET_RTX_CLASS (GET_CODE (XEXP (value, 0))) != RTX_AUTOINC
665 && (reload_in_progress || memory_operand (value, VOIDmode)));
668 /* Symbol ref to small-address-area. */
669 return small_addr_symbolic_operand (value, VOIDmode);
673 return value == CONST0_RTX (GET_MODE (value));
676 /* An integer vector, such that conversion to an integer yields a
677 value appropriate for an integer 'J' constraint. */
678 if (GET_CODE (value) == CONST_VECTOR
679 && GET_MODE_CLASS (GET_MODE (value)) == MODE_VECTOR_INT)
681 value = simplify_subreg (DImode, value, GET_MODE (value), 0);
682 return ia64_const_ok_for_letter_p (INTVAL (value), 'J');
687 /* A V2SF vector containing elements that satisfy 'G'. */
689 (GET_CODE (value) == CONST_VECTOR
690 && GET_MODE (value) == V2SFmode
691 && ia64_const_double_ok_for_letter_p (XVECEXP (value, 0, 0), 'G')
692 && ia64_const_double_ok_for_letter_p (XVECEXP (value, 0, 1), 'G'));
699 /* Return 1 if the operands of a move are ok. */
702 ia64_move_ok (rtx dst, rtx src)
704 /* If we're under init_recog_no_volatile, we'll not be able to use
705 memory_operand. So check the code directly and don't worry about
706 the validity of the underlying address, which should have been
707 checked elsewhere anyway. */
708 if (GET_CODE (dst) != MEM)
710 if (GET_CODE (src) == MEM)
712 if (register_operand (src, VOIDmode))
715 /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0. */
716 if (INTEGRAL_MODE_P (GET_MODE (dst)))
717 return src == const0_rtx;
719 return GET_CODE (src) == CONST_DOUBLE && CONST_DOUBLE_OK_FOR_G (src);
722 /* Return 1 if the operands are ok for a floating point load pair. */
725 ia64_load_pair_ok (rtx dst, rtx src)
727 if (GET_CODE (dst) != REG || !FP_REGNO_P (REGNO (dst)))
729 if (GET_CODE (src) != MEM || MEM_VOLATILE_P (src))
731 switch (GET_CODE (XEXP (src, 0)))
740 rtx adjust = XEXP (XEXP (XEXP (src, 0), 1), 1);
742 if (GET_CODE (adjust) != CONST_INT
743 || INTVAL (adjust) != GET_MODE_SIZE (GET_MODE (src)))
754 addp4_optimize_ok (rtx op1, rtx op2)
756 return (basereg_operand (op1, GET_MODE(op1)) !=
757 basereg_operand (op2, GET_MODE(op2)));
760 /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction.
761 Return the length of the field, or <= 0 on failure. */
764 ia64_depz_field_mask (rtx rop, rtx rshift)
766 unsigned HOST_WIDE_INT op = INTVAL (rop);
767 unsigned HOST_WIDE_INT shift = INTVAL (rshift);
769 /* Get rid of the zero bits we're shifting in. */
772 /* We must now have a solid block of 1's at bit 0. */
773 return exact_log2 (op + 1);
776 /* Return the TLS model to use for ADDR. */
778 static enum tls_model
779 tls_symbolic_operand_type (rtx addr)
781 enum tls_model tls_kind = 0;
783 if (GET_CODE (addr) == CONST)
785 if (GET_CODE (XEXP (addr, 0)) == PLUS
786 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF)
787 tls_kind = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (addr, 0), 0));
789 else if (GET_CODE (addr) == SYMBOL_REF)
790 tls_kind = SYMBOL_REF_TLS_MODEL (addr);
795 /* Return true if X is a constant that is valid for some immediate
796 field in an instruction. */
799 ia64_legitimate_constant_p (rtx x)
801 switch (GET_CODE (x))
808 if (GET_MODE (x) == VOIDmode)
810 return CONST_DOUBLE_OK_FOR_G (x);
814 /* ??? Short term workaround for PR 28490. We must make the code here
815 match the code in ia64_expand_move and move_operand, even though they
816 are both technically wrong. */
817 if (tls_symbolic_operand_type (x) == 0)
819 HOST_WIDE_INT addend = 0;
822 if (GET_CODE (op) == CONST
823 && GET_CODE (XEXP (op, 0)) == PLUS
824 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
826 addend = INTVAL (XEXP (XEXP (op, 0), 1));
827 op = XEXP (XEXP (op, 0), 0);
830 if (any_offset_symbol_operand (op, GET_MODE (op))
831 || function_operand (op, GET_MODE (op)))
833 if (aligned_offset_symbol_operand (op, GET_MODE (op)))
834 return (addend & 0x3fff) == 0;
841 enum machine_mode mode = GET_MODE (x);
843 if (mode == V2SFmode)
844 return ia64_extra_constraint (x, 'Y');
846 return (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
847 && GET_MODE_SIZE (mode) <= 8);
855 /* Don't allow TLS addresses to get spilled to memory. */
858 ia64_cannot_force_const_mem (rtx x)
860 return tls_symbolic_operand_type (x) != 0;
863 /* Expand a symbolic constant load. */
866 ia64_expand_load_address (rtx dest, rtx src)
868 gcc_assert (GET_CODE (dest) == REG);
870 /* ILP32 mode still loads 64-bits of data from the GOT. This avoids
871 having to pointer-extend the value afterward. Other forms of address
872 computation below are also more natural to compute as 64-bit quantities.
873 If we've been given an SImode destination register, change it. */
874 if (GET_MODE (dest) != Pmode)
875 dest = gen_rtx_REG_offset (dest, Pmode, REGNO (dest), 0);
879 if (small_addr_symbolic_operand (src, VOIDmode))
883 emit_insn (gen_load_gprel64 (dest, src));
884 else if (GET_CODE (src) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (src))
885 emit_insn (gen_load_fptr (dest, src));
886 else if (sdata_symbolic_operand (src, VOIDmode))
887 emit_insn (gen_load_gprel (dest, src));
890 HOST_WIDE_INT addend = 0;
893 /* We did split constant offsets in ia64_expand_move, and we did try
894 to keep them split in move_operand, but we also allowed reload to
895 rematerialize arbitrary constants rather than spill the value to
896 the stack and reload it. So we have to be prepared here to split
898 if (GET_CODE (src) == CONST)
900 HOST_WIDE_INT hi, lo;
902 hi = INTVAL (XEXP (XEXP (src, 0), 1));
903 lo = ((hi & 0x3fff) ^ 0x2000) - 0x2000;
909 src = plus_constant (XEXP (XEXP (src, 0), 0), hi);
913 tmp = gen_rtx_HIGH (Pmode, src);
914 tmp = gen_rtx_PLUS (Pmode, tmp, pic_offset_table_rtx);
915 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
917 tmp = gen_rtx_LO_SUM (Pmode, dest, src);
918 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
922 tmp = gen_rtx_PLUS (Pmode, dest, GEN_INT (addend));
923 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
930 static GTY(()) rtx gen_tls_tga;
932 gen_tls_get_addr (void)
935 gen_tls_tga = init_one_libfunc ("__tls_get_addr");
939 static GTY(()) rtx thread_pointer_rtx;
941 gen_thread_pointer (void)
943 if (!thread_pointer_rtx)
944 thread_pointer_rtx = gen_rtx_REG (Pmode, 13);
945 return thread_pointer_rtx;
949 ia64_expand_tls_address (enum tls_model tls_kind, rtx op0, rtx op1,
950 rtx orig_op1, HOST_WIDE_INT addend)
952 rtx tga_op1, tga_op2, tga_ret, tga_eqv, tmp, insns;
954 HOST_WIDE_INT addend_lo, addend_hi;
958 case TLS_MODEL_GLOBAL_DYNAMIC:
961 tga_op1 = gen_reg_rtx (Pmode);
962 emit_insn (gen_load_dtpmod (tga_op1, op1));
964 tga_op2 = gen_reg_rtx (Pmode);
965 emit_insn (gen_load_dtprel (tga_op2, op1));
967 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
968 LCT_CONST, Pmode, 2, tga_op1,
969 Pmode, tga_op2, Pmode);
971 insns = get_insns ();
974 if (GET_MODE (op0) != Pmode)
976 emit_libcall_block (insns, op0, tga_ret, op1);
979 case TLS_MODEL_LOCAL_DYNAMIC:
980 /* ??? This isn't the completely proper way to do local-dynamic
981 If the call to __tls_get_addr is used only by a single symbol,
982 then we should (somehow) move the dtprel to the second arg
983 to avoid the extra add. */
986 tga_op1 = gen_reg_rtx (Pmode);
987 emit_insn (gen_load_dtpmod (tga_op1, op1));
989 tga_op2 = const0_rtx;
991 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
992 LCT_CONST, Pmode, 2, tga_op1,
993 Pmode, tga_op2, Pmode);
995 insns = get_insns ();
998 tga_eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
1000 tmp = gen_reg_rtx (Pmode);
1001 emit_libcall_block (insns, tmp, tga_ret, tga_eqv);
1003 if (!register_operand (op0, Pmode))
1004 op0 = gen_reg_rtx (Pmode);
1007 emit_insn (gen_load_dtprel (op0, op1));
1008 emit_insn (gen_adddi3 (op0, tmp, op0));
1011 emit_insn (gen_add_dtprel (op0, op1, tmp));
1014 case TLS_MODEL_INITIAL_EXEC:
1015 addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000;
1016 addend_hi = addend - addend_lo;
1018 op1 = plus_constant (op1, addend_hi);
1021 tmp = gen_reg_rtx (Pmode);
1022 emit_insn (gen_load_tprel (tmp, op1));
1024 if (!register_operand (op0, Pmode))
1025 op0 = gen_reg_rtx (Pmode);
1026 emit_insn (gen_adddi3 (op0, tmp, gen_thread_pointer ()));
1029 case TLS_MODEL_LOCAL_EXEC:
1030 if (!register_operand (op0, Pmode))
1031 op0 = gen_reg_rtx (Pmode);
1037 emit_insn (gen_load_tprel (op0, op1));
1038 emit_insn (gen_adddi3 (op0, op0, gen_thread_pointer ()));
1041 emit_insn (gen_add_tprel (op0, op1, gen_thread_pointer ()));
1049 op0 = expand_simple_binop (Pmode, PLUS, op0, GEN_INT (addend),
1050 orig_op0, 1, OPTAB_DIRECT);
1051 if (orig_op0 == op0)
1053 if (GET_MODE (orig_op0) == Pmode)
1055 return gen_lowpart (GET_MODE (orig_op0), op0);
1059 ia64_expand_move (rtx op0, rtx op1)
1061 enum machine_mode mode = GET_MODE (op0);
1063 if (!reload_in_progress && !reload_completed && !ia64_move_ok (op0, op1))
1064 op1 = force_reg (mode, op1);
1066 if ((mode == Pmode || mode == ptr_mode) && symbolic_operand (op1, VOIDmode))
1068 HOST_WIDE_INT addend = 0;
1069 enum tls_model tls_kind;
1072 if (GET_CODE (op1) == CONST
1073 && GET_CODE (XEXP (op1, 0)) == PLUS
1074 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT)
1076 addend = INTVAL (XEXP (XEXP (op1, 0), 1));
1077 sym = XEXP (XEXP (op1, 0), 0);
1080 tls_kind = tls_symbolic_operand_type (sym);
1082 return ia64_expand_tls_address (tls_kind, op0, sym, op1, addend);
1084 if (any_offset_symbol_operand (sym, mode))
1086 else if (aligned_offset_symbol_operand (sym, mode))
1088 HOST_WIDE_INT addend_lo, addend_hi;
1090 addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000;
1091 addend_hi = addend - addend_lo;
1095 op1 = plus_constant (sym, addend_hi);
1104 if (reload_completed)
1106 /* We really should have taken care of this offset earlier. */
1107 gcc_assert (addend == 0);
1108 if (ia64_expand_load_address (op0, op1))
1114 rtx subtarget = no_new_pseudos ? op0 : gen_reg_rtx (mode);
1116 emit_insn (gen_rtx_SET (VOIDmode, subtarget, op1));
1118 op1 = expand_simple_binop (mode, PLUS, subtarget,
1119 GEN_INT (addend), op0, 1, OPTAB_DIRECT);
1128 /* Split a move from OP1 to OP0 conditional on COND. */
1131 ia64_emit_cond_move (rtx op0, rtx op1, rtx cond)
1133 rtx insn, first = get_last_insn ();
1135 emit_move_insn (op0, op1);
1137 for (insn = get_last_insn (); insn != first; insn = PREV_INSN (insn))
1139 PATTERN (insn) = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond),
1143 /* Split a post-reload TImode or TFmode reference into two DImode
1144 components. This is made extra difficult by the fact that we do
1145 not get any scratch registers to work with, because reload cannot
1146 be prevented from giving us a scratch that overlaps the register
1147 pair involved. So instead, when addressing memory, we tweak the
1148 pointer register up and back down with POST_INCs. Or up and not
1149 back down when we can get away with it.
1151 REVERSED is true when the loads must be done in reversed order
1152 (high word first) for correctness. DEAD is true when the pointer
1153 dies with the second insn we generate and therefore the second
1154 address must not carry a postmodify.
1156 May return an insn which is to be emitted after the moves. */
1159 ia64_split_tmode (rtx out[2], rtx in, bool reversed, bool dead)
1163 switch (GET_CODE (in))
1166 out[reversed] = gen_rtx_REG (DImode, REGNO (in));
1167 out[!reversed] = gen_rtx_REG (DImode, REGNO (in) + 1);
1172 /* Cannot occur reversed. */
1173 gcc_assert (!reversed);
1175 if (GET_MODE (in) != TFmode)
1176 split_double (in, &out[0], &out[1]);
1178 /* split_double does not understand how to split a TFmode
1179 quantity into a pair of DImode constants. */
1182 unsigned HOST_WIDE_INT p[2];
1183 long l[4]; /* TFmode is 128 bits */
1185 REAL_VALUE_FROM_CONST_DOUBLE (r, in);
1186 real_to_target (l, &r, TFmode);
1188 if (FLOAT_WORDS_BIG_ENDIAN)
1190 p[0] = (((unsigned HOST_WIDE_INT) l[0]) << 32) + l[1];
1191 p[1] = (((unsigned HOST_WIDE_INT) l[2]) << 32) + l[3];
1195 p[0] = (((unsigned HOST_WIDE_INT) l[3]) << 32) + l[2];
1196 p[1] = (((unsigned HOST_WIDE_INT) l[1]) << 32) + l[0];
1198 out[0] = GEN_INT (p[0]);
1199 out[1] = GEN_INT (p[1]);
1205 rtx base = XEXP (in, 0);
1208 switch (GET_CODE (base))
1213 out[0] = adjust_automodify_address
1214 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1215 out[1] = adjust_automodify_address
1216 (in, DImode, dead ? 0 : gen_rtx_POST_DEC (Pmode, base), 8);
1220 /* Reversal requires a pre-increment, which can only
1221 be done as a separate insn. */
1222 emit_insn (gen_adddi3 (base, base, GEN_INT (8)));
1223 out[0] = adjust_automodify_address
1224 (in, DImode, gen_rtx_POST_DEC (Pmode, base), 8);
1225 out[1] = adjust_address (in, DImode, 0);
1230 gcc_assert (!reversed && !dead);
1232 /* Just do the increment in two steps. */
1233 out[0] = adjust_automodify_address (in, DImode, 0, 0);
1234 out[1] = adjust_automodify_address (in, DImode, 0, 8);
1238 gcc_assert (!reversed && !dead);
1240 /* Add 8, subtract 24. */
1241 base = XEXP (base, 0);
1242 out[0] = adjust_automodify_address
1243 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1244 out[1] = adjust_automodify_address
1246 gen_rtx_POST_MODIFY (Pmode, base, plus_constant (base, -24)),
1251 gcc_assert (!reversed && !dead);
1253 /* Extract and adjust the modification. This case is
1254 trickier than the others, because we might have an
1255 index register, or we might have a combined offset that
1256 doesn't fit a signed 9-bit displacement field. We can
1257 assume the incoming expression is already legitimate. */
1258 offset = XEXP (base, 1);
1259 base = XEXP (base, 0);
1261 out[0] = adjust_automodify_address
1262 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1264 if (GET_CODE (XEXP (offset, 1)) == REG)
1266 /* Can't adjust the postmodify to match. Emit the
1267 original, then a separate addition insn. */
1268 out[1] = adjust_automodify_address (in, DImode, 0, 8);
1269 fixup = gen_adddi3 (base, base, GEN_INT (-8));
1273 gcc_assert (GET_CODE (XEXP (offset, 1)) == CONST_INT);
1274 if (INTVAL (XEXP (offset, 1)) < -256 + 8)
1276 /* Again the postmodify cannot be made to match,
1277 but in this case it's more efficient to get rid
1278 of the postmodify entirely and fix up with an
1280 out[1] = adjust_automodify_address (in, DImode, base, 8);
1282 (base, base, GEN_INT (INTVAL (XEXP (offset, 1)) - 8));
1286 /* Combined offset still fits in the displacement field.
1287 (We cannot overflow it at the high end.) */
1288 out[1] = adjust_automodify_address
1289 (in, DImode, gen_rtx_POST_MODIFY
1290 (Pmode, base, gen_rtx_PLUS
1292 GEN_INT (INTVAL (XEXP (offset, 1)) - 8))),
1311 /* Split a TImode or TFmode move instruction after reload.
1312 This is used by *movtf_internal and *movti_internal. */
1314 ia64_split_tmode_move (rtx operands[])
1316 rtx in[2], out[2], insn;
1319 bool reversed = false;
1321 /* It is possible for reload to decide to overwrite a pointer with
1322 the value it points to. In that case we have to do the loads in
1323 the appropriate order so that the pointer is not destroyed too
1324 early. Also we must not generate a postmodify for that second
1325 load, or rws_access_regno will die. */
1326 if (GET_CODE (operands[1]) == MEM
1327 && reg_overlap_mentioned_p (operands[0], operands[1]))
1329 rtx base = XEXP (operands[1], 0);
1330 while (GET_CODE (base) != REG)
1331 base = XEXP (base, 0);
1333 if (REGNO (base) == REGNO (operands[0]))
1337 /* Another reason to do the moves in reversed order is if the first
1338 element of the target register pair is also the second element of
1339 the source register pair. */
1340 if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
1341 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
1344 fixup[0] = ia64_split_tmode (in, operands[1], reversed, dead);
1345 fixup[1] = ia64_split_tmode (out, operands[0], reversed, dead);
1347 #define MAYBE_ADD_REG_INC_NOTE(INSN, EXP) \
1348 if (GET_CODE (EXP) == MEM \
1349 && (GET_CODE (XEXP (EXP, 0)) == POST_MODIFY \
1350 || GET_CODE (XEXP (EXP, 0)) == POST_INC \
1351 || GET_CODE (XEXP (EXP, 0)) == POST_DEC)) \
1352 REG_NOTES (INSN) = gen_rtx_EXPR_LIST (REG_INC, \
1353 XEXP (XEXP (EXP, 0), 0), \
1356 insn = emit_insn (gen_rtx_SET (VOIDmode, out[0], in[0]));
1357 MAYBE_ADD_REG_INC_NOTE (insn, in[0]);
1358 MAYBE_ADD_REG_INC_NOTE (insn, out[0]);
1360 insn = emit_insn (gen_rtx_SET (VOIDmode, out[1], in[1]));
1361 MAYBE_ADD_REG_INC_NOTE (insn, in[1]);
1362 MAYBE_ADD_REG_INC_NOTE (insn, out[1]);
1365 emit_insn (fixup[0]);
1367 emit_insn (fixup[1]);
1369 #undef MAYBE_ADD_REG_INC_NOTE
1372 /* ??? Fixing GR->FR XFmode moves during reload is hard. You need to go
1373 through memory plus an extra GR scratch register. Except that you can
1374 either get the first from SECONDARY_MEMORY_NEEDED or the second from
1375 SECONDARY_RELOAD_CLASS, but not both.
1377 We got into problems in the first place by allowing a construct like
1378 (subreg:XF (reg:TI)), which we got from a union containing a long double.
1379 This solution attempts to prevent this situation from occurring. When
1380 we see something like the above, we spill the inner register to memory. */
1383 spill_xfmode_rfmode_operand (rtx in, int force, enum machine_mode mode)
1385 if (GET_CODE (in) == SUBREG
1386 && GET_MODE (SUBREG_REG (in)) == TImode
1387 && GET_CODE (SUBREG_REG (in)) == REG)
1389 rtx memt = assign_stack_temp (TImode, 16, 0);
1390 emit_move_insn (memt, SUBREG_REG (in));
1391 return adjust_address (memt, mode, 0);
1393 else if (force && GET_CODE (in) == REG)
1395 rtx memx = assign_stack_temp (mode, 16, 0);
1396 emit_move_insn (memx, in);
1403 /* Expand the movxf or movrf pattern (MODE says which) with the given
1404 OPERANDS, returning true if the pattern should then invoke
1408 ia64_expand_movxf_movrf (enum machine_mode mode, rtx operands[])
1410 rtx op0 = operands[0];
1412 if (GET_CODE (op0) == SUBREG)
1413 op0 = SUBREG_REG (op0);
1415 /* We must support XFmode loads into general registers for stdarg/vararg,
1416 unprototyped calls, and a rare case where a long double is passed as
1417 an argument after a float HFA fills the FP registers. We split them into
1418 DImode loads for convenience. We also need to support XFmode stores
1419 for the last case. This case does not happen for stdarg/vararg routines,
1420 because we do a block store to memory of unnamed arguments. */
1422 if (GET_CODE (op0) == REG && GR_REGNO_P (REGNO (op0)))
1426 /* We're hoping to transform everything that deals with XFmode
1427 quantities and GR registers early in the compiler. */
1428 gcc_assert (!no_new_pseudos);
1430 /* Struct to register can just use TImode instead. */
1431 if ((GET_CODE (operands[1]) == SUBREG
1432 && GET_MODE (SUBREG_REG (operands[1])) == TImode)
1433 || (GET_CODE (operands[1]) == REG
1434 && GR_REGNO_P (REGNO (operands[1]))))
1436 rtx op1 = operands[1];
1438 if (GET_CODE (op1) == SUBREG)
1439 op1 = SUBREG_REG (op1);
1441 op1 = gen_rtx_REG (TImode, REGNO (op1));
1443 emit_move_insn (gen_rtx_REG (TImode, REGNO (op0)), op1);
1447 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1449 /* Don't word-swap when reading in the constant. */
1450 emit_move_insn (gen_rtx_REG (DImode, REGNO (op0)),
1451 operand_subword (operands[1], WORDS_BIG_ENDIAN,
1453 emit_move_insn (gen_rtx_REG (DImode, REGNO (op0) + 1),
1454 operand_subword (operands[1], !WORDS_BIG_ENDIAN,
1459 /* If the quantity is in a register not known to be GR, spill it. */
1460 if (register_operand (operands[1], mode))
1461 operands[1] = spill_xfmode_rfmode_operand (operands[1], 1, mode);
1463 gcc_assert (GET_CODE (operands[1]) == MEM);
1465 /* Don't word-swap when reading in the value. */
1466 out[0] = gen_rtx_REG (DImode, REGNO (op0));
1467 out[1] = gen_rtx_REG (DImode, REGNO (op0) + 1);
1469 emit_move_insn (out[0], adjust_address (operands[1], DImode, 0));
1470 emit_move_insn (out[1], adjust_address (operands[1], DImode, 8));
1474 if (GET_CODE (operands[1]) == REG && GR_REGNO_P (REGNO (operands[1])))
1476 /* We're hoping to transform everything that deals with XFmode
1477 quantities and GR registers early in the compiler. */
1478 gcc_assert (!no_new_pseudos);
1480 /* Op0 can't be a GR_REG here, as that case is handled above.
1481 If op0 is a register, then we spill op1, so that we now have a
1482 MEM operand. This requires creating an XFmode subreg of a TImode reg
1483 to force the spill. */
1484 if (register_operand (operands[0], mode))
1486 rtx op1 = gen_rtx_REG (TImode, REGNO (operands[1]));
1487 op1 = gen_rtx_SUBREG (mode, op1, 0);
1488 operands[1] = spill_xfmode_rfmode_operand (op1, 0, mode);
1495 gcc_assert (GET_CODE (operands[0]) == MEM);
1497 /* Don't word-swap when writing out the value. */
1498 in[0] = gen_rtx_REG (DImode, REGNO (operands[1]));
1499 in[1] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1);
1501 emit_move_insn (adjust_address (operands[0], DImode, 0), in[0]);
1502 emit_move_insn (adjust_address (operands[0], DImode, 8), in[1]);
1507 if (!reload_in_progress && !reload_completed)
1509 operands[1] = spill_xfmode_rfmode_operand (operands[1], 0, mode);
1511 if (GET_MODE (op0) == TImode && GET_CODE (op0) == REG)
1513 rtx memt, memx, in = operands[1];
1514 if (CONSTANT_P (in))
1515 in = validize_mem (force_const_mem (mode, in));
1516 if (GET_CODE (in) == MEM)
1517 memt = adjust_address (in, TImode, 0);
1520 memt = assign_stack_temp (TImode, 16, 0);
1521 memx = adjust_address (memt, mode, 0);
1522 emit_move_insn (memx, in);
1524 emit_move_insn (op0, memt);
1528 if (!ia64_move_ok (operands[0], operands[1]))
1529 operands[1] = force_reg (mode, operands[1]);
1535 /* Emit comparison instruction if necessary, returning the expression
1536 that holds the compare result in the proper mode. */
1538 static GTY(()) rtx cmptf_libfunc;
1541 ia64_expand_compare (enum rtx_code code, enum machine_mode mode)
1543 rtx op0 = ia64_compare_op0, op1 = ia64_compare_op1;
1546 /* If we have a BImode input, then we already have a compare result, and
1547 do not need to emit another comparison. */
1548 if (GET_MODE (op0) == BImode)
1550 gcc_assert ((code == NE || code == EQ) && op1 == const0_rtx);
1553 /* HPUX TFmode compare requires a library call to _U_Qfcmp, which takes a
1554 magic number as its third argument, that indicates what to do.
1555 The return value is an integer to be compared against zero. */
1556 else if (GET_MODE (op0) == TFmode)
1559 QCMP_INV = 1, /* Raise FP_INVALID on SNaN as a side effect. */
1565 enum rtx_code ncode;
1568 gcc_assert (cmptf_libfunc && GET_MODE (op1) == TFmode);
1571 /* 1 = equal, 0 = not equal. Equality operators do
1572 not raise FP_INVALID when given an SNaN operand. */
1573 case EQ: magic = QCMP_EQ; ncode = NE; break;
1574 case NE: magic = QCMP_EQ; ncode = EQ; break;
1575 /* isunordered() from C99. */
1576 case UNORDERED: magic = QCMP_UNORD; ncode = NE; break;
1577 case ORDERED: magic = QCMP_UNORD; ncode = EQ; break;
1578 /* Relational operators raise FP_INVALID when given
1580 case LT: magic = QCMP_LT |QCMP_INV; ncode = NE; break;
1581 case LE: magic = QCMP_LT|QCMP_EQ|QCMP_INV; ncode = NE; break;
1582 case GT: magic = QCMP_GT |QCMP_INV; ncode = NE; break;
1583 case GE: magic = QCMP_GT|QCMP_EQ|QCMP_INV; ncode = NE; break;
1584 /* FUTURE: Implement UNEQ, UNLT, UNLE, UNGT, UNGE, LTGT.
1585 Expanders for buneq etc. weuld have to be added to ia64.md
1586 for this to be useful. */
1587 default: gcc_unreachable ();
1592 ret = emit_library_call_value (cmptf_libfunc, 0, LCT_CONST, DImode, 3,
1593 op0, TFmode, op1, TFmode,
1594 GEN_INT (magic), DImode);
1595 cmp = gen_reg_rtx (BImode);
1596 emit_insn (gen_rtx_SET (VOIDmode, cmp,
1597 gen_rtx_fmt_ee (ncode, BImode,
1600 insns = get_insns ();
1603 emit_libcall_block (insns, cmp, cmp,
1604 gen_rtx_fmt_ee (code, BImode, op0, op1));
1609 cmp = gen_reg_rtx (BImode);
1610 emit_insn (gen_rtx_SET (VOIDmode, cmp,
1611 gen_rtx_fmt_ee (code, BImode, op0, op1)));
1615 return gen_rtx_fmt_ee (code, mode, cmp, const0_rtx);
1618 /* Generate an integral vector comparison. Return true if the condition has
1619 been reversed, and so the sense of the comparison should be inverted. */
1622 ia64_expand_vecint_compare (enum rtx_code code, enum machine_mode mode,
1623 rtx dest, rtx op0, rtx op1)
1625 bool negate = false;
1628 /* Canonicalize the comparison to EQ, GT, GTU. */
1639 code = reverse_condition (code);
1645 code = reverse_condition (code);
1651 code = swap_condition (code);
1652 x = op0, op0 = op1, op1 = x;
1659 /* Unsigned parallel compare is not supported by the hardware. Play some
1660 tricks to turn this into a signed comparison against 0. */
1669 /* Perform a parallel modulo subtraction. */
1670 t1 = gen_reg_rtx (V2SImode);
1671 emit_insn (gen_subv2si3 (t1, op0, op1));
1673 /* Extract the original sign bit of op0. */
1674 mask = GEN_INT (-0x80000000);
1675 mask = gen_rtx_CONST_VECTOR (V2SImode, gen_rtvec (2, mask, mask));
1676 mask = force_reg (V2SImode, mask);
1677 t2 = gen_reg_rtx (V2SImode);
1678 emit_insn (gen_andv2si3 (t2, op0, mask));
1680 /* XOR it back into the result of the subtraction. This results
1681 in the sign bit set iff we saw unsigned underflow. */
1682 x = gen_reg_rtx (V2SImode);
1683 emit_insn (gen_xorv2si3 (x, t1, t2));
1687 op1 = CONST0_RTX (mode);
1693 /* Perform a parallel unsigned saturating subtraction. */
1694 x = gen_reg_rtx (mode);
1695 emit_insn (gen_rtx_SET (VOIDmode, x,
1696 gen_rtx_US_MINUS (mode, op0, op1)));
1700 op1 = CONST0_RTX (mode);
1709 x = gen_rtx_fmt_ee (code, mode, op0, op1);
1710 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
1715 /* Emit an integral vector conditional move. */
1718 ia64_expand_vecint_cmov (rtx operands[])
1720 enum machine_mode mode = GET_MODE (operands[0]);
1721 enum rtx_code code = GET_CODE (operands[3]);
1725 cmp = gen_reg_rtx (mode);
1726 negate = ia64_expand_vecint_compare (code, mode, cmp,
1727 operands[4], operands[5]);
1729 ot = operands[1+negate];
1730 of = operands[2-negate];
1732 if (ot == CONST0_RTX (mode))
1734 if (of == CONST0_RTX (mode))
1736 emit_move_insn (operands[0], ot);
1740 x = gen_rtx_NOT (mode, cmp);
1741 x = gen_rtx_AND (mode, x, of);
1742 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1744 else if (of == CONST0_RTX (mode))
1746 x = gen_rtx_AND (mode, cmp, ot);
1747 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1753 t = gen_reg_rtx (mode);
1754 x = gen_rtx_AND (mode, cmp, operands[1+negate]);
1755 emit_insn (gen_rtx_SET (VOIDmode, t, x));
1757 f = gen_reg_rtx (mode);
1758 x = gen_rtx_NOT (mode, cmp);
1759 x = gen_rtx_AND (mode, x, operands[2-negate]);
1760 emit_insn (gen_rtx_SET (VOIDmode, f, x));
1762 x = gen_rtx_IOR (mode, t, f);
1763 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1767 /* Emit an integral vector min or max operation. Return true if all done. */
1770 ia64_expand_vecint_minmax (enum rtx_code code, enum machine_mode mode,
1775 /* These four combinations are supported directly. */
1776 if (mode == V8QImode && (code == UMIN || code == UMAX))
1778 if (mode == V4HImode && (code == SMIN || code == SMAX))
1781 /* This combination can be implemented with only saturating subtraction. */
1782 if (mode == V4HImode && code == UMAX)
1784 rtx x, tmp = gen_reg_rtx (mode);
1786 x = gen_rtx_US_MINUS (mode, operands[1], operands[2]);
1787 emit_insn (gen_rtx_SET (VOIDmode, tmp, x));
1789 emit_insn (gen_addv4hi3 (operands[0], tmp, operands[2]));
1793 /* Everything else implemented via vector comparisons. */
1794 xops[0] = operands[0];
1795 xops[4] = xops[1] = operands[1];
1796 xops[5] = xops[2] = operands[2];
1815 xops[3] = gen_rtx_fmt_ee (code, VOIDmode, operands[1], operands[2]);
1817 ia64_expand_vecint_cmov (xops);
1821 /* Emit an integral vector widening sum operations. */
1824 ia64_expand_widen_sum (rtx operands[3], bool unsignedp)
1827 enum machine_mode wmode, mode;
1828 rtx (*unpack_l) (rtx, rtx, rtx);
1829 rtx (*unpack_h) (rtx, rtx, rtx);
1830 rtx (*plus) (rtx, rtx, rtx);
1832 wmode = GET_MODE (operands[0]);
1833 mode = GET_MODE (operands[1]);
1838 unpack_l = gen_unpack1_l;
1839 unpack_h = gen_unpack1_h;
1840 plus = gen_addv4hi3;
1843 unpack_l = gen_unpack2_l;
1844 unpack_h = gen_unpack2_h;
1845 plus = gen_addv2si3;
1851 /* Fill in x with the sign extension of each element in op1. */
1853 x = CONST0_RTX (mode);
1858 x = gen_reg_rtx (mode);
1860 neg = ia64_expand_vecint_compare (LT, mode, x, operands[1],
1865 l = gen_reg_rtx (wmode);
1866 h = gen_reg_rtx (wmode);
1867 s = gen_reg_rtx (wmode);
1869 emit_insn (unpack_l (gen_lowpart (mode, l), operands[1], x));
1870 emit_insn (unpack_h (gen_lowpart (mode, h), operands[1], x));
1871 emit_insn (plus (s, l, operands[2]));
1872 emit_insn (plus (operands[0], h, s));
1875 /* Emit a signed or unsigned V8QI dot product operation. */
1878 ia64_expand_dot_prod_v8qi (rtx operands[4], bool unsignedp)
1880 rtx l1, l2, h1, h2, x1, x2, p1, p2, p3, p4, s1, s2, s3;
1882 /* Fill in x1 and x2 with the sign extension of each element. */
1884 x1 = x2 = CONST0_RTX (V8QImode);
1889 x1 = gen_reg_rtx (V8QImode);
1890 x2 = gen_reg_rtx (V8QImode);
1892 neg = ia64_expand_vecint_compare (LT, V8QImode, x1, operands[1],
1893 CONST0_RTX (V8QImode));
1895 neg = ia64_expand_vecint_compare (LT, V8QImode, x2, operands[2],
1896 CONST0_RTX (V8QImode));
1900 l1 = gen_reg_rtx (V4HImode);
1901 l2 = gen_reg_rtx (V4HImode);
1902 h1 = gen_reg_rtx (V4HImode);
1903 h2 = gen_reg_rtx (V4HImode);
1905 emit_insn (gen_unpack1_l (gen_lowpart (V8QImode, l1), operands[1], x1));
1906 emit_insn (gen_unpack1_l (gen_lowpart (V8QImode, l2), operands[2], x2));
1907 emit_insn (gen_unpack1_h (gen_lowpart (V8QImode, h1), operands[1], x1));
1908 emit_insn (gen_unpack1_h (gen_lowpart (V8QImode, h2), operands[2], x2));
1910 p1 = gen_reg_rtx (V2SImode);
1911 p2 = gen_reg_rtx (V2SImode);
1912 p3 = gen_reg_rtx (V2SImode);
1913 p4 = gen_reg_rtx (V2SImode);
1914 emit_insn (gen_pmpy2_r (p1, l1, l2));
1915 emit_insn (gen_pmpy2_l (p2, l1, l2));
1916 emit_insn (gen_pmpy2_r (p3, h1, h2));
1917 emit_insn (gen_pmpy2_l (p4, h1, h2));
1919 s1 = gen_reg_rtx (V2SImode);
1920 s2 = gen_reg_rtx (V2SImode);
1921 s3 = gen_reg_rtx (V2SImode);
1922 emit_insn (gen_addv2si3 (s1, p1, p2));
1923 emit_insn (gen_addv2si3 (s2, p3, p4));
1924 emit_insn (gen_addv2si3 (s3, s1, operands[3]));
1925 emit_insn (gen_addv2si3 (operands[0], s2, s3));
1928 /* Emit the appropriate sequence for a call. */
1931 ia64_expand_call (rtx retval, rtx addr, rtx nextarg ATTRIBUTE_UNUSED,
1936 addr = XEXP (addr, 0);
1937 addr = convert_memory_address (DImode, addr);
1938 b0 = gen_rtx_REG (DImode, R_BR (0));
1940 /* ??? Should do this for functions known to bind local too. */
1941 if (TARGET_NO_PIC || TARGET_AUTO_PIC)
1944 insn = gen_sibcall_nogp (addr);
1946 insn = gen_call_nogp (addr, b0);
1948 insn = gen_call_value_nogp (retval, addr, b0);
1949 insn = emit_call_insn (insn);
1954 insn = gen_sibcall_gp (addr);
1956 insn = gen_call_gp (addr, b0);
1958 insn = gen_call_value_gp (retval, addr, b0);
1959 insn = emit_call_insn (insn);
1961 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
1965 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), b0);
1969 ia64_reload_gp (void)
1973 if (current_frame_info.reg_save_gp)
1974 tmp = gen_rtx_REG (DImode, current_frame_info.reg_save_gp);
1977 HOST_WIDE_INT offset;
1979 offset = (current_frame_info.spill_cfa_off
1980 + current_frame_info.spill_size);
1981 if (frame_pointer_needed)
1983 tmp = hard_frame_pointer_rtx;
1988 tmp = stack_pointer_rtx;
1989 offset = current_frame_info.total_size - offset;
1992 if (CONST_OK_FOR_I (offset))
1993 emit_insn (gen_adddi3 (pic_offset_table_rtx,
1994 tmp, GEN_INT (offset)));
1997 emit_move_insn (pic_offset_table_rtx, GEN_INT (offset));
1998 emit_insn (gen_adddi3 (pic_offset_table_rtx,
1999 pic_offset_table_rtx, tmp));
2002 tmp = gen_rtx_MEM (DImode, pic_offset_table_rtx);
2005 emit_move_insn (pic_offset_table_rtx, tmp);
2009 ia64_split_call (rtx retval, rtx addr, rtx retaddr, rtx scratch_r,
2010 rtx scratch_b, int noreturn_p, int sibcall_p)
2013 bool is_desc = false;
2015 /* If we find we're calling through a register, then we're actually
2016 calling through a descriptor, so load up the values. */
2017 if (REG_P (addr) && GR_REGNO_P (REGNO (addr)))
2022 /* ??? We are currently constrained to *not* use peep2, because
2023 we can legitimately change the global lifetime of the GP
2024 (in the form of killing where previously live). This is
2025 because a call through a descriptor doesn't use the previous
2026 value of the GP, while a direct call does, and we do not
2027 commit to either form until the split here.
2029 That said, this means that we lack precise life info for
2030 whether ADDR is dead after this call. This is not terribly
2031 important, since we can fix things up essentially for free
2032 with the POST_DEC below, but it's nice to not use it when we
2033 can immediately tell it's not necessary. */
2034 addr_dead_p = ((noreturn_p || sibcall_p
2035 || TEST_HARD_REG_BIT (regs_invalidated_by_call,
2037 && !FUNCTION_ARG_REGNO_P (REGNO (addr)));
2039 /* Load the code address into scratch_b. */
2040 tmp = gen_rtx_POST_INC (Pmode, addr);
2041 tmp = gen_rtx_MEM (Pmode, tmp);
2042 emit_move_insn (scratch_r, tmp);
2043 emit_move_insn (scratch_b, scratch_r);
2045 /* Load the GP address. If ADDR is not dead here, then we must
2046 revert the change made above via the POST_INCREMENT. */
2048 tmp = gen_rtx_POST_DEC (Pmode, addr);
2051 tmp = gen_rtx_MEM (Pmode, tmp);
2052 emit_move_insn (pic_offset_table_rtx, tmp);
2059 insn = gen_sibcall_nogp (addr);
2061 insn = gen_call_value_nogp (retval, addr, retaddr);
2063 insn = gen_call_nogp (addr, retaddr);
2064 emit_call_insn (insn);
2066 if ((!TARGET_CONST_GP || is_desc) && !noreturn_p && !sibcall_p)
2070 /* Expand an atomic operation. We want to perform MEM <CODE>= VAL atomically.
2072 This differs from the generic code in that we know about the zero-extending
2073 properties of cmpxchg, and the zero-extending requirements of ar.ccv. We
2074 also know that ld.acq+cmpxchg.rel equals a full barrier.
2076 The loop we want to generate looks like
2081 new_reg = cmp_reg op val;
2082 cmp_reg = compare-and-swap(mem, old_reg, new_reg)
2083 if (cmp_reg != old_reg)
2086 Note that we only do the plain load from memory once. Subsequent
2087 iterations use the value loaded by the compare-and-swap pattern. */
2090 ia64_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
2091 rtx old_dst, rtx new_dst)
2093 enum machine_mode mode = GET_MODE (mem);
2094 rtx old_reg, new_reg, cmp_reg, ar_ccv, label;
2095 enum insn_code icode;
2097 /* Special case for using fetchadd. */
2098 if ((mode == SImode || mode == DImode)
2099 && (code == PLUS || code == MINUS)
2100 && fetchadd_operand (val, mode))
2103 val = GEN_INT (-INTVAL (val));
2106 old_dst = gen_reg_rtx (mode);
2108 emit_insn (gen_memory_barrier ());
2111 icode = CODE_FOR_fetchadd_acq_si;
2113 icode = CODE_FOR_fetchadd_acq_di;
2114 emit_insn (GEN_FCN (icode) (old_dst, mem, val));
2118 new_reg = expand_simple_binop (mode, PLUS, old_dst, val, new_dst,
2120 if (new_reg != new_dst)
2121 emit_move_insn (new_dst, new_reg);
2126 /* Because of the volatile mem read, we get an ld.acq, which is the
2127 front half of the full barrier. The end half is the cmpxchg.rel. */
2128 gcc_assert (MEM_VOLATILE_P (mem));
2130 old_reg = gen_reg_rtx (DImode);
2131 cmp_reg = gen_reg_rtx (DImode);
2132 label = gen_label_rtx ();
2136 val = simplify_gen_subreg (DImode, val, mode, 0);
2137 emit_insn (gen_extend_insn (cmp_reg, mem, DImode, mode, 1));
2140 emit_move_insn (cmp_reg, mem);
2144 ar_ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
2145 emit_move_insn (old_reg, cmp_reg);
2146 emit_move_insn (ar_ccv, cmp_reg);
2149 emit_move_insn (old_dst, gen_lowpart (mode, cmp_reg));
2154 new_reg = expand_simple_unop (DImode, NOT, new_reg, NULL_RTX, true);
2157 new_reg = expand_simple_binop (DImode, code, new_reg, val, NULL_RTX,
2158 true, OPTAB_DIRECT);
2161 new_reg = gen_lowpart (mode, new_reg);
2163 emit_move_insn (new_dst, new_reg);
2167 case QImode: icode = CODE_FOR_cmpxchg_rel_qi; break;
2168 case HImode: icode = CODE_FOR_cmpxchg_rel_hi; break;
2169 case SImode: icode = CODE_FOR_cmpxchg_rel_si; break;
2170 case DImode: icode = CODE_FOR_cmpxchg_rel_di; break;
2175 emit_insn (GEN_FCN (icode) (cmp_reg, mem, ar_ccv, new_reg));
2177 emit_cmp_and_jump_insns (cmp_reg, old_reg, NE, NULL, DImode, true, label);
2180 /* Begin the assembly file. */
2183 ia64_file_start (void)
2185 /* Variable tracking should be run after all optimizations which change order
2186 of insns. It also needs a valid CFG. This can't be done in
2187 ia64_override_options, because flag_var_tracking is finalized after
2189 ia64_flag_var_tracking = flag_var_tracking;
2190 flag_var_tracking = 0;
2192 default_file_start ();
2193 emit_safe_across_calls ();
2197 emit_safe_across_calls (void)
2199 unsigned int rs, re;
2206 while (rs < 64 && call_used_regs[PR_REG (rs)])
2210 for (re = rs + 1; re < 64 && ! call_used_regs[PR_REG (re)]; re++)
2214 fputs ("\t.pred.safe_across_calls ", asm_out_file);
2218 fputc (',', asm_out_file);
2220 fprintf (asm_out_file, "p%u", rs);
2222 fprintf (asm_out_file, "p%u-p%u", rs, re - 1);
2226 fputc ('\n', asm_out_file);
2229 /* Helper function for ia64_compute_frame_size: find an appropriate general
2230 register to spill some special register to. SPECIAL_SPILL_MASK contains
2231 bits in GR0 to GR31 that have already been allocated by this routine.
2232 TRY_LOCALS is true if we should attempt to locate a local regnum. */
2235 find_gr_spill (int try_locals)
2239 /* If this is a leaf function, first try an otherwise unused
2240 call-clobbered register. */
2241 if (current_function_is_leaf)
2243 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
2244 if (! regs_ever_live[regno]
2245 && call_used_regs[regno]
2246 && ! fixed_regs[regno]
2247 && ! global_regs[regno]
2248 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0)
2250 current_frame_info.gr_used_mask |= 1 << regno;
2257 regno = current_frame_info.n_local_regs;
2258 /* If there is a frame pointer, then we can't use loc79, because
2259 that is HARD_FRAME_POINTER_REGNUM. In particular, see the
2260 reg_name switching code in ia64_expand_prologue. */
2261 if (regno < (80 - frame_pointer_needed))
2263 current_frame_info.n_local_regs = regno + 1;
2264 return LOC_REG (0) + regno;
2268 /* Failed to find a general register to spill to. Must use stack. */
2272 /* In order to make for nice schedules, we try to allocate every temporary
2273 to a different register. We must of course stay away from call-saved,
2274 fixed, and global registers. We must also stay away from registers
2275 allocated in current_frame_info.gr_used_mask, since those include regs
2276 used all through the prologue.
2278 Any register allocated here must be used immediately. The idea is to
2279 aid scheduling, not to solve data flow problems. */
2281 static int last_scratch_gr_reg;
2284 next_scratch_gr_reg (void)
2288 for (i = 0; i < 32; ++i)
2290 regno = (last_scratch_gr_reg + i + 1) & 31;
2291 if (call_used_regs[regno]
2292 && ! fixed_regs[regno]
2293 && ! global_regs[regno]
2294 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0)
2296 last_scratch_gr_reg = regno;
2301 /* There must be _something_ available. */
2305 /* Helper function for ia64_compute_frame_size, called through
2306 diddle_return_value. Mark REG in current_frame_info.gr_used_mask. */
2309 mark_reg_gr_used_mask (rtx reg, void *data ATTRIBUTE_UNUSED)
2311 unsigned int regno = REGNO (reg);
2314 unsigned int i, n = hard_regno_nregs[regno][GET_MODE (reg)];
2315 for (i = 0; i < n; ++i)
2316 current_frame_info.gr_used_mask |= 1 << (regno + i);
2320 /* Returns the number of bytes offset between the frame pointer and the stack
2321 pointer for the current function. SIZE is the number of bytes of space
2322 needed for local variables. */
2325 ia64_compute_frame_size (HOST_WIDE_INT size)
2327 HOST_WIDE_INT total_size;
2328 HOST_WIDE_INT spill_size = 0;
2329 HOST_WIDE_INT extra_spill_size = 0;
2330 HOST_WIDE_INT pretend_args_size;
2333 int spilled_gr_p = 0;
2334 int spilled_fr_p = 0;
2338 if (current_frame_info.initialized)
2341 memset (¤t_frame_info, 0, sizeof current_frame_info);
2342 CLEAR_HARD_REG_SET (mask);
2344 /* Don't allocate scratches to the return register. */
2345 diddle_return_value (mark_reg_gr_used_mask, NULL);
2347 /* Don't allocate scratches to the EH scratch registers. */
2348 if (cfun->machine->ia64_eh_epilogue_sp)
2349 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_sp, NULL);
2350 if (cfun->machine->ia64_eh_epilogue_bsp)
2351 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_bsp, NULL);
2353 /* Find the size of the register stack frame. We have only 80 local
2354 registers, because we reserve 8 for the inputs and 8 for the
2357 /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed,
2358 since we'll be adjusting that down later. */
2359 regno = LOC_REG (78) + ! frame_pointer_needed;
2360 for (; regno >= LOC_REG (0); regno--)
2361 if (regs_ever_live[regno])
2363 current_frame_info.n_local_regs = regno - LOC_REG (0) + 1;
2365 /* For functions marked with the syscall_linkage attribute, we must mark
2366 all eight input registers as in use, so that locals aren't visible to
2369 if (cfun->machine->n_varargs > 0
2370 || lookup_attribute ("syscall_linkage",
2371 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
2372 current_frame_info.n_input_regs = 8;
2375 for (regno = IN_REG (7); regno >= IN_REG (0); regno--)
2376 if (regs_ever_live[regno])
2378 current_frame_info.n_input_regs = regno - IN_REG (0) + 1;
2381 for (regno = OUT_REG (7); regno >= OUT_REG (0); regno--)
2382 if (regs_ever_live[regno])
2384 i = regno - OUT_REG (0) + 1;
2386 #ifndef PROFILE_HOOK
2387 /* When -p profiling, we need one output register for the mcount argument.
2388 Likewise for -a profiling for the bb_init_func argument. For -ax
2389 profiling, we need two output registers for the two bb_init_trace_func
2391 if (current_function_profile)
2394 current_frame_info.n_output_regs = i;
2396 /* ??? No rotating register support yet. */
2397 current_frame_info.n_rotate_regs = 0;
2399 /* Discover which registers need spilling, and how much room that
2400 will take. Begin with floating point and general registers,
2401 which will always wind up on the stack. */
2403 for (regno = FR_REG (2); regno <= FR_REG (127); regno++)
2404 if (regs_ever_live[regno] && ! call_used_regs[regno])
2406 SET_HARD_REG_BIT (mask, regno);
2412 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
2413 if (regs_ever_live[regno] && ! call_used_regs[regno])
2415 SET_HARD_REG_BIT (mask, regno);
2421 for (regno = BR_REG (1); regno <= BR_REG (7); regno++)
2422 if (regs_ever_live[regno] && ! call_used_regs[regno])
2424 SET_HARD_REG_BIT (mask, regno);
2429 /* Now come all special registers that might get saved in other
2430 general registers. */
2432 if (frame_pointer_needed)
2434 current_frame_info.reg_fp = find_gr_spill (1);
2435 /* If we did not get a register, then we take LOC79. This is guaranteed
2436 to be free, even if regs_ever_live is already set, because this is
2437 HARD_FRAME_POINTER_REGNUM. This requires incrementing n_local_regs,
2438 as we don't count loc79 above. */
2439 if (current_frame_info.reg_fp == 0)
2441 current_frame_info.reg_fp = LOC_REG (79);
2442 current_frame_info.n_local_regs++;
2446 if (! current_function_is_leaf)
2448 /* Emit a save of BR0 if we call other functions. Do this even
2449 if this function doesn't return, as EH depends on this to be
2450 able to unwind the stack. */
2451 SET_HARD_REG_BIT (mask, BR_REG (0));
2453 current_frame_info.reg_save_b0 = find_gr_spill (1);
2454 if (current_frame_info.reg_save_b0 == 0)
2460 /* Similarly for ar.pfs. */
2461 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
2462 current_frame_info.reg_save_ar_pfs = find_gr_spill (1);
2463 if (current_frame_info.reg_save_ar_pfs == 0)
2465 extra_spill_size += 8;
2469 /* Similarly for gp. Note that if we're calling setjmp, the stacked
2470 registers are clobbered, so we fall back to the stack. */
2471 current_frame_info.reg_save_gp
2472 = (current_function_calls_setjmp ? 0 : find_gr_spill (1));
2473 if (current_frame_info.reg_save_gp == 0)
2475 SET_HARD_REG_BIT (mask, GR_REG (1));
2482 if (regs_ever_live[BR_REG (0)] && ! call_used_regs[BR_REG (0)])
2484 SET_HARD_REG_BIT (mask, BR_REG (0));
2489 if (regs_ever_live[AR_PFS_REGNUM])
2491 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
2492 current_frame_info.reg_save_ar_pfs = find_gr_spill (1);
2493 if (current_frame_info.reg_save_ar_pfs == 0)
2495 extra_spill_size += 8;
2501 /* Unwind descriptor hackery: things are most efficient if we allocate
2502 consecutive GR save registers for RP, PFS, FP in that order. However,
2503 it is absolutely critical that FP get the only hard register that's
2504 guaranteed to be free, so we allocated it first. If all three did
2505 happen to be allocated hard regs, and are consecutive, rearrange them
2506 into the preferred order now. */
2507 if (current_frame_info.reg_fp != 0
2508 && current_frame_info.reg_save_b0 == current_frame_info.reg_fp + 1
2509 && current_frame_info.reg_save_ar_pfs == current_frame_info.reg_fp + 2)
2511 current_frame_info.reg_save_b0 = current_frame_info.reg_fp;
2512 current_frame_info.reg_save_ar_pfs = current_frame_info.reg_fp + 1;
2513 current_frame_info.reg_fp = current_frame_info.reg_fp + 2;
2516 /* See if we need to store the predicate register block. */
2517 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
2518 if (regs_ever_live[regno] && ! call_used_regs[regno])
2520 if (regno <= PR_REG (63))
2522 SET_HARD_REG_BIT (mask, PR_REG (0));
2523 current_frame_info.reg_save_pr = find_gr_spill (1);
2524 if (current_frame_info.reg_save_pr == 0)
2526 extra_spill_size += 8;
2530 /* ??? Mark them all as used so that register renaming and such
2531 are free to use them. */
2532 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
2533 regs_ever_live[regno] = 1;
2536 /* If we're forced to use st8.spill, we're forced to save and restore
2537 ar.unat as well. The check for existing liveness allows inline asm
2538 to touch ar.unat. */
2539 if (spilled_gr_p || cfun->machine->n_varargs
2540 || regs_ever_live[AR_UNAT_REGNUM])
2542 regs_ever_live[AR_UNAT_REGNUM] = 1;
2543 SET_HARD_REG_BIT (mask, AR_UNAT_REGNUM);
2544 current_frame_info.reg_save_ar_unat = find_gr_spill (spill_size == 0);
2545 if (current_frame_info.reg_save_ar_unat == 0)
2547 extra_spill_size += 8;
2552 if (regs_ever_live[AR_LC_REGNUM])
2554 SET_HARD_REG_BIT (mask, AR_LC_REGNUM);
2555 current_frame_info.reg_save_ar_lc = find_gr_spill (spill_size == 0);
2556 if (current_frame_info.reg_save_ar_lc == 0)
2558 extra_spill_size += 8;
2563 /* If we have an odd number of words of pretend arguments written to
2564 the stack, then the FR save area will be unaligned. We round the
2565 size of this area up to keep things 16 byte aligned. */
2567 pretend_args_size = IA64_STACK_ALIGN (current_function_pretend_args_size);
2569 pretend_args_size = current_function_pretend_args_size;
2571 total_size = (spill_size + extra_spill_size + size + pretend_args_size
2572 + current_function_outgoing_args_size);
2573 total_size = IA64_STACK_ALIGN (total_size);
2575 /* We always use the 16-byte scratch area provided by the caller, but
2576 if we are a leaf function, there's no one to which we need to provide
2578 if (current_function_is_leaf)
2579 total_size = MAX (0, total_size - 16);
2581 current_frame_info.total_size = total_size;
2582 current_frame_info.spill_cfa_off = pretend_args_size - 16;
2583 current_frame_info.spill_size = spill_size;
2584 current_frame_info.extra_spill_size = extra_spill_size;
2585 COPY_HARD_REG_SET (current_frame_info.mask, mask);
2586 current_frame_info.n_spilled = n_spilled;
2587 current_frame_info.initialized = reload_completed;
2590 /* Compute the initial difference between the specified pair of registers. */
2593 ia64_initial_elimination_offset (int from, int to)
2595 HOST_WIDE_INT offset;
2597 ia64_compute_frame_size (get_frame_size ());
2600 case FRAME_POINTER_REGNUM:
2603 case HARD_FRAME_POINTER_REGNUM:
2604 if (current_function_is_leaf)
2605 offset = -current_frame_info.total_size;
2607 offset = -(current_frame_info.total_size
2608 - current_function_outgoing_args_size - 16);
2611 case STACK_POINTER_REGNUM:
2612 if (current_function_is_leaf)
2615 offset = 16 + current_function_outgoing_args_size;
2623 case ARG_POINTER_REGNUM:
2624 /* Arguments start above the 16 byte save area, unless stdarg
2625 in which case we store through the 16 byte save area. */
2628 case HARD_FRAME_POINTER_REGNUM:
2629 offset = 16 - current_function_pretend_args_size;
2632 case STACK_POINTER_REGNUM:
2633 offset = (current_frame_info.total_size
2634 + 16 - current_function_pretend_args_size);
2649 /* If there are more than a trivial number of register spills, we use
2650 two interleaved iterators so that we can get two memory references
2653 In order to simplify things in the prologue and epilogue expanders,
2654 we use helper functions to fix up the memory references after the
2655 fact with the appropriate offsets to a POST_MODIFY memory mode.
2656 The following data structure tracks the state of the two iterators
2657 while insns are being emitted. */
2659 struct spill_fill_data
2661 rtx init_after; /* point at which to emit initializations */
2662 rtx init_reg[2]; /* initial base register */
2663 rtx iter_reg[2]; /* the iterator registers */
2664 rtx *prev_addr[2]; /* address of last memory use */
2665 rtx prev_insn[2]; /* the insn corresponding to prev_addr */
2666 HOST_WIDE_INT prev_off[2]; /* last offset */
2667 int n_iter; /* number of iterators in use */
2668 int next_iter; /* next iterator to use */
2669 unsigned int save_gr_used_mask;
2672 static struct spill_fill_data spill_fill_data;
2675 setup_spill_pointers (int n_spills, rtx init_reg, HOST_WIDE_INT cfa_off)
2679 spill_fill_data.init_after = get_last_insn ();
2680 spill_fill_data.init_reg[0] = init_reg;
2681 spill_fill_data.init_reg[1] = init_reg;
2682 spill_fill_data.prev_addr[0] = NULL;
2683 spill_fill_data.prev_addr[1] = NULL;
2684 spill_fill_data.prev_insn[0] = NULL;
2685 spill_fill_data.prev_insn[1] = NULL;
2686 spill_fill_data.prev_off[0] = cfa_off;
2687 spill_fill_data.prev_off[1] = cfa_off;
2688 spill_fill_data.next_iter = 0;
2689 spill_fill_data.save_gr_used_mask = current_frame_info.gr_used_mask;
2691 spill_fill_data.n_iter = 1 + (n_spills > 2);
2692 for (i = 0; i < spill_fill_data.n_iter; ++i)
2694 int regno = next_scratch_gr_reg ();
2695 spill_fill_data.iter_reg[i] = gen_rtx_REG (DImode, regno);
2696 current_frame_info.gr_used_mask |= 1 << regno;
2701 finish_spill_pointers (void)
2703 current_frame_info.gr_used_mask = spill_fill_data.save_gr_used_mask;
2707 spill_restore_mem (rtx reg, HOST_WIDE_INT cfa_off)
2709 int iter = spill_fill_data.next_iter;
2710 HOST_WIDE_INT disp = spill_fill_data.prev_off[iter] - cfa_off;
2711 rtx disp_rtx = GEN_INT (disp);
2714 if (spill_fill_data.prev_addr[iter])
2716 if (CONST_OK_FOR_N (disp))
2718 *spill_fill_data.prev_addr[iter]
2719 = gen_rtx_POST_MODIFY (DImode, spill_fill_data.iter_reg[iter],
2720 gen_rtx_PLUS (DImode,
2721 spill_fill_data.iter_reg[iter],
2723 REG_NOTES (spill_fill_data.prev_insn[iter])
2724 = gen_rtx_EXPR_LIST (REG_INC, spill_fill_data.iter_reg[iter],
2725 REG_NOTES (spill_fill_data.prev_insn[iter]));
2729 /* ??? Could use register post_modify for loads. */
2730 if (! CONST_OK_FOR_I (disp))
2732 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
2733 emit_move_insn (tmp, disp_rtx);
2736 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
2737 spill_fill_data.iter_reg[iter], disp_rtx));
2740 /* Micro-optimization: if we've created a frame pointer, it's at
2741 CFA 0, which may allow the real iterator to be initialized lower,
2742 slightly increasing parallelism. Also, if there are few saves
2743 it may eliminate the iterator entirely. */
2745 && spill_fill_data.init_reg[iter] == stack_pointer_rtx
2746 && frame_pointer_needed)
2748 mem = gen_rtx_MEM (GET_MODE (reg), hard_frame_pointer_rtx);
2749 set_mem_alias_set (mem, get_varargs_alias_set ());
2757 seq = gen_movdi (spill_fill_data.iter_reg[iter],
2758 spill_fill_data.init_reg[iter]);
2763 if (! CONST_OK_FOR_I (disp))
2765 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
2766 emit_move_insn (tmp, disp_rtx);
2770 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
2771 spill_fill_data.init_reg[iter],
2778 /* Careful for being the first insn in a sequence. */
2779 if (spill_fill_data.init_after)
2780 insn = emit_insn_after (seq, spill_fill_data.init_after);
2783 rtx first = get_insns ();
2785 insn = emit_insn_before (seq, first);
2787 insn = emit_insn (seq);
2789 spill_fill_data.init_after = insn;
2791 /* If DISP is 0, we may or may not have a further adjustment
2792 afterward. If we do, then the load/store insn may be modified
2793 to be a post-modify. If we don't, then this copy may be
2794 eliminated by copyprop_hardreg_forward, which makes this
2795 insn garbage, which runs afoul of the sanity check in
2796 propagate_one_insn. So mark this insn as legal to delete. */
2798 REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx,
2802 mem = gen_rtx_MEM (GET_MODE (reg), spill_fill_data.iter_reg[iter]);
2804 /* ??? Not all of the spills are for varargs, but some of them are.
2805 The rest of the spills belong in an alias set of their own. But
2806 it doesn't actually hurt to include them here. */
2807 set_mem_alias_set (mem, get_varargs_alias_set ());
2809 spill_fill_data.prev_addr[iter] = &XEXP (mem, 0);
2810 spill_fill_data.prev_off[iter] = cfa_off;
2812 if (++iter >= spill_fill_data.n_iter)
2814 spill_fill_data.next_iter = iter;
2820 do_spill (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off,
2823 int iter = spill_fill_data.next_iter;
2826 mem = spill_restore_mem (reg, cfa_off);
2827 insn = emit_insn ((*move_fn) (mem, reg, GEN_INT (cfa_off)));
2828 spill_fill_data.prev_insn[iter] = insn;
2835 RTX_FRAME_RELATED_P (insn) = 1;
2837 /* Don't even pretend that the unwind code can intuit its way
2838 through a pair of interleaved post_modify iterators. Just
2839 provide the correct answer. */
2841 if (frame_pointer_needed)
2843 base = hard_frame_pointer_rtx;
2848 base = stack_pointer_rtx;
2849 off = current_frame_info.total_size - cfa_off;
2853 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2854 gen_rtx_SET (VOIDmode,
2855 gen_rtx_MEM (GET_MODE (reg),
2856 plus_constant (base, off)),
2863 do_restore (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off)
2865 int iter = spill_fill_data.next_iter;
2868 insn = emit_insn ((*move_fn) (reg, spill_restore_mem (reg, cfa_off),
2869 GEN_INT (cfa_off)));
2870 spill_fill_data.prev_insn[iter] = insn;
2873 /* Wrapper functions that discards the CONST_INT spill offset. These
2874 exist so that we can give gr_spill/gr_fill the offset they need and
2875 use a consistent function interface. */
2878 gen_movdi_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
2880 return gen_movdi (dest, src);
2884 gen_fr_spill_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
2886 return gen_fr_spill (dest, src);
2890 gen_fr_restore_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
2892 return gen_fr_restore (dest, src);
2895 /* Called after register allocation to add any instructions needed for the
2896 prologue. Using a prologue insn is favored compared to putting all of the
2897 instructions in output_function_prologue(), since it allows the scheduler
2898 to intermix instructions with the saves of the caller saved registers. In
2899 some cases, it might be necessary to emit a barrier instruction as the last
2900 insn to prevent such scheduling.
2902 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
2903 so that the debug info generation code can handle them properly.
2905 The register save area is layed out like so:
2907 [ varargs spill area ]
2908 [ fr register spill area ]
2909 [ br register spill area ]
2910 [ ar register spill area ]
2911 [ pr register spill area ]
2912 [ gr register spill area ] */
2914 /* ??? Get inefficient code when the frame size is larger than can fit in an
2915 adds instruction. */
2918 ia64_expand_prologue (void)
2920 rtx insn, ar_pfs_save_reg, ar_unat_save_reg;
2921 int i, epilogue_p, regno, alt_regno, cfa_off, n_varargs;
2924 ia64_compute_frame_size (get_frame_size ());
2925 last_scratch_gr_reg = 15;
2927 /* If there is no epilogue, then we don't need some prologue insns.
2928 We need to avoid emitting the dead prologue insns, because flow
2929 will complain about them. */
2935 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
2936 if ((e->flags & EDGE_FAKE) == 0
2937 && (e->flags & EDGE_FALLTHRU) != 0)
2939 epilogue_p = (e != NULL);
2944 /* Set the local, input, and output register names. We need to do this
2945 for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in
2946 half. If we use in/loc/out register names, then we get assembler errors
2947 in crtn.S because there is no alloc insn or regstk directive in there. */
2948 if (! TARGET_REG_NAMES)
2950 int inputs = current_frame_info.n_input_regs;
2951 int locals = current_frame_info.n_local_regs;
2952 int outputs = current_frame_info.n_output_regs;
2954 for (i = 0; i < inputs; i++)
2955 reg_names[IN_REG (i)] = ia64_reg_numbers[i];
2956 for (i = 0; i < locals; i++)
2957 reg_names[LOC_REG (i)] = ia64_reg_numbers[inputs + i];
2958 for (i = 0; i < outputs; i++)
2959 reg_names[OUT_REG (i)] = ia64_reg_numbers[inputs + locals + i];
2962 /* Set the frame pointer register name. The regnum is logically loc79,
2963 but of course we'll not have allocated that many locals. Rather than
2964 worrying about renumbering the existing rtxs, we adjust the name. */
2965 /* ??? This code means that we can never use one local register when
2966 there is a frame pointer. loc79 gets wasted in this case, as it is
2967 renamed to a register that will never be used. See also the try_locals
2968 code in find_gr_spill. */
2969 if (current_frame_info.reg_fp)
2971 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
2972 reg_names[HARD_FRAME_POINTER_REGNUM]
2973 = reg_names[current_frame_info.reg_fp];
2974 reg_names[current_frame_info.reg_fp] = tmp;
2977 /* We don't need an alloc instruction if we've used no outputs or locals. */
2978 if (current_frame_info.n_local_regs == 0
2979 && current_frame_info.n_output_regs == 0
2980 && current_frame_info.n_input_regs <= current_function_args_info.int_regs
2981 && !TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM))
2983 /* If there is no alloc, but there are input registers used, then we
2984 need a .regstk directive. */
2985 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
2986 ar_pfs_save_reg = NULL_RTX;
2990 current_frame_info.need_regstk = 0;
2992 if (current_frame_info.reg_save_ar_pfs)
2993 regno = current_frame_info.reg_save_ar_pfs;
2995 regno = next_scratch_gr_reg ();
2996 ar_pfs_save_reg = gen_rtx_REG (DImode, regno);
2998 insn = emit_insn (gen_alloc (ar_pfs_save_reg,
2999 GEN_INT (current_frame_info.n_input_regs),
3000 GEN_INT (current_frame_info.n_local_regs),
3001 GEN_INT (current_frame_info.n_output_regs),
3002 GEN_INT (current_frame_info.n_rotate_regs)));
3003 RTX_FRAME_RELATED_P (insn) = (current_frame_info.reg_save_ar_pfs != 0);
3006 /* Set up frame pointer, stack pointer, and spill iterators. */
3008 n_varargs = cfun->machine->n_varargs;
3009 setup_spill_pointers (current_frame_info.n_spilled + n_varargs,
3010 stack_pointer_rtx, 0);
3012 if (frame_pointer_needed)
3014 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
3015 RTX_FRAME_RELATED_P (insn) = 1;
3018 if (current_frame_info.total_size != 0)
3020 rtx frame_size_rtx = GEN_INT (- current_frame_info.total_size);
3023 if (CONST_OK_FOR_I (- current_frame_info.total_size))
3024 offset = frame_size_rtx;
3027 regno = next_scratch_gr_reg ();
3028 offset = gen_rtx_REG (DImode, regno);
3029 emit_move_insn (offset, frame_size_rtx);
3032 insn = emit_insn (gen_adddi3 (stack_pointer_rtx,
3033 stack_pointer_rtx, offset));
3035 if (! frame_pointer_needed)
3037 RTX_FRAME_RELATED_P (insn) = 1;
3038 if (GET_CODE (offset) != CONST_INT)
3041 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3042 gen_rtx_SET (VOIDmode,
3044 gen_rtx_PLUS (DImode,
3051 /* ??? At this point we must generate a magic insn that appears to
3052 modify the stack pointer, the frame pointer, and all spill
3053 iterators. This would allow the most scheduling freedom. For
3054 now, just hard stop. */
3055 emit_insn (gen_blockage ());
3058 /* Must copy out ar.unat before doing any integer spills. */
3059 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
3061 if (current_frame_info.reg_save_ar_unat)
3063 = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_unat);
3066 alt_regno = next_scratch_gr_reg ();
3067 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
3068 current_frame_info.gr_used_mask |= 1 << alt_regno;
3071 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3072 insn = emit_move_insn (ar_unat_save_reg, reg);
3073 RTX_FRAME_RELATED_P (insn) = (current_frame_info.reg_save_ar_unat != 0);
3075 /* Even if we're not going to generate an epilogue, we still
3076 need to save the register so that EH works. */
3077 if (! epilogue_p && current_frame_info.reg_save_ar_unat)
3078 emit_insn (gen_prologue_use (ar_unat_save_reg));
3081 ar_unat_save_reg = NULL_RTX;
3083 /* Spill all varargs registers. Do this before spilling any GR registers,
3084 since we want the UNAT bits for the GR registers to override the UNAT
3085 bits from varargs, which we don't care about. */
3088 for (regno = GR_ARG_FIRST + 7; n_varargs > 0; --n_varargs, --regno)
3090 reg = gen_rtx_REG (DImode, regno);
3091 do_spill (gen_gr_spill, reg, cfa_off += 8, NULL_RTX);
3094 /* Locate the bottom of the register save area. */
3095 cfa_off = (current_frame_info.spill_cfa_off
3096 + current_frame_info.spill_size
3097 + current_frame_info.extra_spill_size);
3099 /* Save the predicate register block either in a register or in memory. */
3100 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
3102 reg = gen_rtx_REG (DImode, PR_REG (0));
3103 if (current_frame_info.reg_save_pr != 0)
3105 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_pr);
3106 insn = emit_move_insn (alt_reg, reg);
3108 /* ??? Denote pr spill/fill by a DImode move that modifies all
3109 64 hard registers. */
3110 RTX_FRAME_RELATED_P (insn) = 1;
3112 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3113 gen_rtx_SET (VOIDmode, alt_reg, reg),
3116 /* Even if we're not going to generate an epilogue, we still
3117 need to save the register so that EH works. */
3119 emit_insn (gen_prologue_use (alt_reg));
3123 alt_regno = next_scratch_gr_reg ();
3124 alt_reg = gen_rtx_REG (DImode, alt_regno);
3125 insn = emit_move_insn (alt_reg, reg);
3126 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3131 /* Handle AR regs in numerical order. All of them get special handling. */
3132 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM)
3133 && current_frame_info.reg_save_ar_unat == 0)
3135 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3136 do_spill (gen_movdi_x, ar_unat_save_reg, cfa_off, reg);
3140 /* The alloc insn already copied ar.pfs into a general register. The
3141 only thing we have to do now is copy that register to a stack slot
3142 if we'd not allocated a local register for the job. */
3143 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM)
3144 && current_frame_info.reg_save_ar_pfs == 0)
3146 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3147 do_spill (gen_movdi_x, ar_pfs_save_reg, cfa_off, reg);
3151 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
3153 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
3154 if (current_frame_info.reg_save_ar_lc != 0)
3156 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_lc);
3157 insn = emit_move_insn (alt_reg, reg);
3158 RTX_FRAME_RELATED_P (insn) = 1;
3160 /* Even if we're not going to generate an epilogue, we still
3161 need to save the register so that EH works. */
3163 emit_insn (gen_prologue_use (alt_reg));
3167 alt_regno = next_scratch_gr_reg ();
3168 alt_reg = gen_rtx_REG (DImode, alt_regno);
3169 emit_move_insn (alt_reg, reg);
3170 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3175 if (current_frame_info.reg_save_gp)
3177 insn = emit_move_insn (gen_rtx_REG (DImode,
3178 current_frame_info.reg_save_gp),
3179 pic_offset_table_rtx);
3180 /* We don't know for sure yet if this is actually needed, since
3181 we've not split the PIC call patterns. If all of the calls
3182 are indirect, and not followed by any uses of the gp, then
3183 this save is dead. Allow it to go away. */
3185 = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx, REG_NOTES (insn));
3188 /* We should now be at the base of the gr/br/fr spill area. */
3189 gcc_assert (cfa_off == (current_frame_info.spill_cfa_off
3190 + current_frame_info.spill_size));
3192 /* Spill all general registers. */
3193 for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
3194 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3196 reg = gen_rtx_REG (DImode, regno);
3197 do_spill (gen_gr_spill, reg, cfa_off, reg);
3201 /* Handle BR0 specially -- it may be getting stored permanently in
3202 some GR register. */
3203 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3205 reg = gen_rtx_REG (DImode, BR_REG (0));
3206 if (current_frame_info.reg_save_b0 != 0)
3208 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
3209 insn = emit_move_insn (alt_reg, reg);
3210 RTX_FRAME_RELATED_P (insn) = 1;
3212 /* Even if we're not going to generate an epilogue, we still
3213 need to save the register so that EH works. */
3215 emit_insn (gen_prologue_use (alt_reg));
3219 alt_regno = next_scratch_gr_reg ();
3220 alt_reg = gen_rtx_REG (DImode, alt_regno);
3221 emit_move_insn (alt_reg, reg);
3222 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3227 /* Spill the rest of the BR registers. */
3228 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
3229 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3231 alt_regno = next_scratch_gr_reg ();
3232 alt_reg = gen_rtx_REG (DImode, alt_regno);
3233 reg = gen_rtx_REG (DImode, regno);
3234 emit_move_insn (alt_reg, reg);
3235 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3239 /* Align the frame and spill all FR registers. */
3240 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
3241 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3243 gcc_assert (!(cfa_off & 15));
3244 reg = gen_rtx_REG (XFmode, regno);
3245 do_spill (gen_fr_spill_x, reg, cfa_off, reg);
3249 gcc_assert (cfa_off == current_frame_info.spill_cfa_off);
3251 finish_spill_pointers ();
3254 /* Called after register allocation to add any instructions needed for the
3255 epilogue. Using an epilogue insn is favored compared to putting all of the
3256 instructions in output_function_prologue(), since it allows the scheduler
3257 to intermix instructions with the saves of the caller saved registers. In
3258 some cases, it might be necessary to emit a barrier instruction as the last
3259 insn to prevent such scheduling. */
3262 ia64_expand_epilogue (int sibcall_p)
3264 rtx insn, reg, alt_reg, ar_unat_save_reg;
3265 int regno, alt_regno, cfa_off;
3267 ia64_compute_frame_size (get_frame_size ());
3269 /* If there is a frame pointer, then we use it instead of the stack
3270 pointer, so that the stack pointer does not need to be valid when
3271 the epilogue starts. See EXIT_IGNORE_STACK. */
3272 if (frame_pointer_needed)
3273 setup_spill_pointers (current_frame_info.n_spilled,
3274 hard_frame_pointer_rtx, 0);
3276 setup_spill_pointers (current_frame_info.n_spilled, stack_pointer_rtx,
3277 current_frame_info.total_size);
3279 if (current_frame_info.total_size != 0)
3281 /* ??? At this point we must generate a magic insn that appears to
3282 modify the spill iterators and the frame pointer. This would
3283 allow the most scheduling freedom. For now, just hard stop. */
3284 emit_insn (gen_blockage ());
3287 /* Locate the bottom of the register save area. */
3288 cfa_off = (current_frame_info.spill_cfa_off
3289 + current_frame_info.spill_size
3290 + current_frame_info.extra_spill_size);
3292 /* Restore the predicate registers. */
3293 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
3295 if (current_frame_info.reg_save_pr != 0)
3296 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_pr);
3299 alt_regno = next_scratch_gr_reg ();
3300 alt_reg = gen_rtx_REG (DImode, alt_regno);
3301 do_restore (gen_movdi_x, alt_reg, cfa_off);
3304 reg = gen_rtx_REG (DImode, PR_REG (0));
3305 emit_move_insn (reg, alt_reg);
3308 /* Restore the application registers. */
3310 /* Load the saved unat from the stack, but do not restore it until
3311 after the GRs have been restored. */
3312 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
3314 if (current_frame_info.reg_save_ar_unat != 0)
3316 = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_unat);
3319 alt_regno = next_scratch_gr_reg ();
3320 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
3321 current_frame_info.gr_used_mask |= 1 << alt_regno;
3322 do_restore (gen_movdi_x, ar_unat_save_reg, cfa_off);
3327 ar_unat_save_reg = NULL_RTX;
3329 if (current_frame_info.reg_save_ar_pfs != 0)
3331 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_pfs);
3332 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3333 emit_move_insn (reg, alt_reg);
3335 else if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM))
3337 alt_regno = next_scratch_gr_reg ();
3338 alt_reg = gen_rtx_REG (DImode, alt_regno);
3339 do_restore (gen_movdi_x, alt_reg, cfa_off);
3341 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3342 emit_move_insn (reg, alt_reg);
3345 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
3347 if (current_frame_info.reg_save_ar_lc != 0)
3348 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_lc);
3351 alt_regno = next_scratch_gr_reg ();
3352 alt_reg = gen_rtx_REG (DImode, alt_regno);
3353 do_restore (gen_movdi_x, alt_reg, cfa_off);
3356 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
3357 emit_move_insn (reg, alt_reg);
3360 /* We should now be at the base of the gr/br/fr spill area. */
3361 gcc_assert (cfa_off == (current_frame_info.spill_cfa_off
3362 + current_frame_info.spill_size));
3364 /* The GP may be stored on the stack in the prologue, but it's
3365 never restored in the epilogue. Skip the stack slot. */
3366 if (TEST_HARD_REG_BIT (current_frame_info.mask, GR_REG (1)))
3369 /* Restore all general registers. */
3370 for (regno = GR_REG (2); regno <= GR_REG (31); ++regno)
3371 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3373 reg = gen_rtx_REG (DImode, regno);
3374 do_restore (gen_gr_restore, reg, cfa_off);
3378 /* Restore the branch registers. Handle B0 specially, as it may
3379 have gotten stored in some GR register. */
3380 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3382 if (current_frame_info.reg_save_b0 != 0)
3383 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
3386 alt_regno = next_scratch_gr_reg ();
3387 alt_reg = gen_rtx_REG (DImode, alt_regno);
3388 do_restore (gen_movdi_x, alt_reg, cfa_off);
3391 reg = gen_rtx_REG (DImode, BR_REG (0));
3392 emit_move_insn (reg, alt_reg);
3395 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
3396 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3398 alt_regno = next_scratch_gr_reg ();
3399 alt_reg = gen_rtx_REG (DImode, alt_regno);
3400 do_restore (gen_movdi_x, alt_reg, cfa_off);
3402 reg = gen_rtx_REG (DImode, regno);
3403 emit_move_insn (reg, alt_reg);
3406 /* Restore floating point registers. */
3407 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
3408 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3410 gcc_assert (!(cfa_off & 15));
3411 reg = gen_rtx_REG (XFmode, regno);
3412 do_restore (gen_fr_restore_x, reg, cfa_off);
3416 /* Restore ar.unat for real. */
3417 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
3419 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3420 emit_move_insn (reg, ar_unat_save_reg);
3423 gcc_assert (cfa_off == current_frame_info.spill_cfa_off);
3425 finish_spill_pointers ();
3427 if (current_frame_info.total_size || cfun->machine->ia64_eh_epilogue_sp)
3429 /* ??? At this point we must generate a magic insn that appears to
3430 modify the spill iterators, the stack pointer, and the frame
3431 pointer. This would allow the most scheduling freedom. For now,
3433 emit_insn (gen_blockage ());
3436 if (cfun->machine->ia64_eh_epilogue_sp)
3437 emit_move_insn (stack_pointer_rtx, cfun->machine->ia64_eh_epilogue_sp);
3438 else if (frame_pointer_needed)
3440 insn = emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
3441 RTX_FRAME_RELATED_P (insn) = 1;
3443 else if (current_frame_info.total_size)
3445 rtx offset, frame_size_rtx;
3447 frame_size_rtx = GEN_INT (current_frame_info.total_size);
3448 if (CONST_OK_FOR_I (current_frame_info.total_size))
3449 offset = frame_size_rtx;
3452 regno = next_scratch_gr_reg ();
3453 offset = gen_rtx_REG (DImode, regno);
3454 emit_move_insn (offset, frame_size_rtx);
3457 insn = emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
3460 RTX_FRAME_RELATED_P (insn) = 1;
3461 if (GET_CODE (offset) != CONST_INT)
3464 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3465 gen_rtx_SET (VOIDmode,
3467 gen_rtx_PLUS (DImode,
3474 if (cfun->machine->ia64_eh_epilogue_bsp)
3475 emit_insn (gen_set_bsp (cfun->machine->ia64_eh_epilogue_bsp));
3478 emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode, BR_REG (0))));
3481 int fp = GR_REG (2);
3482 /* We need a throw away register here, r0 and r1 are reserved, so r2 is the
3483 first available call clobbered register. If there was a frame_pointer
3484 register, we may have swapped the names of r2 and HARD_FRAME_POINTER_REGNUM,
3485 so we have to make sure we're using the string "r2" when emitting
3486 the register name for the assembler. */
3487 if (current_frame_info.reg_fp && current_frame_info.reg_fp == GR_REG (2))
3488 fp = HARD_FRAME_POINTER_REGNUM;
3490 /* We must emit an alloc to force the input registers to become output
3491 registers. Otherwise, if the callee tries to pass its parameters
3492 through to another call without an intervening alloc, then these
3494 /* ??? We don't need to preserve all input registers. We only need to
3495 preserve those input registers used as arguments to the sibling call.
3496 It is unclear how to compute that number here. */
3497 if (current_frame_info.n_input_regs != 0)
3499 rtx n_inputs = GEN_INT (current_frame_info.n_input_regs);
3500 insn = emit_insn (gen_alloc (gen_rtx_REG (DImode, fp),
3501 const0_rtx, const0_rtx,
3502 n_inputs, const0_rtx));
3503 RTX_FRAME_RELATED_P (insn) = 1;
3508 /* Return 1 if br.ret can do all the work required to return from a
3512 ia64_direct_return (void)
3514 if (reload_completed && ! frame_pointer_needed)
3516 ia64_compute_frame_size (get_frame_size ());
3518 return (current_frame_info.total_size == 0
3519 && current_frame_info.n_spilled == 0
3520 && current_frame_info.reg_save_b0 == 0
3521 && current_frame_info.reg_save_pr == 0
3522 && current_frame_info.reg_save_ar_pfs == 0
3523 && current_frame_info.reg_save_ar_unat == 0
3524 && current_frame_info.reg_save_ar_lc == 0);
3529 /* Return the magic cookie that we use to hold the return address
3530 during early compilation. */
3533 ia64_return_addr_rtx (HOST_WIDE_INT count, rtx frame ATTRIBUTE_UNUSED)
3537 return gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_RET_ADDR);
3540 /* Split this value after reload, now that we know where the return
3541 address is saved. */
3544 ia64_split_return_addr_rtx (rtx dest)
3548 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3550 if (current_frame_info.reg_save_b0 != 0)
3551 src = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
3557 /* Compute offset from CFA for BR0. */
3558 /* ??? Must be kept in sync with ia64_expand_prologue. */
3559 off = (current_frame_info.spill_cfa_off
3560 + current_frame_info.spill_size);
3561 for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
3562 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3565 /* Convert CFA offset to a register based offset. */
3566 if (frame_pointer_needed)
3567 src = hard_frame_pointer_rtx;
3570 src = stack_pointer_rtx;
3571 off += current_frame_info.total_size;
3574 /* Load address into scratch register. */
3575 if (CONST_OK_FOR_I (off))
3576 emit_insn (gen_adddi3 (dest, src, GEN_INT (off)));
3579 emit_move_insn (dest, GEN_INT (off));
3580 emit_insn (gen_adddi3 (dest, src, dest));
3583 src = gen_rtx_MEM (Pmode, dest);
3587 src = gen_rtx_REG (DImode, BR_REG (0));
3589 emit_move_insn (dest, src);
3593 ia64_hard_regno_rename_ok (int from, int to)
3595 /* Don't clobber any of the registers we reserved for the prologue. */
3596 if (to == current_frame_info.reg_fp
3597 || to == current_frame_info.reg_save_b0
3598 || to == current_frame_info.reg_save_pr
3599 || to == current_frame_info.reg_save_ar_pfs
3600 || to == current_frame_info.reg_save_ar_unat
3601 || to == current_frame_info.reg_save_ar_lc)
3604 if (from == current_frame_info.reg_fp
3605 || from == current_frame_info.reg_save_b0
3606 || from == current_frame_info.reg_save_pr
3607 || from == current_frame_info.reg_save_ar_pfs
3608 || from == current_frame_info.reg_save_ar_unat
3609 || from == current_frame_info.reg_save_ar_lc)
3612 /* Don't use output registers outside the register frame. */
3613 if (OUT_REGNO_P (to) && to >= OUT_REG (current_frame_info.n_output_regs))
3616 /* Retain even/oddness on predicate register pairs. */
3617 if (PR_REGNO_P (from) && PR_REGNO_P (to))
3618 return (from & 1) == (to & 1);
3623 /* Target hook for assembling integer objects. Handle word-sized
3624 aligned objects and detect the cases when @fptr is needed. */
3627 ia64_assemble_integer (rtx x, unsigned int size, int aligned_p)
3629 if (size == POINTER_SIZE / BITS_PER_UNIT
3630 && !(TARGET_NO_PIC || TARGET_AUTO_PIC)
3631 && GET_CODE (x) == SYMBOL_REF
3632 && SYMBOL_REF_FUNCTION_P (x))
3634 static const char * const directive[2][2] = {
3635 /* 64-bit pointer */ /* 32-bit pointer */
3636 { "\tdata8.ua\t@fptr(", "\tdata4.ua\t@fptr("}, /* unaligned */
3637 { "\tdata8\t@fptr(", "\tdata4\t@fptr("} /* aligned */
3639 fputs (directive[(aligned_p != 0)][POINTER_SIZE == 32], asm_out_file);
3640 output_addr_const (asm_out_file, x);
3641 fputs (")\n", asm_out_file);
3644 return default_assemble_integer (x, size, aligned_p);
3647 /* Emit the function prologue. */
3650 ia64_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3652 int mask, grsave, grsave_prev;
3654 if (current_frame_info.need_regstk)
3655 fprintf (file, "\t.regstk %d, %d, %d, %d\n",
3656 current_frame_info.n_input_regs,
3657 current_frame_info.n_local_regs,
3658 current_frame_info.n_output_regs,
3659 current_frame_info.n_rotate_regs);
3661 if (!flag_unwind_tables && (!flag_exceptions || USING_SJLJ_EXCEPTIONS))
3664 /* Emit the .prologue directive. */
3667 grsave = grsave_prev = 0;
3668 if (current_frame_info.reg_save_b0 != 0)
3671 grsave = grsave_prev = current_frame_info.reg_save_b0;
3673 if (current_frame_info.reg_save_ar_pfs != 0
3674 && (grsave_prev == 0
3675 || current_frame_info.reg_save_ar_pfs == grsave_prev + 1))
3678 if (grsave_prev == 0)
3679 grsave = current_frame_info.reg_save_ar_pfs;
3680 grsave_prev = current_frame_info.reg_save_ar_pfs;
3682 if (current_frame_info.reg_fp != 0
3683 && (grsave_prev == 0
3684 || current_frame_info.reg_fp == grsave_prev + 1))
3687 if (grsave_prev == 0)
3688 grsave = HARD_FRAME_POINTER_REGNUM;
3689 grsave_prev = current_frame_info.reg_fp;
3691 if (current_frame_info.reg_save_pr != 0
3692 && (grsave_prev == 0
3693 || current_frame_info.reg_save_pr == grsave_prev + 1))
3696 if (grsave_prev == 0)
3697 grsave = current_frame_info.reg_save_pr;
3700 if (mask && TARGET_GNU_AS)
3701 fprintf (file, "\t.prologue %d, %d\n", mask,
3702 ia64_dbx_register_number (grsave));
3704 fputs ("\t.prologue\n", file);
3706 /* Emit a .spill directive, if necessary, to relocate the base of
3707 the register spill area. */
3708 if (current_frame_info.spill_cfa_off != -16)
3709 fprintf (file, "\t.spill %ld\n",
3710 (long) (current_frame_info.spill_cfa_off
3711 + current_frame_info.spill_size));
3714 /* Emit the .body directive at the scheduled end of the prologue. */
3717 ia64_output_function_end_prologue (FILE *file)
3719 if (!flag_unwind_tables && (!flag_exceptions || USING_SJLJ_EXCEPTIONS))
3722 fputs ("\t.body\n", file);
3725 /* Emit the function epilogue. */
3728 ia64_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
3729 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3733 if (current_frame_info.reg_fp)
3735 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
3736 reg_names[HARD_FRAME_POINTER_REGNUM]
3737 = reg_names[current_frame_info.reg_fp];
3738 reg_names[current_frame_info.reg_fp] = tmp;
3740 if (! TARGET_REG_NAMES)
3742 for (i = 0; i < current_frame_info.n_input_regs; i++)
3743 reg_names[IN_REG (i)] = ia64_input_reg_names[i];
3744 for (i = 0; i < current_frame_info.n_local_regs; i++)
3745 reg_names[LOC_REG (i)] = ia64_local_reg_names[i];
3746 for (i = 0; i < current_frame_info.n_output_regs; i++)
3747 reg_names[OUT_REG (i)] = ia64_output_reg_names[i];
3750 current_frame_info.initialized = 0;
3754 ia64_dbx_register_number (int regno)
3756 /* In ia64_expand_prologue we quite literally renamed the frame pointer
3757 from its home at loc79 to something inside the register frame. We
3758 must perform the same renumbering here for the debug info. */
3759 if (current_frame_info.reg_fp)
3761 if (regno == HARD_FRAME_POINTER_REGNUM)
3762 regno = current_frame_info.reg_fp;
3763 else if (regno == current_frame_info.reg_fp)
3764 regno = HARD_FRAME_POINTER_REGNUM;
3767 if (IN_REGNO_P (regno))
3768 return 32 + regno - IN_REG (0);
3769 else if (LOC_REGNO_P (regno))
3770 return 32 + current_frame_info.n_input_regs + regno - LOC_REG (0);
3771 else if (OUT_REGNO_P (regno))
3772 return (32 + current_frame_info.n_input_regs
3773 + current_frame_info.n_local_regs + regno - OUT_REG (0));
3779 ia64_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
3781 rtx addr_reg, eight = GEN_INT (8);
3783 /* The Intel assembler requires that the global __ia64_trampoline symbol
3784 be declared explicitly */
3787 static bool declared_ia64_trampoline = false;
3789 if (!declared_ia64_trampoline)
3791 declared_ia64_trampoline = true;
3792 (*targetm.asm_out.globalize_label) (asm_out_file,
3793 "__ia64_trampoline");
3797 /* Make sure addresses are Pmode even if we are in ILP32 mode. */
3798 addr = convert_memory_address (Pmode, addr);
3799 fnaddr = convert_memory_address (Pmode, fnaddr);
3800 static_chain = convert_memory_address (Pmode, static_chain);
3802 /* Load up our iterator. */
3803 addr_reg = gen_reg_rtx (Pmode);
3804 emit_move_insn (addr_reg, addr);
3806 /* The first two words are the fake descriptor:
3807 __ia64_trampoline, ADDR+16. */
3808 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg),
3809 gen_rtx_SYMBOL_REF (Pmode, "__ia64_trampoline"));
3810 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
3812 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg),
3813 copy_to_reg (plus_constant (addr, 16)));
3814 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
3816 /* The third word is the target descriptor. */
3817 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg), fnaddr);
3818 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
3820 /* The fourth word is the static chain. */
3821 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg), static_chain);
3824 /* Do any needed setup for a variadic function. CUM has not been updated
3825 for the last named argument which has type TYPE and mode MODE.
3827 We generate the actual spill instructions during prologue generation. */
3830 ia64_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3831 tree type, int * pretend_size,
3832 int second_time ATTRIBUTE_UNUSED)
3834 CUMULATIVE_ARGS next_cum = *cum;
3836 /* Skip the current argument. */
3837 ia64_function_arg_advance (&next_cum, mode, type, 1);
3839 if (next_cum.words < MAX_ARGUMENT_SLOTS)
3841 int n = MAX_ARGUMENT_SLOTS - next_cum.words;
3842 *pretend_size = n * UNITS_PER_WORD;
3843 cfun->machine->n_varargs = n;
3847 /* Check whether TYPE is a homogeneous floating point aggregate. If
3848 it is, return the mode of the floating point type that appears
3849 in all leafs. If it is not, return VOIDmode.
3851 An aggregate is a homogeneous floating point aggregate is if all
3852 fields/elements in it have the same floating point type (e.g,
3853 SFmode). 128-bit quad-precision floats are excluded.
3855 Variable sized aggregates should never arrive here, since we should
3856 have already decided to pass them by reference. Top-level zero-sized
3857 aggregates are excluded because our parallels crash the middle-end. */
3859 static enum machine_mode
3860 hfa_element_mode (tree type, bool nested)
3862 enum machine_mode element_mode = VOIDmode;
3863 enum machine_mode mode;
3864 enum tree_code code = TREE_CODE (type);
3865 int know_element_mode = 0;
3868 if (!nested && (!TYPE_SIZE (type) || integer_zerop (TYPE_SIZE (type))))
3873 case VOID_TYPE: case INTEGER_TYPE: case ENUMERAL_TYPE:
3874 case BOOLEAN_TYPE: case POINTER_TYPE:
3875 case OFFSET_TYPE: case REFERENCE_TYPE: case METHOD_TYPE:
3876 case LANG_TYPE: case FUNCTION_TYPE:
3879 /* Fortran complex types are supposed to be HFAs, so we need to handle
3880 gcc's COMPLEX_TYPEs as HFAs. We need to exclude the integral complex
3883 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_FLOAT
3884 && TYPE_MODE (type) != TCmode)
3885 return GET_MODE_INNER (TYPE_MODE (type));
3890 /* We want to return VOIDmode for raw REAL_TYPEs, but the actual
3891 mode if this is contained within an aggregate. */
3892 if (nested && TYPE_MODE (type) != TFmode)
3893 return TYPE_MODE (type);
3898 return hfa_element_mode (TREE_TYPE (type), 1);
3902 case QUAL_UNION_TYPE:
3903 for (t = TYPE_FIELDS (type); t; t = TREE_CHAIN (t))
3905 if (TREE_CODE (t) != FIELD_DECL)
3908 mode = hfa_element_mode (TREE_TYPE (t), 1);
3909 if (know_element_mode)
3911 if (mode != element_mode)
3914 else if (GET_MODE_CLASS (mode) != MODE_FLOAT)
3918 know_element_mode = 1;
3919 element_mode = mode;
3922 return element_mode;
3925 /* If we reach here, we probably have some front-end specific type
3926 that the backend doesn't know about. This can happen via the
3927 aggregate_value_p call in init_function_start. All we can do is
3928 ignore unknown tree types. */
3935 /* Return the number of words required to hold a quantity of TYPE and MODE
3936 when passed as an argument. */
3938 ia64_function_arg_words (tree type, enum machine_mode mode)
3942 if (mode == BLKmode)
3943 words = int_size_in_bytes (type);
3945 words = GET_MODE_SIZE (mode);
3947 return (words + UNITS_PER_WORD - 1) / UNITS_PER_WORD; /* round up */
3950 /* Return the number of registers that should be skipped so the current
3951 argument (described by TYPE and WORDS) will be properly aligned.
3953 Integer and float arguments larger than 8 bytes start at the next
3954 even boundary. Aggregates larger than 8 bytes start at the next
3955 even boundary if the aggregate has 16 byte alignment. Note that
3956 in the 32-bit ABI, TImode and TFmode have only 8-byte alignment
3957 but are still to be aligned in registers.
3959 ??? The ABI does not specify how to handle aggregates with
3960 alignment from 9 to 15 bytes, or greater than 16. We handle them
3961 all as if they had 16 byte alignment. Such aggregates can occur
3962 only if gcc extensions are used. */
3964 ia64_function_arg_offset (CUMULATIVE_ARGS *cum, tree type, int words)
3966 if ((cum->words & 1) == 0)
3970 && TREE_CODE (type) != INTEGER_TYPE
3971 && TREE_CODE (type) != REAL_TYPE)
3972 return TYPE_ALIGN (type) > 8 * BITS_PER_UNIT;
3977 /* Return rtx for register where argument is passed, or zero if it is passed
3979 /* ??? 128-bit quad-precision floats are always passed in general
3983 ia64_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
3984 int named, int incoming)
3986 int basereg = (incoming ? GR_ARG_FIRST : AR_ARG_FIRST);
3987 int words = ia64_function_arg_words (type, mode);
3988 int offset = ia64_function_arg_offset (cum, type, words);
3989 enum machine_mode hfa_mode = VOIDmode;
3991 /* If all argument slots are used, then it must go on the stack. */
3992 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
3995 /* Check for and handle homogeneous FP aggregates. */
3997 hfa_mode = hfa_element_mode (type, 0);
3999 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
4000 and unprototyped hfas are passed specially. */
4001 if (hfa_mode != VOIDmode && (! cum->prototype || named))
4005 int fp_regs = cum->fp_regs;
4006 int int_regs = cum->words + offset;
4007 int hfa_size = GET_MODE_SIZE (hfa_mode);
4011 /* If prototyped, pass it in FR regs then GR regs.
4012 If not prototyped, pass it in both FR and GR regs.
4014 If this is an SFmode aggregate, then it is possible to run out of
4015 FR regs while GR regs are still left. In that case, we pass the
4016 remaining part in the GR regs. */
4018 /* Fill the FP regs. We do this always. We stop if we reach the end
4019 of the argument, the last FP register, or the last argument slot. */
4021 byte_size = ((mode == BLKmode)
4022 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4023 args_byte_size = int_regs * UNITS_PER_WORD;
4025 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
4026 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD)); i++)
4028 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4029 gen_rtx_REG (hfa_mode, (FR_ARG_FIRST
4033 args_byte_size += hfa_size;
4037 /* If no prototype, then the whole thing must go in GR regs. */
4038 if (! cum->prototype)
4040 /* If this is an SFmode aggregate, then we might have some left over
4041 that needs to go in GR regs. */
4042 else if (byte_size != offset)
4043 int_regs += offset / UNITS_PER_WORD;
4045 /* Fill in the GR regs. We must use DImode here, not the hfa mode. */
4047 for (; offset < byte_size && int_regs < MAX_ARGUMENT_SLOTS; i++)
4049 enum machine_mode gr_mode = DImode;
4050 unsigned int gr_size;
4052 /* If we have an odd 4 byte hunk because we ran out of FR regs,
4053 then this goes in a GR reg left adjusted/little endian, right
4054 adjusted/big endian. */
4055 /* ??? Currently this is handled wrong, because 4-byte hunks are
4056 always right adjusted/little endian. */
4059 /* If we have an even 4 byte hunk because the aggregate is a
4060 multiple of 4 bytes in size, then this goes in a GR reg right
4061 adjusted/little endian. */
4062 else if (byte_size - offset == 4)
4065 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4066 gen_rtx_REG (gr_mode, (basereg
4070 gr_size = GET_MODE_SIZE (gr_mode);
4072 if (gr_size == UNITS_PER_WORD
4073 || (gr_size < UNITS_PER_WORD && offset % UNITS_PER_WORD == 0))
4075 else if (gr_size > UNITS_PER_WORD)
4076 int_regs += gr_size / UNITS_PER_WORD;
4078 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4081 /* Integral and aggregates go in general registers. If we have run out of
4082 FR registers, then FP values must also go in general registers. This can
4083 happen when we have a SFmode HFA. */
4084 else if (mode == TFmode || mode == TCmode
4085 || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
4087 int byte_size = ((mode == BLKmode)
4088 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4089 if (BYTES_BIG_ENDIAN
4090 && (mode == BLKmode || (type && AGGREGATE_TYPE_P (type)))
4091 && byte_size < UNITS_PER_WORD
4094 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
4095 gen_rtx_REG (DImode,
4096 (basereg + cum->words
4099 return gen_rtx_PARALLEL (mode, gen_rtvec (1, gr_reg));
4102 return gen_rtx_REG (mode, basereg + cum->words + offset);
4106 /* If there is a prototype, then FP values go in a FR register when
4107 named, and in a GR register when unnamed. */
4108 else if (cum->prototype)
4111 return gen_rtx_REG (mode, FR_ARG_FIRST + cum->fp_regs);
4112 /* In big-endian mode, an anonymous SFmode value must be represented
4113 as (parallel:SF [(expr_list (reg:DI n) (const_int 0))]) to force
4114 the value into the high half of the general register. */
4115 else if (BYTES_BIG_ENDIAN && mode == SFmode)
4116 return gen_rtx_PARALLEL (mode,
4118 gen_rtx_EXPR_LIST (VOIDmode,
4119 gen_rtx_REG (DImode, basereg + cum->words + offset),
4122 return gen_rtx_REG (mode, basereg + cum->words + offset);
4124 /* If there is no prototype, then FP values go in both FR and GR
4128 /* See comment above. */
4129 enum machine_mode inner_mode =
4130 (BYTES_BIG_ENDIAN && mode == SFmode) ? DImode : mode;
4132 rtx fp_reg = gen_rtx_EXPR_LIST (VOIDmode,
4133 gen_rtx_REG (mode, (FR_ARG_FIRST
4136 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
4137 gen_rtx_REG (inner_mode,
4138 (basereg + cum->words
4142 return gen_rtx_PARALLEL (mode, gen_rtvec (2, fp_reg, gr_reg));
4146 /* Return number of bytes, at the beginning of the argument, that must be
4147 put in registers. 0 is the argument is entirely in registers or entirely
4151 ia64_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4152 tree type, bool named ATTRIBUTE_UNUSED)
4154 int words = ia64_function_arg_words (type, mode);
4155 int offset = ia64_function_arg_offset (cum, type, words);
4157 /* If all argument slots are used, then it must go on the stack. */
4158 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
4161 /* It doesn't matter whether the argument goes in FR or GR regs. If
4162 it fits within the 8 argument slots, then it goes entirely in
4163 registers. If it extends past the last argument slot, then the rest
4164 goes on the stack. */
4166 if (words + cum->words + offset <= MAX_ARGUMENT_SLOTS)
4169 return (MAX_ARGUMENT_SLOTS - cum->words - offset) * UNITS_PER_WORD;
4172 /* Update CUM to point after this argument. This is patterned after
4173 ia64_function_arg. */
4176 ia64_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4177 tree type, int named)
4179 int words = ia64_function_arg_words (type, mode);
4180 int offset = ia64_function_arg_offset (cum, type, words);
4181 enum machine_mode hfa_mode = VOIDmode;
4183 /* If all arg slots are already full, then there is nothing to do. */
4184 if (cum->words >= MAX_ARGUMENT_SLOTS)
4187 cum->words += words + offset;
4189 /* Check for and handle homogeneous FP aggregates. */
4191 hfa_mode = hfa_element_mode (type, 0);
4193 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
4194 and unprototyped hfas are passed specially. */
4195 if (hfa_mode != VOIDmode && (! cum->prototype || named))
4197 int fp_regs = cum->fp_regs;
4198 /* This is the original value of cum->words + offset. */
4199 int int_regs = cum->words - words;
4200 int hfa_size = GET_MODE_SIZE (hfa_mode);
4204 /* If prototyped, pass it in FR regs then GR regs.
4205 If not prototyped, pass it in both FR and GR regs.
4207 If this is an SFmode aggregate, then it is possible to run out of
4208 FR regs while GR regs are still left. In that case, we pass the
4209 remaining part in the GR regs. */
4211 /* Fill the FP regs. We do this always. We stop if we reach the end
4212 of the argument, the last FP register, or the last argument slot. */
4214 byte_size = ((mode == BLKmode)
4215 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4216 args_byte_size = int_regs * UNITS_PER_WORD;
4218 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
4219 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD));)
4222 args_byte_size += hfa_size;
4226 cum->fp_regs = fp_regs;
4229 /* Integral and aggregates go in general registers. So do TFmode FP values.
4230 If we have run out of FR registers, then other FP values must also go in
4231 general registers. This can happen when we have a SFmode HFA. */
4232 else if (mode == TFmode || mode == TCmode
4233 || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
4234 cum->int_regs = cum->words;
4236 /* If there is a prototype, then FP values go in a FR register when
4237 named, and in a GR register when unnamed. */
4238 else if (cum->prototype)
4241 cum->int_regs = cum->words;
4243 /* ??? Complex types should not reach here. */
4244 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
4246 /* If there is no prototype, then FP values go in both FR and GR
4250 /* ??? Complex types should not reach here. */
4251 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
4252 cum->int_regs = cum->words;
4256 /* Arguments with alignment larger than 8 bytes start at the next even
4257 boundary. On ILP32 HPUX, TFmode arguments start on next even boundary
4258 even though their normal alignment is 8 bytes. See ia64_function_arg. */
4261 ia64_function_arg_boundary (enum machine_mode mode, tree type)
4264 if (mode == TFmode && TARGET_HPUX && TARGET_ILP32)
4265 return PARM_BOUNDARY * 2;
4269 if (TYPE_ALIGN (type) > PARM_BOUNDARY)
4270 return PARM_BOUNDARY * 2;
4272 return PARM_BOUNDARY;
4275 if (GET_MODE_BITSIZE (mode) > PARM_BOUNDARY)
4276 return PARM_BOUNDARY * 2;
4278 return PARM_BOUNDARY;
4281 /* True if it is OK to do sibling call optimization for the specified
4282 call expression EXP. DECL will be the called function, or NULL if
4283 this is an indirect call. */
4285 ia64_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
4287 /* We can't perform a sibcall if the current function has the syscall_linkage
4289 if (lookup_attribute ("syscall_linkage",
4290 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
4293 /* We must always return with our current GP. This means we can
4294 only sibcall to functions defined in the current module. */
4295 return decl && (*targetm.binds_local_p) (decl);
4299 /* Implement va_arg. */
4302 ia64_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
4304 /* Variable sized types are passed by reference. */
4305 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
4307 tree ptrtype = build_pointer_type (type);
4308 tree addr = std_gimplify_va_arg_expr (valist, ptrtype, pre_p, post_p);
4309 return build_va_arg_indirect_ref (addr);
4312 /* Aggregate arguments with alignment larger than 8 bytes start at
4313 the next even boundary. Integer and floating point arguments
4314 do so if they are larger than 8 bytes, whether or not they are
4315 also aligned larger than 8 bytes. */
4316 if ((TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == INTEGER_TYPE)
4317 ? int_size_in_bytes (type) > 8 : TYPE_ALIGN (type) > 8 * BITS_PER_UNIT)
4319 tree t = build2 (PLUS_EXPR, TREE_TYPE (valist), valist,
4320 build_int_cst (NULL_TREE, 2 * UNITS_PER_WORD - 1));
4321 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
4322 build_int_cst (NULL_TREE, -2 * UNITS_PER_WORD));
4323 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (valist), valist, t);
4324 gimplify_and_add (t, pre_p);
4327 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4330 /* Return 1 if function return value returned in memory. Return 0 if it is
4334 ia64_return_in_memory (tree valtype, tree fntype ATTRIBUTE_UNUSED)
4336 enum machine_mode mode;
4337 enum machine_mode hfa_mode;
4338 HOST_WIDE_INT byte_size;
4340 mode = TYPE_MODE (valtype);
4341 byte_size = GET_MODE_SIZE (mode);
4342 if (mode == BLKmode)
4344 byte_size = int_size_in_bytes (valtype);
4349 /* Hfa's with up to 8 elements are returned in the FP argument registers. */
4351 hfa_mode = hfa_element_mode (valtype, 0);
4352 if (hfa_mode != VOIDmode)
4354 int hfa_size = GET_MODE_SIZE (hfa_mode);
4356 if (byte_size / hfa_size > MAX_ARGUMENT_SLOTS)
4361 else if (byte_size > UNITS_PER_WORD * MAX_INT_RETURN_SLOTS)
4367 /* Return rtx for register that holds the function return value. */
4370 ia64_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
4372 enum machine_mode mode;
4373 enum machine_mode hfa_mode;
4375 mode = TYPE_MODE (valtype);
4376 hfa_mode = hfa_element_mode (valtype, 0);
4378 if (hfa_mode != VOIDmode)
4386 hfa_size = GET_MODE_SIZE (hfa_mode);
4387 byte_size = ((mode == BLKmode)
4388 ? int_size_in_bytes (valtype) : GET_MODE_SIZE (mode));
4390 for (i = 0; offset < byte_size; i++)
4392 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4393 gen_rtx_REG (hfa_mode, FR_ARG_FIRST + i),
4397 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4399 else if (FLOAT_TYPE_P (valtype) && mode != TFmode && mode != TCmode)
4400 return gen_rtx_REG (mode, FR_ARG_FIRST);
4403 bool need_parallel = false;
4405 /* In big-endian mode, we need to manage the layout of aggregates
4406 in the registers so that we get the bits properly aligned in
4407 the highpart of the registers. */
4408 if (BYTES_BIG_ENDIAN
4409 && (mode == BLKmode || (valtype && AGGREGATE_TYPE_P (valtype))))
4410 need_parallel = true;
4412 /* Something like struct S { long double x; char a[0] } is not an
4413 HFA structure, and therefore doesn't go in fp registers. But
4414 the middle-end will give it XFmode anyway, and XFmode values
4415 don't normally fit in integer registers. So we need to smuggle
4416 the value inside a parallel. */
4417 else if (mode == XFmode || mode == XCmode || mode == RFmode)
4418 need_parallel = true;
4428 bytesize = int_size_in_bytes (valtype);
4429 /* An empty PARALLEL is invalid here, but the return value
4430 doesn't matter for empty structs. */
4432 return gen_rtx_REG (mode, GR_RET_FIRST);
4433 for (i = 0; offset < bytesize; i++)
4435 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4436 gen_rtx_REG (DImode,
4439 offset += UNITS_PER_WORD;
4441 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4444 return gen_rtx_REG (mode, GR_RET_FIRST);
4448 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4449 We need to emit DTP-relative relocations. */
4452 ia64_output_dwarf_dtprel (FILE *file, int size, rtx x)
4454 gcc_assert (size == 4 || size == 8);
4456 fputs ("\tdata4.ua\t@dtprel(", file);
4458 fputs ("\tdata8.ua\t@dtprel(", file);
4459 output_addr_const (file, x);
4463 /* Print a memory address as an operand to reference that memory location. */
4465 /* ??? Do we need this? It gets used only for 'a' operands. We could perhaps
4466 also call this from ia64_print_operand for memory addresses. */
4469 ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED,
4470 rtx address ATTRIBUTE_UNUSED)
4474 /* Print an operand to an assembler instruction.
4475 C Swap and print a comparison operator.
4476 D Print an FP comparison operator.
4477 E Print 32 - constant, for SImode shifts as extract.
4478 e Print 64 - constant, for DImode rotates.
4479 F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
4480 a floating point register emitted normally.
4481 I Invert a predicate register by adding 1.
4482 J Select the proper predicate register for a condition.
4483 j Select the inverse predicate register for a condition.
4484 O Append .acq for volatile load.
4485 P Postincrement of a MEM.
4486 Q Append .rel for volatile store.
4487 S Shift amount for shladd instruction.
4488 T Print an 8-bit sign extended number (K) as a 32-bit unsigned number
4489 for Intel assembler.
4490 U Print an 8-bit sign extended number (K) as a 64-bit unsigned number
4491 for Intel assembler.
4492 X A pair of floating point registers.
4493 r Print register name, or constant 0 as r0. HP compatibility for
4495 v Print vector constant value as an 8-byte integer value. */
4498 ia64_print_operand (FILE * file, rtx x, int code)
4505 /* Handled below. */
4510 enum rtx_code c = swap_condition (GET_CODE (x));
4511 fputs (GET_RTX_NAME (c), file);
4516 switch (GET_CODE (x))
4528 str = GET_RTX_NAME (GET_CODE (x));
4535 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - INTVAL (x));
4539 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - INTVAL (x));
4543 if (x == CONST0_RTX (GET_MODE (x)))
4544 str = reg_names [FR_REG (0)];
4545 else if (x == CONST1_RTX (GET_MODE (x)))
4546 str = reg_names [FR_REG (1)];
4549 gcc_assert (GET_CODE (x) == REG);
4550 str = reg_names [REGNO (x)];
4556 fputs (reg_names [REGNO (x) + 1], file);
4562 unsigned int regno = REGNO (XEXP (x, 0));
4563 if (GET_CODE (x) == EQ)
4567 fputs (reg_names [regno], file);
4572 if (MEM_VOLATILE_P (x))
4573 fputs(".acq", file);
4578 HOST_WIDE_INT value;
4580 switch (GET_CODE (XEXP (x, 0)))
4586 x = XEXP (XEXP (XEXP (x, 0), 1), 1);
4587 if (GET_CODE (x) == CONST_INT)
4591 gcc_assert (GET_CODE (x) == REG);
4592 fprintf (file, ", %s", reg_names[REGNO (x)]);
4598 value = GET_MODE_SIZE (GET_MODE (x));
4602 value = - (HOST_WIDE_INT) GET_MODE_SIZE (GET_MODE (x));
4606 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC, value);
4611 if (MEM_VOLATILE_P (x))
4612 fputs(".rel", file);
4616 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4620 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
4622 fprintf (file, "0x%x", (int) INTVAL (x) & 0xffffffff);
4628 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
4630 const char *prefix = "0x";
4631 if (INTVAL (x) & 0x80000000)
4633 fprintf (file, "0xffffffff");
4636 fprintf (file, "%s%x", prefix, (int) INTVAL (x) & 0xffffffff);
4643 unsigned int regno = REGNO (x);
4644 fprintf (file, "%s, %s", reg_names [regno], reg_names [regno + 1]);
4649 /* If this operand is the constant zero, write it as register zero.
4650 Any register, zero, or CONST_INT value is OK here. */
4651 if (GET_CODE (x) == REG)
4652 fputs (reg_names[REGNO (x)], file);
4653 else if (x == CONST0_RTX (GET_MODE (x)))
4655 else if (GET_CODE (x) == CONST_INT)
4656 output_addr_const (file, x);
4658 output_operand_lossage ("invalid %%r value");
4662 gcc_assert (GET_CODE (x) == CONST_VECTOR);
4663 x = simplify_subreg (DImode, x, GET_MODE (x), 0);
4670 /* For conditional branches, returns or calls, substitute
4671 sptk, dptk, dpnt, or spnt for %s. */
4672 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
4675 int pred_val = INTVAL (XEXP (x, 0));
4677 /* Guess top and bottom 10% statically predicted. */
4678 if (pred_val < REG_BR_PROB_BASE / 50
4679 && br_prob_note_reliable_p (x))
4681 else if (pred_val < REG_BR_PROB_BASE / 2)
4683 else if (pred_val < REG_BR_PROB_BASE / 100 * 98
4684 || !br_prob_note_reliable_p (x))
4689 else if (GET_CODE (current_output_insn) == CALL_INSN)
4694 fputs (which, file);
4699 x = current_insn_predicate;
4702 unsigned int regno = REGNO (XEXP (x, 0));
4703 if (GET_CODE (x) == EQ)
4705 fprintf (file, "(%s) ", reg_names [regno]);
4710 output_operand_lossage ("ia64_print_operand: unknown code");
4714 switch (GET_CODE (x))
4716 /* This happens for the spill/restore instructions. */
4721 /* ... fall through ... */
4724 fputs (reg_names [REGNO (x)], file);
4729 rtx addr = XEXP (x, 0);
4730 if (GET_RTX_CLASS (GET_CODE (addr)) == RTX_AUTOINC)
4731 addr = XEXP (addr, 0);
4732 fprintf (file, "[%s]", reg_names [REGNO (addr)]);
4737 output_addr_const (file, x);
4744 /* Compute a (partial) cost for rtx X. Return true if the complete
4745 cost has been computed, and false if subexpressions should be
4746 scanned. In either case, *TOTAL contains the cost result. */
4747 /* ??? This is incomplete. */
4750 ia64_rtx_costs (rtx x, int code, int outer_code, int *total)
4758 *total = CONST_OK_FOR_J (INTVAL (x)) ? 0 : COSTS_N_INSNS (1);
4761 if (CONST_OK_FOR_I (INTVAL (x)))
4763 else if (CONST_OK_FOR_J (INTVAL (x)))
4766 *total = COSTS_N_INSNS (1);
4769 if (CONST_OK_FOR_K (INTVAL (x)) || CONST_OK_FOR_L (INTVAL (x)))
4772 *total = COSTS_N_INSNS (1);
4777 *total = COSTS_N_INSNS (1);
4783 *total = COSTS_N_INSNS (3);
4787 /* For multiplies wider than HImode, we have to go to the FPU,
4788 which normally involves copies. Plus there's the latency
4789 of the multiply itself, and the latency of the instructions to
4790 transfer integer regs to FP regs. */
4791 /* ??? Check for FP mode. */
4792 if (GET_MODE_SIZE (GET_MODE (x)) > 2)
4793 *total = COSTS_N_INSNS (10);
4795 *total = COSTS_N_INSNS (2);
4803 *total = COSTS_N_INSNS (1);
4810 /* We make divide expensive, so that divide-by-constant will be
4811 optimized to a multiply. */
4812 *total = COSTS_N_INSNS (60);
4820 /* Calculate the cost of moving data from a register in class FROM to
4821 one in class TO, using MODE. */
4824 ia64_register_move_cost (enum machine_mode mode, enum reg_class from,
4827 /* ADDL_REGS is the same as GR_REGS for movement purposes. */
4828 if (to == ADDL_REGS)
4830 if (from == ADDL_REGS)
4833 /* All costs are symmetric, so reduce cases by putting the
4834 lower number class as the destination. */
4837 enum reg_class tmp = to;
4838 to = from, from = tmp;
4841 /* Moving from FR<->GR in XFmode must be more expensive than 2,
4842 so that we get secondary memory reloads. Between FR_REGS,
4843 we have to make this at least as expensive as MEMORY_MOVE_COST
4844 to avoid spectacularly poor register class preferencing. */
4845 if (mode == XFmode || mode == RFmode)
4847 if (to != GR_REGS || from != GR_REGS)
4848 return MEMORY_MOVE_COST (mode, to, 0);
4856 /* Moving between PR registers takes two insns. */
4857 if (from == PR_REGS)
4859 /* Moving between PR and anything but GR is impossible. */
4860 if (from != GR_REGS)
4861 return MEMORY_MOVE_COST (mode, to, 0);
4865 /* Moving between BR and anything but GR is impossible. */
4866 if (from != GR_REGS && from != GR_AND_BR_REGS)
4867 return MEMORY_MOVE_COST (mode, to, 0);
4872 /* Moving between AR and anything but GR is impossible. */
4873 if (from != GR_REGS)
4874 return MEMORY_MOVE_COST (mode, to, 0);
4880 case GR_AND_FR_REGS:
4881 case GR_AND_BR_REGS:
4892 /* Implement PREFERRED_RELOAD_CLASS. Place additional restrictions on CLASS
4893 to use when copying X into that class. */
4896 ia64_preferred_reload_class (rtx x, enum reg_class class)
4902 /* Don't allow volatile mem reloads into floating point registers.
4903 This is defined to force reload to choose the r/m case instead
4904 of the f/f case when reloading (set (reg fX) (mem/v)). */
4905 if (MEM_P (x) && MEM_VOLATILE_P (x))
4908 /* Force all unrecognized constants into the constant pool. */
4926 /* This function returns the register class required for a secondary
4927 register when copying between one of the registers in CLASS, and X,
4928 using MODE. A return value of NO_REGS means that no secondary register
4932 ia64_secondary_reload_class (enum reg_class class,
4933 enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
4937 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
4938 regno = true_regnum (x);
4945 /* ??? BR<->BR register copies can happen due to a bad gcse/cse/global
4946 interaction. We end up with two pseudos with overlapping lifetimes
4947 both of which are equiv to the same constant, and both which need
4948 to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end
4949 changes depending on the path length, which means the qty_first_reg
4950 check in make_regs_eqv can give different answers at different times.
4951 At some point I'll probably need a reload_indi pattern to handle
4954 We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we
4955 wound up with a FP register from GR_AND_FR_REGS. Extend that to all
4956 non-general registers for good measure. */
4957 if (regno >= 0 && ! GENERAL_REGNO_P (regno))
4960 /* This is needed if a pseudo used as a call_operand gets spilled to a
4962 if (GET_CODE (x) == MEM)
4968 /* Need to go through general registers to get to other class regs. */
4969 if (regno >= 0 && ! (FR_REGNO_P (regno) || GENERAL_REGNO_P (regno)))
4972 /* This can happen when a paradoxical subreg is an operand to the
4974 /* ??? This shouldn't be necessary after instruction scheduling is
4975 enabled, because paradoxical subregs are not accepted by
4976 register_operand when INSN_SCHEDULING is defined. Or alternatively,
4977 stop the paradoxical subreg stupidity in the *_operand functions
4979 if (GET_CODE (x) == MEM
4980 && (GET_MODE (x) == SImode || GET_MODE (x) == HImode
4981 || GET_MODE (x) == QImode))
4984 /* This can happen because of the ior/and/etc patterns that accept FP
4985 registers as operands. If the third operand is a constant, then it
4986 needs to be reloaded into a FP register. */
4987 if (GET_CODE (x) == CONST_INT)
4990 /* This can happen because of register elimination in a muldi3 insn.
4991 E.g. `26107 * (unsigned long)&u'. */
4992 if (GET_CODE (x) == PLUS)
4997 /* ??? This happens if we cse/gcse a BImode value across a call,
4998 and the function has a nonlocal goto. This is because global
4999 does not allocate call crossing pseudos to hard registers when
5000 current_function_has_nonlocal_goto is true. This is relatively
5001 common for C++ programs that use exceptions. To reproduce,
5002 return NO_REGS and compile libstdc++. */
5003 if (GET_CODE (x) == MEM)
5006 /* This can happen when we take a BImode subreg of a DImode value,
5007 and that DImode value winds up in some non-GR register. */
5008 if (regno >= 0 && ! GENERAL_REGNO_P (regno) && ! PR_REGNO_P (regno))
5020 /* Parse the -mfixed-range= option string. */
5023 fix_range (const char *const_str)
5026 char *str, *dash, *comma;
5028 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
5029 REG2 are either register names or register numbers. The effect
5030 of this option is to mark the registers in the range from REG1 to
5031 REG2 as ``fixed'' so they won't be used by the compiler. This is
5032 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
5034 i = strlen (const_str);
5035 str = (char *) alloca (i + 1);
5036 memcpy (str, const_str, i + 1);
5040 dash = strchr (str, '-');
5043 warning (0, "value of -mfixed-range must have form REG1-REG2");
5048 comma = strchr (dash + 1, ',');
5052 first = decode_reg_name (str);
5055 warning (0, "unknown register name: %s", str);
5059 last = decode_reg_name (dash + 1);
5062 warning (0, "unknown register name: %s", dash + 1);
5070 warning (0, "%s-%s is an empty range", str, dash + 1);
5074 for (i = first; i <= last; ++i)
5075 fixed_regs[i] = call_used_regs[i] = 1;
5085 /* Implement TARGET_HANDLE_OPTION. */
5088 ia64_handle_option (size_t code, const char *arg, int value)
5092 case OPT_mfixed_range_:
5096 case OPT_mtls_size_:
5097 if (value != 14 && value != 22 && value != 64)
5098 error ("bad value %<%s%> for -mtls-size= switch", arg);
5105 const char *name; /* processor name or nickname. */
5106 enum processor_type processor;
5108 const processor_alias_table[] =
5110 {"itanium", PROCESSOR_ITANIUM},
5111 {"itanium1", PROCESSOR_ITANIUM},
5112 {"merced", PROCESSOR_ITANIUM},
5113 {"itanium2", PROCESSOR_ITANIUM2},
5114 {"mckinley", PROCESSOR_ITANIUM2},
5116 int const pta_size = ARRAY_SIZE (processor_alias_table);
5119 for (i = 0; i < pta_size; i++)
5120 if (!strcmp (arg, processor_alias_table[i].name))
5122 ia64_tune = processor_alias_table[i].processor;
5126 error ("bad value %<%s%> for -mtune= switch", arg);
5135 /* Implement OVERRIDE_OPTIONS. */
5138 ia64_override_options (void)
5140 if (TARGET_AUTO_PIC)
5141 target_flags |= MASK_CONST_GP;
5143 if (TARGET_INLINE_SQRT == INL_MIN_LAT)
5145 warning (0, "not yet implemented: latency-optimized inline square root");
5146 TARGET_INLINE_SQRT = INL_MAX_THR;
5149 ia64_flag_schedule_insns2 = flag_schedule_insns_after_reload;
5150 flag_schedule_insns_after_reload = 0;
5152 ia64_section_threshold = g_switch_set ? g_switch_value : IA64_DEFAULT_GVALUE;
5154 init_machine_status = ia64_init_machine_status;
5157 static struct machine_function *
5158 ia64_init_machine_status (void)
5160 return ggc_alloc_cleared (sizeof (struct machine_function));
5163 static enum attr_itanium_class ia64_safe_itanium_class (rtx);
5164 static enum attr_type ia64_safe_type (rtx);
5166 static enum attr_itanium_class
5167 ia64_safe_itanium_class (rtx insn)
5169 if (recog_memoized (insn) >= 0)
5170 return get_attr_itanium_class (insn);
5172 return ITANIUM_CLASS_UNKNOWN;
5175 static enum attr_type
5176 ia64_safe_type (rtx insn)
5178 if (recog_memoized (insn) >= 0)
5179 return get_attr_type (insn);
5181 return TYPE_UNKNOWN;
5184 /* The following collection of routines emit instruction group stop bits as
5185 necessary to avoid dependencies. */
5187 /* Need to track some additional registers as far as serialization is
5188 concerned so we can properly handle br.call and br.ret. We could
5189 make these registers visible to gcc, but since these registers are
5190 never explicitly used in gcc generated code, it seems wasteful to
5191 do so (plus it would make the call and return patterns needlessly
5193 #define REG_RP (BR_REG (0))
5194 #define REG_AR_CFM (FIRST_PSEUDO_REGISTER + 1)
5195 /* This is used for volatile asms which may require a stop bit immediately
5196 before and after them. */
5197 #define REG_VOLATILE (FIRST_PSEUDO_REGISTER + 2)
5198 #define AR_UNAT_BIT_0 (FIRST_PSEUDO_REGISTER + 3)
5199 #define NUM_REGS (AR_UNAT_BIT_0 + 64)
5201 /* For each register, we keep track of how it has been written in the
5202 current instruction group.
5204 If a register is written unconditionally (no qualifying predicate),
5205 WRITE_COUNT is set to 2 and FIRST_PRED is ignored.
5207 If a register is written if its qualifying predicate P is true, we
5208 set WRITE_COUNT to 1 and FIRST_PRED to P. Later on, the same register
5209 may be written again by the complement of P (P^1) and when this happens,
5210 WRITE_COUNT gets set to 2.
5212 The result of this is that whenever an insn attempts to write a register
5213 whose WRITE_COUNT is two, we need to issue an insn group barrier first.
5215 If a predicate register is written by a floating-point insn, we set
5216 WRITTEN_BY_FP to true.
5218 If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND
5219 to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true. */
5221 struct reg_write_state
5223 unsigned int write_count : 2;
5224 unsigned int first_pred : 16;
5225 unsigned int written_by_fp : 1;
5226 unsigned int written_by_and : 1;
5227 unsigned int written_by_or : 1;
5230 /* Cumulative info for the current instruction group. */
5231 struct reg_write_state rws_sum[NUM_REGS];
5232 /* Info for the current instruction. This gets copied to rws_sum after a
5233 stop bit is emitted. */
5234 struct reg_write_state rws_insn[NUM_REGS];
5236 /* Indicates whether this is the first instruction after a stop bit,
5237 in which case we don't need another stop bit. Without this,
5238 ia64_variable_issue will die when scheduling an alloc. */
5239 static int first_instruction;
5241 /* Misc flags needed to compute RAW/WAW dependencies while we are traversing
5242 RTL for one instruction. */
5245 unsigned int is_write : 1; /* Is register being written? */
5246 unsigned int is_fp : 1; /* Is register used as part of an fp op? */
5247 unsigned int is_branch : 1; /* Is register used as part of a branch? */
5248 unsigned int is_and : 1; /* Is register used as part of and.orcm? */
5249 unsigned int is_or : 1; /* Is register used as part of or.andcm? */
5250 unsigned int is_sibcall : 1; /* Is this a sibling or normal call? */
5253 static void rws_update (struct reg_write_state *, int, struct reg_flags, int);
5254 static int rws_access_regno (int, struct reg_flags, int);
5255 static int rws_access_reg (rtx, struct reg_flags, int);
5256 static void update_set_flags (rtx, struct reg_flags *);
5257 static int set_src_needs_barrier (rtx, struct reg_flags, int);
5258 static int rtx_needs_barrier (rtx, struct reg_flags, int);
5259 static void init_insn_group_barriers (void);
5260 static int group_barrier_needed (rtx);
5261 static int safe_group_barrier_needed (rtx);
5263 /* Update *RWS for REGNO, which is being written by the current instruction,
5264 with predicate PRED, and associated register flags in FLAGS. */
5267 rws_update (struct reg_write_state *rws, int regno, struct reg_flags flags, int pred)
5270 rws[regno].write_count++;
5272 rws[regno].write_count = 2;
5273 rws[regno].written_by_fp |= flags.is_fp;
5274 /* ??? Not tracking and/or across differing predicates. */
5275 rws[regno].written_by_and = flags.is_and;
5276 rws[regno].written_by_or = flags.is_or;
5277 rws[regno].first_pred = pred;
5280 /* Handle an access to register REGNO of type FLAGS using predicate register
5281 PRED. Update rws_insn and rws_sum arrays. Return 1 if this access creates
5282 a dependency with an earlier instruction in the same group. */
5285 rws_access_regno (int regno, struct reg_flags flags, int pred)
5287 int need_barrier = 0;
5289 gcc_assert (regno < NUM_REGS);
5291 if (! PR_REGNO_P (regno))
5292 flags.is_and = flags.is_or = 0;
5298 /* One insn writes same reg multiple times? */
5299 gcc_assert (!rws_insn[regno].write_count);
5301 /* Update info for current instruction. */
5302 rws_update (rws_insn, regno, flags, pred);
5303 write_count = rws_sum[regno].write_count;
5305 switch (write_count)
5308 /* The register has not been written yet. */
5309 rws_update (rws_sum, regno, flags, pred);
5313 /* The register has been written via a predicate. If this is
5314 not a complementary predicate, then we need a barrier. */
5315 /* ??? This assumes that P and P+1 are always complementary
5316 predicates for P even. */
5317 if (flags.is_and && rws_sum[regno].written_by_and)
5319 else if (flags.is_or && rws_sum[regno].written_by_or)
5321 else if ((rws_sum[regno].first_pred ^ 1) != pred)
5323 rws_update (rws_sum, regno, flags, pred);
5327 /* The register has been unconditionally written already. We
5329 if (flags.is_and && rws_sum[regno].written_by_and)
5331 else if (flags.is_or && rws_sum[regno].written_by_or)
5335 rws_sum[regno].written_by_and = flags.is_and;
5336 rws_sum[regno].written_by_or = flags.is_or;
5345 if (flags.is_branch)
5347 /* Branches have several RAW exceptions that allow to avoid
5350 if (REGNO_REG_CLASS (regno) == BR_REGS || regno == AR_PFS_REGNUM)
5351 /* RAW dependencies on branch regs are permissible as long
5352 as the writer is a non-branch instruction. Since we
5353 never generate code that uses a branch register written
5354 by a branch instruction, handling this case is
5358 if (REGNO_REG_CLASS (regno) == PR_REGS
5359 && ! rws_sum[regno].written_by_fp)
5360 /* The predicates of a branch are available within the
5361 same insn group as long as the predicate was written by
5362 something other than a floating-point instruction. */
5366 if (flags.is_and && rws_sum[regno].written_by_and)
5368 if (flags.is_or && rws_sum[regno].written_by_or)
5371 switch (rws_sum[regno].write_count)
5374 /* The register has not been written yet. */
5378 /* The register has been written via a predicate. If this is
5379 not a complementary predicate, then we need a barrier. */
5380 /* ??? This assumes that P and P+1 are always complementary
5381 predicates for P even. */
5382 if ((rws_sum[regno].first_pred ^ 1) != pred)
5387 /* The register has been unconditionally written already. We
5397 return need_barrier;
5401 rws_access_reg (rtx reg, struct reg_flags flags, int pred)
5403 int regno = REGNO (reg);
5404 int n = HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg));
5407 return rws_access_regno (regno, flags, pred);
5410 int need_barrier = 0;
5412 need_barrier |= rws_access_regno (regno + n, flags, pred);
5413 return need_barrier;
5417 /* Examine X, which is a SET rtx, and update the flags, the predicate, and
5418 the condition, stored in *PFLAGS, *PPRED and *PCOND. */
5421 update_set_flags (rtx x, struct reg_flags *pflags)
5423 rtx src = SET_SRC (x);
5425 switch (GET_CODE (src))
5431 /* There are four cases here:
5432 (1) The destination is (pc), in which case this is a branch,
5433 nothing here applies.
5434 (2) The destination is ar.lc, in which case this is a
5435 doloop_end_internal,
5436 (3) The destination is an fp register, in which case this is
5437 an fselect instruction.
5438 (4) The condition has (unspec [(reg)] UNSPEC_LDC), in which case
5439 this is a check load.
5440 In all cases, nothing we do in this function applies. */
5444 if (COMPARISON_P (src)
5445 && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (src, 0))))
5446 /* Set pflags->is_fp to 1 so that we know we're dealing
5447 with a floating point comparison when processing the
5448 destination of the SET. */
5451 /* Discover if this is a parallel comparison. We only handle
5452 and.orcm and or.andcm at present, since we must retain a
5453 strict inverse on the predicate pair. */
5454 else if (GET_CODE (src) == AND)
5456 else if (GET_CODE (src) == IOR)
5463 /* Subroutine of rtx_needs_barrier; this function determines whether the
5464 source of a given SET rtx found in X needs a barrier. FLAGS and PRED
5465 are as in rtx_needs_barrier. COND is an rtx that holds the condition
5469 set_src_needs_barrier (rtx x, struct reg_flags flags, int pred)
5471 int need_barrier = 0;
5473 rtx src = SET_SRC (x);
5475 if (GET_CODE (src) == CALL)
5476 /* We don't need to worry about the result registers that
5477 get written by subroutine call. */
5478 return rtx_needs_barrier (src, flags, pred);
5479 else if (SET_DEST (x) == pc_rtx)
5481 /* X is a conditional branch. */
5482 /* ??? This seems redundant, as the caller sets this bit for
5484 if (!ia64_spec_check_src_p (src))
5485 flags.is_branch = 1;
5486 return rtx_needs_barrier (src, flags, pred);
5489 if (ia64_spec_check_src_p (src))
5490 /* Avoid checking one register twice (in condition
5491 and in 'then' section) for ldc pattern. */
5493 gcc_assert (REG_P (XEXP (src, 2)));
5494 need_barrier = rtx_needs_barrier (XEXP (src, 2), flags, pred);
5496 /* We process MEM below. */
5497 src = XEXP (src, 1);
5500 need_barrier |= rtx_needs_barrier (src, flags, pred);
5503 if (GET_CODE (dst) == ZERO_EXTRACT)
5505 need_barrier |= rtx_needs_barrier (XEXP (dst, 1), flags, pred);
5506 need_barrier |= rtx_needs_barrier (XEXP (dst, 2), flags, pred);
5508 return need_barrier;
5511 /* Handle an access to rtx X of type FLAGS using predicate register
5512 PRED. Return 1 if this access creates a dependency with an earlier
5513 instruction in the same group. */
5516 rtx_needs_barrier (rtx x, struct reg_flags flags, int pred)
5519 int is_complemented = 0;
5520 int need_barrier = 0;
5521 const char *format_ptr;
5522 struct reg_flags new_flags;
5530 switch (GET_CODE (x))
5533 update_set_flags (x, &new_flags);
5534 need_barrier = set_src_needs_barrier (x, new_flags, pred);
5535 if (GET_CODE (SET_SRC (x)) != CALL)
5537 new_flags.is_write = 1;
5538 need_barrier |= rtx_needs_barrier (SET_DEST (x), new_flags, pred);
5543 new_flags.is_write = 0;
5544 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
5546 /* Avoid multiple register writes, in case this is a pattern with
5547 multiple CALL rtx. This avoids a failure in rws_access_reg. */
5548 if (! flags.is_sibcall && ! rws_insn[REG_AR_CFM].write_count)
5550 new_flags.is_write = 1;
5551 need_barrier |= rws_access_regno (REG_RP, new_flags, pred);
5552 need_barrier |= rws_access_regno (AR_PFS_REGNUM, new_flags, pred);
5553 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
5558 /* X is a predicated instruction. */
5560 cond = COND_EXEC_TEST (x);
5562 need_barrier = rtx_needs_barrier (cond, flags, 0);
5564 if (GET_CODE (cond) == EQ)
5565 is_complemented = 1;
5566 cond = XEXP (cond, 0);
5567 gcc_assert (GET_CODE (cond) == REG
5568 && REGNO_REG_CLASS (REGNO (cond)) == PR_REGS);
5569 pred = REGNO (cond);
5570 if (is_complemented)
5573 need_barrier |= rtx_needs_barrier (COND_EXEC_CODE (x), flags, pred);
5574 return need_barrier;
5578 /* Clobber & use are for earlier compiler-phases only. */
5583 /* We always emit stop bits for traditional asms. We emit stop bits
5584 for volatile extended asms if TARGET_VOL_ASM_STOP is true. */
5585 if (GET_CODE (x) != ASM_OPERANDS
5586 || (MEM_VOLATILE_P (x) && TARGET_VOL_ASM_STOP))
5588 /* Avoid writing the register multiple times if we have multiple
5589 asm outputs. This avoids a failure in rws_access_reg. */
5590 if (! rws_insn[REG_VOLATILE].write_count)
5592 new_flags.is_write = 1;
5593 rws_access_regno (REG_VOLATILE, new_flags, pred);
5598 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
5599 We cannot just fall through here since then we would be confused
5600 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
5601 traditional asms unlike their normal usage. */
5603 for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; --i)
5604 if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x, i), flags, pred))
5609 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
5611 rtx pat = XVECEXP (x, 0, i);
5612 switch (GET_CODE (pat))
5615 update_set_flags (pat, &new_flags);
5616 need_barrier |= set_src_needs_barrier (pat, new_flags, pred);
5622 need_barrier |= rtx_needs_barrier (pat, flags, pred);
5633 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
5635 rtx pat = XVECEXP (x, 0, i);
5636 if (GET_CODE (pat) == SET)
5638 if (GET_CODE (SET_SRC (pat)) != CALL)
5640 new_flags.is_write = 1;
5641 need_barrier |= rtx_needs_barrier (SET_DEST (pat), new_flags,
5645 else if (GET_CODE (pat) == CLOBBER || GET_CODE (pat) == RETURN)
5646 need_barrier |= rtx_needs_barrier (pat, flags, pred);
5651 need_barrier |= rtx_needs_barrier (SUBREG_REG (x), flags, pred);
5654 if (REGNO (x) == AR_UNAT_REGNUM)
5656 for (i = 0; i < 64; ++i)
5657 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + i, flags, pred);
5660 need_barrier = rws_access_reg (x, flags, pred);
5664 /* Find the regs used in memory address computation. */
5665 new_flags.is_write = 0;
5666 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
5669 case CONST_INT: case CONST_DOUBLE: case CONST_VECTOR:
5670 case SYMBOL_REF: case LABEL_REF: case CONST:
5673 /* Operators with side-effects. */
5674 case POST_INC: case POST_DEC:
5675 gcc_assert (GET_CODE (XEXP (x, 0)) == REG);
5677 new_flags.is_write = 0;
5678 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
5679 new_flags.is_write = 1;
5680 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
5684 gcc_assert (GET_CODE (XEXP (x, 0)) == REG);
5686 new_flags.is_write = 0;
5687 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
5688 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
5689 new_flags.is_write = 1;
5690 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
5693 /* Handle common unary and binary ops for efficiency. */
5694 case COMPARE: case PLUS: case MINUS: case MULT: case DIV:
5695 case MOD: case UDIV: case UMOD: case AND: case IOR:
5696 case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT:
5697 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
5698 case NE: case EQ: case GE: case GT: case LE:
5699 case LT: case GEU: case GTU: case LEU: case LTU:
5700 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
5701 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
5704 case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND:
5705 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT:
5706 case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS:
5707 case SQRT: case FFS: case POPCOUNT:
5708 need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred);
5712 /* VEC_SELECT's second argument is a PARALLEL with integers that
5713 describe the elements selected. On ia64, those integers are
5714 always constants. Avoid walking the PARALLEL so that we don't
5715 get confused with "normal" parallels and then die. */
5716 need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred);
5720 switch (XINT (x, 1))
5722 case UNSPEC_LTOFF_DTPMOD:
5723 case UNSPEC_LTOFF_DTPREL:
5725 case UNSPEC_LTOFF_TPREL:
5727 case UNSPEC_PRED_REL_MUTEX:
5728 case UNSPEC_PIC_CALL:
5730 case UNSPEC_FETCHADD_ACQ:
5731 case UNSPEC_BSP_VALUE:
5732 case UNSPEC_FLUSHRS:
5733 case UNSPEC_BUNDLE_SELECTOR:
5736 case UNSPEC_GR_SPILL:
5737 case UNSPEC_GR_RESTORE:
5739 HOST_WIDE_INT offset = INTVAL (XVECEXP (x, 0, 1));
5740 HOST_WIDE_INT bit = (offset >> 3) & 63;
5742 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
5743 new_flags.is_write = (XINT (x, 1) == UNSPEC_GR_SPILL);
5744 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + bit,
5749 case UNSPEC_FR_SPILL:
5750 case UNSPEC_FR_RESTORE:
5751 case UNSPEC_GETF_EXP:
5752 case UNSPEC_SETF_EXP:
5754 case UNSPEC_FR_SQRT_RECIP_APPROX:
5758 case UNSPEC_CHKACLR:
5760 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
5763 case UNSPEC_FR_RECIP_APPROX:
5765 case UNSPEC_COPYSIGN:
5766 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
5767 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
5770 case UNSPEC_CMPXCHG_ACQ:
5771 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
5772 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 2), flags, pred);
5780 case UNSPEC_VOLATILE:
5781 switch (XINT (x, 1))
5784 /* Alloc must always be the first instruction of a group.
5785 We force this by always returning true. */
5786 /* ??? We might get better scheduling if we explicitly check for
5787 input/local/output register dependencies, and modify the
5788 scheduler so that alloc is always reordered to the start of
5789 the current group. We could then eliminate all of the
5790 first_instruction code. */
5791 rws_access_regno (AR_PFS_REGNUM, flags, pred);
5793 new_flags.is_write = 1;
5794 rws_access_regno (REG_AR_CFM, new_flags, pred);
5797 case UNSPECV_SET_BSP:
5801 case UNSPECV_BLOCKAGE:
5802 case UNSPECV_INSN_GROUP_BARRIER:
5804 case UNSPECV_PSAC_ALL:
5805 case UNSPECV_PSAC_NORMAL:
5814 new_flags.is_write = 0;
5815 need_barrier = rws_access_regno (REG_RP, flags, pred);
5816 need_barrier |= rws_access_regno (AR_PFS_REGNUM, flags, pred);
5818 new_flags.is_write = 1;
5819 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
5820 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
5824 format_ptr = GET_RTX_FORMAT (GET_CODE (x));
5825 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5826 switch (format_ptr[i])
5828 case '0': /* unused field */
5829 case 'i': /* integer */
5830 case 'n': /* note */
5831 case 'w': /* wide integer */
5832 case 's': /* pointer to string */
5833 case 'S': /* optional pointer to string */
5837 if (rtx_needs_barrier (XEXP (x, i), flags, pred))
5842 for (j = XVECLEN (x, i) - 1; j >= 0; --j)
5843 if (rtx_needs_barrier (XVECEXP (x, i, j), flags, pred))
5852 return need_barrier;
5855 /* Clear out the state for group_barrier_needed at the start of a
5856 sequence of insns. */
5859 init_insn_group_barriers (void)
5861 memset (rws_sum, 0, sizeof (rws_sum));
5862 first_instruction = 1;
5865 /* Given the current state, determine whether a group barrier (a stop bit) is
5866 necessary before INSN. Return nonzero if so. This modifies the state to
5867 include the effects of INSN as a side-effect. */
5870 group_barrier_needed (rtx insn)
5873 int need_barrier = 0;
5874 struct reg_flags flags;
5876 memset (&flags, 0, sizeof (flags));
5877 switch (GET_CODE (insn))
5883 /* A barrier doesn't imply an instruction group boundary. */
5887 memset (rws_insn, 0, sizeof (rws_insn));
5891 flags.is_branch = 1;
5892 flags.is_sibcall = SIBLING_CALL_P (insn);
5893 memset (rws_insn, 0, sizeof (rws_insn));
5895 /* Don't bundle a call following another call. */
5896 if ((pat = prev_active_insn (insn))
5897 && GET_CODE (pat) == CALL_INSN)
5903 need_barrier = rtx_needs_barrier (PATTERN (insn), flags, 0);
5907 if (!ia64_spec_check_p (insn))
5908 flags.is_branch = 1;
5910 /* Don't bundle a jump following a call. */
5911 if ((pat = prev_active_insn (insn))
5912 && GET_CODE (pat) == CALL_INSN)
5920 if (GET_CODE (PATTERN (insn)) == USE
5921 || GET_CODE (PATTERN (insn)) == CLOBBER)
5922 /* Don't care about USE and CLOBBER "insns"---those are used to
5923 indicate to the optimizer that it shouldn't get rid of
5924 certain operations. */
5927 pat = PATTERN (insn);
5929 /* Ug. Hack hacks hacked elsewhere. */
5930 switch (recog_memoized (insn))
5932 /* We play dependency tricks with the epilogue in order
5933 to get proper schedules. Undo this for dv analysis. */
5934 case CODE_FOR_epilogue_deallocate_stack:
5935 case CODE_FOR_prologue_allocate_stack:
5936 pat = XVECEXP (pat, 0, 0);
5939 /* The pattern we use for br.cloop confuses the code above.
5940 The second element of the vector is representative. */
5941 case CODE_FOR_doloop_end_internal:
5942 pat = XVECEXP (pat, 0, 1);
5945 /* Doesn't generate code. */
5946 case CODE_FOR_pred_rel_mutex:
5947 case CODE_FOR_prologue_use:
5954 memset (rws_insn, 0, sizeof (rws_insn));
5955 need_barrier = rtx_needs_barrier (pat, flags, 0);
5957 /* Check to see if the previous instruction was a volatile
5960 need_barrier = rws_access_regno (REG_VOLATILE, flags, 0);
5967 if (first_instruction && INSN_P (insn)
5968 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
5969 && GET_CODE (PATTERN (insn)) != USE
5970 && GET_CODE (PATTERN (insn)) != CLOBBER)
5973 first_instruction = 0;
5976 return need_barrier;
5979 /* Like group_barrier_needed, but do not clobber the current state. */
5982 safe_group_barrier_needed (rtx insn)
5984 struct reg_write_state rws_saved[NUM_REGS];
5985 int saved_first_instruction;
5988 memcpy (rws_saved, rws_sum, NUM_REGS * sizeof *rws_saved);
5989 saved_first_instruction = first_instruction;
5991 t = group_barrier_needed (insn);
5993 memcpy (rws_sum, rws_saved, NUM_REGS * sizeof *rws_saved);
5994 first_instruction = saved_first_instruction;
5999 /* Scan the current function and insert stop bits as necessary to
6000 eliminate dependencies. This function assumes that a final
6001 instruction scheduling pass has been run which has already
6002 inserted most of the necessary stop bits. This function only
6003 inserts new ones at basic block boundaries, since these are
6004 invisible to the scheduler. */
6007 emit_insn_group_barriers (FILE *dump)
6011 int insns_since_last_label = 0;
6013 init_insn_group_barriers ();
6015 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6017 if (GET_CODE (insn) == CODE_LABEL)
6019 if (insns_since_last_label)
6021 insns_since_last_label = 0;
6023 else if (GET_CODE (insn) == NOTE
6024 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_BASIC_BLOCK)
6026 if (insns_since_last_label)
6028 insns_since_last_label = 0;
6030 else if (GET_CODE (insn) == INSN
6031 && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
6032 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
6034 init_insn_group_barriers ();
6037 else if (INSN_P (insn))
6039 insns_since_last_label = 1;
6041 if (group_barrier_needed (insn))
6046 fprintf (dump, "Emitting stop before label %d\n",
6047 INSN_UID (last_label));
6048 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), last_label);
6051 init_insn_group_barriers ();
6059 /* Like emit_insn_group_barriers, but run if no final scheduling pass was run.
6060 This function has to emit all necessary group barriers. */
6063 emit_all_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED)
6067 init_insn_group_barriers ();
6069 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6071 if (GET_CODE (insn) == BARRIER)
6073 rtx last = prev_active_insn (insn);
6077 if (GET_CODE (last) == JUMP_INSN
6078 && GET_CODE (PATTERN (last)) == ADDR_DIFF_VEC)
6079 last = prev_active_insn (last);
6080 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
6081 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
6083 init_insn_group_barriers ();
6085 else if (INSN_P (insn))
6087 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
6088 init_insn_group_barriers ();
6089 else if (group_barrier_needed (insn))
6091 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn);
6092 init_insn_group_barriers ();
6093 group_barrier_needed (insn);
6101 /* Instruction scheduling support. */
6103 #define NR_BUNDLES 10
6105 /* A list of names of all available bundles. */
6107 static const char *bundle_name [NR_BUNDLES] =
6113 #if NR_BUNDLES == 10
6123 /* Nonzero if we should insert stop bits into the schedule. */
6125 int ia64_final_schedule = 0;
6127 /* Codes of the corresponding queried units: */
6129 static int _0mii_, _0mmi_, _0mfi_, _0mmf_;
6130 static int _0bbb_, _0mbb_, _0mib_, _0mmb_, _0mfb_, _0mlx_;
6132 static int _1mii_, _1mmi_, _1mfi_, _1mmf_;
6133 static int _1bbb_, _1mbb_, _1mib_, _1mmb_, _1mfb_, _1mlx_;
6135 static int pos_1, pos_2, pos_3, pos_4, pos_5, pos_6;
6137 /* The following variable value is an insn group barrier. */
6139 static rtx dfa_stop_insn;
6141 /* The following variable value is the last issued insn. */
6143 static rtx last_scheduled_insn;
6145 /* The following variable value is size of the DFA state. */
6147 static size_t dfa_state_size;
6149 /* The following variable value is pointer to a DFA state used as
6150 temporary variable. */
6152 static state_t temp_dfa_state = NULL;
6154 /* The following variable value is DFA state after issuing the last
6157 static state_t prev_cycle_state = NULL;
6159 /* The following array element values are TRUE if the corresponding
6160 insn requires to add stop bits before it. */
6162 static char *stops_p = NULL;
6164 /* The following array element values are ZERO for non-speculative
6165 instructions and hold corresponding speculation check number for
6166 speculative instructions. */
6167 static int *spec_check_no = NULL;
6169 /* Size of spec_check_no array. */
6170 static int max_uid = 0;
6172 /* The following variable is used to set up the mentioned above array. */
6174 static int stop_before_p = 0;
6176 /* The following variable value is length of the arrays `clocks' and
6179 static int clocks_length;
6181 /* The following array element values are cycles on which the
6182 corresponding insn will be issued. The array is used only for
6187 /* The following array element values are numbers of cycles should be
6188 added to improve insn scheduling for MM_insns for Itanium1. */
6190 static int *add_cycles;
6192 /* The following variable value is number of data speculations in progress. */
6193 static int pending_data_specs = 0;
6195 static rtx ia64_single_set (rtx);
6196 static void ia64_emit_insn_before (rtx, rtx);
6198 /* Map a bundle number to its pseudo-op. */
6201 get_bundle_name (int b)
6203 return bundle_name[b];
6207 /* Return the maximum number of instructions a cpu can issue. */
6210 ia64_issue_rate (void)
6215 /* Helper function - like single_set, but look inside COND_EXEC. */
6218 ia64_single_set (rtx insn)
6220 rtx x = PATTERN (insn), ret;
6221 if (GET_CODE (x) == COND_EXEC)
6222 x = COND_EXEC_CODE (x);
6223 if (GET_CODE (x) == SET)
6226 /* Special case here prologue_allocate_stack and epilogue_deallocate_stack.
6227 Although they are not classical single set, the second set is there just
6228 to protect it from moving past FP-relative stack accesses. */
6229 switch (recog_memoized (insn))
6231 case CODE_FOR_prologue_allocate_stack:
6232 case CODE_FOR_epilogue_deallocate_stack:
6233 ret = XVECEXP (x, 0, 0);
6237 ret = single_set_2 (insn, x);
6244 /* Adjust the cost of a scheduling dependency.
6245 Return the new cost of a dependency of type DEP_TYPE or INSN on DEP_INSN.
6246 COST is the current cost. */
6249 ia64_adjust_cost_2 (rtx insn, int dep_type1, rtx dep_insn, int cost)
6251 enum reg_note dep_type = (enum reg_note) dep_type1;
6252 enum attr_itanium_class dep_class;
6253 enum attr_itanium_class insn_class;
6255 if (dep_type != REG_DEP_OUTPUT)
6258 insn_class = ia64_safe_itanium_class (insn);
6259 dep_class = ia64_safe_itanium_class (dep_insn);
6260 if (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF
6261 || insn_class == ITANIUM_CLASS_ST || insn_class == ITANIUM_CLASS_STF)
6267 /* Like emit_insn_before, but skip cycle_display notes.
6268 ??? When cycle display notes are implemented, update this. */
6271 ia64_emit_insn_before (rtx insn, rtx before)
6273 emit_insn_before (insn, before);
6276 /* The following function marks insns who produce addresses for load
6277 and store insns. Such insns will be placed into M slots because it
6278 decrease latency time for Itanium1 (see function
6279 `ia64_produce_address_p' and the DFA descriptions). */
6282 ia64_dependencies_evaluation_hook (rtx head, rtx tail)
6284 rtx insn, link, next, next_tail;
6286 /* Before reload, which_alternative is not set, which means that
6287 ia64_safe_itanium_class will produce wrong results for (at least)
6288 move instructions. */
6289 if (!reload_completed)
6292 next_tail = NEXT_INSN (tail);
6293 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
6296 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
6298 && ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IALU)
6300 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
6302 enum attr_itanium_class c;
6304 if (REG_NOTE_KIND (link) != REG_DEP_TRUE)
6306 next = XEXP (link, 0);
6307 c = ia64_safe_itanium_class (next);
6308 if ((c == ITANIUM_CLASS_ST
6309 || c == ITANIUM_CLASS_STF)
6310 && ia64_st_address_bypass_p (insn, next))
6312 else if ((c == ITANIUM_CLASS_LD
6313 || c == ITANIUM_CLASS_FLD
6314 || c == ITANIUM_CLASS_FLDP)
6315 && ia64_ld_address_bypass_p (insn, next))
6318 insn->call = link != 0;
6322 /* We're beginning a new block. Initialize data structures as necessary. */
6325 ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED,
6326 int sched_verbose ATTRIBUTE_UNUSED,
6327 int max_ready ATTRIBUTE_UNUSED)
6329 #ifdef ENABLE_CHECKING
6332 if (reload_completed)
6333 for (insn = NEXT_INSN (current_sched_info->prev_head);
6334 insn != current_sched_info->next_tail;
6335 insn = NEXT_INSN (insn))
6336 gcc_assert (!SCHED_GROUP_P (insn));
6338 last_scheduled_insn = NULL_RTX;
6339 init_insn_group_barriers ();
6342 /* We're beginning a scheduling pass. Check assertion. */
6345 ia64_sched_init_global (FILE *dump ATTRIBUTE_UNUSED,
6346 int sched_verbose ATTRIBUTE_UNUSED,
6347 int max_ready ATTRIBUTE_UNUSED)
6349 gcc_assert (!pending_data_specs);
6352 /* Scheduling pass is now finished. Free/reset static variable. */
6354 ia64_sched_finish_global (FILE *dump ATTRIBUTE_UNUSED,
6355 int sched_verbose ATTRIBUTE_UNUSED)
6357 free (spec_check_no);
6362 /* We are about to being issuing insns for this clock cycle.
6363 Override the default sort algorithm to better slot instructions. */
6366 ia64_dfa_sched_reorder (FILE *dump, int sched_verbose, rtx *ready,
6367 int *pn_ready, int clock_var ATTRIBUTE_UNUSED,
6371 int n_ready = *pn_ready;
6372 rtx *e_ready = ready + n_ready;
6376 fprintf (dump, "// ia64_dfa_sched_reorder (type %d):\n", reorder_type);
6378 if (reorder_type == 0)
6380 /* First, move all USEs, CLOBBERs and other crud out of the way. */
6382 for (insnp = ready; insnp < e_ready; insnp++)
6383 if (insnp < e_ready)
6386 enum attr_type t = ia64_safe_type (insn);
6387 if (t == TYPE_UNKNOWN)
6389 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
6390 || asm_noperands (PATTERN (insn)) >= 0)
6392 rtx lowest = ready[n_asms];
6393 ready[n_asms] = insn;
6399 rtx highest = ready[n_ready - 1];
6400 ready[n_ready - 1] = insn;
6407 if (n_asms < n_ready)
6409 /* Some normal insns to process. Skip the asms. */
6413 else if (n_ready > 0)
6417 if (ia64_final_schedule)
6420 int nr_need_stop = 0;
6422 for (insnp = ready; insnp < e_ready; insnp++)
6423 if (safe_group_barrier_needed (*insnp))
6426 if (reorder_type == 1 && n_ready == nr_need_stop)
6428 if (reorder_type == 0)
6431 /* Move down everything that needs a stop bit, preserving
6433 while (insnp-- > ready + deleted)
6434 while (insnp >= ready + deleted)
6437 if (! safe_group_barrier_needed (insn))
6439 memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx));
6450 /* We are about to being issuing insns for this clock cycle. Override
6451 the default sort algorithm to better slot instructions. */
6454 ia64_sched_reorder (FILE *dump, int sched_verbose, rtx *ready, int *pn_ready,
6457 return ia64_dfa_sched_reorder (dump, sched_verbose, ready,
6458 pn_ready, clock_var, 0);
6461 /* Like ia64_sched_reorder, but called after issuing each insn.
6462 Override the default sort algorithm to better slot instructions. */
6465 ia64_sched_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
6466 int sched_verbose ATTRIBUTE_UNUSED, rtx *ready,
6467 int *pn_ready, int clock_var)
6469 if (ia64_tune == PROCESSOR_ITANIUM && reload_completed && last_scheduled_insn)
6470 clocks [INSN_UID (last_scheduled_insn)] = clock_var;
6471 return ia64_dfa_sched_reorder (dump, sched_verbose, ready, pn_ready,
6475 /* We are about to issue INSN. Return the number of insns left on the
6476 ready queue that can be issued this cycle. */
6479 ia64_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
6480 int sched_verbose ATTRIBUTE_UNUSED,
6481 rtx insn ATTRIBUTE_UNUSED,
6482 int can_issue_more ATTRIBUTE_UNUSED)
6484 if (current_sched_info->flags & DO_SPECULATION)
6485 /* Modulo scheduling does not extend h_i_d when emitting
6486 new instructions. Deal with it. */
6488 if (DONE_SPEC (insn) & BEGIN_DATA)
6489 pending_data_specs++;
6490 if (CHECK_SPEC (insn) & BEGIN_DATA)
6491 pending_data_specs--;
6494 last_scheduled_insn = insn;
6495 memcpy (prev_cycle_state, curr_state, dfa_state_size);
6496 if (reload_completed)
6498 int needed = group_barrier_needed (insn);
6500 gcc_assert (!needed);
6501 if (GET_CODE (insn) == CALL_INSN)
6502 init_insn_group_barriers ();
6503 stops_p [INSN_UID (insn)] = stop_before_p;
6509 /* We are choosing insn from the ready queue. Return nonzero if INSN
6513 ia64_first_cycle_multipass_dfa_lookahead_guard (rtx insn)
6515 gcc_assert (insn && INSN_P (insn));
6516 return ((!reload_completed
6517 || !safe_group_barrier_needed (insn))
6518 && ia64_first_cycle_multipass_dfa_lookahead_guard_spec (insn));
6521 /* We are choosing insn from the ready queue. Return nonzero if INSN
6525 ia64_first_cycle_multipass_dfa_lookahead_guard_spec (rtx insn)
6527 gcc_assert (insn && INSN_P (insn));
6528 /* Size of ALAT is 32. As far as we perform conservative data speculation,
6529 we keep ALAT half-empty. */
6530 return (pending_data_specs < 16
6531 || !(TODO_SPEC (insn) & BEGIN_DATA));
6534 /* The following variable value is pseudo-insn used by the DFA insn
6535 scheduler to change the DFA state when the simulated clock is
6538 static rtx dfa_pre_cycle_insn;
6540 /* We are about to being issuing INSN. Return nonzero if we cannot
6541 issue it on given cycle CLOCK and return zero if we should not sort
6542 the ready queue on the next clock start. */
6545 ia64_dfa_new_cycle (FILE *dump, int verbose, rtx insn, int last_clock,
6546 int clock, int *sort_p)
6548 int setup_clocks_p = FALSE;
6550 gcc_assert (insn && INSN_P (insn));
6551 if ((reload_completed && safe_group_barrier_needed (insn))
6552 || (last_scheduled_insn
6553 && (GET_CODE (last_scheduled_insn) == CALL_INSN
6554 || GET_CODE (PATTERN (last_scheduled_insn)) == ASM_INPUT
6555 || asm_noperands (PATTERN (last_scheduled_insn)) >= 0)))
6557 init_insn_group_barriers ();
6558 if (verbose && dump)
6559 fprintf (dump, "// Stop should be before %d%s\n", INSN_UID (insn),
6560 last_clock == clock ? " + cycle advance" : "");
6562 if (last_clock == clock)
6564 state_transition (curr_state, dfa_stop_insn);
6565 if (TARGET_EARLY_STOP_BITS)
6566 *sort_p = (last_scheduled_insn == NULL_RTX
6567 || GET_CODE (last_scheduled_insn) != CALL_INSN);
6572 else if (reload_completed)
6573 setup_clocks_p = TRUE;
6574 if (GET_CODE (PATTERN (last_scheduled_insn)) == ASM_INPUT
6575 || asm_noperands (PATTERN (last_scheduled_insn)) >= 0)
6576 state_reset (curr_state);
6579 memcpy (curr_state, prev_cycle_state, dfa_state_size);
6580 state_transition (curr_state, dfa_stop_insn);
6581 state_transition (curr_state, dfa_pre_cycle_insn);
6582 state_transition (curr_state, NULL);
6585 else if (reload_completed)
6586 setup_clocks_p = TRUE;
6587 if (setup_clocks_p && ia64_tune == PROCESSOR_ITANIUM
6588 && GET_CODE (PATTERN (insn)) != ASM_INPUT
6589 && asm_noperands (PATTERN (insn)) < 0)
6591 enum attr_itanium_class c = ia64_safe_itanium_class (insn);
6593 if (c != ITANIUM_CLASS_MMMUL && c != ITANIUM_CLASS_MMSHF)
6598 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
6599 if (REG_NOTE_KIND (link) == 0)
6601 enum attr_itanium_class dep_class;
6602 rtx dep_insn = XEXP (link, 0);
6604 dep_class = ia64_safe_itanium_class (dep_insn);
6605 if ((dep_class == ITANIUM_CLASS_MMMUL
6606 || dep_class == ITANIUM_CLASS_MMSHF)
6607 && last_clock - clocks [INSN_UID (dep_insn)] < 4
6609 || last_clock - clocks [INSN_UID (dep_insn)] < d))
6610 d = last_clock - clocks [INSN_UID (dep_insn)];
6613 add_cycles [INSN_UID (insn)] = 3 - d;
6619 /* Implement targetm.sched.h_i_d_extended hook.
6620 Extend internal data structures. */
6622 ia64_h_i_d_extended (void)
6624 if (current_sched_info->flags & DO_SPECULATION)
6626 int new_max_uid = get_max_uid () + 1;
6628 spec_check_no = xrecalloc (spec_check_no, new_max_uid,
6629 max_uid, sizeof (*spec_check_no));
6630 max_uid = new_max_uid;
6633 if (stops_p != NULL)
6635 int new_clocks_length = get_max_uid () + 1;
6637 stops_p = xrecalloc (stops_p, new_clocks_length, clocks_length, 1);
6639 if (ia64_tune == PROCESSOR_ITANIUM)
6641 clocks = xrecalloc (clocks, new_clocks_length, clocks_length,
6643 add_cycles = xrecalloc (add_cycles, new_clocks_length, clocks_length,
6647 clocks_length = new_clocks_length;
6651 /* Constants that help mapping 'enum machine_mode' to int. */
6654 SPEC_MODE_INVALID = -1,
6655 SPEC_MODE_FIRST = 0,
6656 SPEC_MODE_FOR_EXTEND_FIRST = 1,
6657 SPEC_MODE_FOR_EXTEND_LAST = 3,
6661 /* Return index of the MODE. */
6663 ia64_mode_to_int (enum machine_mode mode)
6667 case BImode: return 0; /* SPEC_MODE_FIRST */
6668 case QImode: return 1; /* SPEC_MODE_FOR_EXTEND_FIRST */
6669 case HImode: return 2;
6670 case SImode: return 3; /* SPEC_MODE_FOR_EXTEND_LAST */
6671 case DImode: return 4;
6672 case SFmode: return 5;
6673 case DFmode: return 6;
6674 case XFmode: return 7;
6676 /* ??? This mode needs testing. Bypasses for ldfp8 instruction are not
6677 mentioned in itanium[12].md. Predicate fp_register_operand also
6678 needs to be defined. Bottom line: better disable for now. */
6679 return SPEC_MODE_INVALID;
6680 default: return SPEC_MODE_INVALID;
6684 /* Provide information about speculation capabilities. */
6686 ia64_set_sched_flags (spec_info_t spec_info)
6688 unsigned int *flags = &(current_sched_info->flags);
6690 if (*flags & SCHED_RGN
6691 || *flags & SCHED_EBB)
6695 if ((mflag_sched_br_data_spec && !reload_completed && optimize > 0)
6696 || (mflag_sched_ar_data_spec && reload_completed))
6700 if ((mflag_sched_br_in_data_spec && !reload_completed)
6701 || (mflag_sched_ar_in_data_spec && reload_completed))
6705 if (mflag_sched_control_spec)
6707 mask |= BEGIN_CONTROL;
6709 if (mflag_sched_in_control_spec)
6710 mask |= BE_IN_CONTROL;
6713 gcc_assert (*flags & USE_GLAT);
6717 *flags |= USE_DEPS_LIST | DETACH_LIFE_INFO | DO_SPECULATION;
6719 spec_info->mask = mask;
6720 spec_info->flags = 0;
6722 if ((mask & DATA_SPEC) && mflag_sched_prefer_non_data_spec_insns)
6723 spec_info->flags |= PREFER_NON_DATA_SPEC;
6725 if ((mask & CONTROL_SPEC)
6726 && mflag_sched_prefer_non_control_spec_insns)
6727 spec_info->flags |= PREFER_NON_CONTROL_SPEC;
6729 if (mflag_sched_spec_verbose)
6731 if (sched_verbose >= 1)
6732 spec_info->dump = sched_dump;
6734 spec_info->dump = stderr;
6737 spec_info->dump = 0;
6739 if (mflag_sched_count_spec_in_critical_path)
6740 spec_info->flags |= COUNT_SPEC_IN_CRITICAL_PATH;
6745 /* Implement targetm.sched.speculate_insn hook.
6746 Check if the INSN can be TS speculative.
6747 If 'no' - return -1.
6748 If 'yes' - generate speculative pattern in the NEW_PAT and return 1.
6749 If current pattern of the INSN already provides TS speculation, return 0. */
6751 ia64_speculate_insn (rtx insn, ds_t ts, rtx *new_pat)
6753 rtx pat, reg, mem, mem_reg;
6754 int mode_no, gen_p = 1;
6757 gcc_assert (!(ts & ~BEGIN_SPEC) && ts);
6759 pat = PATTERN (insn);
6761 if (GET_CODE (pat) == COND_EXEC)
6762 pat = COND_EXEC_CODE (pat);
6764 if (GET_CODE (pat) != SET)
6766 reg = SET_DEST (pat);
6770 mem = SET_SRC (pat);
6771 if (GET_CODE (mem) == ZERO_EXTEND)
6773 mem = XEXP (mem, 0);
6779 if (GET_CODE (mem) == UNSPEC)
6783 code = XINT (mem, 1);
6784 if (code != UNSPEC_LDA && code != UNSPEC_LDS && code != UNSPEC_LDSA)
6787 if ((code == UNSPEC_LDA && !(ts & BEGIN_CONTROL))
6788 || (code == UNSPEC_LDS && !(ts & BEGIN_DATA))
6789 || code == UNSPEC_LDSA)
6792 mem = XVECEXP (mem, 0, 0);
6793 gcc_assert (MEM_P (mem));
6797 mem_reg = XEXP (mem, 0);
6798 if (!REG_P (mem_reg))
6801 /* We should use MEM's mode since REG's mode in presence of ZERO_EXTEND
6802 will always be DImode. */
6803 mode_no = ia64_mode_to_int (GET_MODE (mem));
6805 if (mode_no == SPEC_MODE_INVALID
6807 && !(SPEC_MODE_FOR_EXTEND_FIRST <= mode_no
6808 && mode_no <= SPEC_MODE_FOR_EXTEND_LAST)))
6811 extract_insn_cached (insn);
6812 gcc_assert (reg == recog_data.operand[0] && mem == recog_data.operand[1]);
6813 *new_pat = ia64_gen_spec_insn (insn, ts, mode_no, gen_p != 0, extend_p);
6820 /* Offset to reach ZERO_EXTEND patterns. */
6821 SPEC_GEN_EXTEND_OFFSET = SPEC_MODE_LAST - SPEC_MODE_FOR_EXTEND_FIRST + 1,
6822 /* Number of patterns for each speculation mode. */
6823 SPEC_N = (SPEC_MODE_LAST
6824 + SPEC_MODE_FOR_EXTEND_LAST - SPEC_MODE_FOR_EXTEND_FIRST + 2)
6827 enum SPEC_GEN_LD_MAP
6829 /* Offset to ld.a patterns. */
6830 SPEC_GEN_A = 0 * SPEC_N,
6831 /* Offset to ld.s patterns. */
6832 SPEC_GEN_S = 1 * SPEC_N,
6833 /* Offset to ld.sa patterns. */
6834 SPEC_GEN_SA = 2 * SPEC_N,
6835 /* Offset to ld.sa patterns. For this patterns corresponding ld.c will
6837 SPEC_GEN_SA_FOR_S = 3 * SPEC_N
6840 /* These offsets are used to get (4 * SPEC_N). */
6841 enum SPEC_GEN_CHECK_OFFSET
6843 SPEC_GEN_CHKA_FOR_A_OFFSET = 4 * SPEC_N - SPEC_GEN_A,
6844 SPEC_GEN_CHKA_FOR_SA_OFFSET = 4 * SPEC_N - SPEC_GEN_SA
6847 /* If GEN_P is true, calculate the index of needed speculation check and return
6848 speculative pattern for INSN with speculative mode TS, machine mode
6849 MODE_NO and with ZERO_EXTEND (if EXTEND_P is true).
6850 If GEN_P is false, just calculate the index of needed speculation check. */
6852 ia64_gen_spec_insn (rtx insn, ds_t ts, int mode_no, bool gen_p, bool extend_p)
6858 static rtx (* const gen_load[]) (rtx, rtx) = {
6868 gen_zero_extendqidi2_advanced,
6869 gen_zero_extendhidi2_advanced,
6870 gen_zero_extendsidi2_advanced,
6872 gen_movbi_speculative,
6873 gen_movqi_speculative,
6874 gen_movhi_speculative,
6875 gen_movsi_speculative,
6876 gen_movdi_speculative,
6877 gen_movsf_speculative,
6878 gen_movdf_speculative,
6879 gen_movxf_speculative,
6880 gen_movti_speculative,
6881 gen_zero_extendqidi2_speculative,
6882 gen_zero_extendhidi2_speculative,
6883 gen_zero_extendsidi2_speculative,
6885 gen_movbi_speculative_advanced,
6886 gen_movqi_speculative_advanced,
6887 gen_movhi_speculative_advanced,
6888 gen_movsi_speculative_advanced,
6889 gen_movdi_speculative_advanced,
6890 gen_movsf_speculative_advanced,
6891 gen_movdf_speculative_advanced,
6892 gen_movxf_speculative_advanced,
6893 gen_movti_speculative_advanced,
6894 gen_zero_extendqidi2_speculative_advanced,
6895 gen_zero_extendhidi2_speculative_advanced,
6896 gen_zero_extendsidi2_speculative_advanced,
6898 gen_movbi_speculative_advanced,
6899 gen_movqi_speculative_advanced,
6900 gen_movhi_speculative_advanced,
6901 gen_movsi_speculative_advanced,
6902 gen_movdi_speculative_advanced,
6903 gen_movsf_speculative_advanced,
6904 gen_movdf_speculative_advanced,
6905 gen_movxf_speculative_advanced,
6906 gen_movti_speculative_advanced,
6907 gen_zero_extendqidi2_speculative_advanced,
6908 gen_zero_extendhidi2_speculative_advanced,
6909 gen_zero_extendsidi2_speculative_advanced
6912 load_no = extend_p ? mode_no + SPEC_GEN_EXTEND_OFFSET : mode_no;
6914 if (ts & BEGIN_DATA)
6916 /* We don't need recovery because even if this is ld.sa
6917 ALAT entry will be allocated only if NAT bit is set to zero.
6918 So it is enough to use ld.c here. */
6920 if (ts & BEGIN_CONTROL)
6922 load_no += SPEC_GEN_SA;
6924 if (!mflag_sched_ldc)
6925 shift = SPEC_GEN_CHKA_FOR_SA_OFFSET;
6929 load_no += SPEC_GEN_A;
6931 if (!mflag_sched_ldc)
6932 shift = SPEC_GEN_CHKA_FOR_A_OFFSET;
6935 else if (ts & BEGIN_CONTROL)
6937 /* ld.sa can be used instead of ld.s to avoid basic block splitting. */
6938 if (!mflag_control_ldc)
6939 load_no += SPEC_GEN_S;
6942 gcc_assert (mflag_sched_ldc);
6943 load_no += SPEC_GEN_SA_FOR_S;
6949 /* Set the desired check index. We add '1', because zero element in this
6950 array means, that instruction with such uid is non-speculative. */
6951 spec_check_no[INSN_UID (insn)] = load_no + shift + 1;
6956 new_pat = gen_load[load_no] (copy_rtx (recog_data.operand[0]),
6957 copy_rtx (recog_data.operand[1]));
6959 pat = PATTERN (insn);
6960 if (GET_CODE (pat) == COND_EXEC)
6961 new_pat = gen_rtx_COND_EXEC (VOIDmode, copy_rtx
6962 (COND_EXEC_TEST (pat)), new_pat);
6967 /* Offset to branchy checks. */
6968 enum { SPEC_GEN_CHECK_MUTATION_OFFSET = 5 * SPEC_N };
6970 /* Return nonzero, if INSN needs branchy recovery check. */
6972 ia64_needs_block_p (rtx insn)
6976 check_no = spec_check_no[INSN_UID(insn)] - 1;
6977 gcc_assert (0 <= check_no && check_no < SPEC_GEN_CHECK_MUTATION_OFFSET);
6979 return ((SPEC_GEN_S <= check_no && check_no < SPEC_GEN_S + SPEC_N)
6980 || (4 * SPEC_N <= check_no && check_no < 4 * SPEC_N + SPEC_N));
6983 /* Generate (or regenerate, if (MUTATE_P)) recovery check for INSN.
6984 If (LABEL != 0 || MUTATE_P), generate branchy recovery check.
6985 Otherwise, generate a simple check. */
6987 ia64_gen_check (rtx insn, rtx label, bool mutate_p)
6989 rtx op1, pat, check_pat;
6991 static rtx (* const gen_check[]) (rtx, rtx) = {
7001 gen_zero_extendqidi2_clr,
7002 gen_zero_extendhidi2_clr,
7003 gen_zero_extendsidi2_clr,
7005 gen_speculation_check_bi,
7006 gen_speculation_check_qi,
7007 gen_speculation_check_hi,
7008 gen_speculation_check_si,
7009 gen_speculation_check_di,
7010 gen_speculation_check_sf,
7011 gen_speculation_check_df,
7012 gen_speculation_check_xf,
7013 gen_speculation_check_ti,
7014 gen_speculation_check_di,
7015 gen_speculation_check_di,
7016 gen_speculation_check_di,
7027 gen_zero_extendqidi2_clr,
7028 gen_zero_extendhidi2_clr,
7029 gen_zero_extendsidi2_clr,
7040 gen_zero_extendqidi2_clr,
7041 gen_zero_extendhidi2_clr,
7042 gen_zero_extendsidi2_clr,
7044 gen_advanced_load_check_clr_bi,
7045 gen_advanced_load_check_clr_qi,
7046 gen_advanced_load_check_clr_hi,
7047 gen_advanced_load_check_clr_si,
7048 gen_advanced_load_check_clr_di,
7049 gen_advanced_load_check_clr_sf,
7050 gen_advanced_load_check_clr_df,
7051 gen_advanced_load_check_clr_xf,
7052 gen_advanced_load_check_clr_ti,
7053 gen_advanced_load_check_clr_di,
7054 gen_advanced_load_check_clr_di,
7055 gen_advanced_load_check_clr_di,
7057 /* Following checks are generated during mutation. */
7058 gen_advanced_load_check_clr_bi,
7059 gen_advanced_load_check_clr_qi,
7060 gen_advanced_load_check_clr_hi,
7061 gen_advanced_load_check_clr_si,
7062 gen_advanced_load_check_clr_di,
7063 gen_advanced_load_check_clr_sf,
7064 gen_advanced_load_check_clr_df,
7065 gen_advanced_load_check_clr_xf,
7066 gen_advanced_load_check_clr_ti,
7067 gen_advanced_load_check_clr_di,
7068 gen_advanced_load_check_clr_di,
7069 gen_advanced_load_check_clr_di,
7071 0,0,0,0,0,0,0,0,0,0,0,0,
7073 gen_advanced_load_check_clr_bi,
7074 gen_advanced_load_check_clr_qi,
7075 gen_advanced_load_check_clr_hi,
7076 gen_advanced_load_check_clr_si,
7077 gen_advanced_load_check_clr_di,
7078 gen_advanced_load_check_clr_sf,
7079 gen_advanced_load_check_clr_df,
7080 gen_advanced_load_check_clr_xf,
7081 gen_advanced_load_check_clr_ti,
7082 gen_advanced_load_check_clr_di,
7083 gen_advanced_load_check_clr_di,
7084 gen_advanced_load_check_clr_di,
7086 gen_speculation_check_bi,
7087 gen_speculation_check_qi,
7088 gen_speculation_check_hi,
7089 gen_speculation_check_si,
7090 gen_speculation_check_di,
7091 gen_speculation_check_sf,
7092 gen_speculation_check_df,
7093 gen_speculation_check_xf,
7094 gen_speculation_check_ti,
7095 gen_speculation_check_di,
7096 gen_speculation_check_di,
7097 gen_speculation_check_di
7100 extract_insn_cached (insn);
7104 gcc_assert (mutate_p || ia64_needs_block_p (insn));
7109 gcc_assert (!mutate_p && !ia64_needs_block_p (insn));
7110 op1 = copy_rtx (recog_data.operand[1]);
7115 Find the speculation check number by searching for original
7116 speculative load in the RESOLVED_DEPS list of INSN.
7117 As long as patterns are unique for each instruction, this can be
7118 accomplished by matching ORIG_PAT fields. */
7122 rtx orig_pat = ORIG_PAT (insn);
7124 for (link = RESOLVED_DEPS (insn); link; link = XEXP (link, 1))
7126 rtx x = XEXP (link, 0);
7128 if (ORIG_PAT (x) == orig_pat)
7129 check_no = spec_check_no[INSN_UID (x)];
7131 gcc_assert (check_no);
7133 spec_check_no[INSN_UID (insn)] = (check_no
7134 + SPEC_GEN_CHECK_MUTATION_OFFSET);
7137 check_pat = (gen_check[spec_check_no[INSN_UID (insn)] - 1]
7138 (copy_rtx (recog_data.operand[0]), op1));
7140 pat = PATTERN (insn);
7141 if (GET_CODE (pat) == COND_EXEC)
7142 check_pat = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (COND_EXEC_TEST (pat)),
7148 /* Return nonzero, if X is branchy recovery check. */
7150 ia64_spec_check_p (rtx x)
7153 if (GET_CODE (x) == COND_EXEC)
7154 x = COND_EXEC_CODE (x);
7155 if (GET_CODE (x) == SET)
7156 return ia64_spec_check_src_p (SET_SRC (x));
7160 /* Return nonzero, if SRC belongs to recovery check. */
7162 ia64_spec_check_src_p (rtx src)
7164 if (GET_CODE (src) == IF_THEN_ELSE)
7169 if (GET_CODE (t) == NE)
7173 if (GET_CODE (t) == UNSPEC)
7179 if (code == UNSPEC_CHKACLR
7180 || code == UNSPEC_CHKS
7181 || code == UNSPEC_LDCCLR)
7183 gcc_assert (code != 0);
7193 /* The following page contains abstract data `bundle states' which are
7194 used for bundling insns (inserting nops and template generation). */
7196 /* The following describes state of insn bundling. */
7200 /* Unique bundle state number to identify them in the debugging
7203 rtx insn; /* corresponding insn, NULL for the 1st and the last state */
7204 /* number nops before and after the insn */
7205 short before_nops_num, after_nops_num;
7206 int insn_num; /* insn number (0 - for initial state, 1 - for the 1st
7208 int cost; /* cost of the state in cycles */
7209 int accumulated_insns_num; /* number of all previous insns including
7210 nops. L is considered as 2 insns */
7211 int branch_deviation; /* deviation of previous branches from 3rd slots */
7212 struct bundle_state *next; /* next state with the same insn_num */
7213 struct bundle_state *originator; /* originator (previous insn state) */
7214 /* All bundle states are in the following chain. */
7215 struct bundle_state *allocated_states_chain;
7216 /* The DFA State after issuing the insn and the nops. */
7220 /* The following is map insn number to the corresponding bundle state. */
7222 static struct bundle_state **index_to_bundle_states;
7224 /* The unique number of next bundle state. */
7226 static int bundle_states_num;
7228 /* All allocated bundle states are in the following chain. */
7230 static struct bundle_state *allocated_bundle_states_chain;
7232 /* All allocated but not used bundle states are in the following
7235 static struct bundle_state *free_bundle_state_chain;
7238 /* The following function returns a free bundle state. */
7240 static struct bundle_state *
7241 get_free_bundle_state (void)
7243 struct bundle_state *result;
7245 if (free_bundle_state_chain != NULL)
7247 result = free_bundle_state_chain;
7248 free_bundle_state_chain = result->next;
7252 result = xmalloc (sizeof (struct bundle_state));
7253 result->dfa_state = xmalloc (dfa_state_size);
7254 result->allocated_states_chain = allocated_bundle_states_chain;
7255 allocated_bundle_states_chain = result;
7257 result->unique_num = bundle_states_num++;
7262 /* The following function frees given bundle state. */
7265 free_bundle_state (struct bundle_state *state)
7267 state->next = free_bundle_state_chain;
7268 free_bundle_state_chain = state;
7271 /* Start work with abstract data `bundle states'. */
7274 initiate_bundle_states (void)
7276 bundle_states_num = 0;
7277 free_bundle_state_chain = NULL;
7278 allocated_bundle_states_chain = NULL;
7281 /* Finish work with abstract data `bundle states'. */
7284 finish_bundle_states (void)
7286 struct bundle_state *curr_state, *next_state;
7288 for (curr_state = allocated_bundle_states_chain;
7290 curr_state = next_state)
7292 next_state = curr_state->allocated_states_chain;
7293 free (curr_state->dfa_state);
7298 /* Hash table of the bundle states. The key is dfa_state and insn_num
7299 of the bundle states. */
7301 static htab_t bundle_state_table;
7303 /* The function returns hash of BUNDLE_STATE. */
7306 bundle_state_hash (const void *bundle_state)
7308 const struct bundle_state *state = (struct bundle_state *) bundle_state;
7311 for (result = i = 0; i < dfa_state_size; i++)
7312 result += (((unsigned char *) state->dfa_state) [i]
7313 << ((i % CHAR_BIT) * 3 + CHAR_BIT));
7314 return result + state->insn_num;
7317 /* The function returns nonzero if the bundle state keys are equal. */
7320 bundle_state_eq_p (const void *bundle_state_1, const void *bundle_state_2)
7322 const struct bundle_state * state1 = (struct bundle_state *) bundle_state_1;
7323 const struct bundle_state * state2 = (struct bundle_state *) bundle_state_2;
7325 return (state1->insn_num == state2->insn_num
7326 && memcmp (state1->dfa_state, state2->dfa_state,
7327 dfa_state_size) == 0);
7330 /* The function inserts the BUNDLE_STATE into the hash table. The
7331 function returns nonzero if the bundle has been inserted into the
7332 table. The table contains the best bundle state with given key. */
7335 insert_bundle_state (struct bundle_state *bundle_state)
7339 entry_ptr = htab_find_slot (bundle_state_table, bundle_state, 1);
7340 if (*entry_ptr == NULL)
7342 bundle_state->next = index_to_bundle_states [bundle_state->insn_num];
7343 index_to_bundle_states [bundle_state->insn_num] = bundle_state;
7344 *entry_ptr = (void *) bundle_state;
7347 else if (bundle_state->cost < ((struct bundle_state *) *entry_ptr)->cost
7348 || (bundle_state->cost == ((struct bundle_state *) *entry_ptr)->cost
7349 && (((struct bundle_state *)*entry_ptr)->accumulated_insns_num
7350 > bundle_state->accumulated_insns_num
7351 || (((struct bundle_state *)
7352 *entry_ptr)->accumulated_insns_num
7353 == bundle_state->accumulated_insns_num
7354 && ((struct bundle_state *)
7355 *entry_ptr)->branch_deviation
7356 > bundle_state->branch_deviation))))
7359 struct bundle_state temp;
7361 temp = *(struct bundle_state *) *entry_ptr;
7362 *(struct bundle_state *) *entry_ptr = *bundle_state;
7363 ((struct bundle_state *) *entry_ptr)->next = temp.next;
7364 *bundle_state = temp;
7369 /* Start work with the hash table. */
7372 initiate_bundle_state_table (void)
7374 bundle_state_table = htab_create (50, bundle_state_hash, bundle_state_eq_p,
7378 /* Finish work with the hash table. */
7381 finish_bundle_state_table (void)
7383 htab_delete (bundle_state_table);
7388 /* The following variable is a insn `nop' used to check bundle states
7389 with different number of inserted nops. */
7391 static rtx ia64_nop;
7393 /* The following function tries to issue NOPS_NUM nops for the current
7394 state without advancing processor cycle. If it failed, the
7395 function returns FALSE and frees the current state. */
7398 try_issue_nops (struct bundle_state *curr_state, int nops_num)
7402 for (i = 0; i < nops_num; i++)
7403 if (state_transition (curr_state->dfa_state, ia64_nop) >= 0)
7405 free_bundle_state (curr_state);
7411 /* The following function tries to issue INSN for the current
7412 state without advancing processor cycle. If it failed, the
7413 function returns FALSE and frees the current state. */
7416 try_issue_insn (struct bundle_state *curr_state, rtx insn)
7418 if (insn && state_transition (curr_state->dfa_state, insn) >= 0)
7420 free_bundle_state (curr_state);
7426 /* The following function tries to issue BEFORE_NOPS_NUM nops and INSN
7427 starting with ORIGINATOR without advancing processor cycle. If
7428 TRY_BUNDLE_END_P is TRUE, the function also/only (if
7429 ONLY_BUNDLE_END_P is TRUE) tries to issue nops to fill all bundle.
7430 If it was successful, the function creates new bundle state and
7431 insert into the hash table and into `index_to_bundle_states'. */
7434 issue_nops_and_insn (struct bundle_state *originator, int before_nops_num,
7435 rtx insn, int try_bundle_end_p, int only_bundle_end_p)
7437 struct bundle_state *curr_state;
7439 curr_state = get_free_bundle_state ();
7440 memcpy (curr_state->dfa_state, originator->dfa_state, dfa_state_size);
7441 curr_state->insn = insn;
7442 curr_state->insn_num = originator->insn_num + 1;
7443 curr_state->cost = originator->cost;
7444 curr_state->originator = originator;
7445 curr_state->before_nops_num = before_nops_num;
7446 curr_state->after_nops_num = 0;
7447 curr_state->accumulated_insns_num
7448 = originator->accumulated_insns_num + before_nops_num;
7449 curr_state->branch_deviation = originator->branch_deviation;
7451 if (INSN_CODE (insn) == CODE_FOR_insn_group_barrier)
7453 gcc_assert (GET_MODE (insn) != TImode);
7454 if (!try_issue_nops (curr_state, before_nops_num))
7456 if (!try_issue_insn (curr_state, insn))
7458 memcpy (temp_dfa_state, curr_state->dfa_state, dfa_state_size);
7459 if (state_transition (temp_dfa_state, dfa_pre_cycle_insn) >= 0
7460 && curr_state->accumulated_insns_num % 3 != 0)
7462 free_bundle_state (curr_state);
7466 else if (GET_MODE (insn) != TImode)
7468 if (!try_issue_nops (curr_state, before_nops_num))
7470 if (!try_issue_insn (curr_state, insn))
7472 curr_state->accumulated_insns_num++;
7473 gcc_assert (GET_CODE (PATTERN (insn)) != ASM_INPUT
7474 && asm_noperands (PATTERN (insn)) < 0);
7476 if (ia64_safe_type (insn) == TYPE_L)
7477 curr_state->accumulated_insns_num++;
7481 /* If this is an insn that must be first in a group, then don't allow
7482 nops to be emitted before it. Currently, alloc is the only such
7483 supported instruction. */
7484 /* ??? The bundling automatons should handle this for us, but they do
7485 not yet have support for the first_insn attribute. */
7486 if (before_nops_num > 0 && get_attr_first_insn (insn) == FIRST_INSN_YES)
7488 free_bundle_state (curr_state);
7492 state_transition (curr_state->dfa_state, dfa_pre_cycle_insn);
7493 state_transition (curr_state->dfa_state, NULL);
7495 if (!try_issue_nops (curr_state, before_nops_num))
7497 if (!try_issue_insn (curr_state, insn))
7499 curr_state->accumulated_insns_num++;
7500 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
7501 || asm_noperands (PATTERN (insn)) >= 0)
7503 /* Finish bundle containing asm insn. */
7504 curr_state->after_nops_num
7505 = 3 - curr_state->accumulated_insns_num % 3;
7506 curr_state->accumulated_insns_num
7507 += 3 - curr_state->accumulated_insns_num % 3;
7509 else if (ia64_safe_type (insn) == TYPE_L)
7510 curr_state->accumulated_insns_num++;
7512 if (ia64_safe_type (insn) == TYPE_B)
7513 curr_state->branch_deviation
7514 += 2 - (curr_state->accumulated_insns_num - 1) % 3;
7515 if (try_bundle_end_p && curr_state->accumulated_insns_num % 3 != 0)
7517 if (!only_bundle_end_p && insert_bundle_state (curr_state))
7520 struct bundle_state *curr_state1;
7521 struct bundle_state *allocated_states_chain;
7523 curr_state1 = get_free_bundle_state ();
7524 dfa_state = curr_state1->dfa_state;
7525 allocated_states_chain = curr_state1->allocated_states_chain;
7526 *curr_state1 = *curr_state;
7527 curr_state1->dfa_state = dfa_state;
7528 curr_state1->allocated_states_chain = allocated_states_chain;
7529 memcpy (curr_state1->dfa_state, curr_state->dfa_state,
7531 curr_state = curr_state1;
7533 if (!try_issue_nops (curr_state,
7534 3 - curr_state->accumulated_insns_num % 3))
7536 curr_state->after_nops_num
7537 = 3 - curr_state->accumulated_insns_num % 3;
7538 curr_state->accumulated_insns_num
7539 += 3 - curr_state->accumulated_insns_num % 3;
7541 if (!insert_bundle_state (curr_state))
7542 free_bundle_state (curr_state);
7546 /* The following function returns position in the two window bundle
7550 get_max_pos (state_t state)
7552 if (cpu_unit_reservation_p (state, pos_6))
7554 else if (cpu_unit_reservation_p (state, pos_5))
7556 else if (cpu_unit_reservation_p (state, pos_4))
7558 else if (cpu_unit_reservation_p (state, pos_3))
7560 else if (cpu_unit_reservation_p (state, pos_2))
7562 else if (cpu_unit_reservation_p (state, pos_1))
7568 /* The function returns code of a possible template for given position
7569 and state. The function should be called only with 2 values of
7570 position equal to 3 or 6. We avoid generating F NOPs by putting
7571 templates containing F insns at the end of the template search
7572 because undocumented anomaly in McKinley derived cores which can
7573 cause stalls if an F-unit insn (including a NOP) is issued within a
7574 six-cycle window after reading certain application registers (such
7575 as ar.bsp). Furthermore, power-considerations also argue against
7576 the use of F-unit instructions unless they're really needed. */
7579 get_template (state_t state, int pos)
7584 if (cpu_unit_reservation_p (state, _0mmi_))
7586 else if (cpu_unit_reservation_p (state, _0mii_))
7588 else if (cpu_unit_reservation_p (state, _0mmb_))
7590 else if (cpu_unit_reservation_p (state, _0mib_))
7592 else if (cpu_unit_reservation_p (state, _0mbb_))
7594 else if (cpu_unit_reservation_p (state, _0bbb_))
7596 else if (cpu_unit_reservation_p (state, _0mmf_))
7598 else if (cpu_unit_reservation_p (state, _0mfi_))
7600 else if (cpu_unit_reservation_p (state, _0mfb_))
7602 else if (cpu_unit_reservation_p (state, _0mlx_))
7607 if (cpu_unit_reservation_p (state, _1mmi_))
7609 else if (cpu_unit_reservation_p (state, _1mii_))
7611 else if (cpu_unit_reservation_p (state, _1mmb_))
7613 else if (cpu_unit_reservation_p (state, _1mib_))
7615 else if (cpu_unit_reservation_p (state, _1mbb_))
7617 else if (cpu_unit_reservation_p (state, _1bbb_))
7619 else if (_1mmf_ >= 0 && cpu_unit_reservation_p (state, _1mmf_))
7621 else if (cpu_unit_reservation_p (state, _1mfi_))
7623 else if (cpu_unit_reservation_p (state, _1mfb_))
7625 else if (cpu_unit_reservation_p (state, _1mlx_))
7634 /* The following function returns an insn important for insn bundling
7635 followed by INSN and before TAIL. */
7638 get_next_important_insn (rtx insn, rtx tail)
7640 for (; insn && insn != tail; insn = NEXT_INSN (insn))
7642 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
7643 && GET_CODE (PATTERN (insn)) != USE
7644 && GET_CODE (PATTERN (insn)) != CLOBBER)
7649 /* Add a bundle selector TEMPLATE0 before INSN. */
7652 ia64_add_bundle_selector_before (int template0, rtx insn)
7654 rtx b = gen_bundle_selector (GEN_INT (template0));
7656 ia64_emit_insn_before (b, insn);
7657 #if NR_BUNDLES == 10
7658 if ((template0 == 4 || template0 == 5)
7659 && (flag_unwind_tables || (flag_exceptions && !USING_SJLJ_EXCEPTIONS)))
7662 rtx note = NULL_RTX;
7664 /* In .mbb and .bbb bundles, check if CALL_INSN isn't in the
7665 first or second slot. If it is and has REG_EH_NOTE set, copy it
7666 to following nops, as br.call sets rp to the address of following
7667 bundle and therefore an EH region end must be on a bundle
7669 insn = PREV_INSN (insn);
7670 for (i = 0; i < 3; i++)
7673 insn = next_active_insn (insn);
7674 while (GET_CODE (insn) == INSN
7675 && get_attr_empty (insn) == EMPTY_YES);
7676 if (GET_CODE (insn) == CALL_INSN)
7677 note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
7682 gcc_assert ((code = recog_memoized (insn)) == CODE_FOR_nop
7683 || code == CODE_FOR_nop_b);
7684 if (find_reg_note (insn, REG_EH_REGION, NULL_RTX))
7688 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0),
7696 /* The following function does insn bundling. Bundling means
7697 inserting templates and nop insns to fit insn groups into permitted
7698 templates. Instruction scheduling uses NDFA (non-deterministic
7699 finite automata) encoding informations about the templates and the
7700 inserted nops. Nondeterminism of the automata permits follows
7701 all possible insn sequences very fast.
7703 Unfortunately it is not possible to get information about inserting
7704 nop insns and used templates from the automata states. The
7705 automata only says that we can issue an insn possibly inserting
7706 some nops before it and using some template. Therefore insn
7707 bundling in this function is implemented by using DFA
7708 (deterministic finite automata). We follow all possible insn
7709 sequences by inserting 0-2 nops (that is what the NDFA describe for
7710 insn scheduling) before/after each insn being bundled. We know the
7711 start of simulated processor cycle from insn scheduling (insn
7712 starting a new cycle has TImode).
7714 Simple implementation of insn bundling would create enormous
7715 number of possible insn sequences satisfying information about new
7716 cycle ticks taken from the insn scheduling. To make the algorithm
7717 practical we use dynamic programming. Each decision (about
7718 inserting nops and implicitly about previous decisions) is described
7719 by structure bundle_state (see above). If we generate the same
7720 bundle state (key is automaton state after issuing the insns and
7721 nops for it), we reuse already generated one. As consequence we
7722 reject some decisions which cannot improve the solution and
7723 reduce memory for the algorithm.
7725 When we reach the end of EBB (extended basic block), we choose the
7726 best sequence and then, moving back in EBB, insert templates for
7727 the best alternative. The templates are taken from querying
7728 automaton state for each insn in chosen bundle states.
7730 So the algorithm makes two (forward and backward) passes through
7731 EBB. There is an additional forward pass through EBB for Itanium1
7732 processor. This pass inserts more nops to make dependency between
7733 a producer insn and MMMUL/MMSHF at least 4 cycles long. */
7736 bundling (FILE *dump, int verbose, rtx prev_head_insn, rtx tail)
7738 struct bundle_state *curr_state, *next_state, *best_state;
7739 rtx insn, next_insn;
7741 int i, bundle_end_p, only_bundle_end_p, asm_p;
7742 int pos = 0, max_pos, template0, template1;
7745 enum attr_type type;
7748 /* Count insns in the EBB. */
7749 for (insn = NEXT_INSN (prev_head_insn);
7750 insn && insn != tail;
7751 insn = NEXT_INSN (insn))
7757 dfa_clean_insn_cache ();
7758 initiate_bundle_state_table ();
7759 index_to_bundle_states = xmalloc ((insn_num + 2)
7760 * sizeof (struct bundle_state *));
7761 /* First (forward) pass -- generation of bundle states. */
7762 curr_state = get_free_bundle_state ();
7763 curr_state->insn = NULL;
7764 curr_state->before_nops_num = 0;
7765 curr_state->after_nops_num = 0;
7766 curr_state->insn_num = 0;
7767 curr_state->cost = 0;
7768 curr_state->accumulated_insns_num = 0;
7769 curr_state->branch_deviation = 0;
7770 curr_state->next = NULL;
7771 curr_state->originator = NULL;
7772 state_reset (curr_state->dfa_state);
7773 index_to_bundle_states [0] = curr_state;
7775 /* Shift cycle mark if it is put on insn which could be ignored. */
7776 for (insn = NEXT_INSN (prev_head_insn);
7778 insn = NEXT_INSN (insn))
7780 && (ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IGNORE
7781 || GET_CODE (PATTERN (insn)) == USE
7782 || GET_CODE (PATTERN (insn)) == CLOBBER)
7783 && GET_MODE (insn) == TImode)
7785 PUT_MODE (insn, VOIDmode);
7786 for (next_insn = NEXT_INSN (insn);
7788 next_insn = NEXT_INSN (next_insn))
7789 if (INSN_P (next_insn)
7790 && ia64_safe_itanium_class (next_insn) != ITANIUM_CLASS_IGNORE
7791 && GET_CODE (PATTERN (next_insn)) != USE
7792 && GET_CODE (PATTERN (next_insn)) != CLOBBER)
7794 PUT_MODE (next_insn, TImode);
7798 /* Forward pass: generation of bundle states. */
7799 for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail);
7803 gcc_assert (INSN_P (insn)
7804 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
7805 && GET_CODE (PATTERN (insn)) != USE
7806 && GET_CODE (PATTERN (insn)) != CLOBBER);
7807 type = ia64_safe_type (insn);
7808 next_insn = get_next_important_insn (NEXT_INSN (insn), tail);
7810 index_to_bundle_states [insn_num] = NULL;
7811 for (curr_state = index_to_bundle_states [insn_num - 1];
7813 curr_state = next_state)
7815 pos = curr_state->accumulated_insns_num % 3;
7816 next_state = curr_state->next;
7817 /* We must fill up the current bundle in order to start a
7818 subsequent asm insn in a new bundle. Asm insn is always
7819 placed in a separate bundle. */
7821 = (next_insn != NULL_RTX
7822 && INSN_CODE (insn) == CODE_FOR_insn_group_barrier
7823 && ia64_safe_type (next_insn) == TYPE_UNKNOWN);
7824 /* We may fill up the current bundle if it is the cycle end
7825 without a group barrier. */
7827 = (only_bundle_end_p || next_insn == NULL_RTX
7828 || (GET_MODE (next_insn) == TImode
7829 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier));
7830 if (type == TYPE_F || type == TYPE_B || type == TYPE_L
7832 /* We need to insert 2 nops for cases like M_MII. To
7833 guarantee issuing all insns on the same cycle for
7834 Itanium 1, we need to issue 2 nops after the first M
7835 insn (MnnMII where n is a nop insn). */
7836 || ((type == TYPE_M || type == TYPE_A)
7837 && ia64_tune == PROCESSOR_ITANIUM
7838 && !bundle_end_p && pos == 1))
7839 issue_nops_and_insn (curr_state, 2, insn, bundle_end_p,
7841 issue_nops_and_insn (curr_state, 1, insn, bundle_end_p,
7843 issue_nops_and_insn (curr_state, 0, insn, bundle_end_p,
7846 gcc_assert (index_to_bundle_states [insn_num]);
7847 for (curr_state = index_to_bundle_states [insn_num];
7849 curr_state = curr_state->next)
7850 if (verbose >= 2 && dump)
7852 /* This structure is taken from generated code of the
7853 pipeline hazard recognizer (see file insn-attrtab.c).
7854 Please don't forget to change the structure if a new
7855 automaton is added to .md file. */
7858 unsigned short one_automaton_state;
7859 unsigned short oneb_automaton_state;
7860 unsigned short two_automaton_state;
7861 unsigned short twob_automaton_state;
7866 "// Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
7867 curr_state->unique_num,
7868 (curr_state->originator == NULL
7869 ? -1 : curr_state->originator->unique_num),
7871 curr_state->before_nops_num, curr_state->after_nops_num,
7872 curr_state->accumulated_insns_num, curr_state->branch_deviation,
7873 (ia64_tune == PROCESSOR_ITANIUM
7874 ? ((struct DFA_chip *) curr_state->dfa_state)->oneb_automaton_state
7875 : ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state),
7880 /* We should find a solution because the 2nd insn scheduling has
7882 gcc_assert (index_to_bundle_states [insn_num]);
7883 /* Find a state corresponding to the best insn sequence. */
7885 for (curr_state = index_to_bundle_states [insn_num];
7887 curr_state = curr_state->next)
7888 /* We are just looking at the states with fully filled up last
7889 bundle. The first we prefer insn sequences with minimal cost
7890 then with minimal inserted nops and finally with branch insns
7891 placed in the 3rd slots. */
7892 if (curr_state->accumulated_insns_num % 3 == 0
7893 && (best_state == NULL || best_state->cost > curr_state->cost
7894 || (best_state->cost == curr_state->cost
7895 && (curr_state->accumulated_insns_num
7896 < best_state->accumulated_insns_num
7897 || (curr_state->accumulated_insns_num
7898 == best_state->accumulated_insns_num
7899 && curr_state->branch_deviation
7900 < best_state->branch_deviation)))))
7901 best_state = curr_state;
7902 /* Second (backward) pass: adding nops and templates. */
7903 insn_num = best_state->before_nops_num;
7904 template0 = template1 = -1;
7905 for (curr_state = best_state;
7906 curr_state->originator != NULL;
7907 curr_state = curr_state->originator)
7909 insn = curr_state->insn;
7910 asm_p = (GET_CODE (PATTERN (insn)) == ASM_INPUT
7911 || asm_noperands (PATTERN (insn)) >= 0);
7913 if (verbose >= 2 && dump)
7917 unsigned short one_automaton_state;
7918 unsigned short oneb_automaton_state;
7919 unsigned short two_automaton_state;
7920 unsigned short twob_automaton_state;
7925 "// Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
7926 curr_state->unique_num,
7927 (curr_state->originator == NULL
7928 ? -1 : curr_state->originator->unique_num),
7930 curr_state->before_nops_num, curr_state->after_nops_num,
7931 curr_state->accumulated_insns_num, curr_state->branch_deviation,
7932 (ia64_tune == PROCESSOR_ITANIUM
7933 ? ((struct DFA_chip *) curr_state->dfa_state)->oneb_automaton_state
7934 : ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state),
7937 /* Find the position in the current bundle window. The window can
7938 contain at most two bundles. Two bundle window means that
7939 the processor will make two bundle rotation. */
7940 max_pos = get_max_pos (curr_state->dfa_state);
7942 /* The following (negative template number) means that the
7943 processor did one bundle rotation. */
7944 || (max_pos == 3 && template0 < 0))
7946 /* We are at the end of the window -- find template(s) for
7950 template0 = get_template (curr_state->dfa_state, 3);
7953 template1 = get_template (curr_state->dfa_state, 3);
7954 template0 = get_template (curr_state->dfa_state, 6);
7957 if (max_pos > 3 && template1 < 0)
7958 /* It may happen when we have the stop inside a bundle. */
7960 gcc_assert (pos <= 3);
7961 template1 = get_template (curr_state->dfa_state, 3);
7965 /* Emit nops after the current insn. */
7966 for (i = 0; i < curr_state->after_nops_num; i++)
7969 emit_insn_after (nop, insn);
7971 gcc_assert (pos >= 0);
7974 /* We are at the start of a bundle: emit the template
7975 (it should be defined). */
7976 gcc_assert (template0 >= 0);
7977 ia64_add_bundle_selector_before (template0, nop);
7978 /* If we have two bundle window, we make one bundle
7979 rotation. Otherwise template0 will be undefined
7980 (negative value). */
7981 template0 = template1;
7985 /* Move the position backward in the window. Group barrier has
7986 no slot. Asm insn takes all bundle. */
7987 if (INSN_CODE (insn) != CODE_FOR_insn_group_barrier
7988 && GET_CODE (PATTERN (insn)) != ASM_INPUT
7989 && asm_noperands (PATTERN (insn)) < 0)
7991 /* Long insn takes 2 slots. */
7992 if (ia64_safe_type (insn) == TYPE_L)
7994 gcc_assert (pos >= 0);
7996 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier
7997 && GET_CODE (PATTERN (insn)) != ASM_INPUT
7998 && asm_noperands (PATTERN (insn)) < 0)
8000 /* The current insn is at the bundle start: emit the
8002 gcc_assert (template0 >= 0);
8003 ia64_add_bundle_selector_before (template0, insn);
8004 b = PREV_INSN (insn);
8006 /* See comment above in analogous place for emitting nops
8008 template0 = template1;
8011 /* Emit nops after the current insn. */
8012 for (i = 0; i < curr_state->before_nops_num; i++)
8015 ia64_emit_insn_before (nop, insn);
8016 nop = PREV_INSN (insn);
8019 gcc_assert (pos >= 0);
8022 /* See comment above in analogous place for emitting nops
8024 gcc_assert (template0 >= 0);
8025 ia64_add_bundle_selector_before (template0, insn);
8026 b = PREV_INSN (insn);
8028 template0 = template1;
8033 if (ia64_tune == PROCESSOR_ITANIUM)
8034 /* Insert additional cycles for MM-insns (MMMUL and MMSHF).
8035 Itanium1 has a strange design, if the distance between an insn
8036 and dependent MM-insn is less 4 then we have a 6 additional
8037 cycles stall. So we make the distance equal to 4 cycles if it
8039 for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail);
8043 gcc_assert (INSN_P (insn)
8044 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
8045 && GET_CODE (PATTERN (insn)) != USE
8046 && GET_CODE (PATTERN (insn)) != CLOBBER);
8047 next_insn = get_next_important_insn (NEXT_INSN (insn), tail);
8048 if (INSN_UID (insn) < clocks_length && add_cycles [INSN_UID (insn)])
8049 /* We found a MM-insn which needs additional cycles. */
8055 /* Now we are searching for a template of the bundle in
8056 which the MM-insn is placed and the position of the
8057 insn in the bundle (0, 1, 2). Also we are searching
8058 for that there is a stop before the insn. */
8059 last = prev_active_insn (insn);
8060 pred_stop_p = recog_memoized (last) == CODE_FOR_insn_group_barrier;
8062 last = prev_active_insn (last);
8064 for (;; last = prev_active_insn (last))
8065 if (recog_memoized (last) == CODE_FOR_bundle_selector)
8067 template0 = XINT (XVECEXP (PATTERN (last), 0, 0), 0);
8069 /* The insn is in MLX bundle. Change the template
8070 onto MFI because we will add nops before the
8071 insn. It simplifies subsequent code a lot. */
8073 = gen_bundle_selector (const2_rtx); /* -> MFI */
8076 else if (recog_memoized (last) != CODE_FOR_insn_group_barrier
8077 && (ia64_safe_itanium_class (last)
8078 != ITANIUM_CLASS_IGNORE))
8080 /* Some check of correctness: the stop is not at the
8081 bundle start, there are no more 3 insns in the bundle,
8082 and the MM-insn is not at the start of bundle with
8084 gcc_assert ((!pred_stop_p || n)
8086 && (template0 != 9 || !n));
8087 /* Put nops after the insn in the bundle. */
8088 for (j = 3 - n; j > 0; j --)
8089 ia64_emit_insn_before (gen_nop (), insn);
8090 /* It takes into account that we will add more N nops
8091 before the insn lately -- please see code below. */
8092 add_cycles [INSN_UID (insn)]--;
8093 if (!pred_stop_p || add_cycles [INSN_UID (insn)])
8094 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
8097 add_cycles [INSN_UID (insn)]--;
8098 for (i = add_cycles [INSN_UID (insn)]; i > 0; i--)
8100 /* Insert "MII;" template. */
8101 ia64_emit_insn_before (gen_bundle_selector (const0_rtx),
8103 ia64_emit_insn_before (gen_nop (), insn);
8104 ia64_emit_insn_before (gen_nop (), insn);
8107 /* To decrease code size, we use "MI;I;"
8109 ia64_emit_insn_before
8110 (gen_insn_group_barrier (GEN_INT (3)), insn);
8113 ia64_emit_insn_before (gen_nop (), insn);
8114 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
8117 /* Put the MM-insn in the same slot of a bundle with the
8118 same template as the original one. */
8119 ia64_add_bundle_selector_before (template0, insn);
8120 /* To put the insn in the same slot, add necessary number
8122 for (j = n; j > 0; j --)
8123 ia64_emit_insn_before (gen_nop (), insn);
8124 /* Put the stop if the original bundle had it. */
8126 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
8130 free (index_to_bundle_states);
8131 finish_bundle_state_table ();
8133 dfa_clean_insn_cache ();
8136 /* The following function is called at the end of scheduling BB or
8137 EBB. After reload, it inserts stop bits and does insn bundling. */
8140 ia64_sched_finish (FILE *dump, int sched_verbose)
8143 fprintf (dump, "// Finishing schedule.\n");
8144 if (!reload_completed)
8146 if (reload_completed)
8148 final_emit_insn_group_barriers (dump);
8149 bundling (dump, sched_verbose, current_sched_info->prev_head,
8150 current_sched_info->next_tail);
8151 if (sched_verbose && dump)
8152 fprintf (dump, "// finishing %d-%d\n",
8153 INSN_UID (NEXT_INSN (current_sched_info->prev_head)),
8154 INSN_UID (PREV_INSN (current_sched_info->next_tail)));
8160 /* The following function inserts stop bits in scheduled BB or EBB. */
8163 final_emit_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED)
8166 int need_barrier_p = 0;
8167 rtx prev_insn = NULL_RTX;
8169 init_insn_group_barriers ();
8171 for (insn = NEXT_INSN (current_sched_info->prev_head);
8172 insn != current_sched_info->next_tail;
8173 insn = NEXT_INSN (insn))
8175 if (GET_CODE (insn) == BARRIER)
8177 rtx last = prev_active_insn (insn);
8181 if (GET_CODE (last) == JUMP_INSN
8182 && GET_CODE (PATTERN (last)) == ADDR_DIFF_VEC)
8183 last = prev_active_insn (last);
8184 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
8185 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
8187 init_insn_group_barriers ();
8189 prev_insn = NULL_RTX;
8191 else if (INSN_P (insn))
8193 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
8195 init_insn_group_barriers ();
8197 prev_insn = NULL_RTX;
8199 else if (need_barrier_p || group_barrier_needed (insn))
8201 if (TARGET_EARLY_STOP_BITS)
8206 last != current_sched_info->prev_head;
8207 last = PREV_INSN (last))
8208 if (INSN_P (last) && GET_MODE (last) == TImode
8209 && stops_p [INSN_UID (last)])
8211 if (last == current_sched_info->prev_head)
8213 last = prev_active_insn (last);
8215 && recog_memoized (last) != CODE_FOR_insn_group_barrier)
8216 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)),
8218 init_insn_group_barriers ();
8219 for (last = NEXT_INSN (last);
8221 last = NEXT_INSN (last))
8223 group_barrier_needed (last);
8227 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
8229 init_insn_group_barriers ();
8231 group_barrier_needed (insn);
8232 prev_insn = NULL_RTX;
8234 else if (recog_memoized (insn) >= 0)
8236 need_barrier_p = (GET_CODE (insn) == CALL_INSN
8237 || GET_CODE (PATTERN (insn)) == ASM_INPUT
8238 || asm_noperands (PATTERN (insn)) >= 0);
8245 /* If the following function returns TRUE, we will use the DFA
8249 ia64_first_cycle_multipass_dfa_lookahead (void)
8251 return (reload_completed ? 6 : 4);
8254 /* The following function initiates variable `dfa_pre_cycle_insn'. */
8257 ia64_init_dfa_pre_cycle_insn (void)
8259 if (temp_dfa_state == NULL)
8261 dfa_state_size = state_size ();
8262 temp_dfa_state = xmalloc (dfa_state_size);
8263 prev_cycle_state = xmalloc (dfa_state_size);
8265 dfa_pre_cycle_insn = make_insn_raw (gen_pre_cycle ());
8266 PREV_INSN (dfa_pre_cycle_insn) = NEXT_INSN (dfa_pre_cycle_insn) = NULL_RTX;
8267 recog_memoized (dfa_pre_cycle_insn);
8268 dfa_stop_insn = make_insn_raw (gen_insn_group_barrier (GEN_INT (3)));
8269 PREV_INSN (dfa_stop_insn) = NEXT_INSN (dfa_stop_insn) = NULL_RTX;
8270 recog_memoized (dfa_stop_insn);
8273 /* The following function returns the pseudo insn DFA_PRE_CYCLE_INSN
8274 used by the DFA insn scheduler. */
8277 ia64_dfa_pre_cycle_insn (void)
8279 return dfa_pre_cycle_insn;
8282 /* The following function returns TRUE if PRODUCER (of type ilog or
8283 ld) produces address for CONSUMER (of type st or stf). */
8286 ia64_st_address_bypass_p (rtx producer, rtx consumer)
8290 gcc_assert (producer && consumer);
8291 dest = ia64_single_set (producer);
8293 reg = SET_DEST (dest);
8295 if (GET_CODE (reg) == SUBREG)
8296 reg = SUBREG_REG (reg);
8297 gcc_assert (GET_CODE (reg) == REG);
8299 dest = ia64_single_set (consumer);
8301 mem = SET_DEST (dest);
8302 gcc_assert (mem && GET_CODE (mem) == MEM);
8303 return reg_mentioned_p (reg, mem);
8306 /* The following function returns TRUE if PRODUCER (of type ilog or
8307 ld) produces address for CONSUMER (of type ld or fld). */
8310 ia64_ld_address_bypass_p (rtx producer, rtx consumer)
8312 rtx dest, src, reg, mem;
8314 gcc_assert (producer && consumer);
8315 dest = ia64_single_set (producer);
8317 reg = SET_DEST (dest);
8319 if (GET_CODE (reg) == SUBREG)
8320 reg = SUBREG_REG (reg);
8321 gcc_assert (GET_CODE (reg) == REG);
8323 src = ia64_single_set (consumer);
8325 mem = SET_SRC (src);
8328 if (GET_CODE (mem) == UNSPEC && XVECLEN (mem, 0) > 0)
8329 mem = XVECEXP (mem, 0, 0);
8330 else if (GET_CODE (mem) == IF_THEN_ELSE)
8331 /* ??? Is this bypass necessary for ld.c? */
8333 gcc_assert (XINT (XEXP (XEXP (mem, 0), 0), 1) == UNSPEC_LDCCLR);
8334 mem = XEXP (mem, 1);
8337 while (GET_CODE (mem) == SUBREG || GET_CODE (mem) == ZERO_EXTEND)
8338 mem = XEXP (mem, 0);
8340 if (GET_CODE (mem) == UNSPEC)
8342 int c = XINT (mem, 1);
8344 gcc_assert (c == UNSPEC_LDA || c == UNSPEC_LDS || c == UNSPEC_LDSA);
8345 mem = XVECEXP (mem, 0, 0);
8348 /* Note that LO_SUM is used for GOT loads. */
8349 gcc_assert (GET_CODE (mem) == LO_SUM || GET_CODE (mem) == MEM);
8351 return reg_mentioned_p (reg, mem);
8354 /* The following function returns TRUE if INSN produces address for a
8355 load/store insn. We will place such insns into M slot because it
8356 decreases its latency time. */
8359 ia64_produce_address_p (rtx insn)
8365 /* Emit pseudo-ops for the assembler to describe predicate relations.
8366 At present this assumes that we only consider predicate pairs to
8367 be mutex, and that the assembler can deduce proper values from
8368 straight-line code. */
8371 emit_predicate_relation_info (void)
8375 FOR_EACH_BB_REVERSE (bb)
8378 rtx head = BB_HEAD (bb);
8380 /* We only need such notes at code labels. */
8381 if (GET_CODE (head) != CODE_LABEL)
8383 if (GET_CODE (NEXT_INSN (head)) == NOTE
8384 && NOTE_LINE_NUMBER (NEXT_INSN (head)) == NOTE_INSN_BASIC_BLOCK)
8385 head = NEXT_INSN (head);
8387 /* Skip p0, which may be thought to be live due to (reg:DI p0)
8388 grabbing the entire block of predicate registers. */
8389 for (r = PR_REG (2); r < PR_REG (64); r += 2)
8390 if (REGNO_REG_SET_P (bb->il.rtl->global_live_at_start, r))
8392 rtx p = gen_rtx_REG (BImode, r);
8393 rtx n = emit_insn_after (gen_pred_rel_mutex (p), head);
8394 if (head == BB_END (bb))
8400 /* Look for conditional calls that do not return, and protect predicate
8401 relations around them. Otherwise the assembler will assume the call
8402 returns, and complain about uses of call-clobbered predicates after
8404 FOR_EACH_BB_REVERSE (bb)
8406 rtx insn = BB_HEAD (bb);
8410 if (GET_CODE (insn) == CALL_INSN
8411 && GET_CODE (PATTERN (insn)) == COND_EXEC
8412 && find_reg_note (insn, REG_NORETURN, NULL_RTX))
8414 rtx b = emit_insn_before (gen_safe_across_calls_all (), insn);
8415 rtx a = emit_insn_after (gen_safe_across_calls_normal (), insn);
8416 if (BB_HEAD (bb) == insn)
8418 if (BB_END (bb) == insn)
8422 if (insn == BB_END (bb))
8424 insn = NEXT_INSN (insn);
8429 /* Perform machine dependent operations on the rtl chain INSNS. */
8434 /* We are freeing block_for_insn in the toplev to keep compatibility
8435 with old MDEP_REORGS that are not CFG based. Recompute it now. */
8436 compute_bb_for_insn ();
8438 /* If optimizing, we'll have split before scheduling. */
8440 split_all_insns (0);
8442 /* ??? update_life_info_in_dirty_blocks fails to terminate during
8443 non-optimizing bootstrap. */
8444 update_life_info (NULL, UPDATE_LIFE_GLOBAL_RM_NOTES, PROP_DEATH_NOTES);
8446 if (optimize && ia64_flag_schedule_insns2)
8448 timevar_push (TV_SCHED2);
8449 ia64_final_schedule = 1;
8451 initiate_bundle_states ();
8452 ia64_nop = make_insn_raw (gen_nop ());
8453 PREV_INSN (ia64_nop) = NEXT_INSN (ia64_nop) = NULL_RTX;
8454 recog_memoized (ia64_nop);
8455 clocks_length = get_max_uid () + 1;
8456 stops_p = xcalloc (1, clocks_length);
8457 if (ia64_tune == PROCESSOR_ITANIUM)
8459 clocks = xcalloc (clocks_length, sizeof (int));
8460 add_cycles = xcalloc (clocks_length, sizeof (int));
8462 if (ia64_tune == PROCESSOR_ITANIUM2)
8464 pos_1 = get_cpu_unit_code ("2_1");
8465 pos_2 = get_cpu_unit_code ("2_2");
8466 pos_3 = get_cpu_unit_code ("2_3");
8467 pos_4 = get_cpu_unit_code ("2_4");
8468 pos_5 = get_cpu_unit_code ("2_5");
8469 pos_6 = get_cpu_unit_code ("2_6");
8470 _0mii_ = get_cpu_unit_code ("2b_0mii.");
8471 _0mmi_ = get_cpu_unit_code ("2b_0mmi.");
8472 _0mfi_ = get_cpu_unit_code ("2b_0mfi.");
8473 _0mmf_ = get_cpu_unit_code ("2b_0mmf.");
8474 _0bbb_ = get_cpu_unit_code ("2b_0bbb.");
8475 _0mbb_ = get_cpu_unit_code ("2b_0mbb.");
8476 _0mib_ = get_cpu_unit_code ("2b_0mib.");
8477 _0mmb_ = get_cpu_unit_code ("2b_0mmb.");
8478 _0mfb_ = get_cpu_unit_code ("2b_0mfb.");
8479 _0mlx_ = get_cpu_unit_code ("2b_0mlx.");
8480 _1mii_ = get_cpu_unit_code ("2b_1mii.");
8481 _1mmi_ = get_cpu_unit_code ("2b_1mmi.");
8482 _1mfi_ = get_cpu_unit_code ("2b_1mfi.");
8483 _1mmf_ = get_cpu_unit_code ("2b_1mmf.");
8484 _1bbb_ = get_cpu_unit_code ("2b_1bbb.");
8485 _1mbb_ = get_cpu_unit_code ("2b_1mbb.");
8486 _1mib_ = get_cpu_unit_code ("2b_1mib.");
8487 _1mmb_ = get_cpu_unit_code ("2b_1mmb.");
8488 _1mfb_ = get_cpu_unit_code ("2b_1mfb.");
8489 _1mlx_ = get_cpu_unit_code ("2b_1mlx.");
8493 pos_1 = get_cpu_unit_code ("1_1");
8494 pos_2 = get_cpu_unit_code ("1_2");
8495 pos_3 = get_cpu_unit_code ("1_3");
8496 pos_4 = get_cpu_unit_code ("1_4");
8497 pos_5 = get_cpu_unit_code ("1_5");
8498 pos_6 = get_cpu_unit_code ("1_6");
8499 _0mii_ = get_cpu_unit_code ("1b_0mii.");
8500 _0mmi_ = get_cpu_unit_code ("1b_0mmi.");
8501 _0mfi_ = get_cpu_unit_code ("1b_0mfi.");
8502 _0mmf_ = get_cpu_unit_code ("1b_0mmf.");
8503 _0bbb_ = get_cpu_unit_code ("1b_0bbb.");
8504 _0mbb_ = get_cpu_unit_code ("1b_0mbb.");
8505 _0mib_ = get_cpu_unit_code ("1b_0mib.");
8506 _0mmb_ = get_cpu_unit_code ("1b_0mmb.");
8507 _0mfb_ = get_cpu_unit_code ("1b_0mfb.");
8508 _0mlx_ = get_cpu_unit_code ("1b_0mlx.");
8509 _1mii_ = get_cpu_unit_code ("1b_1mii.");
8510 _1mmi_ = get_cpu_unit_code ("1b_1mmi.");
8511 _1mfi_ = get_cpu_unit_code ("1b_1mfi.");
8512 _1mmf_ = get_cpu_unit_code ("1b_1mmf.");
8513 _1bbb_ = get_cpu_unit_code ("1b_1bbb.");
8514 _1mbb_ = get_cpu_unit_code ("1b_1mbb.");
8515 _1mib_ = get_cpu_unit_code ("1b_1mib.");
8516 _1mmb_ = get_cpu_unit_code ("1b_1mmb.");
8517 _1mfb_ = get_cpu_unit_code ("1b_1mfb.");
8518 _1mlx_ = get_cpu_unit_code ("1b_1mlx.");
8521 finish_bundle_states ();
8522 if (ia64_tune == PROCESSOR_ITANIUM)
8529 emit_insn_group_barriers (dump_file);
8531 ia64_final_schedule = 0;
8532 timevar_pop (TV_SCHED2);
8535 emit_all_insn_group_barriers (dump_file);
8537 /* A call must not be the last instruction in a function, so that the
8538 return address is still within the function, so that unwinding works
8539 properly. Note that IA-64 differs from dwarf2 on this point. */
8540 if (flag_unwind_tables || (flag_exceptions && !USING_SJLJ_EXCEPTIONS))
8545 insn = get_last_insn ();
8546 if (! INSN_P (insn))
8547 insn = prev_active_insn (insn);
8548 /* Skip over insns that expand to nothing. */
8549 while (GET_CODE (insn) == INSN && get_attr_empty (insn) == EMPTY_YES)
8551 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
8552 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
8554 insn = prev_active_insn (insn);
8556 if (GET_CODE (insn) == CALL_INSN)
8559 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
8560 emit_insn (gen_break_f ());
8561 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
8565 emit_predicate_relation_info ();
8567 if (ia64_flag_var_tracking)
8569 timevar_push (TV_VAR_TRACKING);
8570 variable_tracking_main ();
8571 timevar_pop (TV_VAR_TRACKING);
8575 /* Return true if REGNO is used by the epilogue. */
8578 ia64_epilogue_uses (int regno)
8583 /* With a call to a function in another module, we will write a new
8584 value to "gp". After returning from such a call, we need to make
8585 sure the function restores the original gp-value, even if the
8586 function itself does not use the gp anymore. */
8587 return !(TARGET_AUTO_PIC || TARGET_NO_PIC);
8589 case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3):
8590 case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7):
8591 /* For functions defined with the syscall_linkage attribute, all
8592 input registers are marked as live at all function exits. This
8593 prevents the register allocator from using the input registers,
8594 which in turn makes it possible to restart a system call after
8595 an interrupt without having to save/restore the input registers.
8596 This also prevents kernel data from leaking to application code. */
8597 return lookup_attribute ("syscall_linkage",
8598 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))) != NULL;
8601 /* Conditional return patterns can't represent the use of `b0' as
8602 the return address, so we force the value live this way. */
8606 /* Likewise for ar.pfs, which is used by br.ret. */
8614 /* Return true if REGNO is used by the frame unwinder. */
8617 ia64_eh_uses (int regno)
8619 if (! reload_completed)
8622 if (current_frame_info.reg_save_b0
8623 && regno == current_frame_info.reg_save_b0)
8625 if (current_frame_info.reg_save_pr
8626 && regno == current_frame_info.reg_save_pr)
8628 if (current_frame_info.reg_save_ar_pfs
8629 && regno == current_frame_info.reg_save_ar_pfs)
8631 if (current_frame_info.reg_save_ar_unat
8632 && regno == current_frame_info.reg_save_ar_unat)
8634 if (current_frame_info.reg_save_ar_lc
8635 && regno == current_frame_info.reg_save_ar_lc)
8641 /* Return true if this goes in small data/bss. */
8643 /* ??? We could also support own long data here. Generating movl/add/ld8
8644 instead of addl,ld8/ld8. This makes the code bigger, but should make the
8645 code faster because there is one less load. This also includes incomplete
8646 types which can't go in sdata/sbss. */
8649 ia64_in_small_data_p (tree exp)
8651 if (TARGET_NO_SDATA)
8654 /* We want to merge strings, so we never consider them small data. */
8655 if (TREE_CODE (exp) == STRING_CST)
8658 /* Functions are never small data. */
8659 if (TREE_CODE (exp) == FUNCTION_DECL)
8662 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
8664 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
8666 if (strcmp (section, ".sdata") == 0
8667 || strncmp (section, ".sdata.", 7) == 0
8668 || strncmp (section, ".gnu.linkonce.s.", 16) == 0
8669 || strcmp (section, ".sbss") == 0
8670 || strncmp (section, ".sbss.", 6) == 0
8671 || strncmp (section, ".gnu.linkonce.sb.", 17) == 0)
8676 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
8678 /* If this is an incomplete type with size 0, then we can't put it
8679 in sdata because it might be too big when completed. */
8680 if (size > 0 && size <= ia64_section_threshold)
8687 /* Output assembly directives for prologue regions. */
8689 /* The current basic block number. */
8691 static bool last_block;
8693 /* True if we need a copy_state command at the start of the next block. */
8695 static bool need_copy_state;
8697 #ifndef MAX_ARTIFICIAL_LABEL_BYTES
8698 # define MAX_ARTIFICIAL_LABEL_BYTES 30
8701 /* Emit a debugging label after a call-frame-related insn. We'd
8702 rather output the label right away, but we'd have to output it
8703 after, not before, the instruction, and the instruction has not
8704 been output yet. So we emit the label after the insn, delete it to
8705 avoid introducing basic blocks, and mark it as preserved, such that
8706 it is still output, given that it is referenced in debug info. */
8709 ia64_emit_deleted_label_after_insn (rtx insn)
8711 char label[MAX_ARTIFICIAL_LABEL_BYTES];
8712 rtx lb = gen_label_rtx ();
8713 rtx label_insn = emit_label_after (lb, insn);
8715 LABEL_PRESERVE_P (lb) = 1;
8717 delete_insn (label_insn);
8719 ASM_GENERATE_INTERNAL_LABEL (label, "L", CODE_LABEL_NUMBER (label_insn));
8721 return xstrdup (label);
8724 /* Define the CFA after INSN with the steady-state definition. */
8727 ia64_dwarf2out_def_steady_cfa (rtx insn)
8729 rtx fp = frame_pointer_needed
8730 ? hard_frame_pointer_rtx
8731 : stack_pointer_rtx;
8734 (ia64_emit_deleted_label_after_insn (insn),
8736 ia64_initial_elimination_offset
8737 (REGNO (arg_pointer_rtx), REGNO (fp))
8738 + ARG_POINTER_CFA_OFFSET (current_function_decl));
8741 /* The generic dwarf2 frame debug info generator does not define a
8742 separate region for the very end of the epilogue, so refrain from
8743 doing so in the IA64-specific code as well. */
8745 #define IA64_CHANGE_CFA_IN_EPILOGUE 0
8747 /* The function emits unwind directives for the start of an epilogue. */
8750 process_epilogue (FILE *asm_out_file, rtx insn, bool unwind, bool frame)
8752 /* If this isn't the last block of the function, then we need to label the
8753 current state, and copy it back in at the start of the next block. */
8758 fprintf (asm_out_file, "\t.label_state %d\n",
8759 ++cfun->machine->state_num);
8760 need_copy_state = true;
8764 fprintf (asm_out_file, "\t.restore sp\n");
8765 if (IA64_CHANGE_CFA_IN_EPILOGUE && frame)
8766 dwarf2out_def_cfa (ia64_emit_deleted_label_after_insn (insn),
8767 STACK_POINTER_REGNUM, INCOMING_FRAME_SP_OFFSET);
8770 /* This function processes a SET pattern looking for specific patterns
8771 which result in emitting an assembly directive required for unwinding. */
8774 process_set (FILE *asm_out_file, rtx pat, rtx insn, bool unwind, bool frame)
8776 rtx src = SET_SRC (pat);
8777 rtx dest = SET_DEST (pat);
8778 int src_regno, dest_regno;
8780 /* Look for the ALLOC insn. */
8781 if (GET_CODE (src) == UNSPEC_VOLATILE
8782 && XINT (src, 1) == UNSPECV_ALLOC
8783 && GET_CODE (dest) == REG)
8785 dest_regno = REGNO (dest);
8787 /* If this is the final destination for ar.pfs, then this must
8788 be the alloc in the prologue. */
8789 if (dest_regno == current_frame_info.reg_save_ar_pfs)
8792 fprintf (asm_out_file, "\t.save ar.pfs, r%d\n",
8793 ia64_dbx_register_number (dest_regno));
8797 /* This must be an alloc before a sibcall. We must drop the
8798 old frame info. The easiest way to drop the old frame
8799 info is to ensure we had a ".restore sp" directive
8800 followed by a new prologue. If the procedure doesn't
8801 have a memory-stack frame, we'll issue a dummy ".restore
8803 if (current_frame_info.total_size == 0 && !frame_pointer_needed)
8804 /* if haven't done process_epilogue() yet, do it now */
8805 process_epilogue (asm_out_file, insn, unwind, frame);
8807 fprintf (asm_out_file, "\t.prologue\n");
8812 /* Look for SP = .... */
8813 if (GET_CODE (dest) == REG && REGNO (dest) == STACK_POINTER_REGNUM)
8815 if (GET_CODE (src) == PLUS)
8817 rtx op0 = XEXP (src, 0);
8818 rtx op1 = XEXP (src, 1);
8820 gcc_assert (op0 == dest && GET_CODE (op1) == CONST_INT);
8822 if (INTVAL (op1) < 0)
8824 gcc_assert (!frame_pointer_needed);
8826 fprintf (asm_out_file, "\t.fframe "HOST_WIDE_INT_PRINT_DEC"\n",
8829 ia64_dwarf2out_def_steady_cfa (insn);
8832 process_epilogue (asm_out_file, insn, unwind, frame);
8836 gcc_assert (GET_CODE (src) == REG
8837 && REGNO (src) == HARD_FRAME_POINTER_REGNUM);
8838 process_epilogue (asm_out_file, insn, unwind, frame);
8844 /* Register move we need to look at. */
8845 if (GET_CODE (dest) == REG && GET_CODE (src) == REG)
8847 src_regno = REGNO (src);
8848 dest_regno = REGNO (dest);
8853 /* Saving return address pointer. */
8854 gcc_assert (dest_regno == current_frame_info.reg_save_b0);
8856 fprintf (asm_out_file, "\t.save rp, r%d\n",
8857 ia64_dbx_register_number (dest_regno));
8861 gcc_assert (dest_regno == current_frame_info.reg_save_pr);
8863 fprintf (asm_out_file, "\t.save pr, r%d\n",
8864 ia64_dbx_register_number (dest_regno));
8867 case AR_UNAT_REGNUM:
8868 gcc_assert (dest_regno == current_frame_info.reg_save_ar_unat);
8870 fprintf (asm_out_file, "\t.save ar.unat, r%d\n",
8871 ia64_dbx_register_number (dest_regno));
8875 gcc_assert (dest_regno == current_frame_info.reg_save_ar_lc);
8877 fprintf (asm_out_file, "\t.save ar.lc, r%d\n",
8878 ia64_dbx_register_number (dest_regno));
8881 case STACK_POINTER_REGNUM:
8882 gcc_assert (dest_regno == HARD_FRAME_POINTER_REGNUM
8883 && frame_pointer_needed);
8885 fprintf (asm_out_file, "\t.vframe r%d\n",
8886 ia64_dbx_register_number (dest_regno));
8888 ia64_dwarf2out_def_steady_cfa (insn);
8892 /* Everything else should indicate being stored to memory. */
8897 /* Memory store we need to look at. */
8898 if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
8904 if (GET_CODE (XEXP (dest, 0)) == REG)
8906 base = XEXP (dest, 0);
8911 gcc_assert (GET_CODE (XEXP (dest, 0)) == PLUS
8912 && GET_CODE (XEXP (XEXP (dest, 0), 1)) == CONST_INT);
8913 base = XEXP (XEXP (dest, 0), 0);
8914 off = INTVAL (XEXP (XEXP (dest, 0), 1));
8917 if (base == hard_frame_pointer_rtx)
8919 saveop = ".savepsp";
8924 gcc_assert (base == stack_pointer_rtx);
8928 src_regno = REGNO (src);
8932 gcc_assert (!current_frame_info.reg_save_b0);
8934 fprintf (asm_out_file, "\t%s rp, %ld\n", saveop, off);
8938 gcc_assert (!current_frame_info.reg_save_pr);
8940 fprintf (asm_out_file, "\t%s pr, %ld\n", saveop, off);
8944 gcc_assert (!current_frame_info.reg_save_ar_lc);
8946 fprintf (asm_out_file, "\t%s ar.lc, %ld\n", saveop, off);
8950 gcc_assert (!current_frame_info.reg_save_ar_pfs);
8952 fprintf (asm_out_file, "\t%s ar.pfs, %ld\n", saveop, off);
8955 case AR_UNAT_REGNUM:
8956 gcc_assert (!current_frame_info.reg_save_ar_unat);
8958 fprintf (asm_out_file, "\t%s ar.unat, %ld\n", saveop, off);
8966 fprintf (asm_out_file, "\t.save.g 0x%x\n",
8967 1 << (src_regno - GR_REG (4)));
8976 fprintf (asm_out_file, "\t.save.b 0x%x\n",
8977 1 << (src_regno - BR_REG (1)));
8985 fprintf (asm_out_file, "\t.save.f 0x%x\n",
8986 1 << (src_regno - FR_REG (2)));
8989 case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19):
8990 case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23):
8991 case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27):
8992 case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31):
8994 fprintf (asm_out_file, "\t.save.gf 0x0, 0x%x\n",
8995 1 << (src_regno - FR_REG (12)));
9007 /* This function looks at a single insn and emits any directives
9008 required to unwind this insn. */
9010 process_for_unwind_directive (FILE *asm_out_file, rtx insn)
9012 bool unwind = (flag_unwind_tables
9013 || (flag_exceptions && !USING_SJLJ_EXCEPTIONS));
9014 bool frame = dwarf2out_do_frame ();
9016 if (unwind || frame)
9020 if (GET_CODE (insn) == NOTE
9021 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_BASIC_BLOCK)
9023 last_block = NOTE_BASIC_BLOCK (insn)->next_bb == EXIT_BLOCK_PTR;
9025 /* Restore unwind state from immediately before the epilogue. */
9026 if (need_copy_state)
9030 fprintf (asm_out_file, "\t.body\n");
9031 fprintf (asm_out_file, "\t.copy_state %d\n",
9032 cfun->machine->state_num);
9034 if (IA64_CHANGE_CFA_IN_EPILOGUE && frame)
9035 ia64_dwarf2out_def_steady_cfa (insn);
9036 need_copy_state = false;
9040 if (GET_CODE (insn) == NOTE || ! RTX_FRAME_RELATED_P (insn))
9043 pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX);
9045 pat = XEXP (pat, 0);
9047 pat = PATTERN (insn);
9049 switch (GET_CODE (pat))
9052 process_set (asm_out_file, pat, insn, unwind, frame);
9058 int limit = XVECLEN (pat, 0);
9059 for (par_index = 0; par_index < limit; par_index++)
9061 rtx x = XVECEXP (pat, 0, par_index);
9062 if (GET_CODE (x) == SET)
9063 process_set (asm_out_file, x, insn, unwind, frame);
9078 IA64_BUILTIN_FLUSHRS
9082 ia64_init_builtins (void)
9087 /* The __fpreg type. */
9088 fpreg_type = make_node (REAL_TYPE);
9089 TYPE_PRECISION (fpreg_type) = 82;
9090 layout_type (fpreg_type);
9091 (*lang_hooks.types.register_builtin_type) (fpreg_type, "__fpreg");
9093 /* The __float80 type. */
9094 float80_type = make_node (REAL_TYPE);
9095 TYPE_PRECISION (float80_type) = 80;
9096 layout_type (float80_type);
9097 (*lang_hooks.types.register_builtin_type) (float80_type, "__float80");
9099 /* The __float128 type. */
9102 tree float128_type = make_node (REAL_TYPE);
9103 TYPE_PRECISION (float128_type) = 128;
9104 layout_type (float128_type);
9105 (*lang_hooks.types.register_builtin_type) (float128_type, "__float128");
9108 /* Under HPUX, this is a synonym for "long double". */
9109 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
9112 #define def_builtin(name, type, code) \
9113 add_builtin_function ((name), (type), (code), BUILT_IN_MD, \
9116 def_builtin ("__builtin_ia64_bsp",
9117 build_function_type (ptr_type_node, void_list_node),
9120 def_builtin ("__builtin_ia64_flushrs",
9121 build_function_type (void_type_node, void_list_node),
9122 IA64_BUILTIN_FLUSHRS);
9128 ia64_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
9129 enum machine_mode mode ATTRIBUTE_UNUSED,
9130 int ignore ATTRIBUTE_UNUSED)
9132 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
9133 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
9137 case IA64_BUILTIN_BSP:
9138 if (! target || ! register_operand (target, DImode))
9139 target = gen_reg_rtx (DImode);
9140 emit_insn (gen_bsp_value (target));
9141 #ifdef POINTERS_EXTEND_UNSIGNED
9142 target = convert_memory_address (ptr_mode, target);
9146 case IA64_BUILTIN_FLUSHRS:
9147 emit_insn (gen_flushrs ());
9157 /* For the HP-UX IA64 aggregate parameters are passed stored in the
9158 most significant bits of the stack slot. */
9161 ia64_hpux_function_arg_padding (enum machine_mode mode, tree type)
9163 /* Exception to normal case for structures/unions/etc. */
9165 if (type && AGGREGATE_TYPE_P (type)
9166 && int_size_in_bytes (type) < UNITS_PER_WORD)
9169 /* Fall back to the default. */
9170 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
9173 /* Emit text to declare externally defined variables and functions, because
9174 the Intel assembler does not support undefined externals. */
9177 ia64_asm_output_external (FILE *file, tree decl, const char *name)
9179 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
9180 set in order to avoid putting out names that are never really
9182 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
9184 /* maybe_assemble_visibility will return 1 if the assembler
9185 visibility directive is outputed. */
9186 int need_visibility = ((*targetm.binds_local_p) (decl)
9187 && maybe_assemble_visibility (decl));
9189 /* GNU as does not need anything here, but the HP linker does
9190 need something for external functions. */
9191 if ((TARGET_HPUX_LD || !TARGET_GNU_AS)
9192 && TREE_CODE (decl) == FUNCTION_DECL)
9194 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
9195 (*targetm.asm_out.globalize_label) (file, name);
9197 else if (need_visibility && !TARGET_GNU_AS)
9198 (*targetm.asm_out.globalize_label) (file, name);
9202 /* Set SImode div/mod functions, init_integral_libfuncs only initializes
9203 modes of word_mode and larger. Rename the TFmode libfuncs using the
9204 HPUX conventions. __divtf3 is used for XFmode. We need to keep it for
9205 backward compatibility. */
9208 ia64_init_libfuncs (void)
9210 set_optab_libfunc (sdiv_optab, SImode, "__divsi3");
9211 set_optab_libfunc (udiv_optab, SImode, "__udivsi3");
9212 set_optab_libfunc (smod_optab, SImode, "__modsi3");
9213 set_optab_libfunc (umod_optab, SImode, "__umodsi3");
9215 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
9216 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
9217 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
9218 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
9219 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
9221 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
9222 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
9223 set_conv_libfunc (sext_optab, TFmode, XFmode, "_U_Qfcnvff_f80_to_quad");
9224 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
9225 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
9226 set_conv_libfunc (trunc_optab, XFmode, TFmode, "_U_Qfcnvff_quad_to_f80");
9228 set_conv_libfunc (sfix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_sgl");
9229 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
9230 set_conv_libfunc (sfix_optab, TImode, TFmode, "_U_Qfcnvfxt_quad_to_quad");
9231 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxut_quad_to_sgl");
9232 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxut_quad_to_dbl");
9234 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
9235 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
9236 set_conv_libfunc (sfloat_optab, TFmode, TImode, "_U_Qfcnvxf_quad_to_quad");
9237 /* HP-UX 11.23 libc does not have a function for unsigned
9238 SImode-to-TFmode conversion. */
9239 set_conv_libfunc (ufloat_optab, TFmode, DImode, "_U_Qfcnvxuf_dbl_to_quad");
9242 /* Rename all the TFmode libfuncs using the HPUX conventions. */
9245 ia64_hpux_init_libfuncs (void)
9247 ia64_init_libfuncs ();
9249 /* The HP SI millicode division and mod functions expect DI arguments.
9250 By turning them off completely we avoid using both libgcc and the
9251 non-standard millicode routines and use the HP DI millicode routines
9254 set_optab_libfunc (sdiv_optab, SImode, 0);
9255 set_optab_libfunc (udiv_optab, SImode, 0);
9256 set_optab_libfunc (smod_optab, SImode, 0);
9257 set_optab_libfunc (umod_optab, SImode, 0);
9259 set_optab_libfunc (sdiv_optab, DImode, "__milli_divI");
9260 set_optab_libfunc (udiv_optab, DImode, "__milli_divU");
9261 set_optab_libfunc (smod_optab, DImode, "__milli_remI");
9262 set_optab_libfunc (umod_optab, DImode, "__milli_remU");
9264 /* HP-UX libc has TF min/max/abs routines in it. */
9265 set_optab_libfunc (smin_optab, TFmode, "_U_Qfmin");
9266 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
9267 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
9269 /* ia64_expand_compare uses this. */
9270 cmptf_libfunc = init_one_libfunc ("_U_Qfcmp");
9272 /* These should never be used. */
9273 set_optab_libfunc (eq_optab, TFmode, 0);
9274 set_optab_libfunc (ne_optab, TFmode, 0);
9275 set_optab_libfunc (gt_optab, TFmode, 0);
9276 set_optab_libfunc (ge_optab, TFmode, 0);
9277 set_optab_libfunc (lt_optab, TFmode, 0);
9278 set_optab_libfunc (le_optab, TFmode, 0);
9281 /* Rename the division and modulus functions in VMS. */
9284 ia64_vms_init_libfuncs (void)
9286 set_optab_libfunc (sdiv_optab, SImode, "OTS$DIV_I");
9287 set_optab_libfunc (sdiv_optab, DImode, "OTS$DIV_L");
9288 set_optab_libfunc (udiv_optab, SImode, "OTS$DIV_UI");
9289 set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL");
9290 set_optab_libfunc (smod_optab, SImode, "OTS$REM_I");
9291 set_optab_libfunc (smod_optab, DImode, "OTS$REM_L");
9292 set_optab_libfunc (umod_optab, SImode, "OTS$REM_UI");
9293 set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL");
9296 /* Rename the TFmode libfuncs available from soft-fp in glibc using
9297 the HPUX conventions. */
9300 ia64_sysv4_init_libfuncs (void)
9302 ia64_init_libfuncs ();
9304 /* These functions are not part of the HPUX TFmode interface. We
9305 use them instead of _U_Qfcmp, which doesn't work the way we
9307 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
9308 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
9309 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
9310 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
9311 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
9312 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
9314 /* We leave out _U_Qfmin, _U_Qfmax and _U_Qfabs since soft-fp in
9315 glibc doesn't have them. */
9318 /* Return the section to use for X. The only special thing we do here
9319 is to honor small data. */
9322 ia64_select_rtx_section (enum machine_mode mode, rtx x,
9323 unsigned HOST_WIDE_INT align)
9325 if (GET_MODE_SIZE (mode) > 0
9326 && GET_MODE_SIZE (mode) <= ia64_section_threshold
9327 && !TARGET_NO_SDATA)
9328 return sdata_section;
9330 return default_elf_select_rtx_section (mode, x, align);
9333 /* It is illegal to have relocations in shared segments on AIX and HPUX.
9334 Pretend flag_pic is always set. */
9337 ia64_rwreloc_select_section (tree exp, int reloc, unsigned HOST_WIDE_INT align)
9339 return default_elf_select_section_1 (exp, reloc, align, true);
9343 ia64_rwreloc_unique_section (tree decl, int reloc)
9345 default_unique_section_1 (decl, reloc, true);
9349 ia64_rwreloc_select_rtx_section (enum machine_mode mode, rtx x,
9350 unsigned HOST_WIDE_INT align)
9353 int save_pic = flag_pic;
9355 sect = ia64_select_rtx_section (mode, x, align);
9356 flag_pic = save_pic;
9360 #ifndef TARGET_RWRELOC
9361 #define TARGET_RWRELOC flag_pic
9365 ia64_section_type_flags (tree decl, const char *name, int reloc)
9367 unsigned int flags = 0;
9369 if (strcmp (name, ".sdata") == 0
9370 || strncmp (name, ".sdata.", 7) == 0
9371 || strncmp (name, ".gnu.linkonce.s.", 16) == 0
9372 || strncmp (name, ".sdata2.", 8) == 0
9373 || strncmp (name, ".gnu.linkonce.s2.", 17) == 0
9374 || strcmp (name, ".sbss") == 0
9375 || strncmp (name, ".sbss.", 6) == 0
9376 || strncmp (name, ".gnu.linkonce.sb.", 17) == 0)
9377 flags = SECTION_SMALL;
9379 flags |= default_section_type_flags_1 (decl, name, reloc, TARGET_RWRELOC);
9383 /* Returns true if FNTYPE (a FUNCTION_TYPE or a METHOD_TYPE) returns a
9384 structure type and that the address of that type should be passed
9385 in out0, rather than in r8. */
9388 ia64_struct_retval_addr_is_first_parm_p (tree fntype)
9390 tree ret_type = TREE_TYPE (fntype);
9392 /* The Itanium C++ ABI requires that out0, rather than r8, be used
9393 as the structure return address parameter, if the return value
9394 type has a non-trivial copy constructor or destructor. It is not
9395 clear if this same convention should be used for other
9396 programming languages. Until G++ 3.4, we incorrectly used r8 for
9397 these return values. */
9398 return (abi_version_at_least (2)
9400 && TYPE_MODE (ret_type) == BLKmode
9401 && TREE_ADDRESSABLE (ret_type)
9402 && strcmp (lang_hooks.name, "GNU C++") == 0);
9405 /* Output the assembler code for a thunk function. THUNK_DECL is the
9406 declaration for the thunk function itself, FUNCTION is the decl for
9407 the target function. DELTA is an immediate constant offset to be
9408 added to THIS. If VCALL_OFFSET is nonzero, the word at
9409 *(*this + vcall_offset) should be added to THIS. */
9412 ia64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
9413 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
9416 rtx this, insn, funexp;
9417 unsigned int this_parmno;
9418 unsigned int this_regno;
9420 reload_completed = 1;
9421 epilogue_completed = 1;
9423 reset_block_changes ();
9425 /* Set things up as ia64_expand_prologue might. */
9426 last_scratch_gr_reg = 15;
9428 memset (¤t_frame_info, 0, sizeof (current_frame_info));
9429 current_frame_info.spill_cfa_off = -16;
9430 current_frame_info.n_input_regs = 1;
9431 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
9433 /* Mark the end of the (empty) prologue. */
9434 emit_note (NOTE_INSN_PROLOGUE_END);
9436 /* Figure out whether "this" will be the first parameter (the
9437 typical case) or the second parameter (as happens when the
9438 virtual function returns certain class objects). */
9440 = (ia64_struct_retval_addr_is_first_parm_p (TREE_TYPE (thunk))
9442 this_regno = IN_REG (this_parmno);
9443 if (!TARGET_REG_NAMES)
9444 reg_names[this_regno] = ia64_reg_numbers[this_parmno];
9446 this = gen_rtx_REG (Pmode, this_regno);
9449 rtx tmp = gen_rtx_REG (ptr_mode, this_regno);
9450 REG_POINTER (tmp) = 1;
9451 if (delta && CONST_OK_FOR_I (delta))
9453 emit_insn (gen_ptr_extend_plus_imm (this, tmp, GEN_INT (delta)));
9457 emit_insn (gen_ptr_extend (this, tmp));
9460 /* Apply the constant offset, if required. */
9463 rtx delta_rtx = GEN_INT (delta);
9465 if (!CONST_OK_FOR_I (delta))
9467 rtx tmp = gen_rtx_REG (Pmode, 2);
9468 emit_move_insn (tmp, delta_rtx);
9471 emit_insn (gen_adddi3 (this, this, delta_rtx));
9474 /* Apply the offset from the vtable, if required. */
9477 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
9478 rtx tmp = gen_rtx_REG (Pmode, 2);
9482 rtx t = gen_rtx_REG (ptr_mode, 2);
9483 REG_POINTER (t) = 1;
9484 emit_move_insn (t, gen_rtx_MEM (ptr_mode, this));
9485 if (CONST_OK_FOR_I (vcall_offset))
9487 emit_insn (gen_ptr_extend_plus_imm (tmp, t,
9492 emit_insn (gen_ptr_extend (tmp, t));
9495 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
9499 if (!CONST_OK_FOR_J (vcall_offset))
9501 rtx tmp2 = gen_rtx_REG (Pmode, next_scratch_gr_reg ());
9502 emit_move_insn (tmp2, vcall_offset_rtx);
9503 vcall_offset_rtx = tmp2;
9505 emit_insn (gen_adddi3 (tmp, tmp, vcall_offset_rtx));
9509 emit_move_insn (gen_rtx_REG (ptr_mode, 2),
9510 gen_rtx_MEM (ptr_mode, tmp));
9512 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
9514 emit_insn (gen_adddi3 (this, this, tmp));
9517 /* Generate a tail call to the target function. */
9518 if (! TREE_USED (function))
9520 assemble_external (function);
9521 TREE_USED (function) = 1;
9523 funexp = XEXP (DECL_RTL (function), 0);
9524 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
9525 ia64_expand_call (NULL_RTX, funexp, NULL_RTX, 1);
9526 insn = get_last_insn ();
9527 SIBLING_CALL_P (insn) = 1;
9529 /* Code generation for calls relies on splitting. */
9530 reload_completed = 1;
9531 epilogue_completed = 1;
9532 try_split (PATTERN (insn), insn, 0);
9536 /* Run just enough of rest_of_compilation to get the insns emitted.
9537 There's not really enough bulk here to make other passes such as
9538 instruction scheduling worth while. Note that use_thunk calls
9539 assemble_start_function and assemble_end_function. */
9541 insn_locators_initialize ();
9542 emit_all_insn_group_barriers (NULL);
9543 insn = get_insns ();
9544 shorten_branches (insn);
9545 final_start_function (insn, file, 1);
9546 final (insn, file, 1);
9547 final_end_function ();
9549 reload_completed = 0;
9550 epilogue_completed = 0;
9554 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9557 ia64_struct_value_rtx (tree fntype,
9558 int incoming ATTRIBUTE_UNUSED)
9560 if (fntype && ia64_struct_retval_addr_is_first_parm_p (fntype))
9562 return gen_rtx_REG (Pmode, GR_REG (8));
9566 ia64_scalar_mode_supported_p (enum machine_mode mode)
9592 ia64_vector_mode_supported_p (enum machine_mode mode)
9609 /* Implement the FUNCTION_PROFILER macro. */
9612 ia64_output_function_profiler (FILE *file, int labelno)
9616 /* If the function needs a static chain and the static chain
9617 register is r15, we use an indirect call so as to bypass
9618 the PLT stub in case the executable is dynamically linked,
9619 because the stub clobbers r15 as per 5.3.6 of the psABI.
9620 We don't need to do that in non canonical PIC mode. */
9622 if (cfun->static_chain_decl && !TARGET_NO_PIC && !TARGET_AUTO_PIC)
9624 gcc_assert (STATIC_CHAIN_REGNUM == 15);
9625 indirect_call = true;
9628 indirect_call = false;
9631 fputs ("\t.prologue 4, r40\n", file);
9633 fputs ("\t.prologue\n\t.save ar.pfs, r40\n", file);
9634 fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", file);
9636 if (NO_PROFILE_COUNTERS)
9637 fputs ("\tmov out3 = r0\n", file);
9641 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
9643 if (TARGET_AUTO_PIC)
9644 fputs ("\tmovl out3 = @gprel(", file);
9646 fputs ("\taddl out3 = @ltoff(", file);
9647 assemble_name (file, buf);
9648 if (TARGET_AUTO_PIC)
9649 fputs (")\n", file);
9651 fputs ("), r1\n", file);
9655 fputs ("\taddl r14 = @ltoff(@fptr(_mcount)), r1\n", file);
9656 fputs ("\t;;\n", file);
9658 fputs ("\t.save rp, r42\n", file);
9659 fputs ("\tmov out2 = b0\n", file);
9661 fputs ("\tld8 r14 = [r14]\n\t;;\n", file);
9662 fputs ("\t.body\n", file);
9663 fputs ("\tmov out1 = r1\n", file);
9666 fputs ("\tld8 r16 = [r14], 8\n\t;;\n", file);
9667 fputs ("\tmov b6 = r16\n", file);
9668 fputs ("\tld8 r1 = [r14]\n", file);
9669 fputs ("\tbr.call.sptk.many b0 = b6\n\t;;\n", file);
9672 fputs ("\tbr.call.sptk.many b0 = _mcount\n\t;;\n", file);
9675 static GTY(()) rtx mcount_func_rtx;
9677 gen_mcount_func_rtx (void)
9679 if (!mcount_func_rtx)
9680 mcount_func_rtx = init_one_libfunc ("_mcount");
9681 return mcount_func_rtx;
9685 ia64_profile_hook (int labelno)
9689 if (NO_PROFILE_COUNTERS)
9694 const char *label_name;
9695 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
9696 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
9697 label = gen_rtx_SYMBOL_REF (Pmode, label_name);
9698 SYMBOL_REF_FLAGS (label) = SYMBOL_FLAG_LOCAL;
9700 ip = gen_reg_rtx (Pmode);
9701 emit_insn (gen_ip_value (ip));
9702 emit_library_call (gen_mcount_func_rtx (), LCT_NORMAL,
9704 gen_rtx_REG (Pmode, BR_REG (0)), Pmode,
9709 /* Return the mangling of TYPE if it is an extended fundamental type. */
9712 ia64_mangle_fundamental_type (tree type)
9714 /* On HP-UX, "long double" is mangled as "e" so __float128 is
9716 if (!TARGET_HPUX && TYPE_MODE (type) == TFmode)
9718 /* On HP-UX, "e" is not available as a mangling of __float80 so use
9719 an extended mangling. Elsewhere, "e" is available since long
9720 double is 80 bits. */
9721 if (TYPE_MODE (type) == XFmode)
9722 return TARGET_HPUX ? "u9__float80" : "e";
9723 if (TYPE_MODE (type) == RFmode)
9728 /* Return the diagnostic message string if conversion from FROMTYPE to
9729 TOTYPE is not allowed, NULL otherwise. */
9731 ia64_invalid_conversion (tree fromtype, tree totype)
9733 /* Reject nontrivial conversion to or from __fpreg. */
9734 if (TYPE_MODE (fromtype) == RFmode
9735 && TYPE_MODE (totype) != RFmode
9736 && TYPE_MODE (totype) != VOIDmode)
9737 return N_("invalid conversion from %<__fpreg%>");
9738 if (TYPE_MODE (totype) == RFmode
9739 && TYPE_MODE (fromtype) != RFmode)
9740 return N_("invalid conversion to %<__fpreg%>");
9744 /* Return the diagnostic message string if the unary operation OP is
9745 not permitted on TYPE, NULL otherwise. */
9747 ia64_invalid_unary_op (int op, tree type)
9749 /* Reject operations on __fpreg other than unary + or &. */
9750 if (TYPE_MODE (type) == RFmode
9751 && op != CONVERT_EXPR
9753 return N_("invalid operation on %<__fpreg%>");
9757 /* Return the diagnostic message string if the binary operation OP is
9758 not permitted on TYPE1 and TYPE2, NULL otherwise. */
9760 ia64_invalid_binary_op (int op ATTRIBUTE_UNUSED, tree type1, tree type2)
9762 /* Reject operations on __fpreg. */
9763 if (TYPE_MODE (type1) == RFmode || TYPE_MODE (type2) == RFmode)
9764 return N_("invalid operation on %<__fpreg%>");
9768 /* Implement overriding of the optimization options. */
9770 ia64_optimization_options (int level ATTRIBUTE_UNUSED,
9771 int size ATTRIBUTE_UNUSED)
9773 /* Let the scheduler form additional regions. */
9774 set_param_value ("max-sched-extend-regions-iters", 2);
9776 /* Set the default values for cache-related parameters. */
9777 set_param_value ("simultaneous-prefetches", 6);
9778 set_param_value ("l1-cache-line-size", 32);
9782 #include "gt-ia64.h"