1 /* Definitions of target machine for GNU compiler.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 Free Software Foundation, Inc.
4 Contributed by James E. Wilson <wilson@cygnus.com> and
5 David Mosberger <davidm@hpl.hp.com>.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
46 #include "sched-int.h"
49 #include "target-def.h"
52 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "tree-gimple.h"
56 /* This is used for communication between ASM_OUTPUT_LABEL and
57 ASM_OUTPUT_LABELREF. */
58 int ia64_asm_output_label = 0;
60 /* Define the information needed to generate branch and scc insns. This is
61 stored from the compare operation. */
62 struct rtx_def * ia64_compare_op0;
63 struct rtx_def * ia64_compare_op1;
65 /* Register names for ia64_expand_prologue. */
66 static const char * const ia64_reg_numbers[96] =
67 { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
68 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
69 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
70 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
71 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
72 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
73 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
74 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
75 "r96", "r97", "r98", "r99", "r100","r101","r102","r103",
76 "r104","r105","r106","r107","r108","r109","r110","r111",
77 "r112","r113","r114","r115","r116","r117","r118","r119",
78 "r120","r121","r122","r123","r124","r125","r126","r127"};
80 /* ??? These strings could be shared with REGISTER_NAMES. */
81 static const char * const ia64_input_reg_names[8] =
82 { "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7" };
84 /* ??? These strings could be shared with REGISTER_NAMES. */
85 static const char * const ia64_local_reg_names[80] =
86 { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7",
87 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15",
88 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23",
89 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31",
90 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39",
91 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47",
92 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55",
93 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63",
94 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71",
95 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" };
97 /* ??? These strings could be shared with REGISTER_NAMES. */
98 static const char * const ia64_output_reg_names[8] =
99 { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" };
101 /* Which cpu are we scheduling for. */
102 enum processor_type ia64_tune = PROCESSOR_ITANIUM2;
104 /* Determines whether we run our final scheduling pass or not. We always
105 avoid the normal second scheduling pass. */
106 static int ia64_flag_schedule_insns2;
108 /* Determines whether we run variable tracking in machine dependent
110 static int ia64_flag_var_tracking;
112 /* Variables which are this size or smaller are put in the sdata/sbss
115 unsigned int ia64_section_threshold;
117 /* The following variable is used by the DFA insn scheduler. The value is
118 TRUE if we do insn bundling instead of insn scheduling. */
121 /* Structure to be filled in by ia64_compute_frame_size with register
122 save masks and offsets for the current function. */
124 struct ia64_frame_info
126 HOST_WIDE_INT total_size; /* size of the stack frame, not including
127 the caller's scratch area. */
128 HOST_WIDE_INT spill_cfa_off; /* top of the reg spill area from the cfa. */
129 HOST_WIDE_INT spill_size; /* size of the gr/br/fr spill area. */
130 HOST_WIDE_INT extra_spill_size; /* size of spill area for others. */
131 HARD_REG_SET mask; /* mask of saved registers. */
132 unsigned int gr_used_mask; /* mask of registers in use as gr spill
133 registers or long-term scratches. */
134 int n_spilled; /* number of spilled registers. */
135 int reg_fp; /* register for fp. */
136 int reg_save_b0; /* save register for b0. */
137 int reg_save_pr; /* save register for prs. */
138 int reg_save_ar_pfs; /* save register for ar.pfs. */
139 int reg_save_ar_unat; /* save register for ar.unat. */
140 int reg_save_ar_lc; /* save register for ar.lc. */
141 int reg_save_gp; /* save register for gp. */
142 int n_input_regs; /* number of input registers used. */
143 int n_local_regs; /* number of local registers used. */
144 int n_output_regs; /* number of output registers used. */
145 int n_rotate_regs; /* number of rotating registers used. */
147 char need_regstk; /* true if a .regstk directive needed. */
148 char initialized; /* true if the data is finalized. */
151 /* Current frame information calculated by ia64_compute_frame_size. */
152 static struct ia64_frame_info current_frame_info;
154 static int ia64_first_cycle_multipass_dfa_lookahead (void);
155 static void ia64_dependencies_evaluation_hook (rtx, rtx);
156 static void ia64_init_dfa_pre_cycle_insn (void);
157 static rtx ia64_dfa_pre_cycle_insn (void);
158 static int ia64_first_cycle_multipass_dfa_lookahead_guard (rtx);
159 static int ia64_dfa_new_cycle (FILE *, int, rtx, int, int, int *);
160 static rtx gen_tls_get_addr (void);
161 static rtx gen_thread_pointer (void);
162 static int find_gr_spill (int);
163 static int next_scratch_gr_reg (void);
164 static void mark_reg_gr_used_mask (rtx, void *);
165 static void ia64_compute_frame_size (HOST_WIDE_INT);
166 static void setup_spill_pointers (int, rtx, HOST_WIDE_INT);
167 static void finish_spill_pointers (void);
168 static rtx spill_restore_mem (rtx, HOST_WIDE_INT);
169 static void do_spill (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT, rtx);
170 static void do_restore (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT);
171 static rtx gen_movdi_x (rtx, rtx, rtx);
172 static rtx gen_fr_spill_x (rtx, rtx, rtx);
173 static rtx gen_fr_restore_x (rtx, rtx, rtx);
175 static enum machine_mode hfa_element_mode (tree, bool);
176 static void ia64_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
178 static bool ia64_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
180 static int ia64_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
182 static bool ia64_function_ok_for_sibcall (tree, tree);
183 static bool ia64_return_in_memory (tree, tree);
184 static bool ia64_rtx_costs (rtx, int, int, int *);
185 static void fix_range (const char *);
186 static bool ia64_handle_option (size_t, const char *, int);
187 static struct machine_function * ia64_init_machine_status (void);
188 static void emit_insn_group_barriers (FILE *);
189 static void emit_all_insn_group_barriers (FILE *);
190 static void final_emit_insn_group_barriers (FILE *);
191 static void emit_predicate_relation_info (void);
192 static void ia64_reorg (void);
193 static bool ia64_in_small_data_p (tree);
194 static void process_epilogue (void);
195 static int process_set (FILE *, rtx);
197 static bool ia64_assemble_integer (rtx, unsigned int, int);
198 static void ia64_output_function_prologue (FILE *, HOST_WIDE_INT);
199 static void ia64_output_function_epilogue (FILE *, HOST_WIDE_INT);
200 static void ia64_output_function_end_prologue (FILE *);
202 static int ia64_issue_rate (void);
203 static int ia64_adjust_cost (rtx, rtx, rtx, int);
204 static void ia64_sched_init (FILE *, int, int);
205 static void ia64_sched_finish (FILE *, int);
206 static int ia64_dfa_sched_reorder (FILE *, int, rtx *, int *, int, int);
207 static int ia64_sched_reorder (FILE *, int, rtx *, int *, int);
208 static int ia64_sched_reorder2 (FILE *, int, rtx *, int *, int);
209 static int ia64_variable_issue (FILE *, int, rtx, int);
211 static struct bundle_state *get_free_bundle_state (void);
212 static void free_bundle_state (struct bundle_state *);
213 static void initiate_bundle_states (void);
214 static void finish_bundle_states (void);
215 static unsigned bundle_state_hash (const void *);
216 static int bundle_state_eq_p (const void *, const void *);
217 static int insert_bundle_state (struct bundle_state *);
218 static void initiate_bundle_state_table (void);
219 static void finish_bundle_state_table (void);
220 static int try_issue_nops (struct bundle_state *, int);
221 static int try_issue_insn (struct bundle_state *, rtx);
222 static void issue_nops_and_insn (struct bundle_state *, int, rtx, int, int);
223 static int get_max_pos (state_t);
224 static int get_template (state_t, int);
226 static rtx get_next_important_insn (rtx, rtx);
227 static void bundling (FILE *, int, rtx, rtx);
229 static void ia64_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
230 HOST_WIDE_INT, tree);
231 static void ia64_file_start (void);
233 static void ia64_select_rtx_section (enum machine_mode, rtx,
234 unsigned HOST_WIDE_INT);
235 static void ia64_output_dwarf_dtprel (FILE *, int, rtx)
237 static void ia64_rwreloc_select_section (tree, int, unsigned HOST_WIDE_INT)
239 static void ia64_rwreloc_unique_section (tree, int)
241 static void ia64_rwreloc_select_rtx_section (enum machine_mode, rtx,
242 unsigned HOST_WIDE_INT)
244 static unsigned int ia64_section_type_flags (tree, const char *, int);
245 static void ia64_hpux_add_extern_decl (tree decl)
247 static void ia64_hpux_file_end (void)
249 static void ia64_init_libfuncs (void)
251 static void ia64_hpux_init_libfuncs (void)
253 static void ia64_sysv4_init_libfuncs (void)
255 static void ia64_vms_init_libfuncs (void)
258 static tree ia64_handle_model_attribute (tree *, tree, tree, int, bool *);
259 static void ia64_encode_section_info (tree, rtx, int);
260 static rtx ia64_struct_value_rtx (tree, int);
261 static tree ia64_gimplify_va_arg (tree, tree, tree *, tree *);
262 static bool ia64_scalar_mode_supported_p (enum machine_mode mode);
263 static bool ia64_vector_mode_supported_p (enum machine_mode mode);
264 static bool ia64_cannot_force_const_mem (rtx);
266 /* Table of valid machine attributes. */
267 static const struct attribute_spec ia64_attribute_table[] =
269 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
270 { "syscall_linkage", 0, 0, false, true, true, NULL },
271 { "model", 1, 1, true, false, false, ia64_handle_model_attribute },
272 { NULL, 0, 0, false, false, false, NULL }
275 /* Initialize the GCC target structure. */
276 #undef TARGET_ATTRIBUTE_TABLE
277 #define TARGET_ATTRIBUTE_TABLE ia64_attribute_table
279 #undef TARGET_INIT_BUILTINS
280 #define TARGET_INIT_BUILTINS ia64_init_builtins
282 #undef TARGET_EXPAND_BUILTIN
283 #define TARGET_EXPAND_BUILTIN ia64_expand_builtin
285 #undef TARGET_ASM_BYTE_OP
286 #define TARGET_ASM_BYTE_OP "\tdata1\t"
287 #undef TARGET_ASM_ALIGNED_HI_OP
288 #define TARGET_ASM_ALIGNED_HI_OP "\tdata2\t"
289 #undef TARGET_ASM_ALIGNED_SI_OP
290 #define TARGET_ASM_ALIGNED_SI_OP "\tdata4\t"
291 #undef TARGET_ASM_ALIGNED_DI_OP
292 #define TARGET_ASM_ALIGNED_DI_OP "\tdata8\t"
293 #undef TARGET_ASM_UNALIGNED_HI_OP
294 #define TARGET_ASM_UNALIGNED_HI_OP "\tdata2.ua\t"
295 #undef TARGET_ASM_UNALIGNED_SI_OP
296 #define TARGET_ASM_UNALIGNED_SI_OP "\tdata4.ua\t"
297 #undef TARGET_ASM_UNALIGNED_DI_OP
298 #define TARGET_ASM_UNALIGNED_DI_OP "\tdata8.ua\t"
299 #undef TARGET_ASM_INTEGER
300 #define TARGET_ASM_INTEGER ia64_assemble_integer
302 #undef TARGET_ASM_FUNCTION_PROLOGUE
303 #define TARGET_ASM_FUNCTION_PROLOGUE ia64_output_function_prologue
304 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
305 #define TARGET_ASM_FUNCTION_END_PROLOGUE ia64_output_function_end_prologue
306 #undef TARGET_ASM_FUNCTION_EPILOGUE
307 #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue
309 #undef TARGET_IN_SMALL_DATA_P
310 #define TARGET_IN_SMALL_DATA_P ia64_in_small_data_p
312 #undef TARGET_SCHED_ADJUST_COST
313 #define TARGET_SCHED_ADJUST_COST ia64_adjust_cost
314 #undef TARGET_SCHED_ISSUE_RATE
315 #define TARGET_SCHED_ISSUE_RATE ia64_issue_rate
316 #undef TARGET_SCHED_VARIABLE_ISSUE
317 #define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue
318 #undef TARGET_SCHED_INIT
319 #define TARGET_SCHED_INIT ia64_sched_init
320 #undef TARGET_SCHED_FINISH
321 #define TARGET_SCHED_FINISH ia64_sched_finish
322 #undef TARGET_SCHED_REORDER
323 #define TARGET_SCHED_REORDER ia64_sched_reorder
324 #undef TARGET_SCHED_REORDER2
325 #define TARGET_SCHED_REORDER2 ia64_sched_reorder2
327 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
328 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ia64_dependencies_evaluation_hook
330 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
331 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ia64_first_cycle_multipass_dfa_lookahead
333 #undef TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN
334 #define TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN ia64_init_dfa_pre_cycle_insn
335 #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN
336 #define TARGET_SCHED_DFA_PRE_CYCLE_INSN ia64_dfa_pre_cycle_insn
338 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
339 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD\
340 ia64_first_cycle_multipass_dfa_lookahead_guard
342 #undef TARGET_SCHED_DFA_NEW_CYCLE
343 #define TARGET_SCHED_DFA_NEW_CYCLE ia64_dfa_new_cycle
345 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
346 #define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall
347 #undef TARGET_PASS_BY_REFERENCE
348 #define TARGET_PASS_BY_REFERENCE ia64_pass_by_reference
349 #undef TARGET_ARG_PARTIAL_BYTES
350 #define TARGET_ARG_PARTIAL_BYTES ia64_arg_partial_bytes
352 #undef TARGET_ASM_OUTPUT_MI_THUNK
353 #define TARGET_ASM_OUTPUT_MI_THUNK ia64_output_mi_thunk
354 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
355 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
357 #undef TARGET_ASM_FILE_START
358 #define TARGET_ASM_FILE_START ia64_file_start
360 #undef TARGET_RTX_COSTS
361 #define TARGET_RTX_COSTS ia64_rtx_costs
362 #undef TARGET_ADDRESS_COST
363 #define TARGET_ADDRESS_COST hook_int_rtx_0
365 #undef TARGET_MACHINE_DEPENDENT_REORG
366 #define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg
368 #undef TARGET_ENCODE_SECTION_INFO
369 #define TARGET_ENCODE_SECTION_INFO ia64_encode_section_info
371 #undef TARGET_SECTION_TYPE_FLAGS
372 #define TARGET_SECTION_TYPE_FLAGS ia64_section_type_flags
375 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
376 #define TARGET_ASM_OUTPUT_DWARF_DTPREL ia64_output_dwarf_dtprel
379 /* ??? ABI doesn't allow us to define this. */
381 #undef TARGET_PROMOTE_FUNCTION_ARGS
382 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
385 /* ??? ABI doesn't allow us to define this. */
387 #undef TARGET_PROMOTE_FUNCTION_RETURN
388 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
391 /* ??? Investigate. */
393 #undef TARGET_PROMOTE_PROTOTYPES
394 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
397 #undef TARGET_STRUCT_VALUE_RTX
398 #define TARGET_STRUCT_VALUE_RTX ia64_struct_value_rtx
399 #undef TARGET_RETURN_IN_MEMORY
400 #define TARGET_RETURN_IN_MEMORY ia64_return_in_memory
401 #undef TARGET_SETUP_INCOMING_VARARGS
402 #define TARGET_SETUP_INCOMING_VARARGS ia64_setup_incoming_varargs
403 #undef TARGET_STRICT_ARGUMENT_NAMING
404 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
405 #undef TARGET_MUST_PASS_IN_STACK
406 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
408 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
409 #define TARGET_GIMPLIFY_VA_ARG_EXPR ia64_gimplify_va_arg
411 #undef TARGET_UNWIND_EMIT
412 #define TARGET_UNWIND_EMIT process_for_unwind_directive
414 #undef TARGET_SCALAR_MODE_SUPPORTED_P
415 #define TARGET_SCALAR_MODE_SUPPORTED_P ia64_scalar_mode_supported_p
416 #undef TARGET_VECTOR_MODE_SUPPORTED_P
417 #define TARGET_VECTOR_MODE_SUPPORTED_P ia64_vector_mode_supported_p
419 /* ia64 architecture manual 4.4.7: ... reads, writes, and flushes may occur
420 in an order different from the specified program order. */
421 #undef TARGET_RELAXED_ORDERING
422 #define TARGET_RELAXED_ORDERING true
424 #undef TARGET_DEFAULT_TARGET_FLAGS
425 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | TARGET_CPU_DEFAULT)
426 #undef TARGET_HANDLE_OPTION
427 #define TARGET_HANDLE_OPTION ia64_handle_option
429 #undef TARGET_CANNOT_FORCE_CONST_MEM
430 #define TARGET_CANNOT_FORCE_CONST_MEM ia64_cannot_force_const_mem
432 struct gcc_target targetm = TARGET_INITIALIZER;
436 ADDR_AREA_NORMAL, /* normal address area */
437 ADDR_AREA_SMALL /* addressable by "addl" (-2MB < addr < 2MB) */
441 static GTY(()) tree small_ident1;
442 static GTY(()) tree small_ident2;
447 if (small_ident1 == 0)
449 small_ident1 = get_identifier ("small");
450 small_ident2 = get_identifier ("__small__");
454 /* Retrieve the address area that has been chosen for the given decl. */
456 static ia64_addr_area
457 ia64_get_addr_area (tree decl)
461 model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
467 id = TREE_VALUE (TREE_VALUE (model_attr));
468 if (id == small_ident1 || id == small_ident2)
469 return ADDR_AREA_SMALL;
471 return ADDR_AREA_NORMAL;
475 ia64_handle_model_attribute (tree *node, tree name, tree args,
476 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
478 ia64_addr_area addr_area = ADDR_AREA_NORMAL;
480 tree arg, decl = *node;
483 arg = TREE_VALUE (args);
484 if (arg == small_ident1 || arg == small_ident2)
486 addr_area = ADDR_AREA_SMALL;
490 warning (OPT_Wattributes, "invalid argument of %qs attribute",
491 IDENTIFIER_POINTER (name));
492 *no_add_attrs = true;
495 switch (TREE_CODE (decl))
498 if ((DECL_CONTEXT (decl) && TREE_CODE (DECL_CONTEXT (decl))
500 && !TREE_STATIC (decl))
502 error ("%Jan address area attribute cannot be specified for "
503 "local variables", decl, decl);
504 *no_add_attrs = true;
506 area = ia64_get_addr_area (decl);
507 if (area != ADDR_AREA_NORMAL && addr_area != area)
509 error ("%Jaddress area of '%s' conflicts with previous "
510 "declaration", decl, decl);
511 *no_add_attrs = true;
516 error ("%Jaddress area attribute cannot be specified for functions",
518 *no_add_attrs = true;
522 warning (OPT_Wattributes, "%qs attribute ignored",
523 IDENTIFIER_POINTER (name));
524 *no_add_attrs = true;
532 ia64_encode_addr_area (tree decl, rtx symbol)
536 flags = SYMBOL_REF_FLAGS (symbol);
537 switch (ia64_get_addr_area (decl))
539 case ADDR_AREA_NORMAL: break;
540 case ADDR_AREA_SMALL: flags |= SYMBOL_FLAG_SMALL_ADDR; break;
541 default: gcc_unreachable ();
543 SYMBOL_REF_FLAGS (symbol) = flags;
547 ia64_encode_section_info (tree decl, rtx rtl, int first)
549 default_encode_section_info (decl, rtl, first);
551 /* Careful not to prod global register variables. */
552 if (TREE_CODE (decl) == VAR_DECL
553 && GET_CODE (DECL_RTL (decl)) == MEM
554 && GET_CODE (XEXP (DECL_RTL (decl), 0)) == SYMBOL_REF
555 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
556 ia64_encode_addr_area (decl, XEXP (rtl, 0));
559 /* Implement CONST_OK_FOR_LETTER_P. */
562 ia64_const_ok_for_letter_p (HOST_WIDE_INT value, char c)
567 return CONST_OK_FOR_I (value);
569 return CONST_OK_FOR_J (value);
571 return CONST_OK_FOR_K (value);
573 return CONST_OK_FOR_L (value);
575 return CONST_OK_FOR_M (value);
577 return CONST_OK_FOR_N (value);
579 return CONST_OK_FOR_O (value);
581 return CONST_OK_FOR_P (value);
587 /* Implement CONST_DOUBLE_OK_FOR_LETTER_P. */
590 ia64_const_double_ok_for_letter_p (rtx value, char c)
595 return CONST_DOUBLE_OK_FOR_G (value);
601 /* Implement EXTRA_CONSTRAINT. */
604 ia64_extra_constraint (rtx value, char c)
609 /* Non-volatile memory for FP_REG loads/stores. */
610 return memory_operand(value, VOIDmode) && !MEM_VOLATILE_P (value);
613 /* 1..4 for shladd arguments. */
614 return (GET_CODE (value) == CONST_INT
615 && INTVAL (value) >= 1 && INTVAL (value) <= 4);
618 /* Non-post-inc memory for asms and other unsavory creatures. */
619 return (GET_CODE (value) == MEM
620 && GET_RTX_CLASS (GET_CODE (XEXP (value, 0))) != RTX_AUTOINC
621 && (reload_in_progress || memory_operand (value, VOIDmode)));
624 /* Symbol ref to small-address-area. */
625 return small_addr_symbolic_operand (value, VOIDmode);
629 return value == CONST0_RTX (GET_MODE (value));
632 /* An integer vector, such that conversion to an integer yields a
633 value appropriate for an integer 'J' constraint. */
634 if (GET_CODE (value) == CONST_VECTOR
635 && GET_MODE_CLASS (GET_MODE (value)) == MODE_VECTOR_INT)
637 value = simplify_subreg (DImode, value, GET_MODE (value), 0);
638 return ia64_const_ok_for_letter_p (INTVAL (value), 'J');
643 /* A V2SF vector containing elements that satisfy 'G'. */
645 (GET_CODE (value) == CONST_VECTOR
646 && GET_MODE (value) == V2SFmode
647 && ia64_const_double_ok_for_letter_p (XVECEXP (value, 0, 0), 'G')
648 && ia64_const_double_ok_for_letter_p (XVECEXP (value, 0, 1), 'G'));
655 /* Return 1 if the operands of a move are ok. */
658 ia64_move_ok (rtx dst, rtx src)
660 /* If we're under init_recog_no_volatile, we'll not be able to use
661 memory_operand. So check the code directly and don't worry about
662 the validity of the underlying address, which should have been
663 checked elsewhere anyway. */
664 if (GET_CODE (dst) != MEM)
666 if (GET_CODE (src) == MEM)
668 if (register_operand (src, VOIDmode))
671 /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0. */
672 if (INTEGRAL_MODE_P (GET_MODE (dst)))
673 return src == const0_rtx;
675 return GET_CODE (src) == CONST_DOUBLE && CONST_DOUBLE_OK_FOR_G (src);
679 addp4_optimize_ok (rtx op1, rtx op2)
681 return (basereg_operand (op1, GET_MODE(op1)) !=
682 basereg_operand (op2, GET_MODE(op2)));
685 /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction.
686 Return the length of the field, or <= 0 on failure. */
689 ia64_depz_field_mask (rtx rop, rtx rshift)
691 unsigned HOST_WIDE_INT op = INTVAL (rop);
692 unsigned HOST_WIDE_INT shift = INTVAL (rshift);
694 /* Get rid of the zero bits we're shifting in. */
697 /* We must now have a solid block of 1's at bit 0. */
698 return exact_log2 (op + 1);
701 /* Return the TLS model to use for ADDR. */
703 static enum tls_model
704 tls_symbolic_operand_type (rtx addr)
706 enum tls_model tls_kind = 0;
708 if (GET_CODE (addr) == CONST)
710 if (GET_CODE (XEXP (addr, 0)) == PLUS
711 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF)
712 tls_kind = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (addr, 0), 0));
714 else if (GET_CODE (addr) == SYMBOL_REF)
715 tls_kind = SYMBOL_REF_TLS_MODEL (addr);
720 /* Return true if X is a constant that is valid for some immediate
721 field in an instruction. */
724 ia64_legitimate_constant_p (rtx x)
726 switch (GET_CODE (x))
733 if (GET_MODE (x) == VOIDmode)
735 return CONST_DOUBLE_OK_FOR_G (x);
739 return tls_symbolic_operand_type (x) == 0;
746 /* Don't allow TLS addresses to get spilled to memory. */
749 ia64_cannot_force_const_mem (rtx x)
751 return tls_symbolic_operand_type (x) != 0;
754 /* Expand a symbolic constant load. */
757 ia64_expand_load_address (rtx dest, rtx src)
759 gcc_assert (GET_CODE (dest) == REG);
761 /* ILP32 mode still loads 64-bits of data from the GOT. This avoids
762 having to pointer-extend the value afterward. Other forms of address
763 computation below are also more natural to compute as 64-bit quantities.
764 If we've been given an SImode destination register, change it. */
765 if (GET_MODE (dest) != Pmode)
766 dest = gen_rtx_REG_offset (dest, Pmode, REGNO (dest), 0);
770 if (small_addr_symbolic_operand (src, VOIDmode))
774 emit_insn (gen_load_gprel64 (dest, src));
775 else if (GET_CODE (src) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (src))
776 emit_insn (gen_load_fptr (dest, src));
777 else if (sdata_symbolic_operand (src, VOIDmode))
778 emit_insn (gen_load_gprel (dest, src));
781 HOST_WIDE_INT addend = 0;
784 /* We did split constant offsets in ia64_expand_move, and we did try
785 to keep them split in move_operand, but we also allowed reload to
786 rematerialize arbitrary constants rather than spill the value to
787 the stack and reload it. So we have to be prepared here to split
789 if (GET_CODE (src) == CONST)
791 HOST_WIDE_INT hi, lo;
793 hi = INTVAL (XEXP (XEXP (src, 0), 1));
794 lo = ((hi & 0x3fff) ^ 0x2000) - 0x2000;
800 src = plus_constant (XEXP (XEXP (src, 0), 0), hi);
804 tmp = gen_rtx_HIGH (Pmode, src);
805 tmp = gen_rtx_PLUS (Pmode, tmp, pic_offset_table_rtx);
806 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
808 tmp = gen_rtx_LO_SUM (Pmode, dest, src);
809 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
813 tmp = gen_rtx_PLUS (Pmode, dest, GEN_INT (addend));
814 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
821 static GTY(()) rtx gen_tls_tga;
823 gen_tls_get_addr (void)
826 gen_tls_tga = init_one_libfunc ("__tls_get_addr");
830 static GTY(()) rtx thread_pointer_rtx;
832 gen_thread_pointer (void)
834 if (!thread_pointer_rtx)
835 thread_pointer_rtx = gen_rtx_REG (Pmode, 13);
836 return thread_pointer_rtx;
840 ia64_expand_tls_address (enum tls_model tls_kind, rtx op0, rtx op1,
841 HOST_WIDE_INT addend)
843 rtx tga_op1, tga_op2, tga_ret, tga_eqv, tmp, insns;
844 rtx orig_op0 = op0, orig_op1 = op1;
845 HOST_WIDE_INT addend_lo, addend_hi;
847 addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000;
848 addend_hi = addend - addend_lo;
852 case TLS_MODEL_GLOBAL_DYNAMIC:
855 tga_op1 = gen_reg_rtx (Pmode);
856 emit_insn (gen_load_dtpmod (tga_op1, op1));
858 tga_op2 = gen_reg_rtx (Pmode);
859 emit_insn (gen_load_dtprel (tga_op2, op1));
861 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
862 LCT_CONST, Pmode, 2, tga_op1,
863 Pmode, tga_op2, Pmode);
865 insns = get_insns ();
868 if (GET_MODE (op0) != Pmode)
870 emit_libcall_block (insns, op0, tga_ret, op1);
873 case TLS_MODEL_LOCAL_DYNAMIC:
874 /* ??? This isn't the completely proper way to do local-dynamic
875 If the call to __tls_get_addr is used only by a single symbol,
876 then we should (somehow) move the dtprel to the second arg
877 to avoid the extra add. */
880 tga_op1 = gen_reg_rtx (Pmode);
881 emit_insn (gen_load_dtpmod (tga_op1, op1));
883 tga_op2 = const0_rtx;
885 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
886 LCT_CONST, Pmode, 2, tga_op1,
887 Pmode, tga_op2, Pmode);
889 insns = get_insns ();
892 tga_eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
894 tmp = gen_reg_rtx (Pmode);
895 emit_libcall_block (insns, tmp, tga_ret, tga_eqv);
897 if (!register_operand (op0, Pmode))
898 op0 = gen_reg_rtx (Pmode);
901 emit_insn (gen_load_dtprel (op0, op1));
902 emit_insn (gen_adddi3 (op0, tmp, op0));
905 emit_insn (gen_add_dtprel (op0, op1, tmp));
908 case TLS_MODEL_INITIAL_EXEC:
909 op1 = plus_constant (op1, addend_hi);
912 tmp = gen_reg_rtx (Pmode);
913 emit_insn (gen_load_tprel (tmp, op1));
915 if (!register_operand (op0, Pmode))
916 op0 = gen_reg_rtx (Pmode);
917 emit_insn (gen_adddi3 (op0, tmp, gen_thread_pointer ()));
920 case TLS_MODEL_LOCAL_EXEC:
921 if (!register_operand (op0, Pmode))
922 op0 = gen_reg_rtx (Pmode);
928 emit_insn (gen_load_tprel (op0, op1));
929 emit_insn (gen_adddi3 (op0, op0, gen_thread_pointer ()));
932 emit_insn (gen_add_tprel (op0, op1, gen_thread_pointer ()));
940 op0 = expand_simple_binop (Pmode, PLUS, op0, GEN_INT (addend),
941 orig_op0, 1, OPTAB_DIRECT);
944 if (GET_MODE (orig_op0) == Pmode)
946 return gen_lowpart (GET_MODE (orig_op0), op0);
950 ia64_expand_move (rtx op0, rtx op1)
952 enum machine_mode mode = GET_MODE (op0);
954 if (!reload_in_progress && !reload_completed && !ia64_move_ok (op0, op1))
955 op1 = force_reg (mode, op1);
957 if ((mode == Pmode || mode == ptr_mode) && symbolic_operand (op1, VOIDmode))
959 HOST_WIDE_INT addend = 0;
960 enum tls_model tls_kind;
963 if (GET_CODE (op1) == CONST
964 && GET_CODE (XEXP (op1, 0)) == PLUS
965 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT)
967 addend = INTVAL (XEXP (XEXP (op1, 0), 1));
968 sym = XEXP (XEXP (op1, 0), 0);
971 tls_kind = tls_symbolic_operand_type (sym);
973 return ia64_expand_tls_address (tls_kind, op0, sym, addend);
975 if (any_offset_symbol_operand (sym, mode))
977 else if (aligned_offset_symbol_operand (sym, mode))
979 HOST_WIDE_INT addend_lo, addend_hi;
981 addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000;
982 addend_hi = addend - addend_lo;
986 op1 = plus_constant (sym, addend_hi);
995 if (reload_completed)
997 /* We really should have taken care of this offset earlier. */
998 gcc_assert (addend == 0);
999 if (ia64_expand_load_address (op0, op1))
1005 rtx subtarget = no_new_pseudos ? op0 : gen_reg_rtx (mode);
1007 emit_insn (gen_rtx_SET (VOIDmode, subtarget, op1));
1009 op1 = expand_simple_binop (mode, PLUS, subtarget,
1010 GEN_INT (addend), op0, 1, OPTAB_DIRECT);
1019 /* Split a move from OP1 to OP0 conditional on COND. */
1022 ia64_emit_cond_move (rtx op0, rtx op1, rtx cond)
1024 rtx insn, first = get_last_insn ();
1026 emit_move_insn (op0, op1);
1028 for (insn = get_last_insn (); insn != first; insn = PREV_INSN (insn))
1030 PATTERN (insn) = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond),
1034 /* Split a post-reload TImode or TFmode reference into two DImode
1035 components. This is made extra difficult by the fact that we do
1036 not get any scratch registers to work with, because reload cannot
1037 be prevented from giving us a scratch that overlaps the register
1038 pair involved. So instead, when addressing memory, we tweak the
1039 pointer register up and back down with POST_INCs. Or up and not
1040 back down when we can get away with it.
1042 REVERSED is true when the loads must be done in reversed order
1043 (high word first) for correctness. DEAD is true when the pointer
1044 dies with the second insn we generate and therefore the second
1045 address must not carry a postmodify.
1047 May return an insn which is to be emitted after the moves. */
1050 ia64_split_tmode (rtx out[2], rtx in, bool reversed, bool dead)
1054 switch (GET_CODE (in))
1057 out[reversed] = gen_rtx_REG (DImode, REGNO (in));
1058 out[!reversed] = gen_rtx_REG (DImode, REGNO (in) + 1);
1063 /* Cannot occur reversed. */
1064 gcc_assert (!reversed);
1066 if (GET_MODE (in) != TFmode)
1067 split_double (in, &out[0], &out[1]);
1069 /* split_double does not understand how to split a TFmode
1070 quantity into a pair of DImode constants. */
1073 unsigned HOST_WIDE_INT p[2];
1074 long l[4]; /* TFmode is 128 bits */
1076 REAL_VALUE_FROM_CONST_DOUBLE (r, in);
1077 real_to_target (l, &r, TFmode);
1079 if (FLOAT_WORDS_BIG_ENDIAN)
1081 p[0] = (((unsigned HOST_WIDE_INT) l[0]) << 32) + l[1];
1082 p[1] = (((unsigned HOST_WIDE_INT) l[2]) << 32) + l[3];
1086 p[0] = (((unsigned HOST_WIDE_INT) l[3]) << 32) + l[2];
1087 p[1] = (((unsigned HOST_WIDE_INT) l[1]) << 32) + l[0];
1089 out[0] = GEN_INT (p[0]);
1090 out[1] = GEN_INT (p[1]);
1096 rtx base = XEXP (in, 0);
1099 switch (GET_CODE (base))
1104 out[0] = adjust_automodify_address
1105 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1106 out[1] = adjust_automodify_address
1107 (in, DImode, dead ? 0 : gen_rtx_POST_DEC (Pmode, base), 8);
1111 /* Reversal requires a pre-increment, which can only
1112 be done as a separate insn. */
1113 emit_insn (gen_adddi3 (base, base, GEN_INT (8)));
1114 out[0] = adjust_automodify_address
1115 (in, DImode, gen_rtx_POST_DEC (Pmode, base), 8);
1116 out[1] = adjust_address (in, DImode, 0);
1121 gcc_assert (!reversed && !dead);
1123 /* Just do the increment in two steps. */
1124 out[0] = adjust_automodify_address (in, DImode, 0, 0);
1125 out[1] = adjust_automodify_address (in, DImode, 0, 8);
1129 gcc_assert (!reversed && !dead);
1131 /* Add 8, subtract 24. */
1132 base = XEXP (base, 0);
1133 out[0] = adjust_automodify_address
1134 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1135 out[1] = adjust_automodify_address
1137 gen_rtx_POST_MODIFY (Pmode, base, plus_constant (base, -24)),
1142 gcc_assert (!reversed && !dead);
1144 /* Extract and adjust the modification. This case is
1145 trickier than the others, because we might have an
1146 index register, or we might have a combined offset that
1147 doesn't fit a signed 9-bit displacement field. We can
1148 assume the incoming expression is already legitimate. */
1149 offset = XEXP (base, 1);
1150 base = XEXP (base, 0);
1152 out[0] = adjust_automodify_address
1153 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1155 if (GET_CODE (XEXP (offset, 1)) == REG)
1157 /* Can't adjust the postmodify to match. Emit the
1158 original, then a separate addition insn. */
1159 out[1] = adjust_automodify_address (in, DImode, 0, 8);
1160 fixup = gen_adddi3 (base, base, GEN_INT (-8));
1164 gcc_assert (GET_CODE (XEXP (offset, 1)) == CONST_INT);
1165 if (INTVAL (XEXP (offset, 1)) < -256 + 8)
1167 /* Again the postmodify cannot be made to match,
1168 but in this case it's more efficient to get rid
1169 of the postmodify entirely and fix up with an
1171 out[1] = adjust_automodify_address (in, DImode, base, 8);
1173 (base, base, GEN_INT (INTVAL (XEXP (offset, 1)) - 8));
1177 /* Combined offset still fits in the displacement field.
1178 (We cannot overflow it at the high end.) */
1179 out[1] = adjust_automodify_address
1180 (in, DImode, gen_rtx_POST_MODIFY
1181 (Pmode, base, gen_rtx_PLUS
1183 GEN_INT (INTVAL (XEXP (offset, 1)) - 8))),
1202 /* Split a TImode or TFmode move instruction after reload.
1203 This is used by *movtf_internal and *movti_internal. */
1205 ia64_split_tmode_move (rtx operands[])
1207 rtx in[2], out[2], insn;
1210 bool reversed = false;
1212 /* It is possible for reload to decide to overwrite a pointer with
1213 the value it points to. In that case we have to do the loads in
1214 the appropriate order so that the pointer is not destroyed too
1215 early. Also we must not generate a postmodify for that second
1216 load, or rws_access_regno will die. */
1217 if (GET_CODE (operands[1]) == MEM
1218 && reg_overlap_mentioned_p (operands[0], operands[1]))
1220 rtx base = XEXP (operands[1], 0);
1221 while (GET_CODE (base) != REG)
1222 base = XEXP (base, 0);
1224 if (REGNO (base) == REGNO (operands[0]))
1228 /* Another reason to do the moves in reversed order is if the first
1229 element of the target register pair is also the second element of
1230 the source register pair. */
1231 if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
1232 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
1235 fixup[0] = ia64_split_tmode (in, operands[1], reversed, dead);
1236 fixup[1] = ia64_split_tmode (out, operands[0], reversed, dead);
1238 #define MAYBE_ADD_REG_INC_NOTE(INSN, EXP) \
1239 if (GET_CODE (EXP) == MEM \
1240 && (GET_CODE (XEXP (EXP, 0)) == POST_MODIFY \
1241 || GET_CODE (XEXP (EXP, 0)) == POST_INC \
1242 || GET_CODE (XEXP (EXP, 0)) == POST_DEC)) \
1243 REG_NOTES (INSN) = gen_rtx_EXPR_LIST (REG_INC, \
1244 XEXP (XEXP (EXP, 0), 0), \
1247 insn = emit_insn (gen_rtx_SET (VOIDmode, out[0], in[0]));
1248 MAYBE_ADD_REG_INC_NOTE (insn, in[0]);
1249 MAYBE_ADD_REG_INC_NOTE (insn, out[0]);
1251 insn = emit_insn (gen_rtx_SET (VOIDmode, out[1], in[1]));
1252 MAYBE_ADD_REG_INC_NOTE (insn, in[1]);
1253 MAYBE_ADD_REG_INC_NOTE (insn, out[1]);
1256 emit_insn (fixup[0]);
1258 emit_insn (fixup[1]);
1260 #undef MAYBE_ADD_REG_INC_NOTE
1263 /* ??? Fixing GR->FR XFmode moves during reload is hard. You need to go
1264 through memory plus an extra GR scratch register. Except that you can
1265 either get the first from SECONDARY_MEMORY_NEEDED or the second from
1266 SECONDARY_RELOAD_CLASS, but not both.
1268 We got into problems in the first place by allowing a construct like
1269 (subreg:XF (reg:TI)), which we got from a union containing a long double.
1270 This solution attempts to prevent this situation from occurring. When
1271 we see something like the above, we spill the inner register to memory. */
1274 spill_xfmode_operand (rtx in, int force)
1276 if (GET_CODE (in) == SUBREG
1277 && GET_MODE (SUBREG_REG (in)) == TImode
1278 && GET_CODE (SUBREG_REG (in)) == REG)
1280 rtx memt = assign_stack_temp (TImode, 16, 0);
1281 emit_move_insn (memt, SUBREG_REG (in));
1282 return adjust_address (memt, XFmode, 0);
1284 else if (force && GET_CODE (in) == REG)
1286 rtx memx = assign_stack_temp (XFmode, 16, 0);
1287 emit_move_insn (memx, in);
1294 /* Emit comparison instruction if necessary, returning the expression
1295 that holds the compare result in the proper mode. */
1297 static GTY(()) rtx cmptf_libfunc;
1300 ia64_expand_compare (enum rtx_code code, enum machine_mode mode)
1302 rtx op0 = ia64_compare_op0, op1 = ia64_compare_op1;
1305 /* If we have a BImode input, then we already have a compare result, and
1306 do not need to emit another comparison. */
1307 if (GET_MODE (op0) == BImode)
1309 gcc_assert ((code == NE || code == EQ) && op1 == const0_rtx);
1312 /* HPUX TFmode compare requires a library call to _U_Qfcmp, which takes a
1313 magic number as its third argument, that indicates what to do.
1314 The return value is an integer to be compared against zero. */
1315 else if (GET_MODE (op0) == TFmode)
1318 QCMP_INV = 1, /* Raise FP_INVALID on SNaN as a side effect. */
1324 enum rtx_code ncode;
1327 gcc_assert (cmptf_libfunc && GET_MODE (op1) == TFmode);
1330 /* 1 = equal, 0 = not equal. Equality operators do
1331 not raise FP_INVALID when given an SNaN operand. */
1332 case EQ: magic = QCMP_EQ; ncode = NE; break;
1333 case NE: magic = QCMP_EQ; ncode = EQ; break;
1334 /* isunordered() from C99. */
1335 case UNORDERED: magic = QCMP_UNORD; ncode = NE; break;
1336 case ORDERED: magic = QCMP_UNORD; ncode = EQ; break;
1337 /* Relational operators raise FP_INVALID when given
1339 case LT: magic = QCMP_LT |QCMP_INV; ncode = NE; break;
1340 case LE: magic = QCMP_LT|QCMP_EQ|QCMP_INV; ncode = NE; break;
1341 case GT: magic = QCMP_GT |QCMP_INV; ncode = NE; break;
1342 case GE: magic = QCMP_GT|QCMP_EQ|QCMP_INV; ncode = NE; break;
1343 /* FUTURE: Implement UNEQ, UNLT, UNLE, UNGT, UNGE, LTGT.
1344 Expanders for buneq etc. weuld have to be added to ia64.md
1345 for this to be useful. */
1346 default: gcc_unreachable ();
1351 ret = emit_library_call_value (cmptf_libfunc, 0, LCT_CONST, DImode, 3,
1352 op0, TFmode, op1, TFmode,
1353 GEN_INT (magic), DImode);
1354 cmp = gen_reg_rtx (BImode);
1355 emit_insn (gen_rtx_SET (VOIDmode, cmp,
1356 gen_rtx_fmt_ee (ncode, BImode,
1359 insns = get_insns ();
1362 emit_libcall_block (insns, cmp, cmp,
1363 gen_rtx_fmt_ee (code, BImode, op0, op1));
1368 cmp = gen_reg_rtx (BImode);
1369 emit_insn (gen_rtx_SET (VOIDmode, cmp,
1370 gen_rtx_fmt_ee (code, BImode, op0, op1)));
1374 return gen_rtx_fmt_ee (code, mode, cmp, const0_rtx);
1377 /* Generate an integral vector comparison. */
1380 ia64_expand_vecint_compare (enum rtx_code code, enum machine_mode mode,
1381 rtx dest, rtx op0, rtx op1)
1383 bool negate = false;
1418 rtx w0h, w0l, w1h, w1l, ch, cl;
1419 enum machine_mode wmode;
1420 rtx (*unpack_l) (rtx, rtx, rtx);
1421 rtx (*unpack_h) (rtx, rtx, rtx);
1422 rtx (*pack) (rtx, rtx, rtx);
1424 /* We don't have native unsigned comparisons, but we can generate
1425 them better than generic code can. */
1427 gcc_assert (mode != V2SImode);
1432 pack = gen_pack2_sss;
1433 unpack_l = gen_unpack1_l;
1434 unpack_h = gen_unpack1_h;
1439 pack = gen_pack4_sss;
1440 unpack_l = gen_unpack2_l;
1441 unpack_h = gen_unpack2_h;
1448 /* Unpack into wider vectors, zero extending the elements. */
1450 w0l = gen_reg_rtx (wmode);
1451 w0h = gen_reg_rtx (wmode);
1452 w1l = gen_reg_rtx (wmode);
1453 w1h = gen_reg_rtx (wmode);
1454 emit_insn (unpack_l (gen_lowpart (mode, w0l), op0, CONST0_RTX (mode)));
1455 emit_insn (unpack_h (gen_lowpart (mode, w0h), op0, CONST0_RTX (mode)));
1456 emit_insn (unpack_l (gen_lowpart (mode, w1l), op1, CONST0_RTX (mode)));
1457 emit_insn (unpack_h (gen_lowpart (mode, w1h), op1, CONST0_RTX (mode)));
1459 /* Compare in the wider mode. */
1461 cl = gen_reg_rtx (wmode);
1462 ch = gen_reg_rtx (wmode);
1463 code = signed_condition (code);
1464 ia64_expand_vecint_compare (code, wmode, cl, w0l, w1l);
1465 negate = ia64_expand_vecint_compare (code, wmode, ch, w0h, w1h);
1467 /* Repack into a single narrower vector. */
1469 emit_insn (pack (dest, cl, ch));
1477 x = gen_rtx_fmt_ee (code, mode, op0, op1);
1478 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
1484 ia64_expand_vcondu_v2si (enum rtx_code code, rtx operands[])
1486 rtx dl, dh, bl, bh, op1l, op1h, op2l, op2h, op4l, op4h, op5l, op5h, x;
1488 /* In this case, we extract the two SImode quantities and generate
1489 normal comparisons for each of them. */
1491 op1l = gen_lowpart (SImode, operands[1]);
1492 op2l = gen_lowpart (SImode, operands[2]);
1493 op4l = gen_lowpart (SImode, operands[4]);
1494 op5l = gen_lowpart (SImode, operands[5]);
1496 op1h = gen_reg_rtx (SImode);
1497 op2h = gen_reg_rtx (SImode);
1498 op4h = gen_reg_rtx (SImode);
1499 op5h = gen_reg_rtx (SImode);
1501 emit_insn (gen_lshrdi3 (gen_lowpart (DImode, op1h),
1502 gen_lowpart (DImode, operands[1]), GEN_INT (32)));
1503 emit_insn (gen_lshrdi3 (gen_lowpart (DImode, op2h),
1504 gen_lowpart (DImode, operands[2]), GEN_INT (32)));
1505 emit_insn (gen_lshrdi3 (gen_lowpart (DImode, op4h),
1506 gen_lowpart (DImode, operands[4]), GEN_INT (32)));
1507 emit_insn (gen_lshrdi3 (gen_lowpart (DImode, op5h),
1508 gen_lowpart (DImode, operands[5]), GEN_INT (32)));
1510 bl = gen_reg_rtx (BImode);
1511 x = gen_rtx_fmt_ee (code, BImode, op4l, op5l);
1512 emit_insn (gen_rtx_SET (VOIDmode, bl, x));
1514 bh = gen_reg_rtx (BImode);
1515 x = gen_rtx_fmt_ee (code, BImode, op4h, op5h);
1516 emit_insn (gen_rtx_SET (VOIDmode, bh, x));
1518 /* With the results of the comparisons, emit conditional moves. */
1520 dl = gen_reg_rtx (SImode);
1521 x = gen_rtx_IF_THEN_ELSE (SImode, bl, op1l, op2l);
1522 emit_insn (gen_rtx_SET (VOIDmode, dl, x));
1524 dh = gen_reg_rtx (SImode);
1525 x = gen_rtx_IF_THEN_ELSE (SImode, bh, op1h, op2h);
1526 emit_insn (gen_rtx_SET (VOIDmode, dh, x));
1528 /* Merge the two partial results back into a vector. */
1530 x = gen_rtx_VEC_CONCAT (V2SImode, dl, dh);
1531 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1534 /* Emit an integral vector conditional move. */
1537 ia64_expand_vecint_cmov (rtx operands[])
1539 enum machine_mode mode = GET_MODE (operands[0]);
1540 enum rtx_code code = GET_CODE (operands[3]);
1544 /* Since we don't have unsigned V2SImode comparisons, it's more efficient
1545 to special-case them entirely. */
1546 if (mode == V2SImode
1547 && (code == GTU || code == GEU || code == LEU || code == LTU))
1549 ia64_expand_vcondu_v2si (code, operands);
1553 cmp = gen_reg_rtx (mode);
1554 negate = ia64_expand_vecint_compare (code, mode, cmp,
1555 operands[4], operands[5]);
1557 ot = operands[1+negate];
1558 of = operands[2-negate];
1560 if (ot == CONST0_RTX (mode))
1562 if (of == CONST0_RTX (mode))
1564 emit_move_insn (operands[0], ot);
1568 x = gen_rtx_NOT (mode, cmp);
1569 x = gen_rtx_AND (mode, x, of);
1570 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1572 else if (of == CONST0_RTX (mode))
1574 x = gen_rtx_AND (mode, cmp, ot);
1575 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1581 t = gen_reg_rtx (mode);
1582 x = gen_rtx_AND (mode, cmp, operands[1+negate]);
1583 emit_insn (gen_rtx_SET (VOIDmode, t, x));
1585 f = gen_reg_rtx (mode);
1586 x = gen_rtx_NOT (mode, cmp);
1587 x = gen_rtx_AND (mode, x, operands[2-negate]);
1588 emit_insn (gen_rtx_SET (VOIDmode, f, x));
1590 x = gen_rtx_IOR (mode, t, f);
1591 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1595 /* Emit an integral vector min or max operation. Return true if all done. */
1598 ia64_expand_vecint_minmax (enum rtx_code code, enum machine_mode mode,
1603 /* These four combinations are supported directly. */
1604 if (mode == V8QImode && (code == UMIN || code == UMAX))
1606 if (mode == V4HImode && (code == SMIN || code == SMAX))
1609 /* Everything else implemented via vector comparisons. */
1610 xops[0] = operands[0];
1611 xops[4] = xops[1] = operands[1];
1612 xops[5] = xops[2] = operands[2];
1631 xops[3] = gen_rtx_fmt_ee (code, VOIDmode, operands[1], operands[2]);
1633 ia64_expand_vecint_cmov (xops);
1637 /* Emit the appropriate sequence for a call. */
1640 ia64_expand_call (rtx retval, rtx addr, rtx nextarg ATTRIBUTE_UNUSED,
1645 addr = XEXP (addr, 0);
1646 addr = convert_memory_address (DImode, addr);
1647 b0 = gen_rtx_REG (DImode, R_BR (0));
1649 /* ??? Should do this for functions known to bind local too. */
1650 if (TARGET_NO_PIC || TARGET_AUTO_PIC)
1653 insn = gen_sibcall_nogp (addr);
1655 insn = gen_call_nogp (addr, b0);
1657 insn = gen_call_value_nogp (retval, addr, b0);
1658 insn = emit_call_insn (insn);
1663 insn = gen_sibcall_gp (addr);
1665 insn = gen_call_gp (addr, b0);
1667 insn = gen_call_value_gp (retval, addr, b0);
1668 insn = emit_call_insn (insn);
1670 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
1674 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), b0);
1678 ia64_reload_gp (void)
1682 if (current_frame_info.reg_save_gp)
1683 tmp = gen_rtx_REG (DImode, current_frame_info.reg_save_gp);
1686 HOST_WIDE_INT offset;
1688 offset = (current_frame_info.spill_cfa_off
1689 + current_frame_info.spill_size);
1690 if (frame_pointer_needed)
1692 tmp = hard_frame_pointer_rtx;
1697 tmp = stack_pointer_rtx;
1698 offset = current_frame_info.total_size - offset;
1701 if (CONST_OK_FOR_I (offset))
1702 emit_insn (gen_adddi3 (pic_offset_table_rtx,
1703 tmp, GEN_INT (offset)));
1706 emit_move_insn (pic_offset_table_rtx, GEN_INT (offset));
1707 emit_insn (gen_adddi3 (pic_offset_table_rtx,
1708 pic_offset_table_rtx, tmp));
1711 tmp = gen_rtx_MEM (DImode, pic_offset_table_rtx);
1714 emit_move_insn (pic_offset_table_rtx, tmp);
1718 ia64_split_call (rtx retval, rtx addr, rtx retaddr, rtx scratch_r,
1719 rtx scratch_b, int noreturn_p, int sibcall_p)
1722 bool is_desc = false;
1724 /* If we find we're calling through a register, then we're actually
1725 calling through a descriptor, so load up the values. */
1726 if (REG_P (addr) && GR_REGNO_P (REGNO (addr)))
1731 /* ??? We are currently constrained to *not* use peep2, because
1732 we can legitimately change the global lifetime of the GP
1733 (in the form of killing where previously live). This is
1734 because a call through a descriptor doesn't use the previous
1735 value of the GP, while a direct call does, and we do not
1736 commit to either form until the split here.
1738 That said, this means that we lack precise life info for
1739 whether ADDR is dead after this call. This is not terribly
1740 important, since we can fix things up essentially for free
1741 with the POST_DEC below, but it's nice to not use it when we
1742 can immediately tell it's not necessary. */
1743 addr_dead_p = ((noreturn_p || sibcall_p
1744 || TEST_HARD_REG_BIT (regs_invalidated_by_call,
1746 && !FUNCTION_ARG_REGNO_P (REGNO (addr)));
1748 /* Load the code address into scratch_b. */
1749 tmp = gen_rtx_POST_INC (Pmode, addr);
1750 tmp = gen_rtx_MEM (Pmode, tmp);
1751 emit_move_insn (scratch_r, tmp);
1752 emit_move_insn (scratch_b, scratch_r);
1754 /* Load the GP address. If ADDR is not dead here, then we must
1755 revert the change made above via the POST_INCREMENT. */
1757 tmp = gen_rtx_POST_DEC (Pmode, addr);
1760 tmp = gen_rtx_MEM (Pmode, tmp);
1761 emit_move_insn (pic_offset_table_rtx, tmp);
1768 insn = gen_sibcall_nogp (addr);
1770 insn = gen_call_value_nogp (retval, addr, retaddr);
1772 insn = gen_call_nogp (addr, retaddr);
1773 emit_call_insn (insn);
1775 if ((!TARGET_CONST_GP || is_desc) && !noreturn_p && !sibcall_p)
1779 /* Expand an atomic operation. We want to perform MEM <CODE>= VAL atomically.
1781 This differs from the generic code in that we know about the zero-extending
1782 properties of cmpxchg, and the zero-extending requirements of ar.ccv. We
1783 also know that ld.acq+cmpxchg.rel equals a full barrier.
1785 The loop we want to generate looks like
1790 new_reg = cmp_reg op val;
1791 cmp_reg = compare-and-swap(mem, old_reg, new_reg)
1792 if (cmp_reg != old_reg)
1795 Note that we only do the plain load from memory once. Subsequent
1796 iterations use the value loaded by the compare-and-swap pattern. */
1799 ia64_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
1800 rtx old_dst, rtx new_dst)
1802 enum machine_mode mode = GET_MODE (mem);
1803 rtx old_reg, new_reg, cmp_reg, ar_ccv, label;
1804 enum insn_code icode;
1806 /* Special case for using fetchadd. */
1807 if ((mode == SImode || mode == DImode) && fetchadd_operand (val, mode))
1810 old_dst = gen_reg_rtx (mode);
1812 emit_insn (gen_memory_barrier ());
1815 icode = CODE_FOR_fetchadd_acq_si;
1817 icode = CODE_FOR_fetchadd_acq_di;
1818 emit_insn (GEN_FCN (icode) (old_dst, mem, val));
1822 new_reg = expand_simple_binop (mode, PLUS, old_dst, val, new_dst,
1824 if (new_reg != new_dst)
1825 emit_move_insn (new_dst, new_reg);
1830 /* Because of the volatile mem read, we get an ld.acq, which is the
1831 front half of the full barrier. The end half is the cmpxchg.rel. */
1832 gcc_assert (MEM_VOLATILE_P (mem));
1834 old_reg = gen_reg_rtx (DImode);
1835 cmp_reg = gen_reg_rtx (DImode);
1836 label = gen_label_rtx ();
1840 val = simplify_gen_subreg (DImode, val, mode, 0);
1841 emit_insn (gen_extend_insn (cmp_reg, mem, DImode, mode, 1));
1844 emit_move_insn (cmp_reg, mem);
1848 ar_ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
1849 emit_move_insn (old_reg, cmp_reg);
1850 emit_move_insn (ar_ccv, cmp_reg);
1853 emit_move_insn (old_dst, gen_lowpart (mode, cmp_reg));
1858 new_reg = expand_simple_unop (DImode, NOT, new_reg, NULL_RTX, true);
1861 new_reg = expand_simple_binop (DImode, code, new_reg, val, NULL_RTX,
1862 true, OPTAB_DIRECT);
1865 new_reg = gen_lowpart (mode, new_reg);
1867 emit_move_insn (new_dst, new_reg);
1871 case QImode: icode = CODE_FOR_cmpxchg_rel_qi; break;
1872 case HImode: icode = CODE_FOR_cmpxchg_rel_hi; break;
1873 case SImode: icode = CODE_FOR_cmpxchg_rel_si; break;
1874 case DImode: icode = CODE_FOR_cmpxchg_rel_di; break;
1879 emit_insn (GEN_FCN (icode) (cmp_reg, mem, ar_ccv, new_reg));
1881 emit_cmp_and_jump_insns (cmp_reg, old_reg, EQ, NULL, DImode, true, label);
1884 /* Begin the assembly file. */
1887 ia64_file_start (void)
1889 /* Variable tracking should be run after all optimizations which change order
1890 of insns. It also needs a valid CFG. This can't be done in
1891 ia64_override_options, because flag_var_tracking is finalized after
1893 ia64_flag_var_tracking = flag_var_tracking;
1894 flag_var_tracking = 0;
1896 default_file_start ();
1897 emit_safe_across_calls ();
1901 emit_safe_across_calls (void)
1903 unsigned int rs, re;
1910 while (rs < 64 && call_used_regs[PR_REG (rs)])
1914 for (re = rs + 1; re < 64 && ! call_used_regs[PR_REG (re)]; re++)
1918 fputs ("\t.pred.safe_across_calls ", asm_out_file);
1922 fputc (',', asm_out_file);
1924 fprintf (asm_out_file, "p%u", rs);
1926 fprintf (asm_out_file, "p%u-p%u", rs, re - 1);
1930 fputc ('\n', asm_out_file);
1933 /* Helper function for ia64_compute_frame_size: find an appropriate general
1934 register to spill some special register to. SPECIAL_SPILL_MASK contains
1935 bits in GR0 to GR31 that have already been allocated by this routine.
1936 TRY_LOCALS is true if we should attempt to locate a local regnum. */
1939 find_gr_spill (int try_locals)
1943 /* If this is a leaf function, first try an otherwise unused
1944 call-clobbered register. */
1945 if (current_function_is_leaf)
1947 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
1948 if (! regs_ever_live[regno]
1949 && call_used_regs[regno]
1950 && ! fixed_regs[regno]
1951 && ! global_regs[regno]
1952 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0)
1954 current_frame_info.gr_used_mask |= 1 << regno;
1961 regno = current_frame_info.n_local_regs;
1962 /* If there is a frame pointer, then we can't use loc79, because
1963 that is HARD_FRAME_POINTER_REGNUM. In particular, see the
1964 reg_name switching code in ia64_expand_prologue. */
1965 if (regno < (80 - frame_pointer_needed))
1967 current_frame_info.n_local_regs = regno + 1;
1968 return LOC_REG (0) + regno;
1972 /* Failed to find a general register to spill to. Must use stack. */
1976 /* In order to make for nice schedules, we try to allocate every temporary
1977 to a different register. We must of course stay away from call-saved,
1978 fixed, and global registers. We must also stay away from registers
1979 allocated in current_frame_info.gr_used_mask, since those include regs
1980 used all through the prologue.
1982 Any register allocated here must be used immediately. The idea is to
1983 aid scheduling, not to solve data flow problems. */
1985 static int last_scratch_gr_reg;
1988 next_scratch_gr_reg (void)
1992 for (i = 0; i < 32; ++i)
1994 regno = (last_scratch_gr_reg + i + 1) & 31;
1995 if (call_used_regs[regno]
1996 && ! fixed_regs[regno]
1997 && ! global_regs[regno]
1998 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0)
2000 last_scratch_gr_reg = regno;
2005 /* There must be _something_ available. */
2009 /* Helper function for ia64_compute_frame_size, called through
2010 diddle_return_value. Mark REG in current_frame_info.gr_used_mask. */
2013 mark_reg_gr_used_mask (rtx reg, void *data ATTRIBUTE_UNUSED)
2015 unsigned int regno = REGNO (reg);
2018 unsigned int i, n = hard_regno_nregs[regno][GET_MODE (reg)];
2019 for (i = 0; i < n; ++i)
2020 current_frame_info.gr_used_mask |= 1 << (regno + i);
2024 /* Returns the number of bytes offset between the frame pointer and the stack
2025 pointer for the current function. SIZE is the number of bytes of space
2026 needed for local variables. */
2029 ia64_compute_frame_size (HOST_WIDE_INT size)
2031 HOST_WIDE_INT total_size;
2032 HOST_WIDE_INT spill_size = 0;
2033 HOST_WIDE_INT extra_spill_size = 0;
2034 HOST_WIDE_INT pretend_args_size;
2037 int spilled_gr_p = 0;
2038 int spilled_fr_p = 0;
2042 if (current_frame_info.initialized)
2045 memset (¤t_frame_info, 0, sizeof current_frame_info);
2046 CLEAR_HARD_REG_SET (mask);
2048 /* Don't allocate scratches to the return register. */
2049 diddle_return_value (mark_reg_gr_used_mask, NULL);
2051 /* Don't allocate scratches to the EH scratch registers. */
2052 if (cfun->machine->ia64_eh_epilogue_sp)
2053 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_sp, NULL);
2054 if (cfun->machine->ia64_eh_epilogue_bsp)
2055 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_bsp, NULL);
2057 /* Find the size of the register stack frame. We have only 80 local
2058 registers, because we reserve 8 for the inputs and 8 for the
2061 /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed,
2062 since we'll be adjusting that down later. */
2063 regno = LOC_REG (78) + ! frame_pointer_needed;
2064 for (; regno >= LOC_REG (0); regno--)
2065 if (regs_ever_live[regno])
2067 current_frame_info.n_local_regs = regno - LOC_REG (0) + 1;
2069 /* For functions marked with the syscall_linkage attribute, we must mark
2070 all eight input registers as in use, so that locals aren't visible to
2073 if (cfun->machine->n_varargs > 0
2074 || lookup_attribute ("syscall_linkage",
2075 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
2076 current_frame_info.n_input_regs = 8;
2079 for (regno = IN_REG (7); regno >= IN_REG (0); regno--)
2080 if (regs_ever_live[regno])
2082 current_frame_info.n_input_regs = regno - IN_REG (0) + 1;
2085 for (regno = OUT_REG (7); regno >= OUT_REG (0); regno--)
2086 if (regs_ever_live[regno])
2088 i = regno - OUT_REG (0) + 1;
2090 /* When -p profiling, we need one output register for the mcount argument.
2091 Likewise for -a profiling for the bb_init_func argument. For -ax
2092 profiling, we need two output registers for the two bb_init_trace_func
2094 if (current_function_profile)
2096 current_frame_info.n_output_regs = i;
2098 /* ??? No rotating register support yet. */
2099 current_frame_info.n_rotate_regs = 0;
2101 /* Discover which registers need spilling, and how much room that
2102 will take. Begin with floating point and general registers,
2103 which will always wind up on the stack. */
2105 for (regno = FR_REG (2); regno <= FR_REG (127); regno++)
2106 if (regs_ever_live[regno] && ! call_used_regs[regno])
2108 SET_HARD_REG_BIT (mask, regno);
2114 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
2115 if (regs_ever_live[regno] && ! call_used_regs[regno])
2117 SET_HARD_REG_BIT (mask, regno);
2123 for (regno = BR_REG (1); regno <= BR_REG (7); regno++)
2124 if (regs_ever_live[regno] && ! call_used_regs[regno])
2126 SET_HARD_REG_BIT (mask, regno);
2131 /* Now come all special registers that might get saved in other
2132 general registers. */
2134 if (frame_pointer_needed)
2136 current_frame_info.reg_fp = find_gr_spill (1);
2137 /* If we did not get a register, then we take LOC79. This is guaranteed
2138 to be free, even if regs_ever_live is already set, because this is
2139 HARD_FRAME_POINTER_REGNUM. This requires incrementing n_local_regs,
2140 as we don't count loc79 above. */
2141 if (current_frame_info.reg_fp == 0)
2143 current_frame_info.reg_fp = LOC_REG (79);
2144 current_frame_info.n_local_regs++;
2148 if (! current_function_is_leaf)
2150 /* Emit a save of BR0 if we call other functions. Do this even
2151 if this function doesn't return, as EH depends on this to be
2152 able to unwind the stack. */
2153 SET_HARD_REG_BIT (mask, BR_REG (0));
2155 current_frame_info.reg_save_b0 = find_gr_spill (1);
2156 if (current_frame_info.reg_save_b0 == 0)
2162 /* Similarly for ar.pfs. */
2163 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
2164 current_frame_info.reg_save_ar_pfs = find_gr_spill (1);
2165 if (current_frame_info.reg_save_ar_pfs == 0)
2167 extra_spill_size += 8;
2171 /* Similarly for gp. Note that if we're calling setjmp, the stacked
2172 registers are clobbered, so we fall back to the stack. */
2173 current_frame_info.reg_save_gp
2174 = (current_function_calls_setjmp ? 0 : find_gr_spill (1));
2175 if (current_frame_info.reg_save_gp == 0)
2177 SET_HARD_REG_BIT (mask, GR_REG (1));
2184 if (regs_ever_live[BR_REG (0)] && ! call_used_regs[BR_REG (0)])
2186 SET_HARD_REG_BIT (mask, BR_REG (0));
2191 if (regs_ever_live[AR_PFS_REGNUM])
2193 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
2194 current_frame_info.reg_save_ar_pfs = find_gr_spill (1);
2195 if (current_frame_info.reg_save_ar_pfs == 0)
2197 extra_spill_size += 8;
2203 /* Unwind descriptor hackery: things are most efficient if we allocate
2204 consecutive GR save registers for RP, PFS, FP in that order. However,
2205 it is absolutely critical that FP get the only hard register that's
2206 guaranteed to be free, so we allocated it first. If all three did
2207 happen to be allocated hard regs, and are consecutive, rearrange them
2208 into the preferred order now. */
2209 if (current_frame_info.reg_fp != 0
2210 && current_frame_info.reg_save_b0 == current_frame_info.reg_fp + 1
2211 && current_frame_info.reg_save_ar_pfs == current_frame_info.reg_fp + 2)
2213 current_frame_info.reg_save_b0 = current_frame_info.reg_fp;
2214 current_frame_info.reg_save_ar_pfs = current_frame_info.reg_fp + 1;
2215 current_frame_info.reg_fp = current_frame_info.reg_fp + 2;
2218 /* See if we need to store the predicate register block. */
2219 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
2220 if (regs_ever_live[regno] && ! call_used_regs[regno])
2222 if (regno <= PR_REG (63))
2224 SET_HARD_REG_BIT (mask, PR_REG (0));
2225 current_frame_info.reg_save_pr = find_gr_spill (1);
2226 if (current_frame_info.reg_save_pr == 0)
2228 extra_spill_size += 8;
2232 /* ??? Mark them all as used so that register renaming and such
2233 are free to use them. */
2234 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
2235 regs_ever_live[regno] = 1;
2238 /* If we're forced to use st8.spill, we're forced to save and restore
2239 ar.unat as well. The check for existing liveness allows inline asm
2240 to touch ar.unat. */
2241 if (spilled_gr_p || cfun->machine->n_varargs
2242 || regs_ever_live[AR_UNAT_REGNUM])
2244 regs_ever_live[AR_UNAT_REGNUM] = 1;
2245 SET_HARD_REG_BIT (mask, AR_UNAT_REGNUM);
2246 current_frame_info.reg_save_ar_unat = find_gr_spill (spill_size == 0);
2247 if (current_frame_info.reg_save_ar_unat == 0)
2249 extra_spill_size += 8;
2254 if (regs_ever_live[AR_LC_REGNUM])
2256 SET_HARD_REG_BIT (mask, AR_LC_REGNUM);
2257 current_frame_info.reg_save_ar_lc = find_gr_spill (spill_size == 0);
2258 if (current_frame_info.reg_save_ar_lc == 0)
2260 extra_spill_size += 8;
2265 /* If we have an odd number of words of pretend arguments written to
2266 the stack, then the FR save area will be unaligned. We round the
2267 size of this area up to keep things 16 byte aligned. */
2269 pretend_args_size = IA64_STACK_ALIGN (current_function_pretend_args_size);
2271 pretend_args_size = current_function_pretend_args_size;
2273 total_size = (spill_size + extra_spill_size + size + pretend_args_size
2274 + current_function_outgoing_args_size);
2275 total_size = IA64_STACK_ALIGN (total_size);
2277 /* We always use the 16-byte scratch area provided by the caller, but
2278 if we are a leaf function, there's no one to which we need to provide
2280 if (current_function_is_leaf)
2281 total_size = MAX (0, total_size - 16);
2283 current_frame_info.total_size = total_size;
2284 current_frame_info.spill_cfa_off = pretend_args_size - 16;
2285 current_frame_info.spill_size = spill_size;
2286 current_frame_info.extra_spill_size = extra_spill_size;
2287 COPY_HARD_REG_SET (current_frame_info.mask, mask);
2288 current_frame_info.n_spilled = n_spilled;
2289 current_frame_info.initialized = reload_completed;
2292 /* Compute the initial difference between the specified pair of registers. */
2295 ia64_initial_elimination_offset (int from, int to)
2297 HOST_WIDE_INT offset;
2299 ia64_compute_frame_size (get_frame_size ());
2302 case FRAME_POINTER_REGNUM:
2305 case HARD_FRAME_POINTER_REGNUM:
2306 if (current_function_is_leaf)
2307 offset = -current_frame_info.total_size;
2309 offset = -(current_frame_info.total_size
2310 - current_function_outgoing_args_size - 16);
2313 case STACK_POINTER_REGNUM:
2314 if (current_function_is_leaf)
2317 offset = 16 + current_function_outgoing_args_size;
2325 case ARG_POINTER_REGNUM:
2326 /* Arguments start above the 16 byte save area, unless stdarg
2327 in which case we store through the 16 byte save area. */
2330 case HARD_FRAME_POINTER_REGNUM:
2331 offset = 16 - current_function_pretend_args_size;
2334 case STACK_POINTER_REGNUM:
2335 offset = (current_frame_info.total_size
2336 + 16 - current_function_pretend_args_size);
2351 /* If there are more than a trivial number of register spills, we use
2352 two interleaved iterators so that we can get two memory references
2355 In order to simplify things in the prologue and epilogue expanders,
2356 we use helper functions to fix up the memory references after the
2357 fact with the appropriate offsets to a POST_MODIFY memory mode.
2358 The following data structure tracks the state of the two iterators
2359 while insns are being emitted. */
2361 struct spill_fill_data
2363 rtx init_after; /* point at which to emit initializations */
2364 rtx init_reg[2]; /* initial base register */
2365 rtx iter_reg[2]; /* the iterator registers */
2366 rtx *prev_addr[2]; /* address of last memory use */
2367 rtx prev_insn[2]; /* the insn corresponding to prev_addr */
2368 HOST_WIDE_INT prev_off[2]; /* last offset */
2369 int n_iter; /* number of iterators in use */
2370 int next_iter; /* next iterator to use */
2371 unsigned int save_gr_used_mask;
2374 static struct spill_fill_data spill_fill_data;
2377 setup_spill_pointers (int n_spills, rtx init_reg, HOST_WIDE_INT cfa_off)
2381 spill_fill_data.init_after = get_last_insn ();
2382 spill_fill_data.init_reg[0] = init_reg;
2383 spill_fill_data.init_reg[1] = init_reg;
2384 spill_fill_data.prev_addr[0] = NULL;
2385 spill_fill_data.prev_addr[1] = NULL;
2386 spill_fill_data.prev_insn[0] = NULL;
2387 spill_fill_data.prev_insn[1] = NULL;
2388 spill_fill_data.prev_off[0] = cfa_off;
2389 spill_fill_data.prev_off[1] = cfa_off;
2390 spill_fill_data.next_iter = 0;
2391 spill_fill_data.save_gr_used_mask = current_frame_info.gr_used_mask;
2393 spill_fill_data.n_iter = 1 + (n_spills > 2);
2394 for (i = 0; i < spill_fill_data.n_iter; ++i)
2396 int regno = next_scratch_gr_reg ();
2397 spill_fill_data.iter_reg[i] = gen_rtx_REG (DImode, regno);
2398 current_frame_info.gr_used_mask |= 1 << regno;
2403 finish_spill_pointers (void)
2405 current_frame_info.gr_used_mask = spill_fill_data.save_gr_used_mask;
2409 spill_restore_mem (rtx reg, HOST_WIDE_INT cfa_off)
2411 int iter = spill_fill_data.next_iter;
2412 HOST_WIDE_INT disp = spill_fill_data.prev_off[iter] - cfa_off;
2413 rtx disp_rtx = GEN_INT (disp);
2416 if (spill_fill_data.prev_addr[iter])
2418 if (CONST_OK_FOR_N (disp))
2420 *spill_fill_data.prev_addr[iter]
2421 = gen_rtx_POST_MODIFY (DImode, spill_fill_data.iter_reg[iter],
2422 gen_rtx_PLUS (DImode,
2423 spill_fill_data.iter_reg[iter],
2425 REG_NOTES (spill_fill_data.prev_insn[iter])
2426 = gen_rtx_EXPR_LIST (REG_INC, spill_fill_data.iter_reg[iter],
2427 REG_NOTES (spill_fill_data.prev_insn[iter]));
2431 /* ??? Could use register post_modify for loads. */
2432 if (! CONST_OK_FOR_I (disp))
2434 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
2435 emit_move_insn (tmp, disp_rtx);
2438 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
2439 spill_fill_data.iter_reg[iter], disp_rtx));
2442 /* Micro-optimization: if we've created a frame pointer, it's at
2443 CFA 0, which may allow the real iterator to be initialized lower,
2444 slightly increasing parallelism. Also, if there are few saves
2445 it may eliminate the iterator entirely. */
2447 && spill_fill_data.init_reg[iter] == stack_pointer_rtx
2448 && frame_pointer_needed)
2450 mem = gen_rtx_MEM (GET_MODE (reg), hard_frame_pointer_rtx);
2451 set_mem_alias_set (mem, get_varargs_alias_set ());
2459 seq = gen_movdi (spill_fill_data.iter_reg[iter],
2460 spill_fill_data.init_reg[iter]);
2465 if (! CONST_OK_FOR_I (disp))
2467 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
2468 emit_move_insn (tmp, disp_rtx);
2472 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
2473 spill_fill_data.init_reg[iter],
2480 /* Careful for being the first insn in a sequence. */
2481 if (spill_fill_data.init_after)
2482 insn = emit_insn_after (seq, spill_fill_data.init_after);
2485 rtx first = get_insns ();
2487 insn = emit_insn_before (seq, first);
2489 insn = emit_insn (seq);
2491 spill_fill_data.init_after = insn;
2493 /* If DISP is 0, we may or may not have a further adjustment
2494 afterward. If we do, then the load/store insn may be modified
2495 to be a post-modify. If we don't, then this copy may be
2496 eliminated by copyprop_hardreg_forward, which makes this
2497 insn garbage, which runs afoul of the sanity check in
2498 propagate_one_insn. So mark this insn as legal to delete. */
2500 REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx,
2504 mem = gen_rtx_MEM (GET_MODE (reg), spill_fill_data.iter_reg[iter]);
2506 /* ??? Not all of the spills are for varargs, but some of them are.
2507 The rest of the spills belong in an alias set of their own. But
2508 it doesn't actually hurt to include them here. */
2509 set_mem_alias_set (mem, get_varargs_alias_set ());
2511 spill_fill_data.prev_addr[iter] = &XEXP (mem, 0);
2512 spill_fill_data.prev_off[iter] = cfa_off;
2514 if (++iter >= spill_fill_data.n_iter)
2516 spill_fill_data.next_iter = iter;
2522 do_spill (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off,
2525 int iter = spill_fill_data.next_iter;
2528 mem = spill_restore_mem (reg, cfa_off);
2529 insn = emit_insn ((*move_fn) (mem, reg, GEN_INT (cfa_off)));
2530 spill_fill_data.prev_insn[iter] = insn;
2537 RTX_FRAME_RELATED_P (insn) = 1;
2539 /* Don't even pretend that the unwind code can intuit its way
2540 through a pair of interleaved post_modify iterators. Just
2541 provide the correct answer. */
2543 if (frame_pointer_needed)
2545 base = hard_frame_pointer_rtx;
2550 base = stack_pointer_rtx;
2551 off = current_frame_info.total_size - cfa_off;
2555 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2556 gen_rtx_SET (VOIDmode,
2557 gen_rtx_MEM (GET_MODE (reg),
2558 plus_constant (base, off)),
2565 do_restore (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off)
2567 int iter = spill_fill_data.next_iter;
2570 insn = emit_insn ((*move_fn) (reg, spill_restore_mem (reg, cfa_off),
2571 GEN_INT (cfa_off)));
2572 spill_fill_data.prev_insn[iter] = insn;
2575 /* Wrapper functions that discards the CONST_INT spill offset. These
2576 exist so that we can give gr_spill/gr_fill the offset they need and
2577 use a consistent function interface. */
2580 gen_movdi_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
2582 return gen_movdi (dest, src);
2586 gen_fr_spill_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
2588 return gen_fr_spill (dest, src);
2592 gen_fr_restore_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
2594 return gen_fr_restore (dest, src);
2597 /* Called after register allocation to add any instructions needed for the
2598 prologue. Using a prologue insn is favored compared to putting all of the
2599 instructions in output_function_prologue(), since it allows the scheduler
2600 to intermix instructions with the saves of the caller saved registers. In
2601 some cases, it might be necessary to emit a barrier instruction as the last
2602 insn to prevent such scheduling.
2604 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
2605 so that the debug info generation code can handle them properly.
2607 The register save area is layed out like so:
2609 [ varargs spill area ]
2610 [ fr register spill area ]
2611 [ br register spill area ]
2612 [ ar register spill area ]
2613 [ pr register spill area ]
2614 [ gr register spill area ] */
2616 /* ??? Get inefficient code when the frame size is larger than can fit in an
2617 adds instruction. */
2620 ia64_expand_prologue (void)
2622 rtx insn, ar_pfs_save_reg, ar_unat_save_reg;
2623 int i, epilogue_p, regno, alt_regno, cfa_off, n_varargs;
2626 ia64_compute_frame_size (get_frame_size ());
2627 last_scratch_gr_reg = 15;
2629 /* If there is no epilogue, then we don't need some prologue insns.
2630 We need to avoid emitting the dead prologue insns, because flow
2631 will complain about them. */
2637 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
2638 if ((e->flags & EDGE_FAKE) == 0
2639 && (e->flags & EDGE_FALLTHRU) != 0)
2641 epilogue_p = (e != NULL);
2646 /* Set the local, input, and output register names. We need to do this
2647 for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in
2648 half. If we use in/loc/out register names, then we get assembler errors
2649 in crtn.S because there is no alloc insn or regstk directive in there. */
2650 if (! TARGET_REG_NAMES)
2652 int inputs = current_frame_info.n_input_regs;
2653 int locals = current_frame_info.n_local_regs;
2654 int outputs = current_frame_info.n_output_regs;
2656 for (i = 0; i < inputs; i++)
2657 reg_names[IN_REG (i)] = ia64_reg_numbers[i];
2658 for (i = 0; i < locals; i++)
2659 reg_names[LOC_REG (i)] = ia64_reg_numbers[inputs + i];
2660 for (i = 0; i < outputs; i++)
2661 reg_names[OUT_REG (i)] = ia64_reg_numbers[inputs + locals + i];
2664 /* Set the frame pointer register name. The regnum is logically loc79,
2665 but of course we'll not have allocated that many locals. Rather than
2666 worrying about renumbering the existing rtxs, we adjust the name. */
2667 /* ??? This code means that we can never use one local register when
2668 there is a frame pointer. loc79 gets wasted in this case, as it is
2669 renamed to a register that will never be used. See also the try_locals
2670 code in find_gr_spill. */
2671 if (current_frame_info.reg_fp)
2673 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
2674 reg_names[HARD_FRAME_POINTER_REGNUM]
2675 = reg_names[current_frame_info.reg_fp];
2676 reg_names[current_frame_info.reg_fp] = tmp;
2679 /* We don't need an alloc instruction if we've used no outputs or locals. */
2680 if (current_frame_info.n_local_regs == 0
2681 && current_frame_info.n_output_regs == 0
2682 && current_frame_info.n_input_regs <= current_function_args_info.int_regs
2683 && !TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM))
2685 /* If there is no alloc, but there are input registers used, then we
2686 need a .regstk directive. */
2687 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
2688 ar_pfs_save_reg = NULL_RTX;
2692 current_frame_info.need_regstk = 0;
2694 if (current_frame_info.reg_save_ar_pfs)
2695 regno = current_frame_info.reg_save_ar_pfs;
2697 regno = next_scratch_gr_reg ();
2698 ar_pfs_save_reg = gen_rtx_REG (DImode, regno);
2700 insn = emit_insn (gen_alloc (ar_pfs_save_reg,
2701 GEN_INT (current_frame_info.n_input_regs),
2702 GEN_INT (current_frame_info.n_local_regs),
2703 GEN_INT (current_frame_info.n_output_regs),
2704 GEN_INT (current_frame_info.n_rotate_regs)));
2705 RTX_FRAME_RELATED_P (insn) = (current_frame_info.reg_save_ar_pfs != 0);
2708 /* Set up frame pointer, stack pointer, and spill iterators. */
2710 n_varargs = cfun->machine->n_varargs;
2711 setup_spill_pointers (current_frame_info.n_spilled + n_varargs,
2712 stack_pointer_rtx, 0);
2714 if (frame_pointer_needed)
2716 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
2717 RTX_FRAME_RELATED_P (insn) = 1;
2720 if (current_frame_info.total_size != 0)
2722 rtx frame_size_rtx = GEN_INT (- current_frame_info.total_size);
2725 if (CONST_OK_FOR_I (- current_frame_info.total_size))
2726 offset = frame_size_rtx;
2729 regno = next_scratch_gr_reg ();
2730 offset = gen_rtx_REG (DImode, regno);
2731 emit_move_insn (offset, frame_size_rtx);
2734 insn = emit_insn (gen_adddi3 (stack_pointer_rtx,
2735 stack_pointer_rtx, offset));
2737 if (! frame_pointer_needed)
2739 RTX_FRAME_RELATED_P (insn) = 1;
2740 if (GET_CODE (offset) != CONST_INT)
2743 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2744 gen_rtx_SET (VOIDmode,
2746 gen_rtx_PLUS (DImode,
2753 /* ??? At this point we must generate a magic insn that appears to
2754 modify the stack pointer, the frame pointer, and all spill
2755 iterators. This would allow the most scheduling freedom. For
2756 now, just hard stop. */
2757 emit_insn (gen_blockage ());
2760 /* Must copy out ar.unat before doing any integer spills. */
2761 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
2763 if (current_frame_info.reg_save_ar_unat)
2765 = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_unat);
2768 alt_regno = next_scratch_gr_reg ();
2769 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
2770 current_frame_info.gr_used_mask |= 1 << alt_regno;
2773 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
2774 insn = emit_move_insn (ar_unat_save_reg, reg);
2775 RTX_FRAME_RELATED_P (insn) = (current_frame_info.reg_save_ar_unat != 0);
2777 /* Even if we're not going to generate an epilogue, we still
2778 need to save the register so that EH works. */
2779 if (! epilogue_p && current_frame_info.reg_save_ar_unat)
2780 emit_insn (gen_prologue_use (ar_unat_save_reg));
2783 ar_unat_save_reg = NULL_RTX;
2785 /* Spill all varargs registers. Do this before spilling any GR registers,
2786 since we want the UNAT bits for the GR registers to override the UNAT
2787 bits from varargs, which we don't care about. */
2790 for (regno = GR_ARG_FIRST + 7; n_varargs > 0; --n_varargs, --regno)
2792 reg = gen_rtx_REG (DImode, regno);
2793 do_spill (gen_gr_spill, reg, cfa_off += 8, NULL_RTX);
2796 /* Locate the bottom of the register save area. */
2797 cfa_off = (current_frame_info.spill_cfa_off
2798 + current_frame_info.spill_size
2799 + current_frame_info.extra_spill_size);
2801 /* Save the predicate register block either in a register or in memory. */
2802 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
2804 reg = gen_rtx_REG (DImode, PR_REG (0));
2805 if (current_frame_info.reg_save_pr != 0)
2807 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_pr);
2808 insn = emit_move_insn (alt_reg, reg);
2810 /* ??? Denote pr spill/fill by a DImode move that modifies all
2811 64 hard registers. */
2812 RTX_FRAME_RELATED_P (insn) = 1;
2814 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2815 gen_rtx_SET (VOIDmode, alt_reg, reg),
2818 /* Even if we're not going to generate an epilogue, we still
2819 need to save the register so that EH works. */
2821 emit_insn (gen_prologue_use (alt_reg));
2825 alt_regno = next_scratch_gr_reg ();
2826 alt_reg = gen_rtx_REG (DImode, alt_regno);
2827 insn = emit_move_insn (alt_reg, reg);
2828 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
2833 /* Handle AR regs in numerical order. All of them get special handling. */
2834 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM)
2835 && current_frame_info.reg_save_ar_unat == 0)
2837 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
2838 do_spill (gen_movdi_x, ar_unat_save_reg, cfa_off, reg);
2842 /* The alloc insn already copied ar.pfs into a general register. The
2843 only thing we have to do now is copy that register to a stack slot
2844 if we'd not allocated a local register for the job. */
2845 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM)
2846 && current_frame_info.reg_save_ar_pfs == 0)
2848 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
2849 do_spill (gen_movdi_x, ar_pfs_save_reg, cfa_off, reg);
2853 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
2855 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
2856 if (current_frame_info.reg_save_ar_lc != 0)
2858 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_lc);
2859 insn = emit_move_insn (alt_reg, reg);
2860 RTX_FRAME_RELATED_P (insn) = 1;
2862 /* Even if we're not going to generate an epilogue, we still
2863 need to save the register so that EH works. */
2865 emit_insn (gen_prologue_use (alt_reg));
2869 alt_regno = next_scratch_gr_reg ();
2870 alt_reg = gen_rtx_REG (DImode, alt_regno);
2871 emit_move_insn (alt_reg, reg);
2872 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
2877 if (current_frame_info.reg_save_gp)
2879 insn = emit_move_insn (gen_rtx_REG (DImode,
2880 current_frame_info.reg_save_gp),
2881 pic_offset_table_rtx);
2882 /* We don't know for sure yet if this is actually needed, since
2883 we've not split the PIC call patterns. If all of the calls
2884 are indirect, and not followed by any uses of the gp, then
2885 this save is dead. Allow it to go away. */
2887 = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx, REG_NOTES (insn));
2890 /* We should now be at the base of the gr/br/fr spill area. */
2891 gcc_assert (cfa_off == (current_frame_info.spill_cfa_off
2892 + current_frame_info.spill_size));
2894 /* Spill all general registers. */
2895 for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
2896 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2898 reg = gen_rtx_REG (DImode, regno);
2899 do_spill (gen_gr_spill, reg, cfa_off, reg);
2903 /* Handle BR0 specially -- it may be getting stored permanently in
2904 some GR register. */
2905 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
2907 reg = gen_rtx_REG (DImode, BR_REG (0));
2908 if (current_frame_info.reg_save_b0 != 0)
2910 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
2911 insn = emit_move_insn (alt_reg, reg);
2912 RTX_FRAME_RELATED_P (insn) = 1;
2914 /* Even if we're not going to generate an epilogue, we still
2915 need to save the register so that EH works. */
2917 emit_insn (gen_prologue_use (alt_reg));
2921 alt_regno = next_scratch_gr_reg ();
2922 alt_reg = gen_rtx_REG (DImode, alt_regno);
2923 emit_move_insn (alt_reg, reg);
2924 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
2929 /* Spill the rest of the BR registers. */
2930 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
2931 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2933 alt_regno = next_scratch_gr_reg ();
2934 alt_reg = gen_rtx_REG (DImode, alt_regno);
2935 reg = gen_rtx_REG (DImode, regno);
2936 emit_move_insn (alt_reg, reg);
2937 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
2941 /* Align the frame and spill all FR registers. */
2942 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
2943 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2945 gcc_assert (!(cfa_off & 15));
2946 reg = gen_rtx_REG (XFmode, regno);
2947 do_spill (gen_fr_spill_x, reg, cfa_off, reg);
2951 gcc_assert (cfa_off == current_frame_info.spill_cfa_off);
2953 finish_spill_pointers ();
2956 /* Called after register allocation to add any instructions needed for the
2957 epilogue. Using an epilogue insn is favored compared to putting all of the
2958 instructions in output_function_prologue(), since it allows the scheduler
2959 to intermix instructions with the saves of the caller saved registers. In
2960 some cases, it might be necessary to emit a barrier instruction as the last
2961 insn to prevent such scheduling. */
2964 ia64_expand_epilogue (int sibcall_p)
2966 rtx insn, reg, alt_reg, ar_unat_save_reg;
2967 int regno, alt_regno, cfa_off;
2969 ia64_compute_frame_size (get_frame_size ());
2971 /* If there is a frame pointer, then we use it instead of the stack
2972 pointer, so that the stack pointer does not need to be valid when
2973 the epilogue starts. See EXIT_IGNORE_STACK. */
2974 if (frame_pointer_needed)
2975 setup_spill_pointers (current_frame_info.n_spilled,
2976 hard_frame_pointer_rtx, 0);
2978 setup_spill_pointers (current_frame_info.n_spilled, stack_pointer_rtx,
2979 current_frame_info.total_size);
2981 if (current_frame_info.total_size != 0)
2983 /* ??? At this point we must generate a magic insn that appears to
2984 modify the spill iterators and the frame pointer. This would
2985 allow the most scheduling freedom. For now, just hard stop. */
2986 emit_insn (gen_blockage ());
2989 /* Locate the bottom of the register save area. */
2990 cfa_off = (current_frame_info.spill_cfa_off
2991 + current_frame_info.spill_size
2992 + current_frame_info.extra_spill_size);
2994 /* Restore the predicate registers. */
2995 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
2997 if (current_frame_info.reg_save_pr != 0)
2998 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_pr);
3001 alt_regno = next_scratch_gr_reg ();
3002 alt_reg = gen_rtx_REG (DImode, alt_regno);
3003 do_restore (gen_movdi_x, alt_reg, cfa_off);
3006 reg = gen_rtx_REG (DImode, PR_REG (0));
3007 emit_move_insn (reg, alt_reg);
3010 /* Restore the application registers. */
3012 /* Load the saved unat from the stack, but do not restore it until
3013 after the GRs have been restored. */
3014 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
3016 if (current_frame_info.reg_save_ar_unat != 0)
3018 = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_unat);
3021 alt_regno = next_scratch_gr_reg ();
3022 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
3023 current_frame_info.gr_used_mask |= 1 << alt_regno;
3024 do_restore (gen_movdi_x, ar_unat_save_reg, cfa_off);
3029 ar_unat_save_reg = NULL_RTX;
3031 if (current_frame_info.reg_save_ar_pfs != 0)
3033 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_pfs);
3034 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3035 emit_move_insn (reg, alt_reg);
3037 else if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM))
3039 alt_regno = next_scratch_gr_reg ();
3040 alt_reg = gen_rtx_REG (DImode, alt_regno);
3041 do_restore (gen_movdi_x, alt_reg, cfa_off);
3043 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3044 emit_move_insn (reg, alt_reg);
3047 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
3049 if (current_frame_info.reg_save_ar_lc != 0)
3050 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_lc);
3053 alt_regno = next_scratch_gr_reg ();
3054 alt_reg = gen_rtx_REG (DImode, alt_regno);
3055 do_restore (gen_movdi_x, alt_reg, cfa_off);
3058 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
3059 emit_move_insn (reg, alt_reg);
3062 /* We should now be at the base of the gr/br/fr spill area. */
3063 gcc_assert (cfa_off == (current_frame_info.spill_cfa_off
3064 + current_frame_info.spill_size));
3066 /* The GP may be stored on the stack in the prologue, but it's
3067 never restored in the epilogue. Skip the stack slot. */
3068 if (TEST_HARD_REG_BIT (current_frame_info.mask, GR_REG (1)))
3071 /* Restore all general registers. */
3072 for (regno = GR_REG (2); regno <= GR_REG (31); ++regno)
3073 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3075 reg = gen_rtx_REG (DImode, regno);
3076 do_restore (gen_gr_restore, reg, cfa_off);
3080 /* Restore the branch registers. Handle B0 specially, as it may
3081 have gotten stored in some GR register. */
3082 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3084 if (current_frame_info.reg_save_b0 != 0)
3085 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
3088 alt_regno = next_scratch_gr_reg ();
3089 alt_reg = gen_rtx_REG (DImode, alt_regno);
3090 do_restore (gen_movdi_x, alt_reg, cfa_off);
3093 reg = gen_rtx_REG (DImode, BR_REG (0));
3094 emit_move_insn (reg, alt_reg);
3097 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
3098 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3100 alt_regno = next_scratch_gr_reg ();
3101 alt_reg = gen_rtx_REG (DImode, alt_regno);
3102 do_restore (gen_movdi_x, alt_reg, cfa_off);
3104 reg = gen_rtx_REG (DImode, regno);
3105 emit_move_insn (reg, alt_reg);
3108 /* Restore floating point registers. */
3109 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
3110 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3112 gcc_assert (!(cfa_off & 15));
3113 reg = gen_rtx_REG (XFmode, regno);
3114 do_restore (gen_fr_restore_x, reg, cfa_off);
3118 /* Restore ar.unat for real. */
3119 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
3121 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3122 emit_move_insn (reg, ar_unat_save_reg);
3125 gcc_assert (cfa_off == current_frame_info.spill_cfa_off);
3127 finish_spill_pointers ();
3129 if (current_frame_info.total_size || cfun->machine->ia64_eh_epilogue_sp)
3131 /* ??? At this point we must generate a magic insn that appears to
3132 modify the spill iterators, the stack pointer, and the frame
3133 pointer. This would allow the most scheduling freedom. For now,
3135 emit_insn (gen_blockage ());
3138 if (cfun->machine->ia64_eh_epilogue_sp)
3139 emit_move_insn (stack_pointer_rtx, cfun->machine->ia64_eh_epilogue_sp);
3140 else if (frame_pointer_needed)
3142 insn = emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
3143 RTX_FRAME_RELATED_P (insn) = 1;
3145 else if (current_frame_info.total_size)
3147 rtx offset, frame_size_rtx;
3149 frame_size_rtx = GEN_INT (current_frame_info.total_size);
3150 if (CONST_OK_FOR_I (current_frame_info.total_size))
3151 offset = frame_size_rtx;
3154 regno = next_scratch_gr_reg ();
3155 offset = gen_rtx_REG (DImode, regno);
3156 emit_move_insn (offset, frame_size_rtx);
3159 insn = emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
3162 RTX_FRAME_RELATED_P (insn) = 1;
3163 if (GET_CODE (offset) != CONST_INT)
3166 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3167 gen_rtx_SET (VOIDmode,
3169 gen_rtx_PLUS (DImode,
3176 if (cfun->machine->ia64_eh_epilogue_bsp)
3177 emit_insn (gen_set_bsp (cfun->machine->ia64_eh_epilogue_bsp));
3180 emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode, BR_REG (0))));
3183 int fp = GR_REG (2);
3184 /* We need a throw away register here, r0 and r1 are reserved, so r2 is the
3185 first available call clobbered register. If there was a frame_pointer
3186 register, we may have swapped the names of r2 and HARD_FRAME_POINTER_REGNUM,
3187 so we have to make sure we're using the string "r2" when emitting
3188 the register name for the assembler. */
3189 if (current_frame_info.reg_fp && current_frame_info.reg_fp == GR_REG (2))
3190 fp = HARD_FRAME_POINTER_REGNUM;
3192 /* We must emit an alloc to force the input registers to become output
3193 registers. Otherwise, if the callee tries to pass its parameters
3194 through to another call without an intervening alloc, then these
3196 /* ??? We don't need to preserve all input registers. We only need to
3197 preserve those input registers used as arguments to the sibling call.
3198 It is unclear how to compute that number here. */
3199 if (current_frame_info.n_input_regs != 0)
3201 rtx n_inputs = GEN_INT (current_frame_info.n_input_regs);
3202 insn = emit_insn (gen_alloc (gen_rtx_REG (DImode, fp),
3203 const0_rtx, const0_rtx,
3204 n_inputs, const0_rtx));
3205 RTX_FRAME_RELATED_P (insn) = 1;
3210 /* Return 1 if br.ret can do all the work required to return from a
3214 ia64_direct_return (void)
3216 if (reload_completed && ! frame_pointer_needed)
3218 ia64_compute_frame_size (get_frame_size ());
3220 return (current_frame_info.total_size == 0
3221 && current_frame_info.n_spilled == 0
3222 && current_frame_info.reg_save_b0 == 0
3223 && current_frame_info.reg_save_pr == 0
3224 && current_frame_info.reg_save_ar_pfs == 0
3225 && current_frame_info.reg_save_ar_unat == 0
3226 && current_frame_info.reg_save_ar_lc == 0);
3231 /* Return the magic cookie that we use to hold the return address
3232 during early compilation. */
3235 ia64_return_addr_rtx (HOST_WIDE_INT count, rtx frame ATTRIBUTE_UNUSED)
3239 return gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_RET_ADDR);
3242 /* Split this value after reload, now that we know where the return
3243 address is saved. */
3246 ia64_split_return_addr_rtx (rtx dest)
3250 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3252 if (current_frame_info.reg_save_b0 != 0)
3253 src = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
3259 /* Compute offset from CFA for BR0. */
3260 /* ??? Must be kept in sync with ia64_expand_prologue. */
3261 off = (current_frame_info.spill_cfa_off
3262 + current_frame_info.spill_size);
3263 for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
3264 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3267 /* Convert CFA offset to a register based offset. */
3268 if (frame_pointer_needed)
3269 src = hard_frame_pointer_rtx;
3272 src = stack_pointer_rtx;
3273 off += current_frame_info.total_size;
3276 /* Load address into scratch register. */
3277 if (CONST_OK_FOR_I (off))
3278 emit_insn (gen_adddi3 (dest, src, GEN_INT (off)));
3281 emit_move_insn (dest, GEN_INT (off));
3282 emit_insn (gen_adddi3 (dest, src, dest));
3285 src = gen_rtx_MEM (Pmode, dest);
3289 src = gen_rtx_REG (DImode, BR_REG (0));
3291 emit_move_insn (dest, src);
3295 ia64_hard_regno_rename_ok (int from, int to)
3297 /* Don't clobber any of the registers we reserved for the prologue. */
3298 if (to == current_frame_info.reg_fp
3299 || to == current_frame_info.reg_save_b0
3300 || to == current_frame_info.reg_save_pr
3301 || to == current_frame_info.reg_save_ar_pfs
3302 || to == current_frame_info.reg_save_ar_unat
3303 || to == current_frame_info.reg_save_ar_lc)
3306 if (from == current_frame_info.reg_fp
3307 || from == current_frame_info.reg_save_b0
3308 || from == current_frame_info.reg_save_pr
3309 || from == current_frame_info.reg_save_ar_pfs
3310 || from == current_frame_info.reg_save_ar_unat
3311 || from == current_frame_info.reg_save_ar_lc)
3314 /* Don't use output registers outside the register frame. */
3315 if (OUT_REGNO_P (to) && to >= OUT_REG (current_frame_info.n_output_regs))
3318 /* Retain even/oddness on predicate register pairs. */
3319 if (PR_REGNO_P (from) && PR_REGNO_P (to))
3320 return (from & 1) == (to & 1);
3325 /* Target hook for assembling integer objects. Handle word-sized
3326 aligned objects and detect the cases when @fptr is needed. */
3329 ia64_assemble_integer (rtx x, unsigned int size, int aligned_p)
3331 if (size == POINTER_SIZE / BITS_PER_UNIT
3332 && !(TARGET_NO_PIC || TARGET_AUTO_PIC)
3333 && GET_CODE (x) == SYMBOL_REF
3334 && SYMBOL_REF_FUNCTION_P (x))
3336 static const char * const directive[2][2] = {
3337 /* 64-bit pointer */ /* 32-bit pointer */
3338 { "\tdata8.ua\t@fptr(", "\tdata4.ua\t@fptr("}, /* unaligned */
3339 { "\tdata8\t@fptr(", "\tdata4\t@fptr("} /* aligned */
3341 fputs (directive[(aligned_p != 0)][POINTER_SIZE == 32], asm_out_file);
3342 output_addr_const (asm_out_file, x);
3343 fputs (")\n", asm_out_file);
3346 return default_assemble_integer (x, size, aligned_p);
3349 /* Emit the function prologue. */
3352 ia64_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3354 int mask, grsave, grsave_prev;
3356 if (current_frame_info.need_regstk)
3357 fprintf (file, "\t.regstk %d, %d, %d, %d\n",
3358 current_frame_info.n_input_regs,
3359 current_frame_info.n_local_regs,
3360 current_frame_info.n_output_regs,
3361 current_frame_info.n_rotate_regs);
3363 if (!flag_unwind_tables && (!flag_exceptions || USING_SJLJ_EXCEPTIONS))
3366 /* Emit the .prologue directive. */
3369 grsave = grsave_prev = 0;
3370 if (current_frame_info.reg_save_b0 != 0)
3373 grsave = grsave_prev = current_frame_info.reg_save_b0;
3375 if (current_frame_info.reg_save_ar_pfs != 0
3376 && (grsave_prev == 0
3377 || current_frame_info.reg_save_ar_pfs == grsave_prev + 1))
3380 if (grsave_prev == 0)
3381 grsave = current_frame_info.reg_save_ar_pfs;
3382 grsave_prev = current_frame_info.reg_save_ar_pfs;
3384 if (current_frame_info.reg_fp != 0
3385 && (grsave_prev == 0
3386 || current_frame_info.reg_fp == grsave_prev + 1))
3389 if (grsave_prev == 0)
3390 grsave = HARD_FRAME_POINTER_REGNUM;
3391 grsave_prev = current_frame_info.reg_fp;
3393 if (current_frame_info.reg_save_pr != 0
3394 && (grsave_prev == 0
3395 || current_frame_info.reg_save_pr == grsave_prev + 1))
3398 if (grsave_prev == 0)
3399 grsave = current_frame_info.reg_save_pr;
3402 if (mask && TARGET_GNU_AS)
3403 fprintf (file, "\t.prologue %d, %d\n", mask,
3404 ia64_dbx_register_number (grsave));
3406 fputs ("\t.prologue\n", file);
3408 /* Emit a .spill directive, if necessary, to relocate the base of
3409 the register spill area. */
3410 if (current_frame_info.spill_cfa_off != -16)
3411 fprintf (file, "\t.spill %ld\n",
3412 (long) (current_frame_info.spill_cfa_off
3413 + current_frame_info.spill_size));
3416 /* Emit the .body directive at the scheduled end of the prologue. */
3419 ia64_output_function_end_prologue (FILE *file)
3421 if (!flag_unwind_tables && (!flag_exceptions || USING_SJLJ_EXCEPTIONS))
3424 fputs ("\t.body\n", file);
3427 /* Emit the function epilogue. */
3430 ia64_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
3431 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3435 if (current_frame_info.reg_fp)
3437 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
3438 reg_names[HARD_FRAME_POINTER_REGNUM]
3439 = reg_names[current_frame_info.reg_fp];
3440 reg_names[current_frame_info.reg_fp] = tmp;
3442 if (! TARGET_REG_NAMES)
3444 for (i = 0; i < current_frame_info.n_input_regs; i++)
3445 reg_names[IN_REG (i)] = ia64_input_reg_names[i];
3446 for (i = 0; i < current_frame_info.n_local_regs; i++)
3447 reg_names[LOC_REG (i)] = ia64_local_reg_names[i];
3448 for (i = 0; i < current_frame_info.n_output_regs; i++)
3449 reg_names[OUT_REG (i)] = ia64_output_reg_names[i];
3452 current_frame_info.initialized = 0;
3456 ia64_dbx_register_number (int regno)
3458 /* In ia64_expand_prologue we quite literally renamed the frame pointer
3459 from its home at loc79 to something inside the register frame. We
3460 must perform the same renumbering here for the debug info. */
3461 if (current_frame_info.reg_fp)
3463 if (regno == HARD_FRAME_POINTER_REGNUM)
3464 regno = current_frame_info.reg_fp;
3465 else if (regno == current_frame_info.reg_fp)
3466 regno = HARD_FRAME_POINTER_REGNUM;
3469 if (IN_REGNO_P (regno))
3470 return 32 + regno - IN_REG (0);
3471 else if (LOC_REGNO_P (regno))
3472 return 32 + current_frame_info.n_input_regs + regno - LOC_REG (0);
3473 else if (OUT_REGNO_P (regno))
3474 return (32 + current_frame_info.n_input_regs
3475 + current_frame_info.n_local_regs + regno - OUT_REG (0));
3481 ia64_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
3483 rtx addr_reg, eight = GEN_INT (8);
3485 /* The Intel assembler requires that the global __ia64_trampoline symbol
3486 be declared explicitly */
3489 static bool declared_ia64_trampoline = false;
3491 if (!declared_ia64_trampoline)
3493 declared_ia64_trampoline = true;
3494 (*targetm.asm_out.globalize_label) (asm_out_file,
3495 "__ia64_trampoline");
3499 /* Make sure addresses are Pmode even if we are in ILP32 mode. */
3500 addr = convert_memory_address (Pmode, addr);
3501 fnaddr = convert_memory_address (Pmode, fnaddr);
3502 static_chain = convert_memory_address (Pmode, static_chain);
3504 /* Load up our iterator. */
3505 addr_reg = gen_reg_rtx (Pmode);
3506 emit_move_insn (addr_reg, addr);
3508 /* The first two words are the fake descriptor:
3509 __ia64_trampoline, ADDR+16. */
3510 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg),
3511 gen_rtx_SYMBOL_REF (Pmode, "__ia64_trampoline"));
3512 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
3514 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg),
3515 copy_to_reg (plus_constant (addr, 16)));
3516 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
3518 /* The third word is the target descriptor. */
3519 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg), fnaddr);
3520 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
3522 /* The fourth word is the static chain. */
3523 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg), static_chain);
3526 /* Do any needed setup for a variadic function. CUM has not been updated
3527 for the last named argument which has type TYPE and mode MODE.
3529 We generate the actual spill instructions during prologue generation. */
3532 ia64_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3533 tree type, int * pretend_size,
3534 int second_time ATTRIBUTE_UNUSED)
3536 CUMULATIVE_ARGS next_cum = *cum;
3538 /* Skip the current argument. */
3539 ia64_function_arg_advance (&next_cum, mode, type, 1);
3541 if (next_cum.words < MAX_ARGUMENT_SLOTS)
3543 int n = MAX_ARGUMENT_SLOTS - next_cum.words;
3544 *pretend_size = n * UNITS_PER_WORD;
3545 cfun->machine->n_varargs = n;
3549 /* Check whether TYPE is a homogeneous floating point aggregate. If
3550 it is, return the mode of the floating point type that appears
3551 in all leafs. If it is not, return VOIDmode.
3553 An aggregate is a homogeneous floating point aggregate is if all
3554 fields/elements in it have the same floating point type (e.g,
3555 SFmode). 128-bit quad-precision floats are excluded.
3557 Variable sized aggregates should never arrive here, since we should
3558 have already decided to pass them by reference. Top-level zero-sized
3559 aggregates are excluded because our parallels crash the middle-end. */
3561 static enum machine_mode
3562 hfa_element_mode (tree type, bool nested)
3564 enum machine_mode element_mode = VOIDmode;
3565 enum machine_mode mode;
3566 enum tree_code code = TREE_CODE (type);
3567 int know_element_mode = 0;
3570 if (!nested && (!TYPE_SIZE (type) || integer_zerop (TYPE_SIZE (type))))
3575 case VOID_TYPE: case INTEGER_TYPE: case ENUMERAL_TYPE:
3576 case BOOLEAN_TYPE: case CHAR_TYPE: case POINTER_TYPE:
3577 case OFFSET_TYPE: case REFERENCE_TYPE: case METHOD_TYPE:
3578 case LANG_TYPE: case FUNCTION_TYPE:
3581 /* Fortran complex types are supposed to be HFAs, so we need to handle
3582 gcc's COMPLEX_TYPEs as HFAs. We need to exclude the integral complex
3585 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_FLOAT
3586 && TYPE_MODE (type) != TCmode)
3587 return GET_MODE_INNER (TYPE_MODE (type));
3592 /* We want to return VOIDmode for raw REAL_TYPEs, but the actual
3593 mode if this is contained within an aggregate. */
3594 if (nested && TYPE_MODE (type) != TFmode)
3595 return TYPE_MODE (type);
3600 return hfa_element_mode (TREE_TYPE (type), 1);
3604 case QUAL_UNION_TYPE:
3605 for (t = TYPE_FIELDS (type); t; t = TREE_CHAIN (t))
3607 if (TREE_CODE (t) != FIELD_DECL)
3610 mode = hfa_element_mode (TREE_TYPE (t), 1);
3611 if (know_element_mode)
3613 if (mode != element_mode)
3616 else if (GET_MODE_CLASS (mode) != MODE_FLOAT)
3620 know_element_mode = 1;
3621 element_mode = mode;
3624 return element_mode;
3627 /* If we reach here, we probably have some front-end specific type
3628 that the backend doesn't know about. This can happen via the
3629 aggregate_value_p call in init_function_start. All we can do is
3630 ignore unknown tree types. */
3637 /* Return the number of words required to hold a quantity of TYPE and MODE
3638 when passed as an argument. */
3640 ia64_function_arg_words (tree type, enum machine_mode mode)
3644 if (mode == BLKmode)
3645 words = int_size_in_bytes (type);
3647 words = GET_MODE_SIZE (mode);
3649 return (words + UNITS_PER_WORD - 1) / UNITS_PER_WORD; /* round up */
3652 /* Return the number of registers that should be skipped so the current
3653 argument (described by TYPE and WORDS) will be properly aligned.
3655 Integer and float arguments larger than 8 bytes start at the next
3656 even boundary. Aggregates larger than 8 bytes start at the next
3657 even boundary if the aggregate has 16 byte alignment. Note that
3658 in the 32-bit ABI, TImode and TFmode have only 8-byte alignment
3659 but are still to be aligned in registers.
3661 ??? The ABI does not specify how to handle aggregates with
3662 alignment from 9 to 15 bytes, or greater than 16. We handle them
3663 all as if they had 16 byte alignment. Such aggregates can occur
3664 only if gcc extensions are used. */
3666 ia64_function_arg_offset (CUMULATIVE_ARGS *cum, tree type, int words)
3668 if ((cum->words & 1) == 0)
3672 && TREE_CODE (type) != INTEGER_TYPE
3673 && TREE_CODE (type) != REAL_TYPE)
3674 return TYPE_ALIGN (type) > 8 * BITS_PER_UNIT;
3679 /* Return rtx for register where argument is passed, or zero if it is passed
3681 /* ??? 128-bit quad-precision floats are always passed in general
3685 ia64_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
3686 int named, int incoming)
3688 int basereg = (incoming ? GR_ARG_FIRST : AR_ARG_FIRST);
3689 int words = ia64_function_arg_words (type, mode);
3690 int offset = ia64_function_arg_offset (cum, type, words);
3691 enum machine_mode hfa_mode = VOIDmode;
3693 /* If all argument slots are used, then it must go on the stack. */
3694 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
3697 /* Check for and handle homogeneous FP aggregates. */
3699 hfa_mode = hfa_element_mode (type, 0);
3701 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
3702 and unprototyped hfas are passed specially. */
3703 if (hfa_mode != VOIDmode && (! cum->prototype || named))
3707 int fp_regs = cum->fp_regs;
3708 int int_regs = cum->words + offset;
3709 int hfa_size = GET_MODE_SIZE (hfa_mode);
3713 /* If prototyped, pass it in FR regs then GR regs.
3714 If not prototyped, pass it in both FR and GR regs.
3716 If this is an SFmode aggregate, then it is possible to run out of
3717 FR regs while GR regs are still left. In that case, we pass the
3718 remaining part in the GR regs. */
3720 /* Fill the FP regs. We do this always. We stop if we reach the end
3721 of the argument, the last FP register, or the last argument slot. */
3723 byte_size = ((mode == BLKmode)
3724 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
3725 args_byte_size = int_regs * UNITS_PER_WORD;
3727 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
3728 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD)); i++)
3730 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
3731 gen_rtx_REG (hfa_mode, (FR_ARG_FIRST
3735 args_byte_size += hfa_size;
3739 /* If no prototype, then the whole thing must go in GR regs. */
3740 if (! cum->prototype)
3742 /* If this is an SFmode aggregate, then we might have some left over
3743 that needs to go in GR regs. */
3744 else if (byte_size != offset)
3745 int_regs += offset / UNITS_PER_WORD;
3747 /* Fill in the GR regs. We must use DImode here, not the hfa mode. */
3749 for (; offset < byte_size && int_regs < MAX_ARGUMENT_SLOTS; i++)
3751 enum machine_mode gr_mode = DImode;
3752 unsigned int gr_size;
3754 /* If we have an odd 4 byte hunk because we ran out of FR regs,
3755 then this goes in a GR reg left adjusted/little endian, right
3756 adjusted/big endian. */
3757 /* ??? Currently this is handled wrong, because 4-byte hunks are
3758 always right adjusted/little endian. */
3761 /* If we have an even 4 byte hunk because the aggregate is a
3762 multiple of 4 bytes in size, then this goes in a GR reg right
3763 adjusted/little endian. */
3764 else if (byte_size - offset == 4)
3767 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
3768 gen_rtx_REG (gr_mode, (basereg
3772 gr_size = GET_MODE_SIZE (gr_mode);
3774 if (gr_size == UNITS_PER_WORD
3775 || (gr_size < UNITS_PER_WORD && offset % UNITS_PER_WORD == 0))
3777 else if (gr_size > UNITS_PER_WORD)
3778 int_regs += gr_size / UNITS_PER_WORD;
3780 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
3783 /* Integral and aggregates go in general registers. If we have run out of
3784 FR registers, then FP values must also go in general registers. This can
3785 happen when we have a SFmode HFA. */
3786 else if (mode == TFmode || mode == TCmode
3787 || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
3789 int byte_size = ((mode == BLKmode)
3790 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
3791 if (BYTES_BIG_ENDIAN
3792 && (mode == BLKmode || (type && AGGREGATE_TYPE_P (type)))
3793 && byte_size < UNITS_PER_WORD
3796 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
3797 gen_rtx_REG (DImode,
3798 (basereg + cum->words
3801 return gen_rtx_PARALLEL (mode, gen_rtvec (1, gr_reg));
3804 return gen_rtx_REG (mode, basereg + cum->words + offset);
3808 /* If there is a prototype, then FP values go in a FR register when
3809 named, and in a GR register when unnamed. */
3810 else if (cum->prototype)
3813 return gen_rtx_REG (mode, FR_ARG_FIRST + cum->fp_regs);
3814 /* In big-endian mode, an anonymous SFmode value must be represented
3815 as (parallel:SF [(expr_list (reg:DI n) (const_int 0))]) to force
3816 the value into the high half of the general register. */
3817 else if (BYTES_BIG_ENDIAN && mode == SFmode)
3818 return gen_rtx_PARALLEL (mode,
3820 gen_rtx_EXPR_LIST (VOIDmode,
3821 gen_rtx_REG (DImode, basereg + cum->words + offset),
3824 return gen_rtx_REG (mode, basereg + cum->words + offset);
3826 /* If there is no prototype, then FP values go in both FR and GR
3830 /* See comment above. */
3831 enum machine_mode inner_mode =
3832 (BYTES_BIG_ENDIAN && mode == SFmode) ? DImode : mode;
3834 rtx fp_reg = gen_rtx_EXPR_LIST (VOIDmode,
3835 gen_rtx_REG (mode, (FR_ARG_FIRST
3838 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
3839 gen_rtx_REG (inner_mode,
3840 (basereg + cum->words
3844 return gen_rtx_PARALLEL (mode, gen_rtvec (2, fp_reg, gr_reg));
3848 /* Return number of bytes, at the beginning of the argument, that must be
3849 put in registers. 0 is the argument is entirely in registers or entirely
3853 ia64_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3854 tree type, bool named ATTRIBUTE_UNUSED)
3856 int words = ia64_function_arg_words (type, mode);
3857 int offset = ia64_function_arg_offset (cum, type, words);
3859 /* If all argument slots are used, then it must go on the stack. */
3860 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
3863 /* It doesn't matter whether the argument goes in FR or GR regs. If
3864 it fits within the 8 argument slots, then it goes entirely in
3865 registers. If it extends past the last argument slot, then the rest
3866 goes on the stack. */
3868 if (words + cum->words + offset <= MAX_ARGUMENT_SLOTS)
3871 return (MAX_ARGUMENT_SLOTS - cum->words - offset) * UNITS_PER_WORD;
3874 /* Update CUM to point after this argument. This is patterned after
3875 ia64_function_arg. */
3878 ia64_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3879 tree type, int named)
3881 int words = ia64_function_arg_words (type, mode);
3882 int offset = ia64_function_arg_offset (cum, type, words);
3883 enum machine_mode hfa_mode = VOIDmode;
3885 /* If all arg slots are already full, then there is nothing to do. */
3886 if (cum->words >= MAX_ARGUMENT_SLOTS)
3889 cum->words += words + offset;
3891 /* Check for and handle homogeneous FP aggregates. */
3893 hfa_mode = hfa_element_mode (type, 0);
3895 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
3896 and unprototyped hfas are passed specially. */
3897 if (hfa_mode != VOIDmode && (! cum->prototype || named))
3899 int fp_regs = cum->fp_regs;
3900 /* This is the original value of cum->words + offset. */
3901 int int_regs = cum->words - words;
3902 int hfa_size = GET_MODE_SIZE (hfa_mode);
3906 /* If prototyped, pass it in FR regs then GR regs.
3907 If not prototyped, pass it in both FR and GR regs.
3909 If this is an SFmode aggregate, then it is possible to run out of
3910 FR regs while GR regs are still left. In that case, we pass the
3911 remaining part in the GR regs. */
3913 /* Fill the FP regs. We do this always. We stop if we reach the end
3914 of the argument, the last FP register, or the last argument slot. */
3916 byte_size = ((mode == BLKmode)
3917 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
3918 args_byte_size = int_regs * UNITS_PER_WORD;
3920 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
3921 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD));)
3924 args_byte_size += hfa_size;
3928 cum->fp_regs = fp_regs;
3931 /* Integral and aggregates go in general registers. So do TFmode FP values.
3932 If we have run out of FR registers, then other FP values must also go in
3933 general registers. This can happen when we have a SFmode HFA. */
3934 else if (mode == TFmode || mode == TCmode
3935 || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
3936 cum->int_regs = cum->words;
3938 /* If there is a prototype, then FP values go in a FR register when
3939 named, and in a GR register when unnamed. */
3940 else if (cum->prototype)
3943 cum->int_regs = cum->words;
3945 /* ??? Complex types should not reach here. */
3946 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
3948 /* If there is no prototype, then FP values go in both FR and GR
3952 /* ??? Complex types should not reach here. */
3953 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
3954 cum->int_regs = cum->words;
3958 /* Arguments with alignment larger than 8 bytes start at the next even
3959 boundary. On ILP32 HPUX, TFmode arguments start on next even boundary
3960 even though their normal alignment is 8 bytes. See ia64_function_arg. */
3963 ia64_function_arg_boundary (enum machine_mode mode, tree type)
3966 if (mode == TFmode && TARGET_HPUX && TARGET_ILP32)
3967 return PARM_BOUNDARY * 2;
3971 if (TYPE_ALIGN (type) > PARM_BOUNDARY)
3972 return PARM_BOUNDARY * 2;
3974 return PARM_BOUNDARY;
3977 if (GET_MODE_BITSIZE (mode) > PARM_BOUNDARY)
3978 return PARM_BOUNDARY * 2;
3980 return PARM_BOUNDARY;
3983 /* Variable sized types are passed by reference. */
3984 /* ??? At present this is a GCC extension to the IA-64 ABI. */
3987 ia64_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
3988 enum machine_mode mode ATTRIBUTE_UNUSED,
3989 tree type, bool named ATTRIBUTE_UNUSED)
3991 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
3994 /* True if it is OK to do sibling call optimization for the specified
3995 call expression EXP. DECL will be the called function, or NULL if
3996 this is an indirect call. */
3998 ia64_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
4000 /* We can't perform a sibcall if the current function has the syscall_linkage
4002 if (lookup_attribute ("syscall_linkage",
4003 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
4006 /* We must always return with our current GP. This means we can
4007 only sibcall to functions defined in the current module. */
4008 return decl && (*targetm.binds_local_p) (decl);
4012 /* Implement va_arg. */
4015 ia64_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
4017 /* Variable sized types are passed by reference. */
4018 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
4020 tree ptrtype = build_pointer_type (type);
4021 tree addr = std_gimplify_va_arg_expr (valist, ptrtype, pre_p, post_p);
4022 return build_va_arg_indirect_ref (addr);
4025 /* Aggregate arguments with alignment larger than 8 bytes start at
4026 the next even boundary. Integer and floating point arguments
4027 do so if they are larger than 8 bytes, whether or not they are
4028 also aligned larger than 8 bytes. */
4029 if ((TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == INTEGER_TYPE)
4030 ? int_size_in_bytes (type) > 8 : TYPE_ALIGN (type) > 8 * BITS_PER_UNIT)
4032 tree t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
4033 build_int_cst (NULL_TREE, 2 * UNITS_PER_WORD - 1));
4034 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
4035 build_int_cst (NULL_TREE, -2 * UNITS_PER_WORD));
4036 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
4037 gimplify_and_add (t, pre_p);
4040 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4043 /* Return 1 if function return value returned in memory. Return 0 if it is
4047 ia64_return_in_memory (tree valtype, tree fntype ATTRIBUTE_UNUSED)
4049 enum machine_mode mode;
4050 enum machine_mode hfa_mode;
4051 HOST_WIDE_INT byte_size;
4053 mode = TYPE_MODE (valtype);
4054 byte_size = GET_MODE_SIZE (mode);
4055 if (mode == BLKmode)
4057 byte_size = int_size_in_bytes (valtype);
4062 /* Hfa's with up to 8 elements are returned in the FP argument registers. */
4064 hfa_mode = hfa_element_mode (valtype, 0);
4065 if (hfa_mode != VOIDmode)
4067 int hfa_size = GET_MODE_SIZE (hfa_mode);
4069 if (byte_size / hfa_size > MAX_ARGUMENT_SLOTS)
4074 else if (byte_size > UNITS_PER_WORD * MAX_INT_RETURN_SLOTS)
4080 /* Return rtx for register that holds the function return value. */
4083 ia64_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
4085 enum machine_mode mode;
4086 enum machine_mode hfa_mode;
4088 mode = TYPE_MODE (valtype);
4089 hfa_mode = hfa_element_mode (valtype, 0);
4091 if (hfa_mode != VOIDmode)
4099 hfa_size = GET_MODE_SIZE (hfa_mode);
4100 byte_size = ((mode == BLKmode)
4101 ? int_size_in_bytes (valtype) : GET_MODE_SIZE (mode));
4103 for (i = 0; offset < byte_size; i++)
4105 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4106 gen_rtx_REG (hfa_mode, FR_ARG_FIRST + i),
4110 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4112 else if (FLOAT_TYPE_P (valtype) && mode != TFmode && mode != TCmode)
4113 return gen_rtx_REG (mode, FR_ARG_FIRST);
4116 bool need_parallel = false;
4118 /* In big-endian mode, we need to manage the layout of aggregates
4119 in the registers so that we get the bits properly aligned in
4120 the highpart of the registers. */
4121 if (BYTES_BIG_ENDIAN
4122 && (mode == BLKmode || (valtype && AGGREGATE_TYPE_P (valtype))))
4123 need_parallel = true;
4125 /* Something like struct S { long double x; char a[0] } is not an
4126 HFA structure, and therefore doesn't go in fp registers. But
4127 the middle-end will give it XFmode anyway, and XFmode values
4128 don't normally fit in integer registers. So we need to smuggle
4129 the value inside a parallel. */
4130 else if (mode == XFmode || mode == XCmode)
4131 need_parallel = true;
4141 bytesize = int_size_in_bytes (valtype);
4142 /* An empty PARALLEL is invalid here, but the return value
4143 doesn't matter for empty structs. */
4145 return gen_rtx_REG (mode, GR_RET_FIRST);
4146 for (i = 0; offset < bytesize; i++)
4148 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4149 gen_rtx_REG (DImode,
4152 offset += UNITS_PER_WORD;
4154 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4157 return gen_rtx_REG (mode, GR_RET_FIRST);
4161 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4162 We need to emit DTP-relative relocations. */
4165 ia64_output_dwarf_dtprel (FILE *file, int size, rtx x)
4167 gcc_assert (size == 8);
4168 fputs ("\tdata8.ua\t@dtprel(", file);
4169 output_addr_const (file, x);
4173 /* Print a memory address as an operand to reference that memory location. */
4175 /* ??? Do we need this? It gets used only for 'a' operands. We could perhaps
4176 also call this from ia64_print_operand for memory addresses. */
4179 ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED,
4180 rtx address ATTRIBUTE_UNUSED)
4184 /* Print an operand to an assembler instruction.
4185 C Swap and print a comparison operator.
4186 D Print an FP comparison operator.
4187 E Print 32 - constant, for SImode shifts as extract.
4188 e Print 64 - constant, for DImode rotates.
4189 F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
4190 a floating point register emitted normally.
4191 I Invert a predicate register by adding 1.
4192 J Select the proper predicate register for a condition.
4193 j Select the inverse predicate register for a condition.
4194 O Append .acq for volatile load.
4195 P Postincrement of a MEM.
4196 Q Append .rel for volatile store.
4197 S Shift amount for shladd instruction.
4198 T Print an 8-bit sign extended number (K) as a 32-bit unsigned number
4199 for Intel assembler.
4200 U Print an 8-bit sign extended number (K) as a 64-bit unsigned number
4201 for Intel assembler.
4202 r Print register name, or constant 0 as r0. HP compatibility for
4204 v Print vector constant value as an 8-byte integer value. */
4207 ia64_print_operand (FILE * file, rtx x, int code)
4214 /* Handled below. */
4219 enum rtx_code c = swap_condition (GET_CODE (x));
4220 fputs (GET_RTX_NAME (c), file);
4225 switch (GET_CODE (x))
4237 str = GET_RTX_NAME (GET_CODE (x));
4244 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - INTVAL (x));
4248 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - INTVAL (x));
4252 if (x == CONST0_RTX (GET_MODE (x)))
4253 str = reg_names [FR_REG (0)];
4254 else if (x == CONST1_RTX (GET_MODE (x)))
4255 str = reg_names [FR_REG (1)];
4258 gcc_assert (GET_CODE (x) == REG);
4259 str = reg_names [REGNO (x)];
4265 fputs (reg_names [REGNO (x) + 1], file);
4271 unsigned int regno = REGNO (XEXP (x, 0));
4272 if (GET_CODE (x) == EQ)
4276 fputs (reg_names [regno], file);
4281 if (MEM_VOLATILE_P (x))
4282 fputs(".acq", file);
4287 HOST_WIDE_INT value;
4289 switch (GET_CODE (XEXP (x, 0)))
4295 x = XEXP (XEXP (XEXP (x, 0), 1), 1);
4296 if (GET_CODE (x) == CONST_INT)
4300 gcc_assert (GET_CODE (x) == REG);
4301 fprintf (file, ", %s", reg_names[REGNO (x)]);
4307 value = GET_MODE_SIZE (GET_MODE (x));
4311 value = - (HOST_WIDE_INT) GET_MODE_SIZE (GET_MODE (x));
4315 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC, value);
4320 if (MEM_VOLATILE_P (x))
4321 fputs(".rel", file);
4325 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4329 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
4331 fprintf (file, "0x%x", (int) INTVAL (x) & 0xffffffff);
4337 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
4339 const char *prefix = "0x";
4340 if (INTVAL (x) & 0x80000000)
4342 fprintf (file, "0xffffffff");
4345 fprintf (file, "%s%x", prefix, (int) INTVAL (x) & 0xffffffff);
4351 /* If this operand is the constant zero, write it as register zero.
4352 Any register, zero, or CONST_INT value is OK here. */
4353 if (GET_CODE (x) == REG)
4354 fputs (reg_names[REGNO (x)], file);
4355 else if (x == CONST0_RTX (GET_MODE (x)))
4357 else if (GET_CODE (x) == CONST_INT)
4358 output_addr_const (file, x);
4360 output_operand_lossage ("invalid %%r value");
4364 gcc_assert (GET_CODE (x) == CONST_VECTOR);
4365 x = simplify_subreg (DImode, x, GET_MODE (x), 0);
4372 /* For conditional branches, returns or calls, substitute
4373 sptk, dptk, dpnt, or spnt for %s. */
4374 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
4377 int pred_val = INTVAL (XEXP (x, 0));
4379 /* Guess top and bottom 10% statically predicted. */
4380 if (pred_val < REG_BR_PROB_BASE / 50)
4382 else if (pred_val < REG_BR_PROB_BASE / 2)
4384 else if (pred_val < REG_BR_PROB_BASE / 100 * 98)
4389 else if (GET_CODE (current_output_insn) == CALL_INSN)
4394 fputs (which, file);
4399 x = current_insn_predicate;
4402 unsigned int regno = REGNO (XEXP (x, 0));
4403 if (GET_CODE (x) == EQ)
4405 fprintf (file, "(%s) ", reg_names [regno]);
4410 output_operand_lossage ("ia64_print_operand: unknown code");
4414 switch (GET_CODE (x))
4416 /* This happens for the spill/restore instructions. */
4421 /* ... fall through ... */
4424 fputs (reg_names [REGNO (x)], file);
4429 rtx addr = XEXP (x, 0);
4430 if (GET_RTX_CLASS (GET_CODE (addr)) == RTX_AUTOINC)
4431 addr = XEXP (addr, 0);
4432 fprintf (file, "[%s]", reg_names [REGNO (addr)]);
4437 output_addr_const (file, x);
4444 /* Compute a (partial) cost for rtx X. Return true if the complete
4445 cost has been computed, and false if subexpressions should be
4446 scanned. In either case, *TOTAL contains the cost result. */
4447 /* ??? This is incomplete. */
4450 ia64_rtx_costs (rtx x, int code, int outer_code, int *total)
4458 *total = CONST_OK_FOR_J (INTVAL (x)) ? 0 : COSTS_N_INSNS (1);
4461 if (CONST_OK_FOR_I (INTVAL (x)))
4463 else if (CONST_OK_FOR_J (INTVAL (x)))
4466 *total = COSTS_N_INSNS (1);
4469 if (CONST_OK_FOR_K (INTVAL (x)) || CONST_OK_FOR_L (INTVAL (x)))
4472 *total = COSTS_N_INSNS (1);
4477 *total = COSTS_N_INSNS (1);
4483 *total = COSTS_N_INSNS (3);
4487 /* For multiplies wider than HImode, we have to go to the FPU,
4488 which normally involves copies. Plus there's the latency
4489 of the multiply itself, and the latency of the instructions to
4490 transfer integer regs to FP regs. */
4491 /* ??? Check for FP mode. */
4492 if (GET_MODE_SIZE (GET_MODE (x)) > 2)
4493 *total = COSTS_N_INSNS (10);
4495 *total = COSTS_N_INSNS (2);
4503 *total = COSTS_N_INSNS (1);
4510 /* We make divide expensive, so that divide-by-constant will be
4511 optimized to a multiply. */
4512 *total = COSTS_N_INSNS (60);
4520 /* Calculate the cost of moving data from a register in class FROM to
4521 one in class TO, using MODE. */
4524 ia64_register_move_cost (enum machine_mode mode, enum reg_class from,
4527 /* ADDL_REGS is the same as GR_REGS for movement purposes. */
4528 if (to == ADDL_REGS)
4530 if (from == ADDL_REGS)
4533 /* All costs are symmetric, so reduce cases by putting the
4534 lower number class as the destination. */
4537 enum reg_class tmp = to;
4538 to = from, from = tmp;
4541 /* Moving from FR<->GR in XFmode must be more expensive than 2,
4542 so that we get secondary memory reloads. Between FR_REGS,
4543 we have to make this at least as expensive as MEMORY_MOVE_COST
4544 to avoid spectacularly poor register class preferencing. */
4547 if (to != GR_REGS || from != GR_REGS)
4548 return MEMORY_MOVE_COST (mode, to, 0);
4556 /* Moving between PR registers takes two insns. */
4557 if (from == PR_REGS)
4559 /* Moving between PR and anything but GR is impossible. */
4560 if (from != GR_REGS)
4561 return MEMORY_MOVE_COST (mode, to, 0);
4565 /* Moving between BR and anything but GR is impossible. */
4566 if (from != GR_REGS && from != GR_AND_BR_REGS)
4567 return MEMORY_MOVE_COST (mode, to, 0);
4572 /* Moving between AR and anything but GR is impossible. */
4573 if (from != GR_REGS)
4574 return MEMORY_MOVE_COST (mode, to, 0);
4579 case GR_AND_FR_REGS:
4580 case GR_AND_BR_REGS:
4591 /* Implement PREFERRED_RELOAD_CLASS. Place additional restrictions on CLASS
4592 to use when copying X into that class. */
4595 ia64_preferred_reload_class (rtx x, enum reg_class class)
4600 /* Don't allow volatile mem reloads into floating point registers.
4601 This is defined to force reload to choose the r/m case instead
4602 of the f/f case when reloading (set (reg fX) (mem/v)). */
4603 if (MEM_P (x) && MEM_VOLATILE_P (x))
4606 /* Force all unrecognized constants into the constant pool. */
4624 /* This function returns the register class required for a secondary
4625 register when copying between one of the registers in CLASS, and X,
4626 using MODE. A return value of NO_REGS means that no secondary register
4630 ia64_secondary_reload_class (enum reg_class class,
4631 enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
4635 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
4636 regno = true_regnum (x);
4643 /* ??? BR<->BR register copies can happen due to a bad gcse/cse/global
4644 interaction. We end up with two pseudos with overlapping lifetimes
4645 both of which are equiv to the same constant, and both which need
4646 to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end
4647 changes depending on the path length, which means the qty_first_reg
4648 check in make_regs_eqv can give different answers at different times.
4649 At some point I'll probably need a reload_indi pattern to handle
4652 We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we
4653 wound up with a FP register from GR_AND_FR_REGS. Extend that to all
4654 non-general registers for good measure. */
4655 if (regno >= 0 && ! GENERAL_REGNO_P (regno))
4658 /* This is needed if a pseudo used as a call_operand gets spilled to a
4660 if (GET_CODE (x) == MEM)
4665 /* Need to go through general registers to get to other class regs. */
4666 if (regno >= 0 && ! (FR_REGNO_P (regno) || GENERAL_REGNO_P (regno)))
4669 /* This can happen when a paradoxical subreg is an operand to the
4671 /* ??? This shouldn't be necessary after instruction scheduling is
4672 enabled, because paradoxical subregs are not accepted by
4673 register_operand when INSN_SCHEDULING is defined. Or alternatively,
4674 stop the paradoxical subreg stupidity in the *_operand functions
4676 if (GET_CODE (x) == MEM
4677 && (GET_MODE (x) == SImode || GET_MODE (x) == HImode
4678 || GET_MODE (x) == QImode))
4681 /* This can happen because of the ior/and/etc patterns that accept FP
4682 registers as operands. If the third operand is a constant, then it
4683 needs to be reloaded into a FP register. */
4684 if (GET_CODE (x) == CONST_INT)
4687 /* This can happen because of register elimination in a muldi3 insn.
4688 E.g. `26107 * (unsigned long)&u'. */
4689 if (GET_CODE (x) == PLUS)
4694 /* ??? This happens if we cse/gcse a BImode value across a call,
4695 and the function has a nonlocal goto. This is because global
4696 does not allocate call crossing pseudos to hard registers when
4697 current_function_has_nonlocal_goto is true. This is relatively
4698 common for C++ programs that use exceptions. To reproduce,
4699 return NO_REGS and compile libstdc++. */
4700 if (GET_CODE (x) == MEM)
4703 /* This can happen when we take a BImode subreg of a DImode value,
4704 and that DImode value winds up in some non-GR register. */
4705 if (regno >= 0 && ! GENERAL_REGNO_P (regno) && ! PR_REGNO_P (regno))
4717 /* Emit text to declare externally defined variables and functions, because
4718 the Intel assembler does not support undefined externals. */
4721 ia64_asm_output_external (FILE *file, tree decl, const char *name)
4723 int save_referenced;
4725 /* GNU as does not need anything here, but the HP linker does need
4726 something for external functions. */
4730 || TREE_CODE (decl) != FUNCTION_DECL
4731 || strstr (name, "__builtin_") == name))
4734 /* ??? The Intel assembler creates a reference that needs to be satisfied by
4735 the linker when we do this, so we need to be careful not to do this for
4736 builtin functions which have no library equivalent. Unfortunately, we
4737 can't tell here whether or not a function will actually be called by
4738 expand_expr, so we pull in library functions even if we may not need
4740 if (! strcmp (name, "__builtin_next_arg")
4741 || ! strcmp (name, "alloca")
4742 || ! strcmp (name, "__builtin_constant_p")
4743 || ! strcmp (name, "__builtin_args_info"))
4747 ia64_hpux_add_extern_decl (decl);
4750 /* assemble_name will set TREE_SYMBOL_REFERENCED, so we must save and
4752 save_referenced = TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl));
4753 if (TREE_CODE (decl) == FUNCTION_DECL)
4754 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
4755 (*targetm.asm_out.globalize_label) (file, name);
4756 TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)) = save_referenced;
4760 /* Parse the -mfixed-range= option string. */
4763 fix_range (const char *const_str)
4766 char *str, *dash, *comma;
4768 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
4769 REG2 are either register names or register numbers. The effect
4770 of this option is to mark the registers in the range from REG1 to
4771 REG2 as ``fixed'' so they won't be used by the compiler. This is
4772 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
4774 i = strlen (const_str);
4775 str = (char *) alloca (i + 1);
4776 memcpy (str, const_str, i + 1);
4780 dash = strchr (str, '-');
4783 warning (0, "value of -mfixed-range must have form REG1-REG2");
4788 comma = strchr (dash + 1, ',');
4792 first = decode_reg_name (str);
4795 warning (0, "unknown register name: %s", str);
4799 last = decode_reg_name (dash + 1);
4802 warning (0, "unknown register name: %s", dash + 1);
4810 warning (0, "%s-%s is an empty range", str, dash + 1);
4814 for (i = first; i <= last; ++i)
4815 fixed_regs[i] = call_used_regs[i] = 1;
4825 /* Implement TARGET_HANDLE_OPTION. */
4828 ia64_handle_option (size_t code, const char *arg, int value)
4832 case OPT_mfixed_range_:
4836 case OPT_mtls_size_:
4837 if (value != 14 && value != 22 && value != 64)
4838 error ("bad value %<%s%> for -mtls-size= switch", arg);
4845 const char *name; /* processor name or nickname. */
4846 enum processor_type processor;
4848 const processor_alias_table[] =
4850 {"itanium", PROCESSOR_ITANIUM},
4851 {"itanium1", PROCESSOR_ITANIUM},
4852 {"merced", PROCESSOR_ITANIUM},
4853 {"itanium2", PROCESSOR_ITANIUM2},
4854 {"mckinley", PROCESSOR_ITANIUM2},
4856 int const pta_size = ARRAY_SIZE (processor_alias_table);
4859 for (i = 0; i < pta_size; i++)
4860 if (!strcmp (arg, processor_alias_table[i].name))
4862 ia64_tune = processor_alias_table[i].processor;
4866 error ("bad value %<%s%> for -mtune= switch", arg);
4875 /* Implement OVERRIDE_OPTIONS. */
4878 ia64_override_options (void)
4880 if (TARGET_AUTO_PIC)
4881 target_flags |= MASK_CONST_GP;
4883 if (TARGET_INLINE_SQRT == INL_MIN_LAT)
4885 warning (0, "not yet implemented: latency-optimized inline square root");
4886 TARGET_INLINE_SQRT = INL_MAX_THR;
4889 ia64_flag_schedule_insns2 = flag_schedule_insns_after_reload;
4890 flag_schedule_insns_after_reload = 0;
4892 ia64_section_threshold = g_switch_set ? g_switch_value : IA64_DEFAULT_GVALUE;
4894 init_machine_status = ia64_init_machine_status;
4897 static struct machine_function *
4898 ia64_init_machine_status (void)
4900 return ggc_alloc_cleared (sizeof (struct machine_function));
4903 static enum attr_itanium_class ia64_safe_itanium_class (rtx);
4904 static enum attr_type ia64_safe_type (rtx);
4906 static enum attr_itanium_class
4907 ia64_safe_itanium_class (rtx insn)
4909 if (recog_memoized (insn) >= 0)
4910 return get_attr_itanium_class (insn);
4912 return ITANIUM_CLASS_UNKNOWN;
4915 static enum attr_type
4916 ia64_safe_type (rtx insn)
4918 if (recog_memoized (insn) >= 0)
4919 return get_attr_type (insn);
4921 return TYPE_UNKNOWN;
4924 /* The following collection of routines emit instruction group stop bits as
4925 necessary to avoid dependencies. */
4927 /* Need to track some additional registers as far as serialization is
4928 concerned so we can properly handle br.call and br.ret. We could
4929 make these registers visible to gcc, but since these registers are
4930 never explicitly used in gcc generated code, it seems wasteful to
4931 do so (plus it would make the call and return patterns needlessly
4933 #define REG_RP (BR_REG (0))
4934 #define REG_AR_CFM (FIRST_PSEUDO_REGISTER + 1)
4935 /* This is used for volatile asms which may require a stop bit immediately
4936 before and after them. */
4937 #define REG_VOLATILE (FIRST_PSEUDO_REGISTER + 2)
4938 #define AR_UNAT_BIT_0 (FIRST_PSEUDO_REGISTER + 3)
4939 #define NUM_REGS (AR_UNAT_BIT_0 + 64)
4941 /* For each register, we keep track of how it has been written in the
4942 current instruction group.
4944 If a register is written unconditionally (no qualifying predicate),
4945 WRITE_COUNT is set to 2 and FIRST_PRED is ignored.
4947 If a register is written if its qualifying predicate P is true, we
4948 set WRITE_COUNT to 1 and FIRST_PRED to P. Later on, the same register
4949 may be written again by the complement of P (P^1) and when this happens,
4950 WRITE_COUNT gets set to 2.
4952 The result of this is that whenever an insn attempts to write a register
4953 whose WRITE_COUNT is two, we need to issue an insn group barrier first.
4955 If a predicate register is written by a floating-point insn, we set
4956 WRITTEN_BY_FP to true.
4958 If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND
4959 to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true. */
4961 struct reg_write_state
4963 unsigned int write_count : 2;
4964 unsigned int first_pred : 16;
4965 unsigned int written_by_fp : 1;
4966 unsigned int written_by_and : 1;
4967 unsigned int written_by_or : 1;
4970 /* Cumulative info for the current instruction group. */
4971 struct reg_write_state rws_sum[NUM_REGS];
4972 /* Info for the current instruction. This gets copied to rws_sum after a
4973 stop bit is emitted. */
4974 struct reg_write_state rws_insn[NUM_REGS];
4976 /* Indicates whether this is the first instruction after a stop bit,
4977 in which case we don't need another stop bit. Without this,
4978 ia64_variable_issue will die when scheduling an alloc. */
4979 static int first_instruction;
4981 /* Misc flags needed to compute RAW/WAW dependencies while we are traversing
4982 RTL for one instruction. */
4985 unsigned int is_write : 1; /* Is register being written? */
4986 unsigned int is_fp : 1; /* Is register used as part of an fp op? */
4987 unsigned int is_branch : 1; /* Is register used as part of a branch? */
4988 unsigned int is_and : 1; /* Is register used as part of and.orcm? */
4989 unsigned int is_or : 1; /* Is register used as part of or.andcm? */
4990 unsigned int is_sibcall : 1; /* Is this a sibling or normal call? */
4993 static void rws_update (struct reg_write_state *, int, struct reg_flags, int);
4994 static int rws_access_regno (int, struct reg_flags, int);
4995 static int rws_access_reg (rtx, struct reg_flags, int);
4996 static void update_set_flags (rtx, struct reg_flags *);
4997 static int set_src_needs_barrier (rtx, struct reg_flags, int);
4998 static int rtx_needs_barrier (rtx, struct reg_flags, int);
4999 static void init_insn_group_barriers (void);
5000 static int group_barrier_needed (rtx);
5001 static int safe_group_barrier_needed (rtx);
5003 /* Update *RWS for REGNO, which is being written by the current instruction,
5004 with predicate PRED, and associated register flags in FLAGS. */
5007 rws_update (struct reg_write_state *rws, int regno, struct reg_flags flags, int pred)
5010 rws[regno].write_count++;
5012 rws[regno].write_count = 2;
5013 rws[regno].written_by_fp |= flags.is_fp;
5014 /* ??? Not tracking and/or across differing predicates. */
5015 rws[regno].written_by_and = flags.is_and;
5016 rws[regno].written_by_or = flags.is_or;
5017 rws[regno].first_pred = pred;
5020 /* Handle an access to register REGNO of type FLAGS using predicate register
5021 PRED. Update rws_insn and rws_sum arrays. Return 1 if this access creates
5022 a dependency with an earlier instruction in the same group. */
5025 rws_access_regno (int regno, struct reg_flags flags, int pred)
5027 int need_barrier = 0;
5029 gcc_assert (regno < NUM_REGS);
5031 if (! PR_REGNO_P (regno))
5032 flags.is_and = flags.is_or = 0;
5038 /* One insn writes same reg multiple times? */
5039 gcc_assert (!rws_insn[regno].write_count);
5041 /* Update info for current instruction. */
5042 rws_update (rws_insn, regno, flags, pred);
5043 write_count = rws_sum[regno].write_count;
5045 switch (write_count)
5048 /* The register has not been written yet. */
5049 rws_update (rws_sum, regno, flags, pred);
5053 /* The register has been written via a predicate. If this is
5054 not a complementary predicate, then we need a barrier. */
5055 /* ??? This assumes that P and P+1 are always complementary
5056 predicates for P even. */
5057 if (flags.is_and && rws_sum[regno].written_by_and)
5059 else if (flags.is_or && rws_sum[regno].written_by_or)
5061 else if ((rws_sum[regno].first_pred ^ 1) != pred)
5063 rws_update (rws_sum, regno, flags, pred);
5067 /* The register has been unconditionally written already. We
5069 if (flags.is_and && rws_sum[regno].written_by_and)
5071 else if (flags.is_or && rws_sum[regno].written_by_or)
5075 rws_sum[regno].written_by_and = flags.is_and;
5076 rws_sum[regno].written_by_or = flags.is_or;
5085 if (flags.is_branch)
5087 /* Branches have several RAW exceptions that allow to avoid
5090 if (REGNO_REG_CLASS (regno) == BR_REGS || regno == AR_PFS_REGNUM)
5091 /* RAW dependencies on branch regs are permissible as long
5092 as the writer is a non-branch instruction. Since we
5093 never generate code that uses a branch register written
5094 by a branch instruction, handling this case is
5098 if (REGNO_REG_CLASS (regno) == PR_REGS
5099 && ! rws_sum[regno].written_by_fp)
5100 /* The predicates of a branch are available within the
5101 same insn group as long as the predicate was written by
5102 something other than a floating-point instruction. */
5106 if (flags.is_and && rws_sum[regno].written_by_and)
5108 if (flags.is_or && rws_sum[regno].written_by_or)
5111 switch (rws_sum[regno].write_count)
5114 /* The register has not been written yet. */
5118 /* The register has been written via a predicate. If this is
5119 not a complementary predicate, then we need a barrier. */
5120 /* ??? This assumes that P and P+1 are always complementary
5121 predicates for P even. */
5122 if ((rws_sum[regno].first_pred ^ 1) != pred)
5127 /* The register has been unconditionally written already. We
5137 return need_barrier;
5141 rws_access_reg (rtx reg, struct reg_flags flags, int pred)
5143 int regno = REGNO (reg);
5144 int n = HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg));
5147 return rws_access_regno (regno, flags, pred);
5150 int need_barrier = 0;
5152 need_barrier |= rws_access_regno (regno + n, flags, pred);
5153 return need_barrier;
5157 /* Examine X, which is a SET rtx, and update the flags, the predicate, and
5158 the condition, stored in *PFLAGS, *PPRED and *PCOND. */
5161 update_set_flags (rtx x, struct reg_flags *pflags)
5163 rtx src = SET_SRC (x);
5165 switch (GET_CODE (src))
5171 if (SET_DEST (x) == pc_rtx)
5172 /* X is a conditional branch. */
5176 /* X is a conditional move. */
5177 rtx cond = XEXP (src, 0);
5178 cond = XEXP (cond, 0);
5180 /* We always split conditional moves into COND_EXEC patterns, so the
5181 only pattern that can reach here is doloop_end_internal. We don't
5182 need to do anything special for this pattern. */
5183 gcc_assert (GET_CODE (cond) == REG && REGNO (cond) == AR_LC_REGNUM);
5188 if (COMPARISON_P (src)
5189 && GET_MODE_CLASS (GET_MODE (XEXP (src, 0))) == MODE_FLOAT)
5190 /* Set pflags->is_fp to 1 so that we know we're dealing
5191 with a floating point comparison when processing the
5192 destination of the SET. */
5195 /* Discover if this is a parallel comparison. We only handle
5196 and.orcm and or.andcm at present, since we must retain a
5197 strict inverse on the predicate pair. */
5198 else if (GET_CODE (src) == AND)
5200 else if (GET_CODE (src) == IOR)
5207 /* Subroutine of rtx_needs_barrier; this function determines whether the
5208 source of a given SET rtx found in X needs a barrier. FLAGS and PRED
5209 are as in rtx_needs_barrier. COND is an rtx that holds the condition
5213 set_src_needs_barrier (rtx x, struct reg_flags flags, int pred)
5215 int need_barrier = 0;
5217 rtx src = SET_SRC (x);
5219 if (GET_CODE (src) == CALL)
5220 /* We don't need to worry about the result registers that
5221 get written by subroutine call. */
5222 return rtx_needs_barrier (src, flags, pred);
5223 else if (SET_DEST (x) == pc_rtx)
5225 /* X is a conditional branch. */
5226 /* ??? This seems redundant, as the caller sets this bit for
5228 flags.is_branch = 1;
5229 return rtx_needs_barrier (src, flags, pred);
5232 need_barrier = rtx_needs_barrier (src, flags, pred);
5235 if (GET_CODE (dst) == ZERO_EXTRACT)
5237 need_barrier |= rtx_needs_barrier (XEXP (dst, 1), flags, pred);
5238 need_barrier |= rtx_needs_barrier (XEXP (dst, 2), flags, pred);
5239 dst = XEXP (dst, 0);
5241 return need_barrier;
5244 /* Handle an access to rtx X of type FLAGS using predicate register
5245 PRED. Return 1 if this access creates a dependency with an earlier
5246 instruction in the same group. */
5249 rtx_needs_barrier (rtx x, struct reg_flags flags, int pred)
5252 int is_complemented = 0;
5253 int need_barrier = 0;
5254 const char *format_ptr;
5255 struct reg_flags new_flags;
5263 switch (GET_CODE (x))
5266 update_set_flags (x, &new_flags);
5267 need_barrier = set_src_needs_barrier (x, new_flags, pred);
5268 if (GET_CODE (SET_SRC (x)) != CALL)
5270 new_flags.is_write = 1;
5271 need_barrier |= rtx_needs_barrier (SET_DEST (x), new_flags, pred);
5276 new_flags.is_write = 0;
5277 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
5279 /* Avoid multiple register writes, in case this is a pattern with
5280 multiple CALL rtx. This avoids a failure in rws_access_reg. */
5281 if (! flags.is_sibcall && ! rws_insn[REG_AR_CFM].write_count)
5283 new_flags.is_write = 1;
5284 need_barrier |= rws_access_regno (REG_RP, new_flags, pred);
5285 need_barrier |= rws_access_regno (AR_PFS_REGNUM, new_flags, pred);
5286 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
5291 /* X is a predicated instruction. */
5293 cond = COND_EXEC_TEST (x);
5295 need_barrier = rtx_needs_barrier (cond, flags, 0);
5297 if (GET_CODE (cond) == EQ)
5298 is_complemented = 1;
5299 cond = XEXP (cond, 0);
5300 gcc_assert (GET_CODE (cond) == REG
5301 && REGNO_REG_CLASS (REGNO (cond)) == PR_REGS);
5302 pred = REGNO (cond);
5303 if (is_complemented)
5306 need_barrier |= rtx_needs_barrier (COND_EXEC_CODE (x), flags, pred);
5307 return need_barrier;
5311 /* Clobber & use are for earlier compiler-phases only. */
5316 /* We always emit stop bits for traditional asms. We emit stop bits
5317 for volatile extended asms if TARGET_VOL_ASM_STOP is true. */
5318 if (GET_CODE (x) != ASM_OPERANDS
5319 || (MEM_VOLATILE_P (x) && TARGET_VOL_ASM_STOP))
5321 /* Avoid writing the register multiple times if we have multiple
5322 asm outputs. This avoids a failure in rws_access_reg. */
5323 if (! rws_insn[REG_VOLATILE].write_count)
5325 new_flags.is_write = 1;
5326 rws_access_regno (REG_VOLATILE, new_flags, pred);
5331 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
5332 We cannot just fall through here since then we would be confused
5333 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
5334 traditional asms unlike their normal usage. */
5336 for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; --i)
5337 if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x, i), flags, pred))
5342 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
5344 rtx pat = XVECEXP (x, 0, i);
5345 switch (GET_CODE (pat))
5348 update_set_flags (pat, &new_flags);
5349 need_barrier |= set_src_needs_barrier (pat, new_flags, pred);
5355 need_barrier |= rtx_needs_barrier (pat, flags, pred);
5366 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
5368 rtx pat = XVECEXP (x, 0, i);
5369 if (GET_CODE (pat) == SET)
5371 if (GET_CODE (SET_SRC (pat)) != CALL)
5373 new_flags.is_write = 1;
5374 need_barrier |= rtx_needs_barrier (SET_DEST (pat), new_flags,
5378 else if (GET_CODE (pat) == CLOBBER || GET_CODE (pat) == RETURN)
5379 need_barrier |= rtx_needs_barrier (pat, flags, pred);
5384 need_barrier |= rtx_needs_barrier (SUBREG_REG (x), flags, pred);
5387 if (REGNO (x) == AR_UNAT_REGNUM)
5389 for (i = 0; i < 64; ++i)
5390 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + i, flags, pred);
5393 need_barrier = rws_access_reg (x, flags, pred);
5397 /* Find the regs used in memory address computation. */
5398 new_flags.is_write = 0;
5399 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
5402 case CONST_INT: case CONST_DOUBLE: case CONST_VECTOR:
5403 case SYMBOL_REF: case LABEL_REF: case CONST:
5406 /* Operators with side-effects. */
5407 case POST_INC: case POST_DEC:
5408 gcc_assert (GET_CODE (XEXP (x, 0)) == REG);
5410 new_flags.is_write = 0;
5411 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
5412 new_flags.is_write = 1;
5413 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
5417 gcc_assert (GET_CODE (XEXP (x, 0)) == REG);
5419 new_flags.is_write = 0;
5420 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
5421 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
5422 new_flags.is_write = 1;
5423 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
5426 /* Handle common unary and binary ops for efficiency. */
5427 case COMPARE: case PLUS: case MINUS: case MULT: case DIV:
5428 case MOD: case UDIV: case UMOD: case AND: case IOR:
5429 case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT:
5430 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
5431 case NE: case EQ: case GE: case GT: case LE:
5432 case LT: case GEU: case GTU: case LEU: case LTU:
5433 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
5434 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
5437 case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND:
5438 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT:
5439 case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS:
5440 case SQRT: case FFS: case POPCOUNT:
5441 need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred);
5445 /* VEC_SELECT's second argument is a PARALLEL with integers that
5446 describe the elements selected. On ia64, those integers are
5447 always constants. Avoid walking the PARALLEL so that we don't
5448 get confused with "normal" parallels and then die. */
5449 need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred);
5453 switch (XINT (x, 1))
5455 case UNSPEC_LTOFF_DTPMOD:
5456 case UNSPEC_LTOFF_DTPREL:
5458 case UNSPEC_LTOFF_TPREL:
5460 case UNSPEC_PRED_REL_MUTEX:
5461 case UNSPEC_PIC_CALL:
5463 case UNSPEC_FETCHADD_ACQ:
5464 case UNSPEC_BSP_VALUE:
5465 case UNSPEC_FLUSHRS:
5466 case UNSPEC_BUNDLE_SELECTOR:
5469 case UNSPEC_GR_SPILL:
5470 case UNSPEC_GR_RESTORE:
5472 HOST_WIDE_INT offset = INTVAL (XVECEXP (x, 0, 1));
5473 HOST_WIDE_INT bit = (offset >> 3) & 63;
5475 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
5476 new_flags.is_write = (XINT (x, 1) == UNSPEC_GR_SPILL);
5477 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + bit,
5482 case UNSPEC_FR_SPILL:
5483 case UNSPEC_FR_RESTORE:
5484 case UNSPEC_GETF_EXP:
5485 case UNSPEC_SETF_EXP:
5487 case UNSPEC_FR_SQRT_RECIP_APPROX:
5488 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
5491 case UNSPEC_FR_RECIP_APPROX:
5493 case UNSPEC_COPYSIGN:
5494 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
5495 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
5498 case UNSPEC_CMPXCHG_ACQ:
5499 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
5500 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 2), flags, pred);
5508 case UNSPEC_VOLATILE:
5509 switch (XINT (x, 1))
5512 /* Alloc must always be the first instruction of a group.
5513 We force this by always returning true. */
5514 /* ??? We might get better scheduling if we explicitly check for
5515 input/local/output register dependencies, and modify the
5516 scheduler so that alloc is always reordered to the start of
5517 the current group. We could then eliminate all of the
5518 first_instruction code. */
5519 rws_access_regno (AR_PFS_REGNUM, flags, pred);
5521 new_flags.is_write = 1;
5522 rws_access_regno (REG_AR_CFM, new_flags, pred);
5525 case UNSPECV_SET_BSP:
5529 case UNSPECV_BLOCKAGE:
5530 case UNSPECV_INSN_GROUP_BARRIER:
5532 case UNSPECV_PSAC_ALL:
5533 case UNSPECV_PSAC_NORMAL:
5542 new_flags.is_write = 0;
5543 need_barrier = rws_access_regno (REG_RP, flags, pred);
5544 need_barrier |= rws_access_regno (AR_PFS_REGNUM, flags, pred);
5546 new_flags.is_write = 1;
5547 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
5548 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
5552 format_ptr = GET_RTX_FORMAT (GET_CODE (x));
5553 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5554 switch (format_ptr[i])
5556 case '0': /* unused field */
5557 case 'i': /* integer */
5558 case 'n': /* note */
5559 case 'w': /* wide integer */
5560 case 's': /* pointer to string */
5561 case 'S': /* optional pointer to string */
5565 if (rtx_needs_barrier (XEXP (x, i), flags, pred))
5570 for (j = XVECLEN (x, i) - 1; j >= 0; --j)
5571 if (rtx_needs_barrier (XVECEXP (x, i, j), flags, pred))
5580 return need_barrier;
5583 /* Clear out the state for group_barrier_needed at the start of a
5584 sequence of insns. */
5587 init_insn_group_barriers (void)
5589 memset (rws_sum, 0, sizeof (rws_sum));
5590 first_instruction = 1;
5593 /* Given the current state, determine whether a group barrier (a stop bit) is
5594 necessary before INSN. Return nonzero if so. This modifies the state to
5595 include the effects of INSN as a side-effect. */
5598 group_barrier_needed (rtx insn)
5601 int need_barrier = 0;
5602 struct reg_flags flags;
5604 memset (&flags, 0, sizeof (flags));
5605 switch (GET_CODE (insn))
5611 /* A barrier doesn't imply an instruction group boundary. */
5615 memset (rws_insn, 0, sizeof (rws_insn));
5619 flags.is_branch = 1;
5620 flags.is_sibcall = SIBLING_CALL_P (insn);
5621 memset (rws_insn, 0, sizeof (rws_insn));
5623 /* Don't bundle a call following another call. */
5624 if ((pat = prev_active_insn (insn))
5625 && GET_CODE (pat) == CALL_INSN)
5631 need_barrier = rtx_needs_barrier (PATTERN (insn), flags, 0);
5635 flags.is_branch = 1;
5637 /* Don't bundle a jump following a call. */
5638 if ((pat = prev_active_insn (insn))
5639 && GET_CODE (pat) == CALL_INSN)
5647 if (GET_CODE (PATTERN (insn)) == USE
5648 || GET_CODE (PATTERN (insn)) == CLOBBER)
5649 /* Don't care about USE and CLOBBER "insns"---those are used to
5650 indicate to the optimizer that it shouldn't get rid of
5651 certain operations. */
5654 pat = PATTERN (insn);
5656 /* Ug. Hack hacks hacked elsewhere. */
5657 switch (recog_memoized (insn))
5659 /* We play dependency tricks with the epilogue in order
5660 to get proper schedules. Undo this for dv analysis. */
5661 case CODE_FOR_epilogue_deallocate_stack:
5662 case CODE_FOR_prologue_allocate_stack:
5663 pat = XVECEXP (pat, 0, 0);
5666 /* The pattern we use for br.cloop confuses the code above.
5667 The second element of the vector is representative. */
5668 case CODE_FOR_doloop_end_internal:
5669 pat = XVECEXP (pat, 0, 1);
5672 /* Doesn't generate code. */
5673 case CODE_FOR_pred_rel_mutex:
5674 case CODE_FOR_prologue_use:
5681 memset (rws_insn, 0, sizeof (rws_insn));
5682 need_barrier = rtx_needs_barrier (pat, flags, 0);
5684 /* Check to see if the previous instruction was a volatile
5687 need_barrier = rws_access_regno (REG_VOLATILE, flags, 0);
5694 if (first_instruction && INSN_P (insn)
5695 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
5696 && GET_CODE (PATTERN (insn)) != USE
5697 && GET_CODE (PATTERN (insn)) != CLOBBER)
5700 first_instruction = 0;
5703 return need_barrier;
5706 /* Like group_barrier_needed, but do not clobber the current state. */
5709 safe_group_barrier_needed (rtx insn)
5711 struct reg_write_state rws_saved[NUM_REGS];
5712 int saved_first_instruction;
5715 memcpy (rws_saved, rws_sum, NUM_REGS * sizeof *rws_saved);
5716 saved_first_instruction = first_instruction;
5718 t = group_barrier_needed (insn);
5720 memcpy (rws_sum, rws_saved, NUM_REGS * sizeof *rws_saved);
5721 first_instruction = saved_first_instruction;
5726 /* Scan the current function and insert stop bits as necessary to
5727 eliminate dependencies. This function assumes that a final
5728 instruction scheduling pass has been run which has already
5729 inserted most of the necessary stop bits. This function only
5730 inserts new ones at basic block boundaries, since these are
5731 invisible to the scheduler. */
5734 emit_insn_group_barriers (FILE *dump)
5738 int insns_since_last_label = 0;
5740 init_insn_group_barriers ();
5742 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5744 if (GET_CODE (insn) == CODE_LABEL)
5746 if (insns_since_last_label)
5748 insns_since_last_label = 0;
5750 else if (GET_CODE (insn) == NOTE
5751 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_BASIC_BLOCK)
5753 if (insns_since_last_label)
5755 insns_since_last_label = 0;
5757 else if (GET_CODE (insn) == INSN
5758 && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
5759 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
5761 init_insn_group_barriers ();
5764 else if (INSN_P (insn))
5766 insns_since_last_label = 1;
5768 if (group_barrier_needed (insn))
5773 fprintf (dump, "Emitting stop before label %d\n",
5774 INSN_UID (last_label));
5775 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), last_label);
5778 init_insn_group_barriers ();
5786 /* Like emit_insn_group_barriers, but run if no final scheduling pass was run.
5787 This function has to emit all necessary group barriers. */
5790 emit_all_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED)
5794 init_insn_group_barriers ();
5796 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5798 if (GET_CODE (insn) == BARRIER)
5800 rtx last = prev_active_insn (insn);
5804 if (GET_CODE (last) == JUMP_INSN
5805 && GET_CODE (PATTERN (last)) == ADDR_DIFF_VEC)
5806 last = prev_active_insn (last);
5807 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
5808 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
5810 init_insn_group_barriers ();
5812 else if (INSN_P (insn))
5814 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
5815 init_insn_group_barriers ();
5816 else if (group_barrier_needed (insn))
5818 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn);
5819 init_insn_group_barriers ();
5820 group_barrier_needed (insn);
5828 /* Instruction scheduling support. */
5830 #define NR_BUNDLES 10
5832 /* A list of names of all available bundles. */
5834 static const char *bundle_name [NR_BUNDLES] =
5840 #if NR_BUNDLES == 10
5850 /* Nonzero if we should insert stop bits into the schedule. */
5852 int ia64_final_schedule = 0;
5854 /* Codes of the corresponding queried units: */
5856 static int _0mii_, _0mmi_, _0mfi_, _0mmf_;
5857 static int _0bbb_, _0mbb_, _0mib_, _0mmb_, _0mfb_, _0mlx_;
5859 static int _1mii_, _1mmi_, _1mfi_, _1mmf_;
5860 static int _1bbb_, _1mbb_, _1mib_, _1mmb_, _1mfb_, _1mlx_;
5862 static int pos_1, pos_2, pos_3, pos_4, pos_5, pos_6;
5864 /* The following variable value is an insn group barrier. */
5866 static rtx dfa_stop_insn;
5868 /* The following variable value is the last issued insn. */
5870 static rtx last_scheduled_insn;
5872 /* The following variable value is size of the DFA state. */
5874 static size_t dfa_state_size;
5876 /* The following variable value is pointer to a DFA state used as
5877 temporary variable. */
5879 static state_t temp_dfa_state = NULL;
5881 /* The following variable value is DFA state after issuing the last
5884 static state_t prev_cycle_state = NULL;
5886 /* The following array element values are TRUE if the corresponding
5887 insn requires to add stop bits before it. */
5889 static char *stops_p;
5891 /* The following variable is used to set up the mentioned above array. */
5893 static int stop_before_p = 0;
5895 /* The following variable value is length of the arrays `clocks' and
5898 static int clocks_length;
5900 /* The following array element values are cycles on which the
5901 corresponding insn will be issued. The array is used only for
5906 /* The following array element values are numbers of cycles should be
5907 added to improve insn scheduling for MM_insns for Itanium1. */
5909 static int *add_cycles;
5911 static rtx ia64_single_set (rtx);
5912 static void ia64_emit_insn_before (rtx, rtx);
5914 /* Map a bundle number to its pseudo-op. */
5917 get_bundle_name (int b)
5919 return bundle_name[b];
5923 /* Return the maximum number of instructions a cpu can issue. */
5926 ia64_issue_rate (void)
5931 /* Helper function - like single_set, but look inside COND_EXEC. */
5934 ia64_single_set (rtx insn)
5936 rtx x = PATTERN (insn), ret;
5937 if (GET_CODE (x) == COND_EXEC)
5938 x = COND_EXEC_CODE (x);
5939 if (GET_CODE (x) == SET)
5942 /* Special case here prologue_allocate_stack and epilogue_deallocate_stack.
5943 Although they are not classical single set, the second set is there just
5944 to protect it from moving past FP-relative stack accesses. */
5945 switch (recog_memoized (insn))
5947 case CODE_FOR_prologue_allocate_stack:
5948 case CODE_FOR_epilogue_deallocate_stack:
5949 ret = XVECEXP (x, 0, 0);
5953 ret = single_set_2 (insn, x);
5960 /* Adjust the cost of a scheduling dependency. Return the new cost of
5961 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5964 ia64_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
5966 enum attr_itanium_class dep_class;
5967 enum attr_itanium_class insn_class;
5969 if (REG_NOTE_KIND (link) != REG_DEP_OUTPUT)
5972 insn_class = ia64_safe_itanium_class (insn);
5973 dep_class = ia64_safe_itanium_class (dep_insn);
5974 if (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF
5975 || insn_class == ITANIUM_CLASS_ST || insn_class == ITANIUM_CLASS_STF)
5981 /* Like emit_insn_before, but skip cycle_display notes.
5982 ??? When cycle display notes are implemented, update this. */
5985 ia64_emit_insn_before (rtx insn, rtx before)
5987 emit_insn_before (insn, before);
5990 /* The following function marks insns who produce addresses for load
5991 and store insns. Such insns will be placed into M slots because it
5992 decrease latency time for Itanium1 (see function
5993 `ia64_produce_address_p' and the DFA descriptions). */
5996 ia64_dependencies_evaluation_hook (rtx head, rtx tail)
5998 rtx insn, link, next, next_tail;
6000 /* Before reload, which_alternative is not set, which means that
6001 ia64_safe_itanium_class will produce wrong results for (at least)
6002 move instructions. */
6003 if (!reload_completed)
6006 next_tail = NEXT_INSN (tail);
6007 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
6010 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
6012 && ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IALU)
6014 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
6016 if (REG_NOTE_KIND (link) != REG_DEP_TRUE)
6018 next = XEXP (link, 0);
6019 if ((ia64_safe_itanium_class (next) == ITANIUM_CLASS_ST
6020 || ia64_safe_itanium_class (next) == ITANIUM_CLASS_STF)
6021 && ia64_st_address_bypass_p (insn, next))
6023 else if ((ia64_safe_itanium_class (next) == ITANIUM_CLASS_LD
6024 || ia64_safe_itanium_class (next)
6025 == ITANIUM_CLASS_FLD)
6026 && ia64_ld_address_bypass_p (insn, next))
6029 insn->call = link != 0;
6033 /* We're beginning a new block. Initialize data structures as necessary. */
6036 ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED,
6037 int sched_verbose ATTRIBUTE_UNUSED,
6038 int max_ready ATTRIBUTE_UNUSED)
6040 #ifdef ENABLE_CHECKING
6043 if (reload_completed)
6044 for (insn = NEXT_INSN (current_sched_info->prev_head);
6045 insn != current_sched_info->next_tail;
6046 insn = NEXT_INSN (insn))
6047 gcc_assert (!SCHED_GROUP_P (insn));
6049 last_scheduled_insn = NULL_RTX;
6050 init_insn_group_barriers ();
6053 /* We are about to being issuing insns for this clock cycle.
6054 Override the default sort algorithm to better slot instructions. */
6057 ia64_dfa_sched_reorder (FILE *dump, int sched_verbose, rtx *ready,
6058 int *pn_ready, int clock_var ATTRIBUTE_UNUSED,
6062 int n_ready = *pn_ready;
6063 rtx *e_ready = ready + n_ready;
6067 fprintf (dump, "// ia64_dfa_sched_reorder (type %d):\n", reorder_type);
6069 if (reorder_type == 0)
6071 /* First, move all USEs, CLOBBERs and other crud out of the way. */
6073 for (insnp = ready; insnp < e_ready; insnp++)
6074 if (insnp < e_ready)
6077 enum attr_type t = ia64_safe_type (insn);
6078 if (t == TYPE_UNKNOWN)
6080 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
6081 || asm_noperands (PATTERN (insn)) >= 0)
6083 rtx lowest = ready[n_asms];
6084 ready[n_asms] = insn;
6090 rtx highest = ready[n_ready - 1];
6091 ready[n_ready - 1] = insn;
6098 if (n_asms < n_ready)
6100 /* Some normal insns to process. Skip the asms. */
6104 else if (n_ready > 0)
6108 if (ia64_final_schedule)
6111 int nr_need_stop = 0;
6113 for (insnp = ready; insnp < e_ready; insnp++)
6114 if (safe_group_barrier_needed (*insnp))
6117 if (reorder_type == 1 && n_ready == nr_need_stop)
6119 if (reorder_type == 0)
6122 /* Move down everything that needs a stop bit, preserving
6124 while (insnp-- > ready + deleted)
6125 while (insnp >= ready + deleted)
6128 if (! safe_group_barrier_needed (insn))
6130 memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx));
6141 /* We are about to being issuing insns for this clock cycle. Override
6142 the default sort algorithm to better slot instructions. */
6145 ia64_sched_reorder (FILE *dump, int sched_verbose, rtx *ready, int *pn_ready,
6148 return ia64_dfa_sched_reorder (dump, sched_verbose, ready,
6149 pn_ready, clock_var, 0);
6152 /* Like ia64_sched_reorder, but called after issuing each insn.
6153 Override the default sort algorithm to better slot instructions. */
6156 ia64_sched_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
6157 int sched_verbose ATTRIBUTE_UNUSED, rtx *ready,
6158 int *pn_ready, int clock_var)
6160 if (ia64_tune == PROCESSOR_ITANIUM && reload_completed && last_scheduled_insn)
6161 clocks [INSN_UID (last_scheduled_insn)] = clock_var;
6162 return ia64_dfa_sched_reorder (dump, sched_verbose, ready, pn_ready,
6166 /* We are about to issue INSN. Return the number of insns left on the
6167 ready queue that can be issued this cycle. */
6170 ia64_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
6171 int sched_verbose ATTRIBUTE_UNUSED,
6172 rtx insn ATTRIBUTE_UNUSED,
6173 int can_issue_more ATTRIBUTE_UNUSED)
6175 last_scheduled_insn = insn;
6176 memcpy (prev_cycle_state, curr_state, dfa_state_size);
6177 if (reload_completed)
6179 int needed = group_barrier_needed (insn);
6181 gcc_assert (!needed);
6182 if (GET_CODE (insn) == CALL_INSN)
6183 init_insn_group_barriers ();
6184 stops_p [INSN_UID (insn)] = stop_before_p;
6190 /* We are choosing insn from the ready queue. Return nonzero if INSN
6194 ia64_first_cycle_multipass_dfa_lookahead_guard (rtx insn)
6196 gcc_assert (insn && INSN_P (insn));
6197 return (!reload_completed
6198 || !safe_group_barrier_needed (insn));
6201 /* The following variable value is pseudo-insn used by the DFA insn
6202 scheduler to change the DFA state when the simulated clock is
6205 static rtx dfa_pre_cycle_insn;
6207 /* We are about to being issuing INSN. Return nonzero if we cannot
6208 issue it on given cycle CLOCK and return zero if we should not sort
6209 the ready queue on the next clock start. */
6212 ia64_dfa_new_cycle (FILE *dump, int verbose, rtx insn, int last_clock,
6213 int clock, int *sort_p)
6215 int setup_clocks_p = FALSE;
6217 gcc_assert (insn && INSN_P (insn));
6218 if ((reload_completed && safe_group_barrier_needed (insn))
6219 || (last_scheduled_insn
6220 && (GET_CODE (last_scheduled_insn) == CALL_INSN
6221 || GET_CODE (PATTERN (last_scheduled_insn)) == ASM_INPUT
6222 || asm_noperands (PATTERN (last_scheduled_insn)) >= 0)))
6224 init_insn_group_barriers ();
6225 if (verbose && dump)
6226 fprintf (dump, "// Stop should be before %d%s\n", INSN_UID (insn),
6227 last_clock == clock ? " + cycle advance" : "");
6229 if (last_clock == clock)
6231 state_transition (curr_state, dfa_stop_insn);
6232 if (TARGET_EARLY_STOP_BITS)
6233 *sort_p = (last_scheduled_insn == NULL_RTX
6234 || GET_CODE (last_scheduled_insn) != CALL_INSN);
6239 else if (reload_completed)
6240 setup_clocks_p = TRUE;
6241 if (GET_CODE (PATTERN (last_scheduled_insn)) == ASM_INPUT
6242 || asm_noperands (PATTERN (last_scheduled_insn)) >= 0)
6243 state_reset (curr_state);
6246 memcpy (curr_state, prev_cycle_state, dfa_state_size);
6247 state_transition (curr_state, dfa_stop_insn);
6248 state_transition (curr_state, dfa_pre_cycle_insn);
6249 state_transition (curr_state, NULL);
6252 else if (reload_completed)
6253 setup_clocks_p = TRUE;
6254 if (setup_clocks_p && ia64_tune == PROCESSOR_ITANIUM
6255 && GET_CODE (PATTERN (insn)) != ASM_INPUT
6256 && asm_noperands (PATTERN (insn)) < 0)
6258 enum attr_itanium_class c = ia64_safe_itanium_class (insn);
6260 if (c != ITANIUM_CLASS_MMMUL && c != ITANIUM_CLASS_MMSHF)
6265 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
6266 if (REG_NOTE_KIND (link) == 0)
6268 enum attr_itanium_class dep_class;
6269 rtx dep_insn = XEXP (link, 0);
6271 dep_class = ia64_safe_itanium_class (dep_insn);
6272 if ((dep_class == ITANIUM_CLASS_MMMUL
6273 || dep_class == ITANIUM_CLASS_MMSHF)
6274 && last_clock - clocks [INSN_UID (dep_insn)] < 4
6276 || last_clock - clocks [INSN_UID (dep_insn)] < d))
6277 d = last_clock - clocks [INSN_UID (dep_insn)];
6280 add_cycles [INSN_UID (insn)] = 3 - d;
6288 /* The following page contains abstract data `bundle states' which are
6289 used for bundling insns (inserting nops and template generation). */
6291 /* The following describes state of insn bundling. */
6295 /* Unique bundle state number to identify them in the debugging
6298 rtx insn; /* corresponding insn, NULL for the 1st and the last state */
6299 /* number nops before and after the insn */
6300 short before_nops_num, after_nops_num;
6301 int insn_num; /* insn number (0 - for initial state, 1 - for the 1st
6303 int cost; /* cost of the state in cycles */
6304 int accumulated_insns_num; /* number of all previous insns including
6305 nops. L is considered as 2 insns */
6306 int branch_deviation; /* deviation of previous branches from 3rd slots */
6307 struct bundle_state *next; /* next state with the same insn_num */
6308 struct bundle_state *originator; /* originator (previous insn state) */
6309 /* All bundle states are in the following chain. */
6310 struct bundle_state *allocated_states_chain;
6311 /* The DFA State after issuing the insn and the nops. */
6315 /* The following is map insn number to the corresponding bundle state. */
6317 static struct bundle_state **index_to_bundle_states;
6319 /* The unique number of next bundle state. */
6321 static int bundle_states_num;
6323 /* All allocated bundle states are in the following chain. */
6325 static struct bundle_state *allocated_bundle_states_chain;
6327 /* All allocated but not used bundle states are in the following
6330 static struct bundle_state *free_bundle_state_chain;
6333 /* The following function returns a free bundle state. */
6335 static struct bundle_state *
6336 get_free_bundle_state (void)
6338 struct bundle_state *result;
6340 if (free_bundle_state_chain != NULL)
6342 result = free_bundle_state_chain;
6343 free_bundle_state_chain = result->next;
6347 result = xmalloc (sizeof (struct bundle_state));
6348 result->dfa_state = xmalloc (dfa_state_size);
6349 result->allocated_states_chain = allocated_bundle_states_chain;
6350 allocated_bundle_states_chain = result;
6352 result->unique_num = bundle_states_num++;
6357 /* The following function frees given bundle state. */
6360 free_bundle_state (struct bundle_state *state)
6362 state->next = free_bundle_state_chain;
6363 free_bundle_state_chain = state;
6366 /* Start work with abstract data `bundle states'. */
6369 initiate_bundle_states (void)
6371 bundle_states_num = 0;
6372 free_bundle_state_chain = NULL;
6373 allocated_bundle_states_chain = NULL;
6376 /* Finish work with abstract data `bundle states'. */
6379 finish_bundle_states (void)
6381 struct bundle_state *curr_state, *next_state;
6383 for (curr_state = allocated_bundle_states_chain;
6385 curr_state = next_state)
6387 next_state = curr_state->allocated_states_chain;
6388 free (curr_state->dfa_state);
6393 /* Hash table of the bundle states. The key is dfa_state and insn_num
6394 of the bundle states. */
6396 static htab_t bundle_state_table;
6398 /* The function returns hash of BUNDLE_STATE. */
6401 bundle_state_hash (const void *bundle_state)
6403 const struct bundle_state *state = (struct bundle_state *) bundle_state;
6406 for (result = i = 0; i < dfa_state_size; i++)
6407 result += (((unsigned char *) state->dfa_state) [i]
6408 << ((i % CHAR_BIT) * 3 + CHAR_BIT));
6409 return result + state->insn_num;
6412 /* The function returns nonzero if the bundle state keys are equal. */
6415 bundle_state_eq_p (const void *bundle_state_1, const void *bundle_state_2)
6417 const struct bundle_state * state1 = (struct bundle_state *) bundle_state_1;
6418 const struct bundle_state * state2 = (struct bundle_state *) bundle_state_2;
6420 return (state1->insn_num == state2->insn_num
6421 && memcmp (state1->dfa_state, state2->dfa_state,
6422 dfa_state_size) == 0);
6425 /* The function inserts the BUNDLE_STATE into the hash table. The
6426 function returns nonzero if the bundle has been inserted into the
6427 table. The table contains the best bundle state with given key. */
6430 insert_bundle_state (struct bundle_state *bundle_state)
6434 entry_ptr = htab_find_slot (bundle_state_table, bundle_state, 1);
6435 if (*entry_ptr == NULL)
6437 bundle_state->next = index_to_bundle_states [bundle_state->insn_num];
6438 index_to_bundle_states [bundle_state->insn_num] = bundle_state;
6439 *entry_ptr = (void *) bundle_state;
6442 else if (bundle_state->cost < ((struct bundle_state *) *entry_ptr)->cost
6443 || (bundle_state->cost == ((struct bundle_state *) *entry_ptr)->cost
6444 && (((struct bundle_state *)*entry_ptr)->accumulated_insns_num
6445 > bundle_state->accumulated_insns_num
6446 || (((struct bundle_state *)
6447 *entry_ptr)->accumulated_insns_num
6448 == bundle_state->accumulated_insns_num
6449 && ((struct bundle_state *)
6450 *entry_ptr)->branch_deviation
6451 > bundle_state->branch_deviation))))
6454 struct bundle_state temp;
6456 temp = *(struct bundle_state *) *entry_ptr;
6457 *(struct bundle_state *) *entry_ptr = *bundle_state;
6458 ((struct bundle_state *) *entry_ptr)->next = temp.next;
6459 *bundle_state = temp;
6464 /* Start work with the hash table. */
6467 initiate_bundle_state_table (void)
6469 bundle_state_table = htab_create (50, bundle_state_hash, bundle_state_eq_p,
6473 /* Finish work with the hash table. */
6476 finish_bundle_state_table (void)
6478 htab_delete (bundle_state_table);
6483 /* The following variable is a insn `nop' used to check bundle states
6484 with different number of inserted nops. */
6486 static rtx ia64_nop;
6488 /* The following function tries to issue NOPS_NUM nops for the current
6489 state without advancing processor cycle. If it failed, the
6490 function returns FALSE and frees the current state. */
6493 try_issue_nops (struct bundle_state *curr_state, int nops_num)
6497 for (i = 0; i < nops_num; i++)
6498 if (state_transition (curr_state->dfa_state, ia64_nop) >= 0)
6500 free_bundle_state (curr_state);
6506 /* The following function tries to issue INSN for the current
6507 state without advancing processor cycle. If it failed, the
6508 function returns FALSE and frees the current state. */
6511 try_issue_insn (struct bundle_state *curr_state, rtx insn)
6513 if (insn && state_transition (curr_state->dfa_state, insn) >= 0)
6515 free_bundle_state (curr_state);
6521 /* The following function tries to issue BEFORE_NOPS_NUM nops and INSN
6522 starting with ORIGINATOR without advancing processor cycle. If
6523 TRY_BUNDLE_END_P is TRUE, the function also/only (if
6524 ONLY_BUNDLE_END_P is TRUE) tries to issue nops to fill all bundle.
6525 If it was successful, the function creates new bundle state and
6526 insert into the hash table and into `index_to_bundle_states'. */
6529 issue_nops_and_insn (struct bundle_state *originator, int before_nops_num,
6530 rtx insn, int try_bundle_end_p, int only_bundle_end_p)
6532 struct bundle_state *curr_state;
6534 curr_state = get_free_bundle_state ();
6535 memcpy (curr_state->dfa_state, originator->dfa_state, dfa_state_size);
6536 curr_state->insn = insn;
6537 curr_state->insn_num = originator->insn_num + 1;
6538 curr_state->cost = originator->cost;
6539 curr_state->originator = originator;
6540 curr_state->before_nops_num = before_nops_num;
6541 curr_state->after_nops_num = 0;
6542 curr_state->accumulated_insns_num
6543 = originator->accumulated_insns_num + before_nops_num;
6544 curr_state->branch_deviation = originator->branch_deviation;
6546 if (INSN_CODE (insn) == CODE_FOR_insn_group_barrier)
6548 gcc_assert (GET_MODE (insn) != TImode);
6549 if (!try_issue_nops (curr_state, before_nops_num))
6551 if (!try_issue_insn (curr_state, insn))
6553 memcpy (temp_dfa_state, curr_state->dfa_state, dfa_state_size);
6554 if (state_transition (temp_dfa_state, dfa_pre_cycle_insn) >= 0
6555 && curr_state->accumulated_insns_num % 3 != 0)
6557 free_bundle_state (curr_state);
6561 else if (GET_MODE (insn) != TImode)
6563 if (!try_issue_nops (curr_state, before_nops_num))
6565 if (!try_issue_insn (curr_state, insn))
6567 curr_state->accumulated_insns_num++;
6568 gcc_assert (GET_CODE (PATTERN (insn)) != ASM_INPUT
6569 && asm_noperands (PATTERN (insn)) < 0);
6571 if (ia64_safe_type (insn) == TYPE_L)
6572 curr_state->accumulated_insns_num++;
6576 /* If this is an insn that must be first in a group, then don't allow
6577 nops to be emitted before it. Currently, alloc is the only such
6578 supported instruction. */
6579 /* ??? The bundling automatons should handle this for us, but they do
6580 not yet have support for the first_insn attribute. */
6581 if (before_nops_num > 0 && get_attr_first_insn (insn) == FIRST_INSN_YES)
6583 free_bundle_state (curr_state);
6587 state_transition (curr_state->dfa_state, dfa_pre_cycle_insn);
6588 state_transition (curr_state->dfa_state, NULL);
6590 if (!try_issue_nops (curr_state, before_nops_num))
6592 if (!try_issue_insn (curr_state, insn))
6594 curr_state->accumulated_insns_num++;
6595 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
6596 || asm_noperands (PATTERN (insn)) >= 0)
6598 /* Finish bundle containing asm insn. */
6599 curr_state->after_nops_num
6600 = 3 - curr_state->accumulated_insns_num % 3;
6601 curr_state->accumulated_insns_num
6602 += 3 - curr_state->accumulated_insns_num % 3;
6604 else if (ia64_safe_type (insn) == TYPE_L)
6605 curr_state->accumulated_insns_num++;
6607 if (ia64_safe_type (insn) == TYPE_B)
6608 curr_state->branch_deviation
6609 += 2 - (curr_state->accumulated_insns_num - 1) % 3;
6610 if (try_bundle_end_p && curr_state->accumulated_insns_num % 3 != 0)
6612 if (!only_bundle_end_p && insert_bundle_state (curr_state))
6615 struct bundle_state *curr_state1;
6616 struct bundle_state *allocated_states_chain;
6618 curr_state1 = get_free_bundle_state ();
6619 dfa_state = curr_state1->dfa_state;
6620 allocated_states_chain = curr_state1->allocated_states_chain;
6621 *curr_state1 = *curr_state;
6622 curr_state1->dfa_state = dfa_state;
6623 curr_state1->allocated_states_chain = allocated_states_chain;
6624 memcpy (curr_state1->dfa_state, curr_state->dfa_state,
6626 curr_state = curr_state1;
6628 if (!try_issue_nops (curr_state,
6629 3 - curr_state->accumulated_insns_num % 3))
6631 curr_state->after_nops_num
6632 = 3 - curr_state->accumulated_insns_num % 3;
6633 curr_state->accumulated_insns_num
6634 += 3 - curr_state->accumulated_insns_num % 3;
6636 if (!insert_bundle_state (curr_state))
6637 free_bundle_state (curr_state);
6641 /* The following function returns position in the two window bundle
6645 get_max_pos (state_t state)
6647 if (cpu_unit_reservation_p (state, pos_6))
6649 else if (cpu_unit_reservation_p (state, pos_5))
6651 else if (cpu_unit_reservation_p (state, pos_4))
6653 else if (cpu_unit_reservation_p (state, pos_3))
6655 else if (cpu_unit_reservation_p (state, pos_2))
6657 else if (cpu_unit_reservation_p (state, pos_1))
6663 /* The function returns code of a possible template for given position
6664 and state. The function should be called only with 2 values of
6665 position equal to 3 or 6. We avoid generating F NOPs by putting
6666 templates containing F insns at the end of the template search
6667 because undocumented anomaly in McKinley derived cores which can
6668 cause stalls if an F-unit insn (including a NOP) is issued within a
6669 six-cycle window after reading certain application registers (such
6670 as ar.bsp). Furthermore, power-considerations also argue against
6671 the use of F-unit instructions unless they're really needed. */
6674 get_template (state_t state, int pos)
6679 if (cpu_unit_reservation_p (state, _0mmi_))
6681 else if (cpu_unit_reservation_p (state, _0mii_))
6683 else if (cpu_unit_reservation_p (state, _0mmb_))
6685 else if (cpu_unit_reservation_p (state, _0mib_))
6687 else if (cpu_unit_reservation_p (state, _0mbb_))
6689 else if (cpu_unit_reservation_p (state, _0bbb_))
6691 else if (cpu_unit_reservation_p (state, _0mmf_))
6693 else if (cpu_unit_reservation_p (state, _0mfi_))
6695 else if (cpu_unit_reservation_p (state, _0mfb_))
6697 else if (cpu_unit_reservation_p (state, _0mlx_))
6702 if (cpu_unit_reservation_p (state, _1mmi_))
6704 else if (cpu_unit_reservation_p (state, _1mii_))
6706 else if (cpu_unit_reservation_p (state, _1mmb_))
6708 else if (cpu_unit_reservation_p (state, _1mib_))
6710 else if (cpu_unit_reservation_p (state, _1mbb_))
6712 else if (cpu_unit_reservation_p (state, _1bbb_))
6714 else if (_1mmf_ >= 0 && cpu_unit_reservation_p (state, _1mmf_))
6716 else if (cpu_unit_reservation_p (state, _1mfi_))
6718 else if (cpu_unit_reservation_p (state, _1mfb_))
6720 else if (cpu_unit_reservation_p (state, _1mlx_))
6729 /* The following function returns an insn important for insn bundling
6730 followed by INSN and before TAIL. */
6733 get_next_important_insn (rtx insn, rtx tail)
6735 for (; insn && insn != tail; insn = NEXT_INSN (insn))
6737 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
6738 && GET_CODE (PATTERN (insn)) != USE
6739 && GET_CODE (PATTERN (insn)) != CLOBBER)
6744 /* The following function does insn bundling. Bundling means
6745 inserting templates and nop insns to fit insn groups into permitted
6746 templates. Instruction scheduling uses NDFA (non-deterministic
6747 finite automata) encoding informations about the templates and the
6748 inserted nops. Nondeterminism of the automata permits follows
6749 all possible insn sequences very fast.
6751 Unfortunately it is not possible to get information about inserting
6752 nop insns and used templates from the automata states. The
6753 automata only says that we can issue an insn possibly inserting
6754 some nops before it and using some template. Therefore insn
6755 bundling in this function is implemented by using DFA
6756 (deterministic finite automata). We follows all possible insn
6757 sequences by inserting 0-2 nops (that is what the NDFA describe for
6758 insn scheduling) before/after each insn being bundled. We know the
6759 start of simulated processor cycle from insn scheduling (insn
6760 starting a new cycle has TImode).
6762 Simple implementation of insn bundling would create enormous
6763 number of possible insn sequences satisfying information about new
6764 cycle ticks taken from the insn scheduling. To make the algorithm
6765 practical we use dynamic programming. Each decision (about
6766 inserting nops and implicitly about previous decisions) is described
6767 by structure bundle_state (see above). If we generate the same
6768 bundle state (key is automaton state after issuing the insns and
6769 nops for it), we reuse already generated one. As consequence we
6770 reject some decisions which cannot improve the solution and
6771 reduce memory for the algorithm.
6773 When we reach the end of EBB (extended basic block), we choose the
6774 best sequence and then, moving back in EBB, insert templates for
6775 the best alternative. The templates are taken from querying
6776 automaton state for each insn in chosen bundle states.
6778 So the algorithm makes two (forward and backward) passes through
6779 EBB. There is an additional forward pass through EBB for Itanium1
6780 processor. This pass inserts more nops to make dependency between
6781 a producer insn and MMMUL/MMSHF at least 4 cycles long. */
6784 bundling (FILE *dump, int verbose, rtx prev_head_insn, rtx tail)
6786 struct bundle_state *curr_state, *next_state, *best_state;
6787 rtx insn, next_insn;
6789 int i, bundle_end_p, only_bundle_end_p, asm_p;
6790 int pos = 0, max_pos, template0, template1;
6793 enum attr_type type;
6796 /* Count insns in the EBB. */
6797 for (insn = NEXT_INSN (prev_head_insn);
6798 insn && insn != tail;
6799 insn = NEXT_INSN (insn))
6805 dfa_clean_insn_cache ();
6806 initiate_bundle_state_table ();
6807 index_to_bundle_states = xmalloc ((insn_num + 2)
6808 * sizeof (struct bundle_state *));
6809 /* First (forward) pass -- generation of bundle states. */
6810 curr_state = get_free_bundle_state ();
6811 curr_state->insn = NULL;
6812 curr_state->before_nops_num = 0;
6813 curr_state->after_nops_num = 0;
6814 curr_state->insn_num = 0;
6815 curr_state->cost = 0;
6816 curr_state->accumulated_insns_num = 0;
6817 curr_state->branch_deviation = 0;
6818 curr_state->next = NULL;
6819 curr_state->originator = NULL;
6820 state_reset (curr_state->dfa_state);
6821 index_to_bundle_states [0] = curr_state;
6823 /* Shift cycle mark if it is put on insn which could be ignored. */
6824 for (insn = NEXT_INSN (prev_head_insn);
6826 insn = NEXT_INSN (insn))
6828 && (ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IGNORE
6829 || GET_CODE (PATTERN (insn)) == USE
6830 || GET_CODE (PATTERN (insn)) == CLOBBER)
6831 && GET_MODE (insn) == TImode)
6833 PUT_MODE (insn, VOIDmode);
6834 for (next_insn = NEXT_INSN (insn);
6836 next_insn = NEXT_INSN (next_insn))
6837 if (INSN_P (next_insn)
6838 && ia64_safe_itanium_class (next_insn) != ITANIUM_CLASS_IGNORE
6839 && GET_CODE (PATTERN (next_insn)) != USE
6840 && GET_CODE (PATTERN (next_insn)) != CLOBBER)
6842 PUT_MODE (next_insn, TImode);
6846 /* Froward pass: generation of bundle states. */
6847 for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail);
6851 gcc_assert (INSN_P (insn)
6852 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
6853 && GET_CODE (PATTERN (insn)) != USE
6854 && GET_CODE (PATTERN (insn)) != CLOBBER);
6855 type = ia64_safe_type (insn);
6856 next_insn = get_next_important_insn (NEXT_INSN (insn), tail);
6858 index_to_bundle_states [insn_num] = NULL;
6859 for (curr_state = index_to_bundle_states [insn_num - 1];
6861 curr_state = next_state)
6863 pos = curr_state->accumulated_insns_num % 3;
6864 next_state = curr_state->next;
6865 /* We must fill up the current bundle in order to start a
6866 subsequent asm insn in a new bundle. Asm insn is always
6867 placed in a separate bundle. */
6869 = (next_insn != NULL_RTX
6870 && INSN_CODE (insn) == CODE_FOR_insn_group_barrier
6871 && ia64_safe_type (next_insn) == TYPE_UNKNOWN);
6872 /* We may fill up the current bundle if it is the cycle end
6873 without a group barrier. */
6875 = (only_bundle_end_p || next_insn == NULL_RTX
6876 || (GET_MODE (next_insn) == TImode
6877 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier));
6878 if (type == TYPE_F || type == TYPE_B || type == TYPE_L
6880 /* We need to insert 2 nops for cases like M_MII. To
6881 guarantee issuing all insns on the same cycle for
6882 Itanium 1, we need to issue 2 nops after the first M
6883 insn (MnnMII where n is a nop insn). */
6884 || ((type == TYPE_M || type == TYPE_A)
6885 && ia64_tune == PROCESSOR_ITANIUM
6886 && !bundle_end_p && pos == 1))
6887 issue_nops_and_insn (curr_state, 2, insn, bundle_end_p,
6889 issue_nops_and_insn (curr_state, 1, insn, bundle_end_p,
6891 issue_nops_and_insn (curr_state, 0, insn, bundle_end_p,
6894 gcc_assert (index_to_bundle_states [insn_num]);
6895 for (curr_state = index_to_bundle_states [insn_num];
6897 curr_state = curr_state->next)
6898 if (verbose >= 2 && dump)
6900 /* This structure is taken from generated code of the
6901 pipeline hazard recognizer (see file insn-attrtab.c).
6902 Please don't forget to change the structure if a new
6903 automaton is added to .md file. */
6906 unsigned short one_automaton_state;
6907 unsigned short oneb_automaton_state;
6908 unsigned short two_automaton_state;
6909 unsigned short twob_automaton_state;
6914 "// Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
6915 curr_state->unique_num,
6916 (curr_state->originator == NULL
6917 ? -1 : curr_state->originator->unique_num),
6919 curr_state->before_nops_num, curr_state->after_nops_num,
6920 curr_state->accumulated_insns_num, curr_state->branch_deviation,
6921 (ia64_tune == PROCESSOR_ITANIUM
6922 ? ((struct DFA_chip *) curr_state->dfa_state)->oneb_automaton_state
6923 : ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state),
6928 /* We should find a solution because the 2nd insn scheduling has
6930 gcc_assert (index_to_bundle_states [insn_num]);
6931 /* Find a state corresponding to the best insn sequence. */
6933 for (curr_state = index_to_bundle_states [insn_num];
6935 curr_state = curr_state->next)
6936 /* We are just looking at the states with fully filled up last
6937 bundle. The first we prefer insn sequences with minimal cost
6938 then with minimal inserted nops and finally with branch insns
6939 placed in the 3rd slots. */
6940 if (curr_state->accumulated_insns_num % 3 == 0
6941 && (best_state == NULL || best_state->cost > curr_state->cost
6942 || (best_state->cost == curr_state->cost
6943 && (curr_state->accumulated_insns_num
6944 < best_state->accumulated_insns_num
6945 || (curr_state->accumulated_insns_num
6946 == best_state->accumulated_insns_num
6947 && curr_state->branch_deviation
6948 < best_state->branch_deviation)))))
6949 best_state = curr_state;
6950 /* Second (backward) pass: adding nops and templates. */
6951 insn_num = best_state->before_nops_num;
6952 template0 = template1 = -1;
6953 for (curr_state = best_state;
6954 curr_state->originator != NULL;
6955 curr_state = curr_state->originator)
6957 insn = curr_state->insn;
6958 asm_p = (GET_CODE (PATTERN (insn)) == ASM_INPUT
6959 || asm_noperands (PATTERN (insn)) >= 0);
6961 if (verbose >= 2 && dump)
6965 unsigned short one_automaton_state;
6966 unsigned short oneb_automaton_state;
6967 unsigned short two_automaton_state;
6968 unsigned short twob_automaton_state;
6973 "// Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
6974 curr_state->unique_num,
6975 (curr_state->originator == NULL
6976 ? -1 : curr_state->originator->unique_num),
6978 curr_state->before_nops_num, curr_state->after_nops_num,
6979 curr_state->accumulated_insns_num, curr_state->branch_deviation,
6980 (ia64_tune == PROCESSOR_ITANIUM
6981 ? ((struct DFA_chip *) curr_state->dfa_state)->oneb_automaton_state
6982 : ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state),
6985 /* Find the position in the current bundle window. The window can
6986 contain at most two bundles. Two bundle window means that
6987 the processor will make two bundle rotation. */
6988 max_pos = get_max_pos (curr_state->dfa_state);
6990 /* The following (negative template number) means that the
6991 processor did one bundle rotation. */
6992 || (max_pos == 3 && template0 < 0))
6994 /* We are at the end of the window -- find template(s) for
6998 template0 = get_template (curr_state->dfa_state, 3);
7001 template1 = get_template (curr_state->dfa_state, 3);
7002 template0 = get_template (curr_state->dfa_state, 6);
7005 if (max_pos > 3 && template1 < 0)
7006 /* It may happen when we have the stop inside a bundle. */
7008 gcc_assert (pos <= 3);
7009 template1 = get_template (curr_state->dfa_state, 3);
7013 /* Emit nops after the current insn. */
7014 for (i = 0; i < curr_state->after_nops_num; i++)
7017 emit_insn_after (nop, insn);
7019 gcc_assert (pos >= 0);
7022 /* We are at the start of a bundle: emit the template
7023 (it should be defined). */
7024 gcc_assert (template0 >= 0);
7025 b = gen_bundle_selector (GEN_INT (template0));
7026 ia64_emit_insn_before (b, nop);
7027 /* If we have two bundle window, we make one bundle
7028 rotation. Otherwise template0 will be undefined
7029 (negative value). */
7030 template0 = template1;
7034 /* Move the position backward in the window. Group barrier has
7035 no slot. Asm insn takes all bundle. */
7036 if (INSN_CODE (insn) != CODE_FOR_insn_group_barrier
7037 && GET_CODE (PATTERN (insn)) != ASM_INPUT
7038 && asm_noperands (PATTERN (insn)) < 0)
7040 /* Long insn takes 2 slots. */
7041 if (ia64_safe_type (insn) == TYPE_L)
7043 gcc_assert (pos >= 0);
7045 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier
7046 && GET_CODE (PATTERN (insn)) != ASM_INPUT
7047 && asm_noperands (PATTERN (insn)) < 0)
7049 /* The current insn is at the bundle start: emit the
7051 gcc_assert (template0 >= 0);
7052 b = gen_bundle_selector (GEN_INT (template0));
7053 ia64_emit_insn_before (b, insn);
7054 b = PREV_INSN (insn);
7056 /* See comment above in analogous place for emitting nops
7058 template0 = template1;
7061 /* Emit nops after the current insn. */
7062 for (i = 0; i < curr_state->before_nops_num; i++)
7065 ia64_emit_insn_before (nop, insn);
7066 nop = PREV_INSN (insn);
7069 gcc_assert (pos >= 0);
7072 /* See comment above in analogous place for emitting nops
7074 gcc_assert (template0 >= 0);
7075 b = gen_bundle_selector (GEN_INT (template0));
7076 ia64_emit_insn_before (b, insn);
7077 b = PREV_INSN (insn);
7079 template0 = template1;
7084 if (ia64_tune == PROCESSOR_ITANIUM)
7085 /* Insert additional cycles for MM-insns (MMMUL and MMSHF).
7086 Itanium1 has a strange design, if the distance between an insn
7087 and dependent MM-insn is less 4 then we have a 6 additional
7088 cycles stall. So we make the distance equal to 4 cycles if it
7090 for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail);
7094 gcc_assert (INSN_P (insn)
7095 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
7096 && GET_CODE (PATTERN (insn)) != USE
7097 && GET_CODE (PATTERN (insn)) != CLOBBER);
7098 next_insn = get_next_important_insn (NEXT_INSN (insn), tail);
7099 if (INSN_UID (insn) < clocks_length && add_cycles [INSN_UID (insn)])
7100 /* We found a MM-insn which needs additional cycles. */
7106 /* Now we are searching for a template of the bundle in
7107 which the MM-insn is placed and the position of the
7108 insn in the bundle (0, 1, 2). Also we are searching
7109 for that there is a stop before the insn. */
7110 last = prev_active_insn (insn);
7111 pred_stop_p = recog_memoized (last) == CODE_FOR_insn_group_barrier;
7113 last = prev_active_insn (last);
7115 for (;; last = prev_active_insn (last))
7116 if (recog_memoized (last) == CODE_FOR_bundle_selector)
7118 template0 = XINT (XVECEXP (PATTERN (last), 0, 0), 0);
7120 /* The insn is in MLX bundle. Change the template
7121 onto MFI because we will add nops before the
7122 insn. It simplifies subsequent code a lot. */
7124 = gen_bundle_selector (const2_rtx); /* -> MFI */
7127 else if (recog_memoized (last) != CODE_FOR_insn_group_barrier
7128 && (ia64_safe_itanium_class (last)
7129 != ITANIUM_CLASS_IGNORE))
7131 /* Some check of correctness: the stop is not at the
7132 bundle start, there are no more 3 insns in the bundle,
7133 and the MM-insn is not at the start of bundle with
7135 gcc_assert ((!pred_stop_p || n)
7137 && (template0 != 9 || !n));
7138 /* Put nops after the insn in the bundle. */
7139 for (j = 3 - n; j > 0; j --)
7140 ia64_emit_insn_before (gen_nop (), insn);
7141 /* It takes into account that we will add more N nops
7142 before the insn lately -- please see code below. */
7143 add_cycles [INSN_UID (insn)]--;
7144 if (!pred_stop_p || add_cycles [INSN_UID (insn)])
7145 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7148 add_cycles [INSN_UID (insn)]--;
7149 for (i = add_cycles [INSN_UID (insn)]; i > 0; i--)
7151 /* Insert "MII;" template. */
7152 ia64_emit_insn_before (gen_bundle_selector (const0_rtx),
7154 ia64_emit_insn_before (gen_nop (), insn);
7155 ia64_emit_insn_before (gen_nop (), insn);
7158 /* To decrease code size, we use "MI;I;"
7160 ia64_emit_insn_before
7161 (gen_insn_group_barrier (GEN_INT (3)), insn);
7164 ia64_emit_insn_before (gen_nop (), insn);
7165 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7168 /* Put the MM-insn in the same slot of a bundle with the
7169 same template as the original one. */
7170 ia64_emit_insn_before (gen_bundle_selector (GEN_INT (template0)),
7172 /* To put the insn in the same slot, add necessary number
7174 for (j = n; j > 0; j --)
7175 ia64_emit_insn_before (gen_nop (), insn);
7176 /* Put the stop if the original bundle had it. */
7178 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7182 free (index_to_bundle_states);
7183 finish_bundle_state_table ();
7185 dfa_clean_insn_cache ();
7188 /* The following function is called at the end of scheduling BB or
7189 EBB. After reload, it inserts stop bits and does insn bundling. */
7192 ia64_sched_finish (FILE *dump, int sched_verbose)
7195 fprintf (dump, "// Finishing schedule.\n");
7196 if (!reload_completed)
7198 if (reload_completed)
7200 final_emit_insn_group_barriers (dump);
7201 bundling (dump, sched_verbose, current_sched_info->prev_head,
7202 current_sched_info->next_tail);
7203 if (sched_verbose && dump)
7204 fprintf (dump, "// finishing %d-%d\n",
7205 INSN_UID (NEXT_INSN (current_sched_info->prev_head)),
7206 INSN_UID (PREV_INSN (current_sched_info->next_tail)));
7212 /* The following function inserts stop bits in scheduled BB or EBB. */
7215 final_emit_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED)
7218 int need_barrier_p = 0;
7219 rtx prev_insn = NULL_RTX;
7221 init_insn_group_barriers ();
7223 for (insn = NEXT_INSN (current_sched_info->prev_head);
7224 insn != current_sched_info->next_tail;
7225 insn = NEXT_INSN (insn))
7227 if (GET_CODE (insn) == BARRIER)
7229 rtx last = prev_active_insn (insn);
7233 if (GET_CODE (last) == JUMP_INSN
7234 && GET_CODE (PATTERN (last)) == ADDR_DIFF_VEC)
7235 last = prev_active_insn (last);
7236 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
7237 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
7239 init_insn_group_barriers ();
7241 prev_insn = NULL_RTX;
7243 else if (INSN_P (insn))
7245 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
7247 init_insn_group_barriers ();
7249 prev_insn = NULL_RTX;
7251 else if (need_barrier_p || group_barrier_needed (insn))
7253 if (TARGET_EARLY_STOP_BITS)
7258 last != current_sched_info->prev_head;
7259 last = PREV_INSN (last))
7260 if (INSN_P (last) && GET_MODE (last) == TImode
7261 && stops_p [INSN_UID (last)])
7263 if (last == current_sched_info->prev_head)
7265 last = prev_active_insn (last);
7267 && recog_memoized (last) != CODE_FOR_insn_group_barrier)
7268 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)),
7270 init_insn_group_barriers ();
7271 for (last = NEXT_INSN (last);
7273 last = NEXT_INSN (last))
7275 group_barrier_needed (last);
7279 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7281 init_insn_group_barriers ();
7283 group_barrier_needed (insn);
7284 prev_insn = NULL_RTX;
7286 else if (recog_memoized (insn) >= 0)
7288 need_barrier_p = (GET_CODE (insn) == CALL_INSN
7289 || GET_CODE (PATTERN (insn)) == ASM_INPUT
7290 || asm_noperands (PATTERN (insn)) >= 0);
7297 /* If the following function returns TRUE, we will use the the DFA
7301 ia64_first_cycle_multipass_dfa_lookahead (void)
7303 return (reload_completed ? 6 : 4);
7306 /* The following function initiates variable `dfa_pre_cycle_insn'. */
7309 ia64_init_dfa_pre_cycle_insn (void)
7311 if (temp_dfa_state == NULL)
7313 dfa_state_size = state_size ();
7314 temp_dfa_state = xmalloc (dfa_state_size);
7315 prev_cycle_state = xmalloc (dfa_state_size);
7317 dfa_pre_cycle_insn = make_insn_raw (gen_pre_cycle ());
7318 PREV_INSN (dfa_pre_cycle_insn) = NEXT_INSN (dfa_pre_cycle_insn) = NULL_RTX;
7319 recog_memoized (dfa_pre_cycle_insn);
7320 dfa_stop_insn = make_insn_raw (gen_insn_group_barrier (GEN_INT (3)));
7321 PREV_INSN (dfa_stop_insn) = NEXT_INSN (dfa_stop_insn) = NULL_RTX;
7322 recog_memoized (dfa_stop_insn);
7325 /* The following function returns the pseudo insn DFA_PRE_CYCLE_INSN
7326 used by the DFA insn scheduler. */
7329 ia64_dfa_pre_cycle_insn (void)
7331 return dfa_pre_cycle_insn;
7334 /* The following function returns TRUE if PRODUCER (of type ilog or
7335 ld) produces address for CONSUMER (of type st or stf). */
7338 ia64_st_address_bypass_p (rtx producer, rtx consumer)
7342 gcc_assert (producer && consumer);
7343 dest = ia64_single_set (producer);
7345 reg = SET_DEST (dest);
7347 if (GET_CODE (reg) == SUBREG)
7348 reg = SUBREG_REG (reg);
7349 gcc_assert (GET_CODE (reg) == REG);
7351 dest = ia64_single_set (consumer);
7353 mem = SET_DEST (dest);
7354 gcc_assert (mem && GET_CODE (mem) == MEM);
7355 return reg_mentioned_p (reg, mem);
7358 /* The following function returns TRUE if PRODUCER (of type ilog or
7359 ld) produces address for CONSUMER (of type ld or fld). */
7362 ia64_ld_address_bypass_p (rtx producer, rtx consumer)
7364 rtx dest, src, reg, mem;
7366 gcc_assert (producer && consumer);
7367 dest = ia64_single_set (producer);
7369 reg = SET_DEST (dest);
7371 if (GET_CODE (reg) == SUBREG)
7372 reg = SUBREG_REG (reg);
7373 gcc_assert (GET_CODE (reg) == REG);
7375 src = ia64_single_set (consumer);
7377 mem = SET_SRC (src);
7379 if (GET_CODE (mem) == UNSPEC && XVECLEN (mem, 0) > 0)
7380 mem = XVECEXP (mem, 0, 0);
7381 while (GET_CODE (mem) == SUBREG || GET_CODE (mem) == ZERO_EXTEND)
7382 mem = XEXP (mem, 0);
7384 /* Note that LO_SUM is used for GOT loads. */
7385 gcc_assert (GET_CODE (mem) == LO_SUM || GET_CODE (mem) == MEM);
7387 return reg_mentioned_p (reg, mem);
7390 /* The following function returns TRUE if INSN produces address for a
7391 load/store insn. We will place such insns into M slot because it
7392 decreases its latency time. */
7395 ia64_produce_address_p (rtx insn)
7401 /* Emit pseudo-ops for the assembler to describe predicate relations.
7402 At present this assumes that we only consider predicate pairs to
7403 be mutex, and that the assembler can deduce proper values from
7404 straight-line code. */
7407 emit_predicate_relation_info (void)
7411 FOR_EACH_BB_REVERSE (bb)
7414 rtx head = BB_HEAD (bb);
7416 /* We only need such notes at code labels. */
7417 if (GET_CODE (head) != CODE_LABEL)
7419 if (GET_CODE (NEXT_INSN (head)) == NOTE
7420 && NOTE_LINE_NUMBER (NEXT_INSN (head)) == NOTE_INSN_BASIC_BLOCK)
7421 head = NEXT_INSN (head);
7423 /* Skip p0, which may be thought to be live due to (reg:DI p0)
7424 grabbing the entire block of predicate registers. */
7425 for (r = PR_REG (2); r < PR_REG (64); r += 2)
7426 if (REGNO_REG_SET_P (bb->global_live_at_start, r))
7428 rtx p = gen_rtx_REG (BImode, r);
7429 rtx n = emit_insn_after (gen_pred_rel_mutex (p), head);
7430 if (head == BB_END (bb))
7436 /* Look for conditional calls that do not return, and protect predicate
7437 relations around them. Otherwise the assembler will assume the call
7438 returns, and complain about uses of call-clobbered predicates after
7440 FOR_EACH_BB_REVERSE (bb)
7442 rtx insn = BB_HEAD (bb);
7446 if (GET_CODE (insn) == CALL_INSN
7447 && GET_CODE (PATTERN (insn)) == COND_EXEC
7448 && find_reg_note (insn, REG_NORETURN, NULL_RTX))
7450 rtx b = emit_insn_before (gen_safe_across_calls_all (), insn);
7451 rtx a = emit_insn_after (gen_safe_across_calls_normal (), insn);
7452 if (BB_HEAD (bb) == insn)
7454 if (BB_END (bb) == insn)
7458 if (insn == BB_END (bb))
7460 insn = NEXT_INSN (insn);
7465 /* Perform machine dependent operations on the rtl chain INSNS. */
7470 /* We are freeing block_for_insn in the toplev to keep compatibility
7471 with old MDEP_REORGS that are not CFG based. Recompute it now. */
7472 compute_bb_for_insn ();
7474 /* If optimizing, we'll have split before scheduling. */
7476 split_all_insns (0);
7478 /* ??? update_life_info_in_dirty_blocks fails to terminate during
7479 non-optimizing bootstrap. */
7480 update_life_info (NULL, UPDATE_LIFE_GLOBAL_RM_NOTES, PROP_DEATH_NOTES);
7482 if (ia64_flag_schedule_insns2)
7484 timevar_push (TV_SCHED2);
7485 ia64_final_schedule = 1;
7487 initiate_bundle_states ();
7488 ia64_nop = make_insn_raw (gen_nop ());
7489 PREV_INSN (ia64_nop) = NEXT_INSN (ia64_nop) = NULL_RTX;
7490 recog_memoized (ia64_nop);
7491 clocks_length = get_max_uid () + 1;
7492 stops_p = xcalloc (1, clocks_length);
7493 if (ia64_tune == PROCESSOR_ITANIUM)
7495 clocks = xcalloc (clocks_length, sizeof (int));
7496 add_cycles = xcalloc (clocks_length, sizeof (int));
7498 if (ia64_tune == PROCESSOR_ITANIUM2)
7500 pos_1 = get_cpu_unit_code ("2_1");
7501 pos_2 = get_cpu_unit_code ("2_2");
7502 pos_3 = get_cpu_unit_code ("2_3");
7503 pos_4 = get_cpu_unit_code ("2_4");
7504 pos_5 = get_cpu_unit_code ("2_5");
7505 pos_6 = get_cpu_unit_code ("2_6");
7506 _0mii_ = get_cpu_unit_code ("2b_0mii.");
7507 _0mmi_ = get_cpu_unit_code ("2b_0mmi.");
7508 _0mfi_ = get_cpu_unit_code ("2b_0mfi.");
7509 _0mmf_ = get_cpu_unit_code ("2b_0mmf.");
7510 _0bbb_ = get_cpu_unit_code ("2b_0bbb.");
7511 _0mbb_ = get_cpu_unit_code ("2b_0mbb.");
7512 _0mib_ = get_cpu_unit_code ("2b_0mib.");
7513 _0mmb_ = get_cpu_unit_code ("2b_0mmb.");
7514 _0mfb_ = get_cpu_unit_code ("2b_0mfb.");
7515 _0mlx_ = get_cpu_unit_code ("2b_0mlx.");
7516 _1mii_ = get_cpu_unit_code ("2b_1mii.");
7517 _1mmi_ = get_cpu_unit_code ("2b_1mmi.");
7518 _1mfi_ = get_cpu_unit_code ("2b_1mfi.");
7519 _1mmf_ = get_cpu_unit_code ("2b_1mmf.");
7520 _1bbb_ = get_cpu_unit_code ("2b_1bbb.");
7521 _1mbb_ = get_cpu_unit_code ("2b_1mbb.");
7522 _1mib_ = get_cpu_unit_code ("2b_1mib.");
7523 _1mmb_ = get_cpu_unit_code ("2b_1mmb.");
7524 _1mfb_ = get_cpu_unit_code ("2b_1mfb.");
7525 _1mlx_ = get_cpu_unit_code ("2b_1mlx.");
7529 pos_1 = get_cpu_unit_code ("1_1");
7530 pos_2 = get_cpu_unit_code ("1_2");
7531 pos_3 = get_cpu_unit_code ("1_3");
7532 pos_4 = get_cpu_unit_code ("1_4");
7533 pos_5 = get_cpu_unit_code ("1_5");
7534 pos_6 = get_cpu_unit_code ("1_6");
7535 _0mii_ = get_cpu_unit_code ("1b_0mii.");
7536 _0mmi_ = get_cpu_unit_code ("1b_0mmi.");
7537 _0mfi_ = get_cpu_unit_code ("1b_0mfi.");
7538 _0mmf_ = get_cpu_unit_code ("1b_0mmf.");
7539 _0bbb_ = get_cpu_unit_code ("1b_0bbb.");
7540 _0mbb_ = get_cpu_unit_code ("1b_0mbb.");
7541 _0mib_ = get_cpu_unit_code ("1b_0mib.");
7542 _0mmb_ = get_cpu_unit_code ("1b_0mmb.");
7543 _0mfb_ = get_cpu_unit_code ("1b_0mfb.");
7544 _0mlx_ = get_cpu_unit_code ("1b_0mlx.");
7545 _1mii_ = get_cpu_unit_code ("1b_1mii.");
7546 _1mmi_ = get_cpu_unit_code ("1b_1mmi.");
7547 _1mfi_ = get_cpu_unit_code ("1b_1mfi.");
7548 _1mmf_ = get_cpu_unit_code ("1b_1mmf.");
7549 _1bbb_ = get_cpu_unit_code ("1b_1bbb.");
7550 _1mbb_ = get_cpu_unit_code ("1b_1mbb.");
7551 _1mib_ = get_cpu_unit_code ("1b_1mib.");
7552 _1mmb_ = get_cpu_unit_code ("1b_1mmb.");
7553 _1mfb_ = get_cpu_unit_code ("1b_1mfb.");
7554 _1mlx_ = get_cpu_unit_code ("1b_1mlx.");
7556 schedule_ebbs (dump_file);
7557 finish_bundle_states ();
7558 if (ia64_tune == PROCESSOR_ITANIUM)
7564 emit_insn_group_barriers (dump_file);
7566 ia64_final_schedule = 0;
7567 timevar_pop (TV_SCHED2);
7570 emit_all_insn_group_barriers (dump_file);
7572 /* A call must not be the last instruction in a function, so that the
7573 return address is still within the function, so that unwinding works
7574 properly. Note that IA-64 differs from dwarf2 on this point. */
7575 if (flag_unwind_tables || (flag_exceptions && !USING_SJLJ_EXCEPTIONS))
7580 insn = get_last_insn ();
7581 if (! INSN_P (insn))
7582 insn = prev_active_insn (insn);
7583 /* Skip over insns that expand to nothing. */
7584 while (GET_CODE (insn) == INSN && get_attr_empty (insn) == EMPTY_YES)
7586 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
7587 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
7589 insn = prev_active_insn (insn);
7591 if (GET_CODE (insn) == CALL_INSN)
7594 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
7595 emit_insn (gen_break_f ());
7596 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
7600 emit_predicate_relation_info ();
7602 if (ia64_flag_var_tracking)
7604 timevar_push (TV_VAR_TRACKING);
7605 variable_tracking_main ();
7606 timevar_pop (TV_VAR_TRACKING);
7610 /* Return true if REGNO is used by the epilogue. */
7613 ia64_epilogue_uses (int regno)
7618 /* With a call to a function in another module, we will write a new
7619 value to "gp". After returning from such a call, we need to make
7620 sure the function restores the original gp-value, even if the
7621 function itself does not use the gp anymore. */
7622 return !(TARGET_AUTO_PIC || TARGET_NO_PIC);
7624 case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3):
7625 case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7):
7626 /* For functions defined with the syscall_linkage attribute, all
7627 input registers are marked as live at all function exits. This
7628 prevents the register allocator from using the input registers,
7629 which in turn makes it possible to restart a system call after
7630 an interrupt without having to save/restore the input registers.
7631 This also prevents kernel data from leaking to application code. */
7632 return lookup_attribute ("syscall_linkage",
7633 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))) != NULL;
7636 /* Conditional return patterns can't represent the use of `b0' as
7637 the return address, so we force the value live this way. */
7641 /* Likewise for ar.pfs, which is used by br.ret. */
7649 /* Return true if REGNO is used by the frame unwinder. */
7652 ia64_eh_uses (int regno)
7654 if (! reload_completed)
7657 if (current_frame_info.reg_save_b0
7658 && regno == current_frame_info.reg_save_b0)
7660 if (current_frame_info.reg_save_pr
7661 && regno == current_frame_info.reg_save_pr)
7663 if (current_frame_info.reg_save_ar_pfs
7664 && regno == current_frame_info.reg_save_ar_pfs)
7666 if (current_frame_info.reg_save_ar_unat
7667 && regno == current_frame_info.reg_save_ar_unat)
7669 if (current_frame_info.reg_save_ar_lc
7670 && regno == current_frame_info.reg_save_ar_lc)
7676 /* Return true if this goes in small data/bss. */
7678 /* ??? We could also support own long data here. Generating movl/add/ld8
7679 instead of addl,ld8/ld8. This makes the code bigger, but should make the
7680 code faster because there is one less load. This also includes incomplete
7681 types which can't go in sdata/sbss. */
7684 ia64_in_small_data_p (tree exp)
7686 if (TARGET_NO_SDATA)
7689 /* We want to merge strings, so we never consider them small data. */
7690 if (TREE_CODE (exp) == STRING_CST)
7693 /* Functions are never small data. */
7694 if (TREE_CODE (exp) == FUNCTION_DECL)
7697 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
7699 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
7701 if (strcmp (section, ".sdata") == 0
7702 || strncmp (section, ".sdata.", 7) == 0
7703 || strncmp (section, ".gnu.linkonce.s.", 16) == 0
7704 || strcmp (section, ".sbss") == 0
7705 || strncmp (section, ".sbss.", 6) == 0
7706 || strncmp (section, ".gnu.linkonce.sb.", 17) == 0)
7711 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
7713 /* If this is an incomplete type with size 0, then we can't put it
7714 in sdata because it might be too big when completed. */
7715 if (size > 0 && size <= ia64_section_threshold)
7722 /* Output assembly directives for prologue regions. */
7724 /* The current basic block number. */
7726 static bool last_block;
7728 /* True if we need a copy_state command at the start of the next block. */
7730 static bool need_copy_state;
7732 /* The function emits unwind directives for the start of an epilogue. */
7735 process_epilogue (void)
7737 /* If this isn't the last block of the function, then we need to label the
7738 current state, and copy it back in at the start of the next block. */
7742 fprintf (asm_out_file, "\t.label_state %d\n",
7743 ++cfun->machine->state_num);
7744 need_copy_state = true;
7747 fprintf (asm_out_file, "\t.restore sp\n");
7750 /* This function processes a SET pattern looking for specific patterns
7751 which result in emitting an assembly directive required for unwinding. */
7754 process_set (FILE *asm_out_file, rtx pat)
7756 rtx src = SET_SRC (pat);
7757 rtx dest = SET_DEST (pat);
7758 int src_regno, dest_regno;
7760 /* Look for the ALLOC insn. */
7761 if (GET_CODE (src) == UNSPEC_VOLATILE
7762 && XINT (src, 1) == UNSPECV_ALLOC
7763 && GET_CODE (dest) == REG)
7765 dest_regno = REGNO (dest);
7767 /* If this is the final destination for ar.pfs, then this must
7768 be the alloc in the prologue. */
7769 if (dest_regno == current_frame_info.reg_save_ar_pfs)
7770 fprintf (asm_out_file, "\t.save ar.pfs, r%d\n",
7771 ia64_dbx_register_number (dest_regno));
7774 /* This must be an alloc before a sibcall. We must drop the
7775 old frame info. The easiest way to drop the old frame
7776 info is to ensure we had a ".restore sp" directive
7777 followed by a new prologue. If the procedure doesn't
7778 have a memory-stack frame, we'll issue a dummy ".restore
7780 if (current_frame_info.total_size == 0 && !frame_pointer_needed)
7781 /* if haven't done process_epilogue() yet, do it now */
7782 process_epilogue ();
7783 fprintf (asm_out_file, "\t.prologue\n");
7788 /* Look for SP = .... */
7789 if (GET_CODE (dest) == REG && REGNO (dest) == STACK_POINTER_REGNUM)
7791 if (GET_CODE (src) == PLUS)
7793 rtx op0 = XEXP (src, 0);
7794 rtx op1 = XEXP (src, 1);
7796 gcc_assert (op0 == dest && GET_CODE (op1) == CONST_INT);
7798 if (INTVAL (op1) < 0)
7799 fprintf (asm_out_file, "\t.fframe "HOST_WIDE_INT_PRINT_DEC"\n",
7802 process_epilogue ();
7806 gcc_assert (GET_CODE (src) == REG
7807 && REGNO (src) == HARD_FRAME_POINTER_REGNUM);
7808 process_epilogue ();
7814 /* Register move we need to look at. */
7815 if (GET_CODE (dest) == REG && GET_CODE (src) == REG)
7817 src_regno = REGNO (src);
7818 dest_regno = REGNO (dest);
7823 /* Saving return address pointer. */
7824 gcc_assert (dest_regno == current_frame_info.reg_save_b0);
7825 fprintf (asm_out_file, "\t.save rp, r%d\n",
7826 ia64_dbx_register_number (dest_regno));
7830 gcc_assert (dest_regno == current_frame_info.reg_save_pr);
7831 fprintf (asm_out_file, "\t.save pr, r%d\n",
7832 ia64_dbx_register_number (dest_regno));
7835 case AR_UNAT_REGNUM:
7836 gcc_assert (dest_regno == current_frame_info.reg_save_ar_unat);
7837 fprintf (asm_out_file, "\t.save ar.unat, r%d\n",
7838 ia64_dbx_register_number (dest_regno));
7842 gcc_assert (dest_regno == current_frame_info.reg_save_ar_lc);
7843 fprintf (asm_out_file, "\t.save ar.lc, r%d\n",
7844 ia64_dbx_register_number (dest_regno));
7847 case STACK_POINTER_REGNUM:
7848 gcc_assert (dest_regno == HARD_FRAME_POINTER_REGNUM
7849 && frame_pointer_needed);
7850 fprintf (asm_out_file, "\t.vframe r%d\n",
7851 ia64_dbx_register_number (dest_regno));
7855 /* Everything else should indicate being stored to memory. */
7860 /* Memory store we need to look at. */
7861 if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
7867 if (GET_CODE (XEXP (dest, 0)) == REG)
7869 base = XEXP (dest, 0);
7874 gcc_assert (GET_CODE (XEXP (dest, 0)) == PLUS
7875 && GET_CODE (XEXP (XEXP (dest, 0), 1)) == CONST_INT);
7876 base = XEXP (XEXP (dest, 0), 0);
7877 off = INTVAL (XEXP (XEXP (dest, 0), 1));
7880 if (base == hard_frame_pointer_rtx)
7882 saveop = ".savepsp";
7887 gcc_assert (base == stack_pointer_rtx);
7891 src_regno = REGNO (src);
7895 gcc_assert (!current_frame_info.reg_save_b0);
7896 fprintf (asm_out_file, "\t%s rp, %ld\n", saveop, off);
7900 gcc_assert (!current_frame_info.reg_save_pr);
7901 fprintf (asm_out_file, "\t%s pr, %ld\n", saveop, off);
7905 gcc_assert (!current_frame_info.reg_save_ar_lc);
7906 fprintf (asm_out_file, "\t%s ar.lc, %ld\n", saveop, off);
7910 gcc_assert (!current_frame_info.reg_save_ar_pfs);
7911 fprintf (asm_out_file, "\t%s ar.pfs, %ld\n", saveop, off);
7914 case AR_UNAT_REGNUM:
7915 gcc_assert (!current_frame_info.reg_save_ar_unat);
7916 fprintf (asm_out_file, "\t%s ar.unat, %ld\n", saveop, off);
7923 fprintf (asm_out_file, "\t.save.g 0x%x\n",
7924 1 << (src_regno - GR_REG (4)));
7932 fprintf (asm_out_file, "\t.save.b 0x%x\n",
7933 1 << (src_regno - BR_REG (1)));
7940 fprintf (asm_out_file, "\t.save.f 0x%x\n",
7941 1 << (src_regno - FR_REG (2)));
7944 case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19):
7945 case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23):
7946 case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27):
7947 case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31):
7948 fprintf (asm_out_file, "\t.save.gf 0x0, 0x%x\n",
7949 1 << (src_regno - FR_REG (12)));
7961 /* This function looks at a single insn and emits any directives
7962 required to unwind this insn. */
7964 process_for_unwind_directive (FILE *asm_out_file, rtx insn)
7966 if (flag_unwind_tables
7967 || (flag_exceptions && !USING_SJLJ_EXCEPTIONS))
7971 if (GET_CODE (insn) == NOTE
7972 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_BASIC_BLOCK)
7974 last_block = NOTE_BASIC_BLOCK (insn)->next_bb == EXIT_BLOCK_PTR;
7976 /* Restore unwind state from immediately before the epilogue. */
7977 if (need_copy_state)
7979 fprintf (asm_out_file, "\t.body\n");
7980 fprintf (asm_out_file, "\t.copy_state %d\n",
7981 cfun->machine->state_num);
7982 need_copy_state = false;
7986 if (GET_CODE (insn) == NOTE || ! RTX_FRAME_RELATED_P (insn))
7989 pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX);
7991 pat = XEXP (pat, 0);
7993 pat = PATTERN (insn);
7995 switch (GET_CODE (pat))
7998 process_set (asm_out_file, pat);
8004 int limit = XVECLEN (pat, 0);
8005 for (par_index = 0; par_index < limit; par_index++)
8007 rtx x = XVECEXP (pat, 0, par_index);
8008 if (GET_CODE (x) == SET)
8009 process_set (asm_out_file, x);
8024 IA64_BUILTIN_FLUSHRS
8028 ia64_init_builtins (void)
8033 /* The __fpreg type. */
8034 fpreg_type = make_node (REAL_TYPE);
8035 /* ??? The back end should know to load/save __fpreg variables using
8036 the ldf.fill and stf.spill instructions. */
8037 TYPE_PRECISION (fpreg_type) = 80;
8038 layout_type (fpreg_type);
8039 (*lang_hooks.types.register_builtin_type) (fpreg_type, "__fpreg");
8041 /* The __float80 type. */
8042 float80_type = make_node (REAL_TYPE);
8043 TYPE_PRECISION (float80_type) = 80;
8044 layout_type (float80_type);
8045 (*lang_hooks.types.register_builtin_type) (float80_type, "__float80");
8047 /* The __float128 type. */
8050 tree float128_type = make_node (REAL_TYPE);
8051 TYPE_PRECISION (float128_type) = 128;
8052 layout_type (float128_type);
8053 (*lang_hooks.types.register_builtin_type) (float128_type, "__float128");
8056 /* Under HPUX, this is a synonym for "long double". */
8057 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
8060 #define def_builtin(name, type, code) \
8061 lang_hooks.builtin_function ((name), (type), (code), BUILT_IN_MD, \
8064 def_builtin ("__builtin_ia64_bsp",
8065 build_function_type (ptr_type_node, void_list_node),
8068 def_builtin ("__builtin_ia64_flushrs",
8069 build_function_type (void_type_node, void_list_node),
8070 IA64_BUILTIN_FLUSHRS);
8076 ia64_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8077 enum machine_mode mode ATTRIBUTE_UNUSED,
8078 int ignore ATTRIBUTE_UNUSED)
8080 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
8081 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8085 case IA64_BUILTIN_BSP:
8086 if (! target || ! register_operand (target, DImode))
8087 target = gen_reg_rtx (DImode);
8088 emit_insn (gen_bsp_value (target));
8089 #ifdef POINTERS_EXTEND_UNSIGNED
8090 target = convert_memory_address (ptr_mode, target);
8094 case IA64_BUILTIN_FLUSHRS:
8095 emit_insn (gen_flushrs ());
8105 /* For the HP-UX IA64 aggregate parameters are passed stored in the
8106 most significant bits of the stack slot. */
8109 ia64_hpux_function_arg_padding (enum machine_mode mode, tree type)
8111 /* Exception to normal case for structures/unions/etc. */
8113 if (type && AGGREGATE_TYPE_P (type)
8114 && int_size_in_bytes (type) < UNITS_PER_WORD)
8117 /* Fall back to the default. */
8118 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
8121 /* Linked list of all external functions that are to be emitted by GCC.
8122 We output the name if and only if TREE_SYMBOL_REFERENCED is set in
8123 order to avoid putting out names that are never really used. */
8125 struct extern_func_list GTY(())
8127 struct extern_func_list *next;
8131 static GTY(()) struct extern_func_list *extern_func_head;
8134 ia64_hpux_add_extern_decl (tree decl)
8136 struct extern_func_list *p = ggc_alloc (sizeof (struct extern_func_list));
8139 p->next = extern_func_head;
8140 extern_func_head = p;
8143 /* Print out the list of used global functions. */
8146 ia64_hpux_file_end (void)
8148 struct extern_func_list *p;
8150 for (p = extern_func_head; p; p = p->next)
8152 tree decl = p->decl;
8153 tree id = DECL_ASSEMBLER_NAME (decl);
8157 if (!TREE_ASM_WRITTEN (decl) && TREE_SYMBOL_REFERENCED (id))
8159 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
8161 TREE_ASM_WRITTEN (decl) = 1;
8162 (*targetm.asm_out.globalize_label) (asm_out_file, name);
8163 fputs (TYPE_ASM_OP, asm_out_file);
8164 assemble_name (asm_out_file, name);
8165 fprintf (asm_out_file, "," TYPE_OPERAND_FMT "\n", "function");
8169 extern_func_head = 0;
8172 /* Set SImode div/mod functions, init_integral_libfuncs only initializes
8173 modes of word_mode and larger. Rename the TFmode libfuncs using the
8174 HPUX conventions. __divtf3 is used for XFmode. We need to keep it for
8175 backward compatibility. */
8178 ia64_init_libfuncs (void)
8180 set_optab_libfunc (sdiv_optab, SImode, "__divsi3");
8181 set_optab_libfunc (udiv_optab, SImode, "__udivsi3");
8182 set_optab_libfunc (smod_optab, SImode, "__modsi3");
8183 set_optab_libfunc (umod_optab, SImode, "__umodsi3");
8185 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
8186 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
8187 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
8188 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
8189 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
8191 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
8192 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
8193 set_conv_libfunc (sext_optab, TFmode, XFmode, "_U_Qfcnvff_f80_to_quad");
8194 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
8195 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
8196 set_conv_libfunc (trunc_optab, XFmode, TFmode, "_U_Qfcnvff_quad_to_f80");
8198 set_conv_libfunc (sfix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_sgl");
8199 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
8200 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxut_quad_to_sgl");
8201 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxut_quad_to_dbl");
8203 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
8204 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
8207 /* Rename all the TFmode libfuncs using the HPUX conventions. */
8210 ia64_hpux_init_libfuncs (void)
8212 ia64_init_libfuncs ();
8214 set_optab_libfunc (smin_optab, TFmode, "_U_Qfmin");
8215 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
8216 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
8218 /* ia64_expand_compare uses this. */
8219 cmptf_libfunc = init_one_libfunc ("_U_Qfcmp");
8221 /* These should never be used. */
8222 set_optab_libfunc (eq_optab, TFmode, 0);
8223 set_optab_libfunc (ne_optab, TFmode, 0);
8224 set_optab_libfunc (gt_optab, TFmode, 0);
8225 set_optab_libfunc (ge_optab, TFmode, 0);
8226 set_optab_libfunc (lt_optab, TFmode, 0);
8227 set_optab_libfunc (le_optab, TFmode, 0);
8230 /* Rename the division and modulus functions in VMS. */
8233 ia64_vms_init_libfuncs (void)
8235 set_optab_libfunc (sdiv_optab, SImode, "OTS$DIV_I");
8236 set_optab_libfunc (sdiv_optab, DImode, "OTS$DIV_L");
8237 set_optab_libfunc (udiv_optab, SImode, "OTS$DIV_UI");
8238 set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL");
8239 set_optab_libfunc (smod_optab, SImode, "OTS$REM_I");
8240 set_optab_libfunc (smod_optab, DImode, "OTS$REM_L");
8241 set_optab_libfunc (umod_optab, SImode, "OTS$REM_UI");
8242 set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL");
8245 /* Rename the TFmode libfuncs available from soft-fp in glibc using
8246 the HPUX conventions. */
8249 ia64_sysv4_init_libfuncs (void)
8251 ia64_init_libfuncs ();
8253 /* These functions are not part of the HPUX TFmode interface. We
8254 use them instead of _U_Qfcmp, which doesn't work the way we
8256 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
8257 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
8258 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
8259 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
8260 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
8261 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
8263 /* We leave out _U_Qfmin, _U_Qfmax and _U_Qfabs since soft-fp in
8264 glibc doesn't have them. */
8267 /* Switch to the section to which we should output X. The only thing
8268 special we do here is to honor small data. */
8271 ia64_select_rtx_section (enum machine_mode mode, rtx x,
8272 unsigned HOST_WIDE_INT align)
8274 if (GET_MODE_SIZE (mode) > 0
8275 && GET_MODE_SIZE (mode) <= ia64_section_threshold)
8278 default_elf_select_rtx_section (mode, x, align);
8281 /* It is illegal to have relocations in shared segments on AIX and HPUX.
8282 Pretend flag_pic is always set. */
8285 ia64_rwreloc_select_section (tree exp, int reloc, unsigned HOST_WIDE_INT align)
8287 default_elf_select_section_1 (exp, reloc, align, true);
8291 ia64_rwreloc_unique_section (tree decl, int reloc)
8293 default_unique_section_1 (decl, reloc, true);
8297 ia64_rwreloc_select_rtx_section (enum machine_mode mode, rtx x,
8298 unsigned HOST_WIDE_INT align)
8300 int save_pic = flag_pic;
8302 ia64_select_rtx_section (mode, x, align);
8303 flag_pic = save_pic;
8306 #ifndef TARGET_RWRELOC
8307 #define TARGET_RWRELOC flag_pic
8311 ia64_section_type_flags (tree decl, const char *name, int reloc)
8313 unsigned int flags = 0;
8315 if (strcmp (name, ".sdata") == 0
8316 || strncmp (name, ".sdata.", 7) == 0
8317 || strncmp (name, ".gnu.linkonce.s.", 16) == 0
8318 || strncmp (name, ".sdata2.", 8) == 0
8319 || strncmp (name, ".gnu.linkonce.s2.", 17) == 0
8320 || strcmp (name, ".sbss") == 0
8321 || strncmp (name, ".sbss.", 6) == 0
8322 || strncmp (name, ".gnu.linkonce.sb.", 17) == 0)
8323 flags = SECTION_SMALL;
8325 flags |= default_section_type_flags_1 (decl, name, reloc, TARGET_RWRELOC);
8329 /* Returns true if FNTYPE (a FUNCTION_TYPE or a METHOD_TYPE) returns a
8330 structure type and that the address of that type should be passed
8331 in out0, rather than in r8. */
8334 ia64_struct_retval_addr_is_first_parm_p (tree fntype)
8336 tree ret_type = TREE_TYPE (fntype);
8338 /* The Itanium C++ ABI requires that out0, rather than r8, be used
8339 as the structure return address parameter, if the return value
8340 type has a non-trivial copy constructor or destructor. It is not
8341 clear if this same convention should be used for other
8342 programming languages. Until G++ 3.4, we incorrectly used r8 for
8343 these return values. */
8344 return (abi_version_at_least (2)
8346 && TYPE_MODE (ret_type) == BLKmode
8347 && TREE_ADDRESSABLE (ret_type)
8348 && strcmp (lang_hooks.name, "GNU C++") == 0);
8351 /* Output the assembler code for a thunk function. THUNK_DECL is the
8352 declaration for the thunk function itself, FUNCTION is the decl for
8353 the target function. DELTA is an immediate constant offset to be
8354 added to THIS. If VCALL_OFFSET is nonzero, the word at
8355 *(*this + vcall_offset) should be added to THIS. */
8358 ia64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
8359 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
8362 rtx this, insn, funexp;
8363 unsigned int this_parmno;
8364 unsigned int this_regno;
8366 reload_completed = 1;
8367 epilogue_completed = 1;
8369 reset_block_changes ();
8371 /* Set things up as ia64_expand_prologue might. */
8372 last_scratch_gr_reg = 15;
8374 memset (¤t_frame_info, 0, sizeof (current_frame_info));
8375 current_frame_info.spill_cfa_off = -16;
8376 current_frame_info.n_input_regs = 1;
8377 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
8379 /* Mark the end of the (empty) prologue. */
8380 emit_note (NOTE_INSN_PROLOGUE_END);
8382 /* Figure out whether "this" will be the first parameter (the
8383 typical case) or the second parameter (as happens when the
8384 virtual function returns certain class objects). */
8386 = (ia64_struct_retval_addr_is_first_parm_p (TREE_TYPE (thunk))
8388 this_regno = IN_REG (this_parmno);
8389 if (!TARGET_REG_NAMES)
8390 reg_names[this_regno] = ia64_reg_numbers[this_parmno];
8392 this = gen_rtx_REG (Pmode, this_regno);
8395 rtx tmp = gen_rtx_REG (ptr_mode, this_regno);
8396 REG_POINTER (tmp) = 1;
8397 if (delta && CONST_OK_FOR_I (delta))
8399 emit_insn (gen_ptr_extend_plus_imm (this, tmp, GEN_INT (delta)));
8403 emit_insn (gen_ptr_extend (this, tmp));
8406 /* Apply the constant offset, if required. */
8409 rtx delta_rtx = GEN_INT (delta);
8411 if (!CONST_OK_FOR_I (delta))
8413 rtx tmp = gen_rtx_REG (Pmode, 2);
8414 emit_move_insn (tmp, delta_rtx);
8417 emit_insn (gen_adddi3 (this, this, delta_rtx));
8420 /* Apply the offset from the vtable, if required. */
8423 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
8424 rtx tmp = gen_rtx_REG (Pmode, 2);
8428 rtx t = gen_rtx_REG (ptr_mode, 2);
8429 REG_POINTER (t) = 1;
8430 emit_move_insn (t, gen_rtx_MEM (ptr_mode, this));
8431 if (CONST_OK_FOR_I (vcall_offset))
8433 emit_insn (gen_ptr_extend_plus_imm (tmp, t,
8438 emit_insn (gen_ptr_extend (tmp, t));
8441 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
8445 if (!CONST_OK_FOR_J (vcall_offset))
8447 rtx tmp2 = gen_rtx_REG (Pmode, next_scratch_gr_reg ());
8448 emit_move_insn (tmp2, vcall_offset_rtx);
8449 vcall_offset_rtx = tmp2;
8451 emit_insn (gen_adddi3 (tmp, tmp, vcall_offset_rtx));
8455 emit_move_insn (gen_rtx_REG (ptr_mode, 2),
8456 gen_rtx_MEM (ptr_mode, tmp));
8458 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
8460 emit_insn (gen_adddi3 (this, this, tmp));
8463 /* Generate a tail call to the target function. */
8464 if (! TREE_USED (function))
8466 assemble_external (function);
8467 TREE_USED (function) = 1;
8469 funexp = XEXP (DECL_RTL (function), 0);
8470 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
8471 ia64_expand_call (NULL_RTX, funexp, NULL_RTX, 1);
8472 insn = get_last_insn ();
8473 SIBLING_CALL_P (insn) = 1;
8475 /* Code generation for calls relies on splitting. */
8476 reload_completed = 1;
8477 epilogue_completed = 1;
8478 try_split (PATTERN (insn), insn, 0);
8482 /* Run just enough of rest_of_compilation to get the insns emitted.
8483 There's not really enough bulk here to make other passes such as
8484 instruction scheduling worth while. Note that use_thunk calls
8485 assemble_start_function and assemble_end_function. */
8487 insn_locators_initialize ();
8488 emit_all_insn_group_barriers (NULL);
8489 insn = get_insns ();
8490 shorten_branches (insn);
8491 final_start_function (insn, file, 1);
8492 final (insn, file, 1);
8493 final_end_function ();
8495 reload_completed = 0;
8496 epilogue_completed = 0;
8500 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
8503 ia64_struct_value_rtx (tree fntype,
8504 int incoming ATTRIBUTE_UNUSED)
8506 if (fntype && ia64_struct_retval_addr_is_first_parm_p (fntype))
8508 return gen_rtx_REG (Pmode, GR_REG (8));
8512 ia64_scalar_mode_supported_p (enum machine_mode mode)
8537 ia64_vector_mode_supported_p (enum machine_mode mode)
8554 #include "gt-ia64.h"