1 /* Definitions of target machine for GNU compiler.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
3 2009 Free Software Foundation, Inc.
4 Contributed by James E. Wilson <wilson@cygnus.com> and
5 David Mosberger <davidm@hpl.hp.com>.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
43 #include "basic-block.h"
45 #include "sched-int.h"
48 #include "target-def.h"
51 #include "langhooks.h"
52 #include "cfglayout.h"
59 #include "tm-constrs.h"
60 #include "sel-sched.h"
62 /* This is used for communication between ASM_OUTPUT_LABEL and
63 ASM_OUTPUT_LABELREF. */
64 int ia64_asm_output_label = 0;
66 /* Define the information needed to generate branch and scc insns. This is
67 stored from the compare operation. */
68 struct rtx_def * ia64_compare_op0;
69 struct rtx_def * ia64_compare_op1;
71 /* Register names for ia64_expand_prologue. */
72 static const char * const ia64_reg_numbers[96] =
73 { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
74 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
75 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
76 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
77 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
78 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
79 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
80 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
81 "r96", "r97", "r98", "r99", "r100","r101","r102","r103",
82 "r104","r105","r106","r107","r108","r109","r110","r111",
83 "r112","r113","r114","r115","r116","r117","r118","r119",
84 "r120","r121","r122","r123","r124","r125","r126","r127"};
86 /* ??? These strings could be shared with REGISTER_NAMES. */
87 static const char * const ia64_input_reg_names[8] =
88 { "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7" };
90 /* ??? These strings could be shared with REGISTER_NAMES. */
91 static const char * const ia64_local_reg_names[80] =
92 { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7",
93 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15",
94 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23",
95 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31",
96 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39",
97 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47",
98 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55",
99 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63",
100 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71",
101 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" };
103 /* ??? These strings could be shared with REGISTER_NAMES. */
104 static const char * const ia64_output_reg_names[8] =
105 { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" };
107 /* Which cpu are we scheduling for. */
108 enum processor_type ia64_tune = PROCESSOR_ITANIUM2;
110 /* Determines whether we run our final scheduling pass or not. We always
111 avoid the normal second scheduling pass. */
112 static int ia64_flag_schedule_insns2;
114 /* Determines whether we run variable tracking in machine dependent
116 static int ia64_flag_var_tracking;
118 /* Variables which are this size or smaller are put in the sdata/sbss
121 unsigned int ia64_section_threshold;
123 /* The following variable is used by the DFA insn scheduler. The value is
124 TRUE if we do insn bundling instead of insn scheduling. */
136 number_of_ia64_frame_regs
139 /* Structure to be filled in by ia64_compute_frame_size with register
140 save masks and offsets for the current function. */
142 struct ia64_frame_info
144 HOST_WIDE_INT total_size; /* size of the stack frame, not including
145 the caller's scratch area. */
146 HOST_WIDE_INT spill_cfa_off; /* top of the reg spill area from the cfa. */
147 HOST_WIDE_INT spill_size; /* size of the gr/br/fr spill area. */
148 HOST_WIDE_INT extra_spill_size; /* size of spill area for others. */
149 HARD_REG_SET mask; /* mask of saved registers. */
150 unsigned int gr_used_mask; /* mask of registers in use as gr spill
151 registers or long-term scratches. */
152 int n_spilled; /* number of spilled registers. */
153 int r[number_of_ia64_frame_regs]; /* Frame related registers. */
154 int n_input_regs; /* number of input registers used. */
155 int n_local_regs; /* number of local registers used. */
156 int n_output_regs; /* number of output registers used. */
157 int n_rotate_regs; /* number of rotating registers used. */
159 char need_regstk; /* true if a .regstk directive needed. */
160 char initialized; /* true if the data is finalized. */
163 /* Current frame information calculated by ia64_compute_frame_size. */
164 static struct ia64_frame_info current_frame_info;
165 /* The actual registers that are emitted. */
166 static int emitted_frame_related_regs[number_of_ia64_frame_regs];
168 static int ia64_first_cycle_multipass_dfa_lookahead (void);
169 static void ia64_dependencies_evaluation_hook (rtx, rtx);
170 static void ia64_init_dfa_pre_cycle_insn (void);
171 static rtx ia64_dfa_pre_cycle_insn (void);
172 static int ia64_first_cycle_multipass_dfa_lookahead_guard (rtx);
173 static bool ia64_first_cycle_multipass_dfa_lookahead_guard_spec (const_rtx);
174 static int ia64_dfa_new_cycle (FILE *, int, rtx, int, int, int *);
175 static void ia64_h_i_d_extended (void);
176 static void * ia64_alloc_sched_context (void);
177 static void ia64_init_sched_context (void *, bool);
178 static void ia64_set_sched_context (void *);
179 static void ia64_clear_sched_context (void *);
180 static void ia64_free_sched_context (void *);
181 static int ia64_mode_to_int (enum machine_mode);
182 static void ia64_set_sched_flags (spec_info_t);
183 static ds_t ia64_get_insn_spec_ds (rtx);
184 static ds_t ia64_get_insn_checked_ds (rtx);
185 static bool ia64_skip_rtx_p (const_rtx);
186 static int ia64_speculate_insn (rtx, ds_t, rtx *);
187 static bool ia64_needs_block_p (int);
188 static rtx ia64_gen_spec_check (rtx, rtx, ds_t);
189 static int ia64_spec_check_p (rtx);
190 static int ia64_spec_check_src_p (rtx);
191 static rtx gen_tls_get_addr (void);
192 static rtx gen_thread_pointer (void);
193 static int find_gr_spill (enum ia64_frame_regs, int);
194 static int next_scratch_gr_reg (void);
195 static void mark_reg_gr_used_mask (rtx, void *);
196 static void ia64_compute_frame_size (HOST_WIDE_INT);
197 static void setup_spill_pointers (int, rtx, HOST_WIDE_INT);
198 static void finish_spill_pointers (void);
199 static rtx spill_restore_mem (rtx, HOST_WIDE_INT);
200 static void do_spill (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT, rtx);
201 static void do_restore (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT);
202 static rtx gen_movdi_x (rtx, rtx, rtx);
203 static rtx gen_fr_spill_x (rtx, rtx, rtx);
204 static rtx gen_fr_restore_x (rtx, rtx, rtx);
206 static enum machine_mode hfa_element_mode (const_tree, bool);
207 static void ia64_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
209 static int ia64_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
211 static bool ia64_function_ok_for_sibcall (tree, tree);
212 static bool ia64_return_in_memory (const_tree, const_tree);
213 static bool ia64_rtx_costs (rtx, int, int, int *, bool);
214 static int ia64_unspec_may_trap_p (const_rtx, unsigned);
215 static void fix_range (const char *);
216 static bool ia64_handle_option (size_t, const char *, int);
217 static struct machine_function * ia64_init_machine_status (void);
218 static void emit_insn_group_barriers (FILE *);
219 static void emit_all_insn_group_barriers (FILE *);
220 static void final_emit_insn_group_barriers (FILE *);
221 static void emit_predicate_relation_info (void);
222 static void ia64_reorg (void);
223 static bool ia64_in_small_data_p (const_tree);
224 static void process_epilogue (FILE *, rtx, bool, bool);
225 static int process_set (FILE *, rtx, rtx, bool, bool);
227 static bool ia64_assemble_integer (rtx, unsigned int, int);
228 static void ia64_output_function_prologue (FILE *, HOST_WIDE_INT);
229 static void ia64_output_function_epilogue (FILE *, HOST_WIDE_INT);
230 static void ia64_output_function_end_prologue (FILE *);
232 static int ia64_issue_rate (void);
233 static int ia64_adjust_cost_2 (rtx, int, rtx, int, dw_t);
234 static void ia64_sched_init (FILE *, int, int);
235 static void ia64_sched_init_global (FILE *, int, int);
236 static void ia64_sched_finish_global (FILE *, int);
237 static void ia64_sched_finish (FILE *, int);
238 static int ia64_dfa_sched_reorder (FILE *, int, rtx *, int *, int, int);
239 static int ia64_sched_reorder (FILE *, int, rtx *, int *, int);
240 static int ia64_sched_reorder2 (FILE *, int, rtx *, int *, int);
241 static int ia64_variable_issue (FILE *, int, rtx, int);
243 static struct bundle_state *get_free_bundle_state (void);
244 static void free_bundle_state (struct bundle_state *);
245 static void initiate_bundle_states (void);
246 static void finish_bundle_states (void);
247 static unsigned bundle_state_hash (const void *);
248 static int bundle_state_eq_p (const void *, const void *);
249 static int insert_bundle_state (struct bundle_state *);
250 static void initiate_bundle_state_table (void);
251 static void finish_bundle_state_table (void);
252 static int try_issue_nops (struct bundle_state *, int);
253 static int try_issue_insn (struct bundle_state *, rtx);
254 static void issue_nops_and_insn (struct bundle_state *, int, rtx, int, int);
255 static int get_max_pos (state_t);
256 static int get_template (state_t, int);
258 static rtx get_next_important_insn (rtx, rtx);
259 static bool important_for_bundling_p (rtx);
260 static void bundling (FILE *, int, rtx, rtx);
262 static void ia64_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
263 HOST_WIDE_INT, tree);
264 static void ia64_file_start (void);
265 static void ia64_globalize_decl_name (FILE *, tree);
267 static int ia64_hpux_reloc_rw_mask (void) ATTRIBUTE_UNUSED;
268 static int ia64_reloc_rw_mask (void) ATTRIBUTE_UNUSED;
269 static section *ia64_select_rtx_section (enum machine_mode, rtx,
270 unsigned HOST_WIDE_INT);
271 static void ia64_output_dwarf_dtprel (FILE *, int, rtx)
273 static unsigned int ia64_section_type_flags (tree, const char *, int);
274 static void ia64_init_libfuncs (void)
276 static void ia64_hpux_init_libfuncs (void)
278 static void ia64_sysv4_init_libfuncs (void)
280 static void ia64_vms_init_libfuncs (void)
282 static void ia64_soft_fp_init_libfuncs (void)
285 static tree ia64_handle_model_attribute (tree *, tree, tree, int, bool *);
286 static tree ia64_handle_version_id_attribute (tree *, tree, tree, int, bool *);
287 static void ia64_encode_section_info (tree, rtx, int);
288 static rtx ia64_struct_value_rtx (tree, int);
289 static tree ia64_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *);
290 static bool ia64_scalar_mode_supported_p (enum machine_mode mode);
291 static bool ia64_vector_mode_supported_p (enum machine_mode mode);
292 static bool ia64_cannot_force_const_mem (rtx);
293 static const char *ia64_mangle_type (const_tree);
294 static const char *ia64_invalid_conversion (const_tree, const_tree);
295 static const char *ia64_invalid_unary_op (int, const_tree);
296 static const char *ia64_invalid_binary_op (int, const_tree, const_tree);
297 static enum machine_mode ia64_c_mode_for_suffix (char);
299 /* Table of valid machine attributes. */
300 static const struct attribute_spec ia64_attribute_table[] =
302 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
303 { "syscall_linkage", 0, 0, false, true, true, NULL },
304 { "model", 1, 1, true, false, false, ia64_handle_model_attribute },
305 { "version_id", 1, 1, true, false, false,
306 ia64_handle_version_id_attribute },
307 { NULL, 0, 0, false, false, false, NULL }
310 /* Initialize the GCC target structure. */
311 #undef TARGET_ATTRIBUTE_TABLE
312 #define TARGET_ATTRIBUTE_TABLE ia64_attribute_table
314 #undef TARGET_INIT_BUILTINS
315 #define TARGET_INIT_BUILTINS ia64_init_builtins
317 #undef TARGET_EXPAND_BUILTIN
318 #define TARGET_EXPAND_BUILTIN ia64_expand_builtin
320 #undef TARGET_ASM_BYTE_OP
321 #define TARGET_ASM_BYTE_OP "\tdata1\t"
322 #undef TARGET_ASM_ALIGNED_HI_OP
323 #define TARGET_ASM_ALIGNED_HI_OP "\tdata2\t"
324 #undef TARGET_ASM_ALIGNED_SI_OP
325 #define TARGET_ASM_ALIGNED_SI_OP "\tdata4\t"
326 #undef TARGET_ASM_ALIGNED_DI_OP
327 #define TARGET_ASM_ALIGNED_DI_OP "\tdata8\t"
328 #undef TARGET_ASM_UNALIGNED_HI_OP
329 #define TARGET_ASM_UNALIGNED_HI_OP "\tdata2.ua\t"
330 #undef TARGET_ASM_UNALIGNED_SI_OP
331 #define TARGET_ASM_UNALIGNED_SI_OP "\tdata4.ua\t"
332 #undef TARGET_ASM_UNALIGNED_DI_OP
333 #define TARGET_ASM_UNALIGNED_DI_OP "\tdata8.ua\t"
334 #undef TARGET_ASM_INTEGER
335 #define TARGET_ASM_INTEGER ia64_assemble_integer
337 #undef TARGET_ASM_FUNCTION_PROLOGUE
338 #define TARGET_ASM_FUNCTION_PROLOGUE ia64_output_function_prologue
339 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
340 #define TARGET_ASM_FUNCTION_END_PROLOGUE ia64_output_function_end_prologue
341 #undef TARGET_ASM_FUNCTION_EPILOGUE
342 #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue
344 #undef TARGET_IN_SMALL_DATA_P
345 #define TARGET_IN_SMALL_DATA_P ia64_in_small_data_p
347 #undef TARGET_SCHED_ADJUST_COST_2
348 #define TARGET_SCHED_ADJUST_COST_2 ia64_adjust_cost_2
349 #undef TARGET_SCHED_ISSUE_RATE
350 #define TARGET_SCHED_ISSUE_RATE ia64_issue_rate
351 #undef TARGET_SCHED_VARIABLE_ISSUE
352 #define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue
353 #undef TARGET_SCHED_INIT
354 #define TARGET_SCHED_INIT ia64_sched_init
355 #undef TARGET_SCHED_FINISH
356 #define TARGET_SCHED_FINISH ia64_sched_finish
357 #undef TARGET_SCHED_INIT_GLOBAL
358 #define TARGET_SCHED_INIT_GLOBAL ia64_sched_init_global
359 #undef TARGET_SCHED_FINISH_GLOBAL
360 #define TARGET_SCHED_FINISH_GLOBAL ia64_sched_finish_global
361 #undef TARGET_SCHED_REORDER
362 #define TARGET_SCHED_REORDER ia64_sched_reorder
363 #undef TARGET_SCHED_REORDER2
364 #define TARGET_SCHED_REORDER2 ia64_sched_reorder2
366 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
367 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ia64_dependencies_evaluation_hook
369 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
370 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ia64_first_cycle_multipass_dfa_lookahead
372 #undef TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN
373 #define TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN ia64_init_dfa_pre_cycle_insn
374 #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN
375 #define TARGET_SCHED_DFA_PRE_CYCLE_INSN ia64_dfa_pre_cycle_insn
377 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
378 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD\
379 ia64_first_cycle_multipass_dfa_lookahead_guard
381 #undef TARGET_SCHED_DFA_NEW_CYCLE
382 #define TARGET_SCHED_DFA_NEW_CYCLE ia64_dfa_new_cycle
384 #undef TARGET_SCHED_H_I_D_EXTENDED
385 #define TARGET_SCHED_H_I_D_EXTENDED ia64_h_i_d_extended
387 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
388 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT ia64_alloc_sched_context
390 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
391 #define TARGET_SCHED_INIT_SCHED_CONTEXT ia64_init_sched_context
393 #undef TARGET_SCHED_SET_SCHED_CONTEXT
394 #define TARGET_SCHED_SET_SCHED_CONTEXT ia64_set_sched_context
396 #undef TARGET_SCHED_CLEAR_SCHED_CONTEXT
397 #define TARGET_SCHED_CLEAR_SCHED_CONTEXT ia64_clear_sched_context
399 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
400 #define TARGET_SCHED_FREE_SCHED_CONTEXT ia64_free_sched_context
402 #undef TARGET_SCHED_SET_SCHED_FLAGS
403 #define TARGET_SCHED_SET_SCHED_FLAGS ia64_set_sched_flags
405 #undef TARGET_SCHED_GET_INSN_SPEC_DS
406 #define TARGET_SCHED_GET_INSN_SPEC_DS ia64_get_insn_spec_ds
408 #undef TARGET_SCHED_GET_INSN_CHECKED_DS
409 #define TARGET_SCHED_GET_INSN_CHECKED_DS ia64_get_insn_checked_ds
411 #undef TARGET_SCHED_SPECULATE_INSN
412 #define TARGET_SCHED_SPECULATE_INSN ia64_speculate_insn
414 #undef TARGET_SCHED_NEEDS_BLOCK_P
415 #define TARGET_SCHED_NEEDS_BLOCK_P ia64_needs_block_p
417 #undef TARGET_SCHED_GEN_SPEC_CHECK
418 #define TARGET_SCHED_GEN_SPEC_CHECK ia64_gen_spec_check
420 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD_SPEC
421 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD_SPEC\
422 ia64_first_cycle_multipass_dfa_lookahead_guard_spec
424 #undef TARGET_SCHED_SKIP_RTX_P
425 #define TARGET_SCHED_SKIP_RTX_P ia64_skip_rtx_p
427 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
428 #define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall
429 #undef TARGET_ARG_PARTIAL_BYTES
430 #define TARGET_ARG_PARTIAL_BYTES ia64_arg_partial_bytes
432 #undef TARGET_ASM_OUTPUT_MI_THUNK
433 #define TARGET_ASM_OUTPUT_MI_THUNK ia64_output_mi_thunk
434 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
435 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
437 #undef TARGET_ASM_FILE_START
438 #define TARGET_ASM_FILE_START ia64_file_start
440 #undef TARGET_ASM_GLOBALIZE_DECL_NAME
441 #define TARGET_ASM_GLOBALIZE_DECL_NAME ia64_globalize_decl_name
443 #undef TARGET_RTX_COSTS
444 #define TARGET_RTX_COSTS ia64_rtx_costs
445 #undef TARGET_ADDRESS_COST
446 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
448 #undef TARGET_UNSPEC_MAY_TRAP_P
449 #define TARGET_UNSPEC_MAY_TRAP_P ia64_unspec_may_trap_p
451 #undef TARGET_MACHINE_DEPENDENT_REORG
452 #define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg
454 #undef TARGET_ENCODE_SECTION_INFO
455 #define TARGET_ENCODE_SECTION_INFO ia64_encode_section_info
457 #undef TARGET_SECTION_TYPE_FLAGS
458 #define TARGET_SECTION_TYPE_FLAGS ia64_section_type_flags
461 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
462 #define TARGET_ASM_OUTPUT_DWARF_DTPREL ia64_output_dwarf_dtprel
465 /* ??? ABI doesn't allow us to define this. */
467 #undef TARGET_PROMOTE_FUNCTION_ARGS
468 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
471 /* ??? ABI doesn't allow us to define this. */
473 #undef TARGET_PROMOTE_FUNCTION_RETURN
474 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
477 /* ??? Investigate. */
479 #undef TARGET_PROMOTE_PROTOTYPES
480 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
483 #undef TARGET_STRUCT_VALUE_RTX
484 #define TARGET_STRUCT_VALUE_RTX ia64_struct_value_rtx
485 #undef TARGET_RETURN_IN_MEMORY
486 #define TARGET_RETURN_IN_MEMORY ia64_return_in_memory
487 #undef TARGET_SETUP_INCOMING_VARARGS
488 #define TARGET_SETUP_INCOMING_VARARGS ia64_setup_incoming_varargs
489 #undef TARGET_STRICT_ARGUMENT_NAMING
490 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
491 #undef TARGET_MUST_PASS_IN_STACK
492 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
494 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
495 #define TARGET_GIMPLIFY_VA_ARG_EXPR ia64_gimplify_va_arg
497 #undef TARGET_UNWIND_EMIT
498 #define TARGET_UNWIND_EMIT process_for_unwind_directive
500 #undef TARGET_SCALAR_MODE_SUPPORTED_P
501 #define TARGET_SCALAR_MODE_SUPPORTED_P ia64_scalar_mode_supported_p
502 #undef TARGET_VECTOR_MODE_SUPPORTED_P
503 #define TARGET_VECTOR_MODE_SUPPORTED_P ia64_vector_mode_supported_p
505 /* ia64 architecture manual 4.4.7: ... reads, writes, and flushes may occur
506 in an order different from the specified program order. */
507 #undef TARGET_RELAXED_ORDERING
508 #define TARGET_RELAXED_ORDERING true
510 #undef TARGET_DEFAULT_TARGET_FLAGS
511 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | TARGET_CPU_DEFAULT)
512 #undef TARGET_HANDLE_OPTION
513 #define TARGET_HANDLE_OPTION ia64_handle_option
515 #undef TARGET_CANNOT_FORCE_CONST_MEM
516 #define TARGET_CANNOT_FORCE_CONST_MEM ia64_cannot_force_const_mem
518 #undef TARGET_MANGLE_TYPE
519 #define TARGET_MANGLE_TYPE ia64_mangle_type
521 #undef TARGET_INVALID_CONVERSION
522 #define TARGET_INVALID_CONVERSION ia64_invalid_conversion
523 #undef TARGET_INVALID_UNARY_OP
524 #define TARGET_INVALID_UNARY_OP ia64_invalid_unary_op
525 #undef TARGET_INVALID_BINARY_OP
526 #define TARGET_INVALID_BINARY_OP ia64_invalid_binary_op
528 #undef TARGET_C_MODE_FOR_SUFFIX
529 #define TARGET_C_MODE_FOR_SUFFIX ia64_c_mode_for_suffix
531 struct gcc_target targetm = TARGET_INITIALIZER;
535 ADDR_AREA_NORMAL, /* normal address area */
536 ADDR_AREA_SMALL /* addressable by "addl" (-2MB < addr < 2MB) */
540 static GTY(()) tree small_ident1;
541 static GTY(()) tree small_ident2;
546 if (small_ident1 == 0)
548 small_ident1 = get_identifier ("small");
549 small_ident2 = get_identifier ("__small__");
553 /* Retrieve the address area that has been chosen for the given decl. */
555 static ia64_addr_area
556 ia64_get_addr_area (tree decl)
560 model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
566 id = TREE_VALUE (TREE_VALUE (model_attr));
567 if (id == small_ident1 || id == small_ident2)
568 return ADDR_AREA_SMALL;
570 return ADDR_AREA_NORMAL;
574 ia64_handle_model_attribute (tree *node, tree name, tree args,
575 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
577 ia64_addr_area addr_area = ADDR_AREA_NORMAL;
579 tree arg, decl = *node;
582 arg = TREE_VALUE (args);
583 if (arg == small_ident1 || arg == small_ident2)
585 addr_area = ADDR_AREA_SMALL;
589 warning (OPT_Wattributes, "invalid argument of %qs attribute",
590 IDENTIFIER_POINTER (name));
591 *no_add_attrs = true;
594 switch (TREE_CODE (decl))
597 if ((DECL_CONTEXT (decl) && TREE_CODE (DECL_CONTEXT (decl))
599 && !TREE_STATIC (decl))
601 error ("%Jan address area attribute cannot be specified for "
602 "local variables", decl);
603 *no_add_attrs = true;
605 area = ia64_get_addr_area (decl);
606 if (area != ADDR_AREA_NORMAL && addr_area != area)
608 error ("address area of %q+D conflicts with previous "
609 "declaration", decl);
610 *no_add_attrs = true;
615 error ("%Jaddress area attribute cannot be specified for functions",
617 *no_add_attrs = true;
621 warning (OPT_Wattributes, "%qs attribute ignored",
622 IDENTIFIER_POINTER (name));
623 *no_add_attrs = true;
631 ia64_encode_addr_area (tree decl, rtx symbol)
635 flags = SYMBOL_REF_FLAGS (symbol);
636 switch (ia64_get_addr_area (decl))
638 case ADDR_AREA_NORMAL: break;
639 case ADDR_AREA_SMALL: flags |= SYMBOL_FLAG_SMALL_ADDR; break;
640 default: gcc_unreachable ();
642 SYMBOL_REF_FLAGS (symbol) = flags;
646 ia64_encode_section_info (tree decl, rtx rtl, int first)
648 default_encode_section_info (decl, rtl, first);
650 /* Careful not to prod global register variables. */
651 if (TREE_CODE (decl) == VAR_DECL
652 && GET_CODE (DECL_RTL (decl)) == MEM
653 && GET_CODE (XEXP (DECL_RTL (decl), 0)) == SYMBOL_REF
654 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
655 ia64_encode_addr_area (decl, XEXP (rtl, 0));
658 /* Return 1 if the operands of a move are ok. */
661 ia64_move_ok (rtx dst, rtx src)
663 /* If we're under init_recog_no_volatile, we'll not be able to use
664 memory_operand. So check the code directly and don't worry about
665 the validity of the underlying address, which should have been
666 checked elsewhere anyway. */
667 if (GET_CODE (dst) != MEM)
669 if (GET_CODE (src) == MEM)
671 if (register_operand (src, VOIDmode))
674 /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0. */
675 if (INTEGRAL_MODE_P (GET_MODE (dst)))
676 return src == const0_rtx;
678 return satisfies_constraint_G (src);
681 /* Return 1 if the operands are ok for a floating point load pair. */
684 ia64_load_pair_ok (rtx dst, rtx src)
686 if (GET_CODE (dst) != REG || !FP_REGNO_P (REGNO (dst)))
688 if (GET_CODE (src) != MEM || MEM_VOLATILE_P (src))
690 switch (GET_CODE (XEXP (src, 0)))
699 rtx adjust = XEXP (XEXP (XEXP (src, 0), 1), 1);
701 if (GET_CODE (adjust) != CONST_INT
702 || INTVAL (adjust) != GET_MODE_SIZE (GET_MODE (src)))
713 addp4_optimize_ok (rtx op1, rtx op2)
715 return (basereg_operand (op1, GET_MODE(op1)) !=
716 basereg_operand (op2, GET_MODE(op2)));
719 /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction.
720 Return the length of the field, or <= 0 on failure. */
723 ia64_depz_field_mask (rtx rop, rtx rshift)
725 unsigned HOST_WIDE_INT op = INTVAL (rop);
726 unsigned HOST_WIDE_INT shift = INTVAL (rshift);
728 /* Get rid of the zero bits we're shifting in. */
731 /* We must now have a solid block of 1's at bit 0. */
732 return exact_log2 (op + 1);
735 /* Return the TLS model to use for ADDR. */
737 static enum tls_model
738 tls_symbolic_operand_type (rtx addr)
740 enum tls_model tls_kind = 0;
742 if (GET_CODE (addr) == CONST)
744 if (GET_CODE (XEXP (addr, 0)) == PLUS
745 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF)
746 tls_kind = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (addr, 0), 0));
748 else if (GET_CODE (addr) == SYMBOL_REF)
749 tls_kind = SYMBOL_REF_TLS_MODEL (addr);
754 /* Return true if X is a constant that is valid for some immediate
755 field in an instruction. */
758 ia64_legitimate_constant_p (rtx x)
760 switch (GET_CODE (x))
767 if (GET_MODE (x) == VOIDmode)
769 return satisfies_constraint_G (x);
773 /* ??? Short term workaround for PR 28490. We must make the code here
774 match the code in ia64_expand_move and move_operand, even though they
775 are both technically wrong. */
776 if (tls_symbolic_operand_type (x) == 0)
778 HOST_WIDE_INT addend = 0;
781 if (GET_CODE (op) == CONST
782 && GET_CODE (XEXP (op, 0)) == PLUS
783 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
785 addend = INTVAL (XEXP (XEXP (op, 0), 1));
786 op = XEXP (XEXP (op, 0), 0);
789 if (any_offset_symbol_operand (op, GET_MODE (op))
790 || function_operand (op, GET_MODE (op)))
792 if (aligned_offset_symbol_operand (op, GET_MODE (op)))
793 return (addend & 0x3fff) == 0;
800 enum machine_mode mode = GET_MODE (x);
802 if (mode == V2SFmode)
803 return satisfies_constraint_Y (x);
805 return (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
806 && GET_MODE_SIZE (mode) <= 8);
814 /* Don't allow TLS addresses to get spilled to memory. */
817 ia64_cannot_force_const_mem (rtx x)
819 if (GET_MODE (x) == RFmode)
821 return tls_symbolic_operand_type (x) != 0;
824 /* Expand a symbolic constant load. */
827 ia64_expand_load_address (rtx dest, rtx src)
829 gcc_assert (GET_CODE (dest) == REG);
831 /* ILP32 mode still loads 64-bits of data from the GOT. This avoids
832 having to pointer-extend the value afterward. Other forms of address
833 computation below are also more natural to compute as 64-bit quantities.
834 If we've been given an SImode destination register, change it. */
835 if (GET_MODE (dest) != Pmode)
836 dest = gen_rtx_REG_offset (dest, Pmode, REGNO (dest),
837 byte_lowpart_offset (Pmode, GET_MODE (dest)));
841 if (small_addr_symbolic_operand (src, VOIDmode))
845 emit_insn (gen_load_gprel64 (dest, src));
846 else if (GET_CODE (src) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (src))
847 emit_insn (gen_load_fptr (dest, src));
848 else if (sdata_symbolic_operand (src, VOIDmode))
849 emit_insn (gen_load_gprel (dest, src));
852 HOST_WIDE_INT addend = 0;
855 /* We did split constant offsets in ia64_expand_move, and we did try
856 to keep them split in move_operand, but we also allowed reload to
857 rematerialize arbitrary constants rather than spill the value to
858 the stack and reload it. So we have to be prepared here to split
860 if (GET_CODE (src) == CONST)
862 HOST_WIDE_INT hi, lo;
864 hi = INTVAL (XEXP (XEXP (src, 0), 1));
865 lo = ((hi & 0x3fff) ^ 0x2000) - 0x2000;
871 src = plus_constant (XEXP (XEXP (src, 0), 0), hi);
875 tmp = gen_rtx_HIGH (Pmode, src);
876 tmp = gen_rtx_PLUS (Pmode, tmp, pic_offset_table_rtx);
877 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
879 tmp = gen_rtx_LO_SUM (Pmode, dest, src);
880 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
884 tmp = gen_rtx_PLUS (Pmode, dest, GEN_INT (addend));
885 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
892 static GTY(()) rtx gen_tls_tga;
894 gen_tls_get_addr (void)
897 gen_tls_tga = init_one_libfunc ("__tls_get_addr");
901 static GTY(()) rtx thread_pointer_rtx;
903 gen_thread_pointer (void)
905 if (!thread_pointer_rtx)
906 thread_pointer_rtx = gen_rtx_REG (Pmode, 13);
907 return thread_pointer_rtx;
911 ia64_expand_tls_address (enum tls_model tls_kind, rtx op0, rtx op1,
912 rtx orig_op1, HOST_WIDE_INT addend)
914 rtx tga_op1, tga_op2, tga_ret, tga_eqv, tmp, insns;
916 HOST_WIDE_INT addend_lo, addend_hi;
920 case TLS_MODEL_GLOBAL_DYNAMIC:
923 tga_op1 = gen_reg_rtx (Pmode);
924 emit_insn (gen_load_dtpmod (tga_op1, op1));
926 tga_op2 = gen_reg_rtx (Pmode);
927 emit_insn (gen_load_dtprel (tga_op2, op1));
929 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
930 LCT_CONST, Pmode, 2, tga_op1,
931 Pmode, tga_op2, Pmode);
933 insns = get_insns ();
936 if (GET_MODE (op0) != Pmode)
938 emit_libcall_block (insns, op0, tga_ret, op1);
941 case TLS_MODEL_LOCAL_DYNAMIC:
942 /* ??? This isn't the completely proper way to do local-dynamic
943 If the call to __tls_get_addr is used only by a single symbol,
944 then we should (somehow) move the dtprel to the second arg
945 to avoid the extra add. */
948 tga_op1 = gen_reg_rtx (Pmode);
949 emit_insn (gen_load_dtpmod (tga_op1, op1));
951 tga_op2 = const0_rtx;
953 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
954 LCT_CONST, Pmode, 2, tga_op1,
955 Pmode, tga_op2, Pmode);
957 insns = get_insns ();
960 tga_eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
962 tmp = gen_reg_rtx (Pmode);
963 emit_libcall_block (insns, tmp, tga_ret, tga_eqv);
965 if (!register_operand (op0, Pmode))
966 op0 = gen_reg_rtx (Pmode);
969 emit_insn (gen_load_dtprel (op0, op1));
970 emit_insn (gen_adddi3 (op0, tmp, op0));
973 emit_insn (gen_add_dtprel (op0, op1, tmp));
976 case TLS_MODEL_INITIAL_EXEC:
977 addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000;
978 addend_hi = addend - addend_lo;
980 op1 = plus_constant (op1, addend_hi);
983 tmp = gen_reg_rtx (Pmode);
984 emit_insn (gen_load_tprel (tmp, op1));
986 if (!register_operand (op0, Pmode))
987 op0 = gen_reg_rtx (Pmode);
988 emit_insn (gen_adddi3 (op0, tmp, gen_thread_pointer ()));
991 case TLS_MODEL_LOCAL_EXEC:
992 if (!register_operand (op0, Pmode))
993 op0 = gen_reg_rtx (Pmode);
999 emit_insn (gen_load_tprel (op0, op1));
1000 emit_insn (gen_adddi3 (op0, op0, gen_thread_pointer ()));
1003 emit_insn (gen_add_tprel (op0, op1, gen_thread_pointer ()));
1011 op0 = expand_simple_binop (Pmode, PLUS, op0, GEN_INT (addend),
1012 orig_op0, 1, OPTAB_DIRECT);
1013 if (orig_op0 == op0)
1015 if (GET_MODE (orig_op0) == Pmode)
1017 return gen_lowpart (GET_MODE (orig_op0), op0);
1021 ia64_expand_move (rtx op0, rtx op1)
1023 enum machine_mode mode = GET_MODE (op0);
1025 if (!reload_in_progress && !reload_completed && !ia64_move_ok (op0, op1))
1026 op1 = force_reg (mode, op1);
1028 if ((mode == Pmode || mode == ptr_mode) && symbolic_operand (op1, VOIDmode))
1030 HOST_WIDE_INT addend = 0;
1031 enum tls_model tls_kind;
1034 if (GET_CODE (op1) == CONST
1035 && GET_CODE (XEXP (op1, 0)) == PLUS
1036 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT)
1038 addend = INTVAL (XEXP (XEXP (op1, 0), 1));
1039 sym = XEXP (XEXP (op1, 0), 0);
1042 tls_kind = tls_symbolic_operand_type (sym);
1044 return ia64_expand_tls_address (tls_kind, op0, sym, op1, addend);
1046 if (any_offset_symbol_operand (sym, mode))
1048 else if (aligned_offset_symbol_operand (sym, mode))
1050 HOST_WIDE_INT addend_lo, addend_hi;
1052 addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000;
1053 addend_hi = addend - addend_lo;
1057 op1 = plus_constant (sym, addend_hi);
1066 if (reload_completed)
1068 /* We really should have taken care of this offset earlier. */
1069 gcc_assert (addend == 0);
1070 if (ia64_expand_load_address (op0, op1))
1076 rtx subtarget = !can_create_pseudo_p () ? op0 : gen_reg_rtx (mode);
1078 emit_insn (gen_rtx_SET (VOIDmode, subtarget, op1));
1080 op1 = expand_simple_binop (mode, PLUS, subtarget,
1081 GEN_INT (addend), op0, 1, OPTAB_DIRECT);
1090 /* Split a move from OP1 to OP0 conditional on COND. */
1093 ia64_emit_cond_move (rtx op0, rtx op1, rtx cond)
1095 rtx insn, first = get_last_insn ();
1097 emit_move_insn (op0, op1);
1099 for (insn = get_last_insn (); insn != first; insn = PREV_INSN (insn))
1101 PATTERN (insn) = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond),
1105 /* Split a post-reload TImode or TFmode reference into two DImode
1106 components. This is made extra difficult by the fact that we do
1107 not get any scratch registers to work with, because reload cannot
1108 be prevented from giving us a scratch that overlaps the register
1109 pair involved. So instead, when addressing memory, we tweak the
1110 pointer register up and back down with POST_INCs. Or up and not
1111 back down when we can get away with it.
1113 REVERSED is true when the loads must be done in reversed order
1114 (high word first) for correctness. DEAD is true when the pointer
1115 dies with the second insn we generate and therefore the second
1116 address must not carry a postmodify.
1118 May return an insn which is to be emitted after the moves. */
1121 ia64_split_tmode (rtx out[2], rtx in, bool reversed, bool dead)
1125 switch (GET_CODE (in))
1128 out[reversed] = gen_rtx_REG (DImode, REGNO (in));
1129 out[!reversed] = gen_rtx_REG (DImode, REGNO (in) + 1);
1134 /* Cannot occur reversed. */
1135 gcc_assert (!reversed);
1137 if (GET_MODE (in) != TFmode)
1138 split_double (in, &out[0], &out[1]);
1140 /* split_double does not understand how to split a TFmode
1141 quantity into a pair of DImode constants. */
1144 unsigned HOST_WIDE_INT p[2];
1145 long l[4]; /* TFmode is 128 bits */
1147 REAL_VALUE_FROM_CONST_DOUBLE (r, in);
1148 real_to_target (l, &r, TFmode);
1150 if (FLOAT_WORDS_BIG_ENDIAN)
1152 p[0] = (((unsigned HOST_WIDE_INT) l[0]) << 32) + l[1];
1153 p[1] = (((unsigned HOST_WIDE_INT) l[2]) << 32) + l[3];
1157 p[0] = (((unsigned HOST_WIDE_INT) l[1]) << 32) + l[0];
1158 p[1] = (((unsigned HOST_WIDE_INT) l[3]) << 32) + l[2];
1160 out[0] = GEN_INT (p[0]);
1161 out[1] = GEN_INT (p[1]);
1167 rtx base = XEXP (in, 0);
1170 switch (GET_CODE (base))
1175 out[0] = adjust_automodify_address
1176 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1177 out[1] = adjust_automodify_address
1178 (in, DImode, dead ? 0 : gen_rtx_POST_DEC (Pmode, base), 8);
1182 /* Reversal requires a pre-increment, which can only
1183 be done as a separate insn. */
1184 emit_insn (gen_adddi3 (base, base, GEN_INT (8)));
1185 out[0] = adjust_automodify_address
1186 (in, DImode, gen_rtx_POST_DEC (Pmode, base), 8);
1187 out[1] = adjust_address (in, DImode, 0);
1192 gcc_assert (!reversed && !dead);
1194 /* Just do the increment in two steps. */
1195 out[0] = adjust_automodify_address (in, DImode, 0, 0);
1196 out[1] = adjust_automodify_address (in, DImode, 0, 8);
1200 gcc_assert (!reversed && !dead);
1202 /* Add 8, subtract 24. */
1203 base = XEXP (base, 0);
1204 out[0] = adjust_automodify_address
1205 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1206 out[1] = adjust_automodify_address
1208 gen_rtx_POST_MODIFY (Pmode, base, plus_constant (base, -24)),
1213 gcc_assert (!reversed && !dead);
1215 /* Extract and adjust the modification. This case is
1216 trickier than the others, because we might have an
1217 index register, or we might have a combined offset that
1218 doesn't fit a signed 9-bit displacement field. We can
1219 assume the incoming expression is already legitimate. */
1220 offset = XEXP (base, 1);
1221 base = XEXP (base, 0);
1223 out[0] = adjust_automodify_address
1224 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1226 if (GET_CODE (XEXP (offset, 1)) == REG)
1228 /* Can't adjust the postmodify to match. Emit the
1229 original, then a separate addition insn. */
1230 out[1] = adjust_automodify_address (in, DImode, 0, 8);
1231 fixup = gen_adddi3 (base, base, GEN_INT (-8));
1235 gcc_assert (GET_CODE (XEXP (offset, 1)) == CONST_INT);
1236 if (INTVAL (XEXP (offset, 1)) < -256 + 8)
1238 /* Again the postmodify cannot be made to match,
1239 but in this case it's more efficient to get rid
1240 of the postmodify entirely and fix up with an
1242 out[1] = adjust_automodify_address (in, DImode, base, 8);
1244 (base, base, GEN_INT (INTVAL (XEXP (offset, 1)) - 8));
1248 /* Combined offset still fits in the displacement field.
1249 (We cannot overflow it at the high end.) */
1250 out[1] = adjust_automodify_address
1251 (in, DImode, gen_rtx_POST_MODIFY
1252 (Pmode, base, gen_rtx_PLUS
1254 GEN_INT (INTVAL (XEXP (offset, 1)) - 8))),
1273 /* Split a TImode or TFmode move instruction after reload.
1274 This is used by *movtf_internal and *movti_internal. */
1276 ia64_split_tmode_move (rtx operands[])
1278 rtx in[2], out[2], insn;
1281 bool reversed = false;
1283 /* It is possible for reload to decide to overwrite a pointer with
1284 the value it points to. In that case we have to do the loads in
1285 the appropriate order so that the pointer is not destroyed too
1286 early. Also we must not generate a postmodify for that second
1287 load, or rws_access_regno will die. */
1288 if (GET_CODE (operands[1]) == MEM
1289 && reg_overlap_mentioned_p (operands[0], operands[1]))
1291 rtx base = XEXP (operands[1], 0);
1292 while (GET_CODE (base) != REG)
1293 base = XEXP (base, 0);
1295 if (REGNO (base) == REGNO (operands[0]))
1299 /* Another reason to do the moves in reversed order is if the first
1300 element of the target register pair is also the second element of
1301 the source register pair. */
1302 if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
1303 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
1306 fixup[0] = ia64_split_tmode (in, operands[1], reversed, dead);
1307 fixup[1] = ia64_split_tmode (out, operands[0], reversed, dead);
1309 #define MAYBE_ADD_REG_INC_NOTE(INSN, EXP) \
1310 if (GET_CODE (EXP) == MEM \
1311 && (GET_CODE (XEXP (EXP, 0)) == POST_MODIFY \
1312 || GET_CODE (XEXP (EXP, 0)) == POST_INC \
1313 || GET_CODE (XEXP (EXP, 0)) == POST_DEC)) \
1314 REG_NOTES (INSN) = gen_rtx_EXPR_LIST (REG_INC, \
1315 XEXP (XEXP (EXP, 0), 0), \
1318 insn = emit_insn (gen_rtx_SET (VOIDmode, out[0], in[0]));
1319 MAYBE_ADD_REG_INC_NOTE (insn, in[0]);
1320 MAYBE_ADD_REG_INC_NOTE (insn, out[0]);
1322 insn = emit_insn (gen_rtx_SET (VOIDmode, out[1], in[1]));
1323 MAYBE_ADD_REG_INC_NOTE (insn, in[1]);
1324 MAYBE_ADD_REG_INC_NOTE (insn, out[1]);
1327 emit_insn (fixup[0]);
1329 emit_insn (fixup[1]);
1331 #undef MAYBE_ADD_REG_INC_NOTE
1334 /* ??? Fixing GR->FR XFmode moves during reload is hard. You need to go
1335 through memory plus an extra GR scratch register. Except that you can
1336 either get the first from SECONDARY_MEMORY_NEEDED or the second from
1337 SECONDARY_RELOAD_CLASS, but not both.
1339 We got into problems in the first place by allowing a construct like
1340 (subreg:XF (reg:TI)), which we got from a union containing a long double.
1341 This solution attempts to prevent this situation from occurring. When
1342 we see something like the above, we spill the inner register to memory. */
1345 spill_xfmode_rfmode_operand (rtx in, int force, enum machine_mode mode)
1347 if (GET_CODE (in) == SUBREG
1348 && GET_MODE (SUBREG_REG (in)) == TImode
1349 && GET_CODE (SUBREG_REG (in)) == REG)
1351 rtx memt = assign_stack_temp (TImode, 16, 0);
1352 emit_move_insn (memt, SUBREG_REG (in));
1353 return adjust_address (memt, mode, 0);
1355 else if (force && GET_CODE (in) == REG)
1357 rtx memx = assign_stack_temp (mode, 16, 0);
1358 emit_move_insn (memx, in);
1365 /* Expand the movxf or movrf pattern (MODE says which) with the given
1366 OPERANDS, returning true if the pattern should then invoke
1370 ia64_expand_movxf_movrf (enum machine_mode mode, rtx operands[])
1372 rtx op0 = operands[0];
1374 if (GET_CODE (op0) == SUBREG)
1375 op0 = SUBREG_REG (op0);
1377 /* We must support XFmode loads into general registers for stdarg/vararg,
1378 unprototyped calls, and a rare case where a long double is passed as
1379 an argument after a float HFA fills the FP registers. We split them into
1380 DImode loads for convenience. We also need to support XFmode stores
1381 for the last case. This case does not happen for stdarg/vararg routines,
1382 because we do a block store to memory of unnamed arguments. */
1384 if (GET_CODE (op0) == REG && GR_REGNO_P (REGNO (op0)))
1388 /* We're hoping to transform everything that deals with XFmode
1389 quantities and GR registers early in the compiler. */
1390 gcc_assert (can_create_pseudo_p ());
1392 /* Struct to register can just use TImode instead. */
1393 if ((GET_CODE (operands[1]) == SUBREG
1394 && GET_MODE (SUBREG_REG (operands[1])) == TImode)
1395 || (GET_CODE (operands[1]) == REG
1396 && GR_REGNO_P (REGNO (operands[1]))))
1398 rtx op1 = operands[1];
1400 if (GET_CODE (op1) == SUBREG)
1401 op1 = SUBREG_REG (op1);
1403 op1 = gen_rtx_REG (TImode, REGNO (op1));
1405 emit_move_insn (gen_rtx_REG (TImode, REGNO (op0)), op1);
1409 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1411 /* Don't word-swap when reading in the constant. */
1412 emit_move_insn (gen_rtx_REG (DImode, REGNO (op0)),
1413 operand_subword (operands[1], WORDS_BIG_ENDIAN,
1415 emit_move_insn (gen_rtx_REG (DImode, REGNO (op0) + 1),
1416 operand_subword (operands[1], !WORDS_BIG_ENDIAN,
1421 /* If the quantity is in a register not known to be GR, spill it. */
1422 if (register_operand (operands[1], mode))
1423 operands[1] = spill_xfmode_rfmode_operand (operands[1], 1, mode);
1425 gcc_assert (GET_CODE (operands[1]) == MEM);
1427 /* Don't word-swap when reading in the value. */
1428 out[0] = gen_rtx_REG (DImode, REGNO (op0));
1429 out[1] = gen_rtx_REG (DImode, REGNO (op0) + 1);
1431 emit_move_insn (out[0], adjust_address (operands[1], DImode, 0));
1432 emit_move_insn (out[1], adjust_address (operands[1], DImode, 8));
1436 if (GET_CODE (operands[1]) == REG && GR_REGNO_P (REGNO (operands[1])))
1438 /* We're hoping to transform everything that deals with XFmode
1439 quantities and GR registers early in the compiler. */
1440 gcc_assert (can_create_pseudo_p ());
1442 /* Op0 can't be a GR_REG here, as that case is handled above.
1443 If op0 is a register, then we spill op1, so that we now have a
1444 MEM operand. This requires creating an XFmode subreg of a TImode reg
1445 to force the spill. */
1446 if (register_operand (operands[0], mode))
1448 rtx op1 = gen_rtx_REG (TImode, REGNO (operands[1]));
1449 op1 = gen_rtx_SUBREG (mode, op1, 0);
1450 operands[1] = spill_xfmode_rfmode_operand (op1, 0, mode);
1457 gcc_assert (GET_CODE (operands[0]) == MEM);
1459 /* Don't word-swap when writing out the value. */
1460 in[0] = gen_rtx_REG (DImode, REGNO (operands[1]));
1461 in[1] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1);
1463 emit_move_insn (adjust_address (operands[0], DImode, 0), in[0]);
1464 emit_move_insn (adjust_address (operands[0], DImode, 8), in[1]);
1469 if (!reload_in_progress && !reload_completed)
1471 operands[1] = spill_xfmode_rfmode_operand (operands[1], 0, mode);
1473 if (GET_MODE (op0) == TImode && GET_CODE (op0) == REG)
1475 rtx memt, memx, in = operands[1];
1476 if (CONSTANT_P (in))
1477 in = validize_mem (force_const_mem (mode, in));
1478 if (GET_CODE (in) == MEM)
1479 memt = adjust_address (in, TImode, 0);
1482 memt = assign_stack_temp (TImode, 16, 0);
1483 memx = adjust_address (memt, mode, 0);
1484 emit_move_insn (memx, in);
1486 emit_move_insn (op0, memt);
1490 if (!ia64_move_ok (operands[0], operands[1]))
1491 operands[1] = force_reg (mode, operands[1]);
1497 /* Emit comparison instruction if necessary, returning the expression
1498 that holds the compare result in the proper mode. */
1500 static GTY(()) rtx cmptf_libfunc;
1503 ia64_expand_compare (enum rtx_code code, enum machine_mode mode)
1505 rtx op0 = ia64_compare_op0, op1 = ia64_compare_op1;
1508 /* If we have a BImode input, then we already have a compare result, and
1509 do not need to emit another comparison. */
1510 if (GET_MODE (op0) == BImode)
1512 gcc_assert ((code == NE || code == EQ) && op1 == const0_rtx);
1515 /* HPUX TFmode compare requires a library call to _U_Qfcmp, which takes a
1516 magic number as its third argument, that indicates what to do.
1517 The return value is an integer to be compared against zero. */
1518 else if (TARGET_HPUX && GET_MODE (op0) == TFmode)
1521 QCMP_INV = 1, /* Raise FP_INVALID on SNaN as a side effect. */
1527 enum rtx_code ncode;
1530 gcc_assert (cmptf_libfunc && GET_MODE (op1) == TFmode);
1533 /* 1 = equal, 0 = not equal. Equality operators do
1534 not raise FP_INVALID when given an SNaN operand. */
1535 case EQ: magic = QCMP_EQ; ncode = NE; break;
1536 case NE: magic = QCMP_EQ; ncode = EQ; break;
1537 /* isunordered() from C99. */
1538 case UNORDERED: magic = QCMP_UNORD; ncode = NE; break;
1539 case ORDERED: magic = QCMP_UNORD; ncode = EQ; break;
1540 /* Relational operators raise FP_INVALID when given
1542 case LT: magic = QCMP_LT |QCMP_INV; ncode = NE; break;
1543 case LE: magic = QCMP_LT|QCMP_EQ|QCMP_INV; ncode = NE; break;
1544 case GT: magic = QCMP_GT |QCMP_INV; ncode = NE; break;
1545 case GE: magic = QCMP_GT|QCMP_EQ|QCMP_INV; ncode = NE; break;
1546 /* FUTURE: Implement UNEQ, UNLT, UNLE, UNGT, UNGE, LTGT.
1547 Expanders for buneq etc. weuld have to be added to ia64.md
1548 for this to be useful. */
1549 default: gcc_unreachable ();
1554 ret = emit_library_call_value (cmptf_libfunc, 0, LCT_CONST, DImode, 3,
1555 op0, TFmode, op1, TFmode,
1556 GEN_INT (magic), DImode);
1557 cmp = gen_reg_rtx (BImode);
1558 emit_insn (gen_rtx_SET (VOIDmode, cmp,
1559 gen_rtx_fmt_ee (ncode, BImode,
1562 insns = get_insns ();
1565 emit_libcall_block (insns, cmp, cmp,
1566 gen_rtx_fmt_ee (code, BImode, op0, op1));
1571 cmp = gen_reg_rtx (BImode);
1572 emit_insn (gen_rtx_SET (VOIDmode, cmp,
1573 gen_rtx_fmt_ee (code, BImode, op0, op1)));
1577 return gen_rtx_fmt_ee (code, mode, cmp, const0_rtx);
1580 /* Generate an integral vector comparison. Return true if the condition has
1581 been reversed, and so the sense of the comparison should be inverted. */
1584 ia64_expand_vecint_compare (enum rtx_code code, enum machine_mode mode,
1585 rtx dest, rtx op0, rtx op1)
1587 bool negate = false;
1590 /* Canonicalize the comparison to EQ, GT, GTU. */
1601 code = reverse_condition (code);
1607 code = reverse_condition (code);
1613 code = swap_condition (code);
1614 x = op0, op0 = op1, op1 = x;
1621 /* Unsigned parallel compare is not supported by the hardware. Play some
1622 tricks to turn this into a signed comparison against 0. */
1631 /* Perform a parallel modulo subtraction. */
1632 t1 = gen_reg_rtx (V2SImode);
1633 emit_insn (gen_subv2si3 (t1, op0, op1));
1635 /* Extract the original sign bit of op0. */
1636 mask = GEN_INT (-0x80000000);
1637 mask = gen_rtx_CONST_VECTOR (V2SImode, gen_rtvec (2, mask, mask));
1638 mask = force_reg (V2SImode, mask);
1639 t2 = gen_reg_rtx (V2SImode);
1640 emit_insn (gen_andv2si3 (t2, op0, mask));
1642 /* XOR it back into the result of the subtraction. This results
1643 in the sign bit set iff we saw unsigned underflow. */
1644 x = gen_reg_rtx (V2SImode);
1645 emit_insn (gen_xorv2si3 (x, t1, t2));
1649 op1 = CONST0_RTX (mode);
1655 /* Perform a parallel unsigned saturating subtraction. */
1656 x = gen_reg_rtx (mode);
1657 emit_insn (gen_rtx_SET (VOIDmode, x,
1658 gen_rtx_US_MINUS (mode, op0, op1)));
1662 op1 = CONST0_RTX (mode);
1671 x = gen_rtx_fmt_ee (code, mode, op0, op1);
1672 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
1677 /* Emit an integral vector conditional move. */
1680 ia64_expand_vecint_cmov (rtx operands[])
1682 enum machine_mode mode = GET_MODE (operands[0]);
1683 enum rtx_code code = GET_CODE (operands[3]);
1687 cmp = gen_reg_rtx (mode);
1688 negate = ia64_expand_vecint_compare (code, mode, cmp,
1689 operands[4], operands[5]);
1691 ot = operands[1+negate];
1692 of = operands[2-negate];
1694 if (ot == CONST0_RTX (mode))
1696 if (of == CONST0_RTX (mode))
1698 emit_move_insn (operands[0], ot);
1702 x = gen_rtx_NOT (mode, cmp);
1703 x = gen_rtx_AND (mode, x, of);
1704 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1706 else if (of == CONST0_RTX (mode))
1708 x = gen_rtx_AND (mode, cmp, ot);
1709 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1715 t = gen_reg_rtx (mode);
1716 x = gen_rtx_AND (mode, cmp, operands[1+negate]);
1717 emit_insn (gen_rtx_SET (VOIDmode, t, x));
1719 f = gen_reg_rtx (mode);
1720 x = gen_rtx_NOT (mode, cmp);
1721 x = gen_rtx_AND (mode, x, operands[2-negate]);
1722 emit_insn (gen_rtx_SET (VOIDmode, f, x));
1724 x = gen_rtx_IOR (mode, t, f);
1725 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1729 /* Emit an integral vector min or max operation. Return true if all done. */
1732 ia64_expand_vecint_minmax (enum rtx_code code, enum machine_mode mode,
1737 /* These four combinations are supported directly. */
1738 if (mode == V8QImode && (code == UMIN || code == UMAX))
1740 if (mode == V4HImode && (code == SMIN || code == SMAX))
1743 /* This combination can be implemented with only saturating subtraction. */
1744 if (mode == V4HImode && code == UMAX)
1746 rtx x, tmp = gen_reg_rtx (mode);
1748 x = gen_rtx_US_MINUS (mode, operands[1], operands[2]);
1749 emit_insn (gen_rtx_SET (VOIDmode, tmp, x));
1751 emit_insn (gen_addv4hi3 (operands[0], tmp, operands[2]));
1755 /* Everything else implemented via vector comparisons. */
1756 xops[0] = operands[0];
1757 xops[4] = xops[1] = operands[1];
1758 xops[5] = xops[2] = operands[2];
1777 xops[3] = gen_rtx_fmt_ee (code, VOIDmode, operands[1], operands[2]);
1779 ia64_expand_vecint_cmov (xops);
1783 /* Emit an integral vector widening sum operations. */
1786 ia64_expand_widen_sum (rtx operands[3], bool unsignedp)
1789 enum machine_mode wmode, mode;
1790 rtx (*unpack_l) (rtx, rtx, rtx);
1791 rtx (*unpack_h) (rtx, rtx, rtx);
1792 rtx (*plus) (rtx, rtx, rtx);
1794 wmode = GET_MODE (operands[0]);
1795 mode = GET_MODE (operands[1]);
1800 unpack_l = gen_unpack1_l;
1801 unpack_h = gen_unpack1_h;
1802 plus = gen_addv4hi3;
1805 unpack_l = gen_unpack2_l;
1806 unpack_h = gen_unpack2_h;
1807 plus = gen_addv2si3;
1813 /* Fill in x with the sign extension of each element in op1. */
1815 x = CONST0_RTX (mode);
1820 x = gen_reg_rtx (mode);
1822 neg = ia64_expand_vecint_compare (LT, mode, x, operands[1],
1827 l = gen_reg_rtx (wmode);
1828 h = gen_reg_rtx (wmode);
1829 s = gen_reg_rtx (wmode);
1831 emit_insn (unpack_l (gen_lowpart (mode, l), operands[1], x));
1832 emit_insn (unpack_h (gen_lowpart (mode, h), operands[1], x));
1833 emit_insn (plus (s, l, operands[2]));
1834 emit_insn (plus (operands[0], h, s));
1837 /* Emit a signed or unsigned V8QI dot product operation. */
1840 ia64_expand_dot_prod_v8qi (rtx operands[4], bool unsignedp)
1842 rtx l1, l2, h1, h2, x1, x2, p1, p2, p3, p4, s1, s2, s3;
1844 /* Fill in x1 and x2 with the sign extension of each element. */
1846 x1 = x2 = CONST0_RTX (V8QImode);
1851 x1 = gen_reg_rtx (V8QImode);
1852 x2 = gen_reg_rtx (V8QImode);
1854 neg = ia64_expand_vecint_compare (LT, V8QImode, x1, operands[1],
1855 CONST0_RTX (V8QImode));
1857 neg = ia64_expand_vecint_compare (LT, V8QImode, x2, operands[2],
1858 CONST0_RTX (V8QImode));
1862 l1 = gen_reg_rtx (V4HImode);
1863 l2 = gen_reg_rtx (V4HImode);
1864 h1 = gen_reg_rtx (V4HImode);
1865 h2 = gen_reg_rtx (V4HImode);
1867 emit_insn (gen_unpack1_l (gen_lowpart (V8QImode, l1), operands[1], x1));
1868 emit_insn (gen_unpack1_l (gen_lowpart (V8QImode, l2), operands[2], x2));
1869 emit_insn (gen_unpack1_h (gen_lowpart (V8QImode, h1), operands[1], x1));
1870 emit_insn (gen_unpack1_h (gen_lowpart (V8QImode, h2), operands[2], x2));
1872 p1 = gen_reg_rtx (V2SImode);
1873 p2 = gen_reg_rtx (V2SImode);
1874 p3 = gen_reg_rtx (V2SImode);
1875 p4 = gen_reg_rtx (V2SImode);
1876 emit_insn (gen_pmpy2_r (p1, l1, l2));
1877 emit_insn (gen_pmpy2_l (p2, l1, l2));
1878 emit_insn (gen_pmpy2_r (p3, h1, h2));
1879 emit_insn (gen_pmpy2_l (p4, h1, h2));
1881 s1 = gen_reg_rtx (V2SImode);
1882 s2 = gen_reg_rtx (V2SImode);
1883 s3 = gen_reg_rtx (V2SImode);
1884 emit_insn (gen_addv2si3 (s1, p1, p2));
1885 emit_insn (gen_addv2si3 (s2, p3, p4));
1886 emit_insn (gen_addv2si3 (s3, s1, operands[3]));
1887 emit_insn (gen_addv2si3 (operands[0], s2, s3));
1890 /* Emit the appropriate sequence for a call. */
1893 ia64_expand_call (rtx retval, rtx addr, rtx nextarg ATTRIBUTE_UNUSED,
1898 addr = XEXP (addr, 0);
1899 addr = convert_memory_address (DImode, addr);
1900 b0 = gen_rtx_REG (DImode, R_BR (0));
1902 /* ??? Should do this for functions known to bind local too. */
1903 if (TARGET_NO_PIC || TARGET_AUTO_PIC)
1906 insn = gen_sibcall_nogp (addr);
1908 insn = gen_call_nogp (addr, b0);
1910 insn = gen_call_value_nogp (retval, addr, b0);
1911 insn = emit_call_insn (insn);
1916 insn = gen_sibcall_gp (addr);
1918 insn = gen_call_gp (addr, b0);
1920 insn = gen_call_value_gp (retval, addr, b0);
1921 insn = emit_call_insn (insn);
1923 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
1927 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), b0);
1931 reg_emitted (enum ia64_frame_regs r)
1933 if (emitted_frame_related_regs[r] == 0)
1934 emitted_frame_related_regs[r] = current_frame_info.r[r];
1936 gcc_assert (emitted_frame_related_regs[r] == current_frame_info.r[r]);
1940 get_reg (enum ia64_frame_regs r)
1943 return current_frame_info.r[r];
1947 is_emitted (int regno)
1949 enum ia64_frame_regs r;
1951 for (r = reg_fp; r < number_of_ia64_frame_regs; r++)
1952 if (emitted_frame_related_regs[r] == regno)
1958 ia64_reload_gp (void)
1962 if (current_frame_info.r[reg_save_gp])
1964 tmp = gen_rtx_REG (DImode, get_reg (reg_save_gp));
1968 HOST_WIDE_INT offset;
1971 offset = (current_frame_info.spill_cfa_off
1972 + current_frame_info.spill_size);
1973 if (frame_pointer_needed)
1975 tmp = hard_frame_pointer_rtx;
1980 tmp = stack_pointer_rtx;
1981 offset = current_frame_info.total_size - offset;
1984 offset_r = GEN_INT (offset);
1985 if (satisfies_constraint_I (offset_r))
1986 emit_insn (gen_adddi3 (pic_offset_table_rtx, tmp, offset_r));
1989 emit_move_insn (pic_offset_table_rtx, offset_r);
1990 emit_insn (gen_adddi3 (pic_offset_table_rtx,
1991 pic_offset_table_rtx, tmp));
1994 tmp = gen_rtx_MEM (DImode, pic_offset_table_rtx);
1997 emit_move_insn (pic_offset_table_rtx, tmp);
2001 ia64_split_call (rtx retval, rtx addr, rtx retaddr, rtx scratch_r,
2002 rtx scratch_b, int noreturn_p, int sibcall_p)
2005 bool is_desc = false;
2007 /* If we find we're calling through a register, then we're actually
2008 calling through a descriptor, so load up the values. */
2009 if (REG_P (addr) && GR_REGNO_P (REGNO (addr)))
2014 /* ??? We are currently constrained to *not* use peep2, because
2015 we can legitimately change the global lifetime of the GP
2016 (in the form of killing where previously live). This is
2017 because a call through a descriptor doesn't use the previous
2018 value of the GP, while a direct call does, and we do not
2019 commit to either form until the split here.
2021 That said, this means that we lack precise life info for
2022 whether ADDR is dead after this call. This is not terribly
2023 important, since we can fix things up essentially for free
2024 with the POST_DEC below, but it's nice to not use it when we
2025 can immediately tell it's not necessary. */
2026 addr_dead_p = ((noreturn_p || sibcall_p
2027 || TEST_HARD_REG_BIT (regs_invalidated_by_call,
2029 && !FUNCTION_ARG_REGNO_P (REGNO (addr)));
2031 /* Load the code address into scratch_b. */
2032 tmp = gen_rtx_POST_INC (Pmode, addr);
2033 tmp = gen_rtx_MEM (Pmode, tmp);
2034 emit_move_insn (scratch_r, tmp);
2035 emit_move_insn (scratch_b, scratch_r);
2037 /* Load the GP address. If ADDR is not dead here, then we must
2038 revert the change made above via the POST_INCREMENT. */
2040 tmp = gen_rtx_POST_DEC (Pmode, addr);
2043 tmp = gen_rtx_MEM (Pmode, tmp);
2044 emit_move_insn (pic_offset_table_rtx, tmp);
2051 insn = gen_sibcall_nogp (addr);
2053 insn = gen_call_value_nogp (retval, addr, retaddr);
2055 insn = gen_call_nogp (addr, retaddr);
2056 emit_call_insn (insn);
2058 if ((!TARGET_CONST_GP || is_desc) && !noreturn_p && !sibcall_p)
2062 /* Expand an atomic operation. We want to perform MEM <CODE>= VAL atomically.
2064 This differs from the generic code in that we know about the zero-extending
2065 properties of cmpxchg, and the zero-extending requirements of ar.ccv. We
2066 also know that ld.acq+cmpxchg.rel equals a full barrier.
2068 The loop we want to generate looks like
2073 new_reg = cmp_reg op val;
2074 cmp_reg = compare-and-swap(mem, old_reg, new_reg)
2075 if (cmp_reg != old_reg)
2078 Note that we only do the plain load from memory once. Subsequent
2079 iterations use the value loaded by the compare-and-swap pattern. */
2082 ia64_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
2083 rtx old_dst, rtx new_dst)
2085 enum machine_mode mode = GET_MODE (mem);
2086 rtx old_reg, new_reg, cmp_reg, ar_ccv, label;
2087 enum insn_code icode;
2089 /* Special case for using fetchadd. */
2090 if ((mode == SImode || mode == DImode)
2091 && (code == PLUS || code == MINUS)
2092 && fetchadd_operand (val, mode))
2095 val = GEN_INT (-INTVAL (val));
2098 old_dst = gen_reg_rtx (mode);
2100 emit_insn (gen_memory_barrier ());
2103 icode = CODE_FOR_fetchadd_acq_si;
2105 icode = CODE_FOR_fetchadd_acq_di;
2106 emit_insn (GEN_FCN (icode) (old_dst, mem, val));
2110 new_reg = expand_simple_binop (mode, PLUS, old_dst, val, new_dst,
2112 if (new_reg != new_dst)
2113 emit_move_insn (new_dst, new_reg);
2118 /* Because of the volatile mem read, we get an ld.acq, which is the
2119 front half of the full barrier. The end half is the cmpxchg.rel. */
2120 gcc_assert (MEM_VOLATILE_P (mem));
2122 old_reg = gen_reg_rtx (DImode);
2123 cmp_reg = gen_reg_rtx (DImode);
2124 label = gen_label_rtx ();
2128 val = simplify_gen_subreg (DImode, val, mode, 0);
2129 emit_insn (gen_extend_insn (cmp_reg, mem, DImode, mode, 1));
2132 emit_move_insn (cmp_reg, mem);
2136 ar_ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
2137 emit_move_insn (old_reg, cmp_reg);
2138 emit_move_insn (ar_ccv, cmp_reg);
2141 emit_move_insn (old_dst, gen_lowpart (mode, cmp_reg));
2146 new_reg = expand_simple_binop (DImode, AND, new_reg, val, NULL_RTX,
2147 true, OPTAB_DIRECT);
2148 new_reg = expand_simple_unop (DImode, code, new_reg, NULL_RTX, true);
2151 new_reg = expand_simple_binop (DImode, code, new_reg, val, NULL_RTX,
2152 true, OPTAB_DIRECT);
2155 new_reg = gen_lowpart (mode, new_reg);
2157 emit_move_insn (new_dst, new_reg);
2161 case QImode: icode = CODE_FOR_cmpxchg_rel_qi; break;
2162 case HImode: icode = CODE_FOR_cmpxchg_rel_hi; break;
2163 case SImode: icode = CODE_FOR_cmpxchg_rel_si; break;
2164 case DImode: icode = CODE_FOR_cmpxchg_rel_di; break;
2169 emit_insn (GEN_FCN (icode) (cmp_reg, mem, ar_ccv, new_reg));
2171 emit_cmp_and_jump_insns (cmp_reg, old_reg, NE, NULL, DImode, true, label);
2174 /* Begin the assembly file. */
2177 ia64_file_start (void)
2179 /* Variable tracking should be run after all optimizations which change order
2180 of insns. It also needs a valid CFG. This can't be done in
2181 ia64_override_options, because flag_var_tracking is finalized after
2183 ia64_flag_var_tracking = flag_var_tracking;
2184 flag_var_tracking = 0;
2186 default_file_start ();
2187 emit_safe_across_calls ();
2191 emit_safe_across_calls (void)
2193 unsigned int rs, re;
2200 while (rs < 64 && call_used_regs[PR_REG (rs)])
2204 for (re = rs + 1; re < 64 && ! call_used_regs[PR_REG (re)]; re++)
2208 fputs ("\t.pred.safe_across_calls ", asm_out_file);
2212 fputc (',', asm_out_file);
2214 fprintf (asm_out_file, "p%u", rs);
2216 fprintf (asm_out_file, "p%u-p%u", rs, re - 1);
2220 fputc ('\n', asm_out_file);
2223 /* Globalize a declaration. */
2226 ia64_globalize_decl_name (FILE * stream, tree decl)
2228 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2229 tree version_attr = lookup_attribute ("version_id", DECL_ATTRIBUTES (decl));
2232 tree v = TREE_VALUE (TREE_VALUE (version_attr));
2233 const char *p = TREE_STRING_POINTER (v);
2234 fprintf (stream, "\t.alias %s#, \"%s{%s}\"\n", name, name, p);
2236 targetm.asm_out.globalize_label (stream, name);
2237 if (TREE_CODE (decl) == FUNCTION_DECL)
2238 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "function");
2241 /* Helper function for ia64_compute_frame_size: find an appropriate general
2242 register to spill some special register to. SPECIAL_SPILL_MASK contains
2243 bits in GR0 to GR31 that have already been allocated by this routine.
2244 TRY_LOCALS is true if we should attempt to locate a local regnum. */
2247 find_gr_spill (enum ia64_frame_regs r, int try_locals)
2251 if (emitted_frame_related_regs[r] != 0)
2253 regno = emitted_frame_related_regs[r];
2254 if (regno >= LOC_REG (0) && regno < LOC_REG (80 - frame_pointer_needed)
2255 && current_frame_info.n_local_regs < regno - LOC_REG (0) + 1)
2256 current_frame_info.n_local_regs = regno - LOC_REG (0) + 1;
2257 else if (current_function_is_leaf
2258 && regno >= GR_REG (1) && regno <= GR_REG (31))
2259 current_frame_info.gr_used_mask |= 1 << regno;
2264 /* If this is a leaf function, first try an otherwise unused
2265 call-clobbered register. */
2266 if (current_function_is_leaf)
2268 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
2269 if (! df_regs_ever_live_p (regno)
2270 && call_used_regs[regno]
2271 && ! fixed_regs[regno]
2272 && ! global_regs[regno]
2273 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0
2274 && ! is_emitted (regno))
2276 current_frame_info.gr_used_mask |= 1 << regno;
2283 regno = current_frame_info.n_local_regs;
2284 /* If there is a frame pointer, then we can't use loc79, because
2285 that is HARD_FRAME_POINTER_REGNUM. In particular, see the
2286 reg_name switching code in ia64_expand_prologue. */
2287 while (regno < (80 - frame_pointer_needed))
2288 if (! is_emitted (LOC_REG (regno++)))
2290 current_frame_info.n_local_regs = regno;
2291 return LOC_REG (regno - 1);
2295 /* Failed to find a general register to spill to. Must use stack. */
2299 /* In order to make for nice schedules, we try to allocate every temporary
2300 to a different register. We must of course stay away from call-saved,
2301 fixed, and global registers. We must also stay away from registers
2302 allocated in current_frame_info.gr_used_mask, since those include regs
2303 used all through the prologue.
2305 Any register allocated here must be used immediately. The idea is to
2306 aid scheduling, not to solve data flow problems. */
2308 static int last_scratch_gr_reg;
2311 next_scratch_gr_reg (void)
2315 for (i = 0; i < 32; ++i)
2317 regno = (last_scratch_gr_reg + i + 1) & 31;
2318 if (call_used_regs[regno]
2319 && ! fixed_regs[regno]
2320 && ! global_regs[regno]
2321 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0)
2323 last_scratch_gr_reg = regno;
2328 /* There must be _something_ available. */
2332 /* Helper function for ia64_compute_frame_size, called through
2333 diddle_return_value. Mark REG in current_frame_info.gr_used_mask. */
2336 mark_reg_gr_used_mask (rtx reg, void *data ATTRIBUTE_UNUSED)
2338 unsigned int regno = REGNO (reg);
2341 unsigned int i, n = hard_regno_nregs[regno][GET_MODE (reg)];
2342 for (i = 0; i < n; ++i)
2343 current_frame_info.gr_used_mask |= 1 << (regno + i);
2348 /* Returns the number of bytes offset between the frame pointer and the stack
2349 pointer for the current function. SIZE is the number of bytes of space
2350 needed for local variables. */
2353 ia64_compute_frame_size (HOST_WIDE_INT size)
2355 HOST_WIDE_INT total_size;
2356 HOST_WIDE_INT spill_size = 0;
2357 HOST_WIDE_INT extra_spill_size = 0;
2358 HOST_WIDE_INT pretend_args_size;
2361 int spilled_gr_p = 0;
2362 int spilled_fr_p = 0;
2368 if (current_frame_info.initialized)
2371 memset (¤t_frame_info, 0, sizeof current_frame_info);
2372 CLEAR_HARD_REG_SET (mask);
2374 /* Don't allocate scratches to the return register. */
2375 diddle_return_value (mark_reg_gr_used_mask, NULL);
2377 /* Don't allocate scratches to the EH scratch registers. */
2378 if (cfun->machine->ia64_eh_epilogue_sp)
2379 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_sp, NULL);
2380 if (cfun->machine->ia64_eh_epilogue_bsp)
2381 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_bsp, NULL);
2383 /* Find the size of the register stack frame. We have only 80 local
2384 registers, because we reserve 8 for the inputs and 8 for the
2387 /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed,
2388 since we'll be adjusting that down later. */
2389 regno = LOC_REG (78) + ! frame_pointer_needed;
2390 for (; regno >= LOC_REG (0); regno--)
2391 if (df_regs_ever_live_p (regno) && !is_emitted (regno))
2393 current_frame_info.n_local_regs = regno - LOC_REG (0) + 1;
2395 /* For functions marked with the syscall_linkage attribute, we must mark
2396 all eight input registers as in use, so that locals aren't visible to
2399 if (cfun->machine->n_varargs > 0
2400 || lookup_attribute ("syscall_linkage",
2401 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
2402 current_frame_info.n_input_regs = 8;
2405 for (regno = IN_REG (7); regno >= IN_REG (0); regno--)
2406 if (df_regs_ever_live_p (regno))
2408 current_frame_info.n_input_regs = regno - IN_REG (0) + 1;
2411 for (regno = OUT_REG (7); regno >= OUT_REG (0); regno--)
2412 if (df_regs_ever_live_p (regno))
2414 i = regno - OUT_REG (0) + 1;
2416 #ifndef PROFILE_HOOK
2417 /* When -p profiling, we need one output register for the mcount argument.
2418 Likewise for -a profiling for the bb_init_func argument. For -ax
2419 profiling, we need two output registers for the two bb_init_trace_func
2424 current_frame_info.n_output_regs = i;
2426 /* ??? No rotating register support yet. */
2427 current_frame_info.n_rotate_regs = 0;
2429 /* Discover which registers need spilling, and how much room that
2430 will take. Begin with floating point and general registers,
2431 which will always wind up on the stack. */
2433 for (regno = FR_REG (2); regno <= FR_REG (127); regno++)
2434 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
2436 SET_HARD_REG_BIT (mask, regno);
2442 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
2443 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
2445 SET_HARD_REG_BIT (mask, regno);
2451 for (regno = BR_REG (1); regno <= BR_REG (7); regno++)
2452 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
2454 SET_HARD_REG_BIT (mask, regno);
2459 /* Now come all special registers that might get saved in other
2460 general registers. */
2462 if (frame_pointer_needed)
2464 current_frame_info.r[reg_fp] = find_gr_spill (reg_fp, 1);
2465 /* If we did not get a register, then we take LOC79. This is guaranteed
2466 to be free, even if regs_ever_live is already set, because this is
2467 HARD_FRAME_POINTER_REGNUM. This requires incrementing n_local_regs,
2468 as we don't count loc79 above. */
2469 if (current_frame_info.r[reg_fp] == 0)
2471 current_frame_info.r[reg_fp] = LOC_REG (79);
2472 current_frame_info.n_local_regs = LOC_REG (79) - LOC_REG (0) + 1;
2476 if (! current_function_is_leaf)
2478 /* Emit a save of BR0 if we call other functions. Do this even
2479 if this function doesn't return, as EH depends on this to be
2480 able to unwind the stack. */
2481 SET_HARD_REG_BIT (mask, BR_REG (0));
2483 current_frame_info.r[reg_save_b0] = find_gr_spill (reg_save_b0, 1);
2484 if (current_frame_info.r[reg_save_b0] == 0)
2486 extra_spill_size += 8;
2490 /* Similarly for ar.pfs. */
2491 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
2492 current_frame_info.r[reg_save_ar_pfs] = find_gr_spill (reg_save_ar_pfs, 1);
2493 if (current_frame_info.r[reg_save_ar_pfs] == 0)
2495 extra_spill_size += 8;
2499 /* Similarly for gp. Note that if we're calling setjmp, the stacked
2500 registers are clobbered, so we fall back to the stack. */
2501 current_frame_info.r[reg_save_gp]
2502 = (cfun->calls_setjmp ? 0 : find_gr_spill (reg_save_gp, 1));
2503 if (current_frame_info.r[reg_save_gp] == 0)
2505 SET_HARD_REG_BIT (mask, GR_REG (1));
2512 if (df_regs_ever_live_p (BR_REG (0)) && ! call_used_regs[BR_REG (0)])
2514 SET_HARD_REG_BIT (mask, BR_REG (0));
2515 extra_spill_size += 8;
2519 if (df_regs_ever_live_p (AR_PFS_REGNUM))
2521 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
2522 current_frame_info.r[reg_save_ar_pfs]
2523 = find_gr_spill (reg_save_ar_pfs, 1);
2524 if (current_frame_info.r[reg_save_ar_pfs] == 0)
2526 extra_spill_size += 8;
2532 /* Unwind descriptor hackery: things are most efficient if we allocate
2533 consecutive GR save registers for RP, PFS, FP in that order. However,
2534 it is absolutely critical that FP get the only hard register that's
2535 guaranteed to be free, so we allocated it first. If all three did
2536 happen to be allocated hard regs, and are consecutive, rearrange them
2537 into the preferred order now.
2539 If we have already emitted code for any of those registers,
2540 then it's already too late to change. */
2541 min_regno = MIN (current_frame_info.r[reg_fp],
2542 MIN (current_frame_info.r[reg_save_b0],
2543 current_frame_info.r[reg_save_ar_pfs]));
2544 max_regno = MAX (current_frame_info.r[reg_fp],
2545 MAX (current_frame_info.r[reg_save_b0],
2546 current_frame_info.r[reg_save_ar_pfs]));
2548 && min_regno + 2 == max_regno
2549 && (current_frame_info.r[reg_fp] == min_regno + 1
2550 || current_frame_info.r[reg_save_b0] == min_regno + 1
2551 || current_frame_info.r[reg_save_ar_pfs] == min_regno + 1)
2552 && (emitted_frame_related_regs[reg_save_b0] == 0
2553 || emitted_frame_related_regs[reg_save_b0] == min_regno)
2554 && (emitted_frame_related_regs[reg_save_ar_pfs] == 0
2555 || emitted_frame_related_regs[reg_save_ar_pfs] == min_regno + 1)
2556 && (emitted_frame_related_regs[reg_fp] == 0
2557 || emitted_frame_related_regs[reg_fp] == min_regno + 2))
2559 current_frame_info.r[reg_save_b0] = min_regno;
2560 current_frame_info.r[reg_save_ar_pfs] = min_regno + 1;
2561 current_frame_info.r[reg_fp] = min_regno + 2;
2564 /* See if we need to store the predicate register block. */
2565 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
2566 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
2568 if (regno <= PR_REG (63))
2570 SET_HARD_REG_BIT (mask, PR_REG (0));
2571 current_frame_info.r[reg_save_pr] = find_gr_spill (reg_save_pr, 1);
2572 if (current_frame_info.r[reg_save_pr] == 0)
2574 extra_spill_size += 8;
2578 /* ??? Mark them all as used so that register renaming and such
2579 are free to use them. */
2580 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
2581 df_set_regs_ever_live (regno, true);
2584 /* If we're forced to use st8.spill, we're forced to save and restore
2585 ar.unat as well. The check for existing liveness allows inline asm
2586 to touch ar.unat. */
2587 if (spilled_gr_p || cfun->machine->n_varargs
2588 || df_regs_ever_live_p (AR_UNAT_REGNUM))
2590 df_set_regs_ever_live (AR_UNAT_REGNUM, true);
2591 SET_HARD_REG_BIT (mask, AR_UNAT_REGNUM);
2592 current_frame_info.r[reg_save_ar_unat]
2593 = find_gr_spill (reg_save_ar_unat, spill_size == 0);
2594 if (current_frame_info.r[reg_save_ar_unat] == 0)
2596 extra_spill_size += 8;
2601 if (df_regs_ever_live_p (AR_LC_REGNUM))
2603 SET_HARD_REG_BIT (mask, AR_LC_REGNUM);
2604 current_frame_info.r[reg_save_ar_lc]
2605 = find_gr_spill (reg_save_ar_lc, spill_size == 0);
2606 if (current_frame_info.r[reg_save_ar_lc] == 0)
2608 extra_spill_size += 8;
2613 /* If we have an odd number of words of pretend arguments written to
2614 the stack, then the FR save area will be unaligned. We round the
2615 size of this area up to keep things 16 byte aligned. */
2617 pretend_args_size = IA64_STACK_ALIGN (crtl->args.pretend_args_size);
2619 pretend_args_size = crtl->args.pretend_args_size;
2621 total_size = (spill_size + extra_spill_size + size + pretend_args_size
2622 + crtl->outgoing_args_size);
2623 total_size = IA64_STACK_ALIGN (total_size);
2625 /* We always use the 16-byte scratch area provided by the caller, but
2626 if we are a leaf function, there's no one to which we need to provide
2628 if (current_function_is_leaf)
2629 total_size = MAX (0, total_size - 16);
2631 current_frame_info.total_size = total_size;
2632 current_frame_info.spill_cfa_off = pretend_args_size - 16;
2633 current_frame_info.spill_size = spill_size;
2634 current_frame_info.extra_spill_size = extra_spill_size;
2635 COPY_HARD_REG_SET (current_frame_info.mask, mask);
2636 current_frame_info.n_spilled = n_spilled;
2637 current_frame_info.initialized = reload_completed;
2640 /* Compute the initial difference between the specified pair of registers. */
2643 ia64_initial_elimination_offset (int from, int to)
2645 HOST_WIDE_INT offset;
2647 ia64_compute_frame_size (get_frame_size ());
2650 case FRAME_POINTER_REGNUM:
2653 case HARD_FRAME_POINTER_REGNUM:
2654 if (current_function_is_leaf)
2655 offset = -current_frame_info.total_size;
2657 offset = -(current_frame_info.total_size
2658 - crtl->outgoing_args_size - 16);
2661 case STACK_POINTER_REGNUM:
2662 if (current_function_is_leaf)
2665 offset = 16 + crtl->outgoing_args_size;
2673 case ARG_POINTER_REGNUM:
2674 /* Arguments start above the 16 byte save area, unless stdarg
2675 in which case we store through the 16 byte save area. */
2678 case HARD_FRAME_POINTER_REGNUM:
2679 offset = 16 - crtl->args.pretend_args_size;
2682 case STACK_POINTER_REGNUM:
2683 offset = (current_frame_info.total_size
2684 + 16 - crtl->args.pretend_args_size);
2699 /* If there are more than a trivial number of register spills, we use
2700 two interleaved iterators so that we can get two memory references
2703 In order to simplify things in the prologue and epilogue expanders,
2704 we use helper functions to fix up the memory references after the
2705 fact with the appropriate offsets to a POST_MODIFY memory mode.
2706 The following data structure tracks the state of the two iterators
2707 while insns are being emitted. */
2709 struct spill_fill_data
2711 rtx init_after; /* point at which to emit initializations */
2712 rtx init_reg[2]; /* initial base register */
2713 rtx iter_reg[2]; /* the iterator registers */
2714 rtx *prev_addr[2]; /* address of last memory use */
2715 rtx prev_insn[2]; /* the insn corresponding to prev_addr */
2716 HOST_WIDE_INT prev_off[2]; /* last offset */
2717 int n_iter; /* number of iterators in use */
2718 int next_iter; /* next iterator to use */
2719 unsigned int save_gr_used_mask;
2722 static struct spill_fill_data spill_fill_data;
2725 setup_spill_pointers (int n_spills, rtx init_reg, HOST_WIDE_INT cfa_off)
2729 spill_fill_data.init_after = get_last_insn ();
2730 spill_fill_data.init_reg[0] = init_reg;
2731 spill_fill_data.init_reg[1] = init_reg;
2732 spill_fill_data.prev_addr[0] = NULL;
2733 spill_fill_data.prev_addr[1] = NULL;
2734 spill_fill_data.prev_insn[0] = NULL;
2735 spill_fill_data.prev_insn[1] = NULL;
2736 spill_fill_data.prev_off[0] = cfa_off;
2737 spill_fill_data.prev_off[1] = cfa_off;
2738 spill_fill_data.next_iter = 0;
2739 spill_fill_data.save_gr_used_mask = current_frame_info.gr_used_mask;
2741 spill_fill_data.n_iter = 1 + (n_spills > 2);
2742 for (i = 0; i < spill_fill_data.n_iter; ++i)
2744 int regno = next_scratch_gr_reg ();
2745 spill_fill_data.iter_reg[i] = gen_rtx_REG (DImode, regno);
2746 current_frame_info.gr_used_mask |= 1 << regno;
2751 finish_spill_pointers (void)
2753 current_frame_info.gr_used_mask = spill_fill_data.save_gr_used_mask;
2757 spill_restore_mem (rtx reg, HOST_WIDE_INT cfa_off)
2759 int iter = spill_fill_data.next_iter;
2760 HOST_WIDE_INT disp = spill_fill_data.prev_off[iter] - cfa_off;
2761 rtx disp_rtx = GEN_INT (disp);
2764 if (spill_fill_data.prev_addr[iter])
2766 if (satisfies_constraint_N (disp_rtx))
2768 *spill_fill_data.prev_addr[iter]
2769 = gen_rtx_POST_MODIFY (DImode, spill_fill_data.iter_reg[iter],
2770 gen_rtx_PLUS (DImode,
2771 spill_fill_data.iter_reg[iter],
2773 REG_NOTES (spill_fill_data.prev_insn[iter])
2774 = gen_rtx_EXPR_LIST (REG_INC, spill_fill_data.iter_reg[iter],
2775 REG_NOTES (spill_fill_data.prev_insn[iter]));
2779 /* ??? Could use register post_modify for loads. */
2780 if (!satisfies_constraint_I (disp_rtx))
2782 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
2783 emit_move_insn (tmp, disp_rtx);
2786 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
2787 spill_fill_data.iter_reg[iter], disp_rtx));
2790 /* Micro-optimization: if we've created a frame pointer, it's at
2791 CFA 0, which may allow the real iterator to be initialized lower,
2792 slightly increasing parallelism. Also, if there are few saves
2793 it may eliminate the iterator entirely. */
2795 && spill_fill_data.init_reg[iter] == stack_pointer_rtx
2796 && frame_pointer_needed)
2798 mem = gen_rtx_MEM (GET_MODE (reg), hard_frame_pointer_rtx);
2799 set_mem_alias_set (mem, get_varargs_alias_set ());
2807 seq = gen_movdi (spill_fill_data.iter_reg[iter],
2808 spill_fill_data.init_reg[iter]);
2813 if (!satisfies_constraint_I (disp_rtx))
2815 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
2816 emit_move_insn (tmp, disp_rtx);
2820 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
2821 spill_fill_data.init_reg[iter],
2828 /* Careful for being the first insn in a sequence. */
2829 if (spill_fill_data.init_after)
2830 insn = emit_insn_after (seq, spill_fill_data.init_after);
2833 rtx first = get_insns ();
2835 insn = emit_insn_before (seq, first);
2837 insn = emit_insn (seq);
2839 spill_fill_data.init_after = insn;
2842 mem = gen_rtx_MEM (GET_MODE (reg), spill_fill_data.iter_reg[iter]);
2844 /* ??? Not all of the spills are for varargs, but some of them are.
2845 The rest of the spills belong in an alias set of their own. But
2846 it doesn't actually hurt to include them here. */
2847 set_mem_alias_set (mem, get_varargs_alias_set ());
2849 spill_fill_data.prev_addr[iter] = &XEXP (mem, 0);
2850 spill_fill_data.prev_off[iter] = cfa_off;
2852 if (++iter >= spill_fill_data.n_iter)
2854 spill_fill_data.next_iter = iter;
2860 do_spill (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off,
2863 int iter = spill_fill_data.next_iter;
2866 mem = spill_restore_mem (reg, cfa_off);
2867 insn = emit_insn ((*move_fn) (mem, reg, GEN_INT (cfa_off)));
2868 spill_fill_data.prev_insn[iter] = insn;
2875 RTX_FRAME_RELATED_P (insn) = 1;
2877 /* Don't even pretend that the unwind code can intuit its way
2878 through a pair of interleaved post_modify iterators. Just
2879 provide the correct answer. */
2881 if (frame_pointer_needed)
2883 base = hard_frame_pointer_rtx;
2888 base = stack_pointer_rtx;
2889 off = current_frame_info.total_size - cfa_off;
2893 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2894 gen_rtx_SET (VOIDmode,
2895 gen_rtx_MEM (GET_MODE (reg),
2896 plus_constant (base, off)),
2903 do_restore (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off)
2905 int iter = spill_fill_data.next_iter;
2908 insn = emit_insn ((*move_fn) (reg, spill_restore_mem (reg, cfa_off),
2909 GEN_INT (cfa_off)));
2910 spill_fill_data.prev_insn[iter] = insn;
2913 /* Wrapper functions that discards the CONST_INT spill offset. These
2914 exist so that we can give gr_spill/gr_fill the offset they need and
2915 use a consistent function interface. */
2918 gen_movdi_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
2920 return gen_movdi (dest, src);
2924 gen_fr_spill_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
2926 return gen_fr_spill (dest, src);
2930 gen_fr_restore_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
2932 return gen_fr_restore (dest, src);
2935 /* Called after register allocation to add any instructions needed for the
2936 prologue. Using a prologue insn is favored compared to putting all of the
2937 instructions in output_function_prologue(), since it allows the scheduler
2938 to intermix instructions with the saves of the caller saved registers. In
2939 some cases, it might be necessary to emit a barrier instruction as the last
2940 insn to prevent such scheduling.
2942 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
2943 so that the debug info generation code can handle them properly.
2945 The register save area is layed out like so:
2947 [ varargs spill area ]
2948 [ fr register spill area ]
2949 [ br register spill area ]
2950 [ ar register spill area ]
2951 [ pr register spill area ]
2952 [ gr register spill area ] */
2954 /* ??? Get inefficient code when the frame size is larger than can fit in an
2955 adds instruction. */
2958 ia64_expand_prologue (void)
2960 rtx insn, ar_pfs_save_reg, ar_unat_save_reg;
2961 int i, epilogue_p, regno, alt_regno, cfa_off, n_varargs;
2964 ia64_compute_frame_size (get_frame_size ());
2965 last_scratch_gr_reg = 15;
2969 fprintf (dump_file, "ia64 frame related registers "
2970 "recorded in current_frame_info.r[]:\n");
2971 #define PRINTREG(a) if (current_frame_info.r[a]) \
2972 fprintf(dump_file, "%s = %d\n", #a, current_frame_info.r[a])
2974 PRINTREG(reg_save_b0);
2975 PRINTREG(reg_save_pr);
2976 PRINTREG(reg_save_ar_pfs);
2977 PRINTREG(reg_save_ar_unat);
2978 PRINTREG(reg_save_ar_lc);
2979 PRINTREG(reg_save_gp);
2983 /* If there is no epilogue, then we don't need some prologue insns.
2984 We need to avoid emitting the dead prologue insns, because flow
2985 will complain about them. */
2991 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
2992 if ((e->flags & EDGE_FAKE) == 0
2993 && (e->flags & EDGE_FALLTHRU) != 0)
2995 epilogue_p = (e != NULL);
3000 /* Set the local, input, and output register names. We need to do this
3001 for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in
3002 half. If we use in/loc/out register names, then we get assembler errors
3003 in crtn.S because there is no alloc insn or regstk directive in there. */
3004 if (! TARGET_REG_NAMES)
3006 int inputs = current_frame_info.n_input_regs;
3007 int locals = current_frame_info.n_local_regs;
3008 int outputs = current_frame_info.n_output_regs;
3010 for (i = 0; i < inputs; i++)
3011 reg_names[IN_REG (i)] = ia64_reg_numbers[i];
3012 for (i = 0; i < locals; i++)
3013 reg_names[LOC_REG (i)] = ia64_reg_numbers[inputs + i];
3014 for (i = 0; i < outputs; i++)
3015 reg_names[OUT_REG (i)] = ia64_reg_numbers[inputs + locals + i];
3018 /* Set the frame pointer register name. The regnum is logically loc79,
3019 but of course we'll not have allocated that many locals. Rather than
3020 worrying about renumbering the existing rtxs, we adjust the name. */
3021 /* ??? This code means that we can never use one local register when
3022 there is a frame pointer. loc79 gets wasted in this case, as it is
3023 renamed to a register that will never be used. See also the try_locals
3024 code in find_gr_spill. */
3025 if (current_frame_info.r[reg_fp])
3027 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
3028 reg_names[HARD_FRAME_POINTER_REGNUM]
3029 = reg_names[current_frame_info.r[reg_fp]];
3030 reg_names[current_frame_info.r[reg_fp]] = tmp;
3033 /* We don't need an alloc instruction if we've used no outputs or locals. */
3034 if (current_frame_info.n_local_regs == 0
3035 && current_frame_info.n_output_regs == 0
3036 && current_frame_info.n_input_regs <= crtl->args.info.int_regs
3037 && !TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM))
3039 /* If there is no alloc, but there are input registers used, then we
3040 need a .regstk directive. */
3041 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
3042 ar_pfs_save_reg = NULL_RTX;
3046 current_frame_info.need_regstk = 0;
3048 if (current_frame_info.r[reg_save_ar_pfs])
3050 regno = current_frame_info.r[reg_save_ar_pfs];
3051 reg_emitted (reg_save_ar_pfs);
3054 regno = next_scratch_gr_reg ();
3055 ar_pfs_save_reg = gen_rtx_REG (DImode, regno);
3057 insn = emit_insn (gen_alloc (ar_pfs_save_reg,
3058 GEN_INT (current_frame_info.n_input_regs),
3059 GEN_INT (current_frame_info.n_local_regs),
3060 GEN_INT (current_frame_info.n_output_regs),
3061 GEN_INT (current_frame_info.n_rotate_regs)));
3062 RTX_FRAME_RELATED_P (insn) = (current_frame_info.r[reg_save_ar_pfs] != 0);
3065 /* Set up frame pointer, stack pointer, and spill iterators. */
3067 n_varargs = cfun->machine->n_varargs;
3068 setup_spill_pointers (current_frame_info.n_spilled + n_varargs,
3069 stack_pointer_rtx, 0);
3071 if (frame_pointer_needed)
3073 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
3074 RTX_FRAME_RELATED_P (insn) = 1;
3077 if (current_frame_info.total_size != 0)
3079 rtx frame_size_rtx = GEN_INT (- current_frame_info.total_size);
3082 if (satisfies_constraint_I (frame_size_rtx))
3083 offset = frame_size_rtx;
3086 regno = next_scratch_gr_reg ();
3087 offset = gen_rtx_REG (DImode, regno);
3088 emit_move_insn (offset, frame_size_rtx);
3091 insn = emit_insn (gen_adddi3 (stack_pointer_rtx,
3092 stack_pointer_rtx, offset));
3094 if (! frame_pointer_needed)
3096 RTX_FRAME_RELATED_P (insn) = 1;
3097 if (GET_CODE (offset) != CONST_INT)
3100 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3101 gen_rtx_SET (VOIDmode,
3103 gen_rtx_PLUS (DImode,
3110 /* ??? At this point we must generate a magic insn that appears to
3111 modify the stack pointer, the frame pointer, and all spill
3112 iterators. This would allow the most scheduling freedom. For
3113 now, just hard stop. */
3114 emit_insn (gen_blockage ());
3117 /* Must copy out ar.unat before doing any integer spills. */
3118 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
3120 if (current_frame_info.r[reg_save_ar_unat])
3123 = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_unat]);
3124 reg_emitted (reg_save_ar_unat);
3128 alt_regno = next_scratch_gr_reg ();
3129 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
3130 current_frame_info.gr_used_mask |= 1 << alt_regno;
3133 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3134 insn = emit_move_insn (ar_unat_save_reg, reg);
3135 RTX_FRAME_RELATED_P (insn) = (current_frame_info.r[reg_save_ar_unat] != 0);
3137 /* Even if we're not going to generate an epilogue, we still
3138 need to save the register so that EH works. */
3139 if (! epilogue_p && current_frame_info.r[reg_save_ar_unat])
3140 emit_insn (gen_prologue_use (ar_unat_save_reg));
3143 ar_unat_save_reg = NULL_RTX;
3145 /* Spill all varargs registers. Do this before spilling any GR registers,
3146 since we want the UNAT bits for the GR registers to override the UNAT
3147 bits from varargs, which we don't care about. */
3150 for (regno = GR_ARG_FIRST + 7; n_varargs > 0; --n_varargs, --regno)
3152 reg = gen_rtx_REG (DImode, regno);
3153 do_spill (gen_gr_spill, reg, cfa_off += 8, NULL_RTX);
3156 /* Locate the bottom of the register save area. */
3157 cfa_off = (current_frame_info.spill_cfa_off
3158 + current_frame_info.spill_size
3159 + current_frame_info.extra_spill_size);
3161 /* Save the predicate register block either in a register or in memory. */
3162 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
3164 reg = gen_rtx_REG (DImode, PR_REG (0));
3165 if (current_frame_info.r[reg_save_pr] != 0)
3167 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_pr]);
3168 reg_emitted (reg_save_pr);
3169 insn = emit_move_insn (alt_reg, reg);
3171 /* ??? Denote pr spill/fill by a DImode move that modifies all
3172 64 hard registers. */
3173 RTX_FRAME_RELATED_P (insn) = 1;
3175 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3176 gen_rtx_SET (VOIDmode, alt_reg, reg),
3179 /* Even if we're not going to generate an epilogue, we still
3180 need to save the register so that EH works. */
3182 emit_insn (gen_prologue_use (alt_reg));
3186 alt_regno = next_scratch_gr_reg ();
3187 alt_reg = gen_rtx_REG (DImode, alt_regno);
3188 insn = emit_move_insn (alt_reg, reg);
3189 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3194 /* Handle AR regs in numerical order. All of them get special handling. */
3195 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM)
3196 && current_frame_info.r[reg_save_ar_unat] == 0)
3198 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3199 do_spill (gen_movdi_x, ar_unat_save_reg, cfa_off, reg);
3203 /* The alloc insn already copied ar.pfs into a general register. The
3204 only thing we have to do now is copy that register to a stack slot
3205 if we'd not allocated a local register for the job. */
3206 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM)
3207 && current_frame_info.r[reg_save_ar_pfs] == 0)
3209 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3210 do_spill (gen_movdi_x, ar_pfs_save_reg, cfa_off, reg);
3214 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
3216 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
3217 if (current_frame_info.r[reg_save_ar_lc] != 0)
3219 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_lc]);
3220 reg_emitted (reg_save_ar_lc);
3221 insn = emit_move_insn (alt_reg, reg);
3222 RTX_FRAME_RELATED_P (insn) = 1;
3224 /* Even if we're not going to generate an epilogue, we still
3225 need to save the register so that EH works. */
3227 emit_insn (gen_prologue_use (alt_reg));
3231 alt_regno = next_scratch_gr_reg ();
3232 alt_reg = gen_rtx_REG (DImode, alt_regno);
3233 emit_move_insn (alt_reg, reg);
3234 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3239 /* Save the return pointer. */
3240 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3242 reg = gen_rtx_REG (DImode, BR_REG (0));
3243 if (current_frame_info.r[reg_save_b0] != 0)
3245 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]);
3246 reg_emitted (reg_save_b0);
3247 insn = emit_move_insn (alt_reg, reg);
3248 RTX_FRAME_RELATED_P (insn) = 1;
3250 /* Even if we're not going to generate an epilogue, we still
3251 need to save the register so that EH works. */
3253 emit_insn (gen_prologue_use (alt_reg));
3257 alt_regno = next_scratch_gr_reg ();
3258 alt_reg = gen_rtx_REG (DImode, alt_regno);
3259 emit_move_insn (alt_reg, reg);
3260 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3265 if (current_frame_info.r[reg_save_gp])
3267 reg_emitted (reg_save_gp);
3268 insn = emit_move_insn (gen_rtx_REG (DImode,
3269 current_frame_info.r[reg_save_gp]),
3270 pic_offset_table_rtx);
3273 /* We should now be at the base of the gr/br/fr spill area. */
3274 gcc_assert (cfa_off == (current_frame_info.spill_cfa_off
3275 + current_frame_info.spill_size));
3277 /* Spill all general registers. */
3278 for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
3279 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3281 reg = gen_rtx_REG (DImode, regno);
3282 do_spill (gen_gr_spill, reg, cfa_off, reg);
3286 /* Spill the rest of the BR registers. */
3287 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
3288 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3290 alt_regno = next_scratch_gr_reg ();
3291 alt_reg = gen_rtx_REG (DImode, alt_regno);
3292 reg = gen_rtx_REG (DImode, regno);
3293 emit_move_insn (alt_reg, reg);
3294 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3298 /* Align the frame and spill all FR registers. */
3299 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
3300 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3302 gcc_assert (!(cfa_off & 15));
3303 reg = gen_rtx_REG (XFmode, regno);
3304 do_spill (gen_fr_spill_x, reg, cfa_off, reg);
3308 gcc_assert (cfa_off == current_frame_info.spill_cfa_off);
3310 finish_spill_pointers ();
3313 /* Called after register allocation to add any instructions needed for the
3314 epilogue. Using an epilogue insn is favored compared to putting all of the
3315 instructions in output_function_prologue(), since it allows the scheduler
3316 to intermix instructions with the saves of the caller saved registers. In
3317 some cases, it might be necessary to emit a barrier instruction as the last
3318 insn to prevent such scheduling. */
3321 ia64_expand_epilogue (int sibcall_p)
3323 rtx insn, reg, alt_reg, ar_unat_save_reg;
3324 int regno, alt_regno, cfa_off;
3326 ia64_compute_frame_size (get_frame_size ());
3328 /* If there is a frame pointer, then we use it instead of the stack
3329 pointer, so that the stack pointer does not need to be valid when
3330 the epilogue starts. See EXIT_IGNORE_STACK. */
3331 if (frame_pointer_needed)
3332 setup_spill_pointers (current_frame_info.n_spilled,
3333 hard_frame_pointer_rtx, 0);
3335 setup_spill_pointers (current_frame_info.n_spilled, stack_pointer_rtx,
3336 current_frame_info.total_size);
3338 if (current_frame_info.total_size != 0)
3340 /* ??? At this point we must generate a magic insn that appears to
3341 modify the spill iterators and the frame pointer. This would
3342 allow the most scheduling freedom. For now, just hard stop. */
3343 emit_insn (gen_blockage ());
3346 /* Locate the bottom of the register save area. */
3347 cfa_off = (current_frame_info.spill_cfa_off
3348 + current_frame_info.spill_size
3349 + current_frame_info.extra_spill_size);
3351 /* Restore the predicate registers. */
3352 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
3354 if (current_frame_info.r[reg_save_pr] != 0)
3356 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_pr]);
3357 reg_emitted (reg_save_pr);
3361 alt_regno = next_scratch_gr_reg ();
3362 alt_reg = gen_rtx_REG (DImode, alt_regno);
3363 do_restore (gen_movdi_x, alt_reg, cfa_off);
3366 reg = gen_rtx_REG (DImode, PR_REG (0));
3367 emit_move_insn (reg, alt_reg);
3370 /* Restore the application registers. */
3372 /* Load the saved unat from the stack, but do not restore it until
3373 after the GRs have been restored. */
3374 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
3376 if (current_frame_info.r[reg_save_ar_unat] != 0)
3379 = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_unat]);
3380 reg_emitted (reg_save_ar_unat);
3384 alt_regno = next_scratch_gr_reg ();
3385 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
3386 current_frame_info.gr_used_mask |= 1 << alt_regno;
3387 do_restore (gen_movdi_x, ar_unat_save_reg, cfa_off);
3392 ar_unat_save_reg = NULL_RTX;
3394 if (current_frame_info.r[reg_save_ar_pfs] != 0)
3396 reg_emitted (reg_save_ar_pfs);
3397 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_pfs]);
3398 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3399 emit_move_insn (reg, alt_reg);
3401 else if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM))
3403 alt_regno = next_scratch_gr_reg ();
3404 alt_reg = gen_rtx_REG (DImode, alt_regno);
3405 do_restore (gen_movdi_x, alt_reg, cfa_off);
3407 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3408 emit_move_insn (reg, alt_reg);
3411 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
3413 if (current_frame_info.r[reg_save_ar_lc] != 0)
3415 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_lc]);
3416 reg_emitted (reg_save_ar_lc);
3420 alt_regno = next_scratch_gr_reg ();
3421 alt_reg = gen_rtx_REG (DImode, alt_regno);
3422 do_restore (gen_movdi_x, alt_reg, cfa_off);
3425 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
3426 emit_move_insn (reg, alt_reg);
3429 /* Restore the return pointer. */
3430 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3432 if (current_frame_info.r[reg_save_b0] != 0)
3434 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]);
3435 reg_emitted (reg_save_b0);
3439 alt_regno = next_scratch_gr_reg ();
3440 alt_reg = gen_rtx_REG (DImode, alt_regno);
3441 do_restore (gen_movdi_x, alt_reg, cfa_off);
3444 reg = gen_rtx_REG (DImode, BR_REG (0));
3445 emit_move_insn (reg, alt_reg);
3448 /* We should now be at the base of the gr/br/fr spill area. */
3449 gcc_assert (cfa_off == (current_frame_info.spill_cfa_off
3450 + current_frame_info.spill_size));
3452 /* The GP may be stored on the stack in the prologue, but it's
3453 never restored in the epilogue. Skip the stack slot. */
3454 if (TEST_HARD_REG_BIT (current_frame_info.mask, GR_REG (1)))
3457 /* Restore all general registers. */
3458 for (regno = GR_REG (2); regno <= GR_REG (31); ++regno)
3459 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3461 reg = gen_rtx_REG (DImode, regno);
3462 do_restore (gen_gr_restore, reg, cfa_off);
3466 /* Restore the branch registers. */
3467 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
3468 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3470 alt_regno = next_scratch_gr_reg ();
3471 alt_reg = gen_rtx_REG (DImode, alt_regno);
3472 do_restore (gen_movdi_x, alt_reg, cfa_off);
3474 reg = gen_rtx_REG (DImode, regno);
3475 emit_move_insn (reg, alt_reg);
3478 /* Restore floating point registers. */
3479 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
3480 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3482 gcc_assert (!(cfa_off & 15));
3483 reg = gen_rtx_REG (XFmode, regno);
3484 do_restore (gen_fr_restore_x, reg, cfa_off);
3488 /* Restore ar.unat for real. */
3489 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
3491 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3492 emit_move_insn (reg, ar_unat_save_reg);
3495 gcc_assert (cfa_off == current_frame_info.spill_cfa_off);
3497 finish_spill_pointers ();
3499 if (current_frame_info.total_size
3500 || cfun->machine->ia64_eh_epilogue_sp
3501 || frame_pointer_needed)
3503 /* ??? At this point we must generate a magic insn that appears to
3504 modify the spill iterators, the stack pointer, and the frame
3505 pointer. This would allow the most scheduling freedom. For now,
3507 emit_insn (gen_blockage ());
3510 if (cfun->machine->ia64_eh_epilogue_sp)
3511 emit_move_insn (stack_pointer_rtx, cfun->machine->ia64_eh_epilogue_sp);
3512 else if (frame_pointer_needed)
3514 insn = emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
3515 RTX_FRAME_RELATED_P (insn) = 1;
3517 else if (current_frame_info.total_size)
3519 rtx offset, frame_size_rtx;
3521 frame_size_rtx = GEN_INT (current_frame_info.total_size);
3522 if (satisfies_constraint_I (frame_size_rtx))
3523 offset = frame_size_rtx;
3526 regno = next_scratch_gr_reg ();
3527 offset = gen_rtx_REG (DImode, regno);
3528 emit_move_insn (offset, frame_size_rtx);
3531 insn = emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
3534 RTX_FRAME_RELATED_P (insn) = 1;
3535 if (GET_CODE (offset) != CONST_INT)
3538 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3539 gen_rtx_SET (VOIDmode,
3541 gen_rtx_PLUS (DImode,
3548 if (cfun->machine->ia64_eh_epilogue_bsp)
3549 emit_insn (gen_set_bsp (cfun->machine->ia64_eh_epilogue_bsp));
3552 emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode, BR_REG (0))));
3555 int fp = GR_REG (2);
3556 /* We need a throw away register here, r0 and r1 are reserved, so r2 is the
3557 first available call clobbered register. If there was a frame_pointer
3558 register, we may have swapped the names of r2 and HARD_FRAME_POINTER_REGNUM,
3559 so we have to make sure we're using the string "r2" when emitting
3560 the register name for the assembler. */
3561 if (current_frame_info.r[reg_fp]
3562 && current_frame_info.r[reg_fp] == GR_REG (2))
3563 fp = HARD_FRAME_POINTER_REGNUM;
3565 /* We must emit an alloc to force the input registers to become output
3566 registers. Otherwise, if the callee tries to pass its parameters
3567 through to another call without an intervening alloc, then these
3569 /* ??? We don't need to preserve all input registers. We only need to
3570 preserve those input registers used as arguments to the sibling call.
3571 It is unclear how to compute that number here. */
3572 if (current_frame_info.n_input_regs != 0)
3574 rtx n_inputs = GEN_INT (current_frame_info.n_input_regs);
3575 insn = emit_insn (gen_alloc (gen_rtx_REG (DImode, fp),
3576 const0_rtx, const0_rtx,
3577 n_inputs, const0_rtx));
3578 RTX_FRAME_RELATED_P (insn) = 1;
3583 /* Return 1 if br.ret can do all the work required to return from a
3587 ia64_direct_return (void)
3589 if (reload_completed && ! frame_pointer_needed)
3591 ia64_compute_frame_size (get_frame_size ());
3593 return (current_frame_info.total_size == 0
3594 && current_frame_info.n_spilled == 0
3595 && current_frame_info.r[reg_save_b0] == 0
3596 && current_frame_info.r[reg_save_pr] == 0
3597 && current_frame_info.r[reg_save_ar_pfs] == 0
3598 && current_frame_info.r[reg_save_ar_unat] == 0
3599 && current_frame_info.r[reg_save_ar_lc] == 0);
3604 /* Return the magic cookie that we use to hold the return address
3605 during early compilation. */
3608 ia64_return_addr_rtx (HOST_WIDE_INT count, rtx frame ATTRIBUTE_UNUSED)
3612 return gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_RET_ADDR);
3615 /* Split this value after reload, now that we know where the return
3616 address is saved. */
3619 ia64_split_return_addr_rtx (rtx dest)
3623 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3625 if (current_frame_info.r[reg_save_b0] != 0)
3627 src = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]);
3628 reg_emitted (reg_save_b0);
3636 /* Compute offset from CFA for BR0. */
3637 /* ??? Must be kept in sync with ia64_expand_prologue. */
3638 off = (current_frame_info.spill_cfa_off
3639 + current_frame_info.spill_size);
3640 for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
3641 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3644 /* Convert CFA offset to a register based offset. */
3645 if (frame_pointer_needed)
3646 src = hard_frame_pointer_rtx;
3649 src = stack_pointer_rtx;
3650 off += current_frame_info.total_size;
3653 /* Load address into scratch register. */
3654 off_r = GEN_INT (off);
3655 if (satisfies_constraint_I (off_r))
3656 emit_insn (gen_adddi3 (dest, src, off_r));
3659 emit_move_insn (dest, off_r);
3660 emit_insn (gen_adddi3 (dest, src, dest));
3663 src = gen_rtx_MEM (Pmode, dest);
3667 src = gen_rtx_REG (DImode, BR_REG (0));
3669 emit_move_insn (dest, src);
3673 ia64_hard_regno_rename_ok (int from, int to)
3675 /* Don't clobber any of the registers we reserved for the prologue. */
3676 enum ia64_frame_regs r;
3678 for (r = reg_fp; r <= reg_save_ar_lc; r++)
3679 if (to == current_frame_info.r[r]
3680 || from == current_frame_info.r[r]
3681 || to == emitted_frame_related_regs[r]
3682 || from == emitted_frame_related_regs[r])
3685 /* Don't use output registers outside the register frame. */
3686 if (OUT_REGNO_P (to) && to >= OUT_REG (current_frame_info.n_output_regs))
3689 /* Retain even/oddness on predicate register pairs. */
3690 if (PR_REGNO_P (from) && PR_REGNO_P (to))
3691 return (from & 1) == (to & 1);
3696 /* Target hook for assembling integer objects. Handle word-sized
3697 aligned objects and detect the cases when @fptr is needed. */
3700 ia64_assemble_integer (rtx x, unsigned int size, int aligned_p)
3702 if (size == POINTER_SIZE / BITS_PER_UNIT
3703 && !(TARGET_NO_PIC || TARGET_AUTO_PIC)
3704 && GET_CODE (x) == SYMBOL_REF
3705 && SYMBOL_REF_FUNCTION_P (x))
3707 static const char * const directive[2][2] = {
3708 /* 64-bit pointer */ /* 32-bit pointer */
3709 { "\tdata8.ua\t@fptr(", "\tdata4.ua\t@fptr("}, /* unaligned */
3710 { "\tdata8\t@fptr(", "\tdata4\t@fptr("} /* aligned */
3712 fputs (directive[(aligned_p != 0)][POINTER_SIZE == 32], asm_out_file);
3713 output_addr_const (asm_out_file, x);
3714 fputs (")\n", asm_out_file);
3717 return default_assemble_integer (x, size, aligned_p);
3720 /* Emit the function prologue. */
3723 ia64_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3725 int mask, grsave, grsave_prev;
3727 if (current_frame_info.need_regstk)
3728 fprintf (file, "\t.regstk %d, %d, %d, %d\n",
3729 current_frame_info.n_input_regs,
3730 current_frame_info.n_local_regs,
3731 current_frame_info.n_output_regs,
3732 current_frame_info.n_rotate_regs);
3734 if (!flag_unwind_tables && (!flag_exceptions || USING_SJLJ_EXCEPTIONS))
3737 /* Emit the .prologue directive. */
3740 grsave = grsave_prev = 0;
3741 if (current_frame_info.r[reg_save_b0] != 0)
3744 grsave = grsave_prev = current_frame_info.r[reg_save_b0];
3746 if (current_frame_info.r[reg_save_ar_pfs] != 0
3747 && (grsave_prev == 0
3748 || current_frame_info.r[reg_save_ar_pfs] == grsave_prev + 1))
3751 if (grsave_prev == 0)
3752 grsave = current_frame_info.r[reg_save_ar_pfs];
3753 grsave_prev = current_frame_info.r[reg_save_ar_pfs];
3755 if (current_frame_info.r[reg_fp] != 0
3756 && (grsave_prev == 0
3757 || current_frame_info.r[reg_fp] == grsave_prev + 1))
3760 if (grsave_prev == 0)
3761 grsave = HARD_FRAME_POINTER_REGNUM;
3762 grsave_prev = current_frame_info.r[reg_fp];
3764 if (current_frame_info.r[reg_save_pr] != 0
3765 && (grsave_prev == 0
3766 || current_frame_info.r[reg_save_pr] == grsave_prev + 1))
3769 if (grsave_prev == 0)
3770 grsave = current_frame_info.r[reg_save_pr];
3773 if (mask && TARGET_GNU_AS)
3774 fprintf (file, "\t.prologue %d, %d\n", mask,
3775 ia64_dbx_register_number (grsave));
3777 fputs ("\t.prologue\n", file);
3779 /* Emit a .spill directive, if necessary, to relocate the base of
3780 the register spill area. */
3781 if (current_frame_info.spill_cfa_off != -16)
3782 fprintf (file, "\t.spill %ld\n",
3783 (long) (current_frame_info.spill_cfa_off
3784 + current_frame_info.spill_size));
3787 /* Emit the .body directive at the scheduled end of the prologue. */
3790 ia64_output_function_end_prologue (FILE *file)
3792 if (!flag_unwind_tables && (!flag_exceptions || USING_SJLJ_EXCEPTIONS))
3795 fputs ("\t.body\n", file);
3798 /* Emit the function epilogue. */
3801 ia64_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
3802 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3806 if (current_frame_info.r[reg_fp])
3808 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
3809 reg_names[HARD_FRAME_POINTER_REGNUM]
3810 = reg_names[current_frame_info.r[reg_fp]];
3811 reg_names[current_frame_info.r[reg_fp]] = tmp;
3812 reg_emitted (reg_fp);
3814 if (! TARGET_REG_NAMES)
3816 for (i = 0; i < current_frame_info.n_input_regs; i++)
3817 reg_names[IN_REG (i)] = ia64_input_reg_names[i];
3818 for (i = 0; i < current_frame_info.n_local_regs; i++)
3819 reg_names[LOC_REG (i)] = ia64_local_reg_names[i];
3820 for (i = 0; i < current_frame_info.n_output_regs; i++)
3821 reg_names[OUT_REG (i)] = ia64_output_reg_names[i];
3824 current_frame_info.initialized = 0;
3828 ia64_dbx_register_number (int regno)
3830 /* In ia64_expand_prologue we quite literally renamed the frame pointer
3831 from its home at loc79 to something inside the register frame. We
3832 must perform the same renumbering here for the debug info. */
3833 if (current_frame_info.r[reg_fp])
3835 if (regno == HARD_FRAME_POINTER_REGNUM)
3836 regno = current_frame_info.r[reg_fp];
3837 else if (regno == current_frame_info.r[reg_fp])
3838 regno = HARD_FRAME_POINTER_REGNUM;
3841 if (IN_REGNO_P (regno))
3842 return 32 + regno - IN_REG (0);
3843 else if (LOC_REGNO_P (regno))
3844 return 32 + current_frame_info.n_input_regs + regno - LOC_REG (0);
3845 else if (OUT_REGNO_P (regno))
3846 return (32 + current_frame_info.n_input_regs
3847 + current_frame_info.n_local_regs + regno - OUT_REG (0));
3853 ia64_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
3855 rtx addr_reg, eight = GEN_INT (8);
3857 /* The Intel assembler requires that the global __ia64_trampoline symbol
3858 be declared explicitly */
3861 static bool declared_ia64_trampoline = false;
3863 if (!declared_ia64_trampoline)
3865 declared_ia64_trampoline = true;
3866 (*targetm.asm_out.globalize_label) (asm_out_file,
3867 "__ia64_trampoline");
3871 /* Make sure addresses are Pmode even if we are in ILP32 mode. */
3872 addr = convert_memory_address (Pmode, addr);
3873 fnaddr = convert_memory_address (Pmode, fnaddr);
3874 static_chain = convert_memory_address (Pmode, static_chain);
3876 /* Load up our iterator. */
3877 addr_reg = gen_reg_rtx (Pmode);
3878 emit_move_insn (addr_reg, addr);
3880 /* The first two words are the fake descriptor:
3881 __ia64_trampoline, ADDR+16. */
3882 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg),
3883 gen_rtx_SYMBOL_REF (Pmode, "__ia64_trampoline"));
3884 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
3886 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg),
3887 copy_to_reg (plus_constant (addr, 16)));
3888 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
3890 /* The third word is the target descriptor. */
3891 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg), fnaddr);
3892 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
3894 /* The fourth word is the static chain. */
3895 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg), static_chain);
3898 /* Do any needed setup for a variadic function. CUM has not been updated
3899 for the last named argument which has type TYPE and mode MODE.
3901 We generate the actual spill instructions during prologue generation. */
3904 ia64_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3905 tree type, int * pretend_size,
3906 int second_time ATTRIBUTE_UNUSED)
3908 CUMULATIVE_ARGS next_cum = *cum;
3910 /* Skip the current argument. */
3911 ia64_function_arg_advance (&next_cum, mode, type, 1);
3913 if (next_cum.words < MAX_ARGUMENT_SLOTS)
3915 int n = MAX_ARGUMENT_SLOTS - next_cum.words;
3916 *pretend_size = n * UNITS_PER_WORD;
3917 cfun->machine->n_varargs = n;
3921 /* Check whether TYPE is a homogeneous floating point aggregate. If
3922 it is, return the mode of the floating point type that appears
3923 in all leafs. If it is not, return VOIDmode.
3925 An aggregate is a homogeneous floating point aggregate is if all
3926 fields/elements in it have the same floating point type (e.g,
3927 SFmode). 128-bit quad-precision floats are excluded.
3929 Variable sized aggregates should never arrive here, since we should
3930 have already decided to pass them by reference. Top-level zero-sized
3931 aggregates are excluded because our parallels crash the middle-end. */
3933 static enum machine_mode
3934 hfa_element_mode (const_tree type, bool nested)
3936 enum machine_mode element_mode = VOIDmode;
3937 enum machine_mode mode;
3938 enum tree_code code = TREE_CODE (type);
3939 int know_element_mode = 0;
3942 if (!nested && (!TYPE_SIZE (type) || integer_zerop (TYPE_SIZE (type))))
3947 case VOID_TYPE: case INTEGER_TYPE: case ENUMERAL_TYPE:
3948 case BOOLEAN_TYPE: case POINTER_TYPE:
3949 case OFFSET_TYPE: case REFERENCE_TYPE: case METHOD_TYPE:
3950 case LANG_TYPE: case FUNCTION_TYPE:
3953 /* Fortran complex types are supposed to be HFAs, so we need to handle
3954 gcc's COMPLEX_TYPEs as HFAs. We need to exclude the integral complex
3957 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_FLOAT
3958 && TYPE_MODE (type) != TCmode)
3959 return GET_MODE_INNER (TYPE_MODE (type));
3964 /* We want to return VOIDmode for raw REAL_TYPEs, but the actual
3965 mode if this is contained within an aggregate. */
3966 if (nested && TYPE_MODE (type) != TFmode)
3967 return TYPE_MODE (type);
3972 return hfa_element_mode (TREE_TYPE (type), 1);
3976 case QUAL_UNION_TYPE:
3977 for (t = TYPE_FIELDS (type); t; t = TREE_CHAIN (t))
3979 if (TREE_CODE (t) != FIELD_DECL)
3982 mode = hfa_element_mode (TREE_TYPE (t), 1);
3983 if (know_element_mode)
3985 if (mode != element_mode)
3988 else if (GET_MODE_CLASS (mode) != MODE_FLOAT)
3992 know_element_mode = 1;
3993 element_mode = mode;
3996 return element_mode;
3999 /* If we reach here, we probably have some front-end specific type
4000 that the backend doesn't know about. This can happen via the
4001 aggregate_value_p call in init_function_start. All we can do is
4002 ignore unknown tree types. */
4009 /* Return the number of words required to hold a quantity of TYPE and MODE
4010 when passed as an argument. */
4012 ia64_function_arg_words (tree type, enum machine_mode mode)
4016 if (mode == BLKmode)
4017 words = int_size_in_bytes (type);
4019 words = GET_MODE_SIZE (mode);
4021 return (words + UNITS_PER_WORD - 1) / UNITS_PER_WORD; /* round up */
4024 /* Return the number of registers that should be skipped so the current
4025 argument (described by TYPE and WORDS) will be properly aligned.
4027 Integer and float arguments larger than 8 bytes start at the next
4028 even boundary. Aggregates larger than 8 bytes start at the next
4029 even boundary if the aggregate has 16 byte alignment. Note that
4030 in the 32-bit ABI, TImode and TFmode have only 8-byte alignment
4031 but are still to be aligned in registers.
4033 ??? The ABI does not specify how to handle aggregates with
4034 alignment from 9 to 15 bytes, or greater than 16. We handle them
4035 all as if they had 16 byte alignment. Such aggregates can occur
4036 only if gcc extensions are used. */
4038 ia64_function_arg_offset (CUMULATIVE_ARGS *cum, tree type, int words)
4040 if ((cum->words & 1) == 0)
4044 && TREE_CODE (type) != INTEGER_TYPE
4045 && TREE_CODE (type) != REAL_TYPE)
4046 return TYPE_ALIGN (type) > 8 * BITS_PER_UNIT;
4051 /* Return rtx for register where argument is passed, or zero if it is passed
4053 /* ??? 128-bit quad-precision floats are always passed in general
4057 ia64_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
4058 int named, int incoming)
4060 int basereg = (incoming ? GR_ARG_FIRST : AR_ARG_FIRST);
4061 int words = ia64_function_arg_words (type, mode);
4062 int offset = ia64_function_arg_offset (cum, type, words);
4063 enum machine_mode hfa_mode = VOIDmode;
4065 /* If all argument slots are used, then it must go on the stack. */
4066 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
4069 /* Check for and handle homogeneous FP aggregates. */
4071 hfa_mode = hfa_element_mode (type, 0);
4073 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
4074 and unprototyped hfas are passed specially. */
4075 if (hfa_mode != VOIDmode && (! cum->prototype || named))
4079 int fp_regs = cum->fp_regs;
4080 int int_regs = cum->words + offset;
4081 int hfa_size = GET_MODE_SIZE (hfa_mode);
4085 /* If prototyped, pass it in FR regs then GR regs.
4086 If not prototyped, pass it in both FR and GR regs.
4088 If this is an SFmode aggregate, then it is possible to run out of
4089 FR regs while GR regs are still left. In that case, we pass the
4090 remaining part in the GR regs. */
4092 /* Fill the FP regs. We do this always. We stop if we reach the end
4093 of the argument, the last FP register, or the last argument slot. */
4095 byte_size = ((mode == BLKmode)
4096 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4097 args_byte_size = int_regs * UNITS_PER_WORD;
4099 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
4100 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD)); i++)
4102 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4103 gen_rtx_REG (hfa_mode, (FR_ARG_FIRST
4107 args_byte_size += hfa_size;
4111 /* If no prototype, then the whole thing must go in GR regs. */
4112 if (! cum->prototype)
4114 /* If this is an SFmode aggregate, then we might have some left over
4115 that needs to go in GR regs. */
4116 else if (byte_size != offset)
4117 int_regs += offset / UNITS_PER_WORD;
4119 /* Fill in the GR regs. We must use DImode here, not the hfa mode. */
4121 for (; offset < byte_size && int_regs < MAX_ARGUMENT_SLOTS; i++)
4123 enum machine_mode gr_mode = DImode;
4124 unsigned int gr_size;
4126 /* If we have an odd 4 byte hunk because we ran out of FR regs,
4127 then this goes in a GR reg left adjusted/little endian, right
4128 adjusted/big endian. */
4129 /* ??? Currently this is handled wrong, because 4-byte hunks are
4130 always right adjusted/little endian. */
4133 /* If we have an even 4 byte hunk because the aggregate is a
4134 multiple of 4 bytes in size, then this goes in a GR reg right
4135 adjusted/little endian. */
4136 else if (byte_size - offset == 4)
4139 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4140 gen_rtx_REG (gr_mode, (basereg
4144 gr_size = GET_MODE_SIZE (gr_mode);
4146 if (gr_size == UNITS_PER_WORD
4147 || (gr_size < UNITS_PER_WORD && offset % UNITS_PER_WORD == 0))
4149 else if (gr_size > UNITS_PER_WORD)
4150 int_regs += gr_size / UNITS_PER_WORD;
4152 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4155 /* Integral and aggregates go in general registers. If we have run out of
4156 FR registers, then FP values must also go in general registers. This can
4157 happen when we have a SFmode HFA. */
4158 else if (mode == TFmode || mode == TCmode
4159 || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
4161 int byte_size = ((mode == BLKmode)
4162 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4163 if (BYTES_BIG_ENDIAN
4164 && (mode == BLKmode || (type && AGGREGATE_TYPE_P (type)))
4165 && byte_size < UNITS_PER_WORD
4168 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
4169 gen_rtx_REG (DImode,
4170 (basereg + cum->words
4173 return gen_rtx_PARALLEL (mode, gen_rtvec (1, gr_reg));
4176 return gen_rtx_REG (mode, basereg + cum->words + offset);
4180 /* If there is a prototype, then FP values go in a FR register when
4181 named, and in a GR register when unnamed. */
4182 else if (cum->prototype)
4185 return gen_rtx_REG (mode, FR_ARG_FIRST + cum->fp_regs);
4186 /* In big-endian mode, an anonymous SFmode value must be represented
4187 as (parallel:SF [(expr_list (reg:DI n) (const_int 0))]) to force
4188 the value into the high half of the general register. */
4189 else if (BYTES_BIG_ENDIAN && mode == SFmode)
4190 return gen_rtx_PARALLEL (mode,
4192 gen_rtx_EXPR_LIST (VOIDmode,
4193 gen_rtx_REG (DImode, basereg + cum->words + offset),
4196 return gen_rtx_REG (mode, basereg + cum->words + offset);
4198 /* If there is no prototype, then FP values go in both FR and GR
4202 /* See comment above. */
4203 enum machine_mode inner_mode =
4204 (BYTES_BIG_ENDIAN && mode == SFmode) ? DImode : mode;
4206 rtx fp_reg = gen_rtx_EXPR_LIST (VOIDmode,
4207 gen_rtx_REG (mode, (FR_ARG_FIRST
4210 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
4211 gen_rtx_REG (inner_mode,
4212 (basereg + cum->words
4216 return gen_rtx_PARALLEL (mode, gen_rtvec (2, fp_reg, gr_reg));
4220 /* Return number of bytes, at the beginning of the argument, that must be
4221 put in registers. 0 is the argument is entirely in registers or entirely
4225 ia64_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4226 tree type, bool named ATTRIBUTE_UNUSED)
4228 int words = ia64_function_arg_words (type, mode);
4229 int offset = ia64_function_arg_offset (cum, type, words);
4231 /* If all argument slots are used, then it must go on the stack. */
4232 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
4235 /* It doesn't matter whether the argument goes in FR or GR regs. If
4236 it fits within the 8 argument slots, then it goes entirely in
4237 registers. If it extends past the last argument slot, then the rest
4238 goes on the stack. */
4240 if (words + cum->words + offset <= MAX_ARGUMENT_SLOTS)
4243 return (MAX_ARGUMENT_SLOTS - cum->words - offset) * UNITS_PER_WORD;
4246 /* Update CUM to point after this argument. This is patterned after
4247 ia64_function_arg. */
4250 ia64_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4251 tree type, int named)
4253 int words = ia64_function_arg_words (type, mode);
4254 int offset = ia64_function_arg_offset (cum, type, words);
4255 enum machine_mode hfa_mode = VOIDmode;
4257 /* If all arg slots are already full, then there is nothing to do. */
4258 if (cum->words >= MAX_ARGUMENT_SLOTS)
4261 cum->words += words + offset;
4263 /* Check for and handle homogeneous FP aggregates. */
4265 hfa_mode = hfa_element_mode (type, 0);
4267 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
4268 and unprototyped hfas are passed specially. */
4269 if (hfa_mode != VOIDmode && (! cum->prototype || named))
4271 int fp_regs = cum->fp_regs;
4272 /* This is the original value of cum->words + offset. */
4273 int int_regs = cum->words - words;
4274 int hfa_size = GET_MODE_SIZE (hfa_mode);
4278 /* If prototyped, pass it in FR regs then GR regs.
4279 If not prototyped, pass it in both FR and GR regs.
4281 If this is an SFmode aggregate, then it is possible to run out of
4282 FR regs while GR regs are still left. In that case, we pass the
4283 remaining part in the GR regs. */
4285 /* Fill the FP regs. We do this always. We stop if we reach the end
4286 of the argument, the last FP register, or the last argument slot. */
4288 byte_size = ((mode == BLKmode)
4289 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4290 args_byte_size = int_regs * UNITS_PER_WORD;
4292 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
4293 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD));)
4296 args_byte_size += hfa_size;
4300 cum->fp_regs = fp_regs;
4303 /* Integral and aggregates go in general registers. So do TFmode FP values.
4304 If we have run out of FR registers, then other FP values must also go in
4305 general registers. This can happen when we have a SFmode HFA. */
4306 else if (mode == TFmode || mode == TCmode
4307 || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
4308 cum->int_regs = cum->words;
4310 /* If there is a prototype, then FP values go in a FR register when
4311 named, and in a GR register when unnamed. */
4312 else if (cum->prototype)
4315 cum->int_regs = cum->words;
4317 /* ??? Complex types should not reach here. */
4318 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
4320 /* If there is no prototype, then FP values go in both FR and GR
4324 /* ??? Complex types should not reach here. */
4325 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
4326 cum->int_regs = cum->words;
4330 /* Arguments with alignment larger than 8 bytes start at the next even
4331 boundary. On ILP32 HPUX, TFmode arguments start on next even boundary
4332 even though their normal alignment is 8 bytes. See ia64_function_arg. */
4335 ia64_function_arg_boundary (enum machine_mode mode, tree type)
4338 if (mode == TFmode && TARGET_HPUX && TARGET_ILP32)
4339 return PARM_BOUNDARY * 2;
4343 if (TYPE_ALIGN (type) > PARM_BOUNDARY)
4344 return PARM_BOUNDARY * 2;
4346 return PARM_BOUNDARY;
4349 if (GET_MODE_BITSIZE (mode) > PARM_BOUNDARY)
4350 return PARM_BOUNDARY * 2;
4352 return PARM_BOUNDARY;
4355 /* True if it is OK to do sibling call optimization for the specified
4356 call expression EXP. DECL will be the called function, or NULL if
4357 this is an indirect call. */
4359 ia64_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
4361 /* We can't perform a sibcall if the current function has the syscall_linkage
4363 if (lookup_attribute ("syscall_linkage",
4364 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
4367 /* We must always return with our current GP. This means we can
4368 only sibcall to functions defined in the current module unless
4369 TARGET_CONST_GP is set to true. */
4370 return (decl && (*targetm.binds_local_p) (decl)) || TARGET_CONST_GP;
4374 /* Implement va_arg. */
4377 ia64_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
4380 /* Variable sized types are passed by reference. */
4381 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
4383 tree ptrtype = build_pointer_type (type);
4384 tree addr = std_gimplify_va_arg_expr (valist, ptrtype, pre_p, post_p);
4385 return build_va_arg_indirect_ref (addr);
4388 /* Aggregate arguments with alignment larger than 8 bytes start at
4389 the next even boundary. Integer and floating point arguments
4390 do so if they are larger than 8 bytes, whether or not they are
4391 also aligned larger than 8 bytes. */
4392 if ((TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == INTEGER_TYPE)
4393 ? int_size_in_bytes (type) > 8 : TYPE_ALIGN (type) > 8 * BITS_PER_UNIT)
4395 tree t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (valist), valist,
4396 size_int (2 * UNITS_PER_WORD - 1));
4397 t = fold_convert (sizetype, t);
4398 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
4399 size_int (-2 * UNITS_PER_WORD));
4400 t = fold_convert (TREE_TYPE (valist), t);
4401 gimplify_assign (unshare_expr (valist), t, pre_p);
4404 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4407 /* Return 1 if function return value returned in memory. Return 0 if it is
4411 ia64_return_in_memory (const_tree valtype, const_tree fntype ATTRIBUTE_UNUSED)
4413 enum machine_mode mode;
4414 enum machine_mode hfa_mode;
4415 HOST_WIDE_INT byte_size;
4417 mode = TYPE_MODE (valtype);
4418 byte_size = GET_MODE_SIZE (mode);
4419 if (mode == BLKmode)
4421 byte_size = int_size_in_bytes (valtype);
4426 /* Hfa's with up to 8 elements are returned in the FP argument registers. */
4428 hfa_mode = hfa_element_mode (valtype, 0);
4429 if (hfa_mode != VOIDmode)
4431 int hfa_size = GET_MODE_SIZE (hfa_mode);
4433 if (byte_size / hfa_size > MAX_ARGUMENT_SLOTS)
4438 else if (byte_size > UNITS_PER_WORD * MAX_INT_RETURN_SLOTS)
4444 /* Return rtx for register that holds the function return value. */
4447 ia64_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED)
4449 enum machine_mode mode;
4450 enum machine_mode hfa_mode;
4452 mode = TYPE_MODE (valtype);
4453 hfa_mode = hfa_element_mode (valtype, 0);
4455 if (hfa_mode != VOIDmode)
4463 hfa_size = GET_MODE_SIZE (hfa_mode);
4464 byte_size = ((mode == BLKmode)
4465 ? int_size_in_bytes (valtype) : GET_MODE_SIZE (mode));
4467 for (i = 0; offset < byte_size; i++)
4469 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4470 gen_rtx_REG (hfa_mode, FR_ARG_FIRST + i),
4474 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4476 else if (FLOAT_TYPE_P (valtype) && mode != TFmode && mode != TCmode)
4477 return gen_rtx_REG (mode, FR_ARG_FIRST);
4480 bool need_parallel = false;
4482 /* In big-endian mode, we need to manage the layout of aggregates
4483 in the registers so that we get the bits properly aligned in
4484 the highpart of the registers. */
4485 if (BYTES_BIG_ENDIAN
4486 && (mode == BLKmode || (valtype && AGGREGATE_TYPE_P (valtype))))
4487 need_parallel = true;
4489 /* Something like struct S { long double x; char a[0] } is not an
4490 HFA structure, and therefore doesn't go in fp registers. But
4491 the middle-end will give it XFmode anyway, and XFmode values
4492 don't normally fit in integer registers. So we need to smuggle
4493 the value inside a parallel. */
4494 else if (mode == XFmode || mode == XCmode || mode == RFmode)
4495 need_parallel = true;
4505 bytesize = int_size_in_bytes (valtype);
4506 /* An empty PARALLEL is invalid here, but the return value
4507 doesn't matter for empty structs. */
4509 return gen_rtx_REG (mode, GR_RET_FIRST);
4510 for (i = 0; offset < bytesize; i++)
4512 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4513 gen_rtx_REG (DImode,
4516 offset += UNITS_PER_WORD;
4518 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4521 return gen_rtx_REG (mode, GR_RET_FIRST);
4525 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4526 We need to emit DTP-relative relocations. */
4529 ia64_output_dwarf_dtprel (FILE *file, int size, rtx x)
4531 gcc_assert (size == 4 || size == 8);
4533 fputs ("\tdata4.ua\t@dtprel(", file);
4535 fputs ("\tdata8.ua\t@dtprel(", file);
4536 output_addr_const (file, x);
4540 /* Print a memory address as an operand to reference that memory location. */
4542 /* ??? Do we need this? It gets used only for 'a' operands. We could perhaps
4543 also call this from ia64_print_operand for memory addresses. */
4546 ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED,
4547 rtx address ATTRIBUTE_UNUSED)
4551 /* Print an operand to an assembler instruction.
4552 C Swap and print a comparison operator.
4553 D Print an FP comparison operator.
4554 E Print 32 - constant, for SImode shifts as extract.
4555 e Print 64 - constant, for DImode rotates.
4556 F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
4557 a floating point register emitted normally.
4558 I Invert a predicate register by adding 1.
4559 J Select the proper predicate register for a condition.
4560 j Select the inverse predicate register for a condition.
4561 O Append .acq for volatile load.
4562 P Postincrement of a MEM.
4563 Q Append .rel for volatile store.
4564 R Print .s .d or nothing for a single, double or no truncation.
4565 S Shift amount for shladd instruction.
4566 T Print an 8-bit sign extended number (K) as a 32-bit unsigned number
4567 for Intel assembler.
4568 U Print an 8-bit sign extended number (K) as a 64-bit unsigned number
4569 for Intel assembler.
4570 X A pair of floating point registers.
4571 r Print register name, or constant 0 as r0. HP compatibility for
4573 v Print vector constant value as an 8-byte integer value. */
4576 ia64_print_operand (FILE * file, rtx x, int code)
4583 /* Handled below. */
4588 enum rtx_code c = swap_condition (GET_CODE (x));
4589 fputs (GET_RTX_NAME (c), file);
4594 switch (GET_CODE (x))
4618 str = GET_RTX_NAME (GET_CODE (x));
4625 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - INTVAL (x));
4629 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - INTVAL (x));
4633 if (x == CONST0_RTX (GET_MODE (x)))
4634 str = reg_names [FR_REG (0)];
4635 else if (x == CONST1_RTX (GET_MODE (x)))
4636 str = reg_names [FR_REG (1)];
4639 gcc_assert (GET_CODE (x) == REG);
4640 str = reg_names [REGNO (x)];
4646 fputs (reg_names [REGNO (x) + 1], file);
4652 unsigned int regno = REGNO (XEXP (x, 0));
4653 if (GET_CODE (x) == EQ)
4657 fputs (reg_names [regno], file);
4662 if (MEM_VOLATILE_P (x))
4663 fputs(".acq", file);
4668 HOST_WIDE_INT value;
4670 switch (GET_CODE (XEXP (x, 0)))
4676 x = XEXP (XEXP (XEXP (x, 0), 1), 1);
4677 if (GET_CODE (x) == CONST_INT)
4681 gcc_assert (GET_CODE (x) == REG);
4682 fprintf (file, ", %s", reg_names[REGNO (x)]);
4688 value = GET_MODE_SIZE (GET_MODE (x));
4692 value = - (HOST_WIDE_INT) GET_MODE_SIZE (GET_MODE (x));
4696 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC, value);
4701 if (MEM_VOLATILE_P (x))
4702 fputs(".rel", file);
4706 if (x == CONST0_RTX (GET_MODE (x)))
4708 else if (x == CONST1_RTX (GET_MODE (x)))
4710 else if (x == CONST2_RTX (GET_MODE (x)))
4713 output_operand_lossage ("invalid %%R value");
4717 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4721 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
4723 fprintf (file, "0x%x", (int) INTVAL (x) & 0xffffffff);
4729 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
4731 const char *prefix = "0x";
4732 if (INTVAL (x) & 0x80000000)
4734 fprintf (file, "0xffffffff");
4737 fprintf (file, "%s%x", prefix, (int) INTVAL (x) & 0xffffffff);
4744 unsigned int regno = REGNO (x);
4745 fprintf (file, "%s, %s", reg_names [regno], reg_names [regno + 1]);
4750 /* If this operand is the constant zero, write it as register zero.
4751 Any register, zero, or CONST_INT value is OK here. */
4752 if (GET_CODE (x) == REG)
4753 fputs (reg_names[REGNO (x)], file);
4754 else if (x == CONST0_RTX (GET_MODE (x)))
4756 else if (GET_CODE (x) == CONST_INT)
4757 output_addr_const (file, x);
4759 output_operand_lossage ("invalid %%r value");
4763 gcc_assert (GET_CODE (x) == CONST_VECTOR);
4764 x = simplify_subreg (DImode, x, GET_MODE (x), 0);
4771 /* For conditional branches, returns or calls, substitute
4772 sptk, dptk, dpnt, or spnt for %s. */
4773 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
4776 int pred_val = INTVAL (XEXP (x, 0));
4778 /* Guess top and bottom 10% statically predicted. */
4779 if (pred_val < REG_BR_PROB_BASE / 50
4780 && br_prob_note_reliable_p (x))
4782 else if (pred_val < REG_BR_PROB_BASE / 2)
4784 else if (pred_val < REG_BR_PROB_BASE / 100 * 98
4785 || !br_prob_note_reliable_p (x))
4790 else if (GET_CODE (current_output_insn) == CALL_INSN)
4795 fputs (which, file);
4800 x = current_insn_predicate;
4803 unsigned int regno = REGNO (XEXP (x, 0));
4804 if (GET_CODE (x) == EQ)
4806 fprintf (file, "(%s) ", reg_names [regno]);
4811 output_operand_lossage ("ia64_print_operand: unknown code");
4815 switch (GET_CODE (x))
4817 /* This happens for the spill/restore instructions. */
4822 /* ... fall through ... */
4825 fputs (reg_names [REGNO (x)], file);
4830 rtx addr = XEXP (x, 0);
4831 if (GET_RTX_CLASS (GET_CODE (addr)) == RTX_AUTOINC)
4832 addr = XEXP (addr, 0);
4833 fprintf (file, "[%s]", reg_names [REGNO (addr)]);
4838 output_addr_const (file, x);
4845 /* Compute a (partial) cost for rtx X. Return true if the complete
4846 cost has been computed, and false if subexpressions should be
4847 scanned. In either case, *TOTAL contains the cost result. */
4848 /* ??? This is incomplete. */
4851 ia64_rtx_costs (rtx x, int code, int outer_code, int *total,
4852 bool speed ATTRIBUTE_UNUSED)
4860 *total = satisfies_constraint_J (x) ? 0 : COSTS_N_INSNS (1);
4863 if (satisfies_constraint_I (x))
4865 else if (satisfies_constraint_J (x))
4868 *total = COSTS_N_INSNS (1);
4871 if (satisfies_constraint_K (x) || satisfies_constraint_L (x))
4874 *total = COSTS_N_INSNS (1);
4879 *total = COSTS_N_INSNS (1);
4885 *total = COSTS_N_INSNS (3);
4889 /* For multiplies wider than HImode, we have to go to the FPU,
4890 which normally involves copies. Plus there's the latency
4891 of the multiply itself, and the latency of the instructions to
4892 transfer integer regs to FP regs. */
4893 /* ??? Check for FP mode. */
4894 if (GET_MODE_SIZE (GET_MODE (x)) > 2)
4895 *total = COSTS_N_INSNS (10);
4897 *total = COSTS_N_INSNS (2);
4905 *total = COSTS_N_INSNS (1);
4912 /* We make divide expensive, so that divide-by-constant will be
4913 optimized to a multiply. */
4914 *total = COSTS_N_INSNS (60);
4922 /* Calculate the cost of moving data from a register in class FROM to
4923 one in class TO, using MODE. */
4926 ia64_register_move_cost (enum machine_mode mode, enum reg_class from,
4929 /* ADDL_REGS is the same as GR_REGS for movement purposes. */
4930 if (to == ADDL_REGS)
4932 if (from == ADDL_REGS)
4935 /* All costs are symmetric, so reduce cases by putting the
4936 lower number class as the destination. */
4939 enum reg_class tmp = to;
4940 to = from, from = tmp;
4943 /* Moving from FR<->GR in XFmode must be more expensive than 2,
4944 so that we get secondary memory reloads. Between FR_REGS,
4945 we have to make this at least as expensive as MEMORY_MOVE_COST
4946 to avoid spectacularly poor register class preferencing. */
4947 if (mode == XFmode || mode == RFmode)
4949 if (to != GR_REGS || from != GR_REGS)
4950 return MEMORY_MOVE_COST (mode, to, 0);
4958 /* Moving between PR registers takes two insns. */
4959 if (from == PR_REGS)
4961 /* Moving between PR and anything but GR is impossible. */
4962 if (from != GR_REGS)
4963 return MEMORY_MOVE_COST (mode, to, 0);
4967 /* Moving between BR and anything but GR is impossible. */
4968 if (from != GR_REGS && from != GR_AND_BR_REGS)
4969 return MEMORY_MOVE_COST (mode, to, 0);
4974 /* Moving between AR and anything but GR is impossible. */
4975 if (from != GR_REGS)
4976 return MEMORY_MOVE_COST (mode, to, 0);
4982 case GR_AND_FR_REGS:
4983 case GR_AND_BR_REGS:
4994 /* Implement PREFERRED_RELOAD_CLASS. Place additional restrictions on RCLASS
4995 to use when copying X into that class. */
4998 ia64_preferred_reload_class (rtx x, enum reg_class rclass)
5004 /* Don't allow volatile mem reloads into floating point registers.
5005 This is defined to force reload to choose the r/m case instead
5006 of the f/f case when reloading (set (reg fX) (mem/v)). */
5007 if (MEM_P (x) && MEM_VOLATILE_P (x))
5010 /* Force all unrecognized constants into the constant pool. */
5028 /* This function returns the register class required for a secondary
5029 register when copying between one of the registers in RCLASS, and X,
5030 using MODE. A return value of NO_REGS means that no secondary register
5034 ia64_secondary_reload_class (enum reg_class rclass,
5035 enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
5039 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
5040 regno = true_regnum (x);
5047 /* ??? BR<->BR register copies can happen due to a bad gcse/cse/global
5048 interaction. We end up with two pseudos with overlapping lifetimes
5049 both of which are equiv to the same constant, and both which need
5050 to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end
5051 changes depending on the path length, which means the qty_first_reg
5052 check in make_regs_eqv can give different answers at different times.
5053 At some point I'll probably need a reload_indi pattern to handle
5056 We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we
5057 wound up with a FP register from GR_AND_FR_REGS. Extend that to all
5058 non-general registers for good measure. */
5059 if (regno >= 0 && ! GENERAL_REGNO_P (regno))
5062 /* This is needed if a pseudo used as a call_operand gets spilled to a
5064 if (GET_CODE (x) == MEM)
5070 /* Need to go through general registers to get to other class regs. */
5071 if (regno >= 0 && ! (FR_REGNO_P (regno) || GENERAL_REGNO_P (regno)))
5074 /* This can happen when a paradoxical subreg is an operand to the
5076 /* ??? This shouldn't be necessary after instruction scheduling is
5077 enabled, because paradoxical subregs are not accepted by
5078 register_operand when INSN_SCHEDULING is defined. Or alternatively,
5079 stop the paradoxical subreg stupidity in the *_operand functions
5081 if (GET_CODE (x) == MEM
5082 && (GET_MODE (x) == SImode || GET_MODE (x) == HImode
5083 || GET_MODE (x) == QImode))
5086 /* This can happen because of the ior/and/etc patterns that accept FP
5087 registers as operands. If the third operand is a constant, then it
5088 needs to be reloaded into a FP register. */
5089 if (GET_CODE (x) == CONST_INT)
5092 /* This can happen because of register elimination in a muldi3 insn.
5093 E.g. `26107 * (unsigned long)&u'. */
5094 if (GET_CODE (x) == PLUS)
5099 /* ??? This happens if we cse/gcse a BImode value across a call,
5100 and the function has a nonlocal goto. This is because global
5101 does not allocate call crossing pseudos to hard registers when
5102 crtl->has_nonlocal_goto is true. This is relatively
5103 common for C++ programs that use exceptions. To reproduce,
5104 return NO_REGS and compile libstdc++. */
5105 if (GET_CODE (x) == MEM)
5108 /* This can happen when we take a BImode subreg of a DImode value,
5109 and that DImode value winds up in some non-GR register. */
5110 if (regno >= 0 && ! GENERAL_REGNO_P (regno) && ! PR_REGNO_P (regno))
5122 /* Implement targetm.unspec_may_trap_p hook. */
5124 ia64_unspec_may_trap_p (const_rtx x, unsigned flags)
5126 if (GET_CODE (x) == UNSPEC)
5128 switch (XINT (x, 1))
5134 case UNSPEC_CHKACLR:
5136 /* These unspecs are just wrappers. */
5137 return may_trap_p_1 (XVECEXP (x, 0, 0), flags);
5141 return default_unspec_may_trap_p (x, flags);
5145 /* Parse the -mfixed-range= option string. */
5148 fix_range (const char *const_str)
5151 char *str, *dash, *comma;
5153 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
5154 REG2 are either register names or register numbers. The effect
5155 of this option is to mark the registers in the range from REG1 to
5156 REG2 as ``fixed'' so they won't be used by the compiler. This is
5157 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
5159 i = strlen (const_str);
5160 str = (char *) alloca (i + 1);
5161 memcpy (str, const_str, i + 1);
5165 dash = strchr (str, '-');
5168 warning (0, "value of -mfixed-range must have form REG1-REG2");
5173 comma = strchr (dash + 1, ',');
5177 first = decode_reg_name (str);
5180 warning (0, "unknown register name: %s", str);
5184 last = decode_reg_name (dash + 1);
5187 warning (0, "unknown register name: %s", dash + 1);
5195 warning (0, "%s-%s is an empty range", str, dash + 1);
5199 for (i = first; i <= last; ++i)
5200 fixed_regs[i] = call_used_regs[i] = 1;
5210 /* Implement TARGET_HANDLE_OPTION. */
5213 ia64_handle_option (size_t code, const char *arg, int value)
5217 case OPT_mfixed_range_:
5221 case OPT_mtls_size_:
5222 if (value != 14 && value != 22 && value != 64)
5223 error ("bad value %<%s%> for -mtls-size= switch", arg);
5230 const char *name; /* processor name or nickname. */
5231 enum processor_type processor;
5233 const processor_alias_table[] =
5235 {"itanium", PROCESSOR_ITANIUM},
5236 {"itanium1", PROCESSOR_ITANIUM},
5237 {"merced", PROCESSOR_ITANIUM},
5238 {"itanium2", PROCESSOR_ITANIUM2},
5239 {"mckinley", PROCESSOR_ITANIUM2},
5241 int const pta_size = ARRAY_SIZE (processor_alias_table);
5244 for (i = 0; i < pta_size; i++)
5245 if (!strcmp (arg, processor_alias_table[i].name))
5247 ia64_tune = processor_alias_table[i].processor;
5251 error ("bad value %<%s%> for -mtune= switch", arg);
5260 /* Implement OVERRIDE_OPTIONS. */
5263 ia64_override_options (void)
5265 if (TARGET_AUTO_PIC)
5266 target_flags |= MASK_CONST_GP;
5268 if (TARGET_INLINE_SQRT == INL_MIN_LAT)
5270 warning (0, "not yet implemented: latency-optimized inline square root");
5271 TARGET_INLINE_SQRT = INL_MAX_THR;
5274 ia64_flag_schedule_insns2 = flag_schedule_insns_after_reload;
5275 flag_schedule_insns_after_reload = 0;
5278 && ! sel_sched_switch_set)
5280 flag_selective_scheduling2 = 1;
5281 flag_sel_sched_pipelining = 1;
5283 if (mflag_sched_control_spec == 2)
5285 /* Control speculation is on by default for the selective scheduler,
5286 but not for the Haifa scheduler. */
5287 mflag_sched_control_spec = flag_selective_scheduling2 ? 1 : 0;
5289 if (flag_sel_sched_pipelining && flag_auto_inc_dec)
5291 /* FIXME: remove this when we'd implement breaking autoinsns as
5292 a transformation. */
5293 flag_auto_inc_dec = 0;
5296 ia64_section_threshold = g_switch_set ? g_switch_value : IA64_DEFAULT_GVALUE;
5298 init_machine_status = ia64_init_machine_status;
5300 if (align_functions <= 0)
5301 align_functions = 64;
5302 if (align_loops <= 0)
5306 /* Initialize the record of emitted frame related registers. */
5308 void ia64_init_expanders (void)
5310 memset (&emitted_frame_related_regs, 0, sizeof (emitted_frame_related_regs));
5313 static struct machine_function *
5314 ia64_init_machine_status (void)
5316 return GGC_CNEW (struct machine_function);
5319 static enum attr_itanium_class ia64_safe_itanium_class (rtx);
5320 static enum attr_type ia64_safe_type (rtx);
5322 static enum attr_itanium_class
5323 ia64_safe_itanium_class (rtx insn)
5325 if (recog_memoized (insn) >= 0)
5326 return get_attr_itanium_class (insn);
5328 return ITANIUM_CLASS_UNKNOWN;
5331 static enum attr_type
5332 ia64_safe_type (rtx insn)
5334 if (recog_memoized (insn) >= 0)
5335 return get_attr_type (insn);
5337 return TYPE_UNKNOWN;
5340 /* The following collection of routines emit instruction group stop bits as
5341 necessary to avoid dependencies. */
5343 /* Need to track some additional registers as far as serialization is
5344 concerned so we can properly handle br.call and br.ret. We could
5345 make these registers visible to gcc, but since these registers are
5346 never explicitly used in gcc generated code, it seems wasteful to
5347 do so (plus it would make the call and return patterns needlessly
5349 #define REG_RP (BR_REG (0))
5350 #define REG_AR_CFM (FIRST_PSEUDO_REGISTER + 1)
5351 /* This is used for volatile asms which may require a stop bit immediately
5352 before and after them. */
5353 #define REG_VOLATILE (FIRST_PSEUDO_REGISTER + 2)
5354 #define AR_UNAT_BIT_0 (FIRST_PSEUDO_REGISTER + 3)
5355 #define NUM_REGS (AR_UNAT_BIT_0 + 64)
5357 /* For each register, we keep track of how it has been written in the
5358 current instruction group.
5360 If a register is written unconditionally (no qualifying predicate),
5361 WRITE_COUNT is set to 2 and FIRST_PRED is ignored.
5363 If a register is written if its qualifying predicate P is true, we
5364 set WRITE_COUNT to 1 and FIRST_PRED to P. Later on, the same register
5365 may be written again by the complement of P (P^1) and when this happens,
5366 WRITE_COUNT gets set to 2.
5368 The result of this is that whenever an insn attempts to write a register
5369 whose WRITE_COUNT is two, we need to issue an insn group barrier first.
5371 If a predicate register is written by a floating-point insn, we set
5372 WRITTEN_BY_FP to true.
5374 If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND
5375 to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true. */
5377 #if GCC_VERSION >= 4000
5378 #define RWS_FIELD_TYPE __extension__ unsigned short
5380 #define RWS_FIELD_TYPE unsigned int
5382 struct reg_write_state
5384 RWS_FIELD_TYPE write_count : 2;
5385 RWS_FIELD_TYPE first_pred : 10;
5386 RWS_FIELD_TYPE written_by_fp : 1;
5387 RWS_FIELD_TYPE written_by_and : 1;
5388 RWS_FIELD_TYPE written_by_or : 1;
5391 /* Cumulative info for the current instruction group. */
5392 struct reg_write_state rws_sum[NUM_REGS];
5393 #ifdef ENABLE_CHECKING
5394 /* Bitmap whether a register has been written in the current insn. */
5395 HARD_REG_ELT_TYPE rws_insn[(NUM_REGS + HOST_BITS_PER_WIDEST_FAST_INT - 1)
5396 / HOST_BITS_PER_WIDEST_FAST_INT];
5399 rws_insn_set (int regno)
5401 gcc_assert (!TEST_HARD_REG_BIT (rws_insn, regno));
5402 SET_HARD_REG_BIT (rws_insn, regno);
5406 rws_insn_test (int regno)
5408 return TEST_HARD_REG_BIT (rws_insn, regno);
5411 /* When not checking, track just REG_AR_CFM and REG_VOLATILE. */
5412 unsigned char rws_insn[2];
5415 rws_insn_set (int regno)
5417 if (regno == REG_AR_CFM)
5419 else if (regno == REG_VOLATILE)
5424 rws_insn_test (int regno)
5426 if (regno == REG_AR_CFM)
5428 if (regno == REG_VOLATILE)
5434 /* Indicates whether this is the first instruction after a stop bit,
5435 in which case we don't need another stop bit. Without this,
5436 ia64_variable_issue will die when scheduling an alloc. */
5437 static int first_instruction;
5439 /* Misc flags needed to compute RAW/WAW dependencies while we are traversing
5440 RTL for one instruction. */
5443 unsigned int is_write : 1; /* Is register being written? */
5444 unsigned int is_fp : 1; /* Is register used as part of an fp op? */
5445 unsigned int is_branch : 1; /* Is register used as part of a branch? */
5446 unsigned int is_and : 1; /* Is register used as part of and.orcm? */
5447 unsigned int is_or : 1; /* Is register used as part of or.andcm? */
5448 unsigned int is_sibcall : 1; /* Is this a sibling or normal call? */
5451 static void rws_update (int, struct reg_flags, int);
5452 static int rws_access_regno (int, struct reg_flags, int);
5453 static int rws_access_reg (rtx, struct reg_flags, int);
5454 static void update_set_flags (rtx, struct reg_flags *);
5455 static int set_src_needs_barrier (rtx, struct reg_flags, int);
5456 static int rtx_needs_barrier (rtx, struct reg_flags, int);
5457 static void init_insn_group_barriers (void);
5458 static int group_barrier_needed (rtx);
5459 static int safe_group_barrier_needed (rtx);
5460 static int in_safe_group_barrier;
5462 /* Update *RWS for REGNO, which is being written by the current instruction,
5463 with predicate PRED, and associated register flags in FLAGS. */
5466 rws_update (int regno, struct reg_flags flags, int pred)
5469 rws_sum[regno].write_count++;
5471 rws_sum[regno].write_count = 2;
5472 rws_sum[regno].written_by_fp |= flags.is_fp;
5473 /* ??? Not tracking and/or across differing predicates. */
5474 rws_sum[regno].written_by_and = flags.is_and;
5475 rws_sum[regno].written_by_or = flags.is_or;
5476 rws_sum[regno].first_pred = pred;
5479 /* Handle an access to register REGNO of type FLAGS using predicate register
5480 PRED. Update rws_sum array. Return 1 if this access creates
5481 a dependency with an earlier instruction in the same group. */
5484 rws_access_regno (int regno, struct reg_flags flags, int pred)
5486 int need_barrier = 0;
5488 gcc_assert (regno < NUM_REGS);
5490 if (! PR_REGNO_P (regno))
5491 flags.is_and = flags.is_or = 0;
5497 rws_insn_set (regno);
5498 write_count = rws_sum[regno].write_count;
5500 switch (write_count)
5503 /* The register has not been written yet. */
5504 if (!in_safe_group_barrier)
5505 rws_update (regno, flags, pred);
5509 /* The register has been written via a predicate. If this is
5510 not a complementary predicate, then we need a barrier. */
5511 /* ??? This assumes that P and P+1 are always complementary
5512 predicates for P even. */
5513 if (flags.is_and && rws_sum[regno].written_by_and)
5515 else if (flags.is_or && rws_sum[regno].written_by_or)
5517 else if ((rws_sum[regno].first_pred ^ 1) != pred)
5519 if (!in_safe_group_barrier)
5520 rws_update (regno, flags, pred);
5524 /* The register has been unconditionally written already. We
5526 if (flags.is_and && rws_sum[regno].written_by_and)
5528 else if (flags.is_or && rws_sum[regno].written_by_or)
5532 if (!in_safe_group_barrier)
5534 rws_sum[regno].written_by_and = flags.is_and;
5535 rws_sum[regno].written_by_or = flags.is_or;
5545 if (flags.is_branch)
5547 /* Branches have several RAW exceptions that allow to avoid
5550 if (REGNO_REG_CLASS (regno) == BR_REGS || regno == AR_PFS_REGNUM)
5551 /* RAW dependencies on branch regs are permissible as long
5552 as the writer is a non-branch instruction. Since we
5553 never generate code that uses a branch register written
5554 by a branch instruction, handling this case is
5558 if (REGNO_REG_CLASS (regno) == PR_REGS
5559 && ! rws_sum[regno].written_by_fp)
5560 /* The predicates of a branch are available within the
5561 same insn group as long as the predicate was written by
5562 something other than a floating-point instruction. */
5566 if (flags.is_and && rws_sum[regno].written_by_and)
5568 if (flags.is_or && rws_sum[regno].written_by_or)
5571 switch (rws_sum[regno].write_count)
5574 /* The register has not been written yet. */
5578 /* The register has been written via a predicate. If this is
5579 not a complementary predicate, then we need a barrier. */
5580 /* ??? This assumes that P and P+1 are always complementary
5581 predicates for P even. */
5582 if ((rws_sum[regno].first_pred ^ 1) != pred)
5587 /* The register has been unconditionally written already. We
5597 return need_barrier;
5601 rws_access_reg (rtx reg, struct reg_flags flags, int pred)
5603 int regno = REGNO (reg);
5604 int n = HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg));
5607 return rws_access_regno (regno, flags, pred);
5610 int need_barrier = 0;
5612 need_barrier |= rws_access_regno (regno + n, flags, pred);
5613 return need_barrier;
5617 /* Examine X, which is a SET rtx, and update the flags, the predicate, and
5618 the condition, stored in *PFLAGS, *PPRED and *PCOND. */
5621 update_set_flags (rtx x, struct reg_flags *pflags)
5623 rtx src = SET_SRC (x);
5625 switch (GET_CODE (src))
5631 /* There are four cases here:
5632 (1) The destination is (pc), in which case this is a branch,
5633 nothing here applies.
5634 (2) The destination is ar.lc, in which case this is a
5635 doloop_end_internal,
5636 (3) The destination is an fp register, in which case this is
5637 an fselect instruction.
5638 (4) The condition has (unspec [(reg)] UNSPEC_LDC), in which case
5639 this is a check load.
5640 In all cases, nothing we do in this function applies. */
5644 if (COMPARISON_P (src)
5645 && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (src, 0))))
5646 /* Set pflags->is_fp to 1 so that we know we're dealing
5647 with a floating point comparison when processing the
5648 destination of the SET. */
5651 /* Discover if this is a parallel comparison. We only handle
5652 and.orcm and or.andcm at present, since we must retain a
5653 strict inverse on the predicate pair. */
5654 else if (GET_CODE (src) == AND)
5656 else if (GET_CODE (src) == IOR)
5663 /* Subroutine of rtx_needs_barrier; this function determines whether the
5664 source of a given SET rtx found in X needs a barrier. FLAGS and PRED
5665 are as in rtx_needs_barrier. COND is an rtx that holds the condition
5669 set_src_needs_barrier (rtx x, struct reg_flags flags, int pred)
5671 int need_barrier = 0;
5673 rtx src = SET_SRC (x);
5675 if (GET_CODE (src) == CALL)
5676 /* We don't need to worry about the result registers that
5677 get written by subroutine call. */
5678 return rtx_needs_barrier (src, flags, pred);
5679 else if (SET_DEST (x) == pc_rtx)
5681 /* X is a conditional branch. */
5682 /* ??? This seems redundant, as the caller sets this bit for
5684 if (!ia64_spec_check_src_p (src))
5685 flags.is_branch = 1;
5686 return rtx_needs_barrier (src, flags, pred);
5689 if (ia64_spec_check_src_p (src))
5690 /* Avoid checking one register twice (in condition
5691 and in 'then' section) for ldc pattern. */
5693 gcc_assert (REG_P (XEXP (src, 2)));
5694 need_barrier = rtx_needs_barrier (XEXP (src, 2), flags, pred);
5696 /* We process MEM below. */
5697 src = XEXP (src, 1);
5700 need_barrier |= rtx_needs_barrier (src, flags, pred);
5703 if (GET_CODE (dst) == ZERO_EXTRACT)
5705 need_barrier |= rtx_needs_barrier (XEXP (dst, 1), flags, pred);
5706 need_barrier |= rtx_needs_barrier (XEXP (dst, 2), flags, pred);
5708 return need_barrier;
5711 /* Handle an access to rtx X of type FLAGS using predicate register
5712 PRED. Return 1 if this access creates a dependency with an earlier
5713 instruction in the same group. */
5716 rtx_needs_barrier (rtx x, struct reg_flags flags, int pred)
5719 int is_complemented = 0;
5720 int need_barrier = 0;
5721 const char *format_ptr;
5722 struct reg_flags new_flags;
5730 switch (GET_CODE (x))
5733 update_set_flags (x, &new_flags);
5734 need_barrier = set_src_needs_barrier (x, new_flags, pred);
5735 if (GET_CODE (SET_SRC (x)) != CALL)
5737 new_flags.is_write = 1;
5738 need_barrier |= rtx_needs_barrier (SET_DEST (x), new_flags, pred);
5743 new_flags.is_write = 0;
5744 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
5746 /* Avoid multiple register writes, in case this is a pattern with
5747 multiple CALL rtx. This avoids a failure in rws_access_reg. */
5748 if (! flags.is_sibcall && ! rws_insn_test (REG_AR_CFM))
5750 new_flags.is_write = 1;
5751 need_barrier |= rws_access_regno (REG_RP, new_flags, pred);
5752 need_barrier |= rws_access_regno (AR_PFS_REGNUM, new_flags, pred);
5753 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
5758 /* X is a predicated instruction. */
5760 cond = COND_EXEC_TEST (x);
5762 need_barrier = rtx_needs_barrier (cond, flags, 0);
5764 if (GET_CODE (cond) == EQ)
5765 is_complemented = 1;
5766 cond = XEXP (cond, 0);
5767 gcc_assert (GET_CODE (cond) == REG
5768 && REGNO_REG_CLASS (REGNO (cond)) == PR_REGS);
5769 pred = REGNO (cond);
5770 if (is_complemented)
5773 need_barrier |= rtx_needs_barrier (COND_EXEC_CODE (x), flags, pred);
5774 return need_barrier;
5778 /* Clobber & use are for earlier compiler-phases only. */
5783 /* We always emit stop bits for traditional asms. We emit stop bits
5784 for volatile extended asms if TARGET_VOL_ASM_STOP is true. */
5785 if (GET_CODE (x) != ASM_OPERANDS
5786 || (MEM_VOLATILE_P (x) && TARGET_VOL_ASM_STOP))
5788 /* Avoid writing the register multiple times if we have multiple
5789 asm outputs. This avoids a failure in rws_access_reg. */
5790 if (! rws_insn_test (REG_VOLATILE))
5792 new_flags.is_write = 1;
5793 rws_access_regno (REG_VOLATILE, new_flags, pred);
5798 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
5799 We cannot just fall through here since then we would be confused
5800 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
5801 traditional asms unlike their normal usage. */
5803 for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; --i)
5804 if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x, i), flags, pred))
5809 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
5811 rtx pat = XVECEXP (x, 0, i);
5812 switch (GET_CODE (pat))
5815 update_set_flags (pat, &new_flags);
5816 need_barrier |= set_src_needs_barrier (pat, new_flags, pred);
5822 need_barrier |= rtx_needs_barrier (pat, flags, pred);
5833 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
5835 rtx pat = XVECEXP (x, 0, i);
5836 if (GET_CODE (pat) == SET)
5838 if (GET_CODE (SET_SRC (pat)) != CALL)
5840 new_flags.is_write = 1;
5841 need_barrier |= rtx_needs_barrier (SET_DEST (pat), new_flags,
5845 else if (GET_CODE (pat) == CLOBBER || GET_CODE (pat) == RETURN)
5846 need_barrier |= rtx_needs_barrier (pat, flags, pred);
5851 need_barrier |= rtx_needs_barrier (SUBREG_REG (x), flags, pred);
5854 if (REGNO (x) == AR_UNAT_REGNUM)
5856 for (i = 0; i < 64; ++i)
5857 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + i, flags, pred);
5860 need_barrier = rws_access_reg (x, flags, pred);
5864 /* Find the regs used in memory address computation. */
5865 new_flags.is_write = 0;
5866 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
5869 case CONST_INT: case CONST_DOUBLE: case CONST_VECTOR:
5870 case SYMBOL_REF: case LABEL_REF: case CONST:
5873 /* Operators with side-effects. */
5874 case POST_INC: case POST_DEC:
5875 gcc_assert (GET_CODE (XEXP (x, 0)) == REG);
5877 new_flags.is_write = 0;
5878 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
5879 new_flags.is_write = 1;
5880 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
5884 gcc_assert (GET_CODE (XEXP (x, 0)) == REG);
5886 new_flags.is_write = 0;
5887 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
5888 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
5889 new_flags.is_write = 1;
5890 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
5893 /* Handle common unary and binary ops for efficiency. */
5894 case COMPARE: case PLUS: case MINUS: case MULT: case DIV:
5895 case MOD: case UDIV: case UMOD: case AND: case IOR:
5896 case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT:
5897 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
5898 case NE: case EQ: case GE: case GT: case LE:
5899 case LT: case GEU: case GTU: case LEU: case LTU:
5900 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
5901 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
5904 case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND:
5905 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT:
5906 case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS:
5907 case SQRT: case FFS: case POPCOUNT:
5908 need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred);
5912 /* VEC_SELECT's second argument is a PARALLEL with integers that
5913 describe the elements selected. On ia64, those integers are
5914 always constants. Avoid walking the PARALLEL so that we don't
5915 get confused with "normal" parallels and then die. */
5916 need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred);
5920 switch (XINT (x, 1))
5922 case UNSPEC_LTOFF_DTPMOD:
5923 case UNSPEC_LTOFF_DTPREL:
5925 case UNSPEC_LTOFF_TPREL:
5927 case UNSPEC_PRED_REL_MUTEX:
5928 case UNSPEC_PIC_CALL:
5930 case UNSPEC_FETCHADD_ACQ:
5931 case UNSPEC_BSP_VALUE:
5932 case UNSPEC_FLUSHRS:
5933 case UNSPEC_BUNDLE_SELECTOR:
5936 case UNSPEC_GR_SPILL:
5937 case UNSPEC_GR_RESTORE:
5939 HOST_WIDE_INT offset = INTVAL (XVECEXP (x, 0, 1));
5940 HOST_WIDE_INT bit = (offset >> 3) & 63;
5942 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
5943 new_flags.is_write = (XINT (x, 1) == UNSPEC_GR_SPILL);
5944 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + bit,
5949 case UNSPEC_FR_SPILL:
5950 case UNSPEC_FR_RESTORE:
5951 case UNSPEC_GETF_EXP:
5952 case UNSPEC_SETF_EXP:
5954 case UNSPEC_FR_SQRT_RECIP_APPROX:
5955 case UNSPEC_FR_SQRT_RECIP_APPROX_RES:
5960 case UNSPEC_CHKACLR:
5962 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
5965 case UNSPEC_FR_RECIP_APPROX:
5967 case UNSPEC_COPYSIGN:
5968 case UNSPEC_FR_RECIP_APPROX_RES:
5969 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
5970 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
5973 case UNSPEC_CMPXCHG_ACQ:
5974 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
5975 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 2), flags, pred);
5983 case UNSPEC_VOLATILE:
5984 switch (XINT (x, 1))
5987 /* Alloc must always be the first instruction of a group.
5988 We force this by always returning true. */
5989 /* ??? We might get better scheduling if we explicitly check for
5990 input/local/output register dependencies, and modify the
5991 scheduler so that alloc is always reordered to the start of
5992 the current group. We could then eliminate all of the
5993 first_instruction code. */
5994 rws_access_regno (AR_PFS_REGNUM, flags, pred);
5996 new_flags.is_write = 1;
5997 rws_access_regno (REG_AR_CFM, new_flags, pred);
6000 case UNSPECV_SET_BSP:
6004 case UNSPECV_BLOCKAGE:
6005 case UNSPECV_INSN_GROUP_BARRIER:
6007 case UNSPECV_PSAC_ALL:
6008 case UNSPECV_PSAC_NORMAL:
6017 new_flags.is_write = 0;
6018 need_barrier = rws_access_regno (REG_RP, flags, pred);
6019 need_barrier |= rws_access_regno (AR_PFS_REGNUM, flags, pred);
6021 new_flags.is_write = 1;
6022 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
6023 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
6027 format_ptr = GET_RTX_FORMAT (GET_CODE (x));
6028 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6029 switch (format_ptr[i])
6031 case '0': /* unused field */
6032 case 'i': /* integer */
6033 case 'n': /* note */
6034 case 'w': /* wide integer */
6035 case 's': /* pointer to string */
6036 case 'S': /* optional pointer to string */
6040 if (rtx_needs_barrier (XEXP (x, i), flags, pred))
6045 for (j = XVECLEN (x, i) - 1; j >= 0; --j)
6046 if (rtx_needs_barrier (XVECEXP (x, i, j), flags, pred))
6055 return need_barrier;
6058 /* Clear out the state for group_barrier_needed at the start of a
6059 sequence of insns. */
6062 init_insn_group_barriers (void)
6064 memset (rws_sum, 0, sizeof (rws_sum));
6065 first_instruction = 1;
6068 /* Given the current state, determine whether a group barrier (a stop bit) is
6069 necessary before INSN. Return nonzero if so. This modifies the state to
6070 include the effects of INSN as a side-effect. */
6073 group_barrier_needed (rtx insn)
6076 int need_barrier = 0;
6077 struct reg_flags flags;
6079 memset (&flags, 0, sizeof (flags));
6080 switch (GET_CODE (insn))
6086 /* A barrier doesn't imply an instruction group boundary. */
6090 memset (rws_insn, 0, sizeof (rws_insn));
6094 flags.is_branch = 1;
6095 flags.is_sibcall = SIBLING_CALL_P (insn);
6096 memset (rws_insn, 0, sizeof (rws_insn));
6098 /* Don't bundle a call following another call. */
6099 if ((pat = prev_active_insn (insn))
6100 && GET_CODE (pat) == CALL_INSN)
6106 need_barrier = rtx_needs_barrier (PATTERN (insn), flags, 0);
6110 if (!ia64_spec_check_p (insn))
6111 flags.is_branch = 1;
6113 /* Don't bundle a jump following a call. */
6114 if ((pat = prev_active_insn (insn))
6115 && GET_CODE (pat) == CALL_INSN)
6123 if (GET_CODE (PATTERN (insn)) == USE
6124 || GET_CODE (PATTERN (insn)) == CLOBBER)
6125 /* Don't care about USE and CLOBBER "insns"---those are used to
6126 indicate to the optimizer that it shouldn't get rid of
6127 certain operations. */
6130 pat = PATTERN (insn);
6132 /* Ug. Hack hacks hacked elsewhere. */
6133 switch (recog_memoized (insn))
6135 /* We play dependency tricks with the epilogue in order
6136 to get proper schedules. Undo this for dv analysis. */
6137 case CODE_FOR_epilogue_deallocate_stack:
6138 case CODE_FOR_prologue_allocate_stack:
6139 pat = XVECEXP (pat, 0, 0);
6142 /* The pattern we use for br.cloop confuses the code above.
6143 The second element of the vector is representative. */
6144 case CODE_FOR_doloop_end_internal:
6145 pat = XVECEXP (pat, 0, 1);
6148 /* Doesn't generate code. */
6149 case CODE_FOR_pred_rel_mutex:
6150 case CODE_FOR_prologue_use:
6157 memset (rws_insn, 0, sizeof (rws_insn));
6158 need_barrier = rtx_needs_barrier (pat, flags, 0);
6160 /* Check to see if the previous instruction was a volatile
6163 need_barrier = rws_access_regno (REG_VOLATILE, flags, 0);
6171 if (first_instruction && INSN_P (insn)
6172 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
6173 && GET_CODE (PATTERN (insn)) != USE
6174 && GET_CODE (PATTERN (insn)) != CLOBBER)
6177 first_instruction = 0;
6180 return need_barrier;
6183 /* Like group_barrier_needed, but do not clobber the current state. */
6186 safe_group_barrier_needed (rtx insn)
6188 int saved_first_instruction;
6191 saved_first_instruction = first_instruction;
6192 in_safe_group_barrier = 1;
6194 t = group_barrier_needed (insn);
6196 first_instruction = saved_first_instruction;
6197 in_safe_group_barrier = 0;
6202 /* Scan the current function and insert stop bits as necessary to
6203 eliminate dependencies. This function assumes that a final
6204 instruction scheduling pass has been run which has already
6205 inserted most of the necessary stop bits. This function only
6206 inserts new ones at basic block boundaries, since these are
6207 invisible to the scheduler. */
6210 emit_insn_group_barriers (FILE *dump)
6214 int insns_since_last_label = 0;
6216 init_insn_group_barriers ();
6218 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6220 if (GET_CODE (insn) == CODE_LABEL)
6222 if (insns_since_last_label)
6224 insns_since_last_label = 0;
6226 else if (GET_CODE (insn) == NOTE
6227 && NOTE_KIND (insn) == NOTE_INSN_BASIC_BLOCK)
6229 if (insns_since_last_label)
6231 insns_since_last_label = 0;
6233 else if (GET_CODE (insn) == INSN
6234 && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
6235 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
6237 init_insn_group_barriers ();
6240 else if (INSN_P (insn))
6242 insns_since_last_label = 1;
6244 if (group_barrier_needed (insn))
6249 fprintf (dump, "Emitting stop before label %d\n",
6250 INSN_UID (last_label));
6251 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), last_label);
6254 init_insn_group_barriers ();
6262 /* Like emit_insn_group_barriers, but run if no final scheduling pass was run.
6263 This function has to emit all necessary group barriers. */
6266 emit_all_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED)
6270 init_insn_group_barriers ();
6272 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6274 if (GET_CODE (insn) == BARRIER)
6276 rtx last = prev_active_insn (insn);
6280 if (GET_CODE (last) == JUMP_INSN
6281 && GET_CODE (PATTERN (last)) == ADDR_DIFF_VEC)
6282 last = prev_active_insn (last);
6283 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
6284 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
6286 init_insn_group_barriers ();
6288 else if (INSN_P (insn))
6290 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
6291 init_insn_group_barriers ();
6292 else if (group_barrier_needed (insn))
6294 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn);
6295 init_insn_group_barriers ();
6296 group_barrier_needed (insn);
6304 /* Instruction scheduling support. */
6306 #define NR_BUNDLES 10
6308 /* A list of names of all available bundles. */
6310 static const char *bundle_name [NR_BUNDLES] =
6316 #if NR_BUNDLES == 10
6326 /* Nonzero if we should insert stop bits into the schedule. */
6328 int ia64_final_schedule = 0;
6330 /* Codes of the corresponding queried units: */
6332 static int _0mii_, _0mmi_, _0mfi_, _0mmf_;
6333 static int _0bbb_, _0mbb_, _0mib_, _0mmb_, _0mfb_, _0mlx_;
6335 static int _1mii_, _1mmi_, _1mfi_, _1mmf_;
6336 static int _1bbb_, _1mbb_, _1mib_, _1mmb_, _1mfb_, _1mlx_;
6338 static int pos_1, pos_2, pos_3, pos_4, pos_5, pos_6;
6340 /* The following variable value is an insn group barrier. */
6342 static rtx dfa_stop_insn;
6344 /* The following variable value is the last issued insn. */
6346 static rtx last_scheduled_insn;
6348 /* The following variable value is pointer to a DFA state used as
6349 temporary variable. */
6351 static state_t temp_dfa_state = NULL;
6353 /* The following variable value is DFA state after issuing the last
6356 static state_t prev_cycle_state = NULL;
6358 /* The following array element values are TRUE if the corresponding
6359 insn requires to add stop bits before it. */
6361 static char *stops_p = NULL;
6363 /* The following variable is used to set up the mentioned above array. */
6365 static int stop_before_p = 0;
6367 /* The following variable value is length of the arrays `clocks' and
6370 static int clocks_length;
6372 /* The following array element values are cycles on which the
6373 corresponding insn will be issued. The array is used only for
6378 /* The following array element values are numbers of cycles should be
6379 added to improve insn scheduling for MM_insns for Itanium1. */
6381 static int *add_cycles;
6383 /* The following variable value is number of data speculations in progress. */
6384 static int pending_data_specs = 0;
6386 /* Number of memory references on current and three future processor cycles. */
6387 static char mem_ops_in_group[4];
6389 /* Number of current processor cycle (from scheduler's point of view). */
6390 static int current_cycle;
6392 static rtx ia64_single_set (rtx);
6393 static void ia64_emit_insn_before (rtx, rtx);
6395 /* Map a bundle number to its pseudo-op. */
6398 get_bundle_name (int b)
6400 return bundle_name[b];
6404 /* Return the maximum number of instructions a cpu can issue. */
6407 ia64_issue_rate (void)
6412 /* Helper function - like single_set, but look inside COND_EXEC. */
6415 ia64_single_set (rtx insn)
6417 rtx x = PATTERN (insn), ret;
6418 if (GET_CODE (x) == COND_EXEC)
6419 x = COND_EXEC_CODE (x);
6420 if (GET_CODE (x) == SET)
6423 /* Special case here prologue_allocate_stack and epilogue_deallocate_stack.
6424 Although they are not classical single set, the second set is there just
6425 to protect it from moving past FP-relative stack accesses. */
6426 switch (recog_memoized (insn))
6428 case CODE_FOR_prologue_allocate_stack:
6429 case CODE_FOR_epilogue_deallocate_stack:
6430 ret = XVECEXP (x, 0, 0);
6434 ret = single_set_2 (insn, x);
6441 /* Adjust the cost of a scheduling dependency.
6442 Return the new cost of a dependency of type DEP_TYPE or INSN on DEP_INSN.
6443 COST is the current cost, DW is dependency weakness. */
6445 ia64_adjust_cost_2 (rtx insn, int dep_type1, rtx dep_insn, int cost, dw_t dw)
6447 enum reg_note dep_type = (enum reg_note) dep_type1;
6448 enum attr_itanium_class dep_class;
6449 enum attr_itanium_class insn_class;
6451 insn_class = ia64_safe_itanium_class (insn);
6452 dep_class = ia64_safe_itanium_class (dep_insn);
6454 /* Treat true memory dependencies separately. Ignore apparent true
6455 dependence between store and call (call has a MEM inside a SYMBOL_REF). */
6456 if (dep_type == REG_DEP_TRUE
6457 && (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF)
6458 && (insn_class == ITANIUM_CLASS_BR || insn_class == ITANIUM_CLASS_SCALL))
6461 if (dw == MIN_DEP_WEAK)
6462 /* Store and load are likely to alias, use higher cost to avoid stall. */
6463 return PARAM_VALUE (PARAM_SCHED_MEM_TRUE_DEP_COST);
6464 else if (dw > MIN_DEP_WEAK)
6466 /* Store and load are less likely to alias. */
6467 if (mflag_sched_fp_mem_deps_zero_cost && dep_class == ITANIUM_CLASS_STF)
6468 /* Assume there will be no cache conflict for floating-point data.
6469 For integer data, L1 conflict penalty is huge (17 cycles), so we
6470 never assume it will not cause a conflict. */
6476 if (dep_type != REG_DEP_OUTPUT)
6479 if (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF
6480 || insn_class == ITANIUM_CLASS_ST || insn_class == ITANIUM_CLASS_STF)
6486 /* Like emit_insn_before, but skip cycle_display notes.
6487 ??? When cycle display notes are implemented, update this. */
6490 ia64_emit_insn_before (rtx insn, rtx before)
6492 emit_insn_before (insn, before);
6495 /* The following function marks insns who produce addresses for load
6496 and store insns. Such insns will be placed into M slots because it
6497 decrease latency time for Itanium1 (see function
6498 `ia64_produce_address_p' and the DFA descriptions). */
6501 ia64_dependencies_evaluation_hook (rtx head, rtx tail)
6503 rtx insn, next, next_tail;
6505 /* Before reload, which_alternative is not set, which means that
6506 ia64_safe_itanium_class will produce wrong results for (at least)
6507 move instructions. */
6508 if (!reload_completed)
6511 next_tail = NEXT_INSN (tail);
6512 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
6515 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
6517 && ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IALU)
6519 sd_iterator_def sd_it;
6521 bool has_mem_op_consumer_p = false;
6523 FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep)
6525 enum attr_itanium_class c;
6527 if (DEP_TYPE (dep) != REG_DEP_TRUE)
6530 next = DEP_CON (dep);
6531 c = ia64_safe_itanium_class (next);
6532 if ((c == ITANIUM_CLASS_ST
6533 || c == ITANIUM_CLASS_STF)
6534 && ia64_st_address_bypass_p (insn, next))
6536 has_mem_op_consumer_p = true;
6539 else if ((c == ITANIUM_CLASS_LD
6540 || c == ITANIUM_CLASS_FLD
6541 || c == ITANIUM_CLASS_FLDP)
6542 && ia64_ld_address_bypass_p (insn, next))
6544 has_mem_op_consumer_p = true;
6549 insn->call = has_mem_op_consumer_p;
6553 /* We're beginning a new block. Initialize data structures as necessary. */
6556 ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED,
6557 int sched_verbose ATTRIBUTE_UNUSED,
6558 int max_ready ATTRIBUTE_UNUSED)
6560 #ifdef ENABLE_CHECKING
6563 if (!sel_sched_p () && reload_completed)
6564 for (insn = NEXT_INSN (current_sched_info->prev_head);
6565 insn != current_sched_info->next_tail;
6566 insn = NEXT_INSN (insn))
6567 gcc_assert (!SCHED_GROUP_P (insn));
6569 last_scheduled_insn = NULL_RTX;
6570 init_insn_group_barriers ();
6573 memset (mem_ops_in_group, 0, sizeof (mem_ops_in_group));
6576 /* We're beginning a scheduling pass. Check assertion. */
6579 ia64_sched_init_global (FILE *dump ATTRIBUTE_UNUSED,
6580 int sched_verbose ATTRIBUTE_UNUSED,
6581 int max_ready ATTRIBUTE_UNUSED)
6583 gcc_assert (pending_data_specs == 0);
6586 /* Scheduling pass is now finished. Free/reset static variable. */
6588 ia64_sched_finish_global (FILE *dump ATTRIBUTE_UNUSED,
6589 int sched_verbose ATTRIBUTE_UNUSED)
6591 gcc_assert (pending_data_specs == 0);
6594 /* Return TRUE if INSN is a load (either normal or speculative, but not a
6595 speculation check), FALSE otherwise. */
6597 is_load_p (rtx insn)
6599 enum attr_itanium_class insn_class = ia64_safe_itanium_class (insn);
6602 ((insn_class == ITANIUM_CLASS_LD || insn_class == ITANIUM_CLASS_FLD)
6603 && get_attr_check_load (insn) == CHECK_LOAD_NO);
6606 /* If INSN is a memory reference, memoize it in MEM_OPS_IN_GROUP global array
6607 (taking account for 3-cycle cache reference postponing for stores: Intel
6608 Itanium 2 Reference Manual for Software Development and Optimization,
6611 record_memory_reference (rtx insn)
6613 enum attr_itanium_class insn_class = ia64_safe_itanium_class (insn);
6615 switch (insn_class) {
6616 case ITANIUM_CLASS_FLD:
6617 case ITANIUM_CLASS_LD:
6618 mem_ops_in_group[current_cycle % 4]++;
6620 case ITANIUM_CLASS_STF:
6621 case ITANIUM_CLASS_ST:
6622 mem_ops_in_group[(current_cycle + 3) % 4]++;
6628 /* We are about to being issuing insns for this clock cycle.
6629 Override the default sort algorithm to better slot instructions. */
6632 ia64_dfa_sched_reorder (FILE *dump, int sched_verbose, rtx *ready,
6633 int *pn_ready, int clock_var,
6637 int n_ready = *pn_ready;
6638 rtx *e_ready = ready + n_ready;
6642 fprintf (dump, "// ia64_dfa_sched_reorder (type %d):\n", reorder_type);
6644 if (reorder_type == 0)
6646 /* First, move all USEs, CLOBBERs and other crud out of the way. */
6648 for (insnp = ready; insnp < e_ready; insnp++)
6649 if (insnp < e_ready)
6652 enum attr_type t = ia64_safe_type (insn);
6653 if (t == TYPE_UNKNOWN)
6655 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
6656 || asm_noperands (PATTERN (insn)) >= 0)
6658 rtx lowest = ready[n_asms];
6659 ready[n_asms] = insn;
6665 rtx highest = ready[n_ready - 1];
6666 ready[n_ready - 1] = insn;
6673 if (n_asms < n_ready)
6675 /* Some normal insns to process. Skip the asms. */
6679 else if (n_ready > 0)
6683 if (ia64_final_schedule)
6686 int nr_need_stop = 0;
6688 for (insnp = ready; insnp < e_ready; insnp++)
6689 if (safe_group_barrier_needed (*insnp))
6692 if (reorder_type == 1 && n_ready == nr_need_stop)
6694 if (reorder_type == 0)
6697 /* Move down everything that needs a stop bit, preserving
6699 while (insnp-- > ready + deleted)
6700 while (insnp >= ready + deleted)
6703 if (! safe_group_barrier_needed (insn))
6705 memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx));
6713 current_cycle = clock_var;
6714 if (reload_completed && mem_ops_in_group[clock_var % 4] >= ia64_max_memory_insns)
6719 /* Move down loads/stores, preserving relative order. */
6720 while (insnp-- > ready + moved)
6721 while (insnp >= ready + moved)
6724 if (! is_load_p (insn))
6726 memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx));
6737 /* We are about to being issuing insns for this clock cycle. Override
6738 the default sort algorithm to better slot instructions. */
6741 ia64_sched_reorder (FILE *dump, int sched_verbose, rtx *ready, int *pn_ready,
6744 return ia64_dfa_sched_reorder (dump, sched_verbose, ready,
6745 pn_ready, clock_var, 0);
6748 /* Like ia64_sched_reorder, but called after issuing each insn.
6749 Override the default sort algorithm to better slot instructions. */
6752 ia64_sched_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
6753 int sched_verbose ATTRIBUTE_UNUSED, rtx *ready,
6754 int *pn_ready, int clock_var)
6756 if (ia64_tune == PROCESSOR_ITANIUM && reload_completed && last_scheduled_insn)
6757 clocks [INSN_UID (last_scheduled_insn)] = clock_var;
6758 return ia64_dfa_sched_reorder (dump, sched_verbose, ready, pn_ready,
6762 /* We are about to issue INSN. Return the number of insns left on the
6763 ready queue that can be issued this cycle. */
6766 ia64_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
6767 int sched_verbose ATTRIBUTE_UNUSED,
6768 rtx insn ATTRIBUTE_UNUSED,
6769 int can_issue_more ATTRIBUTE_UNUSED)
6771 if (sched_deps_info->generate_spec_deps && !sel_sched_p ())
6772 /* Modulo scheduling does not extend h_i_d when emitting
6773 new instructions. Don't use h_i_d, if we don't have to. */
6775 if (DONE_SPEC (insn) & BEGIN_DATA)
6776 pending_data_specs++;
6777 if (CHECK_SPEC (insn) & BEGIN_DATA)
6778 pending_data_specs--;
6781 last_scheduled_insn = insn;
6782 memcpy (prev_cycle_state, curr_state, dfa_state_size);
6783 if (reload_completed)
6785 int needed = group_barrier_needed (insn);
6787 gcc_assert (!needed);
6788 if (GET_CODE (insn) == CALL_INSN)
6789 init_insn_group_barriers ();
6790 stops_p [INSN_UID (insn)] = stop_before_p;
6793 record_memory_reference (insn);
6798 /* We are choosing insn from the ready queue. Return nonzero if INSN
6802 ia64_first_cycle_multipass_dfa_lookahead_guard (rtx insn)
6804 gcc_assert (insn && INSN_P (insn));
6805 return ((!reload_completed
6806 || !safe_group_barrier_needed (insn))
6807 && ia64_first_cycle_multipass_dfa_lookahead_guard_spec (insn)
6808 && (!mflag_sched_mem_insns_hard_limit
6809 || !is_load_p (insn)
6810 || mem_ops_in_group[current_cycle % 4] < ia64_max_memory_insns));
6813 /* We are choosing insn from the ready queue. Return nonzero if INSN
6817 ia64_first_cycle_multipass_dfa_lookahead_guard_spec (const_rtx insn)
6819 gcc_assert (insn && INSN_P (insn));
6820 /* Size of ALAT is 32. As far as we perform conservative data speculation,
6821 we keep ALAT half-empty. */
6822 return (pending_data_specs < 16
6823 || !(TODO_SPEC (insn) & BEGIN_DATA));
6826 /* The following variable value is pseudo-insn used by the DFA insn
6827 scheduler to change the DFA state when the simulated clock is
6830 static rtx dfa_pre_cycle_insn;
6832 /* Returns 1 when a meaningful insn was scheduled between the last group
6833 barrier and LAST. */
6835 scheduled_good_insn (rtx last)
6837 if (last && recog_memoized (last) >= 0)
6841 last != NULL && !NOTE_INSN_BASIC_BLOCK_P (last)
6842 && !stops_p[INSN_UID (last)];
6843 last = PREV_INSN (last))
6844 /* We could hit a NOTE_INSN_DELETED here which is actually outside
6845 the ebb we're scheduling. */
6846 if (INSN_P (last) && recog_memoized (last) >= 0)
6852 /* We are about to being issuing INSN. Return nonzero if we cannot
6853 issue it on given cycle CLOCK and return zero if we should not sort
6854 the ready queue on the next clock start. */
6857 ia64_dfa_new_cycle (FILE *dump, int verbose, rtx insn, int last_clock,
6858 int clock, int *sort_p)
6860 int setup_clocks_p = FALSE;
6862 gcc_assert (insn && INSN_P (insn));
6863 /* When a group barrier is needed for insn, last_scheduled_insn
6865 gcc_assert (!(reload_completed && safe_group_barrier_needed (insn))
6866 || last_scheduled_insn);
6868 if ((reload_completed
6869 && (safe_group_barrier_needed (insn)
6870 || (mflag_sched_stop_bits_after_every_cycle
6871 && last_clock != clock
6872 && last_scheduled_insn
6873 && scheduled_good_insn (last_scheduled_insn))))
6874 || (last_scheduled_insn
6875 && (GET_CODE (last_scheduled_insn) == CALL_INSN
6876 || GET_CODE (PATTERN (last_scheduled_insn)) == ASM_INPUT
6877 || asm_noperands (PATTERN (last_scheduled_insn)) >= 0)))
6879 init_insn_group_barriers ();
6881 if (verbose && dump)
6882 fprintf (dump, "// Stop should be before %d%s\n", INSN_UID (insn),
6883 last_clock == clock ? " + cycle advance" : "");
6886 current_cycle = clock;
6887 mem_ops_in_group[current_cycle % 4] = 0;
6889 if (last_clock == clock)
6891 state_transition (curr_state, dfa_stop_insn);
6892 if (TARGET_EARLY_STOP_BITS)
6893 *sort_p = (last_scheduled_insn == NULL_RTX
6894 || GET_CODE (last_scheduled_insn) != CALL_INSN);
6899 else if (reload_completed)
6900 setup_clocks_p = TRUE;
6902 if (last_scheduled_insn)
6904 if (GET_CODE (PATTERN (last_scheduled_insn)) == ASM_INPUT
6905 || asm_noperands (PATTERN (last_scheduled_insn)) >= 0)
6906 state_reset (curr_state);
6909 memcpy (curr_state, prev_cycle_state, dfa_state_size);
6910 state_transition (curr_state, dfa_stop_insn);
6911 state_transition (curr_state, dfa_pre_cycle_insn);
6912 state_transition (curr_state, NULL);
6916 else if (reload_completed)
6917 setup_clocks_p = TRUE;
6919 if (setup_clocks_p && ia64_tune == PROCESSOR_ITANIUM
6920 && GET_CODE (PATTERN (insn)) != ASM_INPUT
6921 && asm_noperands (PATTERN (insn)) < 0)
6923 enum attr_itanium_class c = ia64_safe_itanium_class (insn);
6925 if (c != ITANIUM_CLASS_MMMUL && c != ITANIUM_CLASS_MMSHF)
6927 sd_iterator_def sd_it;
6931 FOR_EACH_DEP (insn, SD_LIST_BACK, sd_it, dep)
6932 if (DEP_TYPE (dep) == REG_DEP_TRUE)
6934 enum attr_itanium_class dep_class;
6935 rtx dep_insn = DEP_PRO (dep);
6937 dep_class = ia64_safe_itanium_class (dep_insn);
6938 if ((dep_class == ITANIUM_CLASS_MMMUL
6939 || dep_class == ITANIUM_CLASS_MMSHF)
6940 && last_clock - clocks [INSN_UID (dep_insn)] < 4
6942 || last_clock - clocks [INSN_UID (dep_insn)] < d))
6943 d = last_clock - clocks [INSN_UID (dep_insn)];
6946 add_cycles [INSN_UID (insn)] = 3 - d;
6953 /* Implement targetm.sched.h_i_d_extended hook.
6954 Extend internal data structures. */
6956 ia64_h_i_d_extended (void)
6958 if (stops_p != NULL)
6960 int new_clocks_length = get_max_uid () * 3 / 2;
6962 stops_p = (char *) xrecalloc (stops_p, new_clocks_length, clocks_length, 1);
6964 if (ia64_tune == PROCESSOR_ITANIUM)
6966 clocks = (int *) xrecalloc (clocks, new_clocks_length, clocks_length,
6968 add_cycles = (int *) xrecalloc (add_cycles, new_clocks_length,
6969 clocks_length, sizeof (int));
6972 clocks_length = new_clocks_length;
6977 /* This structure describes the data used by the backend to guide scheduling.
6978 When the current scheduling point is switched, this data should be saved
6979 and restored later, if the scheduler returns to this point. */
6980 struct _ia64_sched_context
6982 state_t prev_cycle_state;
6983 rtx last_scheduled_insn;
6984 struct reg_write_state rws_sum[NUM_REGS];
6985 struct reg_write_state rws_insn[NUM_REGS];
6986 int first_instruction;
6987 int pending_data_specs;
6989 char mem_ops_in_group[4];
6991 typedef struct _ia64_sched_context *ia64_sched_context_t;
6993 /* Allocates a scheduling context. */
6995 ia64_alloc_sched_context (void)
6997 return xmalloc (sizeof (struct _ia64_sched_context));
7000 /* Initializes the _SC context with clean data, if CLEAN_P, and from
7001 the global context otherwise. */
7003 ia64_init_sched_context (void *_sc, bool clean_p)
7005 ia64_sched_context_t sc = (ia64_sched_context_t) _sc;
7007 sc->prev_cycle_state = xmalloc (dfa_state_size);
7010 state_reset (sc->prev_cycle_state);
7011 sc->last_scheduled_insn = NULL_RTX;
7012 memset (sc->rws_sum, 0, sizeof (rws_sum));
7013 memset (sc->rws_insn, 0, sizeof (rws_insn));
7014 sc->first_instruction = 1;
7015 sc->pending_data_specs = 0;
7016 sc->current_cycle = 0;
7017 memset (sc->mem_ops_in_group, 0, sizeof (mem_ops_in_group));
7021 memcpy (sc->prev_cycle_state, prev_cycle_state, dfa_state_size);
7022 sc->last_scheduled_insn = last_scheduled_insn;
7023 memcpy (sc->rws_sum, rws_sum, sizeof (rws_sum));
7024 memcpy (sc->rws_insn, rws_insn, sizeof (rws_insn));
7025 sc->first_instruction = first_instruction;
7026 sc->pending_data_specs = pending_data_specs;
7027 sc->current_cycle = current_cycle;
7028 memcpy (sc->mem_ops_in_group, mem_ops_in_group, sizeof (mem_ops_in_group));
7032 /* Sets the global scheduling context to the one pointed to by _SC. */
7034 ia64_set_sched_context (void *_sc)
7036 ia64_sched_context_t sc = (ia64_sched_context_t) _sc;
7038 gcc_assert (sc != NULL);
7040 memcpy (prev_cycle_state, sc->prev_cycle_state, dfa_state_size);
7041 last_scheduled_insn = sc->last_scheduled_insn;
7042 memcpy (rws_sum, sc->rws_sum, sizeof (rws_sum));
7043 memcpy (rws_insn, sc->rws_insn, sizeof (rws_insn));
7044 first_instruction = sc->first_instruction;
7045 pending_data_specs = sc->pending_data_specs;
7046 current_cycle = sc->current_cycle;
7047 memcpy (mem_ops_in_group, sc->mem_ops_in_group, sizeof (mem_ops_in_group));
7050 /* Clears the data in the _SC scheduling context. */
7052 ia64_clear_sched_context (void *_sc)
7054 ia64_sched_context_t sc = (ia64_sched_context_t) _sc;
7056 free (sc->prev_cycle_state);
7057 sc->prev_cycle_state = NULL;
7060 /* Frees the _SC scheduling context. */
7062 ia64_free_sched_context (void *_sc)
7064 gcc_assert (_sc != NULL);
7069 typedef rtx (* gen_func_t) (rtx, rtx);
7071 /* Return a function that will generate a load of mode MODE_NO
7072 with speculation types TS. */
7074 get_spec_load_gen_function (ds_t ts, int mode_no)
7076 static gen_func_t gen_ld_[] = {
7086 gen_zero_extendqidi2,
7087 gen_zero_extendhidi2,
7088 gen_zero_extendsidi2,
7091 static gen_func_t gen_ld_a[] = {
7101 gen_zero_extendqidi2_advanced,
7102 gen_zero_extendhidi2_advanced,
7103 gen_zero_extendsidi2_advanced,
7105 static gen_func_t gen_ld_s[] = {
7106 gen_movbi_speculative,
7107 gen_movqi_speculative,
7108 gen_movhi_speculative,
7109 gen_movsi_speculative,
7110 gen_movdi_speculative,
7111 gen_movsf_speculative,
7112 gen_movdf_speculative,
7113 gen_movxf_speculative,
7114 gen_movti_speculative,
7115 gen_zero_extendqidi2_speculative,
7116 gen_zero_extendhidi2_speculative,
7117 gen_zero_extendsidi2_speculative,
7119 static gen_func_t gen_ld_sa[] = {
7120 gen_movbi_speculative_advanced,
7121 gen_movqi_speculative_advanced,
7122 gen_movhi_speculative_advanced,
7123 gen_movsi_speculative_advanced,
7124 gen_movdi_speculative_advanced,
7125 gen_movsf_speculative_advanced,
7126 gen_movdf_speculative_advanced,
7127 gen_movxf_speculative_advanced,
7128 gen_movti_speculative_advanced,
7129 gen_zero_extendqidi2_speculative_advanced,
7130 gen_zero_extendhidi2_speculative_advanced,
7131 gen_zero_extendsidi2_speculative_advanced,
7133 static gen_func_t gen_ld_s_a[] = {
7134 gen_movbi_speculative_a,
7135 gen_movqi_speculative_a,
7136 gen_movhi_speculative_a,
7137 gen_movsi_speculative_a,
7138 gen_movdi_speculative_a,
7139 gen_movsf_speculative_a,
7140 gen_movdf_speculative_a,
7141 gen_movxf_speculative_a,
7142 gen_movti_speculative_a,
7143 gen_zero_extendqidi2_speculative_a,
7144 gen_zero_extendhidi2_speculative_a,
7145 gen_zero_extendsidi2_speculative_a,
7150 if (ts & BEGIN_DATA)
7152 if (ts & BEGIN_CONTROL)
7157 else if (ts & BEGIN_CONTROL)
7159 if ((spec_info->flags & SEL_SCHED_SPEC_DONT_CHECK_CONTROL)
7160 || ia64_needs_block_p (ts))
7163 gen_ld = gen_ld_s_a;
7170 return gen_ld[mode_no];
7173 /* Constants that help mapping 'enum machine_mode' to int. */
7176 SPEC_MODE_INVALID = -1,
7177 SPEC_MODE_FIRST = 0,
7178 SPEC_MODE_FOR_EXTEND_FIRST = 1,
7179 SPEC_MODE_FOR_EXTEND_LAST = 3,
7185 /* Offset to reach ZERO_EXTEND patterns. */
7186 SPEC_GEN_EXTEND_OFFSET = SPEC_MODE_LAST - SPEC_MODE_FOR_EXTEND_FIRST + 1
7189 /* Return index of the MODE. */
7191 ia64_mode_to_int (enum machine_mode mode)
7195 case BImode: return 0; /* SPEC_MODE_FIRST */
7196 case QImode: return 1; /* SPEC_MODE_FOR_EXTEND_FIRST */
7197 case HImode: return 2;
7198 case SImode: return 3; /* SPEC_MODE_FOR_EXTEND_LAST */
7199 case DImode: return 4;
7200 case SFmode: return 5;
7201 case DFmode: return 6;
7202 case XFmode: return 7;
7204 /* ??? This mode needs testing. Bypasses for ldfp8 instruction are not
7205 mentioned in itanium[12].md. Predicate fp_register_operand also
7206 needs to be defined. Bottom line: better disable for now. */
7207 return SPEC_MODE_INVALID;
7208 default: return SPEC_MODE_INVALID;
7212 /* Provide information about speculation capabilities. */
7214 ia64_set_sched_flags (spec_info_t spec_info)
7216 unsigned int *flags = &(current_sched_info->flags);
7218 if (*flags & SCHED_RGN
7219 || *flags & SCHED_EBB
7220 || *flags & SEL_SCHED)
7224 if ((mflag_sched_br_data_spec && !reload_completed && optimize > 0)
7225 || (mflag_sched_ar_data_spec && reload_completed))
7230 && ((mflag_sched_br_in_data_spec && !reload_completed)
7231 || (mflag_sched_ar_in_data_spec && reload_completed)))
7235 if (mflag_sched_control_spec
7237 || reload_completed))
7239 mask |= BEGIN_CONTROL;
7241 if (!sel_sched_p () && mflag_sched_in_control_spec)
7242 mask |= BE_IN_CONTROL;
7245 spec_info->mask = mask;
7249 *flags |= USE_DEPS_LIST | DO_SPECULATION;
7251 if (mask & BE_IN_SPEC)
7254 spec_info->flags = 0;
7256 if ((mask & DATA_SPEC) && mflag_sched_prefer_non_data_spec_insns)
7257 spec_info->flags |= PREFER_NON_DATA_SPEC;
7259 if (mask & CONTROL_SPEC)
7261 if (mflag_sched_prefer_non_control_spec_insns)
7262 spec_info->flags |= PREFER_NON_CONTROL_SPEC;
7264 if (sel_sched_p () && mflag_sel_sched_dont_check_control_spec)
7265 spec_info->flags |= SEL_SCHED_SPEC_DONT_CHECK_CONTROL;
7268 if (sched_verbose >= 1)
7269 spec_info->dump = sched_dump;
7271 spec_info->dump = 0;
7273 if (mflag_sched_count_spec_in_critical_path)
7274 spec_info->flags |= COUNT_SPEC_IN_CRITICAL_PATH;
7278 spec_info->mask = 0;
7281 /* If INSN is an appropriate load return its mode.
7282 Return -1 otherwise. */
7284 get_mode_no_for_insn (rtx insn)
7286 rtx reg, mem, mode_rtx;
7290 extract_insn_cached (insn);
7292 /* We use WHICH_ALTERNATIVE only after reload. This will
7293 guarantee that reload won't touch a speculative insn. */
7295 if (recog_data.n_operands != 2)
7298 reg = recog_data.operand[0];
7299 mem = recog_data.operand[1];
7301 /* We should use MEM's mode since REG's mode in presence of
7302 ZERO_EXTEND will always be DImode. */
7303 if (get_attr_speculable1 (insn) == SPECULABLE1_YES)
7304 /* Process non-speculative ld. */
7306 if (!reload_completed)
7308 /* Do not speculate into regs like ar.lc. */
7309 if (!REG_P (reg) || AR_REGNO_P (REGNO (reg)))
7316 rtx mem_reg = XEXP (mem, 0);
7318 if (!REG_P (mem_reg))
7324 else if (get_attr_speculable2 (insn) == SPECULABLE2_YES)
7326 gcc_assert (REG_P (reg) && MEM_P (mem));
7332 else if (get_attr_data_speculative (insn) == DATA_SPECULATIVE_YES
7333 || get_attr_control_speculative (insn) == CONTROL_SPECULATIVE_YES
7334 || get_attr_check_load (insn) == CHECK_LOAD_YES)
7335 /* Process speculative ld or ld.c. */
7337 gcc_assert (REG_P (reg) && MEM_P (mem));
7342 enum attr_itanium_class attr_class = get_attr_itanium_class (insn);
7344 if (attr_class == ITANIUM_CLASS_CHK_A
7345 || attr_class == ITANIUM_CLASS_CHK_S_I
7346 || attr_class == ITANIUM_CLASS_CHK_S_F)
7353 mode_no = ia64_mode_to_int (GET_MODE (mode_rtx));
7355 if (mode_no == SPEC_MODE_INVALID)
7358 extend_p = (GET_MODE (reg) != GET_MODE (mode_rtx));
7362 if (!(SPEC_MODE_FOR_EXTEND_FIRST <= mode_no
7363 && mode_no <= SPEC_MODE_FOR_EXTEND_LAST))
7366 mode_no += SPEC_GEN_EXTEND_OFFSET;
7372 /* If X is an unspec part of a speculative load, return its code.
7373 Return -1 otherwise. */
7375 get_spec_unspec_code (const_rtx x)
7377 if (GET_CODE (x) != UNSPEC)
7399 /* Implement skip_rtx_p hook. */
7401 ia64_skip_rtx_p (const_rtx x)
7403 return get_spec_unspec_code (x) != -1;
7406 /* If INSN is a speculative load, return its UNSPEC code.
7407 Return -1 otherwise. */
7409 get_insn_spec_code (const_rtx insn)
7413 pat = PATTERN (insn);
7415 if (GET_CODE (pat) == COND_EXEC)
7416 pat = COND_EXEC_CODE (pat);
7418 if (GET_CODE (pat) != SET)
7421 reg = SET_DEST (pat);
7425 mem = SET_SRC (pat);
7426 if (GET_CODE (mem) == ZERO_EXTEND)
7427 mem = XEXP (mem, 0);
7429 return get_spec_unspec_code (mem);
7432 /* If INSN is a speculative load, return a ds with the speculation types.
7433 Otherwise [if INSN is a normal instruction] return 0. */
7435 ia64_get_insn_spec_ds (rtx insn)
7437 int code = get_insn_spec_code (insn);
7446 return BEGIN_CONTROL;
7449 return BEGIN_DATA | BEGIN_CONTROL;
7456 /* If INSN is a speculative load return a ds with the speculation types that
7458 Otherwise [if INSN is a normal instruction] return 0. */
7460 ia64_get_insn_checked_ds (rtx insn)
7462 int code = get_insn_spec_code (insn);
7467 return BEGIN_DATA | BEGIN_CONTROL;
7470 return BEGIN_CONTROL;
7474 return BEGIN_DATA | BEGIN_CONTROL;
7481 /* If GEN_P is true, calculate the index of needed speculation check and return
7482 speculative pattern for INSN with speculative mode TS, machine mode
7483 MODE_NO and with ZERO_EXTEND (if EXTEND_P is true).
7484 If GEN_P is false, just calculate the index of needed speculation check. */
7486 ia64_gen_spec_load (rtx insn, ds_t ts, int mode_no)
7489 gen_func_t gen_load;
7491 gen_load = get_spec_load_gen_function (ts, mode_no);
7493 new_pat = gen_load (copy_rtx (recog_data.operand[0]),
7494 copy_rtx (recog_data.operand[1]));
7496 pat = PATTERN (insn);
7497 if (GET_CODE (pat) == COND_EXEC)
7498 new_pat = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (COND_EXEC_TEST (pat)),
7505 insn_can_be_in_speculative_p (rtx insn ATTRIBUTE_UNUSED,
7506 ds_t ds ATTRIBUTE_UNUSED)
7511 /* Implement targetm.sched.speculate_insn hook.
7512 Check if the INSN can be TS speculative.
7513 If 'no' - return -1.
7514 If 'yes' - generate speculative pattern in the NEW_PAT and return 1.
7515 If current pattern of the INSN already provides TS speculation,
7518 ia64_speculate_insn (rtx insn, ds_t ts, rtx *new_pat)
7523 gcc_assert (!(ts & ~SPECULATIVE));
7525 if (ia64_spec_check_p (insn))
7528 if ((ts & BE_IN_SPEC)
7529 && !insn_can_be_in_speculative_p (insn, ts))
7532 mode_no = get_mode_no_for_insn (insn);
7534 if (mode_no != SPEC_MODE_INVALID)
7536 if (ia64_get_insn_spec_ds (insn) == ds_get_speculation_types (ts))
7541 *new_pat = ia64_gen_spec_load (insn, ts, mode_no);
7550 /* Return a function that will generate a check for speculation TS with mode
7552 If simple check is needed, pass true for SIMPLE_CHECK_P.
7553 If clearing check is needed, pass true for CLEARING_CHECK_P. */
7555 get_spec_check_gen_function (ds_t ts, int mode_no,
7556 bool simple_check_p, bool clearing_check_p)
7558 static gen_func_t gen_ld_c_clr[] = {
7568 gen_zero_extendqidi2_clr,
7569 gen_zero_extendhidi2_clr,
7570 gen_zero_extendsidi2_clr,
7572 static gen_func_t gen_ld_c_nc[] = {
7582 gen_zero_extendqidi2_nc,
7583 gen_zero_extendhidi2_nc,
7584 gen_zero_extendsidi2_nc,
7586 static gen_func_t gen_chk_a_clr[] = {
7587 gen_advanced_load_check_clr_bi,
7588 gen_advanced_load_check_clr_qi,
7589 gen_advanced_load_check_clr_hi,
7590 gen_advanced_load_check_clr_si,
7591 gen_advanced_load_check_clr_di,
7592 gen_advanced_load_check_clr_sf,
7593 gen_advanced_load_check_clr_df,
7594 gen_advanced_load_check_clr_xf,
7595 gen_advanced_load_check_clr_ti,
7596 gen_advanced_load_check_clr_di,
7597 gen_advanced_load_check_clr_di,
7598 gen_advanced_load_check_clr_di,
7600 static gen_func_t gen_chk_a_nc[] = {
7601 gen_advanced_load_check_nc_bi,
7602 gen_advanced_load_check_nc_qi,
7603 gen_advanced_load_check_nc_hi,
7604 gen_advanced_load_check_nc_si,
7605 gen_advanced_load_check_nc_di,
7606 gen_advanced_load_check_nc_sf,
7607 gen_advanced_load_check_nc_df,
7608 gen_advanced_load_check_nc_xf,
7609 gen_advanced_load_check_nc_ti,
7610 gen_advanced_load_check_nc_di,
7611 gen_advanced_load_check_nc_di,
7612 gen_advanced_load_check_nc_di,
7614 static gen_func_t gen_chk_s[] = {
7615 gen_speculation_check_bi,
7616 gen_speculation_check_qi,
7617 gen_speculation_check_hi,
7618 gen_speculation_check_si,
7619 gen_speculation_check_di,
7620 gen_speculation_check_sf,
7621 gen_speculation_check_df,
7622 gen_speculation_check_xf,
7623 gen_speculation_check_ti,
7624 gen_speculation_check_di,
7625 gen_speculation_check_di,
7626 gen_speculation_check_di,
7629 gen_func_t *gen_check;
7631 if (ts & BEGIN_DATA)
7633 /* We don't need recovery because even if this is ld.sa
7634 ALAT entry will be allocated only if NAT bit is set to zero.
7635 So it is enough to use ld.c here. */
7639 gcc_assert (mflag_sched_spec_ldc);
7641 if (clearing_check_p)
7642 gen_check = gen_ld_c_clr;
7644 gen_check = gen_ld_c_nc;
7648 if (clearing_check_p)
7649 gen_check = gen_chk_a_clr;
7651 gen_check = gen_chk_a_nc;
7654 else if (ts & BEGIN_CONTROL)
7657 /* We might want to use ld.sa -> ld.c instead of
7660 gcc_assert (!ia64_needs_block_p (ts));
7662 if (clearing_check_p)
7663 gen_check = gen_ld_c_clr;
7665 gen_check = gen_ld_c_nc;
7669 gen_check = gen_chk_s;
7675 gcc_assert (mode_no >= 0);
7676 return gen_check[mode_no];
7679 /* Return nonzero, if INSN needs branchy recovery check. */
7681 ia64_needs_block_p (ds_t ts)
7683 if (ts & BEGIN_DATA)
7684 return !mflag_sched_spec_ldc;
7686 gcc_assert ((ts & BEGIN_CONTROL) != 0);
7688 return !(mflag_sched_spec_control_ldc && mflag_sched_spec_ldc);
7691 /* Generate (or regenerate, if (MUTATE_P)) recovery check for INSN.
7692 If (LABEL != 0 || MUTATE_P), generate branchy recovery check.
7693 Otherwise, generate a simple check. */
7695 ia64_gen_spec_check (rtx insn, rtx label, ds_t ds)
7697 rtx op1, pat, check_pat;
7698 gen_func_t gen_check;
7701 mode_no = get_mode_no_for_insn (insn);
7702 gcc_assert (mode_no >= 0);
7708 gcc_assert (!ia64_needs_block_p (ds));
7709 op1 = copy_rtx (recog_data.operand[1]);
7712 gen_check = get_spec_check_gen_function (ds, mode_no, label == NULL_RTX,
7715 check_pat = gen_check (copy_rtx (recog_data.operand[0]), op1);
7717 pat = PATTERN (insn);
7718 if (GET_CODE (pat) == COND_EXEC)
7719 check_pat = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (COND_EXEC_TEST (pat)),
7725 /* Return nonzero, if X is branchy recovery check. */
7727 ia64_spec_check_p (rtx x)
7730 if (GET_CODE (x) == COND_EXEC)
7731 x = COND_EXEC_CODE (x);
7732 if (GET_CODE (x) == SET)
7733 return ia64_spec_check_src_p (SET_SRC (x));
7737 /* Return nonzero, if SRC belongs to recovery check. */
7739 ia64_spec_check_src_p (rtx src)
7741 if (GET_CODE (src) == IF_THEN_ELSE)
7746 if (GET_CODE (t) == NE)
7750 if (GET_CODE (t) == UNSPEC)
7756 if (code == UNSPEC_LDCCLR
7757 || code == UNSPEC_LDCNC
7758 || code == UNSPEC_CHKACLR
7759 || code == UNSPEC_CHKANC
7760 || code == UNSPEC_CHKS)
7762 gcc_assert (code != 0);
7772 /* The following page contains abstract data `bundle states' which are
7773 used for bundling insns (inserting nops and template generation). */
7775 /* The following describes state of insn bundling. */
7779 /* Unique bundle state number to identify them in the debugging
7782 rtx insn; /* corresponding insn, NULL for the 1st and the last state */
7783 /* number nops before and after the insn */
7784 short before_nops_num, after_nops_num;
7785 int insn_num; /* insn number (0 - for initial state, 1 - for the 1st
7787 int cost; /* cost of the state in cycles */
7788 int accumulated_insns_num; /* number of all previous insns including
7789 nops. L is considered as 2 insns */
7790 int branch_deviation; /* deviation of previous branches from 3rd slots */
7791 int middle_bundle_stops; /* number of stop bits in the middle of bundles */
7792 struct bundle_state *next; /* next state with the same insn_num */
7793 struct bundle_state *originator; /* originator (previous insn state) */
7794 /* All bundle states are in the following chain. */
7795 struct bundle_state *allocated_states_chain;
7796 /* The DFA State after issuing the insn and the nops. */
7800 /* The following is map insn number to the corresponding bundle state. */
7802 static struct bundle_state **index_to_bundle_states;
7804 /* The unique number of next bundle state. */
7806 static int bundle_states_num;
7808 /* All allocated bundle states are in the following chain. */
7810 static struct bundle_state *allocated_bundle_states_chain;
7812 /* All allocated but not used bundle states are in the following
7815 static struct bundle_state *free_bundle_state_chain;
7818 /* The following function returns a free bundle state. */
7820 static struct bundle_state *
7821 get_free_bundle_state (void)
7823 struct bundle_state *result;
7825 if (free_bundle_state_chain != NULL)
7827 result = free_bundle_state_chain;
7828 free_bundle_state_chain = result->next;
7832 result = XNEW (struct bundle_state);
7833 result->dfa_state = xmalloc (dfa_state_size);
7834 result->allocated_states_chain = allocated_bundle_states_chain;
7835 allocated_bundle_states_chain = result;
7837 result->unique_num = bundle_states_num++;
7842 /* The following function frees given bundle state. */
7845 free_bundle_state (struct bundle_state *state)
7847 state->next = free_bundle_state_chain;
7848 free_bundle_state_chain = state;
7851 /* Start work with abstract data `bundle states'. */
7854 initiate_bundle_states (void)
7856 bundle_states_num = 0;
7857 free_bundle_state_chain = NULL;
7858 allocated_bundle_states_chain = NULL;
7861 /* Finish work with abstract data `bundle states'. */
7864 finish_bundle_states (void)
7866 struct bundle_state *curr_state, *next_state;
7868 for (curr_state = allocated_bundle_states_chain;
7870 curr_state = next_state)
7872 next_state = curr_state->allocated_states_chain;
7873 free (curr_state->dfa_state);
7878 /* Hash table of the bundle states. The key is dfa_state and insn_num
7879 of the bundle states. */
7881 static htab_t bundle_state_table;
7883 /* The function returns hash of BUNDLE_STATE. */
7886 bundle_state_hash (const void *bundle_state)
7888 const struct bundle_state *const state
7889 = (const struct bundle_state *) bundle_state;
7892 for (result = i = 0; i < dfa_state_size; i++)
7893 result += (((unsigned char *) state->dfa_state) [i]
7894 << ((i % CHAR_BIT) * 3 + CHAR_BIT));
7895 return result + state->insn_num;
7898 /* The function returns nonzero if the bundle state keys are equal. */
7901 bundle_state_eq_p (const void *bundle_state_1, const void *bundle_state_2)
7903 const struct bundle_state *const state1
7904 = (const struct bundle_state *) bundle_state_1;
7905 const struct bundle_state *const state2
7906 = (const struct bundle_state *) bundle_state_2;
7908 return (state1->insn_num == state2->insn_num
7909 && memcmp (state1->dfa_state, state2->dfa_state,
7910 dfa_state_size) == 0);
7913 /* The function inserts the BUNDLE_STATE into the hash table. The
7914 function returns nonzero if the bundle has been inserted into the
7915 table. The table contains the best bundle state with given key. */
7918 insert_bundle_state (struct bundle_state *bundle_state)
7922 entry_ptr = htab_find_slot (bundle_state_table, bundle_state, 1);
7923 if (*entry_ptr == NULL)
7925 bundle_state->next = index_to_bundle_states [bundle_state->insn_num];
7926 index_to_bundle_states [bundle_state->insn_num] = bundle_state;
7927 *entry_ptr = (void *) bundle_state;
7930 else if (bundle_state->cost < ((struct bundle_state *) *entry_ptr)->cost
7931 || (bundle_state->cost == ((struct bundle_state *) *entry_ptr)->cost
7932 && (((struct bundle_state *)*entry_ptr)->accumulated_insns_num
7933 > bundle_state->accumulated_insns_num
7934 || (((struct bundle_state *)
7935 *entry_ptr)->accumulated_insns_num
7936 == bundle_state->accumulated_insns_num
7937 && (((struct bundle_state *)
7938 *entry_ptr)->branch_deviation
7939 > bundle_state->branch_deviation
7940 || (((struct bundle_state *)
7941 *entry_ptr)->branch_deviation
7942 == bundle_state->branch_deviation
7943 && ((struct bundle_state *)
7944 *entry_ptr)->middle_bundle_stops
7945 > bundle_state->middle_bundle_stops))))))
7948 struct bundle_state temp;
7950 temp = *(struct bundle_state *) *entry_ptr;
7951 *(struct bundle_state *) *entry_ptr = *bundle_state;
7952 ((struct bundle_state *) *entry_ptr)->next = temp.next;
7953 *bundle_state = temp;
7958 /* Start work with the hash table. */
7961 initiate_bundle_state_table (void)
7963 bundle_state_table = htab_create (50, bundle_state_hash, bundle_state_eq_p,
7967 /* Finish work with the hash table. */
7970 finish_bundle_state_table (void)
7972 htab_delete (bundle_state_table);
7977 /* The following variable is a insn `nop' used to check bundle states
7978 with different number of inserted nops. */
7980 static rtx ia64_nop;
7982 /* The following function tries to issue NOPS_NUM nops for the current
7983 state without advancing processor cycle. If it failed, the
7984 function returns FALSE and frees the current state. */
7987 try_issue_nops (struct bundle_state *curr_state, int nops_num)
7991 for (i = 0; i < nops_num; i++)
7992 if (state_transition (curr_state->dfa_state, ia64_nop) >= 0)
7994 free_bundle_state (curr_state);
8000 /* The following function tries to issue INSN for the current
8001 state without advancing processor cycle. If it failed, the
8002 function returns FALSE and frees the current state. */
8005 try_issue_insn (struct bundle_state *curr_state, rtx insn)
8007 if (insn && state_transition (curr_state->dfa_state, insn) >= 0)
8009 free_bundle_state (curr_state);
8015 /* The following function tries to issue BEFORE_NOPS_NUM nops and INSN
8016 starting with ORIGINATOR without advancing processor cycle. If
8017 TRY_BUNDLE_END_P is TRUE, the function also/only (if
8018 ONLY_BUNDLE_END_P is TRUE) tries to issue nops to fill all bundle.
8019 If it was successful, the function creates new bundle state and
8020 insert into the hash table and into `index_to_bundle_states'. */
8023 issue_nops_and_insn (struct bundle_state *originator, int before_nops_num,
8024 rtx insn, int try_bundle_end_p, int only_bundle_end_p)
8026 struct bundle_state *curr_state;
8028 curr_state = get_free_bundle_state ();
8029 memcpy (curr_state->dfa_state, originator->dfa_state, dfa_state_size);
8030 curr_state->insn = insn;
8031 curr_state->insn_num = originator->insn_num + 1;
8032 curr_state->cost = originator->cost;
8033 curr_state->originator = originator;
8034 curr_state->before_nops_num = before_nops_num;
8035 curr_state->after_nops_num = 0;
8036 curr_state->accumulated_insns_num
8037 = originator->accumulated_insns_num + before_nops_num;
8038 curr_state->branch_deviation = originator->branch_deviation;
8039 curr_state->middle_bundle_stops = originator->middle_bundle_stops;
8041 if (INSN_CODE (insn) == CODE_FOR_insn_group_barrier)
8043 gcc_assert (GET_MODE (insn) != TImode);
8044 if (!try_issue_nops (curr_state, before_nops_num))
8046 if (!try_issue_insn (curr_state, insn))
8048 memcpy (temp_dfa_state, curr_state->dfa_state, dfa_state_size);
8049 if (curr_state->accumulated_insns_num % 3 != 0)
8050 curr_state->middle_bundle_stops++;
8051 if (state_transition (temp_dfa_state, dfa_pre_cycle_insn) >= 0
8052 && curr_state->accumulated_insns_num % 3 != 0)
8054 free_bundle_state (curr_state);
8058 else if (GET_MODE (insn) != TImode)
8060 if (!try_issue_nops (curr_state, before_nops_num))
8062 if (!try_issue_insn (curr_state, insn))
8064 curr_state->accumulated_insns_num++;
8065 gcc_assert (GET_CODE (PATTERN (insn)) != ASM_INPUT
8066 && asm_noperands (PATTERN (insn)) < 0);
8068 if (ia64_safe_type (insn) == TYPE_L)
8069 curr_state->accumulated_insns_num++;
8073 /* If this is an insn that must be first in a group, then don't allow
8074 nops to be emitted before it. Currently, alloc is the only such
8075 supported instruction. */
8076 /* ??? The bundling automatons should handle this for us, but they do
8077 not yet have support for the first_insn attribute. */
8078 if (before_nops_num > 0 && get_attr_first_insn (insn) == FIRST_INSN_YES)
8080 free_bundle_state (curr_state);
8084 state_transition (curr_state->dfa_state, dfa_pre_cycle_insn);
8085 state_transition (curr_state->dfa_state, NULL);
8087 if (!try_issue_nops (curr_state, before_nops_num))
8089 if (!try_issue_insn (curr_state, insn))
8091 curr_state->accumulated_insns_num++;
8092 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
8093 || asm_noperands (PATTERN (insn)) >= 0)
8095 /* Finish bundle containing asm insn. */
8096 curr_state->after_nops_num
8097 = 3 - curr_state->accumulated_insns_num % 3;
8098 curr_state->accumulated_insns_num
8099 += 3 - curr_state->accumulated_insns_num % 3;
8101 else if (ia64_safe_type (insn) == TYPE_L)
8102 curr_state->accumulated_insns_num++;
8104 if (ia64_safe_type (insn) == TYPE_B)
8105 curr_state->branch_deviation
8106 += 2 - (curr_state->accumulated_insns_num - 1) % 3;
8107 if (try_bundle_end_p && curr_state->accumulated_insns_num % 3 != 0)
8109 if (!only_bundle_end_p && insert_bundle_state (curr_state))
8112 struct bundle_state *curr_state1;
8113 struct bundle_state *allocated_states_chain;
8115 curr_state1 = get_free_bundle_state ();
8116 dfa_state = curr_state1->dfa_state;
8117 allocated_states_chain = curr_state1->allocated_states_chain;
8118 *curr_state1 = *curr_state;
8119 curr_state1->dfa_state = dfa_state;
8120 curr_state1->allocated_states_chain = allocated_states_chain;
8121 memcpy (curr_state1->dfa_state, curr_state->dfa_state,
8123 curr_state = curr_state1;
8125 if (!try_issue_nops (curr_state,
8126 3 - curr_state->accumulated_insns_num % 3))
8128 curr_state->after_nops_num
8129 = 3 - curr_state->accumulated_insns_num % 3;
8130 curr_state->accumulated_insns_num
8131 += 3 - curr_state->accumulated_insns_num % 3;
8133 if (!insert_bundle_state (curr_state))
8134 free_bundle_state (curr_state);
8138 /* The following function returns position in the two window bundle
8142 get_max_pos (state_t state)
8144 if (cpu_unit_reservation_p (state, pos_6))
8146 else if (cpu_unit_reservation_p (state, pos_5))
8148 else if (cpu_unit_reservation_p (state, pos_4))
8150 else if (cpu_unit_reservation_p (state, pos_3))
8152 else if (cpu_unit_reservation_p (state, pos_2))
8154 else if (cpu_unit_reservation_p (state, pos_1))
8160 /* The function returns code of a possible template for given position
8161 and state. The function should be called only with 2 values of
8162 position equal to 3 or 6. We avoid generating F NOPs by putting
8163 templates containing F insns at the end of the template search
8164 because undocumented anomaly in McKinley derived cores which can
8165 cause stalls if an F-unit insn (including a NOP) is issued within a
8166 six-cycle window after reading certain application registers (such
8167 as ar.bsp). Furthermore, power-considerations also argue against
8168 the use of F-unit instructions unless they're really needed. */
8171 get_template (state_t state, int pos)
8176 if (cpu_unit_reservation_p (state, _0mmi_))
8178 else if (cpu_unit_reservation_p (state, _0mii_))
8180 else if (cpu_unit_reservation_p (state, _0mmb_))
8182 else if (cpu_unit_reservation_p (state, _0mib_))
8184 else if (cpu_unit_reservation_p (state, _0mbb_))
8186 else if (cpu_unit_reservation_p (state, _0bbb_))
8188 else if (cpu_unit_reservation_p (state, _0mmf_))
8190 else if (cpu_unit_reservation_p (state, _0mfi_))
8192 else if (cpu_unit_reservation_p (state, _0mfb_))
8194 else if (cpu_unit_reservation_p (state, _0mlx_))
8199 if (cpu_unit_reservation_p (state, _1mmi_))
8201 else if (cpu_unit_reservation_p (state, _1mii_))
8203 else if (cpu_unit_reservation_p (state, _1mmb_))
8205 else if (cpu_unit_reservation_p (state, _1mib_))
8207 else if (cpu_unit_reservation_p (state, _1mbb_))
8209 else if (cpu_unit_reservation_p (state, _1bbb_))
8211 else if (_1mmf_ >= 0 && cpu_unit_reservation_p (state, _1mmf_))
8213 else if (cpu_unit_reservation_p (state, _1mfi_))
8215 else if (cpu_unit_reservation_p (state, _1mfb_))
8217 else if (cpu_unit_reservation_p (state, _1mlx_))
8226 /* True when INSN is important for bundling. */
8228 important_for_bundling_p (rtx insn)
8230 return (INSN_P (insn)
8231 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
8232 && GET_CODE (PATTERN (insn)) != USE
8233 && GET_CODE (PATTERN (insn)) != CLOBBER);
8236 /* The following function returns an insn important for insn bundling
8237 followed by INSN and before TAIL. */
8240 get_next_important_insn (rtx insn, rtx tail)
8242 for (; insn && insn != tail; insn = NEXT_INSN (insn))
8243 if (important_for_bundling_p (insn))
8248 /* Add a bundle selector TEMPLATE0 before INSN. */
8251 ia64_add_bundle_selector_before (int template0, rtx insn)
8253 rtx b = gen_bundle_selector (GEN_INT (template0));
8255 ia64_emit_insn_before (b, insn);
8256 #if NR_BUNDLES == 10
8257 if ((template0 == 4 || template0 == 5)
8258 && (flag_unwind_tables || (flag_exceptions && !USING_SJLJ_EXCEPTIONS)))
8261 rtx note = NULL_RTX;
8263 /* In .mbb and .bbb bundles, check if CALL_INSN isn't in the
8264 first or second slot. If it is and has REG_EH_NOTE set, copy it
8265 to following nops, as br.call sets rp to the address of following
8266 bundle and therefore an EH region end must be on a bundle
8268 insn = PREV_INSN (insn);
8269 for (i = 0; i < 3; i++)
8272 insn = next_active_insn (insn);
8273 while (GET_CODE (insn) == INSN
8274 && get_attr_empty (insn) == EMPTY_YES);
8275 if (GET_CODE (insn) == CALL_INSN)
8276 note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8281 gcc_assert ((code = recog_memoized (insn)) == CODE_FOR_nop
8282 || code == CODE_FOR_nop_b);
8283 if (find_reg_note (insn, REG_EH_REGION, NULL_RTX))
8287 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0),
8295 /* The following function does insn bundling. Bundling means
8296 inserting templates and nop insns to fit insn groups into permitted
8297 templates. Instruction scheduling uses NDFA (non-deterministic
8298 finite automata) encoding informations about the templates and the
8299 inserted nops. Nondeterminism of the automata permits follows
8300 all possible insn sequences very fast.
8302 Unfortunately it is not possible to get information about inserting
8303 nop insns and used templates from the automata states. The
8304 automata only says that we can issue an insn possibly inserting
8305 some nops before it and using some template. Therefore insn
8306 bundling in this function is implemented by using DFA
8307 (deterministic finite automata). We follow all possible insn
8308 sequences by inserting 0-2 nops (that is what the NDFA describe for
8309 insn scheduling) before/after each insn being bundled. We know the
8310 start of simulated processor cycle from insn scheduling (insn
8311 starting a new cycle has TImode).
8313 Simple implementation of insn bundling would create enormous
8314 number of possible insn sequences satisfying information about new
8315 cycle ticks taken from the insn scheduling. To make the algorithm
8316 practical we use dynamic programming. Each decision (about
8317 inserting nops and implicitly about previous decisions) is described
8318 by structure bundle_state (see above). If we generate the same
8319 bundle state (key is automaton state after issuing the insns and
8320 nops for it), we reuse already generated one. As consequence we
8321 reject some decisions which cannot improve the solution and
8322 reduce memory for the algorithm.
8324 When we reach the end of EBB (extended basic block), we choose the
8325 best sequence and then, moving back in EBB, insert templates for
8326 the best alternative. The templates are taken from querying
8327 automaton state for each insn in chosen bundle states.
8329 So the algorithm makes two (forward and backward) passes through
8330 EBB. There is an additional forward pass through EBB for Itanium1
8331 processor. This pass inserts more nops to make dependency between
8332 a producer insn and MMMUL/MMSHF at least 4 cycles long. */
8335 bundling (FILE *dump, int verbose, rtx prev_head_insn, rtx tail)
8337 struct bundle_state *curr_state, *next_state, *best_state;
8338 rtx insn, next_insn;
8340 int i, bundle_end_p, only_bundle_end_p, asm_p;
8341 int pos = 0, max_pos, template0, template1;
8344 enum attr_type type;
8347 /* Count insns in the EBB. */
8348 for (insn = NEXT_INSN (prev_head_insn);
8349 insn && insn != tail;
8350 insn = NEXT_INSN (insn))
8356 dfa_clean_insn_cache ();
8357 initiate_bundle_state_table ();
8358 index_to_bundle_states = XNEWVEC (struct bundle_state *, insn_num + 2);
8359 /* First (forward) pass -- generation of bundle states. */
8360 curr_state = get_free_bundle_state ();
8361 curr_state->insn = NULL;
8362 curr_state->before_nops_num = 0;
8363 curr_state->after_nops_num = 0;
8364 curr_state->insn_num = 0;
8365 curr_state->cost = 0;
8366 curr_state->accumulated_insns_num = 0;
8367 curr_state->branch_deviation = 0;
8368 curr_state->middle_bundle_stops = 0;
8369 curr_state->next = NULL;
8370 curr_state->originator = NULL;
8371 state_reset (curr_state->dfa_state);
8372 index_to_bundle_states [0] = curr_state;
8374 /* Shift cycle mark if it is put on insn which could be ignored. */
8375 for (insn = NEXT_INSN (prev_head_insn);
8377 insn = NEXT_INSN (insn))
8379 && (ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IGNORE
8380 || GET_CODE (PATTERN (insn)) == USE
8381 || GET_CODE (PATTERN (insn)) == CLOBBER)
8382 && GET_MODE (insn) == TImode)
8384 PUT_MODE (insn, VOIDmode);
8385 for (next_insn = NEXT_INSN (insn);
8387 next_insn = NEXT_INSN (next_insn))
8388 if (INSN_P (next_insn)
8389 && ia64_safe_itanium_class (next_insn) != ITANIUM_CLASS_IGNORE
8390 && GET_CODE (PATTERN (next_insn)) != USE
8391 && GET_CODE (PATTERN (next_insn)) != CLOBBER
8392 && INSN_CODE (next_insn) != CODE_FOR_insn_group_barrier)
8394 PUT_MODE (next_insn, TImode);
8398 /* Forward pass: generation of bundle states. */
8399 for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail);
8403 gcc_assert (INSN_P (insn)
8404 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
8405 && GET_CODE (PATTERN (insn)) != USE
8406 && GET_CODE (PATTERN (insn)) != CLOBBER);
8407 type = ia64_safe_type (insn);
8408 next_insn = get_next_important_insn (NEXT_INSN (insn), tail);
8410 index_to_bundle_states [insn_num] = NULL;
8411 for (curr_state = index_to_bundle_states [insn_num - 1];
8413 curr_state = next_state)
8415 pos = curr_state->accumulated_insns_num % 3;
8416 next_state = curr_state->next;
8417 /* We must fill up the current bundle in order to start a
8418 subsequent asm insn in a new bundle. Asm insn is always
8419 placed in a separate bundle. */
8421 = (next_insn != NULL_RTX
8422 && INSN_CODE (insn) == CODE_FOR_insn_group_barrier
8423 && ia64_safe_type (next_insn) == TYPE_UNKNOWN);
8424 /* We may fill up the current bundle if it is the cycle end
8425 without a group barrier. */
8427 = (only_bundle_end_p || next_insn == NULL_RTX
8428 || (GET_MODE (next_insn) == TImode
8429 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier));
8430 if (type == TYPE_F || type == TYPE_B || type == TYPE_L
8432 /* We need to insert 2 nops for cases like M_MII. To
8433 guarantee issuing all insns on the same cycle for
8434 Itanium 1, we need to issue 2 nops after the first M
8435 insn (MnnMII where n is a nop insn). */
8436 || ((type == TYPE_M || type == TYPE_A)
8437 && ia64_tune == PROCESSOR_ITANIUM
8438 && !bundle_end_p && pos == 1))
8439 issue_nops_and_insn (curr_state, 2, insn, bundle_end_p,
8441 issue_nops_and_insn (curr_state, 1, insn, bundle_end_p,
8443 issue_nops_and_insn (curr_state, 0, insn, bundle_end_p,
8446 gcc_assert (index_to_bundle_states [insn_num]);
8447 for (curr_state = index_to_bundle_states [insn_num];
8449 curr_state = curr_state->next)
8450 if (verbose >= 2 && dump)
8452 /* This structure is taken from generated code of the
8453 pipeline hazard recognizer (see file insn-attrtab.c).
8454 Please don't forget to change the structure if a new
8455 automaton is added to .md file. */
8458 unsigned short one_automaton_state;
8459 unsigned short oneb_automaton_state;
8460 unsigned short two_automaton_state;
8461 unsigned short twob_automaton_state;
8466 "// Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, mid.stops %d state %d) for %d\n",
8467 curr_state->unique_num,
8468 (curr_state->originator == NULL
8469 ? -1 : curr_state->originator->unique_num),
8471 curr_state->before_nops_num, curr_state->after_nops_num,
8472 curr_state->accumulated_insns_num, curr_state->branch_deviation,
8473 curr_state->middle_bundle_stops,
8474 (ia64_tune == PROCESSOR_ITANIUM
8475 ? ((struct DFA_chip *) curr_state->dfa_state)->oneb_automaton_state
8476 : ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state),
8481 /* We should find a solution because the 2nd insn scheduling has
8483 gcc_assert (index_to_bundle_states [insn_num]);
8484 /* Find a state corresponding to the best insn sequence. */
8486 for (curr_state = index_to_bundle_states [insn_num];
8488 curr_state = curr_state->next)
8489 /* We are just looking at the states with fully filled up last
8490 bundle. The first we prefer insn sequences with minimal cost
8491 then with minimal inserted nops and finally with branch insns
8492 placed in the 3rd slots. */
8493 if (curr_state->accumulated_insns_num % 3 == 0
8494 && (best_state == NULL || best_state->cost > curr_state->cost
8495 || (best_state->cost == curr_state->cost
8496 && (curr_state->accumulated_insns_num
8497 < best_state->accumulated_insns_num
8498 || (curr_state->accumulated_insns_num
8499 == best_state->accumulated_insns_num
8500 && (curr_state->branch_deviation
8501 < best_state->branch_deviation
8502 || (curr_state->branch_deviation
8503 == best_state->branch_deviation
8504 && curr_state->middle_bundle_stops
8505 < best_state->middle_bundle_stops)))))))
8506 best_state = curr_state;
8507 /* Second (backward) pass: adding nops and templates. */
8508 gcc_assert (best_state);
8509 insn_num = best_state->before_nops_num;
8510 template0 = template1 = -1;
8511 for (curr_state = best_state;
8512 curr_state->originator != NULL;
8513 curr_state = curr_state->originator)
8515 insn = curr_state->insn;
8516 asm_p = (GET_CODE (PATTERN (insn)) == ASM_INPUT
8517 || asm_noperands (PATTERN (insn)) >= 0);
8519 if (verbose >= 2 && dump)
8523 unsigned short one_automaton_state;
8524 unsigned short oneb_automaton_state;
8525 unsigned short two_automaton_state;
8526 unsigned short twob_automaton_state;
8531 "// Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, mid.stops %d, state %d) for %d\n",
8532 curr_state->unique_num,
8533 (curr_state->originator == NULL
8534 ? -1 : curr_state->originator->unique_num),
8536 curr_state->before_nops_num, curr_state->after_nops_num,
8537 curr_state->accumulated_insns_num, curr_state->branch_deviation,
8538 curr_state->middle_bundle_stops,
8539 (ia64_tune == PROCESSOR_ITANIUM
8540 ? ((struct DFA_chip *) curr_state->dfa_state)->oneb_automaton_state
8541 : ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state),
8544 /* Find the position in the current bundle window. The window can
8545 contain at most two bundles. Two bundle window means that
8546 the processor will make two bundle rotation. */
8547 max_pos = get_max_pos (curr_state->dfa_state);
8549 /* The following (negative template number) means that the
8550 processor did one bundle rotation. */
8551 || (max_pos == 3 && template0 < 0))
8553 /* We are at the end of the window -- find template(s) for
8557 template0 = get_template (curr_state->dfa_state, 3);
8560 template1 = get_template (curr_state->dfa_state, 3);
8561 template0 = get_template (curr_state->dfa_state, 6);
8564 if (max_pos > 3 && template1 < 0)
8565 /* It may happen when we have the stop inside a bundle. */
8567 gcc_assert (pos <= 3);
8568 template1 = get_template (curr_state->dfa_state, 3);
8572 /* Emit nops after the current insn. */
8573 for (i = 0; i < curr_state->after_nops_num; i++)
8576 emit_insn_after (nop, insn);
8578 gcc_assert (pos >= 0);
8581 /* We are at the start of a bundle: emit the template
8582 (it should be defined). */
8583 gcc_assert (template0 >= 0);
8584 ia64_add_bundle_selector_before (template0, nop);
8585 /* If we have two bundle window, we make one bundle
8586 rotation. Otherwise template0 will be undefined
8587 (negative value). */
8588 template0 = template1;
8592 /* Move the position backward in the window. Group barrier has
8593 no slot. Asm insn takes all bundle. */
8594 if (INSN_CODE (insn) != CODE_FOR_insn_group_barrier
8595 && GET_CODE (PATTERN (insn)) != ASM_INPUT
8596 && asm_noperands (PATTERN (insn)) < 0)
8598 /* Long insn takes 2 slots. */
8599 if (ia64_safe_type (insn) == TYPE_L)
8601 gcc_assert (pos >= 0);
8603 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier
8604 && GET_CODE (PATTERN (insn)) != ASM_INPUT
8605 && asm_noperands (PATTERN (insn)) < 0)
8607 /* The current insn is at the bundle start: emit the
8609 gcc_assert (template0 >= 0);
8610 ia64_add_bundle_selector_before (template0, insn);
8611 b = PREV_INSN (insn);
8613 /* See comment above in analogous place for emitting nops
8615 template0 = template1;
8618 /* Emit nops after the current insn. */
8619 for (i = 0; i < curr_state->before_nops_num; i++)
8622 ia64_emit_insn_before (nop, insn);
8623 nop = PREV_INSN (insn);
8626 gcc_assert (pos >= 0);
8629 /* See comment above in analogous place for emitting nops
8631 gcc_assert (template0 >= 0);
8632 ia64_add_bundle_selector_before (template0, insn);
8633 b = PREV_INSN (insn);
8635 template0 = template1;
8640 if (ia64_tune == PROCESSOR_ITANIUM)
8641 /* Insert additional cycles for MM-insns (MMMUL and MMSHF).
8642 Itanium1 has a strange design, if the distance between an insn
8643 and dependent MM-insn is less 4 then we have a 6 additional
8644 cycles stall. So we make the distance equal to 4 cycles if it
8646 for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail);
8650 gcc_assert (INSN_P (insn)
8651 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
8652 && GET_CODE (PATTERN (insn)) != USE
8653 && GET_CODE (PATTERN (insn)) != CLOBBER);
8654 next_insn = get_next_important_insn (NEXT_INSN (insn), tail);
8655 if (INSN_UID (insn) < clocks_length && add_cycles [INSN_UID (insn)])
8656 /* We found a MM-insn which needs additional cycles. */
8662 /* Now we are searching for a template of the bundle in
8663 which the MM-insn is placed and the position of the
8664 insn in the bundle (0, 1, 2). Also we are searching
8665 for that there is a stop before the insn. */
8666 last = prev_active_insn (insn);
8667 pred_stop_p = recog_memoized (last) == CODE_FOR_insn_group_barrier;
8669 last = prev_active_insn (last);
8671 for (;; last = prev_active_insn (last))
8672 if (recog_memoized (last) == CODE_FOR_bundle_selector)
8674 template0 = XINT (XVECEXP (PATTERN (last), 0, 0), 0);
8676 /* The insn is in MLX bundle. Change the template
8677 onto MFI because we will add nops before the
8678 insn. It simplifies subsequent code a lot. */
8680 = gen_bundle_selector (const2_rtx); /* -> MFI */
8683 else if (recog_memoized (last) != CODE_FOR_insn_group_barrier
8684 && (ia64_safe_itanium_class (last)
8685 != ITANIUM_CLASS_IGNORE))
8687 /* Some check of correctness: the stop is not at the
8688 bundle start, there are no more 3 insns in the bundle,
8689 and the MM-insn is not at the start of bundle with
8691 gcc_assert ((!pred_stop_p || n)
8693 && (template0 != 9 || !n));
8694 /* Put nops after the insn in the bundle. */
8695 for (j = 3 - n; j > 0; j --)
8696 ia64_emit_insn_before (gen_nop (), insn);
8697 /* It takes into account that we will add more N nops
8698 before the insn lately -- please see code below. */
8699 add_cycles [INSN_UID (insn)]--;
8700 if (!pred_stop_p || add_cycles [INSN_UID (insn)])
8701 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
8704 add_cycles [INSN_UID (insn)]--;
8705 for (i = add_cycles [INSN_UID (insn)]; i > 0; i--)
8707 /* Insert "MII;" template. */
8708 ia64_emit_insn_before (gen_bundle_selector (const0_rtx),
8710 ia64_emit_insn_before (gen_nop (), insn);
8711 ia64_emit_insn_before (gen_nop (), insn);
8714 /* To decrease code size, we use "MI;I;"
8716 ia64_emit_insn_before
8717 (gen_insn_group_barrier (GEN_INT (3)), insn);
8720 ia64_emit_insn_before (gen_nop (), insn);
8721 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
8724 /* Put the MM-insn in the same slot of a bundle with the
8725 same template as the original one. */
8726 ia64_add_bundle_selector_before (template0, insn);
8727 /* To put the insn in the same slot, add necessary number
8729 for (j = n; j > 0; j --)
8730 ia64_emit_insn_before (gen_nop (), insn);
8731 /* Put the stop if the original bundle had it. */
8733 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
8738 #ifdef ENABLE_CHECKING
8740 /* Assert right calculation of middle_bundle_stops. */
8741 int num = best_state->middle_bundle_stops;
8742 bool start_bundle = true, end_bundle = false;
8744 for (insn = NEXT_INSN (prev_head_insn);
8745 insn && insn != tail;
8746 insn = NEXT_INSN (insn))
8750 if (recog_memoized (insn) == CODE_FOR_bundle_selector)
8751 start_bundle = true;
8756 for (next_insn = NEXT_INSN (insn);
8757 next_insn && next_insn != tail;
8758 next_insn = NEXT_INSN (next_insn))
8759 if (INSN_P (next_insn)
8760 && (ia64_safe_itanium_class (next_insn)
8761 != ITANIUM_CLASS_IGNORE
8762 || recog_memoized (next_insn)
8763 == CODE_FOR_bundle_selector)
8764 && GET_CODE (PATTERN (next_insn)) != USE
8765 && GET_CODE (PATTERN (next_insn)) != CLOBBER)
8768 end_bundle = next_insn == NULL_RTX
8769 || next_insn == tail
8770 || (INSN_P (next_insn)
8771 && recog_memoized (next_insn)
8772 == CODE_FOR_bundle_selector);
8773 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier
8774 && !start_bundle && !end_bundle
8776 && GET_CODE (PATTERN (next_insn)) != ASM_INPUT
8777 && asm_noperands (PATTERN (next_insn)) < 0)
8780 start_bundle = false;
8784 gcc_assert (num == 0);
8788 free (index_to_bundle_states);
8789 finish_bundle_state_table ();
8791 dfa_clean_insn_cache ();
8794 /* The following function is called at the end of scheduling BB or
8795 EBB. After reload, it inserts stop bits and does insn bundling. */
8798 ia64_sched_finish (FILE *dump, int sched_verbose)
8801 fprintf (dump, "// Finishing schedule.\n");
8802 if (!reload_completed)
8804 if (reload_completed)
8806 final_emit_insn_group_barriers (dump);
8807 bundling (dump, sched_verbose, current_sched_info->prev_head,
8808 current_sched_info->next_tail);
8809 if (sched_verbose && dump)
8810 fprintf (dump, "// finishing %d-%d\n",
8811 INSN_UID (NEXT_INSN (current_sched_info->prev_head)),
8812 INSN_UID (PREV_INSN (current_sched_info->next_tail)));
8818 /* The following function inserts stop bits in scheduled BB or EBB. */
8821 final_emit_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED)
8824 int need_barrier_p = 0;
8825 int seen_good_insn = 0;
8826 rtx prev_insn = NULL_RTX;
8828 init_insn_group_barriers ();
8830 for (insn = NEXT_INSN (current_sched_info->prev_head);
8831 insn != current_sched_info->next_tail;
8832 insn = NEXT_INSN (insn))
8834 if (GET_CODE (insn) == BARRIER)
8836 rtx last = prev_active_insn (insn);
8840 if (GET_CODE (last) == JUMP_INSN
8841 && GET_CODE (PATTERN (last)) == ADDR_DIFF_VEC)
8842 last = prev_active_insn (last);
8843 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
8844 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
8846 init_insn_group_barriers ();
8849 prev_insn = NULL_RTX;
8851 else if (INSN_P (insn))
8853 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
8855 init_insn_group_barriers ();
8858 prev_insn = NULL_RTX;
8860 else if (need_barrier_p || group_barrier_needed (insn)
8861 || (mflag_sched_stop_bits_after_every_cycle
8862 && GET_MODE (insn) == TImode
8865 if (TARGET_EARLY_STOP_BITS)
8870 last != current_sched_info->prev_head;
8871 last = PREV_INSN (last))
8872 if (INSN_P (last) && GET_MODE (last) == TImode
8873 && stops_p [INSN_UID (last)])
8875 if (last == current_sched_info->prev_head)
8877 last = prev_active_insn (last);
8879 && recog_memoized (last) != CODE_FOR_insn_group_barrier)
8880 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)),
8882 init_insn_group_barriers ();
8883 for (last = NEXT_INSN (last);
8885 last = NEXT_INSN (last))
8888 group_barrier_needed (last);
8889 if (recog_memoized (last) >= 0
8890 && important_for_bundling_p (last))
8896 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
8898 init_insn_group_barriers ();
8901 group_barrier_needed (insn);
8902 if (recog_memoized (insn) >= 0
8903 && important_for_bundling_p (insn))
8905 prev_insn = NULL_RTX;
8907 else if (recog_memoized (insn) >= 0
8908 && important_for_bundling_p (insn))
8913 need_barrier_p = (GET_CODE (insn) == CALL_INSN
8914 || GET_CODE (PATTERN (insn)) == ASM_INPUT
8915 || asm_noperands (PATTERN (insn)) >= 0);
8922 /* If the following function returns TRUE, we will use the DFA
8926 ia64_first_cycle_multipass_dfa_lookahead (void)
8928 return (reload_completed ? 6 : 4);
8931 /* The following function initiates variable `dfa_pre_cycle_insn'. */
8934 ia64_init_dfa_pre_cycle_insn (void)
8936 if (temp_dfa_state == NULL)
8938 dfa_state_size = state_size ();
8939 temp_dfa_state = xmalloc (dfa_state_size);
8940 prev_cycle_state = xmalloc (dfa_state_size);
8942 dfa_pre_cycle_insn = make_insn_raw (gen_pre_cycle ());
8943 PREV_INSN (dfa_pre_cycle_insn) = NEXT_INSN (dfa_pre_cycle_insn) = NULL_RTX;
8944 recog_memoized (dfa_pre_cycle_insn);
8945 dfa_stop_insn = make_insn_raw (gen_insn_group_barrier (GEN_INT (3)));
8946 PREV_INSN (dfa_stop_insn) = NEXT_INSN (dfa_stop_insn) = NULL_RTX;
8947 recog_memoized (dfa_stop_insn);
8950 /* The following function returns the pseudo insn DFA_PRE_CYCLE_INSN
8951 used by the DFA insn scheduler. */
8954 ia64_dfa_pre_cycle_insn (void)
8956 return dfa_pre_cycle_insn;
8959 /* The following function returns TRUE if PRODUCER (of type ilog or
8960 ld) produces address for CONSUMER (of type st or stf). */
8963 ia64_st_address_bypass_p (rtx producer, rtx consumer)
8967 gcc_assert (producer && consumer);
8968 dest = ia64_single_set (producer);
8970 reg = SET_DEST (dest);
8972 if (GET_CODE (reg) == SUBREG)
8973 reg = SUBREG_REG (reg);
8974 gcc_assert (GET_CODE (reg) == REG);
8976 dest = ia64_single_set (consumer);
8978 mem = SET_DEST (dest);
8979 gcc_assert (mem && GET_CODE (mem) == MEM);
8980 return reg_mentioned_p (reg, mem);
8983 /* The following function returns TRUE if PRODUCER (of type ilog or
8984 ld) produces address for CONSUMER (of type ld or fld). */
8987 ia64_ld_address_bypass_p (rtx producer, rtx consumer)
8989 rtx dest, src, reg, mem;
8991 gcc_assert (producer && consumer);
8992 dest = ia64_single_set (producer);
8994 reg = SET_DEST (dest);
8996 if (GET_CODE (reg) == SUBREG)
8997 reg = SUBREG_REG (reg);
8998 gcc_assert (GET_CODE (reg) == REG);
9000 src = ia64_single_set (consumer);
9002 mem = SET_SRC (src);
9005 if (GET_CODE (mem) == UNSPEC && XVECLEN (mem, 0) > 0)
9006 mem = XVECEXP (mem, 0, 0);
9007 else if (GET_CODE (mem) == IF_THEN_ELSE)
9008 /* ??? Is this bypass necessary for ld.c? */
9010 gcc_assert (XINT (XEXP (XEXP (mem, 0), 0), 1) == UNSPEC_LDCCLR);
9011 mem = XEXP (mem, 1);
9014 while (GET_CODE (mem) == SUBREG || GET_CODE (mem) == ZERO_EXTEND)
9015 mem = XEXP (mem, 0);
9017 if (GET_CODE (mem) == UNSPEC)
9019 int c = XINT (mem, 1);
9021 gcc_assert (c == UNSPEC_LDA || c == UNSPEC_LDS || c == UNSPEC_LDS_A
9022 || c == UNSPEC_LDSA);
9023 mem = XVECEXP (mem, 0, 0);
9026 /* Note that LO_SUM is used for GOT loads. */
9027 gcc_assert (GET_CODE (mem) == LO_SUM || GET_CODE (mem) == MEM);
9029 return reg_mentioned_p (reg, mem);
9032 /* The following function returns TRUE if INSN produces address for a
9033 load/store insn. We will place such insns into M slot because it
9034 decreases its latency time. */
9037 ia64_produce_address_p (rtx insn)
9043 /* Emit pseudo-ops for the assembler to describe predicate relations.
9044 At present this assumes that we only consider predicate pairs to
9045 be mutex, and that the assembler can deduce proper values from
9046 straight-line code. */
9049 emit_predicate_relation_info (void)
9053 FOR_EACH_BB_REVERSE (bb)
9056 rtx head = BB_HEAD (bb);
9058 /* We only need such notes at code labels. */
9059 if (GET_CODE (head) != CODE_LABEL)
9061 if (NOTE_INSN_BASIC_BLOCK_P (NEXT_INSN (head)))
9062 head = NEXT_INSN (head);
9064 /* Skip p0, which may be thought to be live due to (reg:DI p0)
9065 grabbing the entire block of predicate registers. */
9066 for (r = PR_REG (2); r < PR_REG (64); r += 2)
9067 if (REGNO_REG_SET_P (df_get_live_in (bb), r))
9069 rtx p = gen_rtx_REG (BImode, r);
9070 rtx n = emit_insn_after (gen_pred_rel_mutex (p), head);
9071 if (head == BB_END (bb))
9077 /* Look for conditional calls that do not return, and protect predicate
9078 relations around them. Otherwise the assembler will assume the call
9079 returns, and complain about uses of call-clobbered predicates after
9081 FOR_EACH_BB_REVERSE (bb)
9083 rtx insn = BB_HEAD (bb);
9087 if (GET_CODE (insn) == CALL_INSN
9088 && GET_CODE (PATTERN (insn)) == COND_EXEC
9089 && find_reg_note (insn, REG_NORETURN, NULL_RTX))
9091 rtx b = emit_insn_before (gen_safe_across_calls_all (), insn);
9092 rtx a = emit_insn_after (gen_safe_across_calls_normal (), insn);
9093 if (BB_HEAD (bb) == insn)
9095 if (BB_END (bb) == insn)
9099 if (insn == BB_END (bb))
9101 insn = NEXT_INSN (insn);
9106 /* Perform machine dependent operations on the rtl chain INSNS. */
9111 /* We are freeing block_for_insn in the toplev to keep compatibility
9112 with old MDEP_REORGS that are not CFG based. Recompute it now. */
9113 compute_bb_for_insn ();
9115 /* If optimizing, we'll have split before scheduling. */
9119 if (optimize && ia64_flag_schedule_insns2
9120 && dbg_cnt (ia64_sched2))
9122 timevar_push (TV_SCHED2);
9123 ia64_final_schedule = 1;
9125 initiate_bundle_states ();
9126 ia64_nop = make_insn_raw (gen_nop ());
9127 PREV_INSN (ia64_nop) = NEXT_INSN (ia64_nop) = NULL_RTX;
9128 recog_memoized (ia64_nop);
9129 clocks_length = get_max_uid () + 1;
9130 stops_p = XCNEWVEC (char, clocks_length);
9131 if (ia64_tune == PROCESSOR_ITANIUM)
9133 clocks = XCNEWVEC (int, clocks_length);
9134 add_cycles = XCNEWVEC (int, clocks_length);
9136 if (ia64_tune == PROCESSOR_ITANIUM2)
9138 pos_1 = get_cpu_unit_code ("2_1");
9139 pos_2 = get_cpu_unit_code ("2_2");
9140 pos_3 = get_cpu_unit_code ("2_3");
9141 pos_4 = get_cpu_unit_code ("2_4");
9142 pos_5 = get_cpu_unit_code ("2_5");
9143 pos_6 = get_cpu_unit_code ("2_6");
9144 _0mii_ = get_cpu_unit_code ("2b_0mii.");
9145 _0mmi_ = get_cpu_unit_code ("2b_0mmi.");
9146 _0mfi_ = get_cpu_unit_code ("2b_0mfi.");
9147 _0mmf_ = get_cpu_unit_code ("2b_0mmf.");
9148 _0bbb_ = get_cpu_unit_code ("2b_0bbb.");
9149 _0mbb_ = get_cpu_unit_code ("2b_0mbb.");
9150 _0mib_ = get_cpu_unit_code ("2b_0mib.");
9151 _0mmb_ = get_cpu_unit_code ("2b_0mmb.");
9152 _0mfb_ = get_cpu_unit_code ("2b_0mfb.");
9153 _0mlx_ = get_cpu_unit_code ("2b_0mlx.");
9154 _1mii_ = get_cpu_unit_code ("2b_1mii.");
9155 _1mmi_ = get_cpu_unit_code ("2b_1mmi.");
9156 _1mfi_ = get_cpu_unit_code ("2b_1mfi.");
9157 _1mmf_ = get_cpu_unit_code ("2b_1mmf.");
9158 _1bbb_ = get_cpu_unit_code ("2b_1bbb.");
9159 _1mbb_ = get_cpu_unit_code ("2b_1mbb.");
9160 _1mib_ = get_cpu_unit_code ("2b_1mib.");
9161 _1mmb_ = get_cpu_unit_code ("2b_1mmb.");
9162 _1mfb_ = get_cpu_unit_code ("2b_1mfb.");
9163 _1mlx_ = get_cpu_unit_code ("2b_1mlx.");
9167 pos_1 = get_cpu_unit_code ("1_1");
9168 pos_2 = get_cpu_unit_code ("1_2");
9169 pos_3 = get_cpu_unit_code ("1_3");
9170 pos_4 = get_cpu_unit_code ("1_4");
9171 pos_5 = get_cpu_unit_code ("1_5");
9172 pos_6 = get_cpu_unit_code ("1_6");
9173 _0mii_ = get_cpu_unit_code ("1b_0mii.");
9174 _0mmi_ = get_cpu_unit_code ("1b_0mmi.");
9175 _0mfi_ = get_cpu_unit_code ("1b_0mfi.");
9176 _0mmf_ = get_cpu_unit_code ("1b_0mmf.");
9177 _0bbb_ = get_cpu_unit_code ("1b_0bbb.");
9178 _0mbb_ = get_cpu_unit_code ("1b_0mbb.");
9179 _0mib_ = get_cpu_unit_code ("1b_0mib.");
9180 _0mmb_ = get_cpu_unit_code ("1b_0mmb.");
9181 _0mfb_ = get_cpu_unit_code ("1b_0mfb.");
9182 _0mlx_ = get_cpu_unit_code ("1b_0mlx.");
9183 _1mii_ = get_cpu_unit_code ("1b_1mii.");
9184 _1mmi_ = get_cpu_unit_code ("1b_1mmi.");
9185 _1mfi_ = get_cpu_unit_code ("1b_1mfi.");
9186 _1mmf_ = get_cpu_unit_code ("1b_1mmf.");
9187 _1bbb_ = get_cpu_unit_code ("1b_1bbb.");
9188 _1mbb_ = get_cpu_unit_code ("1b_1mbb.");
9189 _1mib_ = get_cpu_unit_code ("1b_1mib.");
9190 _1mmb_ = get_cpu_unit_code ("1b_1mmb.");
9191 _1mfb_ = get_cpu_unit_code ("1b_1mfb.");
9192 _1mlx_ = get_cpu_unit_code ("1b_1mlx.");
9195 if (flag_selective_scheduling2
9196 && !maybe_skip_selective_scheduling ())
9197 run_selective_scheduling ();
9201 /* Redo alignment computation, as it might gone wrong. */
9202 compute_alignments ();
9204 /* We cannot reuse this one because it has been corrupted by the
9206 finish_bundle_states ();
9207 if (ia64_tune == PROCESSOR_ITANIUM)
9214 emit_insn_group_barriers (dump_file);
9216 ia64_final_schedule = 0;
9217 timevar_pop (TV_SCHED2);
9220 emit_all_insn_group_barriers (dump_file);
9224 /* A call must not be the last instruction in a function, so that the
9225 return address is still within the function, so that unwinding works
9226 properly. Note that IA-64 differs from dwarf2 on this point. */
9227 if (flag_unwind_tables || (flag_exceptions && !USING_SJLJ_EXCEPTIONS))
9232 insn = get_last_insn ();
9233 if (! INSN_P (insn))
9234 insn = prev_active_insn (insn);
9235 /* Skip over insns that expand to nothing. */
9236 while (GET_CODE (insn) == INSN && get_attr_empty (insn) == EMPTY_YES)
9238 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
9239 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
9241 insn = prev_active_insn (insn);
9243 if (GET_CODE (insn) == CALL_INSN)
9246 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
9247 emit_insn (gen_break_f ());
9248 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
9252 emit_predicate_relation_info ();
9254 if (ia64_flag_var_tracking)
9256 timevar_push (TV_VAR_TRACKING);
9257 variable_tracking_main ();
9258 timevar_pop (TV_VAR_TRACKING);
9260 df_finish_pass (false);
9263 /* Return true if REGNO is used by the epilogue. */
9266 ia64_epilogue_uses (int regno)
9271 /* With a call to a function in another module, we will write a new
9272 value to "gp". After returning from such a call, we need to make
9273 sure the function restores the original gp-value, even if the
9274 function itself does not use the gp anymore. */
9275 return !(TARGET_AUTO_PIC || TARGET_NO_PIC);
9277 case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3):
9278 case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7):
9279 /* For functions defined with the syscall_linkage attribute, all
9280 input registers are marked as live at all function exits. This
9281 prevents the register allocator from using the input registers,
9282 which in turn makes it possible to restart a system call after
9283 an interrupt without having to save/restore the input registers.
9284 This also prevents kernel data from leaking to application code. */
9285 return lookup_attribute ("syscall_linkage",
9286 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))) != NULL;
9289 /* Conditional return patterns can't represent the use of `b0' as
9290 the return address, so we force the value live this way. */
9294 /* Likewise for ar.pfs, which is used by br.ret. */
9302 /* Return true if REGNO is used by the frame unwinder. */
9305 ia64_eh_uses (int regno)
9307 enum ia64_frame_regs r;
9309 if (! reload_completed)
9315 for (r = reg_save_b0; r <= reg_save_ar_lc; r++)
9316 if (regno == current_frame_info.r[r]
9317 || regno == emitted_frame_related_regs[r])
9323 /* Return true if this goes in small data/bss. */
9325 /* ??? We could also support own long data here. Generating movl/add/ld8
9326 instead of addl,ld8/ld8. This makes the code bigger, but should make the
9327 code faster because there is one less load. This also includes incomplete
9328 types which can't go in sdata/sbss. */
9331 ia64_in_small_data_p (const_tree exp)
9333 if (TARGET_NO_SDATA)
9336 /* We want to merge strings, so we never consider them small data. */
9337 if (TREE_CODE (exp) == STRING_CST)
9340 /* Functions are never small data. */
9341 if (TREE_CODE (exp) == FUNCTION_DECL)
9344 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
9346 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
9348 if (strcmp (section, ".sdata") == 0
9349 || strncmp (section, ".sdata.", 7) == 0
9350 || strncmp (section, ".gnu.linkonce.s.", 16) == 0
9351 || strcmp (section, ".sbss") == 0
9352 || strncmp (section, ".sbss.", 6) == 0
9353 || strncmp (section, ".gnu.linkonce.sb.", 17) == 0)
9358 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
9360 /* If this is an incomplete type with size 0, then we can't put it
9361 in sdata because it might be too big when completed. */
9362 if (size > 0 && size <= ia64_section_threshold)
9369 /* Output assembly directives for prologue regions. */
9371 /* The current basic block number. */
9373 static bool last_block;
9375 /* True if we need a copy_state command at the start of the next block. */
9377 static bool need_copy_state;
9379 #ifndef MAX_ARTIFICIAL_LABEL_BYTES
9380 # define MAX_ARTIFICIAL_LABEL_BYTES 30
9383 /* Emit a debugging label after a call-frame-related insn. We'd
9384 rather output the label right away, but we'd have to output it
9385 after, not before, the instruction, and the instruction has not
9386 been output yet. So we emit the label after the insn, delete it to
9387 avoid introducing basic blocks, and mark it as preserved, such that
9388 it is still output, given that it is referenced in debug info. */
9391 ia64_emit_deleted_label_after_insn (rtx insn)
9393 char label[MAX_ARTIFICIAL_LABEL_BYTES];
9394 rtx lb = gen_label_rtx ();
9395 rtx label_insn = emit_label_after (lb, insn);
9397 LABEL_PRESERVE_P (lb) = 1;
9399 delete_insn (label_insn);
9401 ASM_GENERATE_INTERNAL_LABEL (label, "L", CODE_LABEL_NUMBER (label_insn));
9403 return xstrdup (label);
9406 /* Define the CFA after INSN with the steady-state definition. */
9409 ia64_dwarf2out_def_steady_cfa (rtx insn)
9411 rtx fp = frame_pointer_needed
9412 ? hard_frame_pointer_rtx
9413 : stack_pointer_rtx;
9416 (ia64_emit_deleted_label_after_insn (insn),
9418 ia64_initial_elimination_offset
9419 (REGNO (arg_pointer_rtx), REGNO (fp))
9420 + ARG_POINTER_CFA_OFFSET (current_function_decl));
9423 /* The generic dwarf2 frame debug info generator does not define a
9424 separate region for the very end of the epilogue, so refrain from
9425 doing so in the IA64-specific code as well. */
9427 #define IA64_CHANGE_CFA_IN_EPILOGUE 0
9429 /* The function emits unwind directives for the start of an epilogue. */
9432 process_epilogue (FILE *asm_out_file, rtx insn, bool unwind, bool frame)
9434 /* If this isn't the last block of the function, then we need to label the
9435 current state, and copy it back in at the start of the next block. */
9440 fprintf (asm_out_file, "\t.label_state %d\n",
9441 ++cfun->machine->state_num);
9442 need_copy_state = true;
9446 fprintf (asm_out_file, "\t.restore sp\n");
9447 if (IA64_CHANGE_CFA_IN_EPILOGUE && frame)
9448 dwarf2out_def_cfa (ia64_emit_deleted_label_after_insn (insn),
9449 STACK_POINTER_REGNUM, INCOMING_FRAME_SP_OFFSET);
9452 /* This function processes a SET pattern looking for specific patterns
9453 which result in emitting an assembly directive required for unwinding. */
9456 process_set (FILE *asm_out_file, rtx pat, rtx insn, bool unwind, bool frame)
9458 rtx src = SET_SRC (pat);
9459 rtx dest = SET_DEST (pat);
9460 int src_regno, dest_regno;
9462 /* Look for the ALLOC insn. */
9463 if (GET_CODE (src) == UNSPEC_VOLATILE
9464 && XINT (src, 1) == UNSPECV_ALLOC
9465 && GET_CODE (dest) == REG)
9467 dest_regno = REGNO (dest);
9469 /* If this is the final destination for ar.pfs, then this must
9470 be the alloc in the prologue. */
9471 if (dest_regno == current_frame_info.r[reg_save_ar_pfs])
9474 fprintf (asm_out_file, "\t.save ar.pfs, r%d\n",
9475 ia64_dbx_register_number (dest_regno));
9479 /* This must be an alloc before a sibcall. We must drop the
9480 old frame info. The easiest way to drop the old frame
9481 info is to ensure we had a ".restore sp" directive
9482 followed by a new prologue. If the procedure doesn't
9483 have a memory-stack frame, we'll issue a dummy ".restore
9485 if (current_frame_info.total_size == 0 && !frame_pointer_needed)
9486 /* if haven't done process_epilogue() yet, do it now */
9487 process_epilogue (asm_out_file, insn, unwind, frame);
9489 fprintf (asm_out_file, "\t.prologue\n");
9494 /* Look for SP = .... */
9495 if (GET_CODE (dest) == REG && REGNO (dest) == STACK_POINTER_REGNUM)
9497 if (GET_CODE (src) == PLUS)
9499 rtx op0 = XEXP (src, 0);
9500 rtx op1 = XEXP (src, 1);
9502 gcc_assert (op0 == dest && GET_CODE (op1) == CONST_INT);
9504 if (INTVAL (op1) < 0)
9506 gcc_assert (!frame_pointer_needed);
9508 fprintf (asm_out_file, "\t.fframe "HOST_WIDE_INT_PRINT_DEC"\n",
9511 ia64_dwarf2out_def_steady_cfa (insn);
9514 process_epilogue (asm_out_file, insn, unwind, frame);
9518 gcc_assert (GET_CODE (src) == REG
9519 && REGNO (src) == HARD_FRAME_POINTER_REGNUM);
9520 process_epilogue (asm_out_file, insn, unwind, frame);
9526 /* Register move we need to look at. */
9527 if (GET_CODE (dest) == REG && GET_CODE (src) == REG)
9529 src_regno = REGNO (src);
9530 dest_regno = REGNO (dest);
9535 /* Saving return address pointer. */
9536 gcc_assert (dest_regno == current_frame_info.r[reg_save_b0]);
9538 fprintf (asm_out_file, "\t.save rp, r%d\n",
9539 ia64_dbx_register_number (dest_regno));
9543 gcc_assert (dest_regno == current_frame_info.r[reg_save_pr]);
9545 fprintf (asm_out_file, "\t.save pr, r%d\n",
9546 ia64_dbx_register_number (dest_regno));
9549 case AR_UNAT_REGNUM:
9550 gcc_assert (dest_regno == current_frame_info.r[reg_save_ar_unat]);
9552 fprintf (asm_out_file, "\t.save ar.unat, r%d\n",
9553 ia64_dbx_register_number (dest_regno));
9557 gcc_assert (dest_regno == current_frame_info.r[reg_save_ar_lc]);
9559 fprintf (asm_out_file, "\t.save ar.lc, r%d\n",
9560 ia64_dbx_register_number (dest_regno));
9563 case STACK_POINTER_REGNUM:
9564 gcc_assert (dest_regno == HARD_FRAME_POINTER_REGNUM
9565 && frame_pointer_needed);
9567 fprintf (asm_out_file, "\t.vframe r%d\n",
9568 ia64_dbx_register_number (dest_regno));
9570 ia64_dwarf2out_def_steady_cfa (insn);
9574 /* Everything else should indicate being stored to memory. */
9579 /* Memory store we need to look at. */
9580 if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
9586 if (GET_CODE (XEXP (dest, 0)) == REG)
9588 base = XEXP (dest, 0);
9593 gcc_assert (GET_CODE (XEXP (dest, 0)) == PLUS
9594 && GET_CODE (XEXP (XEXP (dest, 0), 1)) == CONST_INT);
9595 base = XEXP (XEXP (dest, 0), 0);
9596 off = INTVAL (XEXP (XEXP (dest, 0), 1));
9599 if (base == hard_frame_pointer_rtx)
9601 saveop = ".savepsp";
9606 gcc_assert (base == stack_pointer_rtx);
9610 src_regno = REGNO (src);
9614 gcc_assert (!current_frame_info.r[reg_save_b0]);
9616 fprintf (asm_out_file, "\t%s rp, %ld\n", saveop, off);
9620 gcc_assert (!current_frame_info.r[reg_save_pr]);
9622 fprintf (asm_out_file, "\t%s pr, %ld\n", saveop, off);
9626 gcc_assert (!current_frame_info.r[reg_save_ar_lc]);
9628 fprintf (asm_out_file, "\t%s ar.lc, %ld\n", saveop, off);
9632 gcc_assert (!current_frame_info.r[reg_save_ar_pfs]);
9634 fprintf (asm_out_file, "\t%s ar.pfs, %ld\n", saveop, off);
9637 case AR_UNAT_REGNUM:
9638 gcc_assert (!current_frame_info.r[reg_save_ar_unat]);
9640 fprintf (asm_out_file, "\t%s ar.unat, %ld\n", saveop, off);
9648 fprintf (asm_out_file, "\t.save.g 0x%x\n",
9649 1 << (src_regno - GR_REG (4)));
9658 fprintf (asm_out_file, "\t.save.b 0x%x\n",
9659 1 << (src_regno - BR_REG (1)));
9667 fprintf (asm_out_file, "\t.save.f 0x%x\n",
9668 1 << (src_regno - FR_REG (2)));
9671 case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19):
9672 case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23):
9673 case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27):
9674 case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31):
9676 fprintf (asm_out_file, "\t.save.gf 0x0, 0x%x\n",
9677 1 << (src_regno - FR_REG (12)));
9689 /* This function looks at a single insn and emits any directives
9690 required to unwind this insn. */
9692 process_for_unwind_directive (FILE *asm_out_file, rtx insn)
9694 bool unwind = (flag_unwind_tables
9695 || (flag_exceptions && !USING_SJLJ_EXCEPTIONS));
9696 bool frame = dwarf2out_do_frame ();
9698 if (unwind || frame)
9702 if (NOTE_INSN_BASIC_BLOCK_P (insn))
9704 last_block = NOTE_BASIC_BLOCK (insn)->next_bb == EXIT_BLOCK_PTR;
9706 /* Restore unwind state from immediately before the epilogue. */
9707 if (need_copy_state)
9711 fprintf (asm_out_file, "\t.body\n");
9712 fprintf (asm_out_file, "\t.copy_state %d\n",
9713 cfun->machine->state_num);
9715 if (IA64_CHANGE_CFA_IN_EPILOGUE && frame)
9716 ia64_dwarf2out_def_steady_cfa (insn);
9717 need_copy_state = false;
9721 if (GET_CODE (insn) == NOTE || ! RTX_FRAME_RELATED_P (insn))
9724 pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX);
9726 pat = XEXP (pat, 0);
9728 pat = PATTERN (insn);
9730 switch (GET_CODE (pat))
9733 process_set (asm_out_file, pat, insn, unwind, frame);
9739 int limit = XVECLEN (pat, 0);
9740 for (par_index = 0; par_index < limit; par_index++)
9742 rtx x = XVECEXP (pat, 0, par_index);
9743 if (GET_CODE (x) == SET)
9744 process_set (asm_out_file, x, insn, unwind, frame);
9759 IA64_BUILTIN_COPYSIGNQ,
9761 IA64_BUILTIN_FLUSHRS,
9766 ia64_init_builtins (void)
9771 /* The __fpreg type. */
9772 fpreg_type = make_node (REAL_TYPE);
9773 TYPE_PRECISION (fpreg_type) = 82;
9774 layout_type (fpreg_type);
9775 (*lang_hooks.types.register_builtin_type) (fpreg_type, "__fpreg");
9777 /* The __float80 type. */
9778 float80_type = make_node (REAL_TYPE);
9779 TYPE_PRECISION (float80_type) = 80;
9780 layout_type (float80_type);
9781 (*lang_hooks.types.register_builtin_type) (float80_type, "__float80");
9783 /* The __float128 type. */
9787 tree float128_type = make_node (REAL_TYPE);
9789 TYPE_PRECISION (float128_type) = 128;
9790 layout_type (float128_type);
9791 (*lang_hooks.types.register_builtin_type) (float128_type, "__float128");
9793 /* TFmode support builtins. */
9794 ftype = build_function_type (float128_type, void_list_node);
9795 add_builtin_function ("__builtin_infq", ftype,
9796 IA64_BUILTIN_INFQ, BUILT_IN_MD,
9799 ftype = build_function_type_list (float128_type,
9802 decl = add_builtin_function ("__builtin_fabsq", ftype,
9803 IA64_BUILTIN_FABSQ, BUILT_IN_MD,
9804 "__fabstf2", NULL_TREE);
9805 TREE_READONLY (decl) = 1;
9807 ftype = build_function_type_list (float128_type,
9811 decl = add_builtin_function ("__builtin_copysignq", ftype,
9812 IA64_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
9813 "__copysigntf3", NULL_TREE);
9814 TREE_READONLY (decl) = 1;
9817 /* Under HPUX, this is a synonym for "long double". */
9818 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
9821 #define def_builtin(name, type, code) \
9822 add_builtin_function ((name), (type), (code), BUILT_IN_MD, \
9825 def_builtin ("__builtin_ia64_bsp",
9826 build_function_type (ptr_type_node, void_list_node),
9829 def_builtin ("__builtin_ia64_flushrs",
9830 build_function_type (void_type_node, void_list_node),
9831 IA64_BUILTIN_FLUSHRS);
9837 if (built_in_decls [BUILT_IN_FINITE])
9838 set_user_assembler_name (built_in_decls [BUILT_IN_FINITE],
9840 if (built_in_decls [BUILT_IN_FINITEF])
9841 set_user_assembler_name (built_in_decls [BUILT_IN_FINITEF],
9843 if (built_in_decls [BUILT_IN_FINITEL])
9844 set_user_assembler_name (built_in_decls [BUILT_IN_FINITEL],
9850 ia64_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
9851 enum machine_mode mode ATTRIBUTE_UNUSED,
9852 int ignore ATTRIBUTE_UNUSED)
9854 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9855 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
9859 case IA64_BUILTIN_BSP:
9860 if (! target || ! register_operand (target, DImode))
9861 target = gen_reg_rtx (DImode);
9862 emit_insn (gen_bsp_value (target));
9863 #ifdef POINTERS_EXTEND_UNSIGNED
9864 target = convert_memory_address (ptr_mode, target);
9868 case IA64_BUILTIN_FLUSHRS:
9869 emit_insn (gen_flushrs ());
9872 case IA64_BUILTIN_INFQ:
9874 REAL_VALUE_TYPE inf;
9878 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
9880 tmp = validize_mem (force_const_mem (mode, tmp));
9883 target = gen_reg_rtx (mode);
9885 emit_move_insn (target, tmp);
9889 case IA64_BUILTIN_FABSQ:
9890 case IA64_BUILTIN_COPYSIGNQ:
9891 return expand_call (exp, target, ignore);
9900 /* For the HP-UX IA64 aggregate parameters are passed stored in the
9901 most significant bits of the stack slot. */
9904 ia64_hpux_function_arg_padding (enum machine_mode mode, const_tree type)
9906 /* Exception to normal case for structures/unions/etc. */
9908 if (type && AGGREGATE_TYPE_P (type)
9909 && int_size_in_bytes (type) < UNITS_PER_WORD)
9912 /* Fall back to the default. */
9913 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
9916 /* Emit text to declare externally defined variables and functions, because
9917 the Intel assembler does not support undefined externals. */
9920 ia64_asm_output_external (FILE *file, tree decl, const char *name)
9922 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
9923 set in order to avoid putting out names that are never really
9925 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
9927 /* maybe_assemble_visibility will return 1 if the assembler
9928 visibility directive is output. */
9929 int need_visibility = ((*targetm.binds_local_p) (decl)
9930 && maybe_assemble_visibility (decl));
9932 /* GNU as does not need anything here, but the HP linker does
9933 need something for external functions. */
9934 if ((TARGET_HPUX_LD || !TARGET_GNU_AS)
9935 && TREE_CODE (decl) == FUNCTION_DECL)
9936 (*targetm.asm_out.globalize_decl_name) (file, decl);
9937 else if (need_visibility && !TARGET_GNU_AS)
9938 (*targetm.asm_out.globalize_label) (file, name);
9942 /* Set SImode div/mod functions, init_integral_libfuncs only initializes
9943 modes of word_mode and larger. Rename the TFmode libfuncs using the
9944 HPUX conventions. __divtf3 is used for XFmode. We need to keep it for
9945 backward compatibility. */
9948 ia64_init_libfuncs (void)
9950 set_optab_libfunc (sdiv_optab, SImode, "__divsi3");
9951 set_optab_libfunc (udiv_optab, SImode, "__udivsi3");
9952 set_optab_libfunc (smod_optab, SImode, "__modsi3");
9953 set_optab_libfunc (umod_optab, SImode, "__umodsi3");
9955 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
9956 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
9957 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
9958 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
9959 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
9961 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
9962 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
9963 set_conv_libfunc (sext_optab, TFmode, XFmode, "_U_Qfcnvff_f80_to_quad");
9964 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
9965 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
9966 set_conv_libfunc (trunc_optab, XFmode, TFmode, "_U_Qfcnvff_quad_to_f80");
9968 set_conv_libfunc (sfix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_sgl");
9969 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
9970 set_conv_libfunc (sfix_optab, TImode, TFmode, "_U_Qfcnvfxt_quad_to_quad");
9971 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxut_quad_to_sgl");
9972 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxut_quad_to_dbl");
9974 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
9975 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
9976 set_conv_libfunc (sfloat_optab, TFmode, TImode, "_U_Qfcnvxf_quad_to_quad");
9977 /* HP-UX 11.23 libc does not have a function for unsigned
9978 SImode-to-TFmode conversion. */
9979 set_conv_libfunc (ufloat_optab, TFmode, DImode, "_U_Qfcnvxuf_dbl_to_quad");
9982 /* Rename all the TFmode libfuncs using the HPUX conventions. */
9985 ia64_hpux_init_libfuncs (void)
9987 ia64_init_libfuncs ();
9989 /* The HP SI millicode division and mod functions expect DI arguments.
9990 By turning them off completely we avoid using both libgcc and the
9991 non-standard millicode routines and use the HP DI millicode routines
9994 set_optab_libfunc (sdiv_optab, SImode, 0);
9995 set_optab_libfunc (udiv_optab, SImode, 0);
9996 set_optab_libfunc (smod_optab, SImode, 0);
9997 set_optab_libfunc (umod_optab, SImode, 0);
9999 set_optab_libfunc (sdiv_optab, DImode, "__milli_divI");
10000 set_optab_libfunc (udiv_optab, DImode, "__milli_divU");
10001 set_optab_libfunc (smod_optab, DImode, "__milli_remI");
10002 set_optab_libfunc (umod_optab, DImode, "__milli_remU");
10004 /* HP-UX libc has TF min/max/abs routines in it. */
10005 set_optab_libfunc (smin_optab, TFmode, "_U_Qfmin");
10006 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
10007 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
10009 /* ia64_expand_compare uses this. */
10010 cmptf_libfunc = init_one_libfunc ("_U_Qfcmp");
10012 /* These should never be used. */
10013 set_optab_libfunc (eq_optab, TFmode, 0);
10014 set_optab_libfunc (ne_optab, TFmode, 0);
10015 set_optab_libfunc (gt_optab, TFmode, 0);
10016 set_optab_libfunc (ge_optab, TFmode, 0);
10017 set_optab_libfunc (lt_optab, TFmode, 0);
10018 set_optab_libfunc (le_optab, TFmode, 0);
10021 /* Rename the division and modulus functions in VMS. */
10024 ia64_vms_init_libfuncs (void)
10026 set_optab_libfunc (sdiv_optab, SImode, "OTS$DIV_I");
10027 set_optab_libfunc (sdiv_optab, DImode, "OTS$DIV_L");
10028 set_optab_libfunc (udiv_optab, SImode, "OTS$DIV_UI");
10029 set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL");
10030 set_optab_libfunc (smod_optab, SImode, "OTS$REM_I");
10031 set_optab_libfunc (smod_optab, DImode, "OTS$REM_L");
10032 set_optab_libfunc (umod_optab, SImode, "OTS$REM_UI");
10033 set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL");
10036 /* Rename the TFmode libfuncs available from soft-fp in glibc using
10037 the HPUX conventions. */
10040 ia64_sysv4_init_libfuncs (void)
10042 ia64_init_libfuncs ();
10044 /* These functions are not part of the HPUX TFmode interface. We
10045 use them instead of _U_Qfcmp, which doesn't work the way we
10047 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
10048 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
10049 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
10050 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
10051 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
10052 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
10054 /* We leave out _U_Qfmin, _U_Qfmax and _U_Qfabs since soft-fp in
10055 glibc doesn't have them. */
10061 ia64_soft_fp_init_libfuncs (void)
10065 /* For HPUX, it is illegal to have relocations in shared segments. */
10068 ia64_hpux_reloc_rw_mask (void)
10073 /* For others, relax this so that relocations to local data goes in
10074 read-only segments, but we still cannot allow global relocations
10075 in read-only segments. */
10078 ia64_reloc_rw_mask (void)
10080 return flag_pic ? 3 : 2;
10083 /* Return the section to use for X. The only special thing we do here
10084 is to honor small data. */
10087 ia64_select_rtx_section (enum machine_mode mode, rtx x,
10088 unsigned HOST_WIDE_INT align)
10090 if (GET_MODE_SIZE (mode) > 0
10091 && GET_MODE_SIZE (mode) <= ia64_section_threshold
10092 && !TARGET_NO_SDATA)
10093 return sdata_section;
10095 return default_elf_select_rtx_section (mode, x, align);
10098 static unsigned int
10099 ia64_section_type_flags (tree decl, const char *name, int reloc)
10101 unsigned int flags = 0;
10103 if (strcmp (name, ".sdata") == 0
10104 || strncmp (name, ".sdata.", 7) == 0
10105 || strncmp (name, ".gnu.linkonce.s.", 16) == 0
10106 || strncmp (name, ".sdata2.", 8) == 0
10107 || strncmp (name, ".gnu.linkonce.s2.", 17) == 0
10108 || strcmp (name, ".sbss") == 0
10109 || strncmp (name, ".sbss.", 6) == 0
10110 || strncmp (name, ".gnu.linkonce.sb.", 17) == 0)
10111 flags = SECTION_SMALL;
10113 flags |= default_section_type_flags (decl, name, reloc);
10117 /* Returns true if FNTYPE (a FUNCTION_TYPE or a METHOD_TYPE) returns a
10118 structure type and that the address of that type should be passed
10119 in out0, rather than in r8. */
10122 ia64_struct_retval_addr_is_first_parm_p (tree fntype)
10124 tree ret_type = TREE_TYPE (fntype);
10126 /* The Itanium C++ ABI requires that out0, rather than r8, be used
10127 as the structure return address parameter, if the return value
10128 type has a non-trivial copy constructor or destructor. It is not
10129 clear if this same convention should be used for other
10130 programming languages. Until G++ 3.4, we incorrectly used r8 for
10131 these return values. */
10132 return (abi_version_at_least (2)
10134 && TYPE_MODE (ret_type) == BLKmode
10135 && TREE_ADDRESSABLE (ret_type)
10136 && strcmp (lang_hooks.name, "GNU C++") == 0);
10139 /* Output the assembler code for a thunk function. THUNK_DECL is the
10140 declaration for the thunk function itself, FUNCTION is the decl for
10141 the target function. DELTA is an immediate constant offset to be
10142 added to THIS. If VCALL_OFFSET is nonzero, the word at
10143 *(*this + vcall_offset) should be added to THIS. */
10146 ia64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
10147 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
10150 rtx this_rtx, insn, funexp;
10151 unsigned int this_parmno;
10152 unsigned int this_regno;
10155 reload_completed = 1;
10156 epilogue_completed = 1;
10158 /* Set things up as ia64_expand_prologue might. */
10159 last_scratch_gr_reg = 15;
10161 memset (¤t_frame_info, 0, sizeof (current_frame_info));
10162 current_frame_info.spill_cfa_off = -16;
10163 current_frame_info.n_input_regs = 1;
10164 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
10166 /* Mark the end of the (empty) prologue. */
10167 emit_note (NOTE_INSN_PROLOGUE_END);
10169 /* Figure out whether "this" will be the first parameter (the
10170 typical case) or the second parameter (as happens when the
10171 virtual function returns certain class objects). */
10173 = (ia64_struct_retval_addr_is_first_parm_p (TREE_TYPE (thunk))
10175 this_regno = IN_REG (this_parmno);
10176 if (!TARGET_REG_NAMES)
10177 reg_names[this_regno] = ia64_reg_numbers[this_parmno];
10179 this_rtx = gen_rtx_REG (Pmode, this_regno);
10181 /* Apply the constant offset, if required. */
10182 delta_rtx = GEN_INT (delta);
10185 rtx tmp = gen_rtx_REG (ptr_mode, this_regno);
10186 REG_POINTER (tmp) = 1;
10187 if (delta && satisfies_constraint_I (delta_rtx))
10189 emit_insn (gen_ptr_extend_plus_imm (this_rtx, tmp, delta_rtx));
10193 emit_insn (gen_ptr_extend (this_rtx, tmp));
10197 if (!satisfies_constraint_I (delta_rtx))
10199 rtx tmp = gen_rtx_REG (Pmode, 2);
10200 emit_move_insn (tmp, delta_rtx);
10203 emit_insn (gen_adddi3 (this_rtx, this_rtx, delta_rtx));
10206 /* Apply the offset from the vtable, if required. */
10209 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
10210 rtx tmp = gen_rtx_REG (Pmode, 2);
10214 rtx t = gen_rtx_REG (ptr_mode, 2);
10215 REG_POINTER (t) = 1;
10216 emit_move_insn (t, gen_rtx_MEM (ptr_mode, this_rtx));
10217 if (satisfies_constraint_I (vcall_offset_rtx))
10219 emit_insn (gen_ptr_extend_plus_imm (tmp, t, vcall_offset_rtx));
10223 emit_insn (gen_ptr_extend (tmp, t));
10226 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
10230 if (!satisfies_constraint_J (vcall_offset_rtx))
10232 rtx tmp2 = gen_rtx_REG (Pmode, next_scratch_gr_reg ());
10233 emit_move_insn (tmp2, vcall_offset_rtx);
10234 vcall_offset_rtx = tmp2;
10236 emit_insn (gen_adddi3 (tmp, tmp, vcall_offset_rtx));
10240 emit_insn (gen_zero_extendsidi2 (tmp, gen_rtx_MEM (ptr_mode, tmp)));
10242 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
10244 emit_insn (gen_adddi3 (this_rtx, this_rtx, tmp));
10247 /* Generate a tail call to the target function. */
10248 if (! TREE_USED (function))
10250 assemble_external (function);
10251 TREE_USED (function) = 1;
10253 funexp = XEXP (DECL_RTL (function), 0);
10254 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
10255 ia64_expand_call (NULL_RTX, funexp, NULL_RTX, 1);
10256 insn = get_last_insn ();
10257 SIBLING_CALL_P (insn) = 1;
10259 /* Code generation for calls relies on splitting. */
10260 reload_completed = 1;
10261 epilogue_completed = 1;
10262 try_split (PATTERN (insn), insn, 0);
10266 /* Run just enough of rest_of_compilation to get the insns emitted.
10267 There's not really enough bulk here to make other passes such as
10268 instruction scheduling worth while. Note that use_thunk calls
10269 assemble_start_function and assemble_end_function. */
10271 insn_locators_alloc ();
10272 emit_all_insn_group_barriers (NULL);
10273 insn = get_insns ();
10274 shorten_branches (insn);
10275 final_start_function (insn, file, 1);
10276 final (insn, file, 1);
10277 final_end_function ();
10278 free_after_compilation (cfun);
10280 reload_completed = 0;
10281 epilogue_completed = 0;
10284 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
10287 ia64_struct_value_rtx (tree fntype,
10288 int incoming ATTRIBUTE_UNUSED)
10290 if (fntype && ia64_struct_retval_addr_is_first_parm_p (fntype))
10292 return gen_rtx_REG (Pmode, GR_REG (8));
10296 ia64_scalar_mode_supported_p (enum machine_mode mode)
10322 ia64_vector_mode_supported_p (enum machine_mode mode)
10339 /* Implement the FUNCTION_PROFILER macro. */
10342 ia64_output_function_profiler (FILE *file, int labelno)
10344 bool indirect_call;
10346 /* If the function needs a static chain and the static chain
10347 register is r15, we use an indirect call so as to bypass
10348 the PLT stub in case the executable is dynamically linked,
10349 because the stub clobbers r15 as per 5.3.6 of the psABI.
10350 We don't need to do that in non canonical PIC mode. */
10352 if (cfun->static_chain_decl && !TARGET_NO_PIC && !TARGET_AUTO_PIC)
10354 gcc_assert (STATIC_CHAIN_REGNUM == 15);
10355 indirect_call = true;
10358 indirect_call = false;
10361 fputs ("\t.prologue 4, r40\n", file);
10363 fputs ("\t.prologue\n\t.save ar.pfs, r40\n", file);
10364 fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", file);
10366 if (NO_PROFILE_COUNTERS)
10367 fputs ("\tmov out3 = r0\n", file);
10371 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
10373 if (TARGET_AUTO_PIC)
10374 fputs ("\tmovl out3 = @gprel(", file);
10376 fputs ("\taddl out3 = @ltoff(", file);
10377 assemble_name (file, buf);
10378 if (TARGET_AUTO_PIC)
10379 fputs (")\n", file);
10381 fputs ("), r1\n", file);
10385 fputs ("\taddl r14 = @ltoff(@fptr(_mcount)), r1\n", file);
10386 fputs ("\t;;\n", file);
10388 fputs ("\t.save rp, r42\n", file);
10389 fputs ("\tmov out2 = b0\n", file);
10391 fputs ("\tld8 r14 = [r14]\n\t;;\n", file);
10392 fputs ("\t.body\n", file);
10393 fputs ("\tmov out1 = r1\n", file);
10396 fputs ("\tld8 r16 = [r14], 8\n\t;;\n", file);
10397 fputs ("\tmov b6 = r16\n", file);
10398 fputs ("\tld8 r1 = [r14]\n", file);
10399 fputs ("\tbr.call.sptk.many b0 = b6\n\t;;\n", file);
10402 fputs ("\tbr.call.sptk.many b0 = _mcount\n\t;;\n", file);
10405 static GTY(()) rtx mcount_func_rtx;
10407 gen_mcount_func_rtx (void)
10409 if (!mcount_func_rtx)
10410 mcount_func_rtx = init_one_libfunc ("_mcount");
10411 return mcount_func_rtx;
10415 ia64_profile_hook (int labelno)
10419 if (NO_PROFILE_COUNTERS)
10420 label = const0_rtx;
10424 const char *label_name;
10425 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
10426 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
10427 label = gen_rtx_SYMBOL_REF (Pmode, label_name);
10428 SYMBOL_REF_FLAGS (label) = SYMBOL_FLAG_LOCAL;
10430 ip = gen_reg_rtx (Pmode);
10431 emit_insn (gen_ip_value (ip));
10432 emit_library_call (gen_mcount_func_rtx (), LCT_NORMAL,
10434 gen_rtx_REG (Pmode, BR_REG (0)), Pmode,
10439 /* Return the mangling of TYPE if it is an extended fundamental type. */
10441 static const char *
10442 ia64_mangle_type (const_tree type)
10444 type = TYPE_MAIN_VARIANT (type);
10446 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
10447 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
10450 /* On HP-UX, "long double" is mangled as "e" so __float128 is
10452 if (!TARGET_HPUX && TYPE_MODE (type) == TFmode)
10454 /* On HP-UX, "e" is not available as a mangling of __float80 so use
10455 an extended mangling. Elsewhere, "e" is available since long
10456 double is 80 bits. */
10457 if (TYPE_MODE (type) == XFmode)
10458 return TARGET_HPUX ? "u9__float80" : "e";
10459 if (TYPE_MODE (type) == RFmode)
10460 return "u7__fpreg";
10464 /* Return the diagnostic message string if conversion from FROMTYPE to
10465 TOTYPE is not allowed, NULL otherwise. */
10466 static const char *
10467 ia64_invalid_conversion (const_tree fromtype, const_tree totype)
10469 /* Reject nontrivial conversion to or from __fpreg. */
10470 if (TYPE_MODE (fromtype) == RFmode
10471 && TYPE_MODE (totype) != RFmode
10472 && TYPE_MODE (totype) != VOIDmode)
10473 return N_("invalid conversion from %<__fpreg%>");
10474 if (TYPE_MODE (totype) == RFmode
10475 && TYPE_MODE (fromtype) != RFmode)
10476 return N_("invalid conversion to %<__fpreg%>");
10480 /* Return the diagnostic message string if the unary operation OP is
10481 not permitted on TYPE, NULL otherwise. */
10482 static const char *
10483 ia64_invalid_unary_op (int op, const_tree type)
10485 /* Reject operations on __fpreg other than unary + or &. */
10486 if (TYPE_MODE (type) == RFmode
10487 && op != CONVERT_EXPR
10488 && op != ADDR_EXPR)
10489 return N_("invalid operation on %<__fpreg%>");
10493 /* Return the diagnostic message string if the binary operation OP is
10494 not permitted on TYPE1 and TYPE2, NULL otherwise. */
10495 static const char *
10496 ia64_invalid_binary_op (int op ATTRIBUTE_UNUSED, const_tree type1, const_tree type2)
10498 /* Reject operations on __fpreg. */
10499 if (TYPE_MODE (type1) == RFmode || TYPE_MODE (type2) == RFmode)
10500 return N_("invalid operation on %<__fpreg%>");
10504 /* Implement overriding of the optimization options. */
10506 ia64_optimization_options (int level ATTRIBUTE_UNUSED,
10507 int size ATTRIBUTE_UNUSED)
10509 /* Let the scheduler form additional regions. */
10510 set_param_value ("max-sched-extend-regions-iters", 2);
10512 /* Set the default values for cache-related parameters. */
10513 set_param_value ("simultaneous-prefetches", 6);
10514 set_param_value ("l1-cache-line-size", 32);
10516 set_param_value("sched-mem-true-dep-cost", 4);
10519 /* HP-UX version_id attribute.
10520 For object foo, if the version_id is set to 1234 put out an alias
10521 of '.alias foo "foo{1234}" We can't use "foo{1234}" in anything
10522 other than an alias statement because it is an illegal symbol name. */
10525 ia64_handle_version_id_attribute (tree *node ATTRIBUTE_UNUSED,
10526 tree name ATTRIBUTE_UNUSED,
10528 int flags ATTRIBUTE_UNUSED,
10529 bool *no_add_attrs)
10531 tree arg = TREE_VALUE (args);
10533 if (TREE_CODE (arg) != STRING_CST)
10535 error("version attribute is not a string");
10536 *no_add_attrs = true;
10542 /* Target hook for c_mode_for_suffix. */
10544 static enum machine_mode
10545 ia64_c_mode_for_suffix (char suffix)
10555 #include "gt-ia64.h"