1 /* Definitions of target machine for GNU compiler.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
4 Free Software Foundation, Inc.
5 Contributed by James E. Wilson <wilson@cygnus.com> and
6 David Mosberger <davidm@hpl.hp.com>.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
43 #include "basic-block.h"
45 #include "diagnostic-core.h"
46 #include "sched-int.h"
49 #include "target-def.h"
52 #include "langhooks.h"
53 #include "cfglayout.h"
60 #include "tm-constrs.h"
61 #include "sel-sched.h"
63 #include "dwarf2out.h"
66 /* This is used for communication between ASM_OUTPUT_LABEL and
67 ASM_OUTPUT_LABELREF. */
68 int ia64_asm_output_label = 0;
70 /* Register names for ia64_expand_prologue. */
71 static const char * const ia64_reg_numbers[96] =
72 { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
73 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
74 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
75 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
76 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
77 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
78 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
79 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
80 "r96", "r97", "r98", "r99", "r100","r101","r102","r103",
81 "r104","r105","r106","r107","r108","r109","r110","r111",
82 "r112","r113","r114","r115","r116","r117","r118","r119",
83 "r120","r121","r122","r123","r124","r125","r126","r127"};
85 /* ??? These strings could be shared with REGISTER_NAMES. */
86 static const char * const ia64_input_reg_names[8] =
87 { "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7" };
89 /* ??? These strings could be shared with REGISTER_NAMES. */
90 static const char * const ia64_local_reg_names[80] =
91 { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7",
92 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15",
93 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23",
94 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31",
95 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39",
96 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47",
97 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55",
98 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63",
99 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71",
100 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" };
102 /* ??? These strings could be shared with REGISTER_NAMES. */
103 static const char * const ia64_output_reg_names[8] =
104 { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" };
106 /* Determines whether we run our final scheduling pass or not. We always
107 avoid the normal second scheduling pass. */
108 static int ia64_flag_schedule_insns2;
110 /* Determines whether we run variable tracking in machine dependent
112 static int ia64_flag_var_tracking;
114 /* Variables which are this size or smaller are put in the sdata/sbss
117 unsigned int ia64_section_threshold;
119 /* The following variable is used by the DFA insn scheduler. The value is
120 TRUE if we do insn bundling instead of insn scheduling. */
132 number_of_ia64_frame_regs
135 /* Structure to be filled in by ia64_compute_frame_size with register
136 save masks and offsets for the current function. */
138 struct ia64_frame_info
140 HOST_WIDE_INT total_size; /* size of the stack frame, not including
141 the caller's scratch area. */
142 HOST_WIDE_INT spill_cfa_off; /* top of the reg spill area from the cfa. */
143 HOST_WIDE_INT spill_size; /* size of the gr/br/fr spill area. */
144 HOST_WIDE_INT extra_spill_size; /* size of spill area for others. */
145 HARD_REG_SET mask; /* mask of saved registers. */
146 unsigned int gr_used_mask; /* mask of registers in use as gr spill
147 registers or long-term scratches. */
148 int n_spilled; /* number of spilled registers. */
149 int r[number_of_ia64_frame_regs]; /* Frame related registers. */
150 int n_input_regs; /* number of input registers used. */
151 int n_local_regs; /* number of local registers used. */
152 int n_output_regs; /* number of output registers used. */
153 int n_rotate_regs; /* number of rotating registers used. */
155 char need_regstk; /* true if a .regstk directive needed. */
156 char initialized; /* true if the data is finalized. */
159 /* Current frame information calculated by ia64_compute_frame_size. */
160 static struct ia64_frame_info current_frame_info;
161 /* The actual registers that are emitted. */
162 static int emitted_frame_related_regs[number_of_ia64_frame_regs];
164 static int ia64_first_cycle_multipass_dfa_lookahead (void);
165 static void ia64_dependencies_evaluation_hook (rtx, rtx);
166 static void ia64_init_dfa_pre_cycle_insn (void);
167 static rtx ia64_dfa_pre_cycle_insn (void);
168 static int ia64_first_cycle_multipass_dfa_lookahead_guard (rtx);
169 static bool ia64_first_cycle_multipass_dfa_lookahead_guard_spec (const_rtx);
170 static int ia64_dfa_new_cycle (FILE *, int, rtx, int, int, int *);
171 static void ia64_h_i_d_extended (void);
172 static void * ia64_alloc_sched_context (void);
173 static void ia64_init_sched_context (void *, bool);
174 static void ia64_set_sched_context (void *);
175 static void ia64_clear_sched_context (void *);
176 static void ia64_free_sched_context (void *);
177 static int ia64_mode_to_int (enum machine_mode);
178 static void ia64_set_sched_flags (spec_info_t);
179 static ds_t ia64_get_insn_spec_ds (rtx);
180 static ds_t ia64_get_insn_checked_ds (rtx);
181 static bool ia64_skip_rtx_p (const_rtx);
182 static int ia64_speculate_insn (rtx, ds_t, rtx *);
183 static bool ia64_needs_block_p (int);
184 static rtx ia64_gen_spec_check (rtx, rtx, ds_t);
185 static int ia64_spec_check_p (rtx);
186 static int ia64_spec_check_src_p (rtx);
187 static rtx gen_tls_get_addr (void);
188 static rtx gen_thread_pointer (void);
189 static int find_gr_spill (enum ia64_frame_regs, int);
190 static int next_scratch_gr_reg (void);
191 static void mark_reg_gr_used_mask (rtx, void *);
192 static void ia64_compute_frame_size (HOST_WIDE_INT);
193 static void setup_spill_pointers (int, rtx, HOST_WIDE_INT);
194 static void finish_spill_pointers (void);
195 static rtx spill_restore_mem (rtx, HOST_WIDE_INT);
196 static void do_spill (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT, rtx);
197 static void do_restore (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT);
198 static rtx gen_movdi_x (rtx, rtx, rtx);
199 static rtx gen_fr_spill_x (rtx, rtx, rtx);
200 static rtx gen_fr_restore_x (rtx, rtx, rtx);
202 static void ia64_option_override (void);
203 static void ia64_option_default_params (void);
204 static bool ia64_can_eliminate (const int, const int);
205 static enum machine_mode hfa_element_mode (const_tree, bool);
206 static void ia64_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
208 static int ia64_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
210 static rtx ia64_function_arg_1 (const CUMULATIVE_ARGS *, enum machine_mode,
211 const_tree, bool, bool);
212 static rtx ia64_function_arg (CUMULATIVE_ARGS *, enum machine_mode,
214 static rtx ia64_function_incoming_arg (CUMULATIVE_ARGS *,
215 enum machine_mode, const_tree, bool);
216 static void ia64_function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode,
218 static unsigned int ia64_function_arg_boundary (enum machine_mode,
220 static bool ia64_function_ok_for_sibcall (tree, tree);
221 static bool ia64_return_in_memory (const_tree, const_tree);
222 static rtx ia64_function_value (const_tree, const_tree, bool);
223 static rtx ia64_libcall_value (enum machine_mode, const_rtx);
224 static bool ia64_function_value_regno_p (const unsigned int);
225 static int ia64_register_move_cost (enum machine_mode, reg_class_t,
227 static int ia64_memory_move_cost (enum machine_mode mode, reg_class_t,
229 static bool ia64_rtx_costs (rtx, int, int, int *, bool);
230 static int ia64_unspec_may_trap_p (const_rtx, unsigned);
231 static void fix_range (const char *);
232 static bool ia64_handle_option (struct gcc_options *, struct gcc_options *,
233 const struct cl_decoded_option *, location_t);
234 static struct machine_function * ia64_init_machine_status (void);
235 static void emit_insn_group_barriers (FILE *);
236 static void emit_all_insn_group_barriers (FILE *);
237 static void final_emit_insn_group_barriers (FILE *);
238 static void emit_predicate_relation_info (void);
239 static void ia64_reorg (void);
240 static bool ia64_in_small_data_p (const_tree);
241 static void process_epilogue (FILE *, rtx, bool, bool);
243 static bool ia64_assemble_integer (rtx, unsigned int, int);
244 static void ia64_output_function_prologue (FILE *, HOST_WIDE_INT);
245 static void ia64_output_function_epilogue (FILE *, HOST_WIDE_INT);
246 static void ia64_output_function_end_prologue (FILE *);
248 static int ia64_issue_rate (void);
249 static int ia64_adjust_cost_2 (rtx, int, rtx, int, dw_t);
250 static void ia64_sched_init (FILE *, int, int);
251 static void ia64_sched_init_global (FILE *, int, int);
252 static void ia64_sched_finish_global (FILE *, int);
253 static void ia64_sched_finish (FILE *, int);
254 static int ia64_dfa_sched_reorder (FILE *, int, rtx *, int *, int, int);
255 static int ia64_sched_reorder (FILE *, int, rtx *, int *, int);
256 static int ia64_sched_reorder2 (FILE *, int, rtx *, int *, int);
257 static int ia64_variable_issue (FILE *, int, rtx, int);
259 static void ia64_asm_unwind_emit (FILE *, rtx);
260 static void ia64_asm_emit_except_personality (rtx);
261 static void ia64_asm_init_sections (void);
263 static enum unwind_info_type ia64_debug_unwind_info (void);
264 static enum unwind_info_type ia64_except_unwind_info (struct gcc_options *);
266 static struct bundle_state *get_free_bundle_state (void);
267 static void free_bundle_state (struct bundle_state *);
268 static void initiate_bundle_states (void);
269 static void finish_bundle_states (void);
270 static unsigned bundle_state_hash (const void *);
271 static int bundle_state_eq_p (const void *, const void *);
272 static int insert_bundle_state (struct bundle_state *);
273 static void initiate_bundle_state_table (void);
274 static void finish_bundle_state_table (void);
275 static int try_issue_nops (struct bundle_state *, int);
276 static int try_issue_insn (struct bundle_state *, rtx);
277 static void issue_nops_and_insn (struct bundle_state *, int, rtx, int, int);
278 static int get_max_pos (state_t);
279 static int get_template (state_t, int);
281 static rtx get_next_important_insn (rtx, rtx);
282 static bool important_for_bundling_p (rtx);
283 static void bundling (FILE *, int, rtx, rtx);
285 static void ia64_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
286 HOST_WIDE_INT, tree);
287 static void ia64_file_start (void);
288 static void ia64_globalize_decl_name (FILE *, tree);
290 static int ia64_hpux_reloc_rw_mask (void) ATTRIBUTE_UNUSED;
291 static int ia64_reloc_rw_mask (void) ATTRIBUTE_UNUSED;
292 static section *ia64_select_rtx_section (enum machine_mode, rtx,
293 unsigned HOST_WIDE_INT);
294 static void ia64_output_dwarf_dtprel (FILE *, int, rtx)
296 static unsigned int ia64_section_type_flags (tree, const char *, int);
297 static void ia64_init_libfuncs (void)
299 static void ia64_hpux_init_libfuncs (void)
301 static void ia64_sysv4_init_libfuncs (void)
303 static void ia64_vms_init_libfuncs (void)
305 static void ia64_soft_fp_init_libfuncs (void)
307 static bool ia64_vms_valid_pointer_mode (enum machine_mode mode)
309 static tree ia64_vms_common_object_attribute (tree *, tree, tree, int, bool *)
312 static tree ia64_handle_model_attribute (tree *, tree, tree, int, bool *);
313 static tree ia64_handle_version_id_attribute (tree *, tree, tree, int, bool *);
314 static void ia64_encode_section_info (tree, rtx, int);
315 static rtx ia64_struct_value_rtx (tree, int);
316 static tree ia64_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *);
317 static bool ia64_scalar_mode_supported_p (enum machine_mode mode);
318 static bool ia64_vector_mode_supported_p (enum machine_mode mode);
319 static bool ia64_legitimate_constant_p (enum machine_mode, rtx);
320 static bool ia64_cannot_force_const_mem (enum machine_mode, rtx);
321 static const char *ia64_mangle_type (const_tree);
322 static const char *ia64_invalid_conversion (const_tree, const_tree);
323 static const char *ia64_invalid_unary_op (int, const_tree);
324 static const char *ia64_invalid_binary_op (int, const_tree, const_tree);
325 static enum machine_mode ia64_c_mode_for_suffix (char);
326 static enum machine_mode ia64_promote_function_mode (const_tree,
331 static void ia64_trampoline_init (rtx, tree, rtx);
332 static void ia64_override_options_after_change (void);
334 static void ia64_dwarf_handle_frame_unspec (const char *, rtx, int);
335 static tree ia64_builtin_decl (unsigned, bool);
337 static reg_class_t ia64_preferred_reload_class (rtx, reg_class_t);
338 static enum machine_mode ia64_get_reg_raw_mode (int regno);
339 static section * ia64_hpux_function_section (tree, enum node_frequency,
342 /* Table of valid machine attributes. */
343 static const struct attribute_spec ia64_attribute_table[] =
345 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
346 affects_type_identity } */
347 { "syscall_linkage", 0, 0, false, true, true, NULL, false },
348 { "model", 1, 1, true, false, false, ia64_handle_model_attribute,
350 #if TARGET_ABI_OPEN_VMS
351 { "common_object", 1, 1, true, false, false,
352 ia64_vms_common_object_attribute, false },
354 { "version_id", 1, 1, true, false, false,
355 ia64_handle_version_id_attribute, false },
356 { NULL, 0, 0, false, false, false, NULL, false }
359 /* Implement overriding of the optimization options. */
360 static const struct default_options ia64_option_optimization_table[] =
362 { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
363 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
364 SUBTARGET_OPTIMIZATION_OPTIONS,
366 { OPT_LEVELS_NONE, 0, NULL, 0 }
369 /* Initialize the GCC target structure. */
370 #undef TARGET_ATTRIBUTE_TABLE
371 #define TARGET_ATTRIBUTE_TABLE ia64_attribute_table
373 #undef TARGET_INIT_BUILTINS
374 #define TARGET_INIT_BUILTINS ia64_init_builtins
376 #undef TARGET_EXPAND_BUILTIN
377 #define TARGET_EXPAND_BUILTIN ia64_expand_builtin
379 #undef TARGET_BUILTIN_DECL
380 #define TARGET_BUILTIN_DECL ia64_builtin_decl
382 #undef TARGET_ASM_BYTE_OP
383 #define TARGET_ASM_BYTE_OP "\tdata1\t"
384 #undef TARGET_ASM_ALIGNED_HI_OP
385 #define TARGET_ASM_ALIGNED_HI_OP "\tdata2\t"
386 #undef TARGET_ASM_ALIGNED_SI_OP
387 #define TARGET_ASM_ALIGNED_SI_OP "\tdata4\t"
388 #undef TARGET_ASM_ALIGNED_DI_OP
389 #define TARGET_ASM_ALIGNED_DI_OP "\tdata8\t"
390 #undef TARGET_ASM_UNALIGNED_HI_OP
391 #define TARGET_ASM_UNALIGNED_HI_OP "\tdata2.ua\t"
392 #undef TARGET_ASM_UNALIGNED_SI_OP
393 #define TARGET_ASM_UNALIGNED_SI_OP "\tdata4.ua\t"
394 #undef TARGET_ASM_UNALIGNED_DI_OP
395 #define TARGET_ASM_UNALIGNED_DI_OP "\tdata8.ua\t"
396 #undef TARGET_ASM_INTEGER
397 #define TARGET_ASM_INTEGER ia64_assemble_integer
399 #undef TARGET_OPTION_OVERRIDE
400 #define TARGET_OPTION_OVERRIDE ia64_option_override
401 #undef TARGET_OPTION_OPTIMIZATION_TABLE
402 #define TARGET_OPTION_OPTIMIZATION_TABLE ia64_option_optimization_table
403 #undef TARGET_OPTION_DEFAULT_PARAMS
404 #define TARGET_OPTION_DEFAULT_PARAMS ia64_option_default_params
406 #undef TARGET_ASM_FUNCTION_PROLOGUE
407 #define TARGET_ASM_FUNCTION_PROLOGUE ia64_output_function_prologue
408 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
409 #define TARGET_ASM_FUNCTION_END_PROLOGUE ia64_output_function_end_prologue
410 #undef TARGET_ASM_FUNCTION_EPILOGUE
411 #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue
413 #undef TARGET_IN_SMALL_DATA_P
414 #define TARGET_IN_SMALL_DATA_P ia64_in_small_data_p
416 #undef TARGET_SCHED_ADJUST_COST_2
417 #define TARGET_SCHED_ADJUST_COST_2 ia64_adjust_cost_2
418 #undef TARGET_SCHED_ISSUE_RATE
419 #define TARGET_SCHED_ISSUE_RATE ia64_issue_rate
420 #undef TARGET_SCHED_VARIABLE_ISSUE
421 #define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue
422 #undef TARGET_SCHED_INIT
423 #define TARGET_SCHED_INIT ia64_sched_init
424 #undef TARGET_SCHED_FINISH
425 #define TARGET_SCHED_FINISH ia64_sched_finish
426 #undef TARGET_SCHED_INIT_GLOBAL
427 #define TARGET_SCHED_INIT_GLOBAL ia64_sched_init_global
428 #undef TARGET_SCHED_FINISH_GLOBAL
429 #define TARGET_SCHED_FINISH_GLOBAL ia64_sched_finish_global
430 #undef TARGET_SCHED_REORDER
431 #define TARGET_SCHED_REORDER ia64_sched_reorder
432 #undef TARGET_SCHED_REORDER2
433 #define TARGET_SCHED_REORDER2 ia64_sched_reorder2
435 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
436 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ia64_dependencies_evaluation_hook
438 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
439 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ia64_first_cycle_multipass_dfa_lookahead
441 #undef TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN
442 #define TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN ia64_init_dfa_pre_cycle_insn
443 #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN
444 #define TARGET_SCHED_DFA_PRE_CYCLE_INSN ia64_dfa_pre_cycle_insn
446 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
447 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD\
448 ia64_first_cycle_multipass_dfa_lookahead_guard
450 #undef TARGET_SCHED_DFA_NEW_CYCLE
451 #define TARGET_SCHED_DFA_NEW_CYCLE ia64_dfa_new_cycle
453 #undef TARGET_SCHED_H_I_D_EXTENDED
454 #define TARGET_SCHED_H_I_D_EXTENDED ia64_h_i_d_extended
456 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
457 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT ia64_alloc_sched_context
459 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
460 #define TARGET_SCHED_INIT_SCHED_CONTEXT ia64_init_sched_context
462 #undef TARGET_SCHED_SET_SCHED_CONTEXT
463 #define TARGET_SCHED_SET_SCHED_CONTEXT ia64_set_sched_context
465 #undef TARGET_SCHED_CLEAR_SCHED_CONTEXT
466 #define TARGET_SCHED_CLEAR_SCHED_CONTEXT ia64_clear_sched_context
468 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
469 #define TARGET_SCHED_FREE_SCHED_CONTEXT ia64_free_sched_context
471 #undef TARGET_SCHED_SET_SCHED_FLAGS
472 #define TARGET_SCHED_SET_SCHED_FLAGS ia64_set_sched_flags
474 #undef TARGET_SCHED_GET_INSN_SPEC_DS
475 #define TARGET_SCHED_GET_INSN_SPEC_DS ia64_get_insn_spec_ds
477 #undef TARGET_SCHED_GET_INSN_CHECKED_DS
478 #define TARGET_SCHED_GET_INSN_CHECKED_DS ia64_get_insn_checked_ds
480 #undef TARGET_SCHED_SPECULATE_INSN
481 #define TARGET_SCHED_SPECULATE_INSN ia64_speculate_insn
483 #undef TARGET_SCHED_NEEDS_BLOCK_P
484 #define TARGET_SCHED_NEEDS_BLOCK_P ia64_needs_block_p
486 #undef TARGET_SCHED_GEN_SPEC_CHECK
487 #define TARGET_SCHED_GEN_SPEC_CHECK ia64_gen_spec_check
489 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD_SPEC
490 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD_SPEC\
491 ia64_first_cycle_multipass_dfa_lookahead_guard_spec
493 #undef TARGET_SCHED_SKIP_RTX_P
494 #define TARGET_SCHED_SKIP_RTX_P ia64_skip_rtx_p
496 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
497 #define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall
498 #undef TARGET_ARG_PARTIAL_BYTES
499 #define TARGET_ARG_PARTIAL_BYTES ia64_arg_partial_bytes
500 #undef TARGET_FUNCTION_ARG
501 #define TARGET_FUNCTION_ARG ia64_function_arg
502 #undef TARGET_FUNCTION_INCOMING_ARG
503 #define TARGET_FUNCTION_INCOMING_ARG ia64_function_incoming_arg
504 #undef TARGET_FUNCTION_ARG_ADVANCE
505 #define TARGET_FUNCTION_ARG_ADVANCE ia64_function_arg_advance
506 #undef TARGET_FUNCTION_ARG_BOUNDARY
507 #define TARGET_FUNCTION_ARG_BOUNDARY ia64_function_arg_boundary
509 #undef TARGET_ASM_OUTPUT_MI_THUNK
510 #define TARGET_ASM_OUTPUT_MI_THUNK ia64_output_mi_thunk
511 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
512 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
514 #undef TARGET_ASM_FILE_START
515 #define TARGET_ASM_FILE_START ia64_file_start
517 #undef TARGET_ASM_GLOBALIZE_DECL_NAME
518 #define TARGET_ASM_GLOBALIZE_DECL_NAME ia64_globalize_decl_name
520 #undef TARGET_REGISTER_MOVE_COST
521 #define TARGET_REGISTER_MOVE_COST ia64_register_move_cost
522 #undef TARGET_MEMORY_MOVE_COST
523 #define TARGET_MEMORY_MOVE_COST ia64_memory_move_cost
524 #undef TARGET_RTX_COSTS
525 #define TARGET_RTX_COSTS ia64_rtx_costs
526 #undef TARGET_ADDRESS_COST
527 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
529 #undef TARGET_UNSPEC_MAY_TRAP_P
530 #define TARGET_UNSPEC_MAY_TRAP_P ia64_unspec_may_trap_p
532 #undef TARGET_MACHINE_DEPENDENT_REORG
533 #define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg
535 #undef TARGET_ENCODE_SECTION_INFO
536 #define TARGET_ENCODE_SECTION_INFO ia64_encode_section_info
538 #undef TARGET_SECTION_TYPE_FLAGS
539 #define TARGET_SECTION_TYPE_FLAGS ia64_section_type_flags
542 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
543 #define TARGET_ASM_OUTPUT_DWARF_DTPREL ia64_output_dwarf_dtprel
546 #undef TARGET_PROMOTE_FUNCTION_MODE
547 #define TARGET_PROMOTE_FUNCTION_MODE ia64_promote_function_mode
549 /* ??? Investigate. */
551 #undef TARGET_PROMOTE_PROTOTYPES
552 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
555 #undef TARGET_FUNCTION_VALUE
556 #define TARGET_FUNCTION_VALUE ia64_function_value
557 #undef TARGET_LIBCALL_VALUE
558 #define TARGET_LIBCALL_VALUE ia64_libcall_value
559 #undef TARGET_FUNCTION_VALUE_REGNO_P
560 #define TARGET_FUNCTION_VALUE_REGNO_P ia64_function_value_regno_p
562 #undef TARGET_STRUCT_VALUE_RTX
563 #define TARGET_STRUCT_VALUE_RTX ia64_struct_value_rtx
564 #undef TARGET_RETURN_IN_MEMORY
565 #define TARGET_RETURN_IN_MEMORY ia64_return_in_memory
566 #undef TARGET_SETUP_INCOMING_VARARGS
567 #define TARGET_SETUP_INCOMING_VARARGS ia64_setup_incoming_varargs
568 #undef TARGET_STRICT_ARGUMENT_NAMING
569 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
570 #undef TARGET_MUST_PASS_IN_STACK
571 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
572 #undef TARGET_GET_RAW_RESULT_MODE
573 #define TARGET_GET_RAW_RESULT_MODE ia64_get_reg_raw_mode
574 #undef TARGET_GET_RAW_ARG_MODE
575 #define TARGET_GET_RAW_ARG_MODE ia64_get_reg_raw_mode
577 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
578 #define TARGET_GIMPLIFY_VA_ARG_EXPR ia64_gimplify_va_arg
580 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
581 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ia64_dwarf_handle_frame_unspec
582 #undef TARGET_ASM_UNWIND_EMIT
583 #define TARGET_ASM_UNWIND_EMIT ia64_asm_unwind_emit
584 #undef TARGET_ASM_EMIT_EXCEPT_PERSONALITY
585 #define TARGET_ASM_EMIT_EXCEPT_PERSONALITY ia64_asm_emit_except_personality
586 #undef TARGET_ASM_INIT_SECTIONS
587 #define TARGET_ASM_INIT_SECTIONS ia64_asm_init_sections
589 #undef TARGET_DEBUG_UNWIND_INFO
590 #define TARGET_DEBUG_UNWIND_INFO ia64_debug_unwind_info
591 #undef TARGET_EXCEPT_UNWIND_INFO
592 #define TARGET_EXCEPT_UNWIND_INFO ia64_except_unwind_info
594 #undef TARGET_SCALAR_MODE_SUPPORTED_P
595 #define TARGET_SCALAR_MODE_SUPPORTED_P ia64_scalar_mode_supported_p
596 #undef TARGET_VECTOR_MODE_SUPPORTED_P
597 #define TARGET_VECTOR_MODE_SUPPORTED_P ia64_vector_mode_supported_p
599 /* ia64 architecture manual 4.4.7: ... reads, writes, and flushes may occur
600 in an order different from the specified program order. */
601 #undef TARGET_RELAXED_ORDERING
602 #define TARGET_RELAXED_ORDERING true
604 #undef TARGET_DEFAULT_TARGET_FLAGS
605 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | TARGET_CPU_DEFAULT)
606 #undef TARGET_HANDLE_OPTION
607 #define TARGET_HANDLE_OPTION ia64_handle_option
609 #undef TARGET_LEGITIMATE_CONSTANT_P
610 #define TARGET_LEGITIMATE_CONSTANT_P ia64_legitimate_constant_p
612 #undef TARGET_CANNOT_FORCE_CONST_MEM
613 #define TARGET_CANNOT_FORCE_CONST_MEM ia64_cannot_force_const_mem
615 #undef TARGET_MANGLE_TYPE
616 #define TARGET_MANGLE_TYPE ia64_mangle_type
618 #undef TARGET_INVALID_CONVERSION
619 #define TARGET_INVALID_CONVERSION ia64_invalid_conversion
620 #undef TARGET_INVALID_UNARY_OP
621 #define TARGET_INVALID_UNARY_OP ia64_invalid_unary_op
622 #undef TARGET_INVALID_BINARY_OP
623 #define TARGET_INVALID_BINARY_OP ia64_invalid_binary_op
625 #undef TARGET_C_MODE_FOR_SUFFIX
626 #define TARGET_C_MODE_FOR_SUFFIX ia64_c_mode_for_suffix
628 #undef TARGET_CAN_ELIMINATE
629 #define TARGET_CAN_ELIMINATE ia64_can_eliminate
631 #undef TARGET_TRAMPOLINE_INIT
632 #define TARGET_TRAMPOLINE_INIT ia64_trampoline_init
634 #undef TARGET_INVALID_WITHIN_DOLOOP
635 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
637 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
638 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE ia64_override_options_after_change
640 #undef TARGET_PREFERRED_RELOAD_CLASS
641 #define TARGET_PREFERRED_RELOAD_CLASS ia64_preferred_reload_class
643 struct gcc_target targetm = TARGET_INITIALIZER;
647 ADDR_AREA_NORMAL, /* normal address area */
648 ADDR_AREA_SMALL /* addressable by "addl" (-2MB < addr < 2MB) */
652 static GTY(()) tree small_ident1;
653 static GTY(()) tree small_ident2;
658 if (small_ident1 == 0)
660 small_ident1 = get_identifier ("small");
661 small_ident2 = get_identifier ("__small__");
665 /* Retrieve the address area that has been chosen for the given decl. */
667 static ia64_addr_area
668 ia64_get_addr_area (tree decl)
672 model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
678 id = TREE_VALUE (TREE_VALUE (model_attr));
679 if (id == small_ident1 || id == small_ident2)
680 return ADDR_AREA_SMALL;
682 return ADDR_AREA_NORMAL;
686 ia64_handle_model_attribute (tree *node, tree name, tree args,
687 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
689 ia64_addr_area addr_area = ADDR_AREA_NORMAL;
691 tree arg, decl = *node;
694 arg = TREE_VALUE (args);
695 if (arg == small_ident1 || arg == small_ident2)
697 addr_area = ADDR_AREA_SMALL;
701 warning (OPT_Wattributes, "invalid argument of %qE attribute",
703 *no_add_attrs = true;
706 switch (TREE_CODE (decl))
709 if ((DECL_CONTEXT (decl) && TREE_CODE (DECL_CONTEXT (decl))
711 && !TREE_STATIC (decl))
713 error_at (DECL_SOURCE_LOCATION (decl),
714 "an address area attribute cannot be specified for "
716 *no_add_attrs = true;
718 area = ia64_get_addr_area (decl);
719 if (area != ADDR_AREA_NORMAL && addr_area != area)
721 error ("address area of %q+D conflicts with previous "
722 "declaration", decl);
723 *no_add_attrs = true;
728 error_at (DECL_SOURCE_LOCATION (decl),
729 "address area attribute cannot be specified for "
731 *no_add_attrs = true;
735 warning (OPT_Wattributes, "%qE attribute ignored",
737 *no_add_attrs = true;
744 /* The section must have global and overlaid attributes. */
745 #define SECTION_VMS_OVERLAY SECTION_MACH_DEP
747 /* Part of the low level implementation of DEC Ada pragma Common_Object which
748 enables the shared use of variables stored in overlaid linker areas
749 corresponding to the use of Fortran COMMON. */
752 ia64_vms_common_object_attribute (tree *node, tree name, tree args,
753 int flags ATTRIBUTE_UNUSED,
761 DECL_COMMON (decl) = 1;
762 id = TREE_VALUE (args);
763 if (TREE_CODE (id) == IDENTIFIER_NODE)
764 val = build_string (IDENTIFIER_LENGTH (id), IDENTIFIER_POINTER (id));
765 else if (TREE_CODE (id) == STRING_CST)
769 warning (OPT_Wattributes,
770 "%qE attribute requires a string constant argument", name);
771 *no_add_attrs = true;
774 DECL_SECTION_NAME (decl) = val;
778 /* Part of the low level implementation of DEC Ada pragma Common_Object. */
781 ia64_vms_output_aligned_decl_common (FILE *file, tree decl, const char *name,
782 unsigned HOST_WIDE_INT size,
785 tree attr = DECL_ATTRIBUTES (decl);
787 /* As common_object attribute set DECL_SECTION_NAME check it before
788 looking up the attribute. */
789 if (DECL_SECTION_NAME (decl) && attr)
790 attr = lookup_attribute ("common_object", attr);
796 /* Code from elfos.h. */
797 fprintf (file, "%s", COMMON_ASM_OP);
798 assemble_name (file, name);
799 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
800 size, align / BITS_PER_UNIT);
804 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
805 ASM_OUTPUT_LABEL (file, name);
806 ASM_OUTPUT_SKIP (file, size ? size : 1);
810 /* Definition of TARGET_ASM_NAMED_SECTION for VMS. */
813 ia64_vms_elf_asm_named_section (const char *name, unsigned int flags,
816 if (!(flags & SECTION_VMS_OVERLAY))
818 default_elf_asm_named_section (name, flags, decl);
821 if (flags != (SECTION_VMS_OVERLAY | SECTION_WRITE))
824 if (flags & SECTION_DECLARED)
826 fprintf (asm_out_file, "\t.section\t%s\n", name);
830 fprintf (asm_out_file, "\t.section\t%s,\"awgO\"\n", name);
834 ia64_encode_addr_area (tree decl, rtx symbol)
838 flags = SYMBOL_REF_FLAGS (symbol);
839 switch (ia64_get_addr_area (decl))
841 case ADDR_AREA_NORMAL: break;
842 case ADDR_AREA_SMALL: flags |= SYMBOL_FLAG_SMALL_ADDR; break;
843 default: gcc_unreachable ();
845 SYMBOL_REF_FLAGS (symbol) = flags;
849 ia64_encode_section_info (tree decl, rtx rtl, int first)
851 default_encode_section_info (decl, rtl, first);
853 /* Careful not to prod global register variables. */
854 if (TREE_CODE (decl) == VAR_DECL
855 && GET_CODE (DECL_RTL (decl)) == MEM
856 && GET_CODE (XEXP (DECL_RTL (decl), 0)) == SYMBOL_REF
857 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
858 ia64_encode_addr_area (decl, XEXP (rtl, 0));
861 /* Return 1 if the operands of a move are ok. */
864 ia64_move_ok (rtx dst, rtx src)
866 /* If we're under init_recog_no_volatile, we'll not be able to use
867 memory_operand. So check the code directly and don't worry about
868 the validity of the underlying address, which should have been
869 checked elsewhere anyway. */
870 if (GET_CODE (dst) != MEM)
872 if (GET_CODE (src) == MEM)
874 if (register_operand (src, VOIDmode))
877 /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0. */
878 if (INTEGRAL_MODE_P (GET_MODE (dst)))
879 return src == const0_rtx;
881 return satisfies_constraint_G (src);
884 /* Return 1 if the operands are ok for a floating point load pair. */
887 ia64_load_pair_ok (rtx dst, rtx src)
889 if (GET_CODE (dst) != REG || !FP_REGNO_P (REGNO (dst)))
891 if (GET_CODE (src) != MEM || MEM_VOLATILE_P (src))
893 switch (GET_CODE (XEXP (src, 0)))
902 rtx adjust = XEXP (XEXP (XEXP (src, 0), 1), 1);
904 if (GET_CODE (adjust) != CONST_INT
905 || INTVAL (adjust) != GET_MODE_SIZE (GET_MODE (src)))
916 addp4_optimize_ok (rtx op1, rtx op2)
918 return (basereg_operand (op1, GET_MODE(op1)) !=
919 basereg_operand (op2, GET_MODE(op2)));
922 /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction.
923 Return the length of the field, or <= 0 on failure. */
926 ia64_depz_field_mask (rtx rop, rtx rshift)
928 unsigned HOST_WIDE_INT op = INTVAL (rop);
929 unsigned HOST_WIDE_INT shift = INTVAL (rshift);
931 /* Get rid of the zero bits we're shifting in. */
934 /* We must now have a solid block of 1's at bit 0. */
935 return exact_log2 (op + 1);
938 /* Return the TLS model to use for ADDR. */
940 static enum tls_model
941 tls_symbolic_operand_type (rtx addr)
943 enum tls_model tls_kind = TLS_MODEL_NONE;
945 if (GET_CODE (addr) == CONST)
947 if (GET_CODE (XEXP (addr, 0)) == PLUS
948 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF)
949 tls_kind = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (addr, 0), 0));
951 else if (GET_CODE (addr) == SYMBOL_REF)
952 tls_kind = SYMBOL_REF_TLS_MODEL (addr);
957 /* Return true if X is a constant that is valid for some immediate
958 field in an instruction. */
961 ia64_legitimate_constant_p (enum machine_mode mode, rtx x)
963 switch (GET_CODE (x))
970 if (GET_MODE (x) == VOIDmode || mode == SFmode || mode == DFmode)
972 return satisfies_constraint_G (x);
976 /* ??? Short term workaround for PR 28490. We must make the code here
977 match the code in ia64_expand_move and move_operand, even though they
978 are both technically wrong. */
979 if (tls_symbolic_operand_type (x) == 0)
981 HOST_WIDE_INT addend = 0;
984 if (GET_CODE (op) == CONST
985 && GET_CODE (XEXP (op, 0)) == PLUS
986 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
988 addend = INTVAL (XEXP (XEXP (op, 0), 1));
989 op = XEXP (XEXP (op, 0), 0);
992 if (any_offset_symbol_operand (op, mode)
993 || function_operand (op, mode))
995 if (aligned_offset_symbol_operand (op, mode))
996 return (addend & 0x3fff) == 0;
1002 if (mode == V2SFmode)
1003 return satisfies_constraint_Y (x);
1005 return (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
1006 && GET_MODE_SIZE (mode) <= 8);
1013 /* Don't allow TLS addresses to get spilled to memory. */
1016 ia64_cannot_force_const_mem (enum machine_mode mode, rtx x)
1020 return tls_symbolic_operand_type (x) != 0;
1023 /* Expand a symbolic constant load. */
1026 ia64_expand_load_address (rtx dest, rtx src)
1028 gcc_assert (GET_CODE (dest) == REG);
1030 /* ILP32 mode still loads 64-bits of data from the GOT. This avoids
1031 having to pointer-extend the value afterward. Other forms of address
1032 computation below are also more natural to compute as 64-bit quantities.
1033 If we've been given an SImode destination register, change it. */
1034 if (GET_MODE (dest) != Pmode)
1035 dest = gen_rtx_REG_offset (dest, Pmode, REGNO (dest),
1036 byte_lowpart_offset (Pmode, GET_MODE (dest)));
1040 if (small_addr_symbolic_operand (src, VOIDmode))
1043 if (TARGET_AUTO_PIC)
1044 emit_insn (gen_load_gprel64 (dest, src));
1045 else if (GET_CODE (src) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (src))
1046 emit_insn (gen_load_fptr (dest, src));
1047 else if (sdata_symbolic_operand (src, VOIDmode))
1048 emit_insn (gen_load_gprel (dest, src));
1051 HOST_WIDE_INT addend = 0;
1054 /* We did split constant offsets in ia64_expand_move, and we did try
1055 to keep them split in move_operand, but we also allowed reload to
1056 rematerialize arbitrary constants rather than spill the value to
1057 the stack and reload it. So we have to be prepared here to split
1058 them apart again. */
1059 if (GET_CODE (src) == CONST)
1061 HOST_WIDE_INT hi, lo;
1063 hi = INTVAL (XEXP (XEXP (src, 0), 1));
1064 lo = ((hi & 0x3fff) ^ 0x2000) - 0x2000;
1070 src = plus_constant (XEXP (XEXP (src, 0), 0), hi);
1074 tmp = gen_rtx_HIGH (Pmode, src);
1075 tmp = gen_rtx_PLUS (Pmode, tmp, pic_offset_table_rtx);
1076 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
1078 tmp = gen_rtx_LO_SUM (Pmode, dest, src);
1079 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
1083 tmp = gen_rtx_PLUS (Pmode, dest, GEN_INT (addend));
1084 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
1091 static GTY(()) rtx gen_tls_tga;
1093 gen_tls_get_addr (void)
1096 gen_tls_tga = init_one_libfunc ("__tls_get_addr");
1100 static GTY(()) rtx thread_pointer_rtx;
1102 gen_thread_pointer (void)
1104 if (!thread_pointer_rtx)
1105 thread_pointer_rtx = gen_rtx_REG (Pmode, 13);
1106 return thread_pointer_rtx;
1110 ia64_expand_tls_address (enum tls_model tls_kind, rtx op0, rtx op1,
1111 rtx orig_op1, HOST_WIDE_INT addend)
1113 rtx tga_op1, tga_op2, tga_ret, tga_eqv, tmp, insns;
1115 HOST_WIDE_INT addend_lo, addend_hi;
1119 case TLS_MODEL_GLOBAL_DYNAMIC:
1122 tga_op1 = gen_reg_rtx (Pmode);
1123 emit_insn (gen_load_dtpmod (tga_op1, op1));
1125 tga_op2 = gen_reg_rtx (Pmode);
1126 emit_insn (gen_load_dtprel (tga_op2, op1));
1128 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
1129 LCT_CONST, Pmode, 2, tga_op1,
1130 Pmode, tga_op2, Pmode);
1132 insns = get_insns ();
1135 if (GET_MODE (op0) != Pmode)
1137 emit_libcall_block (insns, op0, tga_ret, op1);
1140 case TLS_MODEL_LOCAL_DYNAMIC:
1141 /* ??? This isn't the completely proper way to do local-dynamic
1142 If the call to __tls_get_addr is used only by a single symbol,
1143 then we should (somehow) move the dtprel to the second arg
1144 to avoid the extra add. */
1147 tga_op1 = gen_reg_rtx (Pmode);
1148 emit_insn (gen_load_dtpmod (tga_op1, op1));
1150 tga_op2 = const0_rtx;
1152 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
1153 LCT_CONST, Pmode, 2, tga_op1,
1154 Pmode, tga_op2, Pmode);
1156 insns = get_insns ();
1159 tga_eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
1161 tmp = gen_reg_rtx (Pmode);
1162 emit_libcall_block (insns, tmp, tga_ret, tga_eqv);
1164 if (!register_operand (op0, Pmode))
1165 op0 = gen_reg_rtx (Pmode);
1168 emit_insn (gen_load_dtprel (op0, op1));
1169 emit_insn (gen_adddi3 (op0, tmp, op0));
1172 emit_insn (gen_add_dtprel (op0, op1, tmp));
1175 case TLS_MODEL_INITIAL_EXEC:
1176 addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000;
1177 addend_hi = addend - addend_lo;
1179 op1 = plus_constant (op1, addend_hi);
1182 tmp = gen_reg_rtx (Pmode);
1183 emit_insn (gen_load_tprel (tmp, op1));
1185 if (!register_operand (op0, Pmode))
1186 op0 = gen_reg_rtx (Pmode);
1187 emit_insn (gen_adddi3 (op0, tmp, gen_thread_pointer ()));
1190 case TLS_MODEL_LOCAL_EXEC:
1191 if (!register_operand (op0, Pmode))
1192 op0 = gen_reg_rtx (Pmode);
1198 emit_insn (gen_load_tprel (op0, op1));
1199 emit_insn (gen_adddi3 (op0, op0, gen_thread_pointer ()));
1202 emit_insn (gen_add_tprel (op0, op1, gen_thread_pointer ()));
1210 op0 = expand_simple_binop (Pmode, PLUS, op0, GEN_INT (addend),
1211 orig_op0, 1, OPTAB_DIRECT);
1212 if (orig_op0 == op0)
1214 if (GET_MODE (orig_op0) == Pmode)
1216 return gen_lowpart (GET_MODE (orig_op0), op0);
1220 ia64_expand_move (rtx op0, rtx op1)
1222 enum machine_mode mode = GET_MODE (op0);
1224 if (!reload_in_progress && !reload_completed && !ia64_move_ok (op0, op1))
1225 op1 = force_reg (mode, op1);
1227 if ((mode == Pmode || mode == ptr_mode) && symbolic_operand (op1, VOIDmode))
1229 HOST_WIDE_INT addend = 0;
1230 enum tls_model tls_kind;
1233 if (GET_CODE (op1) == CONST
1234 && GET_CODE (XEXP (op1, 0)) == PLUS
1235 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT)
1237 addend = INTVAL (XEXP (XEXP (op1, 0), 1));
1238 sym = XEXP (XEXP (op1, 0), 0);
1241 tls_kind = tls_symbolic_operand_type (sym);
1243 return ia64_expand_tls_address (tls_kind, op0, sym, op1, addend);
1245 if (any_offset_symbol_operand (sym, mode))
1247 else if (aligned_offset_symbol_operand (sym, mode))
1249 HOST_WIDE_INT addend_lo, addend_hi;
1251 addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000;
1252 addend_hi = addend - addend_lo;
1256 op1 = plus_constant (sym, addend_hi);
1265 if (reload_completed)
1267 /* We really should have taken care of this offset earlier. */
1268 gcc_assert (addend == 0);
1269 if (ia64_expand_load_address (op0, op1))
1275 rtx subtarget = !can_create_pseudo_p () ? op0 : gen_reg_rtx (mode);
1277 emit_insn (gen_rtx_SET (VOIDmode, subtarget, op1));
1279 op1 = expand_simple_binop (mode, PLUS, subtarget,
1280 GEN_INT (addend), op0, 1, OPTAB_DIRECT);
1289 /* Split a move from OP1 to OP0 conditional on COND. */
1292 ia64_emit_cond_move (rtx op0, rtx op1, rtx cond)
1294 rtx insn, first = get_last_insn ();
1296 emit_move_insn (op0, op1);
1298 for (insn = get_last_insn (); insn != first; insn = PREV_INSN (insn))
1300 PATTERN (insn) = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond),
1304 /* Split a post-reload TImode or TFmode reference into two DImode
1305 components. This is made extra difficult by the fact that we do
1306 not get any scratch registers to work with, because reload cannot
1307 be prevented from giving us a scratch that overlaps the register
1308 pair involved. So instead, when addressing memory, we tweak the
1309 pointer register up and back down with POST_INCs. Or up and not
1310 back down when we can get away with it.
1312 REVERSED is true when the loads must be done in reversed order
1313 (high word first) for correctness. DEAD is true when the pointer
1314 dies with the second insn we generate and therefore the second
1315 address must not carry a postmodify.
1317 May return an insn which is to be emitted after the moves. */
1320 ia64_split_tmode (rtx out[2], rtx in, bool reversed, bool dead)
1324 switch (GET_CODE (in))
1327 out[reversed] = gen_rtx_REG (DImode, REGNO (in));
1328 out[!reversed] = gen_rtx_REG (DImode, REGNO (in) + 1);
1333 /* Cannot occur reversed. */
1334 gcc_assert (!reversed);
1336 if (GET_MODE (in) != TFmode)
1337 split_double (in, &out[0], &out[1]);
1339 /* split_double does not understand how to split a TFmode
1340 quantity into a pair of DImode constants. */
1343 unsigned HOST_WIDE_INT p[2];
1344 long l[4]; /* TFmode is 128 bits */
1346 REAL_VALUE_FROM_CONST_DOUBLE (r, in);
1347 real_to_target (l, &r, TFmode);
1349 if (FLOAT_WORDS_BIG_ENDIAN)
1351 p[0] = (((unsigned HOST_WIDE_INT) l[0]) << 32) + l[1];
1352 p[1] = (((unsigned HOST_WIDE_INT) l[2]) << 32) + l[3];
1356 p[0] = (((unsigned HOST_WIDE_INT) l[1]) << 32) + l[0];
1357 p[1] = (((unsigned HOST_WIDE_INT) l[3]) << 32) + l[2];
1359 out[0] = GEN_INT (p[0]);
1360 out[1] = GEN_INT (p[1]);
1366 rtx base = XEXP (in, 0);
1369 switch (GET_CODE (base))
1374 out[0] = adjust_automodify_address
1375 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1376 out[1] = adjust_automodify_address
1377 (in, DImode, dead ? 0 : gen_rtx_POST_DEC (Pmode, base), 8);
1381 /* Reversal requires a pre-increment, which can only
1382 be done as a separate insn. */
1383 emit_insn (gen_adddi3 (base, base, GEN_INT (8)));
1384 out[0] = adjust_automodify_address
1385 (in, DImode, gen_rtx_POST_DEC (Pmode, base), 8);
1386 out[1] = adjust_address (in, DImode, 0);
1391 gcc_assert (!reversed && !dead);
1393 /* Just do the increment in two steps. */
1394 out[0] = adjust_automodify_address (in, DImode, 0, 0);
1395 out[1] = adjust_automodify_address (in, DImode, 0, 8);
1399 gcc_assert (!reversed && !dead);
1401 /* Add 8, subtract 24. */
1402 base = XEXP (base, 0);
1403 out[0] = adjust_automodify_address
1404 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1405 out[1] = adjust_automodify_address
1407 gen_rtx_POST_MODIFY (Pmode, base, plus_constant (base, -24)),
1412 gcc_assert (!reversed && !dead);
1414 /* Extract and adjust the modification. This case is
1415 trickier than the others, because we might have an
1416 index register, or we might have a combined offset that
1417 doesn't fit a signed 9-bit displacement field. We can
1418 assume the incoming expression is already legitimate. */
1419 offset = XEXP (base, 1);
1420 base = XEXP (base, 0);
1422 out[0] = adjust_automodify_address
1423 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1425 if (GET_CODE (XEXP (offset, 1)) == REG)
1427 /* Can't adjust the postmodify to match. Emit the
1428 original, then a separate addition insn. */
1429 out[1] = adjust_automodify_address (in, DImode, 0, 8);
1430 fixup = gen_adddi3 (base, base, GEN_INT (-8));
1434 gcc_assert (GET_CODE (XEXP (offset, 1)) == CONST_INT);
1435 if (INTVAL (XEXP (offset, 1)) < -256 + 8)
1437 /* Again the postmodify cannot be made to match,
1438 but in this case it's more efficient to get rid
1439 of the postmodify entirely and fix up with an
1441 out[1] = adjust_automodify_address (in, DImode, base, 8);
1443 (base, base, GEN_INT (INTVAL (XEXP (offset, 1)) - 8));
1447 /* Combined offset still fits in the displacement field.
1448 (We cannot overflow it at the high end.) */
1449 out[1] = adjust_automodify_address
1450 (in, DImode, gen_rtx_POST_MODIFY
1451 (Pmode, base, gen_rtx_PLUS
1453 GEN_INT (INTVAL (XEXP (offset, 1)) - 8))),
1472 /* Split a TImode or TFmode move instruction after reload.
1473 This is used by *movtf_internal and *movti_internal. */
1475 ia64_split_tmode_move (rtx operands[])
1477 rtx in[2], out[2], insn;
1480 bool reversed = false;
1482 /* It is possible for reload to decide to overwrite a pointer with
1483 the value it points to. In that case we have to do the loads in
1484 the appropriate order so that the pointer is not destroyed too
1485 early. Also we must not generate a postmodify for that second
1486 load, or rws_access_regno will die. */
1487 if (GET_CODE (operands[1]) == MEM
1488 && reg_overlap_mentioned_p (operands[0], operands[1]))
1490 rtx base = XEXP (operands[1], 0);
1491 while (GET_CODE (base) != REG)
1492 base = XEXP (base, 0);
1494 if (REGNO (base) == REGNO (operands[0]))
1498 /* Another reason to do the moves in reversed order is if the first
1499 element of the target register pair is also the second element of
1500 the source register pair. */
1501 if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
1502 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
1505 fixup[0] = ia64_split_tmode (in, operands[1], reversed, dead);
1506 fixup[1] = ia64_split_tmode (out, operands[0], reversed, dead);
1508 #define MAYBE_ADD_REG_INC_NOTE(INSN, EXP) \
1509 if (GET_CODE (EXP) == MEM \
1510 && (GET_CODE (XEXP (EXP, 0)) == POST_MODIFY \
1511 || GET_CODE (XEXP (EXP, 0)) == POST_INC \
1512 || GET_CODE (XEXP (EXP, 0)) == POST_DEC)) \
1513 add_reg_note (insn, REG_INC, XEXP (XEXP (EXP, 0), 0))
1515 insn = emit_insn (gen_rtx_SET (VOIDmode, out[0], in[0]));
1516 MAYBE_ADD_REG_INC_NOTE (insn, in[0]);
1517 MAYBE_ADD_REG_INC_NOTE (insn, out[0]);
1519 insn = emit_insn (gen_rtx_SET (VOIDmode, out[1], in[1]));
1520 MAYBE_ADD_REG_INC_NOTE (insn, in[1]);
1521 MAYBE_ADD_REG_INC_NOTE (insn, out[1]);
1524 emit_insn (fixup[0]);
1526 emit_insn (fixup[1]);
1528 #undef MAYBE_ADD_REG_INC_NOTE
1531 /* ??? Fixing GR->FR XFmode moves during reload is hard. You need to go
1532 through memory plus an extra GR scratch register. Except that you can
1533 either get the first from SECONDARY_MEMORY_NEEDED or the second from
1534 SECONDARY_RELOAD_CLASS, but not both.
1536 We got into problems in the first place by allowing a construct like
1537 (subreg:XF (reg:TI)), which we got from a union containing a long double.
1538 This solution attempts to prevent this situation from occurring. When
1539 we see something like the above, we spill the inner register to memory. */
1542 spill_xfmode_rfmode_operand (rtx in, int force, enum machine_mode mode)
1544 if (GET_CODE (in) == SUBREG
1545 && GET_MODE (SUBREG_REG (in)) == TImode
1546 && GET_CODE (SUBREG_REG (in)) == REG)
1548 rtx memt = assign_stack_temp (TImode, 16, 0);
1549 emit_move_insn (memt, SUBREG_REG (in));
1550 return adjust_address (memt, mode, 0);
1552 else if (force && GET_CODE (in) == REG)
1554 rtx memx = assign_stack_temp (mode, 16, 0);
1555 emit_move_insn (memx, in);
1562 /* Expand the movxf or movrf pattern (MODE says which) with the given
1563 OPERANDS, returning true if the pattern should then invoke
1567 ia64_expand_movxf_movrf (enum machine_mode mode, rtx operands[])
1569 rtx op0 = operands[0];
1571 if (GET_CODE (op0) == SUBREG)
1572 op0 = SUBREG_REG (op0);
1574 /* We must support XFmode loads into general registers for stdarg/vararg,
1575 unprototyped calls, and a rare case where a long double is passed as
1576 an argument after a float HFA fills the FP registers. We split them into
1577 DImode loads for convenience. We also need to support XFmode stores
1578 for the last case. This case does not happen for stdarg/vararg routines,
1579 because we do a block store to memory of unnamed arguments. */
1581 if (GET_CODE (op0) == REG && GR_REGNO_P (REGNO (op0)))
1585 /* We're hoping to transform everything that deals with XFmode
1586 quantities and GR registers early in the compiler. */
1587 gcc_assert (can_create_pseudo_p ());
1589 /* Struct to register can just use TImode instead. */
1590 if ((GET_CODE (operands[1]) == SUBREG
1591 && GET_MODE (SUBREG_REG (operands[1])) == TImode)
1592 || (GET_CODE (operands[1]) == REG
1593 && GR_REGNO_P (REGNO (operands[1]))))
1595 rtx op1 = operands[1];
1597 if (GET_CODE (op1) == SUBREG)
1598 op1 = SUBREG_REG (op1);
1600 op1 = gen_rtx_REG (TImode, REGNO (op1));
1602 emit_move_insn (gen_rtx_REG (TImode, REGNO (op0)), op1);
1606 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1608 /* Don't word-swap when reading in the constant. */
1609 emit_move_insn (gen_rtx_REG (DImode, REGNO (op0)),
1610 operand_subword (operands[1], WORDS_BIG_ENDIAN,
1612 emit_move_insn (gen_rtx_REG (DImode, REGNO (op0) + 1),
1613 operand_subword (operands[1], !WORDS_BIG_ENDIAN,
1618 /* If the quantity is in a register not known to be GR, spill it. */
1619 if (register_operand (operands[1], mode))
1620 operands[1] = spill_xfmode_rfmode_operand (operands[1], 1, mode);
1622 gcc_assert (GET_CODE (operands[1]) == MEM);
1624 /* Don't word-swap when reading in the value. */
1625 out[0] = gen_rtx_REG (DImode, REGNO (op0));
1626 out[1] = gen_rtx_REG (DImode, REGNO (op0) + 1);
1628 emit_move_insn (out[0], adjust_address (operands[1], DImode, 0));
1629 emit_move_insn (out[1], adjust_address (operands[1], DImode, 8));
1633 if (GET_CODE (operands[1]) == REG && GR_REGNO_P (REGNO (operands[1])))
1635 /* We're hoping to transform everything that deals with XFmode
1636 quantities and GR registers early in the compiler. */
1637 gcc_assert (can_create_pseudo_p ());
1639 /* Op0 can't be a GR_REG here, as that case is handled above.
1640 If op0 is a register, then we spill op1, so that we now have a
1641 MEM operand. This requires creating an XFmode subreg of a TImode reg
1642 to force the spill. */
1643 if (register_operand (operands[0], mode))
1645 rtx op1 = gen_rtx_REG (TImode, REGNO (operands[1]));
1646 op1 = gen_rtx_SUBREG (mode, op1, 0);
1647 operands[1] = spill_xfmode_rfmode_operand (op1, 0, mode);
1654 gcc_assert (GET_CODE (operands[0]) == MEM);
1656 /* Don't word-swap when writing out the value. */
1657 in[0] = gen_rtx_REG (DImode, REGNO (operands[1]));
1658 in[1] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1);
1660 emit_move_insn (adjust_address (operands[0], DImode, 0), in[0]);
1661 emit_move_insn (adjust_address (operands[0], DImode, 8), in[1]);
1666 if (!reload_in_progress && !reload_completed)
1668 operands[1] = spill_xfmode_rfmode_operand (operands[1], 0, mode);
1670 if (GET_MODE (op0) == TImode && GET_CODE (op0) == REG)
1672 rtx memt, memx, in = operands[1];
1673 if (CONSTANT_P (in))
1674 in = validize_mem (force_const_mem (mode, in));
1675 if (GET_CODE (in) == MEM)
1676 memt = adjust_address (in, TImode, 0);
1679 memt = assign_stack_temp (TImode, 16, 0);
1680 memx = adjust_address (memt, mode, 0);
1681 emit_move_insn (memx, in);
1683 emit_move_insn (op0, memt);
1687 if (!ia64_move_ok (operands[0], operands[1]))
1688 operands[1] = force_reg (mode, operands[1]);
1694 /* Emit comparison instruction if necessary, replacing *EXPR, *OP0, *OP1
1695 with the expression that holds the compare result (in VOIDmode). */
1697 static GTY(()) rtx cmptf_libfunc;
1700 ia64_expand_compare (rtx *expr, rtx *op0, rtx *op1)
1702 enum rtx_code code = GET_CODE (*expr);
1705 /* If we have a BImode input, then we already have a compare result, and
1706 do not need to emit another comparison. */
1707 if (GET_MODE (*op0) == BImode)
1709 gcc_assert ((code == NE || code == EQ) && *op1 == const0_rtx);
1712 /* HPUX TFmode compare requires a library call to _U_Qfcmp, which takes a
1713 magic number as its third argument, that indicates what to do.
1714 The return value is an integer to be compared against zero. */
1715 else if (TARGET_HPUX && GET_MODE (*op0) == TFmode)
1718 QCMP_INV = 1, /* Raise FP_INVALID on SNaN as a side effect. */
1725 enum rtx_code ncode;
1728 gcc_assert (cmptf_libfunc && GET_MODE (*op1) == TFmode);
1731 /* 1 = equal, 0 = not equal. Equality operators do
1732 not raise FP_INVALID when given an SNaN operand. */
1733 case EQ: magic = QCMP_EQ; ncode = NE; break;
1734 case NE: magic = QCMP_EQ; ncode = EQ; break;
1735 /* isunordered() from C99. */
1736 case UNORDERED: magic = QCMP_UNORD; ncode = NE; break;
1737 case ORDERED: magic = QCMP_UNORD; ncode = EQ; break;
1738 /* Relational operators raise FP_INVALID when given
1740 case LT: magic = QCMP_LT |QCMP_INV; ncode = NE; break;
1741 case LE: magic = QCMP_LT|QCMP_EQ|QCMP_INV; ncode = NE; break;
1742 case GT: magic = QCMP_GT |QCMP_INV; ncode = NE; break;
1743 case GE: magic = QCMP_GT|QCMP_EQ|QCMP_INV; ncode = NE; break;
1744 /* FUTURE: Implement UNEQ, UNLT, UNLE, UNGT, UNGE, LTGT.
1745 Expanders for buneq etc. weuld have to be added to ia64.md
1746 for this to be useful. */
1747 default: gcc_unreachable ();
1752 ret = emit_library_call_value (cmptf_libfunc, 0, LCT_CONST, DImode, 3,
1753 *op0, TFmode, *op1, TFmode,
1754 GEN_INT (magic), DImode);
1755 cmp = gen_reg_rtx (BImode);
1756 emit_insn (gen_rtx_SET (VOIDmode, cmp,
1757 gen_rtx_fmt_ee (ncode, BImode,
1760 insns = get_insns ();
1763 emit_libcall_block (insns, cmp, cmp,
1764 gen_rtx_fmt_ee (code, BImode, *op0, *op1));
1769 cmp = gen_reg_rtx (BImode);
1770 emit_insn (gen_rtx_SET (VOIDmode, cmp,
1771 gen_rtx_fmt_ee (code, BImode, *op0, *op1)));
1775 *expr = gen_rtx_fmt_ee (code, VOIDmode, cmp, const0_rtx);
1780 /* Generate an integral vector comparison. Return true if the condition has
1781 been reversed, and so the sense of the comparison should be inverted. */
1784 ia64_expand_vecint_compare (enum rtx_code code, enum machine_mode mode,
1785 rtx dest, rtx op0, rtx op1)
1787 bool negate = false;
1790 /* Canonicalize the comparison to EQ, GT, GTU. */
1801 code = reverse_condition (code);
1807 code = reverse_condition (code);
1813 code = swap_condition (code);
1814 x = op0, op0 = op1, op1 = x;
1821 /* Unsigned parallel compare is not supported by the hardware. Play some
1822 tricks to turn this into a signed comparison against 0. */
1831 /* Subtract (-(INT MAX) - 1) from both operands to make
1833 mask = GEN_INT (0x80000000);
1834 mask = gen_rtx_CONST_VECTOR (V2SImode, gen_rtvec (2, mask, mask));
1835 mask = force_reg (mode, mask);
1836 t1 = gen_reg_rtx (mode);
1837 emit_insn (gen_subv2si3 (t1, op0, mask));
1838 t2 = gen_reg_rtx (mode);
1839 emit_insn (gen_subv2si3 (t2, op1, mask));
1848 /* Perform a parallel unsigned saturating subtraction. */
1849 x = gen_reg_rtx (mode);
1850 emit_insn (gen_rtx_SET (VOIDmode, x,
1851 gen_rtx_US_MINUS (mode, op0, op1)));
1855 op1 = CONST0_RTX (mode);
1864 x = gen_rtx_fmt_ee (code, mode, op0, op1);
1865 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
1870 /* Emit an integral vector conditional move. */
1873 ia64_expand_vecint_cmov (rtx operands[])
1875 enum machine_mode mode = GET_MODE (operands[0]);
1876 enum rtx_code code = GET_CODE (operands[3]);
1880 cmp = gen_reg_rtx (mode);
1881 negate = ia64_expand_vecint_compare (code, mode, cmp,
1882 operands[4], operands[5]);
1884 ot = operands[1+negate];
1885 of = operands[2-negate];
1887 if (ot == CONST0_RTX (mode))
1889 if (of == CONST0_RTX (mode))
1891 emit_move_insn (operands[0], ot);
1895 x = gen_rtx_NOT (mode, cmp);
1896 x = gen_rtx_AND (mode, x, of);
1897 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1899 else if (of == CONST0_RTX (mode))
1901 x = gen_rtx_AND (mode, cmp, ot);
1902 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1908 t = gen_reg_rtx (mode);
1909 x = gen_rtx_AND (mode, cmp, operands[1+negate]);
1910 emit_insn (gen_rtx_SET (VOIDmode, t, x));
1912 f = gen_reg_rtx (mode);
1913 x = gen_rtx_NOT (mode, cmp);
1914 x = gen_rtx_AND (mode, x, operands[2-negate]);
1915 emit_insn (gen_rtx_SET (VOIDmode, f, x));
1917 x = gen_rtx_IOR (mode, t, f);
1918 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1922 /* Emit an integral vector min or max operation. Return true if all done. */
1925 ia64_expand_vecint_minmax (enum rtx_code code, enum machine_mode mode,
1930 /* These four combinations are supported directly. */
1931 if (mode == V8QImode && (code == UMIN || code == UMAX))
1933 if (mode == V4HImode && (code == SMIN || code == SMAX))
1936 /* This combination can be implemented with only saturating subtraction. */
1937 if (mode == V4HImode && code == UMAX)
1939 rtx x, tmp = gen_reg_rtx (mode);
1941 x = gen_rtx_US_MINUS (mode, operands[1], operands[2]);
1942 emit_insn (gen_rtx_SET (VOIDmode, tmp, x));
1944 emit_insn (gen_addv4hi3 (operands[0], tmp, operands[2]));
1948 /* Everything else implemented via vector comparisons. */
1949 xops[0] = operands[0];
1950 xops[4] = xops[1] = operands[1];
1951 xops[5] = xops[2] = operands[2];
1970 xops[3] = gen_rtx_fmt_ee (code, VOIDmode, operands[1], operands[2]);
1972 ia64_expand_vecint_cmov (xops);
1976 /* The vectors LO and HI each contain N halves of a double-wide vector.
1977 Reassemble either the first N/2 or the second N/2 elements. */
1980 ia64_unpack_assemble (rtx out, rtx lo, rtx hi, bool highp)
1982 enum machine_mode mode = GET_MODE (lo);
1983 rtx (*gen) (rtx, rtx, rtx);
1989 gen = highp ? gen_vec_interleave_highv8qi : gen_vec_interleave_lowv8qi;
1992 gen = highp ? gen_vec_interleave_highv4hi : gen_vec_interleave_lowv4hi;
1998 x = gen_lowpart (mode, out);
1999 if (TARGET_BIG_ENDIAN)
2000 x = gen (x, hi, lo);
2002 x = gen (x, lo, hi);
2006 /* Return a vector of the sign-extension of VEC. */
2009 ia64_unpack_sign (rtx vec, bool unsignedp)
2011 enum machine_mode mode = GET_MODE (vec);
2012 rtx zero = CONST0_RTX (mode);
2018 rtx sign = gen_reg_rtx (mode);
2021 neg = ia64_expand_vecint_compare (LT, mode, sign, vec, zero);
2028 /* Emit an integral vector unpack operation. */
2031 ia64_expand_unpack (rtx operands[3], bool unsignedp, bool highp)
2033 rtx sign = ia64_unpack_sign (operands[1], unsignedp);
2034 ia64_unpack_assemble (operands[0], operands[1], sign, highp);
2037 /* Emit an integral vector widening sum operations. */
2040 ia64_expand_widen_sum (rtx operands[3], bool unsignedp)
2042 enum machine_mode wmode;
2045 sign = ia64_unpack_sign (operands[1], unsignedp);
2047 wmode = GET_MODE (operands[0]);
2048 l = gen_reg_rtx (wmode);
2049 h = gen_reg_rtx (wmode);
2051 ia64_unpack_assemble (l, operands[1], sign, false);
2052 ia64_unpack_assemble (h, operands[1], sign, true);
2054 t = expand_binop (wmode, add_optab, l, operands[2], NULL, 0, OPTAB_DIRECT);
2055 t = expand_binop (wmode, add_optab, h, t, operands[0], 0, OPTAB_DIRECT);
2056 if (t != operands[0])
2057 emit_move_insn (operands[0], t);
2060 /* Emit a signed or unsigned V8QI dot product operation. */
2063 ia64_expand_dot_prod_v8qi (rtx operands[4], bool unsignedp)
2065 rtx op1, op2, sn1, sn2, l1, l2, h1, h2;
2066 rtx p1, p2, p3, p4, s1, s2, s3;
2070 sn1 = ia64_unpack_sign (op1, unsignedp);
2071 sn2 = ia64_unpack_sign (op2, unsignedp);
2073 l1 = gen_reg_rtx (V4HImode);
2074 l2 = gen_reg_rtx (V4HImode);
2075 h1 = gen_reg_rtx (V4HImode);
2076 h2 = gen_reg_rtx (V4HImode);
2077 ia64_unpack_assemble (l1, op1, sn1, false);
2078 ia64_unpack_assemble (l2, op2, sn2, false);
2079 ia64_unpack_assemble (h1, op1, sn1, true);
2080 ia64_unpack_assemble (h2, op2, sn2, true);
2082 p1 = gen_reg_rtx (V2SImode);
2083 p2 = gen_reg_rtx (V2SImode);
2084 p3 = gen_reg_rtx (V2SImode);
2085 p4 = gen_reg_rtx (V2SImode);
2086 emit_insn (gen_pmpy2_even (p1, l1, l2));
2087 emit_insn (gen_pmpy2_even (p2, h1, h2));
2088 emit_insn (gen_pmpy2_odd (p3, l1, l2));
2089 emit_insn (gen_pmpy2_odd (p4, h1, h2));
2091 s1 = gen_reg_rtx (V2SImode);
2092 s2 = gen_reg_rtx (V2SImode);
2093 s3 = gen_reg_rtx (V2SImode);
2094 emit_insn (gen_addv2si3 (s1, p1, p2));
2095 emit_insn (gen_addv2si3 (s2, p3, p4));
2096 emit_insn (gen_addv2si3 (s3, s1, operands[3]));
2097 emit_insn (gen_addv2si3 (operands[0], s2, s3));
2100 /* Emit the appropriate sequence for a call. */
2103 ia64_expand_call (rtx retval, rtx addr, rtx nextarg ATTRIBUTE_UNUSED,
2108 addr = XEXP (addr, 0);
2109 addr = convert_memory_address (DImode, addr);
2110 b0 = gen_rtx_REG (DImode, R_BR (0));
2112 /* ??? Should do this for functions known to bind local too. */
2113 if (TARGET_NO_PIC || TARGET_AUTO_PIC)
2116 insn = gen_sibcall_nogp (addr);
2118 insn = gen_call_nogp (addr, b0);
2120 insn = gen_call_value_nogp (retval, addr, b0);
2121 insn = emit_call_insn (insn);
2126 insn = gen_sibcall_gp (addr);
2128 insn = gen_call_gp (addr, b0);
2130 insn = gen_call_value_gp (retval, addr, b0);
2131 insn = emit_call_insn (insn);
2133 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2137 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), b0);
2139 if (TARGET_ABI_OPEN_VMS)
2140 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2141 gen_rtx_REG (DImode, GR_REG (25)));
2145 reg_emitted (enum ia64_frame_regs r)
2147 if (emitted_frame_related_regs[r] == 0)
2148 emitted_frame_related_regs[r] = current_frame_info.r[r];
2150 gcc_assert (emitted_frame_related_regs[r] == current_frame_info.r[r]);
2154 get_reg (enum ia64_frame_regs r)
2157 return current_frame_info.r[r];
2161 is_emitted (int regno)
2165 for (r = reg_fp; r < number_of_ia64_frame_regs; r++)
2166 if (emitted_frame_related_regs[r] == regno)
2172 ia64_reload_gp (void)
2176 if (current_frame_info.r[reg_save_gp])
2178 tmp = gen_rtx_REG (DImode, get_reg (reg_save_gp));
2182 HOST_WIDE_INT offset;
2185 offset = (current_frame_info.spill_cfa_off
2186 + current_frame_info.spill_size);
2187 if (frame_pointer_needed)
2189 tmp = hard_frame_pointer_rtx;
2194 tmp = stack_pointer_rtx;
2195 offset = current_frame_info.total_size - offset;
2198 offset_r = GEN_INT (offset);
2199 if (satisfies_constraint_I (offset_r))
2200 emit_insn (gen_adddi3 (pic_offset_table_rtx, tmp, offset_r));
2203 emit_move_insn (pic_offset_table_rtx, offset_r);
2204 emit_insn (gen_adddi3 (pic_offset_table_rtx,
2205 pic_offset_table_rtx, tmp));
2208 tmp = gen_rtx_MEM (DImode, pic_offset_table_rtx);
2211 emit_move_insn (pic_offset_table_rtx, tmp);
2215 ia64_split_call (rtx retval, rtx addr, rtx retaddr, rtx scratch_r,
2216 rtx scratch_b, int noreturn_p, int sibcall_p)
2219 bool is_desc = false;
2221 /* If we find we're calling through a register, then we're actually
2222 calling through a descriptor, so load up the values. */
2223 if (REG_P (addr) && GR_REGNO_P (REGNO (addr)))
2228 /* ??? We are currently constrained to *not* use peep2, because
2229 we can legitimately change the global lifetime of the GP
2230 (in the form of killing where previously live). This is
2231 because a call through a descriptor doesn't use the previous
2232 value of the GP, while a direct call does, and we do not
2233 commit to either form until the split here.
2235 That said, this means that we lack precise life info for
2236 whether ADDR is dead after this call. This is not terribly
2237 important, since we can fix things up essentially for free
2238 with the POST_DEC below, but it's nice to not use it when we
2239 can immediately tell it's not necessary. */
2240 addr_dead_p = ((noreturn_p || sibcall_p
2241 || TEST_HARD_REG_BIT (regs_invalidated_by_call,
2243 && !FUNCTION_ARG_REGNO_P (REGNO (addr)));
2245 /* Load the code address into scratch_b. */
2246 tmp = gen_rtx_POST_INC (Pmode, addr);
2247 tmp = gen_rtx_MEM (Pmode, tmp);
2248 emit_move_insn (scratch_r, tmp);
2249 emit_move_insn (scratch_b, scratch_r);
2251 /* Load the GP address. If ADDR is not dead here, then we must
2252 revert the change made above via the POST_INCREMENT. */
2254 tmp = gen_rtx_POST_DEC (Pmode, addr);
2257 tmp = gen_rtx_MEM (Pmode, tmp);
2258 emit_move_insn (pic_offset_table_rtx, tmp);
2265 insn = gen_sibcall_nogp (addr);
2267 insn = gen_call_value_nogp (retval, addr, retaddr);
2269 insn = gen_call_nogp (addr, retaddr);
2270 emit_call_insn (insn);
2272 if ((!TARGET_CONST_GP || is_desc) && !noreturn_p && !sibcall_p)
2276 /* Expand an atomic operation. We want to perform MEM <CODE>= VAL atomically.
2278 This differs from the generic code in that we know about the zero-extending
2279 properties of cmpxchg, and the zero-extending requirements of ar.ccv. We
2280 also know that ld.acq+cmpxchg.rel equals a full barrier.
2282 The loop we want to generate looks like
2287 new_reg = cmp_reg op val;
2288 cmp_reg = compare-and-swap(mem, old_reg, new_reg)
2289 if (cmp_reg != old_reg)
2292 Note that we only do the plain load from memory once. Subsequent
2293 iterations use the value loaded by the compare-and-swap pattern. */
2296 ia64_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
2297 rtx old_dst, rtx new_dst)
2299 enum machine_mode mode = GET_MODE (mem);
2300 rtx old_reg, new_reg, cmp_reg, ar_ccv, label;
2301 enum insn_code icode;
2303 /* Special case for using fetchadd. */
2304 if ((mode == SImode || mode == DImode)
2305 && (code == PLUS || code == MINUS)
2306 && fetchadd_operand (val, mode))
2309 val = GEN_INT (-INTVAL (val));
2312 old_dst = gen_reg_rtx (mode);
2314 emit_insn (gen_memory_barrier ());
2317 icode = CODE_FOR_fetchadd_acq_si;
2319 icode = CODE_FOR_fetchadd_acq_di;
2320 emit_insn (GEN_FCN (icode) (old_dst, mem, val));
2324 new_reg = expand_simple_binop (mode, PLUS, old_dst, val, new_dst,
2326 if (new_reg != new_dst)
2327 emit_move_insn (new_dst, new_reg);
2332 /* Because of the volatile mem read, we get an ld.acq, which is the
2333 front half of the full barrier. The end half is the cmpxchg.rel. */
2334 gcc_assert (MEM_VOLATILE_P (mem));
2336 old_reg = gen_reg_rtx (DImode);
2337 cmp_reg = gen_reg_rtx (DImode);
2338 label = gen_label_rtx ();
2342 val = simplify_gen_subreg (DImode, val, mode, 0);
2343 emit_insn (gen_extend_insn (cmp_reg, mem, DImode, mode, 1));
2346 emit_move_insn (cmp_reg, mem);
2350 ar_ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
2351 emit_move_insn (old_reg, cmp_reg);
2352 emit_move_insn (ar_ccv, cmp_reg);
2355 emit_move_insn (old_dst, gen_lowpart (mode, cmp_reg));
2360 new_reg = expand_simple_binop (DImode, AND, new_reg, val, NULL_RTX,
2361 true, OPTAB_DIRECT);
2362 new_reg = expand_simple_unop (DImode, code, new_reg, NULL_RTX, true);
2365 new_reg = expand_simple_binop (DImode, code, new_reg, val, NULL_RTX,
2366 true, OPTAB_DIRECT);
2369 new_reg = gen_lowpart (mode, new_reg);
2371 emit_move_insn (new_dst, new_reg);
2375 case QImode: icode = CODE_FOR_cmpxchg_rel_qi; break;
2376 case HImode: icode = CODE_FOR_cmpxchg_rel_hi; break;
2377 case SImode: icode = CODE_FOR_cmpxchg_rel_si; break;
2378 case DImode: icode = CODE_FOR_cmpxchg_rel_di; break;
2383 emit_insn (GEN_FCN (icode) (cmp_reg, mem, ar_ccv, new_reg));
2385 emit_cmp_and_jump_insns (cmp_reg, old_reg, NE, NULL, DImode, true, label);
2388 /* Begin the assembly file. */
2391 ia64_file_start (void)
2393 /* Variable tracking should be run after all optimizations which change order
2394 of insns. It also needs a valid CFG. This can't be done in
2395 ia64_option_override, because flag_var_tracking is finalized after
2397 ia64_flag_var_tracking = flag_var_tracking;
2398 flag_var_tracking = 0;
2400 default_file_start ();
2401 emit_safe_across_calls ();
2405 emit_safe_across_calls (void)
2407 unsigned int rs, re;
2414 while (rs < 64 && call_used_regs[PR_REG (rs)])
2418 for (re = rs + 1; re < 64 && ! call_used_regs[PR_REG (re)]; re++)
2422 fputs ("\t.pred.safe_across_calls ", asm_out_file);
2426 fputc (',', asm_out_file);
2428 fprintf (asm_out_file, "p%u", rs);
2430 fprintf (asm_out_file, "p%u-p%u", rs, re - 1);
2434 fputc ('\n', asm_out_file);
2437 /* Globalize a declaration. */
2440 ia64_globalize_decl_name (FILE * stream, tree decl)
2442 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2443 tree version_attr = lookup_attribute ("version_id", DECL_ATTRIBUTES (decl));
2446 tree v = TREE_VALUE (TREE_VALUE (version_attr));
2447 const char *p = TREE_STRING_POINTER (v);
2448 fprintf (stream, "\t.alias %s#, \"%s{%s}\"\n", name, name, p);
2450 targetm.asm_out.globalize_label (stream, name);
2451 if (TREE_CODE (decl) == FUNCTION_DECL)
2452 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "function");
2455 /* Helper function for ia64_compute_frame_size: find an appropriate general
2456 register to spill some special register to. SPECIAL_SPILL_MASK contains
2457 bits in GR0 to GR31 that have already been allocated by this routine.
2458 TRY_LOCALS is true if we should attempt to locate a local regnum. */
2461 find_gr_spill (enum ia64_frame_regs r, int try_locals)
2465 if (emitted_frame_related_regs[r] != 0)
2467 regno = emitted_frame_related_regs[r];
2468 if (regno >= LOC_REG (0) && regno < LOC_REG (80 - frame_pointer_needed)
2469 && current_frame_info.n_local_regs < regno - LOC_REG (0) + 1)
2470 current_frame_info.n_local_regs = regno - LOC_REG (0) + 1;
2471 else if (current_function_is_leaf
2472 && regno >= GR_REG (1) && regno <= GR_REG (31))
2473 current_frame_info.gr_used_mask |= 1 << regno;
2478 /* If this is a leaf function, first try an otherwise unused
2479 call-clobbered register. */
2480 if (current_function_is_leaf)
2482 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
2483 if (! df_regs_ever_live_p (regno)
2484 && call_used_regs[regno]
2485 && ! fixed_regs[regno]
2486 && ! global_regs[regno]
2487 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0
2488 && ! is_emitted (regno))
2490 current_frame_info.gr_used_mask |= 1 << regno;
2497 regno = current_frame_info.n_local_regs;
2498 /* If there is a frame pointer, then we can't use loc79, because
2499 that is HARD_FRAME_POINTER_REGNUM. In particular, see the
2500 reg_name switching code in ia64_expand_prologue. */
2501 while (regno < (80 - frame_pointer_needed))
2502 if (! is_emitted (LOC_REG (regno++)))
2504 current_frame_info.n_local_regs = regno;
2505 return LOC_REG (regno - 1);
2509 /* Failed to find a general register to spill to. Must use stack. */
2513 /* In order to make for nice schedules, we try to allocate every temporary
2514 to a different register. We must of course stay away from call-saved,
2515 fixed, and global registers. We must also stay away from registers
2516 allocated in current_frame_info.gr_used_mask, since those include regs
2517 used all through the prologue.
2519 Any register allocated here must be used immediately. The idea is to
2520 aid scheduling, not to solve data flow problems. */
2522 static int last_scratch_gr_reg;
2525 next_scratch_gr_reg (void)
2529 for (i = 0; i < 32; ++i)
2531 regno = (last_scratch_gr_reg + i + 1) & 31;
2532 if (call_used_regs[regno]
2533 && ! fixed_regs[regno]
2534 && ! global_regs[regno]
2535 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0)
2537 last_scratch_gr_reg = regno;
2542 /* There must be _something_ available. */
2546 /* Helper function for ia64_compute_frame_size, called through
2547 diddle_return_value. Mark REG in current_frame_info.gr_used_mask. */
2550 mark_reg_gr_used_mask (rtx reg, void *data ATTRIBUTE_UNUSED)
2552 unsigned int regno = REGNO (reg);
2555 unsigned int i, n = hard_regno_nregs[regno][GET_MODE (reg)];
2556 for (i = 0; i < n; ++i)
2557 current_frame_info.gr_used_mask |= 1 << (regno + i);
2562 /* Returns the number of bytes offset between the frame pointer and the stack
2563 pointer for the current function. SIZE is the number of bytes of space
2564 needed for local variables. */
2567 ia64_compute_frame_size (HOST_WIDE_INT size)
2569 HOST_WIDE_INT total_size;
2570 HOST_WIDE_INT spill_size = 0;
2571 HOST_WIDE_INT extra_spill_size = 0;
2572 HOST_WIDE_INT pretend_args_size;
2575 int spilled_gr_p = 0;
2576 int spilled_fr_p = 0;
2582 if (current_frame_info.initialized)
2585 memset (¤t_frame_info, 0, sizeof current_frame_info);
2586 CLEAR_HARD_REG_SET (mask);
2588 /* Don't allocate scratches to the return register. */
2589 diddle_return_value (mark_reg_gr_used_mask, NULL);
2591 /* Don't allocate scratches to the EH scratch registers. */
2592 if (cfun->machine->ia64_eh_epilogue_sp)
2593 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_sp, NULL);
2594 if (cfun->machine->ia64_eh_epilogue_bsp)
2595 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_bsp, NULL);
2597 /* Find the size of the register stack frame. We have only 80 local
2598 registers, because we reserve 8 for the inputs and 8 for the
2601 /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed,
2602 since we'll be adjusting that down later. */
2603 regno = LOC_REG (78) + ! frame_pointer_needed;
2604 for (; regno >= LOC_REG (0); regno--)
2605 if (df_regs_ever_live_p (regno) && !is_emitted (regno))
2607 current_frame_info.n_local_regs = regno - LOC_REG (0) + 1;
2609 /* For functions marked with the syscall_linkage attribute, we must mark
2610 all eight input registers as in use, so that locals aren't visible to
2613 if (cfun->machine->n_varargs > 0
2614 || lookup_attribute ("syscall_linkage",
2615 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
2616 current_frame_info.n_input_regs = 8;
2619 for (regno = IN_REG (7); regno >= IN_REG (0); regno--)
2620 if (df_regs_ever_live_p (regno))
2622 current_frame_info.n_input_regs = regno - IN_REG (0) + 1;
2625 for (regno = OUT_REG (7); regno >= OUT_REG (0); regno--)
2626 if (df_regs_ever_live_p (regno))
2628 i = regno - OUT_REG (0) + 1;
2630 #ifndef PROFILE_HOOK
2631 /* When -p profiling, we need one output register for the mcount argument.
2632 Likewise for -a profiling for the bb_init_func argument. For -ax
2633 profiling, we need two output registers for the two bb_init_trace_func
2638 current_frame_info.n_output_regs = i;
2640 /* ??? No rotating register support yet. */
2641 current_frame_info.n_rotate_regs = 0;
2643 /* Discover which registers need spilling, and how much room that
2644 will take. Begin with floating point and general registers,
2645 which will always wind up on the stack. */
2647 for (regno = FR_REG (2); regno <= FR_REG (127); regno++)
2648 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
2650 SET_HARD_REG_BIT (mask, regno);
2656 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
2657 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
2659 SET_HARD_REG_BIT (mask, regno);
2665 for (regno = BR_REG (1); regno <= BR_REG (7); regno++)
2666 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
2668 SET_HARD_REG_BIT (mask, regno);
2673 /* Now come all special registers that might get saved in other
2674 general registers. */
2676 if (frame_pointer_needed)
2678 current_frame_info.r[reg_fp] = find_gr_spill (reg_fp, 1);
2679 /* If we did not get a register, then we take LOC79. This is guaranteed
2680 to be free, even if regs_ever_live is already set, because this is
2681 HARD_FRAME_POINTER_REGNUM. This requires incrementing n_local_regs,
2682 as we don't count loc79 above. */
2683 if (current_frame_info.r[reg_fp] == 0)
2685 current_frame_info.r[reg_fp] = LOC_REG (79);
2686 current_frame_info.n_local_regs = LOC_REG (79) - LOC_REG (0) + 1;
2690 if (! current_function_is_leaf)
2692 /* Emit a save of BR0 if we call other functions. Do this even
2693 if this function doesn't return, as EH depends on this to be
2694 able to unwind the stack. */
2695 SET_HARD_REG_BIT (mask, BR_REG (0));
2697 current_frame_info.r[reg_save_b0] = find_gr_spill (reg_save_b0, 1);
2698 if (current_frame_info.r[reg_save_b0] == 0)
2700 extra_spill_size += 8;
2704 /* Similarly for ar.pfs. */
2705 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
2706 current_frame_info.r[reg_save_ar_pfs] = find_gr_spill (reg_save_ar_pfs, 1);
2707 if (current_frame_info.r[reg_save_ar_pfs] == 0)
2709 extra_spill_size += 8;
2713 /* Similarly for gp. Note that if we're calling setjmp, the stacked
2714 registers are clobbered, so we fall back to the stack. */
2715 current_frame_info.r[reg_save_gp]
2716 = (cfun->calls_setjmp ? 0 : find_gr_spill (reg_save_gp, 1));
2717 if (current_frame_info.r[reg_save_gp] == 0)
2719 SET_HARD_REG_BIT (mask, GR_REG (1));
2726 if (df_regs_ever_live_p (BR_REG (0)) && ! call_used_regs[BR_REG (0)])
2728 SET_HARD_REG_BIT (mask, BR_REG (0));
2729 extra_spill_size += 8;
2733 if (df_regs_ever_live_p (AR_PFS_REGNUM))
2735 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
2736 current_frame_info.r[reg_save_ar_pfs]
2737 = find_gr_spill (reg_save_ar_pfs, 1);
2738 if (current_frame_info.r[reg_save_ar_pfs] == 0)
2740 extra_spill_size += 8;
2746 /* Unwind descriptor hackery: things are most efficient if we allocate
2747 consecutive GR save registers for RP, PFS, FP in that order. However,
2748 it is absolutely critical that FP get the only hard register that's
2749 guaranteed to be free, so we allocated it first. If all three did
2750 happen to be allocated hard regs, and are consecutive, rearrange them
2751 into the preferred order now.
2753 If we have already emitted code for any of those registers,
2754 then it's already too late to change. */
2755 min_regno = MIN (current_frame_info.r[reg_fp],
2756 MIN (current_frame_info.r[reg_save_b0],
2757 current_frame_info.r[reg_save_ar_pfs]));
2758 max_regno = MAX (current_frame_info.r[reg_fp],
2759 MAX (current_frame_info.r[reg_save_b0],
2760 current_frame_info.r[reg_save_ar_pfs]));
2762 && min_regno + 2 == max_regno
2763 && (current_frame_info.r[reg_fp] == min_regno + 1
2764 || current_frame_info.r[reg_save_b0] == min_regno + 1
2765 || current_frame_info.r[reg_save_ar_pfs] == min_regno + 1)
2766 && (emitted_frame_related_regs[reg_save_b0] == 0
2767 || emitted_frame_related_regs[reg_save_b0] == min_regno)
2768 && (emitted_frame_related_regs[reg_save_ar_pfs] == 0
2769 || emitted_frame_related_regs[reg_save_ar_pfs] == min_regno + 1)
2770 && (emitted_frame_related_regs[reg_fp] == 0
2771 || emitted_frame_related_regs[reg_fp] == min_regno + 2))
2773 current_frame_info.r[reg_save_b0] = min_regno;
2774 current_frame_info.r[reg_save_ar_pfs] = min_regno + 1;
2775 current_frame_info.r[reg_fp] = min_regno + 2;
2778 /* See if we need to store the predicate register block. */
2779 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
2780 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
2782 if (regno <= PR_REG (63))
2784 SET_HARD_REG_BIT (mask, PR_REG (0));
2785 current_frame_info.r[reg_save_pr] = find_gr_spill (reg_save_pr, 1);
2786 if (current_frame_info.r[reg_save_pr] == 0)
2788 extra_spill_size += 8;
2792 /* ??? Mark them all as used so that register renaming and such
2793 are free to use them. */
2794 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
2795 df_set_regs_ever_live (regno, true);
2798 /* If we're forced to use st8.spill, we're forced to save and restore
2799 ar.unat as well. The check for existing liveness allows inline asm
2800 to touch ar.unat. */
2801 if (spilled_gr_p || cfun->machine->n_varargs
2802 || df_regs_ever_live_p (AR_UNAT_REGNUM))
2804 df_set_regs_ever_live (AR_UNAT_REGNUM, true);
2805 SET_HARD_REG_BIT (mask, AR_UNAT_REGNUM);
2806 current_frame_info.r[reg_save_ar_unat]
2807 = find_gr_spill (reg_save_ar_unat, spill_size == 0);
2808 if (current_frame_info.r[reg_save_ar_unat] == 0)
2810 extra_spill_size += 8;
2815 if (df_regs_ever_live_p (AR_LC_REGNUM))
2817 SET_HARD_REG_BIT (mask, AR_LC_REGNUM);
2818 current_frame_info.r[reg_save_ar_lc]
2819 = find_gr_spill (reg_save_ar_lc, spill_size == 0);
2820 if (current_frame_info.r[reg_save_ar_lc] == 0)
2822 extra_spill_size += 8;
2827 /* If we have an odd number of words of pretend arguments written to
2828 the stack, then the FR save area will be unaligned. We round the
2829 size of this area up to keep things 16 byte aligned. */
2831 pretend_args_size = IA64_STACK_ALIGN (crtl->args.pretend_args_size);
2833 pretend_args_size = crtl->args.pretend_args_size;
2835 total_size = (spill_size + extra_spill_size + size + pretend_args_size
2836 + crtl->outgoing_args_size);
2837 total_size = IA64_STACK_ALIGN (total_size);
2839 /* We always use the 16-byte scratch area provided by the caller, but
2840 if we are a leaf function, there's no one to which we need to provide
2842 if (current_function_is_leaf)
2843 total_size = MAX (0, total_size - 16);
2845 current_frame_info.total_size = total_size;
2846 current_frame_info.spill_cfa_off = pretend_args_size - 16;
2847 current_frame_info.spill_size = spill_size;
2848 current_frame_info.extra_spill_size = extra_spill_size;
2849 COPY_HARD_REG_SET (current_frame_info.mask, mask);
2850 current_frame_info.n_spilled = n_spilled;
2851 current_frame_info.initialized = reload_completed;
2854 /* Worker function for TARGET_CAN_ELIMINATE. */
2857 ia64_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
2859 return (to == BR_REG (0) ? current_function_is_leaf : true);
2862 /* Compute the initial difference between the specified pair of registers. */
2865 ia64_initial_elimination_offset (int from, int to)
2867 HOST_WIDE_INT offset;
2869 ia64_compute_frame_size (get_frame_size ());
2872 case FRAME_POINTER_REGNUM:
2875 case HARD_FRAME_POINTER_REGNUM:
2876 if (current_function_is_leaf)
2877 offset = -current_frame_info.total_size;
2879 offset = -(current_frame_info.total_size
2880 - crtl->outgoing_args_size - 16);
2883 case STACK_POINTER_REGNUM:
2884 if (current_function_is_leaf)
2887 offset = 16 + crtl->outgoing_args_size;
2895 case ARG_POINTER_REGNUM:
2896 /* Arguments start above the 16 byte save area, unless stdarg
2897 in which case we store through the 16 byte save area. */
2900 case HARD_FRAME_POINTER_REGNUM:
2901 offset = 16 - crtl->args.pretend_args_size;
2904 case STACK_POINTER_REGNUM:
2905 offset = (current_frame_info.total_size
2906 + 16 - crtl->args.pretend_args_size);
2921 /* If there are more than a trivial number of register spills, we use
2922 two interleaved iterators so that we can get two memory references
2925 In order to simplify things in the prologue and epilogue expanders,
2926 we use helper functions to fix up the memory references after the
2927 fact with the appropriate offsets to a POST_MODIFY memory mode.
2928 The following data structure tracks the state of the two iterators
2929 while insns are being emitted. */
2931 struct spill_fill_data
2933 rtx init_after; /* point at which to emit initializations */
2934 rtx init_reg[2]; /* initial base register */
2935 rtx iter_reg[2]; /* the iterator registers */
2936 rtx *prev_addr[2]; /* address of last memory use */
2937 rtx prev_insn[2]; /* the insn corresponding to prev_addr */
2938 HOST_WIDE_INT prev_off[2]; /* last offset */
2939 int n_iter; /* number of iterators in use */
2940 int next_iter; /* next iterator to use */
2941 unsigned int save_gr_used_mask;
2944 static struct spill_fill_data spill_fill_data;
2947 setup_spill_pointers (int n_spills, rtx init_reg, HOST_WIDE_INT cfa_off)
2951 spill_fill_data.init_after = get_last_insn ();
2952 spill_fill_data.init_reg[0] = init_reg;
2953 spill_fill_data.init_reg[1] = init_reg;
2954 spill_fill_data.prev_addr[0] = NULL;
2955 spill_fill_data.prev_addr[1] = NULL;
2956 spill_fill_data.prev_insn[0] = NULL;
2957 spill_fill_data.prev_insn[1] = NULL;
2958 spill_fill_data.prev_off[0] = cfa_off;
2959 spill_fill_data.prev_off[1] = cfa_off;
2960 spill_fill_data.next_iter = 0;
2961 spill_fill_data.save_gr_used_mask = current_frame_info.gr_used_mask;
2963 spill_fill_data.n_iter = 1 + (n_spills > 2);
2964 for (i = 0; i < spill_fill_data.n_iter; ++i)
2966 int regno = next_scratch_gr_reg ();
2967 spill_fill_data.iter_reg[i] = gen_rtx_REG (DImode, regno);
2968 current_frame_info.gr_used_mask |= 1 << regno;
2973 finish_spill_pointers (void)
2975 current_frame_info.gr_used_mask = spill_fill_data.save_gr_used_mask;
2979 spill_restore_mem (rtx reg, HOST_WIDE_INT cfa_off)
2981 int iter = spill_fill_data.next_iter;
2982 HOST_WIDE_INT disp = spill_fill_data.prev_off[iter] - cfa_off;
2983 rtx disp_rtx = GEN_INT (disp);
2986 if (spill_fill_data.prev_addr[iter])
2988 if (satisfies_constraint_N (disp_rtx))
2990 *spill_fill_data.prev_addr[iter]
2991 = gen_rtx_POST_MODIFY (DImode, spill_fill_data.iter_reg[iter],
2992 gen_rtx_PLUS (DImode,
2993 spill_fill_data.iter_reg[iter],
2995 add_reg_note (spill_fill_data.prev_insn[iter],
2996 REG_INC, spill_fill_data.iter_reg[iter]);
3000 /* ??? Could use register post_modify for loads. */
3001 if (!satisfies_constraint_I (disp_rtx))
3003 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
3004 emit_move_insn (tmp, disp_rtx);
3007 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
3008 spill_fill_data.iter_reg[iter], disp_rtx));
3011 /* Micro-optimization: if we've created a frame pointer, it's at
3012 CFA 0, which may allow the real iterator to be initialized lower,
3013 slightly increasing parallelism. Also, if there are few saves
3014 it may eliminate the iterator entirely. */
3016 && spill_fill_data.init_reg[iter] == stack_pointer_rtx
3017 && frame_pointer_needed)
3019 mem = gen_rtx_MEM (GET_MODE (reg), hard_frame_pointer_rtx);
3020 set_mem_alias_set (mem, get_varargs_alias_set ());
3028 seq = gen_movdi (spill_fill_data.iter_reg[iter],
3029 spill_fill_data.init_reg[iter]);
3034 if (!satisfies_constraint_I (disp_rtx))
3036 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
3037 emit_move_insn (tmp, disp_rtx);
3041 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
3042 spill_fill_data.init_reg[iter],
3049 /* Careful for being the first insn in a sequence. */
3050 if (spill_fill_data.init_after)
3051 insn = emit_insn_after (seq, spill_fill_data.init_after);
3054 rtx first = get_insns ();
3056 insn = emit_insn_before (seq, first);
3058 insn = emit_insn (seq);
3060 spill_fill_data.init_after = insn;
3063 mem = gen_rtx_MEM (GET_MODE (reg), spill_fill_data.iter_reg[iter]);
3065 /* ??? Not all of the spills are for varargs, but some of them are.
3066 The rest of the spills belong in an alias set of their own. But
3067 it doesn't actually hurt to include them here. */
3068 set_mem_alias_set (mem, get_varargs_alias_set ());
3070 spill_fill_data.prev_addr[iter] = &XEXP (mem, 0);
3071 spill_fill_data.prev_off[iter] = cfa_off;
3073 if (++iter >= spill_fill_data.n_iter)
3075 spill_fill_data.next_iter = iter;
3081 do_spill (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off,
3084 int iter = spill_fill_data.next_iter;
3087 mem = spill_restore_mem (reg, cfa_off);
3088 insn = emit_insn ((*move_fn) (mem, reg, GEN_INT (cfa_off)));
3089 spill_fill_data.prev_insn[iter] = insn;
3096 RTX_FRAME_RELATED_P (insn) = 1;
3098 /* Don't even pretend that the unwind code can intuit its way
3099 through a pair of interleaved post_modify iterators. Just
3100 provide the correct answer. */
3102 if (frame_pointer_needed)
3104 base = hard_frame_pointer_rtx;
3109 base = stack_pointer_rtx;
3110 off = current_frame_info.total_size - cfa_off;
3113 add_reg_note (insn, REG_CFA_OFFSET,
3114 gen_rtx_SET (VOIDmode,
3115 gen_rtx_MEM (GET_MODE (reg),
3116 plus_constant (base, off)),
3122 do_restore (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off)
3124 int iter = spill_fill_data.next_iter;
3127 insn = emit_insn ((*move_fn) (reg, spill_restore_mem (reg, cfa_off),
3128 GEN_INT (cfa_off)));
3129 spill_fill_data.prev_insn[iter] = insn;
3132 /* Wrapper functions that discards the CONST_INT spill offset. These
3133 exist so that we can give gr_spill/gr_fill the offset they need and
3134 use a consistent function interface. */
3137 gen_movdi_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
3139 return gen_movdi (dest, src);
3143 gen_fr_spill_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
3145 return gen_fr_spill (dest, src);
3149 gen_fr_restore_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
3151 return gen_fr_restore (dest, src);
3154 /* Called after register allocation to add any instructions needed for the
3155 prologue. Using a prologue insn is favored compared to putting all of the
3156 instructions in output_function_prologue(), since it allows the scheduler
3157 to intermix instructions with the saves of the caller saved registers. In
3158 some cases, it might be necessary to emit a barrier instruction as the last
3159 insn to prevent such scheduling.
3161 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
3162 so that the debug info generation code can handle them properly.
3164 The register save area is layed out like so:
3166 [ varargs spill area ]
3167 [ fr register spill area ]
3168 [ br register spill area ]
3169 [ ar register spill area ]
3170 [ pr register spill area ]
3171 [ gr register spill area ] */
3173 /* ??? Get inefficient code when the frame size is larger than can fit in an
3174 adds instruction. */
3177 ia64_expand_prologue (void)
3179 rtx insn, ar_pfs_save_reg, ar_unat_save_reg;
3180 int i, epilogue_p, regno, alt_regno, cfa_off, n_varargs;
3183 ia64_compute_frame_size (get_frame_size ());
3184 last_scratch_gr_reg = 15;
3186 if (flag_stack_usage)
3187 current_function_static_stack_size = current_frame_info.total_size;
3191 fprintf (dump_file, "ia64 frame related registers "
3192 "recorded in current_frame_info.r[]:\n");
3193 #define PRINTREG(a) if (current_frame_info.r[a]) \
3194 fprintf(dump_file, "%s = %d\n", #a, current_frame_info.r[a])
3196 PRINTREG(reg_save_b0);
3197 PRINTREG(reg_save_pr);
3198 PRINTREG(reg_save_ar_pfs);
3199 PRINTREG(reg_save_ar_unat);
3200 PRINTREG(reg_save_ar_lc);
3201 PRINTREG(reg_save_gp);
3205 /* If there is no epilogue, then we don't need some prologue insns.
3206 We need to avoid emitting the dead prologue insns, because flow
3207 will complain about them. */
3213 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
3214 if ((e->flags & EDGE_FAKE) == 0
3215 && (e->flags & EDGE_FALLTHRU) != 0)
3217 epilogue_p = (e != NULL);
3222 /* Set the local, input, and output register names. We need to do this
3223 for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in
3224 half. If we use in/loc/out register names, then we get assembler errors
3225 in crtn.S because there is no alloc insn or regstk directive in there. */
3226 if (! TARGET_REG_NAMES)
3228 int inputs = current_frame_info.n_input_regs;
3229 int locals = current_frame_info.n_local_regs;
3230 int outputs = current_frame_info.n_output_regs;
3232 for (i = 0; i < inputs; i++)
3233 reg_names[IN_REG (i)] = ia64_reg_numbers[i];
3234 for (i = 0; i < locals; i++)
3235 reg_names[LOC_REG (i)] = ia64_reg_numbers[inputs + i];
3236 for (i = 0; i < outputs; i++)
3237 reg_names[OUT_REG (i)] = ia64_reg_numbers[inputs + locals + i];
3240 /* Set the frame pointer register name. The regnum is logically loc79,
3241 but of course we'll not have allocated that many locals. Rather than
3242 worrying about renumbering the existing rtxs, we adjust the name. */
3243 /* ??? This code means that we can never use one local register when
3244 there is a frame pointer. loc79 gets wasted in this case, as it is
3245 renamed to a register that will never be used. See also the try_locals
3246 code in find_gr_spill. */
3247 if (current_frame_info.r[reg_fp])
3249 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
3250 reg_names[HARD_FRAME_POINTER_REGNUM]
3251 = reg_names[current_frame_info.r[reg_fp]];
3252 reg_names[current_frame_info.r[reg_fp]] = tmp;
3255 /* We don't need an alloc instruction if we've used no outputs or locals. */
3256 if (current_frame_info.n_local_regs == 0
3257 && current_frame_info.n_output_regs == 0
3258 && current_frame_info.n_input_regs <= crtl->args.info.int_regs
3259 && !TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM))
3261 /* If there is no alloc, but there are input registers used, then we
3262 need a .regstk directive. */
3263 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
3264 ar_pfs_save_reg = NULL_RTX;
3268 current_frame_info.need_regstk = 0;
3270 if (current_frame_info.r[reg_save_ar_pfs])
3272 regno = current_frame_info.r[reg_save_ar_pfs];
3273 reg_emitted (reg_save_ar_pfs);
3276 regno = next_scratch_gr_reg ();
3277 ar_pfs_save_reg = gen_rtx_REG (DImode, regno);
3279 insn = emit_insn (gen_alloc (ar_pfs_save_reg,
3280 GEN_INT (current_frame_info.n_input_regs),
3281 GEN_INT (current_frame_info.n_local_regs),
3282 GEN_INT (current_frame_info.n_output_regs),
3283 GEN_INT (current_frame_info.n_rotate_regs)));
3284 RTX_FRAME_RELATED_P (insn) = (current_frame_info.r[reg_save_ar_pfs] != 0);
3287 /* Set up frame pointer, stack pointer, and spill iterators. */
3289 n_varargs = cfun->machine->n_varargs;
3290 setup_spill_pointers (current_frame_info.n_spilled + n_varargs,
3291 stack_pointer_rtx, 0);
3293 if (frame_pointer_needed)
3295 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
3296 RTX_FRAME_RELATED_P (insn) = 1;
3298 /* Force the unwind info to recognize this as defining a new CFA,
3299 rather than some temp register setup. */
3300 add_reg_note (insn, REG_CFA_ADJUST_CFA, NULL_RTX);
3303 if (current_frame_info.total_size != 0)
3305 rtx frame_size_rtx = GEN_INT (- current_frame_info.total_size);
3308 if (satisfies_constraint_I (frame_size_rtx))
3309 offset = frame_size_rtx;
3312 regno = next_scratch_gr_reg ();
3313 offset = gen_rtx_REG (DImode, regno);
3314 emit_move_insn (offset, frame_size_rtx);
3317 insn = emit_insn (gen_adddi3 (stack_pointer_rtx,
3318 stack_pointer_rtx, offset));
3320 if (! frame_pointer_needed)
3322 RTX_FRAME_RELATED_P (insn) = 1;
3323 add_reg_note (insn, REG_CFA_ADJUST_CFA,
3324 gen_rtx_SET (VOIDmode,
3326 gen_rtx_PLUS (DImode,
3331 /* ??? At this point we must generate a magic insn that appears to
3332 modify the stack pointer, the frame pointer, and all spill
3333 iterators. This would allow the most scheduling freedom. For
3334 now, just hard stop. */
3335 emit_insn (gen_blockage ());
3338 /* Must copy out ar.unat before doing any integer spills. */
3339 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
3341 if (current_frame_info.r[reg_save_ar_unat])
3344 = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_unat]);
3345 reg_emitted (reg_save_ar_unat);
3349 alt_regno = next_scratch_gr_reg ();
3350 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
3351 current_frame_info.gr_used_mask |= 1 << alt_regno;
3354 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3355 insn = emit_move_insn (ar_unat_save_reg, reg);
3356 if (current_frame_info.r[reg_save_ar_unat])
3358 RTX_FRAME_RELATED_P (insn) = 1;
3359 add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX);
3362 /* Even if we're not going to generate an epilogue, we still
3363 need to save the register so that EH works. */
3364 if (! epilogue_p && current_frame_info.r[reg_save_ar_unat])
3365 emit_insn (gen_prologue_use (ar_unat_save_reg));
3368 ar_unat_save_reg = NULL_RTX;
3370 /* Spill all varargs registers. Do this before spilling any GR registers,
3371 since we want the UNAT bits for the GR registers to override the UNAT
3372 bits from varargs, which we don't care about. */
3375 for (regno = GR_ARG_FIRST + 7; n_varargs > 0; --n_varargs, --regno)
3377 reg = gen_rtx_REG (DImode, regno);
3378 do_spill (gen_gr_spill, reg, cfa_off += 8, NULL_RTX);
3381 /* Locate the bottom of the register save area. */
3382 cfa_off = (current_frame_info.spill_cfa_off
3383 + current_frame_info.spill_size
3384 + current_frame_info.extra_spill_size);
3386 /* Save the predicate register block either in a register or in memory. */
3387 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
3389 reg = gen_rtx_REG (DImode, PR_REG (0));
3390 if (current_frame_info.r[reg_save_pr] != 0)
3392 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_pr]);
3393 reg_emitted (reg_save_pr);
3394 insn = emit_move_insn (alt_reg, reg);
3396 /* ??? Denote pr spill/fill by a DImode move that modifies all
3397 64 hard registers. */
3398 RTX_FRAME_RELATED_P (insn) = 1;
3399 add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX);
3401 /* Even if we're not going to generate an epilogue, we still
3402 need to save the register so that EH works. */
3404 emit_insn (gen_prologue_use (alt_reg));
3408 alt_regno = next_scratch_gr_reg ();
3409 alt_reg = gen_rtx_REG (DImode, alt_regno);
3410 insn = emit_move_insn (alt_reg, reg);
3411 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3416 /* Handle AR regs in numerical order. All of them get special handling. */
3417 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM)
3418 && current_frame_info.r[reg_save_ar_unat] == 0)
3420 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3421 do_spill (gen_movdi_x, ar_unat_save_reg, cfa_off, reg);
3425 /* The alloc insn already copied ar.pfs into a general register. The
3426 only thing we have to do now is copy that register to a stack slot
3427 if we'd not allocated a local register for the job. */
3428 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM)
3429 && current_frame_info.r[reg_save_ar_pfs] == 0)
3431 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3432 do_spill (gen_movdi_x, ar_pfs_save_reg, cfa_off, reg);
3436 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
3438 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
3439 if (current_frame_info.r[reg_save_ar_lc] != 0)
3441 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_lc]);
3442 reg_emitted (reg_save_ar_lc);
3443 insn = emit_move_insn (alt_reg, reg);
3444 RTX_FRAME_RELATED_P (insn) = 1;
3445 add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX);
3447 /* Even if we're not going to generate an epilogue, we still
3448 need to save the register so that EH works. */
3450 emit_insn (gen_prologue_use (alt_reg));
3454 alt_regno = next_scratch_gr_reg ();
3455 alt_reg = gen_rtx_REG (DImode, alt_regno);
3456 emit_move_insn (alt_reg, reg);
3457 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3462 /* Save the return pointer. */
3463 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3465 reg = gen_rtx_REG (DImode, BR_REG (0));
3466 if (current_frame_info.r[reg_save_b0] != 0)
3468 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]);
3469 reg_emitted (reg_save_b0);
3470 insn = emit_move_insn (alt_reg, reg);
3471 RTX_FRAME_RELATED_P (insn) = 1;
3472 add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX);
3474 /* Even if we're not going to generate an epilogue, we still
3475 need to save the register so that EH works. */
3477 emit_insn (gen_prologue_use (alt_reg));
3481 alt_regno = next_scratch_gr_reg ();
3482 alt_reg = gen_rtx_REG (DImode, alt_regno);
3483 emit_move_insn (alt_reg, reg);
3484 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3489 if (current_frame_info.r[reg_save_gp])
3491 reg_emitted (reg_save_gp);
3492 insn = emit_move_insn (gen_rtx_REG (DImode,
3493 current_frame_info.r[reg_save_gp]),
3494 pic_offset_table_rtx);
3497 /* We should now be at the base of the gr/br/fr spill area. */
3498 gcc_assert (cfa_off == (current_frame_info.spill_cfa_off
3499 + current_frame_info.spill_size));
3501 /* Spill all general registers. */
3502 for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
3503 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3505 reg = gen_rtx_REG (DImode, regno);
3506 do_spill (gen_gr_spill, reg, cfa_off, reg);
3510 /* Spill the rest of the BR registers. */
3511 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
3512 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3514 alt_regno = next_scratch_gr_reg ();
3515 alt_reg = gen_rtx_REG (DImode, alt_regno);
3516 reg = gen_rtx_REG (DImode, regno);
3517 emit_move_insn (alt_reg, reg);
3518 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3522 /* Align the frame and spill all FR registers. */
3523 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
3524 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3526 gcc_assert (!(cfa_off & 15));
3527 reg = gen_rtx_REG (XFmode, regno);
3528 do_spill (gen_fr_spill_x, reg, cfa_off, reg);
3532 gcc_assert (cfa_off == current_frame_info.spill_cfa_off);
3534 finish_spill_pointers ();
3537 /* Output the textual info surrounding the prologue. */
3540 ia64_start_function (FILE *file, const char *fnname,
3541 tree decl ATTRIBUTE_UNUSED)
3543 #if VMS_DEBUGGING_INFO
3545 && debug_info_level > DINFO_LEVEL_NONE
3546 && strncmp (vms_debug_main, fnname, strlen (vms_debug_main)) == 0)
3548 targetm.asm_out.globalize_label (asm_out_file, VMS_DEBUG_MAIN_POINTER);
3549 ASM_OUTPUT_DEF (asm_out_file, VMS_DEBUG_MAIN_POINTER, fnname);
3550 dwarf2out_vms_debug_main_pointer ();
3555 fputs ("\t.proc ", file);
3556 assemble_name (file, fnname);
3558 ASM_OUTPUT_LABEL (file, fnname);
3561 /* Called after register allocation to add any instructions needed for the
3562 epilogue. Using an epilogue insn is favored compared to putting all of the
3563 instructions in output_function_prologue(), since it allows the scheduler
3564 to intermix instructions with the saves of the caller saved registers. In
3565 some cases, it might be necessary to emit a barrier instruction as the last
3566 insn to prevent such scheduling. */
3569 ia64_expand_epilogue (int sibcall_p)
3571 rtx insn, reg, alt_reg, ar_unat_save_reg;
3572 int regno, alt_regno, cfa_off;
3574 ia64_compute_frame_size (get_frame_size ());
3576 /* If there is a frame pointer, then we use it instead of the stack
3577 pointer, so that the stack pointer does not need to be valid when
3578 the epilogue starts. See EXIT_IGNORE_STACK. */
3579 if (frame_pointer_needed)
3580 setup_spill_pointers (current_frame_info.n_spilled,
3581 hard_frame_pointer_rtx, 0);
3583 setup_spill_pointers (current_frame_info.n_spilled, stack_pointer_rtx,
3584 current_frame_info.total_size);
3586 if (current_frame_info.total_size != 0)
3588 /* ??? At this point we must generate a magic insn that appears to
3589 modify the spill iterators and the frame pointer. This would
3590 allow the most scheduling freedom. For now, just hard stop. */
3591 emit_insn (gen_blockage ());
3594 /* Locate the bottom of the register save area. */
3595 cfa_off = (current_frame_info.spill_cfa_off
3596 + current_frame_info.spill_size
3597 + current_frame_info.extra_spill_size);
3599 /* Restore the predicate registers. */
3600 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
3602 if (current_frame_info.r[reg_save_pr] != 0)
3604 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_pr]);
3605 reg_emitted (reg_save_pr);
3609 alt_regno = next_scratch_gr_reg ();
3610 alt_reg = gen_rtx_REG (DImode, alt_regno);
3611 do_restore (gen_movdi_x, alt_reg, cfa_off);
3614 reg = gen_rtx_REG (DImode, PR_REG (0));
3615 emit_move_insn (reg, alt_reg);
3618 /* Restore the application registers. */
3620 /* Load the saved unat from the stack, but do not restore it until
3621 after the GRs have been restored. */
3622 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
3624 if (current_frame_info.r[reg_save_ar_unat] != 0)
3627 = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_unat]);
3628 reg_emitted (reg_save_ar_unat);
3632 alt_regno = next_scratch_gr_reg ();
3633 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
3634 current_frame_info.gr_used_mask |= 1 << alt_regno;
3635 do_restore (gen_movdi_x, ar_unat_save_reg, cfa_off);
3640 ar_unat_save_reg = NULL_RTX;
3642 if (current_frame_info.r[reg_save_ar_pfs] != 0)
3644 reg_emitted (reg_save_ar_pfs);
3645 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_pfs]);
3646 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3647 emit_move_insn (reg, alt_reg);
3649 else if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM))
3651 alt_regno = next_scratch_gr_reg ();
3652 alt_reg = gen_rtx_REG (DImode, alt_regno);
3653 do_restore (gen_movdi_x, alt_reg, cfa_off);
3655 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3656 emit_move_insn (reg, alt_reg);
3659 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
3661 if (current_frame_info.r[reg_save_ar_lc] != 0)
3663 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_lc]);
3664 reg_emitted (reg_save_ar_lc);
3668 alt_regno = next_scratch_gr_reg ();
3669 alt_reg = gen_rtx_REG (DImode, alt_regno);
3670 do_restore (gen_movdi_x, alt_reg, cfa_off);
3673 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
3674 emit_move_insn (reg, alt_reg);
3677 /* Restore the return pointer. */
3678 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3680 if (current_frame_info.r[reg_save_b0] != 0)
3682 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]);
3683 reg_emitted (reg_save_b0);
3687 alt_regno = next_scratch_gr_reg ();
3688 alt_reg = gen_rtx_REG (DImode, alt_regno);
3689 do_restore (gen_movdi_x, alt_reg, cfa_off);
3692 reg = gen_rtx_REG (DImode, BR_REG (0));
3693 emit_move_insn (reg, alt_reg);
3696 /* We should now be at the base of the gr/br/fr spill area. */
3697 gcc_assert (cfa_off == (current_frame_info.spill_cfa_off
3698 + current_frame_info.spill_size));
3700 /* The GP may be stored on the stack in the prologue, but it's
3701 never restored in the epilogue. Skip the stack slot. */
3702 if (TEST_HARD_REG_BIT (current_frame_info.mask, GR_REG (1)))
3705 /* Restore all general registers. */
3706 for (regno = GR_REG (2); regno <= GR_REG (31); ++regno)
3707 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3709 reg = gen_rtx_REG (DImode, regno);
3710 do_restore (gen_gr_restore, reg, cfa_off);
3714 /* Restore the branch registers. */
3715 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
3716 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3718 alt_regno = next_scratch_gr_reg ();
3719 alt_reg = gen_rtx_REG (DImode, alt_regno);
3720 do_restore (gen_movdi_x, alt_reg, cfa_off);
3722 reg = gen_rtx_REG (DImode, regno);
3723 emit_move_insn (reg, alt_reg);
3726 /* Restore floating point registers. */
3727 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
3728 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3730 gcc_assert (!(cfa_off & 15));
3731 reg = gen_rtx_REG (XFmode, regno);
3732 do_restore (gen_fr_restore_x, reg, cfa_off);
3736 /* Restore ar.unat for real. */
3737 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
3739 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3740 emit_move_insn (reg, ar_unat_save_reg);
3743 gcc_assert (cfa_off == current_frame_info.spill_cfa_off);
3745 finish_spill_pointers ();
3747 if (current_frame_info.total_size
3748 || cfun->machine->ia64_eh_epilogue_sp
3749 || frame_pointer_needed)
3751 /* ??? At this point we must generate a magic insn that appears to
3752 modify the spill iterators, the stack pointer, and the frame
3753 pointer. This would allow the most scheduling freedom. For now,
3755 emit_insn (gen_blockage ());
3758 if (cfun->machine->ia64_eh_epilogue_sp)
3759 emit_move_insn (stack_pointer_rtx, cfun->machine->ia64_eh_epilogue_sp);
3760 else if (frame_pointer_needed)
3762 insn = emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
3763 RTX_FRAME_RELATED_P (insn) = 1;
3764 add_reg_note (insn, REG_CFA_ADJUST_CFA, NULL);
3766 else if (current_frame_info.total_size)
3768 rtx offset, frame_size_rtx;
3770 frame_size_rtx = GEN_INT (current_frame_info.total_size);
3771 if (satisfies_constraint_I (frame_size_rtx))
3772 offset = frame_size_rtx;
3775 regno = next_scratch_gr_reg ();
3776 offset = gen_rtx_REG (DImode, regno);
3777 emit_move_insn (offset, frame_size_rtx);
3780 insn = emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
3783 RTX_FRAME_RELATED_P (insn) = 1;
3784 add_reg_note (insn, REG_CFA_ADJUST_CFA,
3785 gen_rtx_SET (VOIDmode,
3787 gen_rtx_PLUS (DImode,
3792 if (cfun->machine->ia64_eh_epilogue_bsp)
3793 emit_insn (gen_set_bsp (cfun->machine->ia64_eh_epilogue_bsp));
3796 emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode, BR_REG (0))));
3799 int fp = GR_REG (2);
3800 /* We need a throw away register here, r0 and r1 are reserved,
3801 so r2 is the first available call clobbered register. If
3802 there was a frame_pointer register, we may have swapped the
3803 names of r2 and HARD_FRAME_POINTER_REGNUM, so we have to make
3804 sure we're using the string "r2" when emitting the register
3805 name for the assembler. */
3806 if (current_frame_info.r[reg_fp]
3807 && current_frame_info.r[reg_fp] == GR_REG (2))
3808 fp = HARD_FRAME_POINTER_REGNUM;
3810 /* We must emit an alloc to force the input registers to become output
3811 registers. Otherwise, if the callee tries to pass its parameters
3812 through to another call without an intervening alloc, then these
3814 /* ??? We don't need to preserve all input registers. We only need to
3815 preserve those input registers used as arguments to the sibling call.
3816 It is unclear how to compute that number here. */
3817 if (current_frame_info.n_input_regs != 0)
3819 rtx n_inputs = GEN_INT (current_frame_info.n_input_regs);
3820 insn = emit_insn (gen_alloc (gen_rtx_REG (DImode, fp),
3821 const0_rtx, const0_rtx,
3822 n_inputs, const0_rtx));
3823 RTX_FRAME_RELATED_P (insn) = 1;
3828 /* Return 1 if br.ret can do all the work required to return from a
3832 ia64_direct_return (void)
3834 if (reload_completed && ! frame_pointer_needed)
3836 ia64_compute_frame_size (get_frame_size ());
3838 return (current_frame_info.total_size == 0
3839 && current_frame_info.n_spilled == 0
3840 && current_frame_info.r[reg_save_b0] == 0
3841 && current_frame_info.r[reg_save_pr] == 0
3842 && current_frame_info.r[reg_save_ar_pfs] == 0
3843 && current_frame_info.r[reg_save_ar_unat] == 0
3844 && current_frame_info.r[reg_save_ar_lc] == 0);
3849 /* Return the magic cookie that we use to hold the return address
3850 during early compilation. */
3853 ia64_return_addr_rtx (HOST_WIDE_INT count, rtx frame ATTRIBUTE_UNUSED)
3857 return gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_RET_ADDR);
3860 /* Split this value after reload, now that we know where the return
3861 address is saved. */
3864 ia64_split_return_addr_rtx (rtx dest)
3868 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3870 if (current_frame_info.r[reg_save_b0] != 0)
3872 src = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]);
3873 reg_emitted (reg_save_b0);
3881 /* Compute offset from CFA for BR0. */
3882 /* ??? Must be kept in sync with ia64_expand_prologue. */
3883 off = (current_frame_info.spill_cfa_off
3884 + current_frame_info.spill_size);
3885 for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
3886 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3889 /* Convert CFA offset to a register based offset. */
3890 if (frame_pointer_needed)
3891 src = hard_frame_pointer_rtx;
3894 src = stack_pointer_rtx;
3895 off += current_frame_info.total_size;
3898 /* Load address into scratch register. */
3899 off_r = GEN_INT (off);
3900 if (satisfies_constraint_I (off_r))
3901 emit_insn (gen_adddi3 (dest, src, off_r));
3904 emit_move_insn (dest, off_r);
3905 emit_insn (gen_adddi3 (dest, src, dest));
3908 src = gen_rtx_MEM (Pmode, dest);
3912 src = gen_rtx_REG (DImode, BR_REG (0));
3914 emit_move_insn (dest, src);
3918 ia64_hard_regno_rename_ok (int from, int to)
3920 /* Don't clobber any of the registers we reserved for the prologue. */
3923 for (r = reg_fp; r <= reg_save_ar_lc; r++)
3924 if (to == current_frame_info.r[r]
3925 || from == current_frame_info.r[r]
3926 || to == emitted_frame_related_regs[r]
3927 || from == emitted_frame_related_regs[r])
3930 /* Don't use output registers outside the register frame. */
3931 if (OUT_REGNO_P (to) && to >= OUT_REG (current_frame_info.n_output_regs))
3934 /* Retain even/oddness on predicate register pairs. */
3935 if (PR_REGNO_P (from) && PR_REGNO_P (to))
3936 return (from & 1) == (to & 1);
3941 /* Target hook for assembling integer objects. Handle word-sized
3942 aligned objects and detect the cases when @fptr is needed. */
3945 ia64_assemble_integer (rtx x, unsigned int size, int aligned_p)
3947 if (size == POINTER_SIZE / BITS_PER_UNIT
3948 && !(TARGET_NO_PIC || TARGET_AUTO_PIC)
3949 && GET_CODE (x) == SYMBOL_REF
3950 && SYMBOL_REF_FUNCTION_P (x))
3952 static const char * const directive[2][2] = {
3953 /* 64-bit pointer */ /* 32-bit pointer */
3954 { "\tdata8.ua\t@fptr(", "\tdata4.ua\t@fptr("}, /* unaligned */
3955 { "\tdata8\t@fptr(", "\tdata4\t@fptr("} /* aligned */
3957 fputs (directive[(aligned_p != 0)][POINTER_SIZE == 32], asm_out_file);
3958 output_addr_const (asm_out_file, x);
3959 fputs (")\n", asm_out_file);
3962 return default_assemble_integer (x, size, aligned_p);
3965 /* Emit the function prologue. */
3968 ia64_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3970 int mask, grsave, grsave_prev;
3972 if (current_frame_info.need_regstk)
3973 fprintf (file, "\t.regstk %d, %d, %d, %d\n",
3974 current_frame_info.n_input_regs,
3975 current_frame_info.n_local_regs,
3976 current_frame_info.n_output_regs,
3977 current_frame_info.n_rotate_regs);
3979 if (ia64_except_unwind_info (&global_options) != UI_TARGET)
3982 /* Emit the .prologue directive. */
3985 grsave = grsave_prev = 0;
3986 if (current_frame_info.r[reg_save_b0] != 0)
3989 grsave = grsave_prev = current_frame_info.r[reg_save_b0];
3991 if (current_frame_info.r[reg_save_ar_pfs] != 0
3992 && (grsave_prev == 0
3993 || current_frame_info.r[reg_save_ar_pfs] == grsave_prev + 1))
3996 if (grsave_prev == 0)
3997 grsave = current_frame_info.r[reg_save_ar_pfs];
3998 grsave_prev = current_frame_info.r[reg_save_ar_pfs];
4000 if (current_frame_info.r[reg_fp] != 0
4001 && (grsave_prev == 0
4002 || current_frame_info.r[reg_fp] == grsave_prev + 1))
4005 if (grsave_prev == 0)
4006 grsave = HARD_FRAME_POINTER_REGNUM;
4007 grsave_prev = current_frame_info.r[reg_fp];
4009 if (current_frame_info.r[reg_save_pr] != 0
4010 && (grsave_prev == 0
4011 || current_frame_info.r[reg_save_pr] == grsave_prev + 1))
4014 if (grsave_prev == 0)
4015 grsave = current_frame_info.r[reg_save_pr];
4018 if (mask && TARGET_GNU_AS)
4019 fprintf (file, "\t.prologue %d, %d\n", mask,
4020 ia64_dbx_register_number (grsave));
4022 fputs ("\t.prologue\n", file);
4024 /* Emit a .spill directive, if necessary, to relocate the base of
4025 the register spill area. */
4026 if (current_frame_info.spill_cfa_off != -16)
4027 fprintf (file, "\t.spill %ld\n",
4028 (long) (current_frame_info.spill_cfa_off
4029 + current_frame_info.spill_size));
4032 /* Emit the .body directive at the scheduled end of the prologue. */
4035 ia64_output_function_end_prologue (FILE *file)
4037 if (ia64_except_unwind_info (&global_options) != UI_TARGET)
4040 fputs ("\t.body\n", file);
4043 /* Emit the function epilogue. */
4046 ia64_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
4047 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4051 if (current_frame_info.r[reg_fp])
4053 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
4054 reg_names[HARD_FRAME_POINTER_REGNUM]
4055 = reg_names[current_frame_info.r[reg_fp]];
4056 reg_names[current_frame_info.r[reg_fp]] = tmp;
4057 reg_emitted (reg_fp);
4059 if (! TARGET_REG_NAMES)
4061 for (i = 0; i < current_frame_info.n_input_regs; i++)
4062 reg_names[IN_REG (i)] = ia64_input_reg_names[i];
4063 for (i = 0; i < current_frame_info.n_local_regs; i++)
4064 reg_names[LOC_REG (i)] = ia64_local_reg_names[i];
4065 for (i = 0; i < current_frame_info.n_output_regs; i++)
4066 reg_names[OUT_REG (i)] = ia64_output_reg_names[i];
4069 current_frame_info.initialized = 0;
4073 ia64_dbx_register_number (int regno)
4075 /* In ia64_expand_prologue we quite literally renamed the frame pointer
4076 from its home at loc79 to something inside the register frame. We
4077 must perform the same renumbering here for the debug info. */
4078 if (current_frame_info.r[reg_fp])
4080 if (regno == HARD_FRAME_POINTER_REGNUM)
4081 regno = current_frame_info.r[reg_fp];
4082 else if (regno == current_frame_info.r[reg_fp])
4083 regno = HARD_FRAME_POINTER_REGNUM;
4086 if (IN_REGNO_P (regno))
4087 return 32 + regno - IN_REG (0);
4088 else if (LOC_REGNO_P (regno))
4089 return 32 + current_frame_info.n_input_regs + regno - LOC_REG (0);
4090 else if (OUT_REGNO_P (regno))
4091 return (32 + current_frame_info.n_input_regs
4092 + current_frame_info.n_local_regs + regno - OUT_REG (0));
4097 /* Implement TARGET_TRAMPOLINE_INIT.
4099 The trampoline should set the static chain pointer to value placed
4100 into the trampoline and should branch to the specified routine.
4101 To make the normal indirect-subroutine calling convention work,
4102 the trampoline must look like a function descriptor; the first
4103 word being the target address and the second being the target's
4106 We abuse the concept of a global pointer by arranging for it
4107 to point to the data we need to load. The complete trampoline
4108 has the following form:
4110 +-------------------+ \
4111 TRAMP: | __ia64_trampoline | |
4112 +-------------------+ > fake function descriptor
4114 +-------------------+ /
4115 | target descriptor |
4116 +-------------------+
4118 +-------------------+
4122 ia64_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain)
4124 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
4125 rtx addr, addr_reg, tramp, eight = GEN_INT (8);
4127 /* The Intel assembler requires that the global __ia64_trampoline symbol
4128 be declared explicitly */
4131 static bool declared_ia64_trampoline = false;
4133 if (!declared_ia64_trampoline)
4135 declared_ia64_trampoline = true;
4136 (*targetm.asm_out.globalize_label) (asm_out_file,
4137 "__ia64_trampoline");
4141 /* Make sure addresses are Pmode even if we are in ILP32 mode. */
4142 addr = convert_memory_address (Pmode, XEXP (m_tramp, 0));
4143 fnaddr = convert_memory_address (Pmode, fnaddr);
4144 static_chain = convert_memory_address (Pmode, static_chain);
4146 /* Load up our iterator. */
4147 addr_reg = copy_to_reg (addr);
4148 m_tramp = adjust_automodify_address (m_tramp, Pmode, addr_reg, 0);
4150 /* The first two words are the fake descriptor:
4151 __ia64_trampoline, ADDR+16. */
4152 tramp = gen_rtx_SYMBOL_REF (Pmode, "__ia64_trampoline");
4153 if (TARGET_ABI_OPEN_VMS)
4155 /* HP decided to break the ELF ABI on VMS (to deal with an ambiguity
4156 in the Macro-32 compiler) and changed the semantics of the LTOFF22
4157 relocation against function symbols to make it identical to the
4158 LTOFF_FPTR22 relocation. Emit the latter directly to stay within
4159 strict ELF and dereference to get the bare code address. */
4160 rtx reg = gen_reg_rtx (Pmode);
4161 SYMBOL_REF_FLAGS (tramp) |= SYMBOL_FLAG_FUNCTION;
4162 emit_move_insn (reg, tramp);
4163 emit_move_insn (reg, gen_rtx_MEM (Pmode, reg));
4166 emit_move_insn (m_tramp, tramp);
4167 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
4168 m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8);
4170 emit_move_insn (m_tramp, force_reg (Pmode, plus_constant (addr, 16)));
4171 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
4172 m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8);
4174 /* The third word is the target descriptor. */
4175 emit_move_insn (m_tramp, force_reg (Pmode, fnaddr));
4176 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
4177 m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8);
4179 /* The fourth word is the static chain. */
4180 emit_move_insn (m_tramp, static_chain);
4183 /* Do any needed setup for a variadic function. CUM has not been updated
4184 for the last named argument which has type TYPE and mode MODE.
4186 We generate the actual spill instructions during prologue generation. */
4189 ia64_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4190 tree type, int * pretend_size,
4191 int second_time ATTRIBUTE_UNUSED)
4193 CUMULATIVE_ARGS next_cum = *cum;
4195 /* Skip the current argument. */
4196 ia64_function_arg_advance (&next_cum, mode, type, 1);
4198 if (next_cum.words < MAX_ARGUMENT_SLOTS)
4200 int n = MAX_ARGUMENT_SLOTS - next_cum.words;
4201 *pretend_size = n * UNITS_PER_WORD;
4202 cfun->machine->n_varargs = n;
4206 /* Check whether TYPE is a homogeneous floating point aggregate. If
4207 it is, return the mode of the floating point type that appears
4208 in all leafs. If it is not, return VOIDmode.
4210 An aggregate is a homogeneous floating point aggregate is if all
4211 fields/elements in it have the same floating point type (e.g,
4212 SFmode). 128-bit quad-precision floats are excluded.
4214 Variable sized aggregates should never arrive here, since we should
4215 have already decided to pass them by reference. Top-level zero-sized
4216 aggregates are excluded because our parallels crash the middle-end. */
4218 static enum machine_mode
4219 hfa_element_mode (const_tree type, bool nested)
4221 enum machine_mode element_mode = VOIDmode;
4222 enum machine_mode mode;
4223 enum tree_code code = TREE_CODE (type);
4224 int know_element_mode = 0;
4227 if (!nested && (!TYPE_SIZE (type) || integer_zerop (TYPE_SIZE (type))))
4232 case VOID_TYPE: case INTEGER_TYPE: case ENUMERAL_TYPE:
4233 case BOOLEAN_TYPE: case POINTER_TYPE:
4234 case OFFSET_TYPE: case REFERENCE_TYPE: case METHOD_TYPE:
4235 case LANG_TYPE: case FUNCTION_TYPE:
4238 /* Fortran complex types are supposed to be HFAs, so we need to handle
4239 gcc's COMPLEX_TYPEs as HFAs. We need to exclude the integral complex
4242 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_FLOAT
4243 && TYPE_MODE (type) != TCmode)
4244 return GET_MODE_INNER (TYPE_MODE (type));
4249 /* We want to return VOIDmode for raw REAL_TYPEs, but the actual
4250 mode if this is contained within an aggregate. */
4251 if (nested && TYPE_MODE (type) != TFmode)
4252 return TYPE_MODE (type);
4257 return hfa_element_mode (TREE_TYPE (type), 1);
4261 case QUAL_UNION_TYPE:
4262 for (t = TYPE_FIELDS (type); t; t = DECL_CHAIN (t))
4264 if (TREE_CODE (t) != FIELD_DECL)
4267 mode = hfa_element_mode (TREE_TYPE (t), 1);
4268 if (know_element_mode)
4270 if (mode != element_mode)
4273 else if (GET_MODE_CLASS (mode) != MODE_FLOAT)
4277 know_element_mode = 1;
4278 element_mode = mode;
4281 return element_mode;
4284 /* If we reach here, we probably have some front-end specific type
4285 that the backend doesn't know about. This can happen via the
4286 aggregate_value_p call in init_function_start. All we can do is
4287 ignore unknown tree types. */
4294 /* Return the number of words required to hold a quantity of TYPE and MODE
4295 when passed as an argument. */
4297 ia64_function_arg_words (const_tree type, enum machine_mode mode)
4301 if (mode == BLKmode)
4302 words = int_size_in_bytes (type);
4304 words = GET_MODE_SIZE (mode);
4306 return (words + UNITS_PER_WORD - 1) / UNITS_PER_WORD; /* round up */
4309 /* Return the number of registers that should be skipped so the current
4310 argument (described by TYPE and WORDS) will be properly aligned.
4312 Integer and float arguments larger than 8 bytes start at the next
4313 even boundary. Aggregates larger than 8 bytes start at the next
4314 even boundary if the aggregate has 16 byte alignment. Note that
4315 in the 32-bit ABI, TImode and TFmode have only 8-byte alignment
4316 but are still to be aligned in registers.
4318 ??? The ABI does not specify how to handle aggregates with
4319 alignment from 9 to 15 bytes, or greater than 16. We handle them
4320 all as if they had 16 byte alignment. Such aggregates can occur
4321 only if gcc extensions are used. */
4323 ia64_function_arg_offset (const CUMULATIVE_ARGS *cum,
4324 const_tree type, int words)
4326 /* No registers are skipped on VMS. */
4327 if (TARGET_ABI_OPEN_VMS || (cum->words & 1) == 0)
4331 && TREE_CODE (type) != INTEGER_TYPE
4332 && TREE_CODE (type) != REAL_TYPE)
4333 return TYPE_ALIGN (type) > 8 * BITS_PER_UNIT;
4338 /* Return rtx for register where argument is passed, or zero if it is passed
4340 /* ??? 128-bit quad-precision floats are always passed in general
4344 ia64_function_arg_1 (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
4345 const_tree type, bool named, bool incoming)
4347 int basereg = (incoming ? GR_ARG_FIRST : AR_ARG_FIRST);
4348 int words = ia64_function_arg_words (type, mode);
4349 int offset = ia64_function_arg_offset (cum, type, words);
4350 enum machine_mode hfa_mode = VOIDmode;
4352 /* For OPEN VMS, emit the instruction setting up the argument register here,
4353 when we know this will be together with the other arguments setup related
4354 insns. This is not the conceptually best place to do this, but this is
4355 the easiest as we have convenient access to cumulative args info. */
4357 if (TARGET_ABI_OPEN_VMS && mode == VOIDmode && type == void_type_node
4360 unsigned HOST_WIDE_INT regval = cum->words;
4363 for (i = 0; i < 8; i++)
4364 regval |= ((int) cum->atypes[i]) << (i * 3 + 8);
4366 emit_move_insn (gen_rtx_REG (DImode, GR_REG (25)),
4370 /* If all argument slots are used, then it must go on the stack. */
4371 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
4374 /* Check for and handle homogeneous FP aggregates. */
4376 hfa_mode = hfa_element_mode (type, 0);
4378 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
4379 and unprototyped hfas are passed specially. */
4380 if (hfa_mode != VOIDmode && (! cum->prototype || named))
4384 int fp_regs = cum->fp_regs;
4385 int int_regs = cum->words + offset;
4386 int hfa_size = GET_MODE_SIZE (hfa_mode);
4390 /* If prototyped, pass it in FR regs then GR regs.
4391 If not prototyped, pass it in both FR and GR regs.
4393 If this is an SFmode aggregate, then it is possible to run out of
4394 FR regs while GR regs are still left. In that case, we pass the
4395 remaining part in the GR regs. */
4397 /* Fill the FP regs. We do this always. We stop if we reach the end
4398 of the argument, the last FP register, or the last argument slot. */
4400 byte_size = ((mode == BLKmode)
4401 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4402 args_byte_size = int_regs * UNITS_PER_WORD;
4404 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
4405 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD)); i++)
4407 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4408 gen_rtx_REG (hfa_mode, (FR_ARG_FIRST
4412 args_byte_size += hfa_size;
4416 /* If no prototype, then the whole thing must go in GR regs. */
4417 if (! cum->prototype)
4419 /* If this is an SFmode aggregate, then we might have some left over
4420 that needs to go in GR regs. */
4421 else if (byte_size != offset)
4422 int_regs += offset / UNITS_PER_WORD;
4424 /* Fill in the GR regs. We must use DImode here, not the hfa mode. */
4426 for (; offset < byte_size && int_regs < MAX_ARGUMENT_SLOTS; i++)
4428 enum machine_mode gr_mode = DImode;
4429 unsigned int gr_size;
4431 /* If we have an odd 4 byte hunk because we ran out of FR regs,
4432 then this goes in a GR reg left adjusted/little endian, right
4433 adjusted/big endian. */
4434 /* ??? Currently this is handled wrong, because 4-byte hunks are
4435 always right adjusted/little endian. */
4438 /* If we have an even 4 byte hunk because the aggregate is a
4439 multiple of 4 bytes in size, then this goes in a GR reg right
4440 adjusted/little endian. */
4441 else if (byte_size - offset == 4)
4444 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4445 gen_rtx_REG (gr_mode, (basereg
4449 gr_size = GET_MODE_SIZE (gr_mode);
4451 if (gr_size == UNITS_PER_WORD
4452 || (gr_size < UNITS_PER_WORD && offset % UNITS_PER_WORD == 0))
4454 else if (gr_size > UNITS_PER_WORD)
4455 int_regs += gr_size / UNITS_PER_WORD;
4457 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4460 /* On OpenVMS variable argument is either in Rn or Fn. */
4461 else if (TARGET_ABI_OPEN_VMS && named == 0)
4463 if (FLOAT_MODE_P (mode))
4464 return gen_rtx_REG (mode, FR_ARG_FIRST + cum->words);
4466 return gen_rtx_REG (mode, basereg + cum->words);
4469 /* Integral and aggregates go in general registers. If we have run out of
4470 FR registers, then FP values must also go in general registers. This can
4471 happen when we have a SFmode HFA. */
4472 else if (mode == TFmode || mode == TCmode
4473 || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
4475 int byte_size = ((mode == BLKmode)
4476 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4477 if (BYTES_BIG_ENDIAN
4478 && (mode == BLKmode || (type && AGGREGATE_TYPE_P (type)))
4479 && byte_size < UNITS_PER_WORD
4482 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
4483 gen_rtx_REG (DImode,
4484 (basereg + cum->words
4487 return gen_rtx_PARALLEL (mode, gen_rtvec (1, gr_reg));
4490 return gen_rtx_REG (mode, basereg + cum->words + offset);
4494 /* If there is a prototype, then FP values go in a FR register when
4495 named, and in a GR register when unnamed. */
4496 else if (cum->prototype)
4499 return gen_rtx_REG (mode, FR_ARG_FIRST + cum->fp_regs);
4500 /* In big-endian mode, an anonymous SFmode value must be represented
4501 as (parallel:SF [(expr_list (reg:DI n) (const_int 0))]) to force
4502 the value into the high half of the general register. */
4503 else if (BYTES_BIG_ENDIAN && mode == SFmode)
4504 return gen_rtx_PARALLEL (mode,
4506 gen_rtx_EXPR_LIST (VOIDmode,
4507 gen_rtx_REG (DImode, basereg + cum->words + offset),
4510 return gen_rtx_REG (mode, basereg + cum->words + offset);
4512 /* If there is no prototype, then FP values go in both FR and GR
4516 /* See comment above. */
4517 enum machine_mode inner_mode =
4518 (BYTES_BIG_ENDIAN && mode == SFmode) ? DImode : mode;
4520 rtx fp_reg = gen_rtx_EXPR_LIST (VOIDmode,
4521 gen_rtx_REG (mode, (FR_ARG_FIRST
4524 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
4525 gen_rtx_REG (inner_mode,
4526 (basereg + cum->words
4530 return gen_rtx_PARALLEL (mode, gen_rtvec (2, fp_reg, gr_reg));
4534 /* Implement TARGET_FUNCION_ARG target hook. */
4537 ia64_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4538 const_tree type, bool named)
4540 return ia64_function_arg_1 (cum, mode, type, named, false);
4543 /* Implement TARGET_FUNCION_INCOMING_ARG target hook. */
4546 ia64_function_incoming_arg (CUMULATIVE_ARGS *cum,
4547 enum machine_mode mode,
4548 const_tree type, bool named)
4550 return ia64_function_arg_1 (cum, mode, type, named, true);
4553 /* Return number of bytes, at the beginning of the argument, that must be
4554 put in registers. 0 is the argument is entirely in registers or entirely
4558 ia64_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4559 tree type, bool named ATTRIBUTE_UNUSED)
4561 int words = ia64_function_arg_words (type, mode);
4562 int offset = ia64_function_arg_offset (cum, type, words);
4564 /* If all argument slots are used, then it must go on the stack. */
4565 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
4568 /* It doesn't matter whether the argument goes in FR or GR regs. If
4569 it fits within the 8 argument slots, then it goes entirely in
4570 registers. If it extends past the last argument slot, then the rest
4571 goes on the stack. */
4573 if (words + cum->words + offset <= MAX_ARGUMENT_SLOTS)
4576 return (MAX_ARGUMENT_SLOTS - cum->words - offset) * UNITS_PER_WORD;
4579 /* Return ivms_arg_type based on machine_mode. */
4581 static enum ivms_arg_type
4582 ia64_arg_type (enum machine_mode mode)
4595 /* Update CUM to point after this argument. This is patterned after
4596 ia64_function_arg. */
4599 ia64_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4600 const_tree type, bool named)
4602 int words = ia64_function_arg_words (type, mode);
4603 int offset = ia64_function_arg_offset (cum, type, words);
4604 enum machine_mode hfa_mode = VOIDmode;
4606 /* If all arg slots are already full, then there is nothing to do. */
4607 if (cum->words >= MAX_ARGUMENT_SLOTS)
4609 cum->words += words + offset;
4613 cum->atypes[cum->words] = ia64_arg_type (mode);
4614 cum->words += words + offset;
4616 /* Check for and handle homogeneous FP aggregates. */
4618 hfa_mode = hfa_element_mode (type, 0);
4620 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
4621 and unprototyped hfas are passed specially. */
4622 if (hfa_mode != VOIDmode && (! cum->prototype || named))
4624 int fp_regs = cum->fp_regs;
4625 /* This is the original value of cum->words + offset. */
4626 int int_regs = cum->words - words;
4627 int hfa_size = GET_MODE_SIZE (hfa_mode);
4631 /* If prototyped, pass it in FR regs then GR regs.
4632 If not prototyped, pass it in both FR and GR regs.
4634 If this is an SFmode aggregate, then it is possible to run out of
4635 FR regs while GR regs are still left. In that case, we pass the
4636 remaining part in the GR regs. */
4638 /* Fill the FP regs. We do this always. We stop if we reach the end
4639 of the argument, the last FP register, or the last argument slot. */
4641 byte_size = ((mode == BLKmode)
4642 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4643 args_byte_size = int_regs * UNITS_PER_WORD;
4645 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
4646 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD));)
4649 args_byte_size += hfa_size;
4653 cum->fp_regs = fp_regs;
4656 /* On OpenVMS variable argument is either in Rn or Fn. */
4657 else if (TARGET_ABI_OPEN_VMS && named == 0)
4659 cum->int_regs = cum->words;
4660 cum->fp_regs = cum->words;
4663 /* Integral and aggregates go in general registers. So do TFmode FP values.
4664 If we have run out of FR registers, then other FP values must also go in
4665 general registers. This can happen when we have a SFmode HFA. */
4666 else if (mode == TFmode || mode == TCmode
4667 || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
4668 cum->int_regs = cum->words;
4670 /* If there is a prototype, then FP values go in a FR register when
4671 named, and in a GR register when unnamed. */
4672 else if (cum->prototype)
4675 cum->int_regs = cum->words;
4677 /* ??? Complex types should not reach here. */
4678 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
4680 /* If there is no prototype, then FP values go in both FR and GR
4684 /* ??? Complex types should not reach here. */
4685 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
4686 cum->int_regs = cum->words;
4690 /* Arguments with alignment larger than 8 bytes start at the next even
4691 boundary. On ILP32 HPUX, TFmode arguments start on next even boundary
4692 even though their normal alignment is 8 bytes. See ia64_function_arg. */
4695 ia64_function_arg_boundary (enum machine_mode mode, const_tree type)
4697 if (mode == TFmode && TARGET_HPUX && TARGET_ILP32)
4698 return PARM_BOUNDARY * 2;
4702 if (TYPE_ALIGN (type) > PARM_BOUNDARY)
4703 return PARM_BOUNDARY * 2;
4705 return PARM_BOUNDARY;
4708 if (GET_MODE_BITSIZE (mode) > PARM_BOUNDARY)
4709 return PARM_BOUNDARY * 2;
4711 return PARM_BOUNDARY;
4714 /* True if it is OK to do sibling call optimization for the specified
4715 call expression EXP. DECL will be the called function, or NULL if
4716 this is an indirect call. */
4718 ia64_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
4720 /* We can't perform a sibcall if the current function has the syscall_linkage
4722 if (lookup_attribute ("syscall_linkage",
4723 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
4726 /* We must always return with our current GP. This means we can
4727 only sibcall to functions defined in the current module unless
4728 TARGET_CONST_GP is set to true. */
4729 return (decl && (*targetm.binds_local_p) (decl)) || TARGET_CONST_GP;
4733 /* Implement va_arg. */
4736 ia64_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
4739 /* Variable sized types are passed by reference. */
4740 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
4742 tree ptrtype = build_pointer_type (type);
4743 tree addr = std_gimplify_va_arg_expr (valist, ptrtype, pre_p, post_p);
4744 return build_va_arg_indirect_ref (addr);
4747 /* Aggregate arguments with alignment larger than 8 bytes start at
4748 the next even boundary. Integer and floating point arguments
4749 do so if they are larger than 8 bytes, whether or not they are
4750 also aligned larger than 8 bytes. */
4751 if ((TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == INTEGER_TYPE)
4752 ? int_size_in_bytes (type) > 8 : TYPE_ALIGN (type) > 8 * BITS_PER_UNIT)
4754 tree t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (valist), valist,
4755 size_int (2 * UNITS_PER_WORD - 1));
4756 t = fold_convert (sizetype, t);
4757 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
4758 size_int (-2 * UNITS_PER_WORD));
4759 t = fold_convert (TREE_TYPE (valist), t);
4760 gimplify_assign (unshare_expr (valist), t, pre_p);
4763 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4766 /* Return 1 if function return value returned in memory. Return 0 if it is
4770 ia64_return_in_memory (const_tree valtype, const_tree fntype ATTRIBUTE_UNUSED)
4772 enum machine_mode mode;
4773 enum machine_mode hfa_mode;
4774 HOST_WIDE_INT byte_size;
4776 mode = TYPE_MODE (valtype);
4777 byte_size = GET_MODE_SIZE (mode);
4778 if (mode == BLKmode)
4780 byte_size = int_size_in_bytes (valtype);
4785 /* Hfa's with up to 8 elements are returned in the FP argument registers. */
4787 hfa_mode = hfa_element_mode (valtype, 0);
4788 if (hfa_mode != VOIDmode)
4790 int hfa_size = GET_MODE_SIZE (hfa_mode);
4792 if (byte_size / hfa_size > MAX_ARGUMENT_SLOTS)
4797 else if (byte_size > UNITS_PER_WORD * MAX_INT_RETURN_SLOTS)
4803 /* Return rtx for register that holds the function return value. */
4806 ia64_function_value (const_tree valtype,
4807 const_tree fn_decl_or_type,
4808 bool outgoing ATTRIBUTE_UNUSED)
4810 enum machine_mode mode;
4811 enum machine_mode hfa_mode;
4813 const_tree func = fn_decl_or_type;
4816 && !DECL_P (fn_decl_or_type))
4819 mode = TYPE_MODE (valtype);
4820 hfa_mode = hfa_element_mode (valtype, 0);
4822 if (hfa_mode != VOIDmode)
4830 hfa_size = GET_MODE_SIZE (hfa_mode);
4831 byte_size = ((mode == BLKmode)
4832 ? int_size_in_bytes (valtype) : GET_MODE_SIZE (mode));
4834 for (i = 0; offset < byte_size; i++)
4836 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4837 gen_rtx_REG (hfa_mode, FR_ARG_FIRST + i),
4841 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4843 else if (FLOAT_TYPE_P (valtype) && mode != TFmode && mode != TCmode)
4844 return gen_rtx_REG (mode, FR_ARG_FIRST);
4847 bool need_parallel = false;
4849 /* In big-endian mode, we need to manage the layout of aggregates
4850 in the registers so that we get the bits properly aligned in
4851 the highpart of the registers. */
4852 if (BYTES_BIG_ENDIAN
4853 && (mode == BLKmode || (valtype && AGGREGATE_TYPE_P (valtype))))
4854 need_parallel = true;
4856 /* Something like struct S { long double x; char a[0] } is not an
4857 HFA structure, and therefore doesn't go in fp registers. But
4858 the middle-end will give it XFmode anyway, and XFmode values
4859 don't normally fit in integer registers. So we need to smuggle
4860 the value inside a parallel. */
4861 else if (mode == XFmode || mode == XCmode || mode == RFmode)
4862 need_parallel = true;
4872 bytesize = int_size_in_bytes (valtype);
4873 /* An empty PARALLEL is invalid here, but the return value
4874 doesn't matter for empty structs. */
4876 return gen_rtx_REG (mode, GR_RET_FIRST);
4877 for (i = 0; offset < bytesize; i++)
4879 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4880 gen_rtx_REG (DImode,
4883 offset += UNITS_PER_WORD;
4885 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4888 mode = ia64_promote_function_mode (valtype, mode, &unsignedp,
4889 func ? TREE_TYPE (func) : NULL_TREE,
4892 return gen_rtx_REG (mode, GR_RET_FIRST);
4896 /* Worker function for TARGET_LIBCALL_VALUE. */
4899 ia64_libcall_value (enum machine_mode mode,
4900 const_rtx fun ATTRIBUTE_UNUSED)
4902 return gen_rtx_REG (mode,
4903 (((GET_MODE_CLASS (mode) == MODE_FLOAT
4904 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4905 && (mode) != TFmode)
4906 ? FR_RET_FIRST : GR_RET_FIRST));
4909 /* Worker function for FUNCTION_VALUE_REGNO_P. */
4912 ia64_function_value_regno_p (const unsigned int regno)
4914 return ((regno >= GR_RET_FIRST && regno <= GR_RET_LAST)
4915 || (regno >= FR_RET_FIRST && regno <= FR_RET_LAST));
4918 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4919 We need to emit DTP-relative relocations. */
4922 ia64_output_dwarf_dtprel (FILE *file, int size, rtx x)
4924 gcc_assert (size == 4 || size == 8);
4926 fputs ("\tdata4.ua\t@dtprel(", file);
4928 fputs ("\tdata8.ua\t@dtprel(", file);
4929 output_addr_const (file, x);
4933 /* Print a memory address as an operand to reference that memory location. */
4935 /* ??? Do we need this? It gets used only for 'a' operands. We could perhaps
4936 also call this from ia64_print_operand for memory addresses. */
4939 ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED,
4940 rtx address ATTRIBUTE_UNUSED)
4944 /* Print an operand to an assembler instruction.
4945 C Swap and print a comparison operator.
4946 D Print an FP comparison operator.
4947 E Print 32 - constant, for SImode shifts as extract.
4948 e Print 64 - constant, for DImode rotates.
4949 F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
4950 a floating point register emitted normally.
4951 G A floating point constant.
4952 I Invert a predicate register by adding 1.
4953 J Select the proper predicate register for a condition.
4954 j Select the inverse predicate register for a condition.
4955 O Append .acq for volatile load.
4956 P Postincrement of a MEM.
4957 Q Append .rel for volatile store.
4958 R Print .s .d or nothing for a single, double or no truncation.
4959 S Shift amount for shladd instruction.
4960 T Print an 8-bit sign extended number (K) as a 32-bit unsigned number
4961 for Intel assembler.
4962 U Print an 8-bit sign extended number (K) as a 64-bit unsigned number
4963 for Intel assembler.
4964 X A pair of floating point registers.
4965 r Print register name, or constant 0 as r0. HP compatibility for
4967 v Print vector constant value as an 8-byte integer value. */
4970 ia64_print_operand (FILE * file, rtx x, int code)
4977 /* Handled below. */
4982 enum rtx_code c = swap_condition (GET_CODE (x));
4983 fputs (GET_RTX_NAME (c), file);
4988 switch (GET_CODE (x))
5012 str = GET_RTX_NAME (GET_CODE (x));
5019 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - INTVAL (x));
5023 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - INTVAL (x));
5027 if (x == CONST0_RTX (GET_MODE (x)))
5028 str = reg_names [FR_REG (0)];
5029 else if (x == CONST1_RTX (GET_MODE (x)))
5030 str = reg_names [FR_REG (1)];
5033 gcc_assert (GET_CODE (x) == REG);
5034 str = reg_names [REGNO (x)];
5043 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
5044 real_to_target (val, &rv, GET_MODE (x));
5045 if (GET_MODE (x) == SFmode)
5046 fprintf (file, "0x%08lx", val[0] & 0xffffffff);
5047 else if (GET_MODE (x) == DFmode)
5048 fprintf (file, "0x%08lx%08lx", (WORDS_BIG_ENDIAN ? val[0] : val[1])
5050 (WORDS_BIG_ENDIAN ? val[1] : val[0])
5053 output_operand_lossage ("invalid %%G mode");
5058 fputs (reg_names [REGNO (x) + 1], file);
5064 unsigned int regno = REGNO (XEXP (x, 0));
5065 if (GET_CODE (x) == EQ)
5069 fputs (reg_names [regno], file);
5074 if (MEM_VOLATILE_P (x))
5075 fputs(".acq", file);
5080 HOST_WIDE_INT value;
5082 switch (GET_CODE (XEXP (x, 0)))
5088 x = XEXP (XEXP (XEXP (x, 0), 1), 1);
5089 if (GET_CODE (x) == CONST_INT)
5093 gcc_assert (GET_CODE (x) == REG);
5094 fprintf (file, ", %s", reg_names[REGNO (x)]);
5100 value = GET_MODE_SIZE (GET_MODE (x));
5104 value = - (HOST_WIDE_INT) GET_MODE_SIZE (GET_MODE (x));
5108 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC, value);
5113 if (MEM_VOLATILE_P (x))
5114 fputs(".rel", file);
5118 if (x == CONST0_RTX (GET_MODE (x)))
5120 else if (x == CONST1_RTX (GET_MODE (x)))
5122 else if (x == CONST2_RTX (GET_MODE (x)))
5125 output_operand_lossage ("invalid %%R value");
5129 fprintf (file, "%d", exact_log2 (INTVAL (x)));
5133 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
5135 fprintf (file, "0x%x", (int) INTVAL (x) & 0xffffffff);
5141 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
5143 const char *prefix = "0x";
5144 if (INTVAL (x) & 0x80000000)
5146 fprintf (file, "0xffffffff");
5149 fprintf (file, "%s%x", prefix, (int) INTVAL (x) & 0xffffffff);
5156 unsigned int regno = REGNO (x);
5157 fprintf (file, "%s, %s", reg_names [regno], reg_names [regno + 1]);
5162 /* If this operand is the constant zero, write it as register zero.
5163 Any register, zero, or CONST_INT value is OK here. */
5164 if (GET_CODE (x) == REG)
5165 fputs (reg_names[REGNO (x)], file);
5166 else if (x == CONST0_RTX (GET_MODE (x)))
5168 else if (GET_CODE (x) == CONST_INT)
5169 output_addr_const (file, x);
5171 output_operand_lossage ("invalid %%r value");
5175 gcc_assert (GET_CODE (x) == CONST_VECTOR);
5176 x = simplify_subreg (DImode, x, GET_MODE (x), 0);
5183 /* For conditional branches, returns or calls, substitute
5184 sptk, dptk, dpnt, or spnt for %s. */
5185 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
5188 int pred_val = INTVAL (XEXP (x, 0));
5190 /* Guess top and bottom 10% statically predicted. */
5191 if (pred_val < REG_BR_PROB_BASE / 50
5192 && br_prob_note_reliable_p (x))
5194 else if (pred_val < REG_BR_PROB_BASE / 2)
5196 else if (pred_val < REG_BR_PROB_BASE / 100 * 98
5197 || !br_prob_note_reliable_p (x))
5202 else if (GET_CODE (current_output_insn) == CALL_INSN)
5207 fputs (which, file);
5212 x = current_insn_predicate;
5215 unsigned int regno = REGNO (XEXP (x, 0));
5216 if (GET_CODE (x) == EQ)
5218 fprintf (file, "(%s) ", reg_names [regno]);
5223 output_operand_lossage ("ia64_print_operand: unknown code");
5227 switch (GET_CODE (x))
5229 /* This happens for the spill/restore instructions. */
5234 /* ... fall through ... */
5237 fputs (reg_names [REGNO (x)], file);
5242 rtx addr = XEXP (x, 0);
5243 if (GET_RTX_CLASS (GET_CODE (addr)) == RTX_AUTOINC)
5244 addr = XEXP (addr, 0);
5245 fprintf (file, "[%s]", reg_names [REGNO (addr)]);
5250 output_addr_const (file, x);
5257 /* Compute a (partial) cost for rtx X. Return true if the complete
5258 cost has been computed, and false if subexpressions should be
5259 scanned. In either case, *TOTAL contains the cost result. */
5260 /* ??? This is incomplete. */
5263 ia64_rtx_costs (rtx x, int code, int outer_code, int *total,
5264 bool speed ATTRIBUTE_UNUSED)
5272 *total = satisfies_constraint_J (x) ? 0 : COSTS_N_INSNS (1);
5275 if (satisfies_constraint_I (x))
5277 else if (satisfies_constraint_J (x))
5280 *total = COSTS_N_INSNS (1);
5283 if (satisfies_constraint_K (x) || satisfies_constraint_L (x))
5286 *total = COSTS_N_INSNS (1);
5291 *total = COSTS_N_INSNS (1);
5297 *total = COSTS_N_INSNS (3);
5301 *total = COSTS_N_INSNS (4);
5305 /* For multiplies wider than HImode, we have to go to the FPU,
5306 which normally involves copies. Plus there's the latency
5307 of the multiply itself, and the latency of the instructions to
5308 transfer integer regs to FP regs. */
5309 if (FLOAT_MODE_P (GET_MODE (x)))
5310 *total = COSTS_N_INSNS (4);
5311 else if (GET_MODE_SIZE (GET_MODE (x)) > 2)
5312 *total = COSTS_N_INSNS (10);
5314 *total = COSTS_N_INSNS (2);
5319 if (FLOAT_MODE_P (GET_MODE (x)))
5321 *total = COSTS_N_INSNS (4);
5329 *total = COSTS_N_INSNS (1);
5336 /* We make divide expensive, so that divide-by-constant will be
5337 optimized to a multiply. */
5338 *total = COSTS_N_INSNS (60);
5346 /* Calculate the cost of moving data from a register in class FROM to
5347 one in class TO, using MODE. */
5350 ia64_register_move_cost (enum machine_mode mode, reg_class_t from_i,
5353 enum reg_class from = (enum reg_class) from_i;
5354 enum reg_class to = (enum reg_class) to_i;
5356 /* ADDL_REGS is the same as GR_REGS for movement purposes. */
5357 if (to == ADDL_REGS)
5359 if (from == ADDL_REGS)
5362 /* All costs are symmetric, so reduce cases by putting the
5363 lower number class as the destination. */
5366 enum reg_class tmp = to;
5367 to = from, from = tmp;
5370 /* Moving from FR<->GR in XFmode must be more expensive than 2,
5371 so that we get secondary memory reloads. Between FR_REGS,
5372 we have to make this at least as expensive as memory_move_cost
5373 to avoid spectacularly poor register class preferencing. */
5374 if (mode == XFmode || mode == RFmode)
5376 if (to != GR_REGS || from != GR_REGS)
5377 return memory_move_cost (mode, to, false);
5385 /* Moving between PR registers takes two insns. */
5386 if (from == PR_REGS)
5388 /* Moving between PR and anything but GR is impossible. */
5389 if (from != GR_REGS)
5390 return memory_move_cost (mode, to, false);
5394 /* Moving between BR and anything but GR is impossible. */
5395 if (from != GR_REGS && from != GR_AND_BR_REGS)
5396 return memory_move_cost (mode, to, false);
5401 /* Moving between AR and anything but GR is impossible. */
5402 if (from != GR_REGS)
5403 return memory_move_cost (mode, to, false);
5409 case GR_AND_FR_REGS:
5410 case GR_AND_BR_REGS:
5421 /* Calculate the cost of moving data of MODE from a register to or from
5425 ia64_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
5427 bool in ATTRIBUTE_UNUSED)
5429 if (rclass == GENERAL_REGS
5430 || rclass == FR_REGS
5431 || rclass == FP_REGS
5432 || rclass == GR_AND_FR_REGS)
5438 /* Implement TARGET_PREFERRED_RELOAD_CLASS. Place additional restrictions
5439 on RCLASS to use when copying X into that class. */
5442 ia64_preferred_reload_class (rtx x, reg_class_t rclass)
5448 /* Don't allow volatile mem reloads into floating point registers.
5449 This is defined to force reload to choose the r/m case instead
5450 of the f/f case when reloading (set (reg fX) (mem/v)). */
5451 if (MEM_P (x) && MEM_VOLATILE_P (x))
5454 /* Force all unrecognized constants into the constant pool. */
5472 /* This function returns the register class required for a secondary
5473 register when copying between one of the registers in RCLASS, and X,
5474 using MODE. A return value of NO_REGS means that no secondary register
5478 ia64_secondary_reload_class (enum reg_class rclass,
5479 enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
5483 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
5484 regno = true_regnum (x);
5491 /* ??? BR<->BR register copies can happen due to a bad gcse/cse/global
5492 interaction. We end up with two pseudos with overlapping lifetimes
5493 both of which are equiv to the same constant, and both which need
5494 to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end
5495 changes depending on the path length, which means the qty_first_reg
5496 check in make_regs_eqv can give different answers at different times.
5497 At some point I'll probably need a reload_indi pattern to handle
5500 We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we
5501 wound up with a FP register from GR_AND_FR_REGS. Extend that to all
5502 non-general registers for good measure. */
5503 if (regno >= 0 && ! GENERAL_REGNO_P (regno))
5506 /* This is needed if a pseudo used as a call_operand gets spilled to a
5508 if (GET_CODE (x) == MEM)
5514 /* Need to go through general registers to get to other class regs. */
5515 if (regno >= 0 && ! (FR_REGNO_P (regno) || GENERAL_REGNO_P (regno)))
5518 /* This can happen when a paradoxical subreg is an operand to the
5520 /* ??? This shouldn't be necessary after instruction scheduling is
5521 enabled, because paradoxical subregs are not accepted by
5522 register_operand when INSN_SCHEDULING is defined. Or alternatively,
5523 stop the paradoxical subreg stupidity in the *_operand functions
5525 if (GET_CODE (x) == MEM
5526 && (GET_MODE (x) == SImode || GET_MODE (x) == HImode
5527 || GET_MODE (x) == QImode))
5530 /* This can happen because of the ior/and/etc patterns that accept FP
5531 registers as operands. If the third operand is a constant, then it
5532 needs to be reloaded into a FP register. */
5533 if (GET_CODE (x) == CONST_INT)
5536 /* This can happen because of register elimination in a muldi3 insn.
5537 E.g. `26107 * (unsigned long)&u'. */
5538 if (GET_CODE (x) == PLUS)
5543 /* ??? This happens if we cse/gcse a BImode value across a call,
5544 and the function has a nonlocal goto. This is because global
5545 does not allocate call crossing pseudos to hard registers when
5546 crtl->has_nonlocal_goto is true. This is relatively
5547 common for C++ programs that use exceptions. To reproduce,
5548 return NO_REGS and compile libstdc++. */
5549 if (GET_CODE (x) == MEM)
5552 /* This can happen when we take a BImode subreg of a DImode value,
5553 and that DImode value winds up in some non-GR register. */
5554 if (regno >= 0 && ! GENERAL_REGNO_P (regno) && ! PR_REGNO_P (regno))
5566 /* Implement targetm.unspec_may_trap_p hook. */
5568 ia64_unspec_may_trap_p (const_rtx x, unsigned flags)
5570 if (GET_CODE (x) == UNSPEC)
5572 switch (XINT (x, 1))
5578 case UNSPEC_CHKACLR:
5580 /* These unspecs are just wrappers. */
5581 return may_trap_p_1 (XVECEXP (x, 0, 0), flags);
5585 return default_unspec_may_trap_p (x, flags);
5589 /* Parse the -mfixed-range= option string. */
5592 fix_range (const char *const_str)
5595 char *str, *dash, *comma;
5597 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
5598 REG2 are either register names or register numbers. The effect
5599 of this option is to mark the registers in the range from REG1 to
5600 REG2 as ``fixed'' so they won't be used by the compiler. This is
5601 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
5603 i = strlen (const_str);
5604 str = (char *) alloca (i + 1);
5605 memcpy (str, const_str, i + 1);
5609 dash = strchr (str, '-');
5612 warning (0, "value of -mfixed-range must have form REG1-REG2");
5617 comma = strchr (dash + 1, ',');
5621 first = decode_reg_name (str);
5624 warning (0, "unknown register name: %s", str);
5628 last = decode_reg_name (dash + 1);
5631 warning (0, "unknown register name: %s", dash + 1);
5639 warning (0, "%s-%s is an empty range", str, dash + 1);
5643 for (i = first; i <= last; ++i)
5644 fixed_regs[i] = call_used_regs[i] = 1;
5654 /* Implement TARGET_HANDLE_OPTION. */
5657 ia64_handle_option (struct gcc_options *opts ATTRIBUTE_UNUSED,
5658 struct gcc_options *opts_set ATTRIBUTE_UNUSED,
5659 const struct cl_decoded_option *decoded,
5662 size_t code = decoded->opt_index;
5663 const char *arg = decoded->arg;
5664 int value = decoded->value;
5668 case OPT_mtls_size_:
5669 if (value != 14 && value != 22 && value != 64)
5670 error_at (loc, "bad value %<%s%> for -mtls-size= switch", arg);
5678 /* Implement TARGET_OPTION_OVERRIDE. */
5681 ia64_option_override (void)
5684 cl_deferred_option *opt;
5685 VEC(cl_deferred_option,heap) *vec
5686 = (VEC(cl_deferred_option,heap) *) ia64_deferred_options;
5688 FOR_EACH_VEC_ELT (cl_deferred_option, vec, i, opt)
5690 switch (opt->opt_index)
5692 case OPT_mfixed_range_:
5693 fix_range (opt->arg);
5701 if (TARGET_AUTO_PIC)
5702 target_flags |= MASK_CONST_GP;
5704 /* Numerous experiment shows that IRA based loop pressure
5705 calculation works better for RTL loop invariant motion on targets
5706 with enough (>= 32) registers. It is an expensive optimization.
5707 So it is on only for peak performance. */
5709 flag_ira_loop_pressure = 1;
5712 ia64_section_threshold = (global_options_set.x_g_switch_value
5714 : IA64_DEFAULT_GVALUE);
5716 init_machine_status = ia64_init_machine_status;
5718 if (align_functions <= 0)
5719 align_functions = 64;
5720 if (align_loops <= 0)
5722 if (TARGET_ABI_OPEN_VMS)
5725 ia64_override_options_after_change();
5728 /* Implement targetm.override_options_after_change. */
5731 ia64_override_options_after_change (void)
5733 ia64_flag_schedule_insns2 = flag_schedule_insns_after_reload;
5734 flag_schedule_insns_after_reload = 0;
5737 && !global_options_set.x_flag_selective_scheduling
5738 && !global_options_set.x_flag_selective_scheduling2)
5740 flag_selective_scheduling2 = 1;
5741 flag_sel_sched_pipelining = 1;
5743 if (mflag_sched_control_spec == 2)
5745 /* Control speculation is on by default for the selective scheduler,
5746 but not for the Haifa scheduler. */
5747 mflag_sched_control_spec = flag_selective_scheduling2 ? 1 : 0;
5749 if (flag_sel_sched_pipelining && flag_auto_inc_dec)
5751 /* FIXME: remove this when we'd implement breaking autoinsns as
5752 a transformation. */
5753 flag_auto_inc_dec = 0;
5757 /* Initialize the record of emitted frame related registers. */
5759 void ia64_init_expanders (void)
5761 memset (&emitted_frame_related_regs, 0, sizeof (emitted_frame_related_regs));
5764 static struct machine_function *
5765 ia64_init_machine_status (void)
5767 return ggc_alloc_cleared_machine_function ();
5770 static enum attr_itanium_class ia64_safe_itanium_class (rtx);
5771 static enum attr_type ia64_safe_type (rtx);
5773 static enum attr_itanium_class
5774 ia64_safe_itanium_class (rtx insn)
5776 if (recog_memoized (insn) >= 0)
5777 return get_attr_itanium_class (insn);
5778 else if (DEBUG_INSN_P (insn))
5779 return ITANIUM_CLASS_IGNORE;
5781 return ITANIUM_CLASS_UNKNOWN;
5784 static enum attr_type
5785 ia64_safe_type (rtx insn)
5787 if (recog_memoized (insn) >= 0)
5788 return get_attr_type (insn);
5790 return TYPE_UNKNOWN;
5793 /* The following collection of routines emit instruction group stop bits as
5794 necessary to avoid dependencies. */
5796 /* Need to track some additional registers as far as serialization is
5797 concerned so we can properly handle br.call and br.ret. We could
5798 make these registers visible to gcc, but since these registers are
5799 never explicitly used in gcc generated code, it seems wasteful to
5800 do so (plus it would make the call and return patterns needlessly
5802 #define REG_RP (BR_REG (0))
5803 #define REG_AR_CFM (FIRST_PSEUDO_REGISTER + 1)
5804 /* This is used for volatile asms which may require a stop bit immediately
5805 before and after them. */
5806 #define REG_VOLATILE (FIRST_PSEUDO_REGISTER + 2)
5807 #define AR_UNAT_BIT_0 (FIRST_PSEUDO_REGISTER + 3)
5808 #define NUM_REGS (AR_UNAT_BIT_0 + 64)
5810 /* For each register, we keep track of how it has been written in the
5811 current instruction group.
5813 If a register is written unconditionally (no qualifying predicate),
5814 WRITE_COUNT is set to 2 and FIRST_PRED is ignored.
5816 If a register is written if its qualifying predicate P is true, we
5817 set WRITE_COUNT to 1 and FIRST_PRED to P. Later on, the same register
5818 may be written again by the complement of P (P^1) and when this happens,
5819 WRITE_COUNT gets set to 2.
5821 The result of this is that whenever an insn attempts to write a register
5822 whose WRITE_COUNT is two, we need to issue an insn group barrier first.
5824 If a predicate register is written by a floating-point insn, we set
5825 WRITTEN_BY_FP to true.
5827 If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND
5828 to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true. */
5830 #if GCC_VERSION >= 4000
5831 #define RWS_FIELD_TYPE __extension__ unsigned short
5833 #define RWS_FIELD_TYPE unsigned int
5835 struct reg_write_state
5837 RWS_FIELD_TYPE write_count : 2;
5838 RWS_FIELD_TYPE first_pred : 10;
5839 RWS_FIELD_TYPE written_by_fp : 1;
5840 RWS_FIELD_TYPE written_by_and : 1;
5841 RWS_FIELD_TYPE written_by_or : 1;
5844 /* Cumulative info for the current instruction group. */
5845 struct reg_write_state rws_sum[NUM_REGS];
5846 #ifdef ENABLE_CHECKING
5847 /* Bitmap whether a register has been written in the current insn. */
5848 HARD_REG_ELT_TYPE rws_insn[(NUM_REGS + HOST_BITS_PER_WIDEST_FAST_INT - 1)
5849 / HOST_BITS_PER_WIDEST_FAST_INT];
5852 rws_insn_set (int regno)
5854 gcc_assert (!TEST_HARD_REG_BIT (rws_insn, regno));
5855 SET_HARD_REG_BIT (rws_insn, regno);
5859 rws_insn_test (int regno)
5861 return TEST_HARD_REG_BIT (rws_insn, regno);
5864 /* When not checking, track just REG_AR_CFM and REG_VOLATILE. */
5865 unsigned char rws_insn[2];
5868 rws_insn_set (int regno)
5870 if (regno == REG_AR_CFM)
5872 else if (regno == REG_VOLATILE)
5877 rws_insn_test (int regno)
5879 if (regno == REG_AR_CFM)
5881 if (regno == REG_VOLATILE)
5887 /* Indicates whether this is the first instruction after a stop bit,
5888 in which case we don't need another stop bit. Without this,
5889 ia64_variable_issue will die when scheduling an alloc. */
5890 static int first_instruction;
5892 /* Misc flags needed to compute RAW/WAW dependencies while we are traversing
5893 RTL for one instruction. */
5896 unsigned int is_write : 1; /* Is register being written? */
5897 unsigned int is_fp : 1; /* Is register used as part of an fp op? */
5898 unsigned int is_branch : 1; /* Is register used as part of a branch? */
5899 unsigned int is_and : 1; /* Is register used as part of and.orcm? */
5900 unsigned int is_or : 1; /* Is register used as part of or.andcm? */
5901 unsigned int is_sibcall : 1; /* Is this a sibling or normal call? */
5904 static void rws_update (int, struct reg_flags, int);
5905 static int rws_access_regno (int, struct reg_flags, int);
5906 static int rws_access_reg (rtx, struct reg_flags, int);
5907 static void update_set_flags (rtx, struct reg_flags *);
5908 static int set_src_needs_barrier (rtx, struct reg_flags, int);
5909 static int rtx_needs_barrier (rtx, struct reg_flags, int);
5910 static void init_insn_group_barriers (void);
5911 static int group_barrier_needed (rtx);
5912 static int safe_group_barrier_needed (rtx);
5913 static int in_safe_group_barrier;
5915 /* Update *RWS for REGNO, which is being written by the current instruction,
5916 with predicate PRED, and associated register flags in FLAGS. */
5919 rws_update (int regno, struct reg_flags flags, int pred)
5922 rws_sum[regno].write_count++;
5924 rws_sum[regno].write_count = 2;
5925 rws_sum[regno].written_by_fp |= flags.is_fp;
5926 /* ??? Not tracking and/or across differing predicates. */
5927 rws_sum[regno].written_by_and = flags.is_and;
5928 rws_sum[regno].written_by_or = flags.is_or;
5929 rws_sum[regno].first_pred = pred;
5932 /* Handle an access to register REGNO of type FLAGS using predicate register
5933 PRED. Update rws_sum array. Return 1 if this access creates
5934 a dependency with an earlier instruction in the same group. */
5937 rws_access_regno (int regno, struct reg_flags flags, int pred)
5939 int need_barrier = 0;
5941 gcc_assert (regno < NUM_REGS);
5943 if (! PR_REGNO_P (regno))
5944 flags.is_and = flags.is_or = 0;
5950 rws_insn_set (regno);
5951 write_count = rws_sum[regno].write_count;
5953 switch (write_count)
5956 /* The register has not been written yet. */
5957 if (!in_safe_group_barrier)
5958 rws_update (regno, flags, pred);
5962 /* The register has been written via a predicate. Treat
5963 it like a unconditional write and do not try to check
5964 for complementary pred reg in earlier write. */
5965 if (flags.is_and && rws_sum[regno].written_by_and)
5967 else if (flags.is_or && rws_sum[regno].written_by_or)
5971 if (!in_safe_group_barrier)
5972 rws_update (regno, flags, pred);
5976 /* The register has been unconditionally written already. We
5978 if (flags.is_and && rws_sum[regno].written_by_and)
5980 else if (flags.is_or && rws_sum[regno].written_by_or)
5984 if (!in_safe_group_barrier)
5986 rws_sum[regno].written_by_and = flags.is_and;
5987 rws_sum[regno].written_by_or = flags.is_or;
5997 if (flags.is_branch)
5999 /* Branches have several RAW exceptions that allow to avoid
6002 if (REGNO_REG_CLASS (regno) == BR_REGS || regno == AR_PFS_REGNUM)
6003 /* RAW dependencies on branch regs are permissible as long
6004 as the writer is a non-branch instruction. Since we
6005 never generate code that uses a branch register written
6006 by a branch instruction, handling this case is
6010 if (REGNO_REG_CLASS (regno) == PR_REGS
6011 && ! rws_sum[regno].written_by_fp)
6012 /* The predicates of a branch are available within the
6013 same insn group as long as the predicate was written by
6014 something other than a floating-point instruction. */
6018 if (flags.is_and && rws_sum[regno].written_by_and)
6020 if (flags.is_or && rws_sum[regno].written_by_or)
6023 switch (rws_sum[regno].write_count)
6026 /* The register has not been written yet. */
6030 /* The register has been written via a predicate, assume we
6031 need a barrier (don't check for complementary regs). */
6036 /* The register has been unconditionally written already. We
6046 return need_barrier;
6050 rws_access_reg (rtx reg, struct reg_flags flags, int pred)
6052 int regno = REGNO (reg);
6053 int n = HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg));
6056 return rws_access_regno (regno, flags, pred);
6059 int need_barrier = 0;
6061 need_barrier |= rws_access_regno (regno + n, flags, pred);
6062 return need_barrier;
6066 /* Examine X, which is a SET rtx, and update the flags, the predicate, and
6067 the condition, stored in *PFLAGS, *PPRED and *PCOND. */
6070 update_set_flags (rtx x, struct reg_flags *pflags)
6072 rtx src = SET_SRC (x);
6074 switch (GET_CODE (src))
6080 /* There are four cases here:
6081 (1) The destination is (pc), in which case this is a branch,
6082 nothing here applies.
6083 (2) The destination is ar.lc, in which case this is a
6084 doloop_end_internal,
6085 (3) The destination is an fp register, in which case this is
6086 an fselect instruction.
6087 (4) The condition has (unspec [(reg)] UNSPEC_LDC), in which case
6088 this is a check load.
6089 In all cases, nothing we do in this function applies. */
6093 if (COMPARISON_P (src)
6094 && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (src, 0))))
6095 /* Set pflags->is_fp to 1 so that we know we're dealing
6096 with a floating point comparison when processing the
6097 destination of the SET. */
6100 /* Discover if this is a parallel comparison. We only handle
6101 and.orcm and or.andcm at present, since we must retain a
6102 strict inverse on the predicate pair. */
6103 else if (GET_CODE (src) == AND)
6105 else if (GET_CODE (src) == IOR)
6112 /* Subroutine of rtx_needs_barrier; this function determines whether the
6113 source of a given SET rtx found in X needs a barrier. FLAGS and PRED
6114 are as in rtx_needs_barrier. COND is an rtx that holds the condition
6118 set_src_needs_barrier (rtx x, struct reg_flags flags, int pred)
6120 int need_barrier = 0;
6122 rtx src = SET_SRC (x);
6124 if (GET_CODE (src) == CALL)
6125 /* We don't need to worry about the result registers that
6126 get written by subroutine call. */
6127 return rtx_needs_barrier (src, flags, pred);
6128 else if (SET_DEST (x) == pc_rtx)
6130 /* X is a conditional branch. */
6131 /* ??? This seems redundant, as the caller sets this bit for
6133 if (!ia64_spec_check_src_p (src))
6134 flags.is_branch = 1;
6135 return rtx_needs_barrier (src, flags, pred);
6138 if (ia64_spec_check_src_p (src))
6139 /* Avoid checking one register twice (in condition
6140 and in 'then' section) for ldc pattern. */
6142 gcc_assert (REG_P (XEXP (src, 2)));
6143 need_barrier = rtx_needs_barrier (XEXP (src, 2), flags, pred);
6145 /* We process MEM below. */
6146 src = XEXP (src, 1);
6149 need_barrier |= rtx_needs_barrier (src, flags, pred);
6152 if (GET_CODE (dst) == ZERO_EXTRACT)
6154 need_barrier |= rtx_needs_barrier (XEXP (dst, 1), flags, pred);
6155 need_barrier |= rtx_needs_barrier (XEXP (dst, 2), flags, pred);
6157 return need_barrier;
6160 /* Handle an access to rtx X of type FLAGS using predicate register
6161 PRED. Return 1 if this access creates a dependency with an earlier
6162 instruction in the same group. */
6165 rtx_needs_barrier (rtx x, struct reg_flags flags, int pred)
6168 int is_complemented = 0;
6169 int need_barrier = 0;
6170 const char *format_ptr;
6171 struct reg_flags new_flags;
6179 switch (GET_CODE (x))
6182 update_set_flags (x, &new_flags);
6183 need_barrier = set_src_needs_barrier (x, new_flags, pred);
6184 if (GET_CODE (SET_SRC (x)) != CALL)
6186 new_flags.is_write = 1;
6187 need_barrier |= rtx_needs_barrier (SET_DEST (x), new_flags, pred);
6192 new_flags.is_write = 0;
6193 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
6195 /* Avoid multiple register writes, in case this is a pattern with
6196 multiple CALL rtx. This avoids a failure in rws_access_reg. */
6197 if (! flags.is_sibcall && ! rws_insn_test (REG_AR_CFM))
6199 new_flags.is_write = 1;
6200 need_barrier |= rws_access_regno (REG_RP, new_flags, pred);
6201 need_barrier |= rws_access_regno (AR_PFS_REGNUM, new_flags, pred);
6202 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
6207 /* X is a predicated instruction. */
6209 cond = COND_EXEC_TEST (x);
6211 need_barrier = rtx_needs_barrier (cond, flags, 0);
6213 if (GET_CODE (cond) == EQ)
6214 is_complemented = 1;
6215 cond = XEXP (cond, 0);
6216 gcc_assert (GET_CODE (cond) == REG
6217 && REGNO_REG_CLASS (REGNO (cond)) == PR_REGS);
6218 pred = REGNO (cond);
6219 if (is_complemented)
6222 need_barrier |= rtx_needs_barrier (COND_EXEC_CODE (x), flags, pred);
6223 return need_barrier;
6227 /* Clobber & use are for earlier compiler-phases only. */
6232 /* We always emit stop bits for traditional asms. We emit stop bits
6233 for volatile extended asms if TARGET_VOL_ASM_STOP is true. */
6234 if (GET_CODE (x) != ASM_OPERANDS
6235 || (MEM_VOLATILE_P (x) && TARGET_VOL_ASM_STOP))
6237 /* Avoid writing the register multiple times if we have multiple
6238 asm outputs. This avoids a failure in rws_access_reg. */
6239 if (! rws_insn_test (REG_VOLATILE))
6241 new_flags.is_write = 1;
6242 rws_access_regno (REG_VOLATILE, new_flags, pred);
6247 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
6248 We cannot just fall through here since then we would be confused
6249 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
6250 traditional asms unlike their normal usage. */
6252 for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; --i)
6253 if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x, i), flags, pred))
6258 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
6260 rtx pat = XVECEXP (x, 0, i);
6261 switch (GET_CODE (pat))
6264 update_set_flags (pat, &new_flags);
6265 need_barrier |= set_src_needs_barrier (pat, new_flags, pred);
6271 need_barrier |= rtx_needs_barrier (pat, flags, pred);
6275 if (REG_P (XEXP (pat, 0))
6276 && extract_asm_operands (x) != NULL_RTX
6277 && REGNO (XEXP (pat, 0)) != AR_UNAT_REGNUM)
6279 new_flags.is_write = 1;
6280 need_barrier |= rtx_needs_barrier (XEXP (pat, 0),
6293 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
6295 rtx pat = XVECEXP (x, 0, i);
6296 if (GET_CODE (pat) == SET)
6298 if (GET_CODE (SET_SRC (pat)) != CALL)
6300 new_flags.is_write = 1;
6301 need_barrier |= rtx_needs_barrier (SET_DEST (pat), new_flags,
6305 else if (GET_CODE (pat) == CLOBBER || GET_CODE (pat) == RETURN)
6306 need_barrier |= rtx_needs_barrier (pat, flags, pred);
6311 need_barrier |= rtx_needs_barrier (SUBREG_REG (x), flags, pred);
6314 if (REGNO (x) == AR_UNAT_REGNUM)
6316 for (i = 0; i < 64; ++i)
6317 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + i, flags, pred);
6320 need_barrier = rws_access_reg (x, flags, pred);
6324 /* Find the regs used in memory address computation. */
6325 new_flags.is_write = 0;
6326 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
6329 case CONST_INT: case CONST_DOUBLE: case CONST_VECTOR:
6330 case SYMBOL_REF: case LABEL_REF: case CONST:
6333 /* Operators with side-effects. */
6334 case POST_INC: case POST_DEC:
6335 gcc_assert (GET_CODE (XEXP (x, 0)) == REG);
6337 new_flags.is_write = 0;
6338 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
6339 new_flags.is_write = 1;
6340 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
6344 gcc_assert (GET_CODE (XEXP (x, 0)) == REG);
6346 new_flags.is_write = 0;
6347 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
6348 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
6349 new_flags.is_write = 1;
6350 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
6353 /* Handle common unary and binary ops for efficiency. */
6354 case COMPARE: case PLUS: case MINUS: case MULT: case DIV:
6355 case MOD: case UDIV: case UMOD: case AND: case IOR:
6356 case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT:
6357 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
6358 case NE: case EQ: case GE: case GT: case LE:
6359 case LT: case GEU: case GTU: case LEU: case LTU:
6360 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
6361 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
6364 case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND:
6365 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT:
6366 case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS:
6367 case SQRT: case FFS: case POPCOUNT:
6368 need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred);
6372 /* VEC_SELECT's second argument is a PARALLEL with integers that
6373 describe the elements selected. On ia64, those integers are
6374 always constants. Avoid walking the PARALLEL so that we don't
6375 get confused with "normal" parallels and then die. */
6376 need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred);
6380 switch (XINT (x, 1))
6382 case UNSPEC_LTOFF_DTPMOD:
6383 case UNSPEC_LTOFF_DTPREL:
6385 case UNSPEC_LTOFF_TPREL:
6387 case UNSPEC_PRED_REL_MUTEX:
6388 case UNSPEC_PIC_CALL:
6390 case UNSPEC_FETCHADD_ACQ:
6391 case UNSPEC_BSP_VALUE:
6392 case UNSPEC_FLUSHRS:
6393 case UNSPEC_BUNDLE_SELECTOR:
6396 case UNSPEC_GR_SPILL:
6397 case UNSPEC_GR_RESTORE:
6399 HOST_WIDE_INT offset = INTVAL (XVECEXP (x, 0, 1));
6400 HOST_WIDE_INT bit = (offset >> 3) & 63;
6402 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
6403 new_flags.is_write = (XINT (x, 1) == UNSPEC_GR_SPILL);
6404 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + bit,
6409 case UNSPEC_FR_SPILL:
6410 case UNSPEC_FR_RESTORE:
6411 case UNSPEC_GETF_EXP:
6412 case UNSPEC_SETF_EXP:
6414 case UNSPEC_FR_SQRT_RECIP_APPROX:
6415 case UNSPEC_FR_SQRT_RECIP_APPROX_RES:
6420 case UNSPEC_CHKACLR:
6422 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
6425 case UNSPEC_FR_RECIP_APPROX:
6427 case UNSPEC_COPYSIGN:
6428 case UNSPEC_FR_RECIP_APPROX_RES:
6429 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
6430 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
6433 case UNSPEC_CMPXCHG_ACQ:
6434 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
6435 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 2), flags, pred);
6443 case UNSPEC_VOLATILE:
6444 switch (XINT (x, 1))
6447 /* Alloc must always be the first instruction of a group.
6448 We force this by always returning true. */
6449 /* ??? We might get better scheduling if we explicitly check for
6450 input/local/output register dependencies, and modify the
6451 scheduler so that alloc is always reordered to the start of
6452 the current group. We could then eliminate all of the
6453 first_instruction code. */
6454 rws_access_regno (AR_PFS_REGNUM, flags, pred);
6456 new_flags.is_write = 1;
6457 rws_access_regno (REG_AR_CFM, new_flags, pred);
6460 case UNSPECV_SET_BSP:
6464 case UNSPECV_BLOCKAGE:
6465 case UNSPECV_INSN_GROUP_BARRIER:
6467 case UNSPECV_PSAC_ALL:
6468 case UNSPECV_PSAC_NORMAL:
6477 new_flags.is_write = 0;
6478 need_barrier = rws_access_regno (REG_RP, flags, pred);
6479 need_barrier |= rws_access_regno (AR_PFS_REGNUM, flags, pred);
6481 new_flags.is_write = 1;
6482 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
6483 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
6487 format_ptr = GET_RTX_FORMAT (GET_CODE (x));
6488 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6489 switch (format_ptr[i])
6491 case '0': /* unused field */
6492 case 'i': /* integer */
6493 case 'n': /* note */
6494 case 'w': /* wide integer */
6495 case 's': /* pointer to string */
6496 case 'S': /* optional pointer to string */
6500 if (rtx_needs_barrier (XEXP (x, i), flags, pred))
6505 for (j = XVECLEN (x, i) - 1; j >= 0; --j)
6506 if (rtx_needs_barrier (XVECEXP (x, i, j), flags, pred))
6515 return need_barrier;
6518 /* Clear out the state for group_barrier_needed at the start of a
6519 sequence of insns. */
6522 init_insn_group_barriers (void)
6524 memset (rws_sum, 0, sizeof (rws_sum));
6525 first_instruction = 1;
6528 /* Given the current state, determine whether a group barrier (a stop bit) is
6529 necessary before INSN. Return nonzero if so. This modifies the state to
6530 include the effects of INSN as a side-effect. */
6533 group_barrier_needed (rtx insn)
6536 int need_barrier = 0;
6537 struct reg_flags flags;
6539 memset (&flags, 0, sizeof (flags));
6540 switch (GET_CODE (insn))
6547 /* A barrier doesn't imply an instruction group boundary. */
6551 memset (rws_insn, 0, sizeof (rws_insn));
6555 flags.is_branch = 1;
6556 flags.is_sibcall = SIBLING_CALL_P (insn);
6557 memset (rws_insn, 0, sizeof (rws_insn));
6559 /* Don't bundle a call following another call. */
6560 if ((pat = prev_active_insn (insn))
6561 && GET_CODE (pat) == CALL_INSN)
6567 need_barrier = rtx_needs_barrier (PATTERN (insn), flags, 0);
6571 if (!ia64_spec_check_p (insn))
6572 flags.is_branch = 1;
6574 /* Don't bundle a jump following a call. */
6575 if ((pat = prev_active_insn (insn))
6576 && GET_CODE (pat) == CALL_INSN)
6584 if (GET_CODE (PATTERN (insn)) == USE
6585 || GET_CODE (PATTERN (insn)) == CLOBBER)
6586 /* Don't care about USE and CLOBBER "insns"---those are used to
6587 indicate to the optimizer that it shouldn't get rid of
6588 certain operations. */
6591 pat = PATTERN (insn);
6593 /* Ug. Hack hacks hacked elsewhere. */
6594 switch (recog_memoized (insn))
6596 /* We play dependency tricks with the epilogue in order
6597 to get proper schedules. Undo this for dv analysis. */
6598 case CODE_FOR_epilogue_deallocate_stack:
6599 case CODE_FOR_prologue_allocate_stack:
6600 pat = XVECEXP (pat, 0, 0);
6603 /* The pattern we use for br.cloop confuses the code above.
6604 The second element of the vector is representative. */
6605 case CODE_FOR_doloop_end_internal:
6606 pat = XVECEXP (pat, 0, 1);
6609 /* Doesn't generate code. */
6610 case CODE_FOR_pred_rel_mutex:
6611 case CODE_FOR_prologue_use:
6618 memset (rws_insn, 0, sizeof (rws_insn));
6619 need_barrier = rtx_needs_barrier (pat, flags, 0);
6621 /* Check to see if the previous instruction was a volatile
6624 need_barrier = rws_access_regno (REG_VOLATILE, flags, 0);
6632 if (first_instruction && INSN_P (insn)
6633 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
6634 && GET_CODE (PATTERN (insn)) != USE
6635 && GET_CODE (PATTERN (insn)) != CLOBBER)
6638 first_instruction = 0;
6641 return need_barrier;
6644 /* Like group_barrier_needed, but do not clobber the current state. */
6647 safe_group_barrier_needed (rtx insn)
6649 int saved_first_instruction;
6652 saved_first_instruction = first_instruction;
6653 in_safe_group_barrier = 1;
6655 t = group_barrier_needed (insn);
6657 first_instruction = saved_first_instruction;
6658 in_safe_group_barrier = 0;
6663 /* Scan the current function and insert stop bits as necessary to
6664 eliminate dependencies. This function assumes that a final
6665 instruction scheduling pass has been run which has already
6666 inserted most of the necessary stop bits. This function only
6667 inserts new ones at basic block boundaries, since these are
6668 invisible to the scheduler. */
6671 emit_insn_group_barriers (FILE *dump)
6675 int insns_since_last_label = 0;
6677 init_insn_group_barriers ();
6679 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6681 if (GET_CODE (insn) == CODE_LABEL)
6683 if (insns_since_last_label)
6685 insns_since_last_label = 0;
6687 else if (GET_CODE (insn) == NOTE
6688 && NOTE_KIND (insn) == NOTE_INSN_BASIC_BLOCK)
6690 if (insns_since_last_label)
6692 insns_since_last_label = 0;
6694 else if (GET_CODE (insn) == INSN
6695 && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
6696 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
6698 init_insn_group_barriers ();
6701 else if (NONDEBUG_INSN_P (insn))
6703 insns_since_last_label = 1;
6705 if (group_barrier_needed (insn))
6710 fprintf (dump, "Emitting stop before label %d\n",
6711 INSN_UID (last_label));
6712 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), last_label);
6715 init_insn_group_barriers ();
6723 /* Like emit_insn_group_barriers, but run if no final scheduling pass was run.
6724 This function has to emit all necessary group barriers. */
6727 emit_all_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED)
6731 init_insn_group_barriers ();
6733 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6735 if (GET_CODE (insn) == BARRIER)
6737 rtx last = prev_active_insn (insn);
6741 if (GET_CODE (last) == JUMP_INSN
6742 && GET_CODE (PATTERN (last)) == ADDR_DIFF_VEC)
6743 last = prev_active_insn (last);
6744 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
6745 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
6747 init_insn_group_barriers ();
6749 else if (NONDEBUG_INSN_P (insn))
6751 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
6752 init_insn_group_barriers ();
6753 else if (group_barrier_needed (insn))
6755 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn);
6756 init_insn_group_barriers ();
6757 group_barrier_needed (insn);
6765 /* Instruction scheduling support. */
6767 #define NR_BUNDLES 10
6769 /* A list of names of all available bundles. */
6771 static const char *bundle_name [NR_BUNDLES] =
6777 #if NR_BUNDLES == 10
6787 /* Nonzero if we should insert stop bits into the schedule. */
6789 int ia64_final_schedule = 0;
6791 /* Codes of the corresponding queried units: */
6793 static int _0mii_, _0mmi_, _0mfi_, _0mmf_;
6794 static int _0bbb_, _0mbb_, _0mib_, _0mmb_, _0mfb_, _0mlx_;
6796 static int _1mii_, _1mmi_, _1mfi_, _1mmf_;
6797 static int _1bbb_, _1mbb_, _1mib_, _1mmb_, _1mfb_, _1mlx_;
6799 static int pos_1, pos_2, pos_3, pos_4, pos_5, pos_6;
6801 /* The following variable value is an insn group barrier. */
6803 static rtx dfa_stop_insn;
6805 /* The following variable value is the last issued insn. */
6807 static rtx last_scheduled_insn;
6809 /* The following variable value is pointer to a DFA state used as
6810 temporary variable. */
6812 static state_t temp_dfa_state = NULL;
6814 /* The following variable value is DFA state after issuing the last
6817 static state_t prev_cycle_state = NULL;
6819 /* The following array element values are TRUE if the corresponding
6820 insn requires to add stop bits before it. */
6822 static char *stops_p = NULL;
6824 /* The following variable is used to set up the mentioned above array. */
6826 static int stop_before_p = 0;
6828 /* The following variable value is length of the arrays `clocks' and
6831 static int clocks_length;
6833 /* The following variable value is number of data speculations in progress. */
6834 static int pending_data_specs = 0;
6836 /* Number of memory references on current and three future processor cycles. */
6837 static char mem_ops_in_group[4];
6839 /* Number of current processor cycle (from scheduler's point of view). */
6840 static int current_cycle;
6842 static rtx ia64_single_set (rtx);
6843 static void ia64_emit_insn_before (rtx, rtx);
6845 /* Map a bundle number to its pseudo-op. */
6848 get_bundle_name (int b)
6850 return bundle_name[b];
6854 /* Return the maximum number of instructions a cpu can issue. */
6857 ia64_issue_rate (void)
6862 /* Helper function - like single_set, but look inside COND_EXEC. */
6865 ia64_single_set (rtx insn)
6867 rtx x = PATTERN (insn), ret;
6868 if (GET_CODE (x) == COND_EXEC)
6869 x = COND_EXEC_CODE (x);
6870 if (GET_CODE (x) == SET)
6873 /* Special case here prologue_allocate_stack and epilogue_deallocate_stack.
6874 Although they are not classical single set, the second set is there just
6875 to protect it from moving past FP-relative stack accesses. */
6876 switch (recog_memoized (insn))
6878 case CODE_FOR_prologue_allocate_stack:
6879 case CODE_FOR_epilogue_deallocate_stack:
6880 ret = XVECEXP (x, 0, 0);
6884 ret = single_set_2 (insn, x);
6891 /* Adjust the cost of a scheduling dependency.
6892 Return the new cost of a dependency of type DEP_TYPE or INSN on DEP_INSN.
6893 COST is the current cost, DW is dependency weakness. */
6895 ia64_adjust_cost_2 (rtx insn, int dep_type1, rtx dep_insn, int cost, dw_t dw)
6897 enum reg_note dep_type = (enum reg_note) dep_type1;
6898 enum attr_itanium_class dep_class;
6899 enum attr_itanium_class insn_class;
6901 insn_class = ia64_safe_itanium_class (insn);
6902 dep_class = ia64_safe_itanium_class (dep_insn);
6904 /* Treat true memory dependencies separately. Ignore apparent true
6905 dependence between store and call (call has a MEM inside a SYMBOL_REF). */
6906 if (dep_type == REG_DEP_TRUE
6907 && (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF)
6908 && (insn_class == ITANIUM_CLASS_BR || insn_class == ITANIUM_CLASS_SCALL))
6911 if (dw == MIN_DEP_WEAK)
6912 /* Store and load are likely to alias, use higher cost to avoid stall. */
6913 return PARAM_VALUE (PARAM_SCHED_MEM_TRUE_DEP_COST);
6914 else if (dw > MIN_DEP_WEAK)
6916 /* Store and load are less likely to alias. */
6917 if (mflag_sched_fp_mem_deps_zero_cost && dep_class == ITANIUM_CLASS_STF)
6918 /* Assume there will be no cache conflict for floating-point data.
6919 For integer data, L1 conflict penalty is huge (17 cycles), so we
6920 never assume it will not cause a conflict. */
6926 if (dep_type != REG_DEP_OUTPUT)
6929 if (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF
6930 || insn_class == ITANIUM_CLASS_ST || insn_class == ITANIUM_CLASS_STF)
6936 /* Like emit_insn_before, but skip cycle_display notes.
6937 ??? When cycle display notes are implemented, update this. */
6940 ia64_emit_insn_before (rtx insn, rtx before)
6942 emit_insn_before (insn, before);
6945 /* The following function marks insns who produce addresses for load
6946 and store insns. Such insns will be placed into M slots because it
6947 decrease latency time for Itanium1 (see function
6948 `ia64_produce_address_p' and the DFA descriptions). */
6951 ia64_dependencies_evaluation_hook (rtx head, rtx tail)
6953 rtx insn, next, next_tail;
6955 /* Before reload, which_alternative is not set, which means that
6956 ia64_safe_itanium_class will produce wrong results for (at least)
6957 move instructions. */
6958 if (!reload_completed)
6961 next_tail = NEXT_INSN (tail);
6962 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
6965 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
6967 && ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IALU)
6969 sd_iterator_def sd_it;
6971 bool has_mem_op_consumer_p = false;
6973 FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep)
6975 enum attr_itanium_class c;
6977 if (DEP_TYPE (dep) != REG_DEP_TRUE)
6980 next = DEP_CON (dep);
6981 c = ia64_safe_itanium_class (next);
6982 if ((c == ITANIUM_CLASS_ST
6983 || c == ITANIUM_CLASS_STF)
6984 && ia64_st_address_bypass_p (insn, next))
6986 has_mem_op_consumer_p = true;
6989 else if ((c == ITANIUM_CLASS_LD
6990 || c == ITANIUM_CLASS_FLD
6991 || c == ITANIUM_CLASS_FLDP)
6992 && ia64_ld_address_bypass_p (insn, next))
6994 has_mem_op_consumer_p = true;
6999 insn->call = has_mem_op_consumer_p;
7003 /* We're beginning a new block. Initialize data structures as necessary. */
7006 ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED,
7007 int sched_verbose ATTRIBUTE_UNUSED,
7008 int max_ready ATTRIBUTE_UNUSED)
7010 #ifdef ENABLE_CHECKING
7013 if (!sel_sched_p () && reload_completed)
7014 for (insn = NEXT_INSN (current_sched_info->prev_head);
7015 insn != current_sched_info->next_tail;
7016 insn = NEXT_INSN (insn))
7017 gcc_assert (!SCHED_GROUP_P (insn));
7019 last_scheduled_insn = NULL_RTX;
7020 init_insn_group_barriers ();
7023 memset (mem_ops_in_group, 0, sizeof (mem_ops_in_group));
7026 /* We're beginning a scheduling pass. Check assertion. */
7029 ia64_sched_init_global (FILE *dump ATTRIBUTE_UNUSED,
7030 int sched_verbose ATTRIBUTE_UNUSED,
7031 int max_ready ATTRIBUTE_UNUSED)
7033 gcc_assert (pending_data_specs == 0);
7036 /* Scheduling pass is now finished. Free/reset static variable. */
7038 ia64_sched_finish_global (FILE *dump ATTRIBUTE_UNUSED,
7039 int sched_verbose ATTRIBUTE_UNUSED)
7041 gcc_assert (pending_data_specs == 0);
7044 /* Return TRUE if INSN is a load (either normal or speculative, but not a
7045 speculation check), FALSE otherwise. */
7047 is_load_p (rtx insn)
7049 enum attr_itanium_class insn_class = ia64_safe_itanium_class (insn);
7052 ((insn_class == ITANIUM_CLASS_LD || insn_class == ITANIUM_CLASS_FLD)
7053 && get_attr_check_load (insn) == CHECK_LOAD_NO);
7056 /* If INSN is a memory reference, memoize it in MEM_OPS_IN_GROUP global array
7057 (taking account for 3-cycle cache reference postponing for stores: Intel
7058 Itanium 2 Reference Manual for Software Development and Optimization,
7061 record_memory_reference (rtx insn)
7063 enum attr_itanium_class insn_class = ia64_safe_itanium_class (insn);
7065 switch (insn_class) {
7066 case ITANIUM_CLASS_FLD:
7067 case ITANIUM_CLASS_LD:
7068 mem_ops_in_group[current_cycle % 4]++;
7070 case ITANIUM_CLASS_STF:
7071 case ITANIUM_CLASS_ST:
7072 mem_ops_in_group[(current_cycle + 3) % 4]++;
7078 /* We are about to being issuing insns for this clock cycle.
7079 Override the default sort algorithm to better slot instructions. */
7082 ia64_dfa_sched_reorder (FILE *dump, int sched_verbose, rtx *ready,
7083 int *pn_ready, int clock_var,
7087 int n_ready = *pn_ready;
7088 rtx *e_ready = ready + n_ready;
7092 fprintf (dump, "// ia64_dfa_sched_reorder (type %d):\n", reorder_type);
7094 if (reorder_type == 0)
7096 /* First, move all USEs, CLOBBERs and other crud out of the way. */
7098 for (insnp = ready; insnp < e_ready; insnp++)
7099 if (insnp < e_ready)
7102 enum attr_type t = ia64_safe_type (insn);
7103 if (t == TYPE_UNKNOWN)
7105 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
7106 || asm_noperands (PATTERN (insn)) >= 0)
7108 rtx lowest = ready[n_asms];
7109 ready[n_asms] = insn;
7115 rtx highest = ready[n_ready - 1];
7116 ready[n_ready - 1] = insn;
7123 if (n_asms < n_ready)
7125 /* Some normal insns to process. Skip the asms. */
7129 else if (n_ready > 0)
7133 if (ia64_final_schedule)
7136 int nr_need_stop = 0;
7138 for (insnp = ready; insnp < e_ready; insnp++)
7139 if (safe_group_barrier_needed (*insnp))
7142 if (reorder_type == 1 && n_ready == nr_need_stop)
7144 if (reorder_type == 0)
7147 /* Move down everything that needs a stop bit, preserving
7149 while (insnp-- > ready + deleted)
7150 while (insnp >= ready + deleted)
7153 if (! safe_group_barrier_needed (insn))
7155 memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx));
7163 current_cycle = clock_var;
7164 if (reload_completed && mem_ops_in_group[clock_var % 4] >= ia64_max_memory_insns)
7169 /* Move down loads/stores, preserving relative order. */
7170 while (insnp-- > ready + moved)
7171 while (insnp >= ready + moved)
7174 if (! is_load_p (insn))
7176 memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx));
7187 /* We are about to being issuing insns for this clock cycle. Override
7188 the default sort algorithm to better slot instructions. */
7191 ia64_sched_reorder (FILE *dump, int sched_verbose, rtx *ready, int *pn_ready,
7194 return ia64_dfa_sched_reorder (dump, sched_verbose, ready,
7195 pn_ready, clock_var, 0);
7198 /* Like ia64_sched_reorder, but called after issuing each insn.
7199 Override the default sort algorithm to better slot instructions. */
7202 ia64_sched_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
7203 int sched_verbose ATTRIBUTE_UNUSED, rtx *ready,
7204 int *pn_ready, int clock_var)
7206 return ia64_dfa_sched_reorder (dump, sched_verbose, ready, pn_ready,
7210 /* We are about to issue INSN. Return the number of insns left on the
7211 ready queue that can be issued this cycle. */
7214 ia64_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
7215 int sched_verbose ATTRIBUTE_UNUSED,
7216 rtx insn ATTRIBUTE_UNUSED,
7217 int can_issue_more ATTRIBUTE_UNUSED)
7219 if (sched_deps_info->generate_spec_deps && !sel_sched_p ())
7220 /* Modulo scheduling does not extend h_i_d when emitting
7221 new instructions. Don't use h_i_d, if we don't have to. */
7223 if (DONE_SPEC (insn) & BEGIN_DATA)
7224 pending_data_specs++;
7225 if (CHECK_SPEC (insn) & BEGIN_DATA)
7226 pending_data_specs--;
7229 if (DEBUG_INSN_P (insn))
7232 last_scheduled_insn = insn;
7233 memcpy (prev_cycle_state, curr_state, dfa_state_size);
7234 if (reload_completed)
7236 int needed = group_barrier_needed (insn);
7238 gcc_assert (!needed);
7239 if (GET_CODE (insn) == CALL_INSN)
7240 init_insn_group_barriers ();
7241 stops_p [INSN_UID (insn)] = stop_before_p;
7244 record_memory_reference (insn);
7249 /* We are choosing insn from the ready queue. Return nonzero if INSN
7253 ia64_first_cycle_multipass_dfa_lookahead_guard (rtx insn)
7255 gcc_assert (insn && INSN_P (insn));
7256 return ((!reload_completed
7257 || !safe_group_barrier_needed (insn))
7258 && ia64_first_cycle_multipass_dfa_lookahead_guard_spec (insn)
7259 && (!mflag_sched_mem_insns_hard_limit
7260 || !is_load_p (insn)
7261 || mem_ops_in_group[current_cycle % 4] < ia64_max_memory_insns));
7264 /* We are choosing insn from the ready queue. Return nonzero if INSN
7268 ia64_first_cycle_multipass_dfa_lookahead_guard_spec (const_rtx insn)
7270 gcc_assert (insn && INSN_P (insn));
7271 /* Size of ALAT is 32. As far as we perform conservative data speculation,
7272 we keep ALAT half-empty. */
7273 return (pending_data_specs < 16
7274 || !(TODO_SPEC (insn) & BEGIN_DATA));
7277 /* The following variable value is pseudo-insn used by the DFA insn
7278 scheduler to change the DFA state when the simulated clock is
7281 static rtx dfa_pre_cycle_insn;
7283 /* Returns 1 when a meaningful insn was scheduled between the last group
7284 barrier and LAST. */
7286 scheduled_good_insn (rtx last)
7288 if (last && recog_memoized (last) >= 0)
7292 last != NULL && !NOTE_INSN_BASIC_BLOCK_P (last)
7293 && !stops_p[INSN_UID (last)];
7294 last = PREV_INSN (last))
7295 /* We could hit a NOTE_INSN_DELETED here which is actually outside
7296 the ebb we're scheduling. */
7297 if (INSN_P (last) && recog_memoized (last) >= 0)
7303 /* We are about to being issuing INSN. Return nonzero if we cannot
7304 issue it on given cycle CLOCK and return zero if we should not sort
7305 the ready queue on the next clock start. */
7308 ia64_dfa_new_cycle (FILE *dump, int verbose, rtx insn, int last_clock,
7309 int clock, int *sort_p)
7311 gcc_assert (insn && INSN_P (insn));
7313 if (DEBUG_INSN_P (insn))
7316 /* When a group barrier is needed for insn, last_scheduled_insn
7318 gcc_assert (!(reload_completed && safe_group_barrier_needed (insn))
7319 || last_scheduled_insn);
7321 if ((reload_completed
7322 && (safe_group_barrier_needed (insn)
7323 || (mflag_sched_stop_bits_after_every_cycle
7324 && last_clock != clock
7325 && last_scheduled_insn
7326 && scheduled_good_insn (last_scheduled_insn))))
7327 || (last_scheduled_insn
7328 && (GET_CODE (last_scheduled_insn) == CALL_INSN
7329 || GET_CODE (PATTERN (last_scheduled_insn)) == ASM_INPUT
7330 || asm_noperands (PATTERN (last_scheduled_insn)) >= 0)))
7332 init_insn_group_barriers ();
7334 if (verbose && dump)
7335 fprintf (dump, "// Stop should be before %d%s\n", INSN_UID (insn),
7336 last_clock == clock ? " + cycle advance" : "");
7339 current_cycle = clock;
7340 mem_ops_in_group[current_cycle % 4] = 0;
7342 if (last_clock == clock)
7344 state_transition (curr_state, dfa_stop_insn);
7345 if (TARGET_EARLY_STOP_BITS)
7346 *sort_p = (last_scheduled_insn == NULL_RTX
7347 || GET_CODE (last_scheduled_insn) != CALL_INSN);
7353 if (last_scheduled_insn)
7355 if (GET_CODE (PATTERN (last_scheduled_insn)) == ASM_INPUT
7356 || asm_noperands (PATTERN (last_scheduled_insn)) >= 0)
7357 state_reset (curr_state);
7360 memcpy (curr_state, prev_cycle_state, dfa_state_size);
7361 state_transition (curr_state, dfa_stop_insn);
7362 state_transition (curr_state, dfa_pre_cycle_insn);
7363 state_transition (curr_state, NULL);
7370 /* Implement targetm.sched.h_i_d_extended hook.
7371 Extend internal data structures. */
7373 ia64_h_i_d_extended (void)
7375 if (stops_p != NULL)
7377 int new_clocks_length = get_max_uid () * 3 / 2;
7378 stops_p = (char *) xrecalloc (stops_p, new_clocks_length, clocks_length, 1);
7379 clocks_length = new_clocks_length;
7384 /* This structure describes the data used by the backend to guide scheduling.
7385 When the current scheduling point is switched, this data should be saved
7386 and restored later, if the scheduler returns to this point. */
7387 struct _ia64_sched_context
7389 state_t prev_cycle_state;
7390 rtx last_scheduled_insn;
7391 struct reg_write_state rws_sum[NUM_REGS];
7392 struct reg_write_state rws_insn[NUM_REGS];
7393 int first_instruction;
7394 int pending_data_specs;
7396 char mem_ops_in_group[4];
7398 typedef struct _ia64_sched_context *ia64_sched_context_t;
7400 /* Allocates a scheduling context. */
7402 ia64_alloc_sched_context (void)
7404 return xmalloc (sizeof (struct _ia64_sched_context));
7407 /* Initializes the _SC context with clean data, if CLEAN_P, and from
7408 the global context otherwise. */
7410 ia64_init_sched_context (void *_sc, bool clean_p)
7412 ia64_sched_context_t sc = (ia64_sched_context_t) _sc;
7414 sc->prev_cycle_state = xmalloc (dfa_state_size);
7417 state_reset (sc->prev_cycle_state);
7418 sc->last_scheduled_insn = NULL_RTX;
7419 memset (sc->rws_sum, 0, sizeof (rws_sum));
7420 memset (sc->rws_insn, 0, sizeof (rws_insn));
7421 sc->first_instruction = 1;
7422 sc->pending_data_specs = 0;
7423 sc->current_cycle = 0;
7424 memset (sc->mem_ops_in_group, 0, sizeof (mem_ops_in_group));
7428 memcpy (sc->prev_cycle_state, prev_cycle_state, dfa_state_size);
7429 sc->last_scheduled_insn = last_scheduled_insn;
7430 memcpy (sc->rws_sum, rws_sum, sizeof (rws_sum));
7431 memcpy (sc->rws_insn, rws_insn, sizeof (rws_insn));
7432 sc->first_instruction = first_instruction;
7433 sc->pending_data_specs = pending_data_specs;
7434 sc->current_cycle = current_cycle;
7435 memcpy (sc->mem_ops_in_group, mem_ops_in_group, sizeof (mem_ops_in_group));
7439 /* Sets the global scheduling context to the one pointed to by _SC. */
7441 ia64_set_sched_context (void *_sc)
7443 ia64_sched_context_t sc = (ia64_sched_context_t) _sc;
7445 gcc_assert (sc != NULL);
7447 memcpy (prev_cycle_state, sc->prev_cycle_state, dfa_state_size);
7448 last_scheduled_insn = sc->last_scheduled_insn;
7449 memcpy (rws_sum, sc->rws_sum, sizeof (rws_sum));
7450 memcpy (rws_insn, sc->rws_insn, sizeof (rws_insn));
7451 first_instruction = sc->first_instruction;
7452 pending_data_specs = sc->pending_data_specs;
7453 current_cycle = sc->current_cycle;
7454 memcpy (mem_ops_in_group, sc->mem_ops_in_group, sizeof (mem_ops_in_group));
7457 /* Clears the data in the _SC scheduling context. */
7459 ia64_clear_sched_context (void *_sc)
7461 ia64_sched_context_t sc = (ia64_sched_context_t) _sc;
7463 free (sc->prev_cycle_state);
7464 sc->prev_cycle_state = NULL;
7467 /* Frees the _SC scheduling context. */
7469 ia64_free_sched_context (void *_sc)
7471 gcc_assert (_sc != NULL);
7476 typedef rtx (* gen_func_t) (rtx, rtx);
7478 /* Return a function that will generate a load of mode MODE_NO
7479 with speculation types TS. */
7481 get_spec_load_gen_function (ds_t ts, int mode_no)
7483 static gen_func_t gen_ld_[] = {
7493 gen_zero_extendqidi2,
7494 gen_zero_extendhidi2,
7495 gen_zero_extendsidi2,
7498 static gen_func_t gen_ld_a[] = {
7508 gen_zero_extendqidi2_advanced,
7509 gen_zero_extendhidi2_advanced,
7510 gen_zero_extendsidi2_advanced,
7512 static gen_func_t gen_ld_s[] = {
7513 gen_movbi_speculative,
7514 gen_movqi_speculative,
7515 gen_movhi_speculative,
7516 gen_movsi_speculative,
7517 gen_movdi_speculative,
7518 gen_movsf_speculative,
7519 gen_movdf_speculative,
7520 gen_movxf_speculative,
7521 gen_movti_speculative,
7522 gen_zero_extendqidi2_speculative,
7523 gen_zero_extendhidi2_speculative,
7524 gen_zero_extendsidi2_speculative,
7526 static gen_func_t gen_ld_sa[] = {
7527 gen_movbi_speculative_advanced,
7528 gen_movqi_speculative_advanced,
7529 gen_movhi_speculative_advanced,
7530 gen_movsi_speculative_advanced,
7531 gen_movdi_speculative_advanced,
7532 gen_movsf_speculative_advanced,
7533 gen_movdf_speculative_advanced,
7534 gen_movxf_speculative_advanced,
7535 gen_movti_speculative_advanced,
7536 gen_zero_extendqidi2_speculative_advanced,
7537 gen_zero_extendhidi2_speculative_advanced,
7538 gen_zero_extendsidi2_speculative_advanced,
7540 static gen_func_t gen_ld_s_a[] = {
7541 gen_movbi_speculative_a,
7542 gen_movqi_speculative_a,
7543 gen_movhi_speculative_a,
7544 gen_movsi_speculative_a,
7545 gen_movdi_speculative_a,
7546 gen_movsf_speculative_a,
7547 gen_movdf_speculative_a,
7548 gen_movxf_speculative_a,
7549 gen_movti_speculative_a,
7550 gen_zero_extendqidi2_speculative_a,
7551 gen_zero_extendhidi2_speculative_a,
7552 gen_zero_extendsidi2_speculative_a,
7557 if (ts & BEGIN_DATA)
7559 if (ts & BEGIN_CONTROL)
7564 else if (ts & BEGIN_CONTROL)
7566 if ((spec_info->flags & SEL_SCHED_SPEC_DONT_CHECK_CONTROL)
7567 || ia64_needs_block_p (ts))
7570 gen_ld = gen_ld_s_a;
7577 return gen_ld[mode_no];
7580 /* Constants that help mapping 'enum machine_mode' to int. */
7583 SPEC_MODE_INVALID = -1,
7584 SPEC_MODE_FIRST = 0,
7585 SPEC_MODE_FOR_EXTEND_FIRST = 1,
7586 SPEC_MODE_FOR_EXTEND_LAST = 3,
7592 /* Offset to reach ZERO_EXTEND patterns. */
7593 SPEC_GEN_EXTEND_OFFSET = SPEC_MODE_LAST - SPEC_MODE_FOR_EXTEND_FIRST + 1
7596 /* Return index of the MODE. */
7598 ia64_mode_to_int (enum machine_mode mode)
7602 case BImode: return 0; /* SPEC_MODE_FIRST */
7603 case QImode: return 1; /* SPEC_MODE_FOR_EXTEND_FIRST */
7604 case HImode: return 2;
7605 case SImode: return 3; /* SPEC_MODE_FOR_EXTEND_LAST */
7606 case DImode: return 4;
7607 case SFmode: return 5;
7608 case DFmode: return 6;
7609 case XFmode: return 7;
7611 /* ??? This mode needs testing. Bypasses for ldfp8 instruction are not
7612 mentioned in itanium[12].md. Predicate fp_register_operand also
7613 needs to be defined. Bottom line: better disable for now. */
7614 return SPEC_MODE_INVALID;
7615 default: return SPEC_MODE_INVALID;
7619 /* Provide information about speculation capabilities. */
7621 ia64_set_sched_flags (spec_info_t spec_info)
7623 unsigned int *flags = &(current_sched_info->flags);
7625 if (*flags & SCHED_RGN
7626 || *flags & SCHED_EBB
7627 || *flags & SEL_SCHED)
7631 if ((mflag_sched_br_data_spec && !reload_completed && optimize > 0)
7632 || (mflag_sched_ar_data_spec && reload_completed))
7637 && ((mflag_sched_br_in_data_spec && !reload_completed)
7638 || (mflag_sched_ar_in_data_spec && reload_completed)))
7642 if (mflag_sched_control_spec
7644 || reload_completed))
7646 mask |= BEGIN_CONTROL;
7648 if (!sel_sched_p () && mflag_sched_in_control_spec)
7649 mask |= BE_IN_CONTROL;
7652 spec_info->mask = mask;
7656 *flags |= USE_DEPS_LIST | DO_SPECULATION;
7658 if (mask & BE_IN_SPEC)
7661 spec_info->flags = 0;
7663 if ((mask & DATA_SPEC) && mflag_sched_prefer_non_data_spec_insns)
7664 spec_info->flags |= PREFER_NON_DATA_SPEC;
7666 if (mask & CONTROL_SPEC)
7668 if (mflag_sched_prefer_non_control_spec_insns)
7669 spec_info->flags |= PREFER_NON_CONTROL_SPEC;
7671 if (sel_sched_p () && mflag_sel_sched_dont_check_control_spec)
7672 spec_info->flags |= SEL_SCHED_SPEC_DONT_CHECK_CONTROL;
7675 if (sched_verbose >= 1)
7676 spec_info->dump = sched_dump;
7678 spec_info->dump = 0;
7680 if (mflag_sched_count_spec_in_critical_path)
7681 spec_info->flags |= COUNT_SPEC_IN_CRITICAL_PATH;
7685 spec_info->mask = 0;
7688 /* If INSN is an appropriate load return its mode.
7689 Return -1 otherwise. */
7691 get_mode_no_for_insn (rtx insn)
7693 rtx reg, mem, mode_rtx;
7697 extract_insn_cached (insn);
7699 /* We use WHICH_ALTERNATIVE only after reload. This will
7700 guarantee that reload won't touch a speculative insn. */
7702 if (recog_data.n_operands != 2)
7705 reg = recog_data.operand[0];
7706 mem = recog_data.operand[1];
7708 /* We should use MEM's mode since REG's mode in presence of
7709 ZERO_EXTEND will always be DImode. */
7710 if (get_attr_speculable1 (insn) == SPECULABLE1_YES)
7711 /* Process non-speculative ld. */
7713 if (!reload_completed)
7715 /* Do not speculate into regs like ar.lc. */
7716 if (!REG_P (reg) || AR_REGNO_P (REGNO (reg)))
7723 rtx mem_reg = XEXP (mem, 0);
7725 if (!REG_P (mem_reg))
7731 else if (get_attr_speculable2 (insn) == SPECULABLE2_YES)
7733 gcc_assert (REG_P (reg) && MEM_P (mem));
7739 else if (get_attr_data_speculative (insn) == DATA_SPECULATIVE_YES
7740 || get_attr_control_speculative (insn) == CONTROL_SPECULATIVE_YES
7741 || get_attr_check_load (insn) == CHECK_LOAD_YES)
7742 /* Process speculative ld or ld.c. */
7744 gcc_assert (REG_P (reg) && MEM_P (mem));
7749 enum attr_itanium_class attr_class = get_attr_itanium_class (insn);
7751 if (attr_class == ITANIUM_CLASS_CHK_A
7752 || attr_class == ITANIUM_CLASS_CHK_S_I
7753 || attr_class == ITANIUM_CLASS_CHK_S_F)
7760 mode_no = ia64_mode_to_int (GET_MODE (mode_rtx));
7762 if (mode_no == SPEC_MODE_INVALID)
7765 extend_p = (GET_MODE (reg) != GET_MODE (mode_rtx));
7769 if (!(SPEC_MODE_FOR_EXTEND_FIRST <= mode_no
7770 && mode_no <= SPEC_MODE_FOR_EXTEND_LAST))
7773 mode_no += SPEC_GEN_EXTEND_OFFSET;
7779 /* If X is an unspec part of a speculative load, return its code.
7780 Return -1 otherwise. */
7782 get_spec_unspec_code (const_rtx x)
7784 if (GET_CODE (x) != UNSPEC)
7806 /* Implement skip_rtx_p hook. */
7808 ia64_skip_rtx_p (const_rtx x)
7810 return get_spec_unspec_code (x) != -1;
7813 /* If INSN is a speculative load, return its UNSPEC code.
7814 Return -1 otherwise. */
7816 get_insn_spec_code (const_rtx insn)
7820 pat = PATTERN (insn);
7822 if (GET_CODE (pat) == COND_EXEC)
7823 pat = COND_EXEC_CODE (pat);
7825 if (GET_CODE (pat) != SET)
7828 reg = SET_DEST (pat);
7832 mem = SET_SRC (pat);
7833 if (GET_CODE (mem) == ZERO_EXTEND)
7834 mem = XEXP (mem, 0);
7836 return get_spec_unspec_code (mem);
7839 /* If INSN is a speculative load, return a ds with the speculation types.
7840 Otherwise [if INSN is a normal instruction] return 0. */
7842 ia64_get_insn_spec_ds (rtx insn)
7844 int code = get_insn_spec_code (insn);
7853 return BEGIN_CONTROL;
7856 return BEGIN_DATA | BEGIN_CONTROL;
7863 /* If INSN is a speculative load return a ds with the speculation types that
7865 Otherwise [if INSN is a normal instruction] return 0. */
7867 ia64_get_insn_checked_ds (rtx insn)
7869 int code = get_insn_spec_code (insn);
7874 return BEGIN_DATA | BEGIN_CONTROL;
7877 return BEGIN_CONTROL;
7881 return BEGIN_DATA | BEGIN_CONTROL;
7888 /* If GEN_P is true, calculate the index of needed speculation check and return
7889 speculative pattern for INSN with speculative mode TS, machine mode
7890 MODE_NO and with ZERO_EXTEND (if EXTEND_P is true).
7891 If GEN_P is false, just calculate the index of needed speculation check. */
7893 ia64_gen_spec_load (rtx insn, ds_t ts, int mode_no)
7896 gen_func_t gen_load;
7898 gen_load = get_spec_load_gen_function (ts, mode_no);
7900 new_pat = gen_load (copy_rtx (recog_data.operand[0]),
7901 copy_rtx (recog_data.operand[1]));
7903 pat = PATTERN (insn);
7904 if (GET_CODE (pat) == COND_EXEC)
7905 new_pat = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (COND_EXEC_TEST (pat)),
7912 insn_can_be_in_speculative_p (rtx insn ATTRIBUTE_UNUSED,
7913 ds_t ds ATTRIBUTE_UNUSED)
7918 /* Implement targetm.sched.speculate_insn hook.
7919 Check if the INSN can be TS speculative.
7920 If 'no' - return -1.
7921 If 'yes' - generate speculative pattern in the NEW_PAT and return 1.
7922 If current pattern of the INSN already provides TS speculation,
7925 ia64_speculate_insn (rtx insn, ds_t ts, rtx *new_pat)
7930 gcc_assert (!(ts & ~SPECULATIVE));
7932 if (ia64_spec_check_p (insn))
7935 if ((ts & BE_IN_SPEC)
7936 && !insn_can_be_in_speculative_p (insn, ts))
7939 mode_no = get_mode_no_for_insn (insn);
7941 if (mode_no != SPEC_MODE_INVALID)
7943 if (ia64_get_insn_spec_ds (insn) == ds_get_speculation_types (ts))
7948 *new_pat = ia64_gen_spec_load (insn, ts, mode_no);
7957 /* Return a function that will generate a check for speculation TS with mode
7959 If simple check is needed, pass true for SIMPLE_CHECK_P.
7960 If clearing check is needed, pass true for CLEARING_CHECK_P. */
7962 get_spec_check_gen_function (ds_t ts, int mode_no,
7963 bool simple_check_p, bool clearing_check_p)
7965 static gen_func_t gen_ld_c_clr[] = {
7975 gen_zero_extendqidi2_clr,
7976 gen_zero_extendhidi2_clr,
7977 gen_zero_extendsidi2_clr,
7979 static gen_func_t gen_ld_c_nc[] = {
7989 gen_zero_extendqidi2_nc,
7990 gen_zero_extendhidi2_nc,
7991 gen_zero_extendsidi2_nc,
7993 static gen_func_t gen_chk_a_clr[] = {
7994 gen_advanced_load_check_clr_bi,
7995 gen_advanced_load_check_clr_qi,
7996 gen_advanced_load_check_clr_hi,
7997 gen_advanced_load_check_clr_si,
7998 gen_advanced_load_check_clr_di,
7999 gen_advanced_load_check_clr_sf,
8000 gen_advanced_load_check_clr_df,
8001 gen_advanced_load_check_clr_xf,
8002 gen_advanced_load_check_clr_ti,
8003 gen_advanced_load_check_clr_di,
8004 gen_advanced_load_check_clr_di,
8005 gen_advanced_load_check_clr_di,
8007 static gen_func_t gen_chk_a_nc[] = {
8008 gen_advanced_load_check_nc_bi,
8009 gen_advanced_load_check_nc_qi,
8010 gen_advanced_load_check_nc_hi,
8011 gen_advanced_load_check_nc_si,
8012 gen_advanced_load_check_nc_di,
8013 gen_advanced_load_check_nc_sf,
8014 gen_advanced_load_check_nc_df,
8015 gen_advanced_load_check_nc_xf,
8016 gen_advanced_load_check_nc_ti,
8017 gen_advanced_load_check_nc_di,
8018 gen_advanced_load_check_nc_di,
8019 gen_advanced_load_check_nc_di,
8021 static gen_func_t gen_chk_s[] = {
8022 gen_speculation_check_bi,
8023 gen_speculation_check_qi,
8024 gen_speculation_check_hi,
8025 gen_speculation_check_si,
8026 gen_speculation_check_di,
8027 gen_speculation_check_sf,
8028 gen_speculation_check_df,
8029 gen_speculation_check_xf,
8030 gen_speculation_check_ti,
8031 gen_speculation_check_di,
8032 gen_speculation_check_di,
8033 gen_speculation_check_di,
8036 gen_func_t *gen_check;
8038 if (ts & BEGIN_DATA)
8040 /* We don't need recovery because even if this is ld.sa
8041 ALAT entry will be allocated only if NAT bit is set to zero.
8042 So it is enough to use ld.c here. */
8046 gcc_assert (mflag_sched_spec_ldc);
8048 if (clearing_check_p)
8049 gen_check = gen_ld_c_clr;
8051 gen_check = gen_ld_c_nc;
8055 if (clearing_check_p)
8056 gen_check = gen_chk_a_clr;
8058 gen_check = gen_chk_a_nc;
8061 else if (ts & BEGIN_CONTROL)
8064 /* We might want to use ld.sa -> ld.c instead of
8067 gcc_assert (!ia64_needs_block_p (ts));
8069 if (clearing_check_p)
8070 gen_check = gen_ld_c_clr;
8072 gen_check = gen_ld_c_nc;
8076 gen_check = gen_chk_s;
8082 gcc_assert (mode_no >= 0);
8083 return gen_check[mode_no];
8086 /* Return nonzero, if INSN needs branchy recovery check. */
8088 ia64_needs_block_p (ds_t ts)
8090 if (ts & BEGIN_DATA)
8091 return !mflag_sched_spec_ldc;
8093 gcc_assert ((ts & BEGIN_CONTROL) != 0);
8095 return !(mflag_sched_spec_control_ldc && mflag_sched_spec_ldc);
8098 /* Generate (or regenerate, if (MUTATE_P)) recovery check for INSN.
8099 If (LABEL != 0 || MUTATE_P), generate branchy recovery check.
8100 Otherwise, generate a simple check. */
8102 ia64_gen_spec_check (rtx insn, rtx label, ds_t ds)
8104 rtx op1, pat, check_pat;
8105 gen_func_t gen_check;
8108 mode_no = get_mode_no_for_insn (insn);
8109 gcc_assert (mode_no >= 0);
8115 gcc_assert (!ia64_needs_block_p (ds));
8116 op1 = copy_rtx (recog_data.operand[1]);
8119 gen_check = get_spec_check_gen_function (ds, mode_no, label == NULL_RTX,
8122 check_pat = gen_check (copy_rtx (recog_data.operand[0]), op1);
8124 pat = PATTERN (insn);
8125 if (GET_CODE (pat) == COND_EXEC)
8126 check_pat = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (COND_EXEC_TEST (pat)),
8132 /* Return nonzero, if X is branchy recovery check. */
8134 ia64_spec_check_p (rtx x)
8137 if (GET_CODE (x) == COND_EXEC)
8138 x = COND_EXEC_CODE (x);
8139 if (GET_CODE (x) == SET)
8140 return ia64_spec_check_src_p (SET_SRC (x));
8144 /* Return nonzero, if SRC belongs to recovery check. */
8146 ia64_spec_check_src_p (rtx src)
8148 if (GET_CODE (src) == IF_THEN_ELSE)
8153 if (GET_CODE (t) == NE)
8157 if (GET_CODE (t) == UNSPEC)
8163 if (code == UNSPEC_LDCCLR
8164 || code == UNSPEC_LDCNC
8165 || code == UNSPEC_CHKACLR
8166 || code == UNSPEC_CHKANC
8167 || code == UNSPEC_CHKS)
8169 gcc_assert (code != 0);
8179 /* The following page contains abstract data `bundle states' which are
8180 used for bundling insns (inserting nops and template generation). */
8182 /* The following describes state of insn bundling. */
8186 /* Unique bundle state number to identify them in the debugging
8189 rtx insn; /* corresponding insn, NULL for the 1st and the last state */
8190 /* number nops before and after the insn */
8191 short before_nops_num, after_nops_num;
8192 int insn_num; /* insn number (0 - for initial state, 1 - for the 1st
8194 int cost; /* cost of the state in cycles */
8195 int accumulated_insns_num; /* number of all previous insns including
8196 nops. L is considered as 2 insns */
8197 int branch_deviation; /* deviation of previous branches from 3rd slots */
8198 int middle_bundle_stops; /* number of stop bits in the middle of bundles */
8199 struct bundle_state *next; /* next state with the same insn_num */
8200 struct bundle_state *originator; /* originator (previous insn state) */
8201 /* All bundle states are in the following chain. */
8202 struct bundle_state *allocated_states_chain;
8203 /* The DFA State after issuing the insn and the nops. */
8207 /* The following is map insn number to the corresponding bundle state. */
8209 static struct bundle_state **index_to_bundle_states;
8211 /* The unique number of next bundle state. */
8213 static int bundle_states_num;
8215 /* All allocated bundle states are in the following chain. */
8217 static struct bundle_state *allocated_bundle_states_chain;
8219 /* All allocated but not used bundle states are in the following
8222 static struct bundle_state *free_bundle_state_chain;
8225 /* The following function returns a free bundle state. */
8227 static struct bundle_state *
8228 get_free_bundle_state (void)
8230 struct bundle_state *result;
8232 if (free_bundle_state_chain != NULL)
8234 result = free_bundle_state_chain;
8235 free_bundle_state_chain = result->next;
8239 result = XNEW (struct bundle_state);
8240 result->dfa_state = xmalloc (dfa_state_size);
8241 result->allocated_states_chain = allocated_bundle_states_chain;
8242 allocated_bundle_states_chain = result;
8244 result->unique_num = bundle_states_num++;
8249 /* The following function frees given bundle state. */
8252 free_bundle_state (struct bundle_state *state)
8254 state->next = free_bundle_state_chain;
8255 free_bundle_state_chain = state;
8258 /* Start work with abstract data `bundle states'. */
8261 initiate_bundle_states (void)
8263 bundle_states_num = 0;
8264 free_bundle_state_chain = NULL;
8265 allocated_bundle_states_chain = NULL;
8268 /* Finish work with abstract data `bundle states'. */
8271 finish_bundle_states (void)
8273 struct bundle_state *curr_state, *next_state;
8275 for (curr_state = allocated_bundle_states_chain;
8277 curr_state = next_state)
8279 next_state = curr_state->allocated_states_chain;
8280 free (curr_state->dfa_state);
8285 /* Hash table of the bundle states. The key is dfa_state and insn_num
8286 of the bundle states. */
8288 static htab_t bundle_state_table;
8290 /* The function returns hash of BUNDLE_STATE. */
8293 bundle_state_hash (const void *bundle_state)
8295 const struct bundle_state *const state
8296 = (const struct bundle_state *) bundle_state;
8299 for (result = i = 0; i < dfa_state_size; i++)
8300 result += (((unsigned char *) state->dfa_state) [i]
8301 << ((i % CHAR_BIT) * 3 + CHAR_BIT));
8302 return result + state->insn_num;
8305 /* The function returns nonzero if the bundle state keys are equal. */
8308 bundle_state_eq_p (const void *bundle_state_1, const void *bundle_state_2)
8310 const struct bundle_state *const state1
8311 = (const struct bundle_state *) bundle_state_1;
8312 const struct bundle_state *const state2
8313 = (const struct bundle_state *) bundle_state_2;
8315 return (state1->insn_num == state2->insn_num
8316 && memcmp (state1->dfa_state, state2->dfa_state,
8317 dfa_state_size) == 0);
8320 /* The function inserts the BUNDLE_STATE into the hash table. The
8321 function returns nonzero if the bundle has been inserted into the
8322 table. The table contains the best bundle state with given key. */
8325 insert_bundle_state (struct bundle_state *bundle_state)
8329 entry_ptr = htab_find_slot (bundle_state_table, bundle_state, INSERT);
8330 if (*entry_ptr == NULL)
8332 bundle_state->next = index_to_bundle_states [bundle_state->insn_num];
8333 index_to_bundle_states [bundle_state->insn_num] = bundle_state;
8334 *entry_ptr = (void *) bundle_state;
8337 else if (bundle_state->cost < ((struct bundle_state *) *entry_ptr)->cost
8338 || (bundle_state->cost == ((struct bundle_state *) *entry_ptr)->cost
8339 && (((struct bundle_state *)*entry_ptr)->accumulated_insns_num
8340 > bundle_state->accumulated_insns_num
8341 || (((struct bundle_state *)
8342 *entry_ptr)->accumulated_insns_num
8343 == bundle_state->accumulated_insns_num
8344 && (((struct bundle_state *)
8345 *entry_ptr)->branch_deviation
8346 > bundle_state->branch_deviation
8347 || (((struct bundle_state *)
8348 *entry_ptr)->branch_deviation
8349 == bundle_state->branch_deviation
8350 && ((struct bundle_state *)
8351 *entry_ptr)->middle_bundle_stops
8352 > bundle_state->middle_bundle_stops))))))
8355 struct bundle_state temp;
8357 temp = *(struct bundle_state *) *entry_ptr;
8358 *(struct bundle_state *) *entry_ptr = *bundle_state;
8359 ((struct bundle_state *) *entry_ptr)->next = temp.next;
8360 *bundle_state = temp;
8365 /* Start work with the hash table. */
8368 initiate_bundle_state_table (void)
8370 bundle_state_table = htab_create (50, bundle_state_hash, bundle_state_eq_p,
8374 /* Finish work with the hash table. */
8377 finish_bundle_state_table (void)
8379 htab_delete (bundle_state_table);
8384 /* The following variable is a insn `nop' used to check bundle states
8385 with different number of inserted nops. */
8387 static rtx ia64_nop;
8389 /* The following function tries to issue NOPS_NUM nops for the current
8390 state without advancing processor cycle. If it failed, the
8391 function returns FALSE and frees the current state. */
8394 try_issue_nops (struct bundle_state *curr_state, int nops_num)
8398 for (i = 0; i < nops_num; i++)
8399 if (state_transition (curr_state->dfa_state, ia64_nop) >= 0)
8401 free_bundle_state (curr_state);
8407 /* The following function tries to issue INSN for the current
8408 state without advancing processor cycle. If it failed, the
8409 function returns FALSE and frees the current state. */
8412 try_issue_insn (struct bundle_state *curr_state, rtx insn)
8414 if (insn && state_transition (curr_state->dfa_state, insn) >= 0)
8416 free_bundle_state (curr_state);
8422 /* The following function tries to issue BEFORE_NOPS_NUM nops and INSN
8423 starting with ORIGINATOR without advancing processor cycle. If
8424 TRY_BUNDLE_END_P is TRUE, the function also/only (if
8425 ONLY_BUNDLE_END_P is TRUE) tries to issue nops to fill all bundle.
8426 If it was successful, the function creates new bundle state and
8427 insert into the hash table and into `index_to_bundle_states'. */
8430 issue_nops_and_insn (struct bundle_state *originator, int before_nops_num,
8431 rtx insn, int try_bundle_end_p, int only_bundle_end_p)
8433 struct bundle_state *curr_state;
8435 curr_state = get_free_bundle_state ();
8436 memcpy (curr_state->dfa_state, originator->dfa_state, dfa_state_size);
8437 curr_state->insn = insn;
8438 curr_state->insn_num = originator->insn_num + 1;
8439 curr_state->cost = originator->cost;
8440 curr_state->originator = originator;
8441 curr_state->before_nops_num = before_nops_num;
8442 curr_state->after_nops_num = 0;
8443 curr_state->accumulated_insns_num
8444 = originator->accumulated_insns_num + before_nops_num;
8445 curr_state->branch_deviation = originator->branch_deviation;
8446 curr_state->middle_bundle_stops = originator->middle_bundle_stops;
8448 if (INSN_CODE (insn) == CODE_FOR_insn_group_barrier)
8450 gcc_assert (GET_MODE (insn) != TImode);
8451 if (!try_issue_nops (curr_state, before_nops_num))
8453 if (!try_issue_insn (curr_state, insn))
8455 memcpy (temp_dfa_state, curr_state->dfa_state, dfa_state_size);
8456 if (curr_state->accumulated_insns_num % 3 != 0)
8457 curr_state->middle_bundle_stops++;
8458 if (state_transition (temp_dfa_state, dfa_pre_cycle_insn) >= 0
8459 && curr_state->accumulated_insns_num % 3 != 0)
8461 free_bundle_state (curr_state);
8465 else if (GET_MODE (insn) != TImode)
8467 if (!try_issue_nops (curr_state, before_nops_num))
8469 if (!try_issue_insn (curr_state, insn))
8471 curr_state->accumulated_insns_num++;
8472 gcc_assert (GET_CODE (PATTERN (insn)) != ASM_INPUT
8473 && asm_noperands (PATTERN (insn)) < 0);
8475 if (ia64_safe_type (insn) == TYPE_L)
8476 curr_state->accumulated_insns_num++;
8480 /* If this is an insn that must be first in a group, then don't allow
8481 nops to be emitted before it. Currently, alloc is the only such
8482 supported instruction. */
8483 /* ??? The bundling automatons should handle this for us, but they do
8484 not yet have support for the first_insn attribute. */
8485 if (before_nops_num > 0 && get_attr_first_insn (insn) == FIRST_INSN_YES)
8487 free_bundle_state (curr_state);
8491 state_transition (curr_state->dfa_state, dfa_pre_cycle_insn);
8492 state_transition (curr_state->dfa_state, NULL);
8494 if (!try_issue_nops (curr_state, before_nops_num))
8496 if (!try_issue_insn (curr_state, insn))
8498 curr_state->accumulated_insns_num++;
8499 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
8500 || asm_noperands (PATTERN (insn)) >= 0)
8502 /* Finish bundle containing asm insn. */
8503 curr_state->after_nops_num
8504 = 3 - curr_state->accumulated_insns_num % 3;
8505 curr_state->accumulated_insns_num
8506 += 3 - curr_state->accumulated_insns_num % 3;
8508 else if (ia64_safe_type (insn) == TYPE_L)
8509 curr_state->accumulated_insns_num++;
8511 if (ia64_safe_type (insn) == TYPE_B)
8512 curr_state->branch_deviation
8513 += 2 - (curr_state->accumulated_insns_num - 1) % 3;
8514 if (try_bundle_end_p && curr_state->accumulated_insns_num % 3 != 0)
8516 if (!only_bundle_end_p && insert_bundle_state (curr_state))
8519 struct bundle_state *curr_state1;
8520 struct bundle_state *allocated_states_chain;
8522 curr_state1 = get_free_bundle_state ();
8523 dfa_state = curr_state1->dfa_state;
8524 allocated_states_chain = curr_state1->allocated_states_chain;
8525 *curr_state1 = *curr_state;
8526 curr_state1->dfa_state = dfa_state;
8527 curr_state1->allocated_states_chain = allocated_states_chain;
8528 memcpy (curr_state1->dfa_state, curr_state->dfa_state,
8530 curr_state = curr_state1;
8532 if (!try_issue_nops (curr_state,
8533 3 - curr_state->accumulated_insns_num % 3))
8535 curr_state->after_nops_num
8536 = 3 - curr_state->accumulated_insns_num % 3;
8537 curr_state->accumulated_insns_num
8538 += 3 - curr_state->accumulated_insns_num % 3;
8540 if (!insert_bundle_state (curr_state))
8541 free_bundle_state (curr_state);
8545 /* The following function returns position in the two window bundle
8549 get_max_pos (state_t state)
8551 if (cpu_unit_reservation_p (state, pos_6))
8553 else if (cpu_unit_reservation_p (state, pos_5))
8555 else if (cpu_unit_reservation_p (state, pos_4))
8557 else if (cpu_unit_reservation_p (state, pos_3))
8559 else if (cpu_unit_reservation_p (state, pos_2))
8561 else if (cpu_unit_reservation_p (state, pos_1))
8567 /* The function returns code of a possible template for given position
8568 and state. The function should be called only with 2 values of
8569 position equal to 3 or 6. We avoid generating F NOPs by putting
8570 templates containing F insns at the end of the template search
8571 because undocumented anomaly in McKinley derived cores which can
8572 cause stalls if an F-unit insn (including a NOP) is issued within a
8573 six-cycle window after reading certain application registers (such
8574 as ar.bsp). Furthermore, power-considerations also argue against
8575 the use of F-unit instructions unless they're really needed. */
8578 get_template (state_t state, int pos)
8583 if (cpu_unit_reservation_p (state, _0mmi_))
8585 else if (cpu_unit_reservation_p (state, _0mii_))
8587 else if (cpu_unit_reservation_p (state, _0mmb_))
8589 else if (cpu_unit_reservation_p (state, _0mib_))
8591 else if (cpu_unit_reservation_p (state, _0mbb_))
8593 else if (cpu_unit_reservation_p (state, _0bbb_))
8595 else if (cpu_unit_reservation_p (state, _0mmf_))
8597 else if (cpu_unit_reservation_p (state, _0mfi_))
8599 else if (cpu_unit_reservation_p (state, _0mfb_))
8601 else if (cpu_unit_reservation_p (state, _0mlx_))
8606 if (cpu_unit_reservation_p (state, _1mmi_))
8608 else if (cpu_unit_reservation_p (state, _1mii_))
8610 else if (cpu_unit_reservation_p (state, _1mmb_))
8612 else if (cpu_unit_reservation_p (state, _1mib_))
8614 else if (cpu_unit_reservation_p (state, _1mbb_))
8616 else if (cpu_unit_reservation_p (state, _1bbb_))
8618 else if (_1mmf_ >= 0 && cpu_unit_reservation_p (state, _1mmf_))
8620 else if (cpu_unit_reservation_p (state, _1mfi_))
8622 else if (cpu_unit_reservation_p (state, _1mfb_))
8624 else if (cpu_unit_reservation_p (state, _1mlx_))
8633 /* True when INSN is important for bundling. */
8635 important_for_bundling_p (rtx insn)
8637 return (INSN_P (insn)
8638 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
8639 && GET_CODE (PATTERN (insn)) != USE
8640 && GET_CODE (PATTERN (insn)) != CLOBBER);
8643 /* The following function returns an insn important for insn bundling
8644 followed by INSN and before TAIL. */
8647 get_next_important_insn (rtx insn, rtx tail)
8649 for (; insn && insn != tail; insn = NEXT_INSN (insn))
8650 if (important_for_bundling_p (insn))
8655 /* Add a bundle selector TEMPLATE0 before INSN. */
8658 ia64_add_bundle_selector_before (int template0, rtx insn)
8660 rtx b = gen_bundle_selector (GEN_INT (template0));
8662 ia64_emit_insn_before (b, insn);
8663 #if NR_BUNDLES == 10
8664 if ((template0 == 4 || template0 == 5)
8665 && ia64_except_unwind_info (&global_options) == UI_TARGET)
8668 rtx note = NULL_RTX;
8670 /* In .mbb and .bbb bundles, check if CALL_INSN isn't in the
8671 first or second slot. If it is and has REG_EH_NOTE set, copy it
8672 to following nops, as br.call sets rp to the address of following
8673 bundle and therefore an EH region end must be on a bundle
8675 insn = PREV_INSN (insn);
8676 for (i = 0; i < 3; i++)
8679 insn = next_active_insn (insn);
8680 while (GET_CODE (insn) == INSN
8681 && get_attr_empty (insn) == EMPTY_YES);
8682 if (GET_CODE (insn) == CALL_INSN)
8683 note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8688 gcc_assert ((code = recog_memoized (insn)) == CODE_FOR_nop
8689 || code == CODE_FOR_nop_b);
8690 if (find_reg_note (insn, REG_EH_REGION, NULL_RTX))
8693 add_reg_note (insn, REG_EH_REGION, XEXP (note, 0));
8700 /* The following function does insn bundling. Bundling means
8701 inserting templates and nop insns to fit insn groups into permitted
8702 templates. Instruction scheduling uses NDFA (non-deterministic
8703 finite automata) encoding informations about the templates and the
8704 inserted nops. Nondeterminism of the automata permits follows
8705 all possible insn sequences very fast.
8707 Unfortunately it is not possible to get information about inserting
8708 nop insns and used templates from the automata states. The
8709 automata only says that we can issue an insn possibly inserting
8710 some nops before it and using some template. Therefore insn
8711 bundling in this function is implemented by using DFA
8712 (deterministic finite automata). We follow all possible insn
8713 sequences by inserting 0-2 nops (that is what the NDFA describe for
8714 insn scheduling) before/after each insn being bundled. We know the
8715 start of simulated processor cycle from insn scheduling (insn
8716 starting a new cycle has TImode).
8718 Simple implementation of insn bundling would create enormous
8719 number of possible insn sequences satisfying information about new
8720 cycle ticks taken from the insn scheduling. To make the algorithm
8721 practical we use dynamic programming. Each decision (about
8722 inserting nops and implicitly about previous decisions) is described
8723 by structure bundle_state (see above). If we generate the same
8724 bundle state (key is automaton state after issuing the insns and
8725 nops for it), we reuse already generated one. As consequence we
8726 reject some decisions which cannot improve the solution and
8727 reduce memory for the algorithm.
8729 When we reach the end of EBB (extended basic block), we choose the
8730 best sequence and then, moving back in EBB, insert templates for
8731 the best alternative. The templates are taken from querying
8732 automaton state for each insn in chosen bundle states.
8734 So the algorithm makes two (forward and backward) passes through
8738 bundling (FILE *dump, int verbose, rtx prev_head_insn, rtx tail)
8740 struct bundle_state *curr_state, *next_state, *best_state;
8741 rtx insn, next_insn;
8743 int i, bundle_end_p, only_bundle_end_p, asm_p;
8744 int pos = 0, max_pos, template0, template1;
8747 enum attr_type type;
8750 /* Count insns in the EBB. */
8751 for (insn = NEXT_INSN (prev_head_insn);
8752 insn && insn != tail;
8753 insn = NEXT_INSN (insn))
8759 dfa_clean_insn_cache ();
8760 initiate_bundle_state_table ();
8761 index_to_bundle_states = XNEWVEC (struct bundle_state *, insn_num + 2);
8762 /* First (forward) pass -- generation of bundle states. */
8763 curr_state = get_free_bundle_state ();
8764 curr_state->insn = NULL;
8765 curr_state->before_nops_num = 0;
8766 curr_state->after_nops_num = 0;
8767 curr_state->insn_num = 0;
8768 curr_state->cost = 0;
8769 curr_state->accumulated_insns_num = 0;
8770 curr_state->branch_deviation = 0;
8771 curr_state->middle_bundle_stops = 0;
8772 curr_state->next = NULL;
8773 curr_state->originator = NULL;
8774 state_reset (curr_state->dfa_state);
8775 index_to_bundle_states [0] = curr_state;
8777 /* Shift cycle mark if it is put on insn which could be ignored. */
8778 for (insn = NEXT_INSN (prev_head_insn);
8780 insn = NEXT_INSN (insn))
8782 && (ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IGNORE
8783 || GET_CODE (PATTERN (insn)) == USE
8784 || GET_CODE (PATTERN (insn)) == CLOBBER)
8785 && GET_MODE (insn) == TImode)
8787 PUT_MODE (insn, VOIDmode);
8788 for (next_insn = NEXT_INSN (insn);
8790 next_insn = NEXT_INSN (next_insn))
8791 if (INSN_P (next_insn)
8792 && ia64_safe_itanium_class (next_insn) != ITANIUM_CLASS_IGNORE
8793 && GET_CODE (PATTERN (next_insn)) != USE
8794 && GET_CODE (PATTERN (next_insn)) != CLOBBER
8795 && INSN_CODE (next_insn) != CODE_FOR_insn_group_barrier)
8797 PUT_MODE (next_insn, TImode);
8801 /* Forward pass: generation of bundle states. */
8802 for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail);
8806 gcc_assert (INSN_P (insn)
8807 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
8808 && GET_CODE (PATTERN (insn)) != USE
8809 && GET_CODE (PATTERN (insn)) != CLOBBER);
8810 type = ia64_safe_type (insn);
8811 next_insn = get_next_important_insn (NEXT_INSN (insn), tail);
8813 index_to_bundle_states [insn_num] = NULL;
8814 for (curr_state = index_to_bundle_states [insn_num - 1];
8816 curr_state = next_state)
8818 pos = curr_state->accumulated_insns_num % 3;
8819 next_state = curr_state->next;
8820 /* We must fill up the current bundle in order to start a
8821 subsequent asm insn in a new bundle. Asm insn is always
8822 placed in a separate bundle. */
8824 = (next_insn != NULL_RTX
8825 && INSN_CODE (insn) == CODE_FOR_insn_group_barrier
8826 && ia64_safe_type (next_insn) == TYPE_UNKNOWN);
8827 /* We may fill up the current bundle if it is the cycle end
8828 without a group barrier. */
8830 = (only_bundle_end_p || next_insn == NULL_RTX
8831 || (GET_MODE (next_insn) == TImode
8832 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier));
8833 if (type == TYPE_F || type == TYPE_B || type == TYPE_L
8835 issue_nops_and_insn (curr_state, 2, insn, bundle_end_p,
8837 issue_nops_and_insn (curr_state, 1, insn, bundle_end_p,
8839 issue_nops_and_insn (curr_state, 0, insn, bundle_end_p,
8842 gcc_assert (index_to_bundle_states [insn_num]);
8843 for (curr_state = index_to_bundle_states [insn_num];
8845 curr_state = curr_state->next)
8846 if (verbose >= 2 && dump)
8848 /* This structure is taken from generated code of the
8849 pipeline hazard recognizer (see file insn-attrtab.c).
8850 Please don't forget to change the structure if a new
8851 automaton is added to .md file. */
8854 unsigned short one_automaton_state;
8855 unsigned short oneb_automaton_state;
8856 unsigned short two_automaton_state;
8857 unsigned short twob_automaton_state;
8862 "// Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, mid.stops %d state %d) for %d\n",
8863 curr_state->unique_num,
8864 (curr_state->originator == NULL
8865 ? -1 : curr_state->originator->unique_num),
8867 curr_state->before_nops_num, curr_state->after_nops_num,
8868 curr_state->accumulated_insns_num, curr_state->branch_deviation,
8869 curr_state->middle_bundle_stops,
8870 ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state,
8875 /* We should find a solution because the 2nd insn scheduling has
8877 gcc_assert (index_to_bundle_states [insn_num]);
8878 /* Find a state corresponding to the best insn sequence. */
8880 for (curr_state = index_to_bundle_states [insn_num];
8882 curr_state = curr_state->next)
8883 /* We are just looking at the states with fully filled up last
8884 bundle. The first we prefer insn sequences with minimal cost
8885 then with minimal inserted nops and finally with branch insns
8886 placed in the 3rd slots. */
8887 if (curr_state->accumulated_insns_num % 3 == 0
8888 && (best_state == NULL || best_state->cost > curr_state->cost
8889 || (best_state->cost == curr_state->cost
8890 && (curr_state->accumulated_insns_num
8891 < best_state->accumulated_insns_num
8892 || (curr_state->accumulated_insns_num
8893 == best_state->accumulated_insns_num
8894 && (curr_state->branch_deviation
8895 < best_state->branch_deviation
8896 || (curr_state->branch_deviation
8897 == best_state->branch_deviation
8898 && curr_state->middle_bundle_stops
8899 < best_state->middle_bundle_stops)))))))
8900 best_state = curr_state;
8901 /* Second (backward) pass: adding nops and templates. */
8902 gcc_assert (best_state);
8903 insn_num = best_state->before_nops_num;
8904 template0 = template1 = -1;
8905 for (curr_state = best_state;
8906 curr_state->originator != NULL;
8907 curr_state = curr_state->originator)
8909 insn = curr_state->insn;
8910 asm_p = (GET_CODE (PATTERN (insn)) == ASM_INPUT
8911 || asm_noperands (PATTERN (insn)) >= 0);
8913 if (verbose >= 2 && dump)
8917 unsigned short one_automaton_state;
8918 unsigned short oneb_automaton_state;
8919 unsigned short two_automaton_state;
8920 unsigned short twob_automaton_state;
8925 "// Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, mid.stops %d, state %d) for %d\n",
8926 curr_state->unique_num,
8927 (curr_state->originator == NULL
8928 ? -1 : curr_state->originator->unique_num),
8930 curr_state->before_nops_num, curr_state->after_nops_num,
8931 curr_state->accumulated_insns_num, curr_state->branch_deviation,
8932 curr_state->middle_bundle_stops,
8933 ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state,
8936 /* Find the position in the current bundle window. The window can
8937 contain at most two bundles. Two bundle window means that
8938 the processor will make two bundle rotation. */
8939 max_pos = get_max_pos (curr_state->dfa_state);
8941 /* The following (negative template number) means that the
8942 processor did one bundle rotation. */
8943 || (max_pos == 3 && template0 < 0))
8945 /* We are at the end of the window -- find template(s) for
8949 template0 = get_template (curr_state->dfa_state, 3);
8952 template1 = get_template (curr_state->dfa_state, 3);
8953 template0 = get_template (curr_state->dfa_state, 6);
8956 if (max_pos > 3 && template1 < 0)
8957 /* It may happen when we have the stop inside a bundle. */
8959 gcc_assert (pos <= 3);
8960 template1 = get_template (curr_state->dfa_state, 3);
8964 /* Emit nops after the current insn. */
8965 for (i = 0; i < curr_state->after_nops_num; i++)
8968 emit_insn_after (nop, insn);
8970 gcc_assert (pos >= 0);
8973 /* We are at the start of a bundle: emit the template
8974 (it should be defined). */
8975 gcc_assert (template0 >= 0);
8976 ia64_add_bundle_selector_before (template0, nop);
8977 /* If we have two bundle window, we make one bundle
8978 rotation. Otherwise template0 will be undefined
8979 (negative value). */
8980 template0 = template1;
8984 /* Move the position backward in the window. Group barrier has
8985 no slot. Asm insn takes all bundle. */
8986 if (INSN_CODE (insn) != CODE_FOR_insn_group_barrier
8987 && GET_CODE (PATTERN (insn)) != ASM_INPUT
8988 && asm_noperands (PATTERN (insn)) < 0)
8990 /* Long insn takes 2 slots. */
8991 if (ia64_safe_type (insn) == TYPE_L)
8993 gcc_assert (pos >= 0);
8995 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier
8996 && GET_CODE (PATTERN (insn)) != ASM_INPUT
8997 && asm_noperands (PATTERN (insn)) < 0)
8999 /* The current insn is at the bundle start: emit the
9001 gcc_assert (template0 >= 0);
9002 ia64_add_bundle_selector_before (template0, insn);
9003 b = PREV_INSN (insn);
9005 /* See comment above in analogous place for emitting nops
9007 template0 = template1;
9010 /* Emit nops after the current insn. */
9011 for (i = 0; i < curr_state->before_nops_num; i++)
9014 ia64_emit_insn_before (nop, insn);
9015 nop = PREV_INSN (insn);
9018 gcc_assert (pos >= 0);
9021 /* See comment above in analogous place for emitting nops
9023 gcc_assert (template0 >= 0);
9024 ia64_add_bundle_selector_before (template0, insn);
9025 b = PREV_INSN (insn);
9027 template0 = template1;
9033 #ifdef ENABLE_CHECKING
9035 /* Assert right calculation of middle_bundle_stops. */
9036 int num = best_state->middle_bundle_stops;
9037 bool start_bundle = true, end_bundle = false;
9039 for (insn = NEXT_INSN (prev_head_insn);
9040 insn && insn != tail;
9041 insn = NEXT_INSN (insn))
9045 if (recog_memoized (insn) == CODE_FOR_bundle_selector)
9046 start_bundle = true;
9051 for (next_insn = NEXT_INSN (insn);
9052 next_insn && next_insn != tail;
9053 next_insn = NEXT_INSN (next_insn))
9054 if (INSN_P (next_insn)
9055 && (ia64_safe_itanium_class (next_insn)
9056 != ITANIUM_CLASS_IGNORE
9057 || recog_memoized (next_insn)
9058 == CODE_FOR_bundle_selector)
9059 && GET_CODE (PATTERN (next_insn)) != USE
9060 && GET_CODE (PATTERN (next_insn)) != CLOBBER)
9063 end_bundle = next_insn == NULL_RTX
9064 || next_insn == tail
9065 || (INSN_P (next_insn)
9066 && recog_memoized (next_insn)
9067 == CODE_FOR_bundle_selector);
9068 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier
9069 && !start_bundle && !end_bundle
9071 && GET_CODE (PATTERN (next_insn)) != ASM_INPUT
9072 && asm_noperands (PATTERN (next_insn)) < 0)
9075 start_bundle = false;
9079 gcc_assert (num == 0);
9083 free (index_to_bundle_states);
9084 finish_bundle_state_table ();
9086 dfa_clean_insn_cache ();
9089 /* The following function is called at the end of scheduling BB or
9090 EBB. After reload, it inserts stop bits and does insn bundling. */
9093 ia64_sched_finish (FILE *dump, int sched_verbose)
9096 fprintf (dump, "// Finishing schedule.\n");
9097 if (!reload_completed)
9099 if (reload_completed)
9101 final_emit_insn_group_barriers (dump);
9102 bundling (dump, sched_verbose, current_sched_info->prev_head,
9103 current_sched_info->next_tail);
9104 if (sched_verbose && dump)
9105 fprintf (dump, "// finishing %d-%d\n",
9106 INSN_UID (NEXT_INSN (current_sched_info->prev_head)),
9107 INSN_UID (PREV_INSN (current_sched_info->next_tail)));
9113 /* The following function inserts stop bits in scheduled BB or EBB. */
9116 final_emit_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED)
9119 int need_barrier_p = 0;
9120 int seen_good_insn = 0;
9122 init_insn_group_barriers ();
9124 for (insn = NEXT_INSN (current_sched_info->prev_head);
9125 insn != current_sched_info->next_tail;
9126 insn = NEXT_INSN (insn))
9128 if (GET_CODE (insn) == BARRIER)
9130 rtx last = prev_active_insn (insn);
9134 if (GET_CODE (last) == JUMP_INSN
9135 && GET_CODE (PATTERN (last)) == ADDR_DIFF_VEC)
9136 last = prev_active_insn (last);
9137 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
9138 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
9140 init_insn_group_barriers ();
9144 else if (NONDEBUG_INSN_P (insn))
9146 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
9148 init_insn_group_barriers ();
9152 else if (need_barrier_p || group_barrier_needed (insn)
9153 || (mflag_sched_stop_bits_after_every_cycle
9154 && GET_MODE (insn) == TImode
9157 if (TARGET_EARLY_STOP_BITS)
9162 last != current_sched_info->prev_head;
9163 last = PREV_INSN (last))
9164 if (INSN_P (last) && GET_MODE (last) == TImode
9165 && stops_p [INSN_UID (last)])
9167 if (last == current_sched_info->prev_head)
9169 last = prev_active_insn (last);
9171 && recog_memoized (last) != CODE_FOR_insn_group_barrier)
9172 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)),
9174 init_insn_group_barriers ();
9175 for (last = NEXT_INSN (last);
9177 last = NEXT_INSN (last))
9180 group_barrier_needed (last);
9181 if (recog_memoized (last) >= 0
9182 && important_for_bundling_p (last))
9188 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
9190 init_insn_group_barriers ();
9193 group_barrier_needed (insn);
9194 if (recog_memoized (insn) >= 0
9195 && important_for_bundling_p (insn))
9198 else if (recog_memoized (insn) >= 0
9199 && important_for_bundling_p (insn))
9201 need_barrier_p = (GET_CODE (insn) == CALL_INSN
9202 || GET_CODE (PATTERN (insn)) == ASM_INPUT
9203 || asm_noperands (PATTERN (insn)) >= 0);
9210 /* If the following function returns TRUE, we will use the DFA
9214 ia64_first_cycle_multipass_dfa_lookahead (void)
9216 return (reload_completed ? 6 : 4);
9219 /* The following function initiates variable `dfa_pre_cycle_insn'. */
9222 ia64_init_dfa_pre_cycle_insn (void)
9224 if (temp_dfa_state == NULL)
9226 dfa_state_size = state_size ();
9227 temp_dfa_state = xmalloc (dfa_state_size);
9228 prev_cycle_state = xmalloc (dfa_state_size);
9230 dfa_pre_cycle_insn = make_insn_raw (gen_pre_cycle ());
9231 PREV_INSN (dfa_pre_cycle_insn) = NEXT_INSN (dfa_pre_cycle_insn) = NULL_RTX;
9232 recog_memoized (dfa_pre_cycle_insn);
9233 dfa_stop_insn = make_insn_raw (gen_insn_group_barrier (GEN_INT (3)));
9234 PREV_INSN (dfa_stop_insn) = NEXT_INSN (dfa_stop_insn) = NULL_RTX;
9235 recog_memoized (dfa_stop_insn);
9238 /* The following function returns the pseudo insn DFA_PRE_CYCLE_INSN
9239 used by the DFA insn scheduler. */
9242 ia64_dfa_pre_cycle_insn (void)
9244 return dfa_pre_cycle_insn;
9247 /* The following function returns TRUE if PRODUCER (of type ilog or
9248 ld) produces address for CONSUMER (of type st or stf). */
9251 ia64_st_address_bypass_p (rtx producer, rtx consumer)
9255 gcc_assert (producer && consumer);
9256 dest = ia64_single_set (producer);
9258 reg = SET_DEST (dest);
9260 if (GET_CODE (reg) == SUBREG)
9261 reg = SUBREG_REG (reg);
9262 gcc_assert (GET_CODE (reg) == REG);
9264 dest = ia64_single_set (consumer);
9266 mem = SET_DEST (dest);
9267 gcc_assert (mem && GET_CODE (mem) == MEM);
9268 return reg_mentioned_p (reg, mem);
9271 /* The following function returns TRUE if PRODUCER (of type ilog or
9272 ld) produces address for CONSUMER (of type ld or fld). */
9275 ia64_ld_address_bypass_p (rtx producer, rtx consumer)
9277 rtx dest, src, reg, mem;
9279 gcc_assert (producer && consumer);
9280 dest = ia64_single_set (producer);
9282 reg = SET_DEST (dest);
9284 if (GET_CODE (reg) == SUBREG)
9285 reg = SUBREG_REG (reg);
9286 gcc_assert (GET_CODE (reg) == REG);
9288 src = ia64_single_set (consumer);
9290 mem = SET_SRC (src);
9293 if (GET_CODE (mem) == UNSPEC && XVECLEN (mem, 0) > 0)
9294 mem = XVECEXP (mem, 0, 0);
9295 else if (GET_CODE (mem) == IF_THEN_ELSE)
9296 /* ??? Is this bypass necessary for ld.c? */
9298 gcc_assert (XINT (XEXP (XEXP (mem, 0), 0), 1) == UNSPEC_LDCCLR);
9299 mem = XEXP (mem, 1);
9302 while (GET_CODE (mem) == SUBREG || GET_CODE (mem) == ZERO_EXTEND)
9303 mem = XEXP (mem, 0);
9305 if (GET_CODE (mem) == UNSPEC)
9307 int c = XINT (mem, 1);
9309 gcc_assert (c == UNSPEC_LDA || c == UNSPEC_LDS || c == UNSPEC_LDS_A
9310 || c == UNSPEC_LDSA);
9311 mem = XVECEXP (mem, 0, 0);
9314 /* Note that LO_SUM is used for GOT loads. */
9315 gcc_assert (GET_CODE (mem) == LO_SUM || GET_CODE (mem) == MEM);
9317 return reg_mentioned_p (reg, mem);
9320 /* The following function returns TRUE if INSN produces address for a
9321 load/store insn. We will place such insns into M slot because it
9322 decreases its latency time. */
9325 ia64_produce_address_p (rtx insn)
9331 /* Emit pseudo-ops for the assembler to describe predicate relations.
9332 At present this assumes that we only consider predicate pairs to
9333 be mutex, and that the assembler can deduce proper values from
9334 straight-line code. */
9337 emit_predicate_relation_info (void)
9341 FOR_EACH_BB_REVERSE (bb)
9344 rtx head = BB_HEAD (bb);
9346 /* We only need such notes at code labels. */
9347 if (GET_CODE (head) != CODE_LABEL)
9349 if (NOTE_INSN_BASIC_BLOCK_P (NEXT_INSN (head)))
9350 head = NEXT_INSN (head);
9352 /* Skip p0, which may be thought to be live due to (reg:DI p0)
9353 grabbing the entire block of predicate registers. */
9354 for (r = PR_REG (2); r < PR_REG (64); r += 2)
9355 if (REGNO_REG_SET_P (df_get_live_in (bb), r))
9357 rtx p = gen_rtx_REG (BImode, r);
9358 rtx n = emit_insn_after (gen_pred_rel_mutex (p), head);
9359 if (head == BB_END (bb))
9365 /* Look for conditional calls that do not return, and protect predicate
9366 relations around them. Otherwise the assembler will assume the call
9367 returns, and complain about uses of call-clobbered predicates after
9369 FOR_EACH_BB_REVERSE (bb)
9371 rtx insn = BB_HEAD (bb);
9375 if (GET_CODE (insn) == CALL_INSN
9376 && GET_CODE (PATTERN (insn)) == COND_EXEC
9377 && find_reg_note (insn, REG_NORETURN, NULL_RTX))
9379 rtx b = emit_insn_before (gen_safe_across_calls_all (), insn);
9380 rtx a = emit_insn_after (gen_safe_across_calls_normal (), insn);
9381 if (BB_HEAD (bb) == insn)
9383 if (BB_END (bb) == insn)
9387 if (insn == BB_END (bb))
9389 insn = NEXT_INSN (insn);
9394 /* Perform machine dependent operations on the rtl chain INSNS. */
9399 /* We are freeing block_for_insn in the toplev to keep compatibility
9400 with old MDEP_REORGS that are not CFG based. Recompute it now. */
9401 compute_bb_for_insn ();
9403 /* If optimizing, we'll have split before scheduling. */
9407 if (optimize && ia64_flag_schedule_insns2
9408 && dbg_cnt (ia64_sched2))
9410 timevar_push (TV_SCHED2);
9411 ia64_final_schedule = 1;
9413 initiate_bundle_states ();
9414 ia64_nop = make_insn_raw (gen_nop ());
9415 PREV_INSN (ia64_nop) = NEXT_INSN (ia64_nop) = NULL_RTX;
9416 recog_memoized (ia64_nop);
9417 clocks_length = get_max_uid () + 1;
9418 stops_p = XCNEWVEC (char, clocks_length);
9420 if (ia64_tune == PROCESSOR_ITANIUM2)
9422 pos_1 = get_cpu_unit_code ("2_1");
9423 pos_2 = get_cpu_unit_code ("2_2");
9424 pos_3 = get_cpu_unit_code ("2_3");
9425 pos_4 = get_cpu_unit_code ("2_4");
9426 pos_5 = get_cpu_unit_code ("2_5");
9427 pos_6 = get_cpu_unit_code ("2_6");
9428 _0mii_ = get_cpu_unit_code ("2b_0mii.");
9429 _0mmi_ = get_cpu_unit_code ("2b_0mmi.");
9430 _0mfi_ = get_cpu_unit_code ("2b_0mfi.");
9431 _0mmf_ = get_cpu_unit_code ("2b_0mmf.");
9432 _0bbb_ = get_cpu_unit_code ("2b_0bbb.");
9433 _0mbb_ = get_cpu_unit_code ("2b_0mbb.");
9434 _0mib_ = get_cpu_unit_code ("2b_0mib.");
9435 _0mmb_ = get_cpu_unit_code ("2b_0mmb.");
9436 _0mfb_ = get_cpu_unit_code ("2b_0mfb.");
9437 _0mlx_ = get_cpu_unit_code ("2b_0mlx.");
9438 _1mii_ = get_cpu_unit_code ("2b_1mii.");
9439 _1mmi_ = get_cpu_unit_code ("2b_1mmi.");
9440 _1mfi_ = get_cpu_unit_code ("2b_1mfi.");
9441 _1mmf_ = get_cpu_unit_code ("2b_1mmf.");
9442 _1bbb_ = get_cpu_unit_code ("2b_1bbb.");
9443 _1mbb_ = get_cpu_unit_code ("2b_1mbb.");
9444 _1mib_ = get_cpu_unit_code ("2b_1mib.");
9445 _1mmb_ = get_cpu_unit_code ("2b_1mmb.");
9446 _1mfb_ = get_cpu_unit_code ("2b_1mfb.");
9447 _1mlx_ = get_cpu_unit_code ("2b_1mlx.");
9451 pos_1 = get_cpu_unit_code ("1_1");
9452 pos_2 = get_cpu_unit_code ("1_2");
9453 pos_3 = get_cpu_unit_code ("1_3");
9454 pos_4 = get_cpu_unit_code ("1_4");
9455 pos_5 = get_cpu_unit_code ("1_5");
9456 pos_6 = get_cpu_unit_code ("1_6");
9457 _0mii_ = get_cpu_unit_code ("1b_0mii.");
9458 _0mmi_ = get_cpu_unit_code ("1b_0mmi.");
9459 _0mfi_ = get_cpu_unit_code ("1b_0mfi.");
9460 _0mmf_ = get_cpu_unit_code ("1b_0mmf.");
9461 _0bbb_ = get_cpu_unit_code ("1b_0bbb.");
9462 _0mbb_ = get_cpu_unit_code ("1b_0mbb.");
9463 _0mib_ = get_cpu_unit_code ("1b_0mib.");
9464 _0mmb_ = get_cpu_unit_code ("1b_0mmb.");
9465 _0mfb_ = get_cpu_unit_code ("1b_0mfb.");
9466 _0mlx_ = get_cpu_unit_code ("1b_0mlx.");
9467 _1mii_ = get_cpu_unit_code ("1b_1mii.");
9468 _1mmi_ = get_cpu_unit_code ("1b_1mmi.");
9469 _1mfi_ = get_cpu_unit_code ("1b_1mfi.");
9470 _1mmf_ = get_cpu_unit_code ("1b_1mmf.");
9471 _1bbb_ = get_cpu_unit_code ("1b_1bbb.");
9472 _1mbb_ = get_cpu_unit_code ("1b_1mbb.");
9473 _1mib_ = get_cpu_unit_code ("1b_1mib.");
9474 _1mmb_ = get_cpu_unit_code ("1b_1mmb.");
9475 _1mfb_ = get_cpu_unit_code ("1b_1mfb.");
9476 _1mlx_ = get_cpu_unit_code ("1b_1mlx.");
9479 if (flag_selective_scheduling2
9480 && !maybe_skip_selective_scheduling ())
9481 run_selective_scheduling ();
9485 /* Redo alignment computation, as it might gone wrong. */
9486 compute_alignments ();
9488 /* We cannot reuse this one because it has been corrupted by the
9490 finish_bundle_states ();
9493 emit_insn_group_barriers (dump_file);
9495 ia64_final_schedule = 0;
9496 timevar_pop (TV_SCHED2);
9499 emit_all_insn_group_barriers (dump_file);
9503 /* A call must not be the last instruction in a function, so that the
9504 return address is still within the function, so that unwinding works
9505 properly. Note that IA-64 differs from dwarf2 on this point. */
9506 if (ia64_except_unwind_info (&global_options) == UI_TARGET)
9511 insn = get_last_insn ();
9512 if (! INSN_P (insn))
9513 insn = prev_active_insn (insn);
9516 /* Skip over insns that expand to nothing. */
9517 while (GET_CODE (insn) == INSN
9518 && get_attr_empty (insn) == EMPTY_YES)
9520 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
9521 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
9523 insn = prev_active_insn (insn);
9525 if (GET_CODE (insn) == CALL_INSN)
9528 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
9529 emit_insn (gen_break_f ());
9530 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
9535 emit_predicate_relation_info ();
9537 if (ia64_flag_var_tracking)
9539 timevar_push (TV_VAR_TRACKING);
9540 variable_tracking_main ();
9541 timevar_pop (TV_VAR_TRACKING);
9543 df_finish_pass (false);
9546 /* Return true if REGNO is used by the epilogue. */
9549 ia64_epilogue_uses (int regno)
9554 /* With a call to a function in another module, we will write a new
9555 value to "gp". After returning from such a call, we need to make
9556 sure the function restores the original gp-value, even if the
9557 function itself does not use the gp anymore. */
9558 return !(TARGET_AUTO_PIC || TARGET_NO_PIC);
9560 case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3):
9561 case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7):
9562 /* For functions defined with the syscall_linkage attribute, all
9563 input registers are marked as live at all function exits. This
9564 prevents the register allocator from using the input registers,
9565 which in turn makes it possible to restart a system call after
9566 an interrupt without having to save/restore the input registers.
9567 This also prevents kernel data from leaking to application code. */
9568 return lookup_attribute ("syscall_linkage",
9569 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))) != NULL;
9572 /* Conditional return patterns can't represent the use of `b0' as
9573 the return address, so we force the value live this way. */
9577 /* Likewise for ar.pfs, which is used by br.ret. */
9585 /* Return true if REGNO is used by the frame unwinder. */
9588 ia64_eh_uses (int regno)
9592 if (! reload_completed)
9598 for (r = reg_save_b0; r <= reg_save_ar_lc; r++)
9599 if (regno == current_frame_info.r[r]
9600 || regno == emitted_frame_related_regs[r])
9606 /* Return true if this goes in small data/bss. */
9608 /* ??? We could also support own long data here. Generating movl/add/ld8
9609 instead of addl,ld8/ld8. This makes the code bigger, but should make the
9610 code faster because there is one less load. This also includes incomplete
9611 types which can't go in sdata/sbss. */
9614 ia64_in_small_data_p (const_tree exp)
9616 if (TARGET_NO_SDATA)
9619 /* We want to merge strings, so we never consider them small data. */
9620 if (TREE_CODE (exp) == STRING_CST)
9623 /* Functions are never small data. */
9624 if (TREE_CODE (exp) == FUNCTION_DECL)
9627 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
9629 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
9631 if (strcmp (section, ".sdata") == 0
9632 || strncmp (section, ".sdata.", 7) == 0
9633 || strncmp (section, ".gnu.linkonce.s.", 16) == 0
9634 || strcmp (section, ".sbss") == 0
9635 || strncmp (section, ".sbss.", 6) == 0
9636 || strncmp (section, ".gnu.linkonce.sb.", 17) == 0)
9641 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
9643 /* If this is an incomplete type with size 0, then we can't put it
9644 in sdata because it might be too big when completed. */
9645 if (size > 0 && size <= ia64_section_threshold)
9652 /* Output assembly directives for prologue regions. */
9654 /* The current basic block number. */
9656 static bool last_block;
9658 /* True if we need a copy_state command at the start of the next block. */
9660 static bool need_copy_state;
9662 #ifndef MAX_ARTIFICIAL_LABEL_BYTES
9663 # define MAX_ARTIFICIAL_LABEL_BYTES 30
9666 /* Emit a debugging label after a call-frame-related insn. We'd
9667 rather output the label right away, but we'd have to output it
9668 after, not before, the instruction, and the instruction has not
9669 been output yet. So we emit the label after the insn, delete it to
9670 avoid introducing basic blocks, and mark it as preserved, such that
9671 it is still output, given that it is referenced in debug info. */
9674 ia64_emit_deleted_label_after_insn (rtx insn)
9676 char label[MAX_ARTIFICIAL_LABEL_BYTES];
9677 rtx lb = gen_label_rtx ();
9678 rtx label_insn = emit_label_after (lb, insn);
9680 LABEL_PRESERVE_P (lb) = 1;
9682 delete_insn (label_insn);
9684 ASM_GENERATE_INTERNAL_LABEL (label, "L", CODE_LABEL_NUMBER (label_insn));
9686 return xstrdup (label);
9689 /* Define the CFA after INSN with the steady-state definition. */
9692 ia64_dwarf2out_def_steady_cfa (rtx insn, bool frame)
9694 rtx fp = frame_pointer_needed
9695 ? hard_frame_pointer_rtx
9696 : stack_pointer_rtx;
9697 const char *label = ia64_emit_deleted_label_after_insn (insn);
9704 ia64_initial_elimination_offset
9705 (REGNO (arg_pointer_rtx), REGNO (fp))
9706 + ARG_POINTER_CFA_OFFSET (current_function_decl));
9709 /* All we need to do here is avoid a crash in the generic dwarf2
9710 processing. The real CFA definition is set up above. */
9713 ia64_dwarf_handle_frame_unspec (const char * ARG_UNUSED (label),
9714 rtx ARG_UNUSED (pattern),
9717 gcc_assert (index == UNSPECV_ALLOC);
9720 /* The generic dwarf2 frame debug info generator does not define a
9721 separate region for the very end of the epilogue, so refrain from
9722 doing so in the IA64-specific code as well. */
9724 #define IA64_CHANGE_CFA_IN_EPILOGUE 0
9726 /* The function emits unwind directives for the start of an epilogue. */
9729 process_epilogue (FILE *asm_out_file, rtx insn, bool unwind, bool frame)
9731 /* If this isn't the last block of the function, then we need to label the
9732 current state, and copy it back in at the start of the next block. */
9737 fprintf (asm_out_file, "\t.label_state %d\n",
9738 ++cfun->machine->state_num);
9739 need_copy_state = true;
9743 fprintf (asm_out_file, "\t.restore sp\n");
9744 if (IA64_CHANGE_CFA_IN_EPILOGUE && frame)
9745 dwarf2out_def_cfa (ia64_emit_deleted_label_after_insn (insn),
9746 STACK_POINTER_REGNUM, INCOMING_FRAME_SP_OFFSET);
9749 /* This function processes a SET pattern for REG_CFA_ADJUST_CFA. */
9752 process_cfa_adjust_cfa (FILE *asm_out_file, rtx pat, rtx insn,
9753 bool unwind, bool frame)
9755 rtx dest = SET_DEST (pat);
9756 rtx src = SET_SRC (pat);
9758 if (dest == stack_pointer_rtx)
9760 if (GET_CODE (src) == PLUS)
9762 rtx op0 = XEXP (src, 0);
9763 rtx op1 = XEXP (src, 1);
9765 gcc_assert (op0 == dest && GET_CODE (op1) == CONST_INT);
9767 if (INTVAL (op1) < 0)
9769 gcc_assert (!frame_pointer_needed);
9771 fprintf (asm_out_file,
9772 "\t.fframe "HOST_WIDE_INT_PRINT_DEC"\n",
9774 ia64_dwarf2out_def_steady_cfa (insn, frame);
9777 process_epilogue (asm_out_file, insn, unwind, frame);
9781 gcc_assert (src == hard_frame_pointer_rtx);
9782 process_epilogue (asm_out_file, insn, unwind, frame);
9785 else if (dest == hard_frame_pointer_rtx)
9787 gcc_assert (src == stack_pointer_rtx);
9788 gcc_assert (frame_pointer_needed);
9791 fprintf (asm_out_file, "\t.vframe r%d\n",
9792 ia64_dbx_register_number (REGNO (dest)));
9793 ia64_dwarf2out_def_steady_cfa (insn, frame);
9799 /* This function processes a SET pattern for REG_CFA_REGISTER. */
9802 process_cfa_register (FILE *asm_out_file, rtx pat, bool unwind)
9804 rtx dest = SET_DEST (pat);
9805 rtx src = SET_SRC (pat);
9807 int dest_regno = REGNO (dest);
9808 int src_regno = REGNO (src);
9813 /* Saving return address pointer. */
9814 gcc_assert (dest_regno == current_frame_info.r[reg_save_b0]);
9816 fprintf (asm_out_file, "\t.save rp, r%d\n",
9817 ia64_dbx_register_number (dest_regno));
9821 gcc_assert (dest_regno == current_frame_info.r[reg_save_pr]);
9823 fprintf (asm_out_file, "\t.save pr, r%d\n",
9824 ia64_dbx_register_number (dest_regno));
9827 case AR_UNAT_REGNUM:
9828 gcc_assert (dest_regno == current_frame_info.r[reg_save_ar_unat]);
9830 fprintf (asm_out_file, "\t.save ar.unat, r%d\n",
9831 ia64_dbx_register_number (dest_regno));
9835 gcc_assert (dest_regno == current_frame_info.r[reg_save_ar_lc]);
9837 fprintf (asm_out_file, "\t.save ar.lc, r%d\n",
9838 ia64_dbx_register_number (dest_regno));
9842 /* Everything else should indicate being stored to memory. */
9847 /* This function processes a SET pattern for REG_CFA_OFFSET. */
9850 process_cfa_offset (FILE *asm_out_file, rtx pat, bool unwind)
9852 rtx dest = SET_DEST (pat);
9853 rtx src = SET_SRC (pat);
9854 int src_regno = REGNO (src);
9859 gcc_assert (MEM_P (dest));
9860 if (GET_CODE (XEXP (dest, 0)) == REG)
9862 base = XEXP (dest, 0);
9867 gcc_assert (GET_CODE (XEXP (dest, 0)) == PLUS
9868 && GET_CODE (XEXP (XEXP (dest, 0), 1)) == CONST_INT);
9869 base = XEXP (XEXP (dest, 0), 0);
9870 off = INTVAL (XEXP (XEXP (dest, 0), 1));
9873 if (base == hard_frame_pointer_rtx)
9875 saveop = ".savepsp";
9880 gcc_assert (base == stack_pointer_rtx);
9884 src_regno = REGNO (src);
9888 gcc_assert (!current_frame_info.r[reg_save_b0]);
9890 fprintf (asm_out_file, "\t%s rp, " HOST_WIDE_INT_PRINT_DEC "\n",
9895 gcc_assert (!current_frame_info.r[reg_save_pr]);
9897 fprintf (asm_out_file, "\t%s pr, " HOST_WIDE_INT_PRINT_DEC "\n",
9902 gcc_assert (!current_frame_info.r[reg_save_ar_lc]);
9904 fprintf (asm_out_file, "\t%s ar.lc, " HOST_WIDE_INT_PRINT_DEC "\n",
9909 gcc_assert (!current_frame_info.r[reg_save_ar_pfs]);
9911 fprintf (asm_out_file, "\t%s ar.pfs, " HOST_WIDE_INT_PRINT_DEC "\n",
9915 case AR_UNAT_REGNUM:
9916 gcc_assert (!current_frame_info.r[reg_save_ar_unat]);
9918 fprintf (asm_out_file, "\t%s ar.unat, " HOST_WIDE_INT_PRINT_DEC "\n",
9927 fprintf (asm_out_file, "\t.save.g 0x%x\n",
9928 1 << (src_regno - GR_REG (4)));
9937 fprintf (asm_out_file, "\t.save.b 0x%x\n",
9938 1 << (src_regno - BR_REG (1)));
9946 fprintf (asm_out_file, "\t.save.f 0x%x\n",
9947 1 << (src_regno - FR_REG (2)));
9950 case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19):
9951 case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23):
9952 case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27):
9953 case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31):
9955 fprintf (asm_out_file, "\t.save.gf 0x0, 0x%x\n",
9956 1 << (src_regno - FR_REG (12)));
9960 /* ??? For some reason we mark other general registers, even those
9961 we can't represent in the unwind info. Ignore them. */
9966 /* This function looks at a single insn and emits any directives
9967 required to unwind this insn. */
9970 ia64_asm_unwind_emit (FILE *asm_out_file, rtx insn)
9972 bool unwind = ia64_except_unwind_info (&global_options) == UI_TARGET;
9973 bool frame = dwarf2out_do_frame ();
9977 if (!unwind && !frame)
9980 if (NOTE_INSN_BASIC_BLOCK_P (insn))
9982 last_block = NOTE_BASIC_BLOCK (insn)->next_bb == EXIT_BLOCK_PTR;
9984 /* Restore unwind state from immediately before the epilogue. */
9985 if (need_copy_state)
9989 fprintf (asm_out_file, "\t.body\n");
9990 fprintf (asm_out_file, "\t.copy_state %d\n",
9991 cfun->machine->state_num);
9993 if (IA64_CHANGE_CFA_IN_EPILOGUE)
9994 ia64_dwarf2out_def_steady_cfa (insn, frame);
9995 need_copy_state = false;
9999 if (GET_CODE (insn) == NOTE || ! RTX_FRAME_RELATED_P (insn))
10002 /* Look for the ALLOC insn. */
10003 if (INSN_CODE (insn) == CODE_FOR_alloc)
10005 rtx dest = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
10006 int dest_regno = REGNO (dest);
10008 /* If this is the final destination for ar.pfs, then this must
10009 be the alloc in the prologue. */
10010 if (dest_regno == current_frame_info.r[reg_save_ar_pfs])
10013 fprintf (asm_out_file, "\t.save ar.pfs, r%d\n",
10014 ia64_dbx_register_number (dest_regno));
10018 /* This must be an alloc before a sibcall. We must drop the
10019 old frame info. The easiest way to drop the old frame
10020 info is to ensure we had a ".restore sp" directive
10021 followed by a new prologue. If the procedure doesn't
10022 have a memory-stack frame, we'll issue a dummy ".restore
10024 if (current_frame_info.total_size == 0 && !frame_pointer_needed)
10025 /* if haven't done process_epilogue() yet, do it now */
10026 process_epilogue (asm_out_file, insn, unwind, frame);
10028 fprintf (asm_out_file, "\t.prologue\n");
10033 handled_one = false;
10034 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
10035 switch (REG_NOTE_KIND (note))
10037 case REG_CFA_ADJUST_CFA:
10038 pat = XEXP (note, 0);
10040 pat = PATTERN (insn);
10041 process_cfa_adjust_cfa (asm_out_file, pat, insn, unwind, frame);
10042 handled_one = true;
10045 case REG_CFA_OFFSET:
10046 pat = XEXP (note, 0);
10048 pat = PATTERN (insn);
10049 process_cfa_offset (asm_out_file, pat, unwind);
10050 handled_one = true;
10053 case REG_CFA_REGISTER:
10054 pat = XEXP (note, 0);
10056 pat = PATTERN (insn);
10057 process_cfa_register (asm_out_file, pat, unwind);
10058 handled_one = true;
10061 case REG_FRAME_RELATED_EXPR:
10062 case REG_CFA_DEF_CFA:
10063 case REG_CFA_EXPRESSION:
10064 case REG_CFA_RESTORE:
10065 case REG_CFA_SET_VDRAP:
10066 /* Not used in the ia64 port. */
10067 gcc_unreachable ();
10070 /* Not a frame-related note. */
10074 /* All REG_FRAME_RELATED_P insns, besides ALLOC, are marked with the
10075 explicit action to take. No guessing required. */
10076 gcc_assert (handled_one);
10079 /* Implement TARGET_ASM_EMIT_EXCEPT_PERSONALITY. */
10082 ia64_asm_emit_except_personality (rtx personality)
10084 fputs ("\t.personality\t", asm_out_file);
10085 output_addr_const (asm_out_file, personality);
10086 fputc ('\n', asm_out_file);
10089 /* Implement TARGET_ASM_INITIALIZE_SECTIONS. */
10092 ia64_asm_init_sections (void)
10094 exception_section = get_unnamed_section (0, output_section_asm_op,
10098 /* Implement TARGET_DEBUG_UNWIND_INFO. */
10100 static enum unwind_info_type
10101 ia64_debug_unwind_info (void)
10106 /* Implement TARGET_EXCEPT_UNWIND_INFO. */
10108 static enum unwind_info_type
10109 ia64_except_unwind_info (struct gcc_options *opts)
10111 /* Honor the --enable-sjlj-exceptions configure switch. */
10112 #ifdef CONFIG_UNWIND_EXCEPTIONS
10113 if (CONFIG_UNWIND_EXCEPTIONS)
10117 /* For simplicity elsewhere in this file, indicate that all unwind
10118 info is disabled if we're not emitting unwind tables. */
10119 if (!opts->x_flag_exceptions && !opts->x_flag_unwind_tables)
10128 IA64_BUILTIN_COPYSIGNQ,
10129 IA64_BUILTIN_FABSQ,
10130 IA64_BUILTIN_FLUSHRS,
10132 IA64_BUILTIN_HUGE_VALQ,
10136 static GTY(()) tree ia64_builtins[(int) IA64_BUILTIN_max];
10139 ia64_init_builtins (void)
10145 /* The __fpreg type. */
10146 fpreg_type = make_node (REAL_TYPE);
10147 TYPE_PRECISION (fpreg_type) = 82;
10148 layout_type (fpreg_type);
10149 (*lang_hooks.types.register_builtin_type) (fpreg_type, "__fpreg");
10151 /* The __float80 type. */
10152 float80_type = make_node (REAL_TYPE);
10153 TYPE_PRECISION (float80_type) = 80;
10154 layout_type (float80_type);
10155 (*lang_hooks.types.register_builtin_type) (float80_type, "__float80");
10157 /* The __float128 type. */
10161 tree float128_type = make_node (REAL_TYPE);
10163 TYPE_PRECISION (float128_type) = 128;
10164 layout_type (float128_type);
10165 (*lang_hooks.types.register_builtin_type) (float128_type, "__float128");
10167 /* TFmode support builtins. */
10168 ftype = build_function_type_list (float128_type, NULL_TREE);
10169 decl = add_builtin_function ("__builtin_infq", ftype,
10170 IA64_BUILTIN_INFQ, BUILT_IN_MD,
10172 ia64_builtins[IA64_BUILTIN_INFQ] = decl;
10174 decl = add_builtin_function ("__builtin_huge_valq", ftype,
10175 IA64_BUILTIN_HUGE_VALQ, BUILT_IN_MD,
10177 ia64_builtins[IA64_BUILTIN_HUGE_VALQ] = decl;
10179 ftype = build_function_type_list (float128_type,
10182 decl = add_builtin_function ("__builtin_fabsq", ftype,
10183 IA64_BUILTIN_FABSQ, BUILT_IN_MD,
10184 "__fabstf2", NULL_TREE);
10185 TREE_READONLY (decl) = 1;
10186 ia64_builtins[IA64_BUILTIN_FABSQ] = decl;
10188 ftype = build_function_type_list (float128_type,
10192 decl = add_builtin_function ("__builtin_copysignq", ftype,
10193 IA64_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
10194 "__copysigntf3", NULL_TREE);
10195 TREE_READONLY (decl) = 1;
10196 ia64_builtins[IA64_BUILTIN_COPYSIGNQ] = decl;
10199 /* Under HPUX, this is a synonym for "long double". */
10200 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
10203 /* Fwrite on VMS is non-standard. */
10204 if (TARGET_ABI_OPEN_VMS)
10206 implicit_built_in_decls[(int) BUILT_IN_FWRITE] = NULL_TREE;
10207 implicit_built_in_decls[(int) BUILT_IN_FWRITE_UNLOCKED] = NULL_TREE;
10210 #define def_builtin(name, type, code) \
10211 add_builtin_function ((name), (type), (code), BUILT_IN_MD, \
10214 decl = def_builtin ("__builtin_ia64_bsp",
10215 build_function_type_list (ptr_type_node, NULL_TREE),
10217 ia64_builtins[IA64_BUILTIN_BSP] = decl;
10219 decl = def_builtin ("__builtin_ia64_flushrs",
10220 build_function_type_list (void_type_node, NULL_TREE),
10221 IA64_BUILTIN_FLUSHRS);
10222 ia64_builtins[IA64_BUILTIN_FLUSHRS] = decl;
10228 if (built_in_decls [BUILT_IN_FINITE])
10229 set_user_assembler_name (built_in_decls [BUILT_IN_FINITE],
10231 if (built_in_decls [BUILT_IN_FINITEF])
10232 set_user_assembler_name (built_in_decls [BUILT_IN_FINITEF],
10234 if (built_in_decls [BUILT_IN_FINITEL])
10235 set_user_assembler_name (built_in_decls [BUILT_IN_FINITEL],
10241 ia64_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10242 enum machine_mode mode ATTRIBUTE_UNUSED,
10243 int ignore ATTRIBUTE_UNUSED)
10245 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10246 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10250 case IA64_BUILTIN_BSP:
10251 if (! target || ! register_operand (target, DImode))
10252 target = gen_reg_rtx (DImode);
10253 emit_insn (gen_bsp_value (target));
10254 #ifdef POINTERS_EXTEND_UNSIGNED
10255 target = convert_memory_address (ptr_mode, target);
10259 case IA64_BUILTIN_FLUSHRS:
10260 emit_insn (gen_flushrs ());
10263 case IA64_BUILTIN_INFQ:
10264 case IA64_BUILTIN_HUGE_VALQ:
10266 enum machine_mode target_mode = TYPE_MODE (TREE_TYPE (exp));
10267 REAL_VALUE_TYPE inf;
10271 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, target_mode);
10273 tmp = validize_mem (force_const_mem (target_mode, tmp));
10276 target = gen_reg_rtx (target_mode);
10278 emit_move_insn (target, tmp);
10282 case IA64_BUILTIN_FABSQ:
10283 case IA64_BUILTIN_COPYSIGNQ:
10284 return expand_call (exp, target, ignore);
10287 gcc_unreachable ();
10293 /* Return the ia64 builtin for CODE. */
10296 ia64_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
10298 if (code >= IA64_BUILTIN_max)
10299 return error_mark_node;
10301 return ia64_builtins[code];
10304 /* For the HP-UX IA64 aggregate parameters are passed stored in the
10305 most significant bits of the stack slot. */
10308 ia64_hpux_function_arg_padding (enum machine_mode mode, const_tree type)
10310 /* Exception to normal case for structures/unions/etc. */
10312 if (type && AGGREGATE_TYPE_P (type)
10313 && int_size_in_bytes (type) < UNITS_PER_WORD)
10316 /* Fall back to the default. */
10317 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
10320 /* Emit text to declare externally defined variables and functions, because
10321 the Intel assembler does not support undefined externals. */
10324 ia64_asm_output_external (FILE *file, tree decl, const char *name)
10326 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
10327 set in order to avoid putting out names that are never really
10329 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
10331 /* maybe_assemble_visibility will return 1 if the assembler
10332 visibility directive is output. */
10333 int need_visibility = ((*targetm.binds_local_p) (decl)
10334 && maybe_assemble_visibility (decl));
10336 #ifdef DO_CRTL_NAMES
10340 /* GNU as does not need anything here, but the HP linker does
10341 need something for external functions. */
10342 if ((TARGET_HPUX_LD || !TARGET_GNU_AS)
10343 && TREE_CODE (decl) == FUNCTION_DECL)
10344 (*targetm.asm_out.globalize_decl_name) (file, decl);
10345 else if (need_visibility && !TARGET_GNU_AS)
10346 (*targetm.asm_out.globalize_label) (file, name);
10350 /* Set SImode div/mod functions, init_integral_libfuncs only initializes
10351 modes of word_mode and larger. Rename the TFmode libfuncs using the
10352 HPUX conventions. __divtf3 is used for XFmode. We need to keep it for
10353 backward compatibility. */
10356 ia64_init_libfuncs (void)
10358 set_optab_libfunc (sdiv_optab, SImode, "__divsi3");
10359 set_optab_libfunc (udiv_optab, SImode, "__udivsi3");
10360 set_optab_libfunc (smod_optab, SImode, "__modsi3");
10361 set_optab_libfunc (umod_optab, SImode, "__umodsi3");
10363 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
10364 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
10365 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
10366 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
10367 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
10369 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
10370 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
10371 set_conv_libfunc (sext_optab, TFmode, XFmode, "_U_Qfcnvff_f80_to_quad");
10372 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
10373 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
10374 set_conv_libfunc (trunc_optab, XFmode, TFmode, "_U_Qfcnvff_quad_to_f80");
10376 set_conv_libfunc (sfix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_sgl");
10377 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
10378 set_conv_libfunc (sfix_optab, TImode, TFmode, "_U_Qfcnvfxt_quad_to_quad");
10379 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxut_quad_to_sgl");
10380 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxut_quad_to_dbl");
10382 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
10383 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
10384 set_conv_libfunc (sfloat_optab, TFmode, TImode, "_U_Qfcnvxf_quad_to_quad");
10385 /* HP-UX 11.23 libc does not have a function for unsigned
10386 SImode-to-TFmode conversion. */
10387 set_conv_libfunc (ufloat_optab, TFmode, DImode, "_U_Qfcnvxuf_dbl_to_quad");
10390 /* Rename all the TFmode libfuncs using the HPUX conventions. */
10393 ia64_hpux_init_libfuncs (void)
10395 ia64_init_libfuncs ();
10397 /* The HP SI millicode division and mod functions expect DI arguments.
10398 By turning them off completely we avoid using both libgcc and the
10399 non-standard millicode routines and use the HP DI millicode routines
10402 set_optab_libfunc (sdiv_optab, SImode, 0);
10403 set_optab_libfunc (udiv_optab, SImode, 0);
10404 set_optab_libfunc (smod_optab, SImode, 0);
10405 set_optab_libfunc (umod_optab, SImode, 0);
10407 set_optab_libfunc (sdiv_optab, DImode, "__milli_divI");
10408 set_optab_libfunc (udiv_optab, DImode, "__milli_divU");
10409 set_optab_libfunc (smod_optab, DImode, "__milli_remI");
10410 set_optab_libfunc (umod_optab, DImode, "__milli_remU");
10412 /* HP-UX libc has TF min/max/abs routines in it. */
10413 set_optab_libfunc (smin_optab, TFmode, "_U_Qfmin");
10414 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
10415 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
10417 /* ia64_expand_compare uses this. */
10418 cmptf_libfunc = init_one_libfunc ("_U_Qfcmp");
10420 /* These should never be used. */
10421 set_optab_libfunc (eq_optab, TFmode, 0);
10422 set_optab_libfunc (ne_optab, TFmode, 0);
10423 set_optab_libfunc (gt_optab, TFmode, 0);
10424 set_optab_libfunc (ge_optab, TFmode, 0);
10425 set_optab_libfunc (lt_optab, TFmode, 0);
10426 set_optab_libfunc (le_optab, TFmode, 0);
10429 /* Rename the division and modulus functions in VMS. */
10432 ia64_vms_init_libfuncs (void)
10434 set_optab_libfunc (sdiv_optab, SImode, "OTS$DIV_I");
10435 set_optab_libfunc (sdiv_optab, DImode, "OTS$DIV_L");
10436 set_optab_libfunc (udiv_optab, SImode, "OTS$DIV_UI");
10437 set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL");
10438 set_optab_libfunc (smod_optab, SImode, "OTS$REM_I");
10439 set_optab_libfunc (smod_optab, DImode, "OTS$REM_L");
10440 set_optab_libfunc (umod_optab, SImode, "OTS$REM_UI");
10441 set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL");
10442 abort_libfunc = init_one_libfunc ("decc$abort");
10443 memcmp_libfunc = init_one_libfunc ("decc$memcmp");
10444 #ifdef MEM_LIBFUNCS_INIT
10449 /* Rename the TFmode libfuncs available from soft-fp in glibc using
10450 the HPUX conventions. */
10453 ia64_sysv4_init_libfuncs (void)
10455 ia64_init_libfuncs ();
10457 /* These functions are not part of the HPUX TFmode interface. We
10458 use them instead of _U_Qfcmp, which doesn't work the way we
10460 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
10461 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
10462 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
10463 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
10464 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
10465 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
10467 /* We leave out _U_Qfmin, _U_Qfmax and _U_Qfabs since soft-fp in
10468 glibc doesn't have them. */
10474 ia64_soft_fp_init_libfuncs (void)
10479 ia64_vms_valid_pointer_mode (enum machine_mode mode)
10481 return (mode == SImode || mode == DImode);
10484 /* For HPUX, it is illegal to have relocations in shared segments. */
10487 ia64_hpux_reloc_rw_mask (void)
10492 /* For others, relax this so that relocations to local data goes in
10493 read-only segments, but we still cannot allow global relocations
10494 in read-only segments. */
10497 ia64_reloc_rw_mask (void)
10499 return flag_pic ? 3 : 2;
10502 /* Return the section to use for X. The only special thing we do here
10503 is to honor small data. */
10506 ia64_select_rtx_section (enum machine_mode mode, rtx x,
10507 unsigned HOST_WIDE_INT align)
10509 if (GET_MODE_SIZE (mode) > 0
10510 && GET_MODE_SIZE (mode) <= ia64_section_threshold
10511 && !TARGET_NO_SDATA)
10512 return sdata_section;
10514 return default_elf_select_rtx_section (mode, x, align);
10517 static unsigned int
10518 ia64_section_type_flags (tree decl, const char *name, int reloc)
10520 unsigned int flags = 0;
10522 if (strcmp (name, ".sdata") == 0
10523 || strncmp (name, ".sdata.", 7) == 0
10524 || strncmp (name, ".gnu.linkonce.s.", 16) == 0
10525 || strncmp (name, ".sdata2.", 8) == 0
10526 || strncmp (name, ".gnu.linkonce.s2.", 17) == 0
10527 || strcmp (name, ".sbss") == 0
10528 || strncmp (name, ".sbss.", 6) == 0
10529 || strncmp (name, ".gnu.linkonce.sb.", 17) == 0)
10530 flags = SECTION_SMALL;
10532 #if TARGET_ABI_OPEN_VMS
10533 if (decl && DECL_ATTRIBUTES (decl)
10534 && lookup_attribute ("common_object", DECL_ATTRIBUTES (decl)))
10535 flags |= SECTION_VMS_OVERLAY;
10538 flags |= default_section_type_flags (decl, name, reloc);
10542 /* Returns true if FNTYPE (a FUNCTION_TYPE or a METHOD_TYPE) returns a
10543 structure type and that the address of that type should be passed
10544 in out0, rather than in r8. */
10547 ia64_struct_retval_addr_is_first_parm_p (tree fntype)
10549 tree ret_type = TREE_TYPE (fntype);
10551 /* The Itanium C++ ABI requires that out0, rather than r8, be used
10552 as the structure return address parameter, if the return value
10553 type has a non-trivial copy constructor or destructor. It is not
10554 clear if this same convention should be used for other
10555 programming languages. Until G++ 3.4, we incorrectly used r8 for
10556 these return values. */
10557 return (abi_version_at_least (2)
10559 && TYPE_MODE (ret_type) == BLKmode
10560 && TREE_ADDRESSABLE (ret_type)
10561 && strcmp (lang_hooks.name, "GNU C++") == 0);
10564 /* Output the assembler code for a thunk function. THUNK_DECL is the
10565 declaration for the thunk function itself, FUNCTION is the decl for
10566 the target function. DELTA is an immediate constant offset to be
10567 added to THIS. If VCALL_OFFSET is nonzero, the word at
10568 *(*this + vcall_offset) should be added to THIS. */
10571 ia64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
10572 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
10575 rtx this_rtx, insn, funexp;
10576 unsigned int this_parmno;
10577 unsigned int this_regno;
10580 reload_completed = 1;
10581 epilogue_completed = 1;
10583 /* Set things up as ia64_expand_prologue might. */
10584 last_scratch_gr_reg = 15;
10586 memset (¤t_frame_info, 0, sizeof (current_frame_info));
10587 current_frame_info.spill_cfa_off = -16;
10588 current_frame_info.n_input_regs = 1;
10589 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
10591 /* Mark the end of the (empty) prologue. */
10592 emit_note (NOTE_INSN_PROLOGUE_END);
10594 /* Figure out whether "this" will be the first parameter (the
10595 typical case) or the second parameter (as happens when the
10596 virtual function returns certain class objects). */
10598 = (ia64_struct_retval_addr_is_first_parm_p (TREE_TYPE (thunk))
10600 this_regno = IN_REG (this_parmno);
10601 if (!TARGET_REG_NAMES)
10602 reg_names[this_regno] = ia64_reg_numbers[this_parmno];
10604 this_rtx = gen_rtx_REG (Pmode, this_regno);
10606 /* Apply the constant offset, if required. */
10607 delta_rtx = GEN_INT (delta);
10610 rtx tmp = gen_rtx_REG (ptr_mode, this_regno);
10611 REG_POINTER (tmp) = 1;
10612 if (delta && satisfies_constraint_I (delta_rtx))
10614 emit_insn (gen_ptr_extend_plus_imm (this_rtx, tmp, delta_rtx));
10618 emit_insn (gen_ptr_extend (this_rtx, tmp));
10622 if (!satisfies_constraint_I (delta_rtx))
10624 rtx tmp = gen_rtx_REG (Pmode, 2);
10625 emit_move_insn (tmp, delta_rtx);
10628 emit_insn (gen_adddi3 (this_rtx, this_rtx, delta_rtx));
10631 /* Apply the offset from the vtable, if required. */
10634 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
10635 rtx tmp = gen_rtx_REG (Pmode, 2);
10639 rtx t = gen_rtx_REG (ptr_mode, 2);
10640 REG_POINTER (t) = 1;
10641 emit_move_insn (t, gen_rtx_MEM (ptr_mode, this_rtx));
10642 if (satisfies_constraint_I (vcall_offset_rtx))
10644 emit_insn (gen_ptr_extend_plus_imm (tmp, t, vcall_offset_rtx));
10648 emit_insn (gen_ptr_extend (tmp, t));
10651 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
10655 if (!satisfies_constraint_J (vcall_offset_rtx))
10657 rtx tmp2 = gen_rtx_REG (Pmode, next_scratch_gr_reg ());
10658 emit_move_insn (tmp2, vcall_offset_rtx);
10659 vcall_offset_rtx = tmp2;
10661 emit_insn (gen_adddi3 (tmp, tmp, vcall_offset_rtx));
10665 emit_insn (gen_zero_extendsidi2 (tmp, gen_rtx_MEM (ptr_mode, tmp)));
10667 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
10669 emit_insn (gen_adddi3 (this_rtx, this_rtx, tmp));
10672 /* Generate a tail call to the target function. */
10673 if (! TREE_USED (function))
10675 assemble_external (function);
10676 TREE_USED (function) = 1;
10678 funexp = XEXP (DECL_RTL (function), 0);
10679 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
10680 ia64_expand_call (NULL_RTX, funexp, NULL_RTX, 1);
10681 insn = get_last_insn ();
10682 SIBLING_CALL_P (insn) = 1;
10684 /* Code generation for calls relies on splitting. */
10685 reload_completed = 1;
10686 epilogue_completed = 1;
10687 try_split (PATTERN (insn), insn, 0);
10691 /* Run just enough of rest_of_compilation to get the insns emitted.
10692 There's not really enough bulk here to make other passes such as
10693 instruction scheduling worth while. Note that use_thunk calls
10694 assemble_start_function and assemble_end_function. */
10696 insn_locators_alloc ();
10697 emit_all_insn_group_barriers (NULL);
10698 insn = get_insns ();
10699 shorten_branches (insn);
10700 final_start_function (insn, file, 1);
10701 final (insn, file, 1);
10702 final_end_function ();
10704 reload_completed = 0;
10705 epilogue_completed = 0;
10708 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
10711 ia64_struct_value_rtx (tree fntype,
10712 int incoming ATTRIBUTE_UNUSED)
10714 if (TARGET_ABI_OPEN_VMS ||
10715 (fntype && ia64_struct_retval_addr_is_first_parm_p (fntype)))
10717 return gen_rtx_REG (Pmode, GR_REG (8));
10721 ia64_scalar_mode_supported_p (enum machine_mode mode)
10747 ia64_vector_mode_supported_p (enum machine_mode mode)
10764 /* Implement the FUNCTION_PROFILER macro. */
10767 ia64_output_function_profiler (FILE *file, int labelno)
10769 bool indirect_call;
10771 /* If the function needs a static chain and the static chain
10772 register is r15, we use an indirect call so as to bypass
10773 the PLT stub in case the executable is dynamically linked,
10774 because the stub clobbers r15 as per 5.3.6 of the psABI.
10775 We don't need to do that in non canonical PIC mode. */
10777 if (cfun->static_chain_decl && !TARGET_NO_PIC && !TARGET_AUTO_PIC)
10779 gcc_assert (STATIC_CHAIN_REGNUM == 15);
10780 indirect_call = true;
10783 indirect_call = false;
10786 fputs ("\t.prologue 4, r40\n", file);
10788 fputs ("\t.prologue\n\t.save ar.pfs, r40\n", file);
10789 fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", file);
10791 if (NO_PROFILE_COUNTERS)
10792 fputs ("\tmov out3 = r0\n", file);
10796 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
10798 if (TARGET_AUTO_PIC)
10799 fputs ("\tmovl out3 = @gprel(", file);
10801 fputs ("\taddl out3 = @ltoff(", file);
10802 assemble_name (file, buf);
10803 if (TARGET_AUTO_PIC)
10804 fputs (")\n", file);
10806 fputs ("), r1\n", file);
10810 fputs ("\taddl r14 = @ltoff(@fptr(_mcount)), r1\n", file);
10811 fputs ("\t;;\n", file);
10813 fputs ("\t.save rp, r42\n", file);
10814 fputs ("\tmov out2 = b0\n", file);
10816 fputs ("\tld8 r14 = [r14]\n\t;;\n", file);
10817 fputs ("\t.body\n", file);
10818 fputs ("\tmov out1 = r1\n", file);
10821 fputs ("\tld8 r16 = [r14], 8\n\t;;\n", file);
10822 fputs ("\tmov b6 = r16\n", file);
10823 fputs ("\tld8 r1 = [r14]\n", file);
10824 fputs ("\tbr.call.sptk.many b0 = b6\n\t;;\n", file);
10827 fputs ("\tbr.call.sptk.many b0 = _mcount\n\t;;\n", file);
10830 static GTY(()) rtx mcount_func_rtx;
10832 gen_mcount_func_rtx (void)
10834 if (!mcount_func_rtx)
10835 mcount_func_rtx = init_one_libfunc ("_mcount");
10836 return mcount_func_rtx;
10840 ia64_profile_hook (int labelno)
10844 if (NO_PROFILE_COUNTERS)
10845 label = const0_rtx;
10849 const char *label_name;
10850 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
10851 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
10852 label = gen_rtx_SYMBOL_REF (Pmode, label_name);
10853 SYMBOL_REF_FLAGS (label) = SYMBOL_FLAG_LOCAL;
10855 ip = gen_reg_rtx (Pmode);
10856 emit_insn (gen_ip_value (ip));
10857 emit_library_call (gen_mcount_func_rtx (), LCT_NORMAL,
10859 gen_rtx_REG (Pmode, BR_REG (0)), Pmode,
10864 /* Return the mangling of TYPE if it is an extended fundamental type. */
10866 static const char *
10867 ia64_mangle_type (const_tree type)
10869 type = TYPE_MAIN_VARIANT (type);
10871 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
10872 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
10875 /* On HP-UX, "long double" is mangled as "e" so __float128 is
10877 if (!TARGET_HPUX && TYPE_MODE (type) == TFmode)
10879 /* On HP-UX, "e" is not available as a mangling of __float80 so use
10880 an extended mangling. Elsewhere, "e" is available since long
10881 double is 80 bits. */
10882 if (TYPE_MODE (type) == XFmode)
10883 return TARGET_HPUX ? "u9__float80" : "e";
10884 if (TYPE_MODE (type) == RFmode)
10885 return "u7__fpreg";
10889 /* Return the diagnostic message string if conversion from FROMTYPE to
10890 TOTYPE is not allowed, NULL otherwise. */
10891 static const char *
10892 ia64_invalid_conversion (const_tree fromtype, const_tree totype)
10894 /* Reject nontrivial conversion to or from __fpreg. */
10895 if (TYPE_MODE (fromtype) == RFmode
10896 && TYPE_MODE (totype) != RFmode
10897 && TYPE_MODE (totype) != VOIDmode)
10898 return N_("invalid conversion from %<__fpreg%>");
10899 if (TYPE_MODE (totype) == RFmode
10900 && TYPE_MODE (fromtype) != RFmode)
10901 return N_("invalid conversion to %<__fpreg%>");
10905 /* Return the diagnostic message string if the unary operation OP is
10906 not permitted on TYPE, NULL otherwise. */
10907 static const char *
10908 ia64_invalid_unary_op (int op, const_tree type)
10910 /* Reject operations on __fpreg other than unary + or &. */
10911 if (TYPE_MODE (type) == RFmode
10912 && op != CONVERT_EXPR
10913 && op != ADDR_EXPR)
10914 return N_("invalid operation on %<__fpreg%>");
10918 /* Return the diagnostic message string if the binary operation OP is
10919 not permitted on TYPE1 and TYPE2, NULL otherwise. */
10920 static const char *
10921 ia64_invalid_binary_op (int op ATTRIBUTE_UNUSED, const_tree type1, const_tree type2)
10923 /* Reject operations on __fpreg. */
10924 if (TYPE_MODE (type1) == RFmode || TYPE_MODE (type2) == RFmode)
10925 return N_("invalid operation on %<__fpreg%>");
10929 /* Implement TARGET_OPTION_DEFAULT_PARAMS. */
10931 ia64_option_default_params (void)
10933 /* Let the scheduler form additional regions. */
10934 set_default_param_value (PARAM_MAX_SCHED_EXTEND_REGIONS_ITERS, 2);
10936 /* Set the default values for cache-related parameters. */
10937 set_default_param_value (PARAM_SIMULTANEOUS_PREFETCHES, 6);
10938 set_default_param_value (PARAM_L1_CACHE_LINE_SIZE, 32);
10940 set_default_param_value (PARAM_SCHED_MEM_TRUE_DEP_COST, 4);
10943 /* HP-UX version_id attribute.
10944 For object foo, if the version_id is set to 1234 put out an alias
10945 of '.alias foo "foo{1234}" We can't use "foo{1234}" in anything
10946 other than an alias statement because it is an illegal symbol name. */
10949 ia64_handle_version_id_attribute (tree *node ATTRIBUTE_UNUSED,
10950 tree name ATTRIBUTE_UNUSED,
10952 int flags ATTRIBUTE_UNUSED,
10953 bool *no_add_attrs)
10955 tree arg = TREE_VALUE (args);
10957 if (TREE_CODE (arg) != STRING_CST)
10959 error("version attribute is not a string");
10960 *no_add_attrs = true;
10966 /* Target hook for c_mode_for_suffix. */
10968 static enum machine_mode
10969 ia64_c_mode_for_suffix (char suffix)
10979 static enum machine_mode
10980 ia64_promote_function_mode (const_tree type,
10981 enum machine_mode mode,
10983 const_tree funtype,
10986 /* Special processing required for OpenVMS ... */
10988 if (!TARGET_ABI_OPEN_VMS)
10989 return default_promote_function_mode(type, mode, punsignedp, funtype,
10992 /* HP OpenVMS Calling Standard dated June, 2004, that describes
10993 HP OpenVMS I64 Version 8.2EFT,
10994 chapter 4 "OpenVMS I64 Conventions"
10995 section 4.7 "Procedure Linkage"
10996 subsection 4.7.5.2, "Normal Register Parameters"
10998 "Unsigned integral (except unsigned 32-bit), set, and VAX floating-point
10999 values passed in registers are zero-filled; signed integral values as
11000 well as unsigned 32-bit integral values are sign-extended to 64 bits.
11001 For all other types passed in the general registers, unused bits are
11004 if (for_return != 2
11005 && GET_MODE_CLASS (mode) == MODE_INT
11006 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
11008 if (mode == SImode)
11013 return promote_mode (type, mode, punsignedp);
11016 static GTY(()) rtx ia64_dconst_0_5_rtx;
11019 ia64_dconst_0_5 (void)
11021 if (! ia64_dconst_0_5_rtx)
11023 REAL_VALUE_TYPE rv;
11024 real_from_string (&rv, "0.5");
11025 ia64_dconst_0_5_rtx = const_double_from_real_value (rv, DFmode);
11027 return ia64_dconst_0_5_rtx;
11030 static GTY(()) rtx ia64_dconst_0_375_rtx;
11033 ia64_dconst_0_375 (void)
11035 if (! ia64_dconst_0_375_rtx)
11037 REAL_VALUE_TYPE rv;
11038 real_from_string (&rv, "0.375");
11039 ia64_dconst_0_375_rtx = const_double_from_real_value (rv, DFmode);
11041 return ia64_dconst_0_375_rtx;
11044 static enum machine_mode
11045 ia64_get_reg_raw_mode (int regno)
11047 if (FR_REGNO_P (regno))
11049 return default_get_reg_raw_mode(regno);
11052 /* Always default to .text section until HP-UX linker is fixed. */
11054 ATTRIBUTE_UNUSED static section *
11055 ia64_hpux_function_section (tree decl ATTRIBUTE_UNUSED,
11056 enum node_frequency freq ATTRIBUTE_UNUSED,
11057 bool startup ATTRIBUTE_UNUSED,
11058 bool exit ATTRIBUTE_UNUSED)
11063 #include "gt-ia64.h"